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Model and configure MDSS Display Port PLL for SDM660 target.
Add changes to define and register DP VCO, divider and mux clocks
as per common clock infrastructure.
Change-Id: Ice83e21323087e81e2f30998260be85120e41fa8
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
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Model and configure MDSS DSI PLL using upstream clock framework
APIs. Add changes to define and register vco, divider, mux clcoks
as per common clock infrastructure.
Change-Id: Idc51070e2bb36d1a757d2714d2875a99901321a7
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
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Porting msm8996 related display clocks/PLL from drivers/clk/msm
to drivers/clk/qcom (upstream version).
Change-Id: I7a4ab0be9e70f25817edadfc2eab4f7adf4435ee
Signed-off-by: Shalini Krishnamoorthi <shakri@codeaurora.org>
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