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Avoid the release of memory for dynamic fps PLL codes. The memory
is part of the continuous splash memory region and will be freed
eventually as part of the splash screen memory cleanup routine.
Change-Id: I67afb46057770298668ae5790637e8b4b08fd030
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
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Add CLK_SET_RATE_NO_REPARENT flag for the software mux clocks in
DSI 14nm PLL driver which is needed for dynamic refresh feature.
Update the dynamic fps structure to align the PLL codes with
vco frequency instead of fps.
Change-Id: I533f615ce51be7229171b6accac3f14ab2dca949
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
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Changes to update DSI PLL settings as per latest recommendation.
Change-Id: Ie864ced700f21b6a94afb9de2d2c55f6ef9c7bd5
Signed-off-by: Rashi Bindra <rbindra@codeaurora.org>
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Add support for DP PLL driver to bring up display port
on sdm630.
Change-Id: I075581be3c69841a7eb3909b28d5214728717f68
Signed-off-by: Narender Ankam <nankam@codeaurora.org>
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Add the sdm630 compatible string to MDSS PLL driver
of_device_id table list, so that initialization of
MDSS PLL driver takes place for sdm630 platform.
Change-Id: I284ff9c07a4a971260ade399a2f7a605003ccf1d
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
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The fractional divider values for DP pixel clock RCG needs to be
determined dynamically. Add the recalc_rate operation for the DP
PLL mux clock dp_vco_divided_clk_src_mux which is the parent of
DP pixel clock RCG. This enables the RCG clock to calculate the
fractional dividers correctly. Modify the determine rate op for the
mux clock to also set the new parent after performing the determine
rate operation.
Change-Id: Id931a60677380ecee28eb9aec6468548898b812b
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
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Model and configure MDSS Display Port PLL for SDM660 target.
Add changes to define and register DP VCO, divider and mux clocks
as per common clock infrastructure.
Change-Id: Ice83e21323087e81e2f30998260be85120e41fa8
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
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Update the code name from msmfalcon/apqfalcon to sdm660/sda660.
As part of this, update the filename containing "falcon" and
files content containing "falcon".
Change-Id: Iec85862251b9e1b4dcc8bdce8b214ce87c0049bc
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
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Add the msmfalcon compatible string to MDSS PLL driver dt
table list so that MDSS PLL driver initialization takes place
for msmflacon platform.
Change-Id: I806456737485dfcbca8a71d59db0927bbd843708
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
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Model and configure MDSS DSI PLL using upstream clock framework
APIs. Add changes to define and register vco, divider, mux clcoks
as per common clock infrastructure.
Change-Id: Idc51070e2bb36d1a757d2714d2875a99901321a7
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
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Update the code name from msmcobalt to msm8998. As a result, update
the filename containing "cobalt" and files content containing "cobalt".
CRs-Fixed: 1070840
Change-Id: I2c7b95e3e2a2fec7730724da9eeb86a39a77faf1
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
Signed-off-by: Kyle Yan <kyan@codeaurora.org>
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
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Porting msm8996 related display clocks/PLL from drivers/clk/msm
to drivers/clk/qcom (upstream version).
Change-Id: I7a4ab0be9e70f25817edadfc2eab4f7adf4435ee
Signed-off-by: Shalini Krishnamoorthi <shakri@codeaurora.org>
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