| Commit message (Collapse) | Author | Age |
| |
|
|
|
|
|
|
|
| |
This reverts commit 5344e5c78f5820dfa34cfcea4572d8e347a018ce.
The change negatively impacted performance.
CRs-Fixed: 2120475
Change-Id: Ib6ff329a3501e77d990c2e9502ed35e041f730c8
Signed-off-by: Kyle Piefer <kpiefer@codeaurora.org>
|
| |
|
|
|
|
|
|
|
|
| |
Change data type for gpu ib vote to unsigned
long to suit the bw vote data type in devfreq
governor functions.
Change-Id: I6aeb201ee67d111ee527c17e051b5125968a9683
Signed-off-by: Archana Sriram <apsrir@codeaurora.org>
Signed-off-by: Pranav Patel <pranavp@codeaurora.org>
|
| |
|
|
|
|
|
|
| |
GPU should not be forced to SUSPEND state when it is in INIT
or NONE state as this transition is invalid.
Change-Id: Ia3d0fd131348508fe34c57f271c1f991a98afa19
Signed-off-by: Archana Sriram <apsrir@codeaurora.org>
|
| |
|
|
|
|
|
|
|
| |
Invoke kgsl_suspend and kgsl_resume during hibernation
of KGSL.
Change-Id: I8e1a8ad8b9293d568950a9e71667d1088ff6fbba
Signed-off-by: Suprith Malligere Shankaregowda <supgow@codeaurora.org>
Signed-off-by: Thomas (Wonyoung) Yun <wyun@codeaurora.org>
|
| |
|
|
|
|
|
|
| |
This patch ensures device resumes successfully after
XO shutdown without any KGSL error.
Change-Id: I9eb8e281bc62793dc7521ba72aaeecf946860851
Signed-off-by: Suprith Malligere Shankaregowda <supgow@codeaurora.org>
|
| |
|
|
|
|
|
|
|
|
| |
rbbmtimer_clk hardwired fixed XO frequency 19.2Mhz. clock_round_rate()
for RBBM timer clock fails with -EPERM as it is fixed. So added a
check to make sure that rbbmtimer_clk clk_set_rate() has valid
frequency. This avoids warning message in the driver log.
Change-Id: I8f8bcec88e6a39e1550bb67590e6b66dba8e7a27
Signed-off-by: Archana Obannagari <aobann@codeaurora.org>
|
| |
|
|
|
|
|
|
|
| |
Before calling kgsl_pwrctrl_clk_set_rate(), make sure the
RBBM timer clock is available. This avoids warning messages
in the driver log.
Change-Id: I0cd21b7253c802e8522d570056c8aeda02729267
Signed-off-by: Archana Obannagari <aobann@codeaurora.org>
|
| |
|
|
|
|
|
|
|
|
| |
Add a PM QOS request to disallow L2PC during wake up
from SLUMBER state. This is required to improve queue
to submit time for first set of GPU commands which results
in GPU wake up.
Change-Id: Iad1a6dfdf9e1fe034eef4fae526138d724bdd3eb
Signed-off-by: Gaurav Sonwani <gsonwani@codeaurora.org>
|
| |\ |
|
| | |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
The debug option to always ON the GPU clocks does not check the regulator
state. If the user tries to set this option while GPU is in Slumber state
then enabling clocks will fail.
Make sure we enable the GPU regulators before enabling its clocks.
Change-Id: Id77773224c674fe2e1b6179a039750b24e5e5f87
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
|
| |/
|
|
|
|
|
|
| |
KGSL power limit pointer can be error or NULL. Add a NULL
check for limit pointer to avoid NULL pointer dereference.
Change-Id: I4aacaddd1cd9b34f1befc21807eb7ab577f0a7f1
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
|
| |\ |
|
| | |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Currently submit ioctl getting blocked till the commands
gets added to ringbuffer incase inflight count is less
than context burst count. If the submit command happens
in GPU slumber state, it will add the GPU wakeup time to
submit IOCTL. This will add latency in preparing next frame
in CPU side. Defer commands submission to dispatcher worker,
if the GPU is in slumber state.
CRs-Fixed: 2055107
Change-Id: I099ba721e02bbcd8ccadb1bc518c7c1ef4fb7e21
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
|
| |/
|
|
|
|
|
|
| |
Handle the clk API return value so that it’s easy
to catch un clocked GPU register access.
Change-Id: I5a1a9a6cbd673394f126bb17b849393268a22b1b
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
|
| |\ |
|
| | |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
For dual channel DDR, IB vote from client is half of actual
IB vote as IB vote calculation on client side doesn't consider
number of DDR channels. ICB driver takes care of multiplying
the client IB vote with number of DDR channels.
This change removes the AB capping check to avoid the scenarios
where AB vote > actual IB vote/2 but gets capped to actual
IB vote/2 because client side IB vote is half of actual IB vote.
Removal of this check will not impact single channel DDR targets
because of the way AB value is calculated. In case of honest BW
voting, AB will always be less than IB as AB calculation doesn't
consider RAM wait value. In case of unhonest vote, AB value is
always caluclated as some percentage of IB vote and this percentage
value is always <=100%.
Change-Id: Icdca6118f6605665979a1bead35ba3ef631d50e8
Signed-off-by: Deepak Kumar <dkumar@codeaurora.org>
|
| |/
|
|
|
|
|
|
|
| |
Memory retention is needed only for NAP state but not for SLUMBER state.
Disables memory retention for core clock before entering SLUMBER to save
power.
Change-Id: I64a5ecec6fc90d662da8d9d793860e56b0c6473f
Signed-off-by: Deepak Kumar <dkumar@codeaurora.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
Following changes been made to improve soft fault detection,
which will fix un clocked register access in dispatcher_do_fault()
and incorrect declaration of GPU soft fault.
i) Stop fault timer before entering to NAP state
ii) Don’t start fault timer if the dispatcher inflight count is zero
iii) Add ringbuffer empty check in _isidle()
iv) Add device state check in dispatcher_do_fault()
CRs-Fixed: 2012731
Change-Id: I5ce498029f389eeeb428b4ac7fb07afd84d5764c
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
| |
To handle Cx peak current limit on SDM660, GPU needs
to call Cx ipeak driver APIs when it switches between
threshold points.
Cx ipeak driver will throttle cDSP frequency if all
the clients are running at their respective threshold
frequencies to limit Cx peak current.
Change-Id: I5ffcf1a42523072d2b8b7bc0022eb3cc067acbb9
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
|
| |
|
|
|
|
|
|
|
| |
If power-related initialization fails during device probe, clean up
the kgsl structure members. This is useful if the device probe is
retried later.
Change-Id: I75aeb199da685bb5055ba5a8a0bb552656951674
Signed-off-by: Lynus Vaz <lvaz@codeaurora.org>
|
| |
|
|
|
|
|
|
|
|
|
|
| |
Currently we sample power stats at the expiry of
cmdbatch. In cases where cmdbatch takes a long time
to finish the job, it delays power stats sampling,
in effect it delays DCVS decision for changing the
frequency. Do a midframe power stats sampling and
feed it to DCVS if it is enabled.
Change-Id: I547d792b38649aa1d60525b0dc335791b37989fd
Signed-off-by: Prakash Kamliya <pkamliya@codeaurora.org>
|
| |
|
|
|
|
|
|
| |
Add a sysfs entry to enable control of notifications
from pwrscale to devfreq.
Change-Id: Ife0a31e96975239bf4fefd59ac6266568c4db1a5
Signed-off-by: Jonathan Wicks <jwicks@codeaurora.org>
|
| |\ |
|
| | |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Add new sysfs nodes which satisfy a generic format requested
by customer. Also add a new node to track GPU temperature.
Create links to these nodes at a generic location:
/sys/kernel/gpu/
CRs-Fixed: 1064728
Change-Id: I414a07ff4f9ee14b8f882d15644b06a73d5fcf76
Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
|
| |/
|
|
|
|
|
|
|
|
|
| |
Reschedule the idle work in case transition to idle state is rejected
because the GPU is busy. This change avoids the condition where
transition to NAP state gets rejected due to a pending IRQ which is
currently getting served by IRQ handler because of which GPU remains
in active state even when GPU is idle.
Change-Id: I472a30b6a0e83cdd6957ed12eaa39d0c7731fcb5
Signed-off-by: Deepak Kumar <dkumar@codeaurora.org>
|
| |
|
|
|
|
|
|
|
| |
Call clk_set_flag() to turn off both memory core and periphery for
bimc_gfx_clk clock and memory for gfx_3d.
CRs-Fixed: 1046649
Change-Id: I941f91eeba01f4e7aa5427056bc57875e7edf197
Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
|
| |
|
|
|
|
|
|
|
|
| |
DEEP-NAP and SLEEP states are not used in targets of previous
two generations. They are neither saving GPU power, nor saving
system power. Remove to reduce maintenance overhead.
CRs-Fixed: 1053516
Change-Id: If2fc2701548f90bb7ea9559a87752e13a7b0f736
Signed-off-by: George Shen <sqiao@codeaurora.org>
|
| |
|
|
|
|
|
|
|
|
|
| |
GFX retention mode does not save GFX rail power. The feature
increased MX rail power. Fixing the problem requires more overhead
than removing it. The feature has never been enabled in any targets.
So remove the feature.
CRs-Fixed: 1053516
Change-Id: I5f118138eca307f7cc16405ff9c8897ecd510c12
Signed-off-by: George Shen <sqiao@codeaurora.org>
|
| |\ |
|
| | |
| |
| |
| |
| |
| |
| |
| |
| | |
In case of GPU idle (NAP), schedule DCVS call to obtain updated
GPU load for correct GPU frequency scaling.
Change-Id: Ifcf05ffde0a054839e51d3f8173b8449fe177aa0
CRs-Fixed: 1050000
Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
|
| |/
|
|
|
|
|
|
|
|
|
|
|
|
| |
Tracks GPU active time per frequency for GPU workload
profiling. The data will be output in
/sys/class/kgsl/kgsl-3d0/gpu_clock_stats
with one u64 value in microseconds per clock level.
For example:
cat /sys/class/kgsl/kgsl-3d0/gpu_clock_stats
39392 29292 929292 929292 4040404
CRs-Fixed: 1011462
Change-Id: I5f2caa8b38d99ffd23f03c1dfed1efda273fc2fb
Signed-off-by: George Shen <sqiao@codeaurora.org>
|
| |
|
|
|
|
|
|
|
|
|
| |
It is no longer power efficient to independently enable and disable
the MMU clocks. We can safely enable and disable them with the rest
of the GPU clocks and take back the infrastructure needed to handle
the clocks.
CRs-Fixed: 1009124
Change-Id: Ic0dedbadc48095eada9c5fce6004475a2cb0f0a9
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
|
| |\ |
|
| | |
| |
| |
| |
| |
| |
| |
| |
| | |
GPMU & CRC perform more effective idle clock control
than software clock gating.
CRs-Fixed: 973565
Change-Id: Ifd45878a65b7da4167d2caa30b3acffd427ad72e
Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
|
| |/
|
|
|
|
|
|
|
| |
By disabling isense clock below nominal level we'll remove
vote for CX rail and save power.
CRs-Fixed: 973565
Change-Id: If4a13b3eca117fc2ff9c32ca3a24eb8b8e70b4fe
Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
|
| |
|
|
|
|
|
|
| |
GPU will vote off gcc_gpu_iref_clk when going to low power modes.
CRs-Fixed: 1024948
Change-Id: I13b7a70f1fa748f2f4cdfb485dda2f7857e0b3d2
Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
|
| |
|
|
|
|
|
|
| |
Deep nap timer value was not calculated right when read from dts file.
CRs-Fixed: 973565
Change-Id: I11a70c61d408921edd89b1417b209c5c5a3ddf24
Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
|
| |
|
|
|
|
|
|
|
| |
Create sysfs entry to have option to disable software clockgating
NAP state.
CRs-Fixed: 973565
Change-Id: I2376f10161040dbf426887ce146ac597f401153f
Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
|
| |
|
|
|
|
|
|
| |
Port GPU dcvs from kernel 3.18 to kernel 4.4.
CRs-Fixed: 1013343
Change-Id: Ide662b12aa59effa541febcd758426e72b4a1b12
Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
|
| |
|
|
|
|
|
|
|
| |
Remove unused #defines, structs and members that are no longer used.
CRs-Fixed: 971156
Change-Id: Ibdf6fef6f3f700f3c5315c228c0473e47fb62163
Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
|
| |
|
|
|
|
|
|
| |
On A540 ISENSE clock rate is controlled by GPU driver.
CRs-Fixed: 973565
Change-Id: Iab40cff01b6e65db51a4b793572714d2059a78ad
Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
|
| |
|
|
|
|
|
|
|
| |
Add a l2pc-cpu-mask-latency in device tree. This latency
is used in kgsl_pwrctrl_update_l2pc() API to avoid L2PC
on masked CPUs by giving reduced latency value.
Change-Id: I0447977bce5ed5c09a863b03bb42b9428686a9f5
Signed-off-by: Divya Ponnusamy <pdivya@codeaurora.org>
|
| |
|
|
|
|
|
|
|
| |
Add new clocks for MSMCOBALT.
CRs-Fixed: 973565
Change-Id: I579875f34cff0ff9b714c0378084826aee0f893c
Signed-off-by: George Shen <sqiao@codeaurora.org>
Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Enable direct programming of GPU-BIMC interface clocks
from kernel driver when moving in and out of TURBO.
This is done only for targets with a device tree
entry defined for GPU-BIMC interface.
This is done because some targets do not support
B/W requirement of GPU at TURBO, for such targets
we need to program the GPU-BIMC interface clocks
with TURBO values to meet the B/W goals.
Change-Id: Ibe82db8718040513ae0d96366195d41001549189
Signed-off-by: Sunil Khatri <sunilkh@codeaurora.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
If any of the Graphics rendering threads are running
on masked CPUs, avoid L2PC for some duration on that
CPU. This reduces latency on CPU (latency mainly
because of L2 cache flush) and helps on performance.
This change uses pm_qos_update_request_timeout() API.
Add l2pc-cpu-mask property in device tree to enable
this.
CRs-Fixed: 962598
Change-Id: If90090cd2c68ea7c07e269723931fef7201ef136
Signed-off-by: Prakash Kamliya <pkamliya@codeaurora.org>
|
| |
|
|
|
|
|
|
| |
Make the various timeout values HZ agnostic by using the proper
macros and values instead.
Change-Id: I708cd491f593782f0172cd7d2cca058cd41044a5
Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
|
| |
|
|
|
|
|
|
| |
Add ISENSE based limit management, provide interfaces to GPMU
and hardware LLM and BCL subsystems.
Change-Id: Ic0419509bdc6d4d9d478277cc90ae75dc527ca66
Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
|
| |
|
|
|
|
|
|
|
| |
Deep nap removes the quality of service latency vote. Restore device
before powering back the GPU while coming out of deep nap.
Change-Id: I9366ffa6f5f2768cb3ea10f9117678ba8cf8d190
Signed-off-by: Prakash Kamliya <pkamliya@codeaurora.org>
Signed-off-by: Divya Ponnusamy <pdivya@codeaurora.org>
|
| |
|
|
|
|
|
| |
Wrap the code to use the bwmon governor or not depending if it
exists.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
|
|
|
Snapshot of the Qualcom Adreno GPU driver (KGSL) as of msm-3.18 commit
commit e70ad0cd5efd ("Promotion of kernel.lnx.3.18-151201.").
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
|