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* | Merge "clk: qcom: Add support to register rpm-smd clocks"Linux Build Service Account2016-09-30
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| * | clk: qcom: Add support to register rpm-smd clocksAmit Nischal2016-09-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update the rpm-smd communication API to send across votes for clock enable/disable to RPM. Use the clk_hw list for the RPM clocks and also update the clock ids and clock names for RPM clocks. Change-Id: I37ae97f22b1b39d040bb78c90b1ff231bc348fe6 Signed-off-by: Amit Nischal <anischal@codeaurora.org>
* | | clk: qcom: Add support for GCC clock for MSMFalconTaniya Das2016-09-29
|/ / | | | | | | | | | | | | | | | | Add support for the global clock controller found on MSMFalcon based devices. This should allow most clocks for peripherals other than multimedia clocks. Change-Id: I1ec6309f32c658177580cc0601083d32bcdfad20 Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | Merge "msm: msm_bus: introduce bus topology for msmfalcon"Linux Build Service Account2016-09-20
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| * | msm: msm_bus: add new master/slave idsKiran Gunda2016-09-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce new master/slave ids to identify the corresponding master/slaves for the bandwidth aggregation done by the bus driver. Change-Id: Ibed309284b47ba3f22ccbac45c750f3e366ec40e Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
* | | Merge "clk: qcom: Clean up the MSM8996 Global Clock Control (GCC) driver"Linux Build Service Account2016-09-13
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| * | clk: qcom: Clean up the MSM8996 Global Clock Control (GCC) driverOdelu Kukatla2016-09-11
| | | | | | | | | | | | | | | | | | | | | | | | Remove the RPM controlled clocks and add missing clocks. Also clean up clock flags and parent info for few clocks. Change-Id: I7ae55f992be29a28617070ca7792f912592c3628 Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
* | | Merge "clk: msm: gcc-cobalt: Add support for gcc_aggre1_ufs_axi_hw_ctl_clk"Linux Build Service Account2016-09-12
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| * | | clk: msm: gcc-cobalt: Add support for gcc_aggre1_ufs_axi_hw_ctl_clkDevesh Jhunjhunwala2016-08-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for controlling the hw_ctl bit of the gcc_aggre1_ufs_axi_clk CBCR. Change-Id: I856f2c76c3149f3704c47e6f8b0019805a1a0cd4 Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
* | | | Merge "pinctrl: qcom: spmi-gpio: Add dtest route for digital input"Linux Build Service Account2016-09-11
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| * | | | pinctrl: qcom: spmi-gpio: Add dtest route for digital inputFenglin Wu2016-09-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add property "qcom,dtest-buffer" to specify which dtest rail to feed when the pin is configured as a digital input. Change-Id: I05b253147677ca66d926eaeaa680bd09e31247a5 Signed-off-by: Fenglin Wu <fenglinw@codeaurora.org>
* | | | | Merge "pinctrl: qcom: spmi-gpio: Add support for GPIO LV/MV subtype"Linux Build Service Account2016-09-11
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| * | | pinctrl: qcom: spmi-gpio: Add support for GPIO LV/MV subtypeFenglin Wu2016-09-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIO LV (low voltage)/MV (medium voltage) subtypes have different features and register mappings than 4CH/8CH subtypes. Add support for LV and MV subtypes. Change-Id: I7bcf4347adce6ba9892d2e57a413d407d35fbc26 Signed-off-by: Fenglin Wu <fenglinw@codeaurora.org>
* | | | Merge "clk: msm: clock-osm: Add measurement support for CPU clocks"Linux Build Service Account2016-09-09
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| * | | | clk: msm: clock-osm: Add measurement support for CPU clocksDeepak Katragadda2016-09-07
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to measure the perf and power cluster clocks via the debug mux on MSMCOBALT. CRs-Fixed: 1059153 Change-Id: I1682481dfe22deef300ea9bd1db558ae634c9129 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | | | Merge "clk: msm: Add support for block reset clocks for msmcobalt"Linux Build Service Account2016-09-02
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| * | | clk: msm: Add support for block reset clocks for msmcobaltTaniya Das2016-08-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the block reset clocks which will be used by clients to assert/deassert these clocks using the reset controller framework. Change-Id: I19f4f6e764ffde26ecf3b7cce3fb53a9bf2cc91a Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | | | Merge "clk: msm: gcc-cobalt: Remove support for wcss clocks"Linux Build Service Account2016-08-26
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| * | | | clk: msm: gcc-cobalt: Remove support for wcss clocksDevesh Jhunjhunwala2016-08-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The wcss clocks are not owned by APCS, and thus should not be modelled in the clock driver. CRs-Fixed: 1054449 Change-Id: I7677bef6a58c028876b72dbade37c1064b428ee2 Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
* | | | | Merge "clk: msm: mdss: update Dp PLL/Phy configuration"Linux Build Service Account2016-08-26
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| * | | | | clk: msm: mdss: update Dp PLL/Phy configurationChandan Uddaraju2016-08-22
| | |_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the Display-Port PHY and PLL configuration with the recommended settings. Remove the support for 9.72Ghz VCO frequency. Update the divider settings to support the new frequency plan. Update the Phy Aux settings and voltage/pre-emphasis settings according to recommended configuration. Change-Id: Ic4d206da3dc6b45214e7601e7556cfb0bef81a7d Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
* / | | | clk: msm: clock: Add voter clocks for mmss_camss_jpeg0_clkDeepak Katragadda2016-08-22
|/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add separate voter clocks for controlling the mmss_camss_jpeg0_clk from two clients on MSMCOBALT. CRs-Fixed: 1049594 Change-Id: I530e35054fd512574bca9e5937317099f58d2bb6 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | | | Merge "clk: msm: clock: Control the GPLL0 input sources to MMSSCC and GPUCC"Linux Build Service Account2016-08-19
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| * | | | clk: msm: clock: Control the GPLL0 input sources to MMSSCC and GPUCCDeepak Katragadda2016-08-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPLL0 input to the multimedia and graphics clock controllers can be managed by use of voting registers. Enable this usage and turn off the inputs when no clocks within these clock controllers need a GPLL0/GPLL0 divider input. CRs-Fixed: 1009689 Change-Id: Iea17649eb63522510cf7887a630d17a2f64a615b Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | | | | Merge "clk: msm: clock: Update clock frequencies on MSMCOBALT"Linux Build Service Account2016-08-16
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| * | | | clk: msm: clock: Update clock frequencies on MSMCOBALTDeepak Katragadda2016-08-10
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the graphics and multimedia clock frequencies and FMAXes to align with the v2 and vq frequency plans. While doing so, remove support for the gpu_pll1 PLL since it is not going to be used to generate any frequencies. CRs-Fixed: 1051170 Change-Id: I4d6547d95bd76d8ca6f4d729009d8b4a78716d5b Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | / / clock: qcom: Update the list of clocks supported on MSMFalconTaniya Das2016-08-12
| |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the new clocks and update the clock ids for GCC, GPU, MMSS clock controllers. Also add the RPM clocks which are supported and would be used by the clients for all clock operations for RPM controlled clocks. There are separate MMSS and GPU clock controllers, so add the dummy controllers for the same. Change-Id: I5a98b6128f5d54163ab5d03c4c023a748e6a4e95 Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | | clk: msm: Add support for block reset clocksTaniya Das2016-08-08
|/ / | | | | | | | | | | | | | | Add the block reset clocks which will be used by clients to assert/deassert these clocks using the reset controller framework. Change-Id: I3e9f7f85bf1faf0e1bb501196ba9d7e197111a03 Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | Merge "clk: msm: clock: Remove support for the USB cfg_ahb2phy clock from HLOS"Linux Build Service Account2016-07-27
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| * | clk: msm: clock: Remove support for the USB cfg_ahb2phy clock from HLOSDeepak Katragadda2016-07-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | The gcc_usb_phy_cfg_ahb2phy_clk clock will be managed by RPM. There is no need to model it in the linux clock driver or to control it from the USB driver. Change-Id: I05641c2d532ada36623da1e1cc687c90bc4ee906 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | | Merge "ASoC: aud-ext-clk: enable lnbbclk2 for tavil"Linux Build Service Account2016-07-18
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| * | | ASoC: aud-ext-clk: enable lnbbclk2 for tavilYeleswarapu Nagaradhesh2016-07-16
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | Tavil is sourced from lnbbclk2 and hence enable this clock for tavil codec. CRs-Fixed: 1041199 Change-Id: I5409b0f4ed58fefdd25abbe79f144de7e693c1a1 Signed-off-by: Yeleswarapu Nagaradhesh <nagaradh@codeaurora.org>
* / / clk: msm: clock-gcc-cobalt: Remove support for gcc_bimc_hmss_axi_clkDeepak Katragadda2016-07-15
|/ / | | | | | | | | | | | | | | | | The gcc_bimc_hmss_axi_clk will be configured outside of HLOS. The linux clock driver does not need to manually enable it. CRs-Fixed: 1012646 Change-Id: Ib0b848fb410f4bf266b09cefed0e8bce7292d2ec Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: clock-mmss-cobalt: Add display port clock supportDeepak Katragadda2016-07-11
| | | | | | | | | | | | | | | | Add support for the DP link and crypto clocks on MSMCOBALT. CRs-Fixed: 1028725 Change-Id: I6cdb366499f9589dff9a42491c7ff357e98d65c5 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clock: qcom: Add the clocks supported on MSMFalconTaniya Das2016-07-05
| | | | | | | | | | | | | | | | | | Add all the clocks which are supported on msmfalcon and would be used by the clients for all clock operations for GCC, MMSS, GPU clock controllers. Change-Id: Ie328cb0516644d8a3d66fd0c054575a5cff637dc Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: qcom: rpmcc: Add rpm clock data for msm8996Rajendra Nayak2016-06-23
| | | | | | | | | | | | | | | | | | | | | | Add all RPM clock data for msm8996 family of devices ToDo: Adapt to changes needed for RPM over GLINK against RPM over SMD that the driver currently supports Change-Id: Ib095af601a4f03d866cf94c8e277d04630abb42b Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: qcom: Add support for RPM ClocksGeorgi Djakov2016-06-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds initial support for clocks controlled by the Resource Power Manager (RPM) processor on some Qualcomm SoCs, which use the qcom_rpm driver to communicate with RPM. Such platforms are apq8064 and msm8960. Change-Id: I1a73355bc9117c34589a25cf58446cad13ceb6e3 (cherry picked from commit 06d998a24c68be94685af38e8becfda3c8bf757b) Git-commit: 06d998a24c68be94685af38e8becfda3c8bf757b Git-repo: https://git.linaro.org/landing-teams/working/qualcomm/kernel.git Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: qcom: Add support for SMD-RPM ClocksGeorgi Djakov2016-06-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds initial support for clocks controlled by the Resource Power Manager (RPM) processor on some Qualcomm SoCs, which use the qcom_smd_rpm driver to communicate with RPM. Such platforms are msm8916, apq8084 and msm8974. The RPM is a dedicated hardware engine for managing the shared SoC resources in order to keep the lowest power profile. It communicates with other hardware subsystems via shared memory and accepts clock requests, aggregates the requests and turns the clocks on/off or scales them on demand. This driver is based on the codeaurora.org driver: https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/clk/qcom/clock-rpm.c Change-Id: I8d2882de9410a992a8045caedc7ab71e3c3e45b2 (cherry picked from commit 69edeaf51c07c24e06b433762b3ada7b3d786315) Git-commit: 69edeaf51c07c24e06b433762b3ada7b3d786315 Git-repo: https://git.linaro.org/landing-teams/working/qualcomm/kernel.git Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: msm: clock: Add support for programming MDP_LUT_CBCR registerDeepak Katragadda2016-06-20
| | | | | | | | | | | | | | | | | | | | | | Add support for the mdss_mdp_lut_clk clock on MSMCOBALT. In addition, remove toggling the memory retention bits for the mdp core clock during gdsc_enable/disable. The display driver will use the set_flags API to set the core clock memory retention. CRs-Fixed: 1025605 Change-Id: If812473a67a7900c8f7b8b97f32fbf003f0e80a4 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: qcom: gdsc: Add the missing BIMC gdsc for msm8996Rajendra Nayak2016-06-17
| | | | | | | | | | | | | | | | Add BIMC gdsc data found in MMCC part of msm8996 family of devices. Change-Id: Ibeac134f941f402bcad8e803bdb73ba73f55909d Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: qcom: gdsc: Add mmcc gdscs for msm8996 familyRajendra Nayak2016-06-17
| | | | | | | | | | | | | | | | | | Add all gdsc data which are part of mmcc on msm8996 family Change-Id: I77caf8f26bf676a7553b6873eb188acb02a9c44d Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: qcom: Add MSM8996 Multimedia Clock Controller (MMCC) driverStephen Boyd2016-06-17
| | | | | | | | | | | | | | | | | | | | Add a driver for the multimedia clock controller found on MSM8996 based devices. This should allow most multimedia device drivers to probe and control their clocks. Change-Id: I0b69b1e78a8b0faeaff3e5c87c73e24b1c19ba55 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
* | clk: qcom: gcc-msm8996: Add missing BCR for USB3 and PCIE clocksAmit Nischal2016-06-16
| | | | | | | | | | | | | | | | The block reset registers for USB3 and PCIE will be required by the clients to reset their subsystem blocks so add them in the reset map. Change-Id: Ie30158592fca057454152f3f46a5d8b89ae36b88 Signed-off-by: Amit Nischal <anischal@codeaurora.org>
* | clk: msm: hdmi: add cobalt hdmi pll calculator and clocksAjay Singh Parmar2016-06-09
| | | | | | | | | | | | | | | | | | | | Add PLL and PHY programming for HDMI. Dynamically calculate the register values to be programmed for a given pixel clock. CRs-Fixed: 1022772 Change-Id: Ibf7877eb6edd29baefee57bc12188989d897d47e Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org> Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
* | clk: msm: clock: Add support for programming the GCC_GPU_IREF_EN registerDeepak Katragadda2016-06-07
| | | | | | | | | | | | | | | | | | | | Add a new gcc_gpu_iref_clk that the graphics driver can control as needed. The default state of the clock is ON; so having this control will mean saving current. CRs-Fixed: 1024948 Change-Id: I562bb546f49b1605f20fb7d705f40584d190230b Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: qcom: gdsc: Add GDSCs in msm8996 GCCRajendra Nayak2016-06-06
| | | | | | | | | | | | | | | | | | Add all data for the GDSCs which are part of msm8996 GCC block Change-Id: I12323575c44b1a3ba4cb2764a498480b3e62dcaa Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: msm: clock-gcc-cobalt: Add the cnoc_periph RPM resource supportDeepak Katragadda2016-06-02
| | | | | | | | | | | | | | | | | | | | Add support for modelling a new cnoc_periph RPM resource on MSM COBALT. In addition, fix the rpm_res_type being used for the mmssnoc_axi_clk and remove the pnoc resource support. CRs-Fixed: 1003213 Change-Id: I9f9845fea425fc4463dae72e8f8ab6e8bda23121 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: qcom: Add MSM8996 Global Clock Control (GCC) driverStephen Boyd2016-06-01
| | | | | | | | | | | | | | | | | | | | Add support for the global clock controller found on MSM8996 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Change-Id: I559f5976b56bf8933df2c68fc4e29b2bd0ce1160 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | ARM: dts: msm: Add snapshot of power-on.hSubbaraman Narayanamurthy2016-05-18
| | | | | | | | | | | | | | | | | | This DT bindings header file snapshot is taken as of msm-3.18 'commit 0b20839e37187 ("Merge "slim-msm: Synchronize SSR callbacks"")'. CRs-Fixed: 1001210 Change-Id: Ic132efb650d4e8de561c3d1f95a281afeef4ce42 Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
* | clk: msm: clock-gcc-cobalt: Add reset capability to PCIE pipe clockDeepak Katragadda2016-05-15
| | | | | | | | | | | | | | | | | | Instead of having a separate reset clock for PCIE 0 reset, tag the BCR register with the gcc_pcie_0_pipe_clk directly. CRs-Fixed: 1014989 Change-Id: Icbc3a4a237bd0ac75fbef0857238e18cfb0ca533 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-21 06:47:53 +0000