diff options
| author | Taniya Das <tdas@codeaurora.org> | 2016-07-28 21:34:02 +0530 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2016-08-08 04:39:14 -0700 |
| commit | 959d88255142f6d5e628bf14e7b9ae72f3e93fab (patch) | |
| tree | 230204874165904cb646421ad2ff43640ede5e77 /include/dt-bindings | |
| parent | 4627274b90b0339045c1b7d2655d8db7196a4432 (diff) | |
clk: msm: Add support for block reset clocks
Add the block reset clocks which will be used by clients to
assert/deassert these clocks using the reset controller framework.
Change-Id: I3e9f7f85bf1faf0e1bb501196ba9d7e197111a03
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/msm-clocks-8996.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/msm-clocks-8996.h b/include/dt-bindings/clock/msm-clocks-8996.h index 2f9cfd0e008c..22109a6766db 100644 --- a/include/dt-bindings/clock/msm-clocks-8996.h +++ b/include/dt-bindings/clock/msm-clocks-8996.h @@ -540,4 +540,33 @@ #define clk_sys_apcsaux_clk 0x0b0dd513 #define clk_cpu_debug_mux 0xc7acaa31 +/* GCC block resets */ +#define QUSB2PHY_PRIM_BCR 0 +#define QUSB2PHY_SEC_BCR 1 +#define BLSP1_BCR 2 +#define BLSP2_BCR 3 +#define BOOT_ROM_BCR 4 +#define PRNG_BCR 5 +#define UFS_BCR 6 +#define USB_20_BCR 7 +#define USB_30_BCR 8 +#define USB3_PHY_BCR 9 +#define USB3PHY_PHY_BCR 10 +#define PCIE_0_PHY_BCR 11 +#define PCIE_1_PHY_BCR 12 +#define PCIE_2_PHY_BCR 13 +#define PCIE_PHY_BCR 14 +#define PCIE_PHY_COM_BCR 15 +#define PCIE_PHY_NOCSR_COM_PHY_BCR 16 + +/* MMSS Block resets */ +#define VIDEO_BCR 0 +#define MDSS_BCR 1 +#define CAMSS_MICRO_BCR 2 +#define CAMSS_JPEG_BCR 3 +#define CAMSS_VFE0_BCR 4 +#define CAMSS_VFE1_BCR 5 +#define FD_BCR 6 +#define GPU_GX_BCR 7 + #endif |