summaryrefslogtreecommitdiff
path: root/drivers/clk/msm/mdss (follow)
Commit message (Collapse)AuthorAge
* clk/msm: fix HDMI PHY registers as per latest programming guideAbhinav Kumar2018-10-25
| | | | | | | | | | | | | HDMI PHY registers for MSM8998 chipset are not programmed as per the latest hardware programming guide for the chipset. This can affect HDMI electrical compliance test cases due to low signal strength. Fix up the HDMI PHY driver to use the latest values for the PHY registers. Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Change-Id: I96dd6ffaf127940d34af898c5a2982209a6fc83c
* clk: qcom: mdss: improve DSI PLL's performanceGuchun Chen2018-03-07
| | | | | | | | To improve performance margin for DSI's PLL at cold temperature case, the value of DSIPHY_PLL_PLL_ICPMSET should be changed from 0x24 to 0x3f. Change-Id: I139e37e137355c5e8f0b3bebd28b23a09593dd13 Signed-off-by: Guchun Chen <guchunc@codeaurora.org>
* clk: qcom: mdss: fix the divider programming for DisplayPort PLLPadmanabhan Komanduru2017-11-16
| | | | | | | | | Fix the divider programming of DisplayPort PLL with the correct value. Without this, display doesn't up fine with certain resolutions on some sinks when link rate is 5.4 GHz. Change-Id: I7c5a452a9df757240a1c6c3d371bd46a16f98efd Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
* clk: msm: mdss: add support for chip serial number in dfps infoAshish Garg2017-09-19
| | | | | | | | | | Dfps info is calculated for a specific msm part and needs to be used for the same. Add a chip serial number for the dfps info so that the PLL trim codes are used for the same msm part on which they are generated. Change-Id: I6f1e519c1e9278b35dfbdf3d9ba4a2ed0e1a6a78 Signed-off-by: Ashish Garg <ashigarg@codeaurora.org>
* Merge "clk: msm: Fix pll out div programming"Linux Build Service Account2017-07-25
|\
| * clk: msm: Fix pll out div programmingRajkumar Subbiah2017-05-15
| | | | | | | | | | | | | | | | | | | | | | The PLL out divider is currently not programmed when the PLL is locked. Since they are setup as fixed ratio dividers, the set_div is not called during set_rate. So this fix moves the pll out div programming to pll out mux selection callback which gets called during set_rate. Change-Id: I48b0254c6eb308071706258d2b5a77f06d9927c2 Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
| * clk: msm: Fix dsi clock divider configurationRajkumar Subbiah2017-05-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The MND values and the PLL output divider configuration does not match the recommended values. When setting DSI pixel clock rate the MND array is ordered in a way that the requested rate goes from highest to lowest. Since the recommendation is to divide the clocks as close to VCO as possible, the request should be from lowest to highest. So reversing the fraction array to match the recommendation. The VCO min max rates are currently forced after pll output divider which is also fixed. Change-Id: I3cb5163f9c8dd3723cdc58bd7e7980719e683f1b Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
* | msm: mdss: Update msm8998 HDMI PHY sequence for bridge chipLei Chen2017-05-31
|/ | | | | | | | | | Add support for 1.8v external power supply HDMI PHY sequence which is used by bridge chip. CRs-Fixed: 1074721 Change-Id: I0ae55cdc9151949b81f6de828238e4b88ceea3df Signed-off-by: Lei Chen <chenl@codeaurora.org> Signed-off-by: Yuchao Ma <yuchaom@codeaurora.org>
* clk: mdss: adjust PLL disable sequence to avoid glitchAbhinav Kumar2017-04-05
| | | | | | | | | Adjust the PLL disable sequence as per the latest HW programming guidelines to ensure there will not be any stray clock glitches when PLL is turned OFF abruptly. Change-Id: I6df35bbe18b0c42b43f38b9dd85c3502b2038928 Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
* clk: mdss: re-program PLL registers to power-on-reset valueAbhinav Kumar2017-04-05
| | | | | | | | | | | | When the supply to PLL digital domain is turned off, it can result in certain PLL registers to get corrupted. Make sure to re-program the PLL registers to the power-on-reset value before starting to program the PLL again to ensure that it locks reliably. Change-Id: I63cac884cf11eae60b187f83654f5922a3342d66 Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
* Merge "clk: msm: mdss: Update DSI PLL configuration for msmcobalt"Linux Build Service Account2016-12-21
|\
| * clk: msm: mdss: Update DSI PLL configuration for msmcobaltNaseer Ahmed2016-12-07
| | | | | | | | | | | | | | | | | | Update the DSI PLL configuration to match the latest recommendations. DP mode is changed from 01 to 00 in addition to other changes. Change-Id: Id0fe7d3d60db310690c2ba2e277da911d3798076 Signed-off-by: Naseer Ahmed <naseer@codeaurora.org>
* | clk: msm: hdmi: HDMI 10nm HPG Rev2.0 updateLei Chen2016-12-16
| | | | | | | | | | | | | | | | | | HPG Rev 1.0 is a basic bring up implementation of HDMI PHY/PLL. This change absorbs the changes upgrade to HPG Rev2.0. CRs-Fixed: 1033918 Change-Id: I768463aaad17f7be5d3fe11d7ca23d422833cfe5 Signed-off-by: Lei Chen <chenl@codeaurora.org>
* | msm: mdss: dp: correctly ref count the pll resourcesSiddhartha Agrawal2016-12-08
|/ | | | | | | | | | This fixes the issue where the dp pll resource was not correctly keeping a refcount on the pll resource. This will fix the bootup warning when both DSI and DP are enabled. Crs-Fixed: 1088737 Change-Id: I19f8eef7f664a58cac1a082b8195e48c52613c5d Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
* clk: msm: mdss: fix PHY programming for flip plug orientationTatenda Chipeperekwa2016-11-28
| | | | | | | | | | | Fix the PHY programming sequence for flip plug orientation by ensuring that the correct PHY_MODE and LANE_MODE values are selected, depending on the orientation and link rate respectively. Change-Id: I6e74c20c509b7007a86df9d99894a9a6c0baa946 Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org> CRs-Fixed: 1062508
* clk: msm: hdmi: correct the precision when calculating HDMI PLLRay Zhang2016-11-25
| | | | | | | | | | In existing HDMI PLL driver the VCO frequency value is truncated so following PLL calculation could be impacted. Use 64 bit value instead to maintain the necessary precision. CRs-Fixed: 1086894 Change-Id: Iec3f65942dd152b0b7aa32af1a90039fff06cb34 Signed-off-by: Ray Zhang <rayz@codeaurora.org>
* clk: msm: hdmi: add support for live programming of HDMI PLLRay Zhang2016-11-25
| | | | | | | | | | | | Clock recovery and dynamic resolution change require changing HDMI clock rate while HDMI PLL is on. There are two paths while clock is changed, one is atomic update which doesn't require PLL tear down, the other is when clock rate change is too big and a full PLL tear down is needed. CRs-Fixed: 1086894 Change-Id: Ia202e0aee09f506a7bbe4e13702f30dee119ce8e Signed-off-by: Ray Zhang <rayz@codeaurora.org>
* msm: 8998: Replace cobalt with 8998Runmin Wang2016-11-22
| | | | | | | | | | | Update the code name from msmcobalt to msm8998. As a result, update the filename containing "cobalt" and files content containing "cobalt". CRs-Fixed: 1070840 Change-Id: I2c7b95e3e2a2fec7730724da9eeb86a39a77faf1 Signed-off-by: Runmin Wang <runminw@codeaurora.org> Signed-off-by: Kyle Yan <kyan@codeaurora.org> Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
* Merge "clk: msm: mdss: fix divider configuration for 5.4 Ghz link rate"Linux Build Service Account2016-11-14
|\
| * clk: msm: mdss: fix divider configuration for 5.4 Ghz link rateChandan Uddaraju2016-11-08
| | | | | | | | | | | | | | | | | | Update the FRAC_START3 register settings for 5.4 GHz link rate in Display-Port PLL driver. This is needed for accurate link and pixel clock values. Change-Id: Ib6a0ee570fe2d5a1d43296e792a354ca25b1d82c Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
* | Merge "clk: msm: mdss: fix potential use of un-initialized variable"Linux Build Service Account2016-11-13
|\ \ | |/ |/|
| * clk: msm: mdss: fix potential use of un-initialized variableNaseer Ahmed2016-09-22
| | | | | | | | | | | | | | Fix potential use of un-initialized variable by initializing the variable. Change-Id: Ib43bdbc1ac51334bcd930657c99f7a0aa255255a Signed-off-by: Naseer Ahmed <naseer@codeaurora.org>
* | clk: msm: mdss: fix DSI PLL post vco divider configurationAravind Venkateswaran2016-10-12
| | | | | | | | | | | | | | | | | | | | | | | | | | The post vco divider clock in the DSI PLL can only be configured to a fixed value of 1 or 4. Current implementation can result in the divider being set to any value between 1 and 4 which can result in failures while enabling the DSI pixel clock. Fix this by replacing the post vco divider with a fixed /1 and /4 dividers followed by a mux clock. CRs-Fixed: 1064277 Change-Id: I01bc7304e446c622849c678c64a3fd6881413e89 Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
* | clk: msm: mdss: use lane count and orientation to configure DP PHYChandan Uddaraju2016-10-07
| | | | | | | | | | | | | | | | | | Use the information about lane count and orientation provided in the spare MDP registers by the DP controller driver to configure the PLL lock sequence. Change-Id: I1d8465087be91f0a35d83a752a6c09ce27100208 Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
* | clk: msm: mdss: update PLL configuration to clear precalibrated valuesSandeep Panda2016-10-06
| | | | | | | | | | | | | | | | | | | | | | | | Before going for full PLL enable sequence, we need to clear out the override bit and precalibrated values of VCO_TUNE and KVCO_CODE, as these registers might be storing values for old VCO rate. This will cause the DSI PLL to be in a bad state and hence PLL unlock errors might occur during use case like resolution switch. So always clear the precalibrated values first in PLL configuration sequence. Change-Id: I407920d63b4600b610794141e5b7ceb5a33980c1 Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
* | msm: mdss: fix 32-bit compilation errors in MDSS PP/interfacesPadmanabhan Komanduru2016-10-06
| | | | | | | | | | | | | | | | Add required changes to fix 32-bit compilation issues in MDSS PP and DP/HDMI interface drivers. Change-Id: I0b342c0307b257cb8c66fcae73dd94d0fb3122db Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
* | clk: msm: mdss: change DP clock rate in order of KHzPadmanabhan Komanduru2016-09-08
|/ | | | | | | | | | | Certain frequencies of DP VCO clock are more than 4.29 GHz and are not supported by clock framework on 32 bit builds, since it exceeds the maximum value of unsigned long data type. To fix this issue, change the DP link clock frequencies in order of KHz in DP FB driver/MMSS cobalt clock driver/DP PLL driver. Change-Id: I46d9b5c57f94aa1f10df08c4430b617355a82eec Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
* Merge "msm: mdss: dsi: update DSI phy v3 initialization sequence"Linux Build Service Account2016-08-26
|\
| * clk: msm: mdss: update DSI PLL programming for msmcobaltAravind Venkateswaran2016-08-18
| | | | | | | | | | | | | | | | | | | | Update the DSI PLL programming for msmcobalt to reflect the recommended values. The key update is to ensure that the global bit clock is turned on only after the PLL is locked. CRs-Fixed: 1033911 Change-Id: I1e4046dd4a7dbb66ad2502e210e58130f08a2b51 Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
* | clk: msm: mdss: update Dp PLL/Phy configurationChandan Uddaraju2016-08-22
| | | | | | | | | | | | | | | | | | | | | | | | Update the Display-Port PHY and PLL configuration with the recommended settings. Remove the support for 9.72Ghz VCO frequency. Update the divider settings to support the new frequency plan. Update the Phy Aux settings and voltage/pre-emphasis settings according to recommended configuration. Change-Id: Ic4d206da3dc6b45214e7601e7556cfb0bef81a7d Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
* | mdss: display-port: fix Display-port disable sequenceChandan Uddaraju2016-08-21
| | | | | | | | | | | | | | | | | | | | | | Fix the OFF path for display-port driver when cable is disconnected. Check for link clock status before accessing any of the mainlink registers. Use common mutex for DP_ON and DP_OFF sequence. Remove the resource vote when PLL is diabled. Change-Id: I9b81f79043b4ea7355b99ba9d8347d79bed10153 Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
* | clk: msm: mdss: add SSC support for dsi PLL on msmcobaltBenjamin Chan2016-08-16
|/ | | | | | | | | Add support to control Spread Spectrum Clocking (SSC) in the DSI PLL on msmcobalt. CRs-Fixed: 1036187 Change-Id: I158670185976801970d54bec4bc42014b1b28b96 Signed-off-by: Benjamin Chan <bkchan@codeaurora.org>
* clk: msm: hdmi: fix value of constant for minimum VCO rateTatenda Chipeperekwa2016-07-21
| | | | | | | | | | | | Fix the value of the constant for the minimum VCO rate by setting it to 250MHz. This fix will allow valid clock rates such as 252MHz to be configured for the HDMI PHY and enable certain HDMI modes to work correctly instead of failing the validation checks when setting the VCO rate. CRs-Fixed: 1039464 Change-Id: I0e90de49d295563aba87af39169bd3dea1f8ade7 Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
* Merge "clk: msm: Add MSM clock config for MSM clock controller"Linux Build Service Account2016-07-18
|\
| * clk: msm: Add MSM clock config for MSM clock controllerTaniya Das2016-07-12
| | | | | | | | | | | | | | | | Support MSM clock controller config to allow MSM devices to use the clock controller. Change-Id: Iae2cf922e8a69979ea353bf7353304f9be7405ce Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: msm: mdss: fix calculation of VCO rate during handoffAravind Venkateswaran2016-07-12
|/ | | | | | | | | | | | When continuous splash screen feature is enabled, the DSI PLL is configured in the bootloader and left on when the kernel boots up. When the PLL clocks are handed off, the VCO rate needs to be computed back from the registers. Fix bugs in the current implementation for calculating the VCO rate. CRs-Fixed: 1037857 Change-Id: I8905b91f26a66d26959fb109480f0390851cbdb4 Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
* clk: msm: hdmi: add cobalt hdmi pll calculator and clocksAjay Singh Parmar2016-06-09
| | | | | | | | | | Add PLL and PHY programming for HDMI. Dynamically calculate the register values to be programmed for a given pixel clock. CRs-Fixed: 1022772 Change-Id: Ibf7877eb6edd29baefee57bc12188989d897d47e Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org> Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
* clk: msm: mdss: fix DP register configurationsChandan Uddaraju2016-05-27
| | | | | | | | | | | | | | | | | This change provides the below updates: - Current DP PLL driver uses the pll_base and the base address for the TXn registers instead of phy_base address. Fix this by using the correct base address. - Disable handoff for vco_divided_clk by implementing handoff function for this clock. - Update the PLL settings to fix PLL locking issues. CRs-Fixed: 1009740 Change-Id: Iea46c5b0482bceb841309175ede42ec3be3e20fd Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
* clk: msm: mdss: fix dp_link_2x_clk_mux clock ops for DP PLL on msmcobaltChandan Uddaraju2016-05-27
| | | | | | | | | | | | | The DP link clock path in the DSI PLL has a mux clock (dp_link_2x_clk_mux) which allows the pixel clock to be either sourced out two divider clocks. In the current code, the ops for this mux clock is overloaded incorrectly which results in the link clock being always sourced out of the first divider clock. Fix this by using the default mux clock ops for this clock. CRs-Fixed: 1009740 Change-Id: Ie12d5ab272dbd79fe97225864c2360fdde7325a7 Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
* clk: msm: mdss: fix DSI PLL programming for msmcobaltAravind Venkateswaran2016-05-24
| | | | | | | | | | | | VCO configuration should be based on the requested vco clock rate and should not factor in the bit clock source divider. In addition, the bit clock source divider for the slave controller should always be set to 1. This will ensure that the PLL is locked at the correct rate. CRs-Fixed: 1019289 Change-Id: Ie5c171e13dcccc711ba03acb38fcd7876e792cee Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
* clk: msm: mdss: fix pclk_src_mux clock ops for DSI PLL on msmcobaltAravind Venkateswaran2016-05-16
| | | | | | | | | | | | The DSI pixel clock path in the DSI PLL has a mux clock (pclk_src_mux) which allows the pixel clock to be either sourced out of the VCO clock or the bitclock. In the current code, the ops for this mux clock is overloaded incorrectly which results in the pixel clock being always sourced out of the bit clock. Fix this by using the default mux clock ops for this clock. Change-Id: I39c23b52d17994e28bd3b0d93e8e3dabdb687940 Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
* clk: qcom: mdss: add Display-port pll clock driver supportChandan Uddaraju2016-05-09
| | | | | | | | | | Add support for new Display-port PLL clock driver to handle different DP panel resolutions in msmcobalt. Add separate files to support this new PHY PLL block. CRs-Fixed: 1009740 Change-Id: Ic282c7e14fc6e23f4d044cb6a58249bdb4c8c2d8 Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
* clk: msm: mdss: add support for dsi pll on msmcobaltAravind Venkateswaran2016-04-25
| | | | | | | | | Add support to program the DSI PLL on msmcobalt which is needed to drive the DSI byte and pixel clocks. CRs-Fixed: 1000576 Change-Id: Ic11a3747a0e008e1f71df91a1a79d33242d2a2a4 Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
* Merge branch 'mdss-final-replay' into msm-4.4Adrian Salido-Moreno2016-04-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This merge brings all display changes from msm-3.18 kernel * (58 commits) msm: mdss: add support for additional DMA pipes msm: mdss: refactor device tree pipe parsing logic msm: mdss: refactor mixer configuration code msm: mdss: add support for secure display on msm8953. msm: mdss: disable ECG feature on 28nm PHY platform msm: mdss: send DSI command using TPG when in secure session msm: mdss: Update histogram and PA LUT in mdss V3 msm: mdss: validate layer count before copying userdata msm: mdss: Fix potential NULL pointer dereferences Revert "msm: mdss: Remove redundant handoff pending check" msm: mdss: hdmi: Do not treat intermediate ddc error as failure msm: mdss: revisit igc pipe enumeration logic msm: mdss: Add PA support for mdss V3 msm: mdss: Add support for mdss v3 ops msm: mdss: Update the postprocessing ops using mdss revision msm: mdss: update the caching payload based on mdss version msm: clk: hdmi: add support for atomic update msm: sde: Add v4l2 rotator driver to enable multi-context usecase msm: mdss: refactor pipe type checks msm: mdss: add proper layer zorder validation msm: mdss: stub bus scaling functions if driver is disabled msm: mdss: avoid failure if primary panel pref is not enabled msm: adv7533: add support for clients to read audio block msm: mdss: add lineptr interrupt support for command mode panels msm: mdss: update rotator frame rate in the pipe configuration mdss: msm: Avoid excessive failure logs in igc config msm: mdss: delay dma commands for split-dsi cmd mode panels msm: mdss: enable GDSC before enabling clocks in MDP3 probe mdss: dsi: turn off phy power supply during static screen mdss: dsi: read dsi and phy revision during dsi ctrl probe msm: mdss: Fix memory leak in MDP3 driver msm: mdss: delay overlay start until first update for external msm: mdss: free splash memory for MSM8909w after splash done msm: mdss: hdmi: separate audio from transmitter core msm: mdss: disable dsi burst mode when idle is enabled msm: mdss: remove invalid csc initialization during hw init msm: mdss: dsi: increase dsi error count only for valid errors msm: mdss: remove HIST LUT programming in mdss_hw_init msm: mdss: dsi: ignore error interrupt when mask not set msm: mdss: add support to configure bus scale vectors from dt msm: mdss: unstage the pipe if there is z_order mismatch msm: mdss: squash MDP3 driver changes and SMMU change msm: mdss: Read the bridge chip name and instance id from DTSI msm: mdss: Enable continuous splash on bridge chip msm: mdss: Fix multiple bridge chip usecase msm: mdss: Enable export of mdss interrupt to external driver msm: mdss: rotator: turn off rotator clock in wq release msm: mdss: fix ulps during suspend feature logic clk: msm: mdss: program correct divider for PLL configuration msm: mdss: fix DSI PHY timing configuration logic msm: mdss: hdmi: add support for hdmi simulation msm: mdss: handle race condition in pingpong done counter clk: qcom: mdss: calculate pixel clock for HDMI during handoff msm: mdss: ensure proper dynamic refresh programming for dual DSI msm: mdss: Add fps flag and update blit request version msm: mdss: initialize fb split values during fb probe mdss: mdp: fix rotator compat layer copy msm: mdss: handle DSI ctrl/PHY regulator control properly CRs-Fixed: 1000197 Change-Id: I521519c8abe8eed6924e2fbe3e1a026126582b77 Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
* clk: msm: mdss: update PLL configuration for 8996Chandan Uddaraju2016-03-25
| | | | | | | | Update the PLL_LPF_CAP values to latest recommended settings. This fixes any PLL locking issues. Change-Id: I206c9cc343ac435161393445714de2e03a64aaae Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
* clk: msm: mdss: update the frame rate count supported for DFPSPadmanabhan Komanduru2016-03-25
| | | | | | | | | | Update the number of frame rates supported for dynamic refresh feature from 10 to 20. This is needed to support all the fps values requested by display HAL between minimum fps and maxiumum fps based on the requirement. Change-Id: Ib7487ad17261ac8c4d6929787899161061e71078 Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
* clk: msm: mdss: update the programming of DYNAMIC_REFRESH_PLL_UPPER_ADDR2Padmanabhan Komanduru2016-03-25
| | | | | | | | | | | | As part of dynamic refresh sequence, we program PLL_UPPER_ADDR2 register to 0x003FFE00 instead of 0x001FFE00. This causes a register write to DSIPHY_PLL_KVCO_COUNT1 to 0x1 during the dynamic refresh operation whereas the register write is supposed to happen for DSIPHY_CMN_PLL_CNTRL register. Update the write value to DYNAMIC_REFRESH_PLL_UPPER_ADDR2 to take care of this. Change-Id: I991920d5a45e79670a4a033c8a83bef6c7f3136b Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
* clk: msm: mdss: update the procedure for storing DSI PLL codesPadmanabhan Komanduru2016-03-23
| | | | | | | | | | | | In the current implementation, the DSI PLL codes are copied from a CMA memory which has a no-map attribute. Update the logic by reading the pre-calibrated DSI PLL codes from physical memory which is re-mapped to virtual memory allocated in kernel using ioremap_page_range. Once the DSI PLL codes are stored, free the reserved CMA memory back to kernel. Change-Id: Iaa0bbd600dd1a18497cd4dfd7830a9bf88ab0ead Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
* clk: qcom: mdss: set the hdmi vco clock rateTatenda Chipeperekwa2016-03-23
| | | | | | | | | Set the VCO rate properly during handoff. This VCO rate can be used during suspend-resume to reconfigure the PLL. Change-Id: Ib67d68f28aa5bd3a09bf7bcc5802ee3b7af342ee Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org> Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
* clk: msm: mdss: Read PLL/PHY status once during bootupTatenda Chipeperekwa2016-03-23
| | | | | | | | | | Read the PLL/PHY status once during bootup to avoid delays due to polling. Polling for PLL/PHY status is only required when handling HDMI use cases in which the cable is connected after bootup is complete. Change-Id: Ie1d5983a7784cb5f3472527d1b510f128ae9d325 Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-28 20:42:02 +0000