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* clock-gcc-8996: gcc_mss_q6_bimc_axi_clk is not always on anymoreYaroslav Furman2022-07-27
| | | | | | | | | | | | For some reason it can randomly error on boot with message [ 0.466725] gcc_mss_q6_bimc_axi_clk: status stuck off *warning* [ 0.468169] failed to enable always-on clock gcc_mss_q6_bimc_axi_clk Fine... Let it not be always on. Signed-off-by: Yaroslav Furman <yaro330@gmail.com> Signed-off-by: Davide Garberi <dade.garberi@gmail.com>
* clk: msm: clock-cpu-8996: Use CLKFLAG_NO_RATE_CACHE for perfcl_hf_muxSultanxda2022-07-27
| | | | | | | | | The performance cluster can have frequency change requests ignored when it comes online without having this flag set. This can result in the perfcl running at its default frequency instead of the frequency that the CPU governor wants. Signed-off-by: Sultanxda <sultanxda@gmail.com>
* clk: msm: Fix compilation errors with clangSwetha Chikkaboraiah2020-06-08
| | | | | | | Fix -Wliteral-conversion specific compilation errors. Change-Id: I91ec707f1099dcd01af9be71fed3dac2b399dfaf Signed-off-by: Swetha Chikkaboraiah <schikk@codeaurora.org>
* clk: msm: mmss: Add dev_pm_ops for MMSS PLL for 8996Taniya Das2018-12-19
| | | | | | | | | | | Support early resume and late suspend for MMPLLs to support hibernation. Without this change, the mmplls were not getting restored to a sane state on the hibernate resume. Change-Id: I7edb7219149d2e96a9487cdaf19a0bc4b9ec709f Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
* clk/msm: fix HDMI PHY registers as per latest programming guideAbhinav Kumar2018-10-25
| | | | | | | | | | | | | HDMI PHY registers for MSM8998 chipset are not programmed as per the latest hardware programming guide for the chipset. This can affect HDMI electrical compliance test cases due to low signal strength. Fix up the HDMI PHY driver to use the latest values for the PHY registers. Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Change-Id: I96dd6ffaf127940d34af898c5a2982209a6fc83c
* clk: msm: add uninterruptible flag in hab receiving for virtual reset.Zhiqiang Tu2018-09-07
| | | | | | | | Add uninterruptible flag in hab receiving for virtual reset controller to avoid being interrupted by signal. Change-Id: Iddca4134eec082537110bd7735e0e282cd5c7454 Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
* clk: msm: clock-mmss-8996: disable cache based clk rateRahul Sharma2018-06-29
| | | | | | | | | | Use flag CLKFLAG_NO_RATE_CACHE for RCG and branch clock for mdss_extpclk_clk used for HDMI interface. Using this flag will allow the clock framework to calculate rate again and not depend on the cached rates. Change-Id: I88f8924074a23e5a6fd48ce6243c7db89580109b Signed-off-by: Rahul Sharma <rahsha@codeaurora.org>
* clk: msm: Add rpm controlled clock support for virtual clockZhiqiang Tu2018-04-25
| | | | | | | | Add rpm controlled clocks for msm8996 frontend virtual clock which need the remote flag. Change-Id: I146ac01522aa13033c959f390667d8098ee333b7 Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
* clk: msm: Fix signal interrupt issue for virtual clockZhiqiang Tu2018-04-10
| | | | | | | | | Virtual clock operations returned error when received signal. Uninterruptible flag is added in receiving response to avoid being interrupted by signal. Change-Id: Id3b5b56432751ec5b49c36a028444c0360fe811f Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
* clk: msm: osm: Update maximum number of bytes to read from bufferTaniya Das2018-04-05
| | | | | | | | | Currently the number of maximum bytes to be copied from buffer is incorrectly using the size of buffer. Replace to use the count which is the maximum number of bytes to be read. Change-Id: I797c4dc0af626e347dfef43a754d0c469585ba55 Signed-off-by: Taniya Das <tdas@codeaurora.org>
* Merge "clk: qcom: mdss: improve DSI PLL's performance"Linux Build Service Account2018-03-07
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| * clk: qcom: mdss: improve DSI PLL's performanceGuchun Chen2018-03-07
| | | | | | | | | | | | | | | | To improve performance margin for DSI's PLL at cold temperature case, the value of DSIPHY_PLL_PLL_ICPMSET should be changed from 0x24 to 0x3f. Change-Id: I139e37e137355c5e8f0b3bebd28b23a09593dd13 Signed-off-by: Guchun Chen <guchunc@codeaurora.org>
* | clk: msm: Add reset support in dummy clock driverZhiqiang Tu2018-02-14
| | | | | | | | | | | | | | | | | | Some pass-through devices on msm8996 virtual platform need dummy clock reset. Change-Id: I88f4028fe56e428f12b2149a4413c3328da880bb Signed-off-by: Ramachandran Venkataramani <ramavenk@codeaurora.org> Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
* | clk: msm: Add usb2s support for msm8996 virtual clockZhiqiang Tu2018-01-21
| | | | | | | | | | | | | | Add the usb2s relevant clocks in msm8996 virtual clock driver. Change-Id: Id72e1a69f39ee2dd0c871828e9faed8dbedefd5b Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
* | clk: msm: Add reset support in virtual clock frontend driverZhiqiang Tu2018-01-15
|/ | | | | | | | | | To support reset function in virtual clock driver, we register a reset controller in virtual clock front driver. It is a virtual reset controller which talks with host backend via virtual clock message. Change-Id: I13d48180534110260d66e42f3a02b63c2afcaeca Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
* clk: msm: virtual clock adds support for usb, lpass and modemZhiqiang Tu2017-12-13
| | | | | | | | Support usb, lpass and modem clocks in msm8996 virtual clock frontend driver. Change-Id: I5ee4f2d951f133a8403442707e633563efdc5c65 Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
* clk: msm: Add virtual clock frontend driverZhiqiang Tu2017-12-08
| | | | | | | | | It is virtual clock frontend driver which communicates with host backend clock service/driver over HABMM. It only supports msm8996 virtual platform currently. Change-Id: Icfee28c301fa4a583b45e5d364432535643eb9b7 Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
* clk: qcom: mdss: fix the divider programming for DisplayPort PLLPadmanabhan Komanduru2017-11-16
| | | | | | | | | Fix the divider programming of DisplayPort PLL with the correct value. Without this, display doesn't up fine with certain resolutions on some sinks when link rate is 5.4 GHz. Change-Id: I7c5a452a9df757240a1c6c3d371bd46a16f98efd Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
* clk: msm: Fix dummy clock fixed rate setting issueZhiqiang Tu2017-10-13
| | | | | | | | Set fixed rate in of_dummy_get since dummy_clk_dt_parser is not called. Change-Id: Id33be0a00a0a29100618f5fd25a917983f654025 Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
* clk: msm: mdss: add support for chip serial number in dfps infoAshish Garg2017-09-19
| | | | | | | | | | Dfps info is calculated for a specific msm part and needs to be used for the same. Add a chip serial number for the dfps info so that the PLL trim codes are used for the same msm part on which they are generated. Change-Id: I6f1e519c1e9278b35dfbdf3d9ba4a2ed0e1a6a78 Signed-off-by: Ashish Garg <ashigarg@codeaurora.org>
* Merge branch 'msm-4.4' into dev/msm-4.4-8996auZhiqiang Tu2017-08-24
|\ | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/iommu/arm-smmu.c drivers/media/platform/msm/ais/fd/msm_fd_dev.c drivers/media/platform/msm/camera_v2/fd/msm_fd_dev.c drivers/soc/qcom/glink.c include/uapi/linux/msm_ipa.h Change-Id: Id007a850fa2df09f08c413ffcd447a6532fad83c Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
| * Merge "clk: osm: Check for valid acd offset for input from debugfs"Linux Build Service Account2017-08-21
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| | * clk: osm: Check for valid acd offset for input from debugfsTaniya Das2017-07-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The user supplied acd offset is not verified to be within the acd register range which could lead to out-of-bounds read/write. Fix the same by checking the input and also make sure the acd base is present before the read/write. Change-Id: I9c0d9049d273633f6ef99593b1b45d98cc7c3827 Signed-off-by: Taniya Das <tdas@codeaurora.org>
| * | Merge "clk: msm: Fix pll out div programming"Linux Build Service Account2017-07-25
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| | * clk: msm: Fix pll out div programmingRajkumar Subbiah2017-05-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PLL out divider is currently not programmed when the PLL is locked. Since they are setup as fixed ratio dividers, the set_div is not called during set_rate. So this fix moves the pll out div programming to pll out mux selection callback which gets called during set_rate. Change-Id: I48b0254c6eb308071706258d2b5a77f06d9927c2 Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
| | * clk: msm: Fix dsi clock divider configurationRajkumar Subbiah2017-05-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MND values and the PLL output divider configuration does not match the recommended values. When setting DSI pixel clock rate the MND array is ordered in a way that the requested rate goes from highest to lowest. Since the recommendation is to divide the clocks as close to VCO as possible, the request should be from lowest to highest. So reversing the fraction array to match the recommendation. The VCO min max rates are currently forced after pll output divider which is also fixed. Change-Id: I3cb5163f9c8dd3723cdc58bd7e7980719e683f1b Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
| * | clk: msm: clock-osm: Do not initialize ACD if the cluster isn't onlineDeepak Katragadda2017-06-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The OSM clock driver currently enables ACD for the silver and gold clusters regardless of whether they've been brought up or not. ACD requires the cluster PLLs to be running for initialization, a requirement which would not be met if the cluster hasn't been brought online. Tie the ACD initialization sequence with enabling OSM for that cluster. Change-Id: Ib393dd339f8095029c9703fbe67897d0a491eced Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | | clk: msm: Add fixed rate clock support for dummy clock driverZhiqiang Tu2017-06-22
|/ / | | | | | | | | | | | | | | Virtual platform uses dummy clock driver. It needs dummy clock driver to support fixed rate clock. Change-Id: Id0f6ce592447a443c22ad49fddeaa598cf3d047e Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
* | Merge "msm: mdss: Update msm8998 HDMI PHY sequence for bridge chip"Linux Build Service Account2017-06-07
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| * | msm: mdss: Update msm8998 HDMI PHY sequence for bridge chipLei Chen2017-05-31
| |/ | | | | | | | | | | | | | | | | | | Add support for 1.8v external power supply HDMI PHY sequence which is used by bridge chip. CRs-Fixed: 1074721 Change-Id: I0ae55cdc9151949b81f6de828238e4b88ceea3df Signed-off-by: Lei Chen <chenl@codeaurora.org> Signed-off-by: Yuchao Ma <yuchaom@codeaurora.org>
* | Merge "drivers: Warning fixes to disable CC_OPTIMIZE_FOR_SIZE"Linux Build Service Account2017-06-07
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| * | drivers: Warning fixes to disable CC_OPTIMIZE_FOR_SIZEPrasad Sodagudi2017-05-31
| |/ | | | | | | | | | | | | | | | | | | These are all driver changes needed for disablement of CONFIG_CC_OPTIMIZE_FOR_SIZE. CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is enabled by default once CONFIG_CC_OPTIMIZE_FOR_SIZE is disabled. Change-Id: Ia46a1f24e8a082a29ea6151e41e6d3a85a05fd4f Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org> Signed-off-by: Sridhar Parasuram <sridhar@codeaurora.org>
* / clk: msm: clock-local2: Remove checks for display RCG re-configurationDeepak Katragadda2017-06-01
|/ | | | | | | | | | Allow re-configuring the DSI, DP and HDMI RCGs even if their current configuration matches that of the requested frequency. This is to work around the MM RCGs being latched to run off of XO by default after an MM GDSC power collapse. Change-Id: Idf5f1f25df6d6a8ef29eb8c15086deba1017584e Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* Merge remote-tracking branch 'remotes/quic/dev/msm-4.4-8996au' into msm-4.4Zhiqiang Tu2017-05-02
|\ | | | | | | | | | | | | | | | | Conflicts: arch/arm/boot/dts/qcom/msm8996-auto-cdp.dtsi drivers/gpu/drm/msm/Makefile Change-Id: Ief80c28ff1422fd71a0c3d2041531e2ab078ee7a Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
| * Merge remote-tracking branch 'remotes/origin/msm-4.4' into dev/msm-4.4-8996auArun KS2017-04-06
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/boot/dts/qcom/msm8996pro.dtsi arch/arm64/kernel/Makefile drivers/leds/leds-qpnp-flash.c sound/soc/msm/apq8096-auto.c Change-Id: Idea5d05fec354b8f38ea70643decb03f7b80ddb7 Signed-off-by: Arun KS <arunks@codeaurora.org>
| * \ Merge "clk: msm: clock: Add support for early boot frequency for MSM8996" ↵Linux Build Service Account2017-04-06
| |\ \ | | | | | | | | | | | | into dev/msm-4.4-8996au
| | * | clk: msm: clock: Add support for early boot frequency for MSM8996Odelu Kukatla2017-04-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Power and perf clusters early boot up frequencies require to be updated to maximum frequnecy of NOM voltage corner to improve the boot up time, so add support for the same. Change-Id: Icf54a648f47765867812edc5a68cf52b7fd58fdd Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
| * | | clk: msm: clock: Avoid turning off hmss_ahb_clk during certain LPM statesDeepak Katragadda2017-04-06
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock driver sets the sleep_ena bit to allow the hmss_ahb_clk to be disabled by hardware during certain low power modes. The PCIe controller however might need to access some registers that need this hmss_ahb_clk to be on. Remove the additional settings in the clock driver to resolve the issue. CRs-Fixed: 994609 Change-Id: Ib486a27f2e1c2d2231f8bedcb4ee8b39381cbd25 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
| * | Merge changes I63d7ce3e,I6fda5ed9 into dev/msm-4.4-8996auSrivatsa Vaddagiri2017-03-31
| |\ \ | | | | | | | | | | | | | | | | | | | | * changes: clk: msm: clock-cpu-8996: Allow interrupts during alt_pll set_rate clk: msm: clock-alpha-pll: Allow interrupts to be enabled during set_rate
| | * | clk: msm: clock-cpu-8996: Allow interrupts during alt_pll set_rateVikram Mulukutla2017-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU that is disabling the alternate PLL may also need to handle CPR interrupts. Allow the CPU to handle interrupts during the set_rate operation. CRs-Fixed: 960701 Change-Id: I63d7ce3e3dd2b559c4db383b64faa9335c404576 Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
| | * | clk: msm: clock-alpha-pll: Allow interrupts to be enabled during set_rateVikram Mulukutla2017-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some PLL implementations depend on the CPU being able to handle certain interrupts in order for the set_rate operation to complete. Allow interrupts to be handled in the set_rate op. CRs-Fixed: 960701 Change-Id: I6fda5ed9eb7d6f2e2cd91c58ebabfd7bc1c8a2fc Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
| * | | clk: msm: clock-gcc-8996: Add additional frequencies for QSPI clockDeepak Katragadda2017-03-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for additional frequencies for the qspi_ser_clk_src on msm8996. Change-Id: I4efa0ad4dc3f68a0c54bd4cf7ee77b4c78be4be1 CRs-Fixed: 994014 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
| * | | clk: msm: gcc-8996: Add pinctrl clk for ln_bb_clkDevesh Jhunjhunwala2017-03-28
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | Add the pinctrl clock for ln_bb_clk to the GCC driver for MSM8996. CRs-Fixed: 1063062 Change-Id: If85a0dbb26e350588cbd6614c032bf208a205be2 Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
* | | Merge "clk: msm: clock-mmss-8998: Set non_local_children flag for mdp_clk_src"Linux Build Service Account2017-04-21
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| * | | clk: msm: clock-mmss-8998: Set non_local_children flag for mdp_clk_srcAmit Nischal2017-04-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some use cases, mdp clock source needs to be parked at a safe frequency when it is disabled and force enabled in order to execute a safe dynamic switch. Add support for the same by adding non_local_children flag. Change-Id: Idcbaef90fdfcb80e93b00c61a91e5eadaabfbf56 Signed-off-by: Amit Nischal <anischal@codeaurora.org>
* | | | clk: msm: clock-local2: Fix get_rate ops for branch clockAmit Nischal2017-04-20
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | For branch clocks having aggr_sibling_rates flag as set, get_rate() always returns the parents rate despite the branch clocks prepare status. Fix the same by adding a check for branch prepare status and aggr_sibling_rates flag value. Change-Id: If0ba62e178f14bc5fd8ec6007a67538a9b97285b Signed-off-by: Amit Nischal <anischal@codeaurora.org>
* | | clk: mdss: adjust PLL disable sequence to avoid glitchAbhinav Kumar2017-04-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust the PLL disable sequence as per the latest HW programming guidelines to ensure there will not be any stray clock glitches when PLL is turned OFF abruptly. Change-Id: I6df35bbe18b0c42b43f38b9dd85c3502b2038928 Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
* | | clk: mdss: re-program PLL registers to power-on-reset valueAbhinav Kumar2017-04-05
| |/ |/| | | | | | | | | | | | | | | | | | | | | When the supply to PLL digital domain is turned off, it can result in certain PLL registers to get corrupted. Make sure to re-program the PLL registers to the power-on-reset value before starting to program the PLL again to ensure that it locks reliably. Change-Id: I63cac884cf11eae60b187f83654f5922a3342d66 Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
* | Merge "clk: msm: clock-gcc-8998: Update parent src for qup_spi/uart_apps clocks"Linux Build Service Account2017-04-04
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| * | clk: msm: clock-gcc-8998: Update parent src for qup_spi/uart_apps clocksAmit Nischal2017-03-21
| |/ | | | | | | | | | | | | | | | | The blsp qup_spi and uart_apps frequencies in the LOW_SVS corner needs to be derived from the gpll0_div2 source, so as to not result in under voting, so update the sources for the same. Change-Id: I2ab9ced70db0fdf2c8c93bce48ff4e97ec36125a Signed-off-by: Amit Nischal <anischal@codeaurora.org>
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