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-rw-r--r--drivers/platform/msm/Kconfig7
-rw-r--r--drivers/platform/msm/qpnp-coincell.c97
-rw-r--r--drivers/platform/msm/qpnp-haptic.c325
-rw-r--r--drivers/platform/msm/qpnp-power-on.c547
-rw-r--r--drivers/platform/msm/qpnp-revid.c63
5 files changed, 540 insertions, 499 deletions
diff --git a/drivers/platform/msm/Kconfig b/drivers/platform/msm/Kconfig
index 2f394f3fdcee..3d75cb1882d1 100644
--- a/drivers/platform/msm/Kconfig
+++ b/drivers/platform/msm/Kconfig
@@ -3,7 +3,7 @@ menu "Qualcomm MSM specific device drivers"
config QPNP_POWER_ON
tristate "QPNP PMIC POWER-ON Driver"
- depends on OF_SPMI && (SPMI || MSM_SPMI) && MSM_QPNP_INT && INPUT
+ depends on SPMI && INPUT
help
This driver supports the power-on functionality on Qualcomm
PNP PMIC. It currently supports reporting the change in status of
@@ -11,7 +11,7 @@ config QPNP_POWER_ON
config QPNP_REVID
tristate "QPNP Revision ID Peripheral"
- depends on SPMI || MSM_SPMI
+ depends on SPMI
help
Say 'y' here to include support for the Qualcomm QPNP REVID
peripheral. REVID prints out the PMIC type and revision numbers
@@ -20,7 +20,7 @@ config QPNP_REVID
config QPNP_COINCELL
tristate "Qualcomm QPNP coincell charger support"
- depends on (SPMI || MSM_SPMI) && OF_SPMI
+ depends on SPMI
help
This driver supports the QPNP coincell peripheral found inside of
Qualcomm QPNP PMIC devices. The coincell charger provides a means to
@@ -30,7 +30,6 @@ config QPNP_COINCELL
config QPNP_HAPTIC
tristate "Haptic support for QPNP PMIC"
- depends on OF_SPMI
help
This option enables device driver support for the Haptic
on the Qualcomm Technologies' QPNP PMICs. It uses the android
diff --git a/drivers/platform/msm/qpnp-coincell.c b/drivers/platform/msm/qpnp-coincell.c
index ec060bbc4171..6aaa53526868 100644
--- a/drivers/platform/msm/qpnp-coincell.c
+++ b/drivers/platform/msm/qpnp-coincell.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -13,9 +13,11 @@
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/kernel.h>
+#include <linux/regmap.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/spmi.h>
+#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
@@ -23,7 +25,8 @@
#define QPNP_COINCELL_DRIVER_NAME "qcom,qpnp-coincell"
struct qpnp_coincell {
- struct spmi_device *spmi_dev;
+ struct platform_device *pdev;
+ struct regmap *regmap;
u16 base_addr;
};
@@ -56,10 +59,11 @@ static int qpnp_coincell_set_resistance(struct qpnp_coincell *chip, int rset)
}
reg = i;
- rc = spmi_ext_register_writel(chip->spmi_dev->ctrl, chip->spmi_dev->sid,
- chip->base_addr + QPNP_COINCELL_REG_RSET, &reg, 1);
+ rc = regmap_write(chip->regmap,
+ chip->base_addr + QPNP_COINCELL_REG_RSET, reg);
if (rc)
- dev_err(&chip->spmi_dev->dev, "%s: could not write to RSET register, rc=%d\n",
+ dev_err(&chip->pdev->dev,
+ "%s: could not write to RSET register, rc=%d\n",
__func__, rc);
return rc;
@@ -80,10 +84,11 @@ static int qpnp_coincell_set_voltage(struct qpnp_coincell *chip, int vset)
}
reg = i;
- rc = spmi_ext_register_writel(chip->spmi_dev->ctrl, chip->spmi_dev->sid,
- chip->base_addr + QPNP_COINCELL_REG_VSET, &reg, 1);
+ rc = regmap_write(chip->regmap,
+ chip->base_addr + QPNP_COINCELL_REG_VSET, reg);
if (rc)
- dev_err(&chip->spmi_dev->dev, "%s: could not write to VSET register, rc=%d\n",
+ dev_err(&chip->pdev->dev,
+ "%s: could not write to VSET register, rc=%d\n",
__func__, rc);
return rc;
@@ -95,10 +100,11 @@ static int qpnp_coincell_set_charge(struct qpnp_coincell *chip, bool enabled)
u8 reg;
reg = enabled ? QPNP_COINCELL_ENABLE : QPNP_COINCELL_DISABLE;
- rc = spmi_ext_register_writel(chip->spmi_dev->ctrl, chip->spmi_dev->sid,
- chip->base_addr + QPNP_COINCELL_REG_ENABLE, &reg, 1);
+ rc = regmap_write(chip->regmap,
+ chip->base_addr + QPNP_COINCELL_REG_ENABLE, reg);
if (rc)
- dev_err(&chip->spmi_dev->dev, "%s: could not write to ENABLE register, rc=%d\n",
+ dev_err(&chip->pdev->dev,
+ "%s: could not write to ENABLE register, rc=%d\n",
__func__, rc);
return rc;
@@ -110,17 +116,20 @@ static void qpnp_coincell_charger_show_state(struct qpnp_coincell *chip)
bool enabled;
u8 reg[QPNP_COINCELL_REG_ENABLE - QPNP_COINCELL_REG_RSET + 1];
- rc = spmi_ext_register_readl(chip->spmi_dev->ctrl, chip->spmi_dev->sid,
- chip->base_addr + QPNP_COINCELL_REG_RSET, reg, ARRAY_SIZE(reg));
+ rc = regmap_bulk_read(chip->regmap,
+ chip->base_addr + QPNP_COINCELL_REG_RSET, reg,
+ ARRAY_SIZE(reg));
if (rc) {
- dev_err(&chip->spmi_dev->dev, "%s: could not read RSET register, rc=%d\n",
+ dev_err(&chip->pdev->dev,
+ "%s: could not read RSET register, rc=%d\n",
__func__, rc);
return;
}
temp = reg[QPNP_COINCELL_REG_RSET - QPNP_COINCELL_REG_RSET];
if (temp >= ARRAY_SIZE(qpnp_rset_map)) {
- dev_err(&chip->spmi_dev->dev, "unknown RSET=0x%02X register value\n",
+ dev_err(&chip->pdev->dev,
+ "unknown RSET=0x%02X register value\n",
temp);
return;
}
@@ -128,7 +137,8 @@ static void qpnp_coincell_charger_show_state(struct qpnp_coincell *chip)
temp = reg[QPNP_COINCELL_REG_VSET - QPNP_COINCELL_REG_RSET];
if (temp >= ARRAY_SIZE(qpnp_vset_map)) {
- dev_err(&chip->spmi_dev->dev, "unknown VSET=0x%02X register value\n",
+ dev_err(&chip->pdev->dev,
+ "unknown VSET=0x%02X register value\n",
temp);
return;
}
@@ -146,16 +156,19 @@ static int qpnp_coincell_check_type(struct qpnp_coincell *chip)
int rc;
u8 type[2];
- rc = spmi_ext_register_readl(chip->spmi_dev->ctrl, chip->spmi_dev->sid,
- chip->base_addr + QPNP_COINCELL_REG_TYPE, type, 2);
+ rc = regmap_bulk_read(chip->regmap,
+ chip->base_addr + QPNP_COINCELL_REG_TYPE, type,
+ 2);
if (rc) {
- dev_err(&chip->spmi_dev->dev, "%s: could not read type register, rc=%d\n",
+ dev_err(&chip->pdev->dev,
+ "%s: could not read type register, rc=%d\n",
__func__, rc);
return rc;
}
if (type[0] != QPNP_COINCELL_TYPE || type[1] != QPNP_COINCELL_SUBTYPE) {
- dev_err(&chip->spmi_dev->dev, "%s: invalid type=0x%02X or subtype=0x%02X register value\n",
+ dev_err(&chip->pdev->dev,
+ "%s: invalid type=0x%02X or subtype=0x%02X register value\n",
__func__, type[0], type[1]);
return -ENODEV;
}
@@ -163,34 +176,38 @@ static int qpnp_coincell_check_type(struct qpnp_coincell *chip)
return rc;
}
-static int qpnp_coincell_probe(struct spmi_device *spmi)
+static int qpnp_coincell_probe(struct platform_device *pdev)
{
- struct device_node *node = spmi->dev.of_node;
+ struct device_node *node = pdev->dev.of_node;
struct qpnp_coincell *chip;
- struct resource *res;
+ unsigned int base;
u32 temp;
int rc = 0;
if (!node) {
- dev_err(&spmi->dev, "%s: device node missing\n", __func__);
+ dev_err(&pdev->dev, "%s: device node missing\n", __func__);
return -ENODEV;
}
- chip = devm_kzalloc(&spmi->dev, sizeof(*chip), GFP_KERNEL);
- if (!chip) {
- dev_err(&spmi->dev, "%s: cannot allocate qpnp_coincell\n",
- __func__);
+ chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
+ if (!chip)
return -ENOMEM;
- }
- chip->spmi_dev = spmi;
- res = spmi_get_resource(spmi, NULL, IORESOURCE_MEM, 0);
- if (!res) {
- dev_err(&spmi->dev, "%s: node is missing base address\n",
- __func__);
+ chip->regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ if (!chip->regmap) {
+ dev_err(&pdev->dev, "Couldn't get parent's regmap\n");
return -EINVAL;
}
- chip->base_addr = res->start;
+ chip->pdev = pdev;
+
+ rc = of_property_read_u32(pdev->dev.of_node, "reg", &base);
+ if (rc < 0) {
+ dev_err(&pdev->dev,
+ "Couldn't find reg in node = %s rc = %d\n",
+ pdev->dev.of_node->full_name, rc);
+ return rc;
+ }
+ chip->base_addr = base;
rc = qpnp_coincell_check_type(chip);
if (rc)
@@ -222,7 +239,7 @@ static int qpnp_coincell_probe(struct spmi_device *spmi)
return 0;
}
-static int qpnp_coincell_remove(struct spmi_device *spmi)
+static int qpnp_coincell_remove(struct platform_device *pdev)
{
return 0;
}
@@ -232,13 +249,13 @@ static struct of_device_id qpnp_coincell_match_table[] = {
{}
};
-static const struct spmi_device_id qpnp_coincell_id[] = {
+static const struct platform_device_id qpnp_coincell_id[] = {
{ QPNP_COINCELL_DRIVER_NAME, 0 },
{}
};
MODULE_DEVICE_TABLE(spmi, qpnp_coincell_id);
-static struct spmi_driver qpnp_coincell_driver = {
+static struct platform_driver qpnp_coincell_driver = {
.driver = {
.name = QPNP_COINCELL_DRIVER_NAME,
.of_match_table = qpnp_coincell_match_table,
@@ -251,12 +268,12 @@ static struct spmi_driver qpnp_coincell_driver = {
static int __init qpnp_coincell_init(void)
{
- return spmi_driver_register(&qpnp_coincell_driver);
+ return platform_driver_register(&qpnp_coincell_driver);
}
static void __exit qpnp_coincell_exit(void)
{
- spmi_driver_unregister(&qpnp_coincell_driver);
+ platform_driver_unregister(&qpnp_coincell_driver);
}
MODULE_DESCRIPTION("QPNP PMIC coincell charger driver");
diff --git a/drivers/platform/msm/qpnp-haptic.c b/drivers/platform/msm/qpnp-haptic.c
index 45be1b11a2c2..54638c5a883c 100644
--- a/drivers/platform/msm/qpnp-haptic.c
+++ b/drivers/platform/msm/qpnp-haptic.c
@@ -13,11 +13,13 @@
#include <linux/module.h>
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/regmap.h>
#include <linux/errno.h>
#include <linux/slab.h>
#include <linux/hrtimer.h>
#include <linux/of_device.h>
#include <linux/spmi.h>
+#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/interrupt.h>
#include <linux/qpnp/pwm.h>
@@ -280,56 +282,57 @@ struct qpnp_pwm_info {
* @ misc_trim_error_rc19p2_clk_reg_present - if MISC Trim Error reg is present
*/
struct qpnp_hap {
- struct spmi_device *spmi;
- struct regulator *vcc_pon;
- struct hrtimer hap_timer;
- struct hrtimer auto_res_err_poll_timer;
- struct timed_output_dev timed_dev;
- struct work_struct work;
- struct work_struct auto_res_err_work;
- struct delayed_work sc_work;
- struct hrtimer hap_test_timer;
- struct work_struct test_work;
- struct qpnp_pwm_info pwm_info;
- struct mutex lock;
- struct mutex wf_lock;
- struct completion completion;
- enum qpnp_hap_mode play_mode;
- enum qpnp_hap_auto_res_mode auto_res_mode;
- enum qpnp_hap_high_z lra_high_z;
- u32 timeout_ms;
- u32 vmax_mv;
- u32 ilim_ma;
- u32 sc_deb_cycles;
- u32 int_pwm_freq_khz;
- u32 wave_play_rate_us;
- u32 ext_pwm_freq_khz;
- u32 wave_rep_cnt;
- u32 wave_s_rep_cnt;
- u32 play_irq;
- u32 sc_irq;
- u16 base;
- u8 act_type;
- u8 wave_shape;
+ struct platform_device *pdev;
+ struct regmap *regmap;
+ struct regulator *vcc_pon;
+ struct hrtimer hap_timer;
+ struct hrtimer auto_res_err_poll_timer;
+ struct timed_output_dev timed_dev;
+ struct work_struct work;
+ struct work_struct auto_res_err_work;
+ struct delayed_work sc_work;
+ struct hrtimer hap_test_timer;
+ struct work_struct test_work;
+ struct qpnp_pwm_info pwm_info;
+ struct mutex lock;
+ struct mutex wf_lock;
+ struct completion completion;
+ enum qpnp_hap_mode play_mode;
+ enum qpnp_hap_auto_res_mode auto_res_mode;
+ enum qpnp_hap_high_z lra_high_z;
+ u32 timeout_ms;
+ u32 vmax_mv;
+ u32 ilim_ma;
+ u32 sc_deb_cycles;
+ u32 int_pwm_freq_khz;
+ u32 wave_play_rate_us;
+ u32 ext_pwm_freq_khz;
+ u32 wave_rep_cnt;
+ u32 wave_s_rep_cnt;
+ u32 play_irq;
+ u32 sc_irq;
+ u16 base;
+ u8 act_type;
+ u8 wave_shape;
u8 wave_samp[QPNP_HAP_WAV_SAMP_LEN];
u8 shadow_wave_samp[QPNP_HAP_WAV_SAMP_LEN];
u8 brake_pat[QPNP_HAP_BRAKE_PAT_LEN];
- u8 reg_en_ctl;
- u8 reg_play;
- u8 lra_res_cal_period;
- u8 sc_duration;
- u8 ext_pwm_dtest_line;
- bool state;
- bool use_play_irq;
- bool use_sc_irq;
- bool manage_pon_supply;
- bool wf_update;
- bool pwm_cfg_state;
- bool buffer_cfg_state;
- bool en_brake;
- bool sup_brake_pat;
- bool correct_lra_drive_freq;
- bool misc_trim_error_rc19p2_clk_reg_present;
+ u8 reg_en_ctl;
+ u8 reg_play;
+ u8 lra_res_cal_period;
+ u8 sc_duration;
+ u8 ext_pwm_dtest_line;
+ bool state;
+ bool use_play_irq;
+ bool use_sc_irq;
+ bool manage_pon_supply;
+ bool wf_update;
+ bool pwm_cfg_state;
+ bool buffer_cfg_state;
+ bool en_brake;
+ bool sup_brake_pat;
+ bool correct_lra_drive_freq;
+ bool misc_trim_error_rc19p2_clk_reg_present;
};
static struct qpnp_hap *ghap;
@@ -338,13 +341,13 @@ static struct qpnp_hap *ghap;
static int qpnp_hap_read_reg(struct qpnp_hap *hap, u8 *data, u16 addr)
{
int rc;
+ uint val;
- rc = spmi_ext_register_readl(hap->spmi->ctrl, hap->spmi->sid,
- addr, data, 1);
+ rc = regmap_read(hap->regmap, addr, &val);
if (rc < 0)
- dev_err(&hap->spmi->dev,
+ dev_err(&hap->pdev->dev,
"Error reading address: %X - ret %X\n", addr, rc);
-
+ *data = (u8)val;
return rc;
}
@@ -353,13 +356,12 @@ static int qpnp_hap_write_reg(struct qpnp_hap *hap, u8 *data, u16 addr)
{
int rc;
- rc = spmi_ext_register_writel(hap->spmi->ctrl, hap->spmi->sid,
- addr, data, 1);
+ rc = regmap_write(hap->regmap, addr, *data);
if (rc < 0)
- dev_err(&hap->spmi->dev,
+ dev_err(&hap->pdev->dev,
"Error writing address: %X - ret %X\n", addr, rc);
- dev_dbg(&hap->spmi->dev, "write: HAP_0x%x = 0x%x\n", addr, *data);
+ dev_dbg(&hap->pdev->dev, "write: HAP_0x%x = 0x%x\n", addr, *data);
return rc;
}
@@ -410,7 +412,7 @@ static int qpnp_hap_mod_enable(struct qpnp_hap *hap, int on)
rc = qpnp_hap_read_reg(hap, &val,
QPNP_HAP_STATUS(hap->base));
- dev_dbg(&hap->spmi->dev, "HAP_STATUS=0x%x\n", val);
+ dev_dbg(&hap->pdev->dev, "HAP_STATUS=0x%x\n", val);
/* wait for QPNP_HAP_CYCLS cycles of play rate */
if (val & QPNP_HAP_STATUS_BUSY) {
@@ -423,7 +425,7 @@ static int qpnp_hap_mod_enable(struct qpnp_hap *hap, int on)
}
if (i >= QPNP_HAP_MAX_RETRIES)
- dev_dbg(&hap->spmi->dev,
+ dev_dbg(&hap->pdev->dev,
"Haptics Busy. Force disable\n");
val &= ~QPNP_HAP_EN;
@@ -517,7 +519,7 @@ static irqreturn_t qpnp_hap_sc_irq(int irq, void *_hap)
u8 disable_haptics = 0x00;
u8 val;
- dev_dbg(&hap->spmi->dev, "Short circuit detected\n");
+ dev_dbg(&hap->pdev->dev, "Short circuit detected\n");
if (hap->sc_duration < SC_MAX_DURATION) {
qpnp_hap_read_reg(hap, &val, QPNP_HAP_STATUS(hap->base));
@@ -532,7 +534,7 @@ static irqreturn_t qpnp_hap_sc_irq(int irq, void *_hap)
*/
rc = qpnp_hap_write_reg(hap, &disable_haptics,
QPNP_HAP_EN_CTL_REG(hap->base));
- dev_err(&hap->spmi->dev,
+ dev_err(&hap->pdev->dev,
"Haptics disabled permanently due to short circuit\n");
}
@@ -582,12 +584,12 @@ static int qpnp_hap_buffer_config(struct qpnp_hap *hap)
/* setup play irq */
if (hap->use_play_irq) {
- rc = devm_request_threaded_irq(&hap->spmi->dev, hap->play_irq,
+ rc = devm_request_threaded_irq(&hap->pdev->dev, hap->play_irq,
NULL, qpnp_hap_play_irq,
QPNP_IRQ_FLAGS,
"qpnp_play_irq", hap);
if (rc < 0) {
- dev_err(&hap->spmi->dev,
+ dev_err(&hap->pdev->dev,
"Unable to request play(%d) IRQ(err:%d)\n",
hap->play_irq, rc);
return rc;
@@ -638,7 +640,7 @@ static int qpnp_hap_pwm_config(struct qpnp_hap *hap)
return rc;
if (!hap->ext_pwm_dtest_line ||
hap->ext_pwm_dtest_line > PWM_MAX_DTEST_LINES) {
- dev_err(&hap->spmi->dev, "invalid dtest line\n");
+ dev_err(&hap->pdev->dev, "invalid dtest line\n");
return -EINVAL;
}
@@ -661,7 +663,7 @@ static int qpnp_hap_pwm_config(struct qpnp_hap *hap)
hap->pwm_info.duty_us * NSEC_PER_USEC,
hap->pwm_info.period_us * NSEC_PER_USEC);
if (rc < 0) {
- dev_err(&hap->spmi->dev, "hap pwm config failed\n");
+ dev_err(&hap->pdev->dev, "hap pwm config failed\n");
pwm_free(hap->pwm_info.pwm_dev);
return -ENODEV;
}
@@ -742,48 +744,47 @@ static int qpnp_hap_sc_deb_config(struct qpnp_hap *hap)
/* DT parsing api for buffer mode */
static int qpnp_hap_parse_buffer_dt(struct qpnp_hap *hap)
{
- struct spmi_device *spmi = hap->spmi;
+ struct platform_device *pdev = hap->pdev;
struct property *prop;
u32 temp;
int rc, i;
hap->wave_rep_cnt = QPNP_HAP_WAV_REP_MIN;
- rc = of_property_read_u32(spmi->dev.of_node,
+ rc = of_property_read_u32(pdev->dev.of_node,
"qcom,wave-rep-cnt", &temp);
if (!rc) {
hap->wave_rep_cnt = temp;
} else if (rc != -EINVAL) {
- dev_err(&spmi->dev, "Unable to read rep cnt\n");
+ dev_err(&pdev->dev, "Unable to read rep cnt\n");
return rc;
}
hap->wave_s_rep_cnt = QPNP_HAP_WAV_S_REP_MIN;
- rc = of_property_read_u32(spmi->dev.of_node,
+ rc = of_property_read_u32(pdev->dev.of_node,
"qcom,wave-samp-rep-cnt", &temp);
if (!rc) {
hap->wave_s_rep_cnt = temp;
} else if (rc != -EINVAL) {
- dev_err(&spmi->dev, "Unable to read samp rep cnt\n");
+ dev_err(&pdev->dev, "Unable to read samp rep cnt\n");
return rc;
}
- prop = of_find_property(spmi->dev.of_node,
+ prop = of_find_property(pdev->dev.of_node,
"qcom,wave-samples", &temp);
if (!prop || temp != QPNP_HAP_WAV_SAMP_LEN) {
- dev_err(&spmi->dev, "Invalid wave samples, use default");
+ dev_err(&pdev->dev, "Invalid wave samples, use default");
for (i = 0; i < QPNP_HAP_WAV_SAMP_LEN; i++)
hap->wave_samp[i] = QPNP_HAP_WAV_SAMP_MAX;
} else {
memcpy(hap->wave_samp, prop->value, QPNP_HAP_WAV_SAMP_LEN);
}
- hap->use_play_irq = of_property_read_bool(spmi->dev.of_node,
+ hap->use_play_irq = of_property_read_bool(pdev->dev.of_node,
"qcom,use-play-irq");
if (hap->use_play_irq) {
- hap->play_irq = spmi_get_irq_byname(hap->spmi,
- NULL, "play-irq");
+ hap->play_irq = platform_get_irq_byname(hap->pdev, "play-irq");
if (hap->play_irq < 0) {
- dev_err(&spmi->dev, "Unable to get play irq\n");
+ dev_err(&pdev->dev, "Unable to get play irq\n");
return hap->play_irq;
}
}
@@ -794,51 +795,49 @@ static int qpnp_hap_parse_buffer_dt(struct qpnp_hap *hap)
/* DT parsing api for PWM mode */
static int qpnp_hap_parse_pwm_dt(struct qpnp_hap *hap)
{
- struct spmi_device *spmi = hap->spmi;
+ struct platform_device *pdev = hap->pdev;
u32 temp;
int rc;
hap->ext_pwm_freq_khz = QPNP_HAP_EXT_PWM_FREQ_25_KHZ;
- rc = of_property_read_u32(spmi->dev.of_node,
+ rc = of_property_read_u32(pdev->dev.of_node,
"qcom,ext-pwm-freq-khz", &temp);
if (!rc) {
hap->ext_pwm_freq_khz = temp;
} else if (rc != -EINVAL) {
- dev_err(&spmi->dev, "Unable to read ext pwm freq\n");
+ dev_err(&pdev->dev, "Unable to read ext pwm freq\n");
return rc;
}
- rc = of_property_read_u32(spmi->dev.of_node,
+ rc = of_property_read_u32(pdev->dev.of_node,
"qcom,pwm-channel", &temp);
if (!rc)
hap->pwm_info.pwm_channel = temp;
else
return rc;
- hap->pwm_info.pwm_dev = of_pwm_get(spmi->dev.of_node, NULL);
+ hap->pwm_info.pwm_dev = of_pwm_get(pdev->dev.of_node, NULL);
if (IS_ERR(hap->pwm_info.pwm_dev)) {
rc = PTR_ERR(hap->pwm_info.pwm_dev);
- dev_err(&spmi->dev, "Cannot get PWM device rc:(%d)\n", rc);
+ dev_err(&pdev->dev, "Cannot get PWM device rc:(%d)\n", rc);
hap->pwm_info.pwm_dev = NULL;
return rc;
}
- rc = of_property_read_u32(spmi->dev.of_node,
- "qcom,period-us", &temp);
+ rc = of_property_read_u32(pdev->dev.of_node, "qcom,period-us", &temp);
if (!rc)
hap->pwm_info.period_us = temp;
else
return rc;
- rc = of_property_read_u32(spmi->dev.of_node,
- "qcom,duty-us", &temp);
+ rc = of_property_read_u32(pdev->dev.of_node, "qcom,duty-us", &temp);
if (!rc)
hap->pwm_info.duty_us = temp;
else
return rc;
- rc = of_property_read_u32(spmi->dev.of_node,
+ rc = of_property_read_u32(pdev->dev.of_node,
"qcom,ext-pwm-dtest-line", &temp);
if (!rc)
hap->ext_pwm_dtest_line = temp;
@@ -1587,7 +1586,7 @@ int qpnp_hap_play_byte(u8 data, bool on)
}
if (hap->play_mode != QPNP_HAP_PWM) {
- dev_err(&hap->spmi->dev, "only PWM mode is supported\n");
+ dev_err(&hap->pdev->dev, "only PWM mode is supported\n");
return -EINVAL;
}
@@ -1624,7 +1623,8 @@ int qpnp_hap_play_byte(u8 data, bool on)
if (rc)
return rc;
- dev_dbg(&hap->spmi->dev, "data=0x%x duty_per=%d\n", data, duty_percent);
+ dev_dbg(&hap->pdev->dev, "data=0x%x duty_per=%d\n", data,
+ duty_percent);
rc = qpnp_hap_set(hap, true);
@@ -1723,8 +1723,9 @@ static SIMPLE_DEV_PM_OPS(qpnp_haptic_pm_ops, qpnp_haptic_suspend, NULL);
/* Configuration api for haptics registers */
static int qpnp_hap_config(struct qpnp_hap *hap)
{
- u8 reg = 0, error_code = 0, unlock_val, error_value;
+ u8 reg = 0, unlock_val, error_value;
int rc, i, temp;
+ uint error_code = 0;
/* Configure the ACTUATOR TYPE register */
rc = qpnp_hap_read_reg(hap, &reg, QPNP_HAP_ACT_TYPE_REG(hap->base));
@@ -1862,15 +1863,13 @@ static int qpnp_hap_config(struct qpnp_hap *hap)
if ((hap->act_type == QPNP_HAP_LRA) && hap->correct_lra_drive_freq
&& hap->misc_trim_error_rc19p2_clk_reg_present) {
unlock_val = MISC_SEC_UNLOCK;
- rc = spmi_ext_register_writel(hap->spmi->ctrl,
- PMI8950_MISC_SID, MISC_SEC_ACCESS,
- &unlock_val, 1);
+ rc = regmap_write(hap->regmap, MISC_SEC_ACCESS, unlock_val);
if (rc)
- dev_err(&hap->spmi->dev,
+ dev_err(&hap->pdev->dev,
"Unable to do SEC_ACCESS rc:%d\n", rc);
- spmi_ext_register_readl(hap->spmi->ctrl, PMI8950_MISC_SID,
- MISC_TRIM_ERROR_RC19P2_CLK, &error_code, 1);
+ regmap_read(hap->regmap, MISC_TRIM_ERROR_RC19P2_CLK,
+ &error_code);
error_value = (error_code & 0x0F) * 7;
@@ -1947,12 +1946,12 @@ static int qpnp_hap_config(struct qpnp_hap *hap)
/* setup short circuit irq */
if (hap->use_sc_irq) {
- rc = devm_request_threaded_irq(&hap->spmi->dev, hap->sc_irq,
+ rc = devm_request_threaded_irq(&hap->pdev->dev, hap->sc_irq,
NULL, qpnp_hap_sc_irq,
QPNP_IRQ_FLAGS,
"qpnp_sc_irq", hap);
if (rc < 0) {
- dev_err(&hap->spmi->dev,
+ dev_err(&hap->pdev->dev,
"Unable to request sc(%d) IRQ(err:%d)\n",
hap->sc_irq, rc);
return rc;
@@ -1967,24 +1966,24 @@ static int qpnp_hap_config(struct qpnp_hap *hap)
/* DT parsing for haptics parameters */
static int qpnp_hap_parse_dt(struct qpnp_hap *hap)
{
- struct spmi_device *spmi = hap->spmi;
+ struct platform_device *pdev = hap->pdev;
struct property *prop;
const char *temp_str;
u32 temp;
int rc;
hap->timeout_ms = QPNP_HAP_TIMEOUT_MS_MAX;
- rc = of_property_read_u32(spmi->dev.of_node,
+ rc = of_property_read_u32(pdev->dev.of_node,
"qcom,timeout-ms", &temp);
if (!rc) {
hap->timeout_ms = temp;
} else if (rc != -EINVAL) {
- dev_err(&spmi->dev, "Unable to read timeout\n");
+ dev_err(&pdev->dev, "Unable to read timeout\n");
return rc;
}
hap->act_type = QPNP_HAP_LRA;
- rc = of_property_read_string(spmi->dev.of_node,
+ rc = of_property_read_string(pdev->dev.of_node,
"qcom,actuator-type", &temp_str);
if (!rc) {
if (strcmp(temp_str, "erm") == 0)
@@ -1992,17 +1991,17 @@ static int qpnp_hap_parse_dt(struct qpnp_hap *hap)
else if (strcmp(temp_str, "lra") == 0)
hap->act_type = QPNP_HAP_LRA;
else {
- dev_err(&spmi->dev, "Invalid actuator type\n");
+ dev_err(&pdev->dev, "Invalid actuator type\n");
return -EINVAL;
}
} else if (rc != -EINVAL) {
- dev_err(&spmi->dev, "Unable to read actuator type\n");
+ dev_err(&pdev->dev, "Unable to read actuator type\n");
return rc;
}
if (hap->act_type == QPNP_HAP_LRA) {
hap->auto_res_mode = QPNP_HAP_AUTO_RES_ZXD_EOP;
- rc = of_property_read_string(spmi->dev.of_node,
+ rc = of_property_read_string(pdev->dev.of_node,
"qcom,lra-auto-res-mode", &temp_str);
if (!rc) {
if (strcmp(temp_str, "none") == 0)
@@ -2016,12 +2015,12 @@ static int qpnp_hap_parse_dt(struct qpnp_hap *hap)
else
hap->auto_res_mode = QPNP_HAP_AUTO_RES_ZXD_EOP;
} else if (rc != -EINVAL) {
- dev_err(&spmi->dev, "Unable to read auto res mode\n");
+ dev_err(&pdev->dev, "Unable to read auto res mode\n");
return rc;
}
hap->lra_high_z = QPNP_HAP_LRA_HIGH_Z_OPT3;
- rc = of_property_read_string(spmi->dev.of_node,
+ rc = of_property_read_string(pdev->dev.of_node,
"qcom,lra-high-z", &temp_str);
if (!rc) {
if (strcmp(temp_str, "none") == 0)
@@ -2033,30 +2032,30 @@ static int qpnp_hap_parse_dt(struct qpnp_hap *hap)
else
hap->lra_high_z = QPNP_HAP_LRA_HIGH_Z_OPT3;
} else if (rc != -EINVAL) {
- dev_err(&spmi->dev, "Unable to read LRA high-z\n");
+ dev_err(&pdev->dev, "Unable to read LRA high-z\n");
return rc;
}
hap->lra_res_cal_period = QPNP_HAP_RES_CAL_PERIOD_MAX;
- rc = of_property_read_u32(spmi->dev.of_node,
+ rc = of_property_read_u32(pdev->dev.of_node,
"qcom,lra-res-cal-period", &temp);
if (!rc) {
hap->lra_res_cal_period = temp;
} else if (rc != -EINVAL) {
- dev_err(&spmi->dev, "Unable to read cal period\n");
+ dev_err(&pdev->dev, "Unable to read cal period\n");
return rc;
}
hap->correct_lra_drive_freq =
- of_property_read_bool(spmi->dev.of_node,
+ of_property_read_bool(pdev->dev.of_node,
"qcom,correct-lra-drive-freq");
hap->misc_trim_error_rc19p2_clk_reg_present =
- of_property_read_bool(spmi->dev.of_node,
+ of_property_read_bool(pdev->dev.of_node,
"qcom,misc-trim-error-rc19p2-clk-reg-present");
}
- rc = of_property_read_string(spmi->dev.of_node,
+ rc = of_property_read_string(pdev->dev.of_node,
"qcom,play-mode", &temp_str);
if (!rc) {
if (strcmp(temp_str, "direct") == 0)
@@ -2068,56 +2067,54 @@ static int qpnp_hap_parse_dt(struct qpnp_hap *hap)
else if (strcmp(temp_str, "audio") == 0)
hap->play_mode = QPNP_HAP_AUDIO;
else {
- dev_err(&spmi->dev, "Invalid play mode\n");
+ dev_err(&pdev->dev, "Invalid play mode\n");
return -EINVAL;
}
} else {
- dev_err(&spmi->dev, "Unable to read play mode\n");
+ dev_err(&pdev->dev, "Unable to read play mode\n");
return rc;
}
hap->vmax_mv = QPNP_HAP_VMAX_MAX_MV;
- rc = of_property_read_u32(spmi->dev.of_node,
- "qcom,vmax-mv", &temp);
+ rc = of_property_read_u32(pdev->dev.of_node, "qcom,vmax-mv", &temp);
if (!rc) {
hap->vmax_mv = temp;
} else if (rc != -EINVAL) {
- dev_err(&spmi->dev, "Unable to read vmax\n");
+ dev_err(&pdev->dev, "Unable to read vmax\n");
return rc;
}
hap->ilim_ma = QPNP_HAP_ILIM_MIN_MV;
- rc = of_property_read_u32(spmi->dev.of_node,
- "qcom,ilim-ma", &temp);
+ rc = of_property_read_u32(pdev->dev.of_node, "qcom,ilim-ma", &temp);
if (!rc) {
hap->ilim_ma = temp;
} else if (rc != -EINVAL) {
- dev_err(&spmi->dev, "Unable to read ILim\n");
+ dev_err(&pdev->dev, "Unable to read ILim\n");
return rc;
}
hap->sc_deb_cycles = QPNP_HAP_DEF_SC_DEB_CYCLES;
- rc = of_property_read_u32(spmi->dev.of_node,
+ rc = of_property_read_u32(pdev->dev.of_node,
"qcom,sc-deb-cycles", &temp);
if (!rc) {
hap->sc_deb_cycles = temp;
} else if (rc != -EINVAL) {
- dev_err(&spmi->dev, "Unable to read sc debounce\n");
+ dev_err(&pdev->dev, "Unable to read sc debounce\n");
return rc;
}
hap->int_pwm_freq_khz = QPNP_HAP_INT_PWM_FREQ_505_KHZ;
- rc = of_property_read_u32(spmi->dev.of_node,
+ rc = of_property_read_u32(pdev->dev.of_node,
"qcom,int-pwm-freq-khz", &temp);
if (!rc) {
hap->int_pwm_freq_khz = temp;
} else if (rc != -EINVAL) {
- dev_err(&spmi->dev, "Unable to read int pwm freq\n");
+ dev_err(&pdev->dev, "Unable to read int pwm freq\n");
return rc;
}
hap->wave_shape = QPNP_HAP_WAV_SQUARE;
- rc = of_property_read_string(spmi->dev.of_node,
+ rc = of_property_read_string(pdev->dev.of_node,
"qcom,wave-shape", &temp_str);
if (!rc) {
if (strcmp(temp_str, "sine") == 0)
@@ -2125,21 +2122,21 @@ static int qpnp_hap_parse_dt(struct qpnp_hap *hap)
else if (strcmp(temp_str, "square") == 0)
hap->wave_shape = QPNP_HAP_WAV_SQUARE;
else {
- dev_err(&spmi->dev, "Unsupported wav shape\n");
+ dev_err(&pdev->dev, "Unsupported wav shape\n");
return -EINVAL;
}
} else if (rc != -EINVAL) {
- dev_err(&spmi->dev, "Unable to read wav shape\n");
+ dev_err(&pdev->dev, "Unable to read wav shape\n");
return rc;
}
hap->wave_play_rate_us = QPNP_HAP_DEF_WAVE_PLAY_RATE_US;
- rc = of_property_read_u32(spmi->dev.of_node,
+ rc = of_property_read_u32(pdev->dev.of_node,
"qcom,wave-play-rate-us", &temp);
if (!rc) {
hap->wave_play_rate_us = temp;
} else if (rc != -EINVAL) {
- dev_err(&spmi->dev, "Unable to read play rate\n");
+ dev_err(&pdev->dev, "Unable to read play rate\n");
return rc;
}
@@ -2151,16 +2148,16 @@ static int qpnp_hap_parse_dt(struct qpnp_hap *hap)
if (rc < 0)
return rc;
- hap->en_brake = of_property_read_bool(spmi->dev.of_node,
+ hap->en_brake = of_property_read_bool(pdev->dev.of_node,
"qcom,en-brake");
if (hap->en_brake) {
- prop = of_find_property(spmi->dev.of_node,
+ prop = of_find_property(pdev->dev.of_node,
"qcom,brake-pattern", &temp);
if (!prop) {
- dev_info(&spmi->dev, "brake pattern not found");
+ dev_info(&pdev->dev, "brake pattern not found");
} else if (temp != QPNP_HAP_BRAKE_PAT_LEN) {
- dev_err(&spmi->dev, "Invalid len of brake pattern\n");
+ dev_err(&pdev->dev, "Invalid len of brake pattern\n");
return -EINVAL;
} else {
hap->sup_brake_pat = true;
@@ -2169,54 +2166,60 @@ static int qpnp_hap_parse_dt(struct qpnp_hap *hap)
}
}
- hap->use_sc_irq = of_property_read_bool(spmi->dev.of_node,
+ hap->use_sc_irq = of_property_read_bool(pdev->dev.of_node,
"qcom,use-sc-irq");
if (hap->use_sc_irq) {
- hap->sc_irq = spmi_get_irq_byname(hap->spmi,
- NULL, "sc-irq");
+ hap->sc_irq = platform_get_irq_byname(hap->pdev, "sc-irq");
if (hap->sc_irq < 0) {
- dev_err(&spmi->dev, "Unable to get sc irq\n");
+ dev_err(&pdev->dev, "Unable to get sc irq\n");
return hap->sc_irq;
}
}
- if (of_find_property(spmi->dev.of_node, "vcc_pon-supply", NULL))
+ if (of_find_property(pdev->dev.of_node, "vcc_pon-supply", NULL))
hap->manage_pon_supply = true;
return 0;
}
-static int qpnp_haptic_probe(struct spmi_device *spmi)
+static int qpnp_haptic_probe(struct platform_device *pdev)
{
struct qpnp_hap *hap;
- struct resource *hap_resource;
+ unsigned int base;
struct regulator *vcc_pon;
int rc, i;
- hap = devm_kzalloc(&spmi->dev, sizeof(*hap), GFP_KERNEL);
+ hap = devm_kzalloc(&pdev->dev, sizeof(*hap), GFP_KERNEL);
if (!hap)
return -ENOMEM;
+ hap->regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ if (!hap->regmap) {
+ dev_err(&pdev->dev, "Couldn't get parent's regmap\n");
+ return -EINVAL;
+ }
- hap->spmi = spmi;
+ hap->pdev = pdev;
- hap_resource = spmi_get_resource(spmi, 0, IORESOURCE_MEM, 0);
- if (!hap_resource) {
- dev_err(&spmi->dev, "Unable to get haptic base address\n");
- return -EINVAL;
+ rc = of_property_read_u32(pdev->dev.of_node, "reg", &base);
+ if (rc < 0) {
+ dev_err(&pdev->dev,
+ "Couldn't find reg in node = %s rc = %d\n",
+ pdev->dev.of_node->full_name, rc);
+ return rc;
}
- hap->base = hap_resource->start;
+ hap->base = base;
- dev_set_drvdata(&spmi->dev, hap);
+ dev_set_drvdata(&pdev->dev, hap);
rc = qpnp_hap_parse_dt(hap);
if (rc) {
- dev_err(&spmi->dev, "DT parsing failed\n");
+ dev_err(&pdev->dev, "DT parsing failed\n");
return rc;
}
rc = qpnp_hap_config(hap);
if (rc) {
- dev_err(&spmi->dev, "hap config failed\n");
+ dev_err(&pdev->dev, "hap config failed\n");
return rc;
}
@@ -2245,7 +2248,7 @@ static int qpnp_haptic_probe(struct spmi_device *spmi)
rc = timed_output_dev_register(&hap->timed_dev);
if (rc < 0) {
- dev_err(&spmi->dev, "timed_output registration failed\n");
+ dev_err(&pdev->dev, "timed_output registration failed\n");
goto timed_output_fail;
}
@@ -2253,16 +2256,16 @@ static int qpnp_haptic_probe(struct spmi_device *spmi)
rc = sysfs_create_file(&hap->timed_dev.dev->kobj,
&qpnp_hap_attrs[i].attr);
if (rc < 0) {
- dev_err(&spmi->dev, "sysfs creation failed\n");
+ dev_err(&pdev->dev, "sysfs creation failed\n");
goto sysfs_fail;
}
}
if (hap->manage_pon_supply) {
- vcc_pon = regulator_get(&spmi->dev, "vcc_pon");
+ vcc_pon = regulator_get(&pdev->dev, "vcc_pon");
if (IS_ERR(vcc_pon)) {
rc = PTR_ERR(vcc_pon);
- dev_err(&spmi->dev,
+ dev_err(&pdev->dev,
"regulator get failed vcc_pon rc=%d\n", rc);
goto sysfs_fail;
}
@@ -2289,9 +2292,9 @@ timed_output_fail:
return rc;
}
-static int qpnp_haptic_remove(struct spmi_device *spmi)
+static int qpnp_haptic_remove(struct platform_device *pdev)
{
- struct qpnp_hap *hap = dev_get_drvdata(&spmi->dev);
+ struct qpnp_hap *hap = dev_get_drvdata(&pdev->dev);
int i;
for (i = 0; i < ARRAY_SIZE(qpnp_hap_attrs); i++)
@@ -2316,11 +2319,11 @@ static struct of_device_id spmi_match_table[] = {
{ },
};
-static struct spmi_driver qpnp_haptic_driver = {
+static struct platform_driver qpnp_haptic_driver = {
.driver = {
- .name = "qcom,qpnp-haptic",
- .of_match_table = spmi_match_table,
- .pm = &qpnp_haptic_pm_ops,
+ .name = "qcom,qpnp-haptic",
+ .of_match_table = spmi_match_table,
+ .pm = &qpnp_haptic_pm_ops,
},
.probe = qpnp_haptic_probe,
.remove = qpnp_haptic_remove,
@@ -2328,13 +2331,13 @@ static struct spmi_driver qpnp_haptic_driver = {
static int __init qpnp_haptic_init(void)
{
- return spmi_driver_register(&qpnp_haptic_driver);
+ return platform_driver_register(&qpnp_haptic_driver);
}
module_init(qpnp_haptic_init);
static void __exit qpnp_haptic_exit(void)
{
- return spmi_driver_unregister(&qpnp_haptic_driver);
+ return platform_driver_unregister(&qpnp_haptic_driver);
}
module_exit(qpnp_haptic_exit);
diff --git a/drivers/platform/msm/qpnp-power-on.c b/drivers/platform/msm/qpnp-power-on.c
index 964ecfd483ed..135c484d071e 100644
--- a/drivers/platform/msm/qpnp-power-on.c
+++ b/drivers/platform/msm/qpnp-power-on.c
@@ -14,9 +14,11 @@
#include <linux/init.h>
#include <linux/debugfs.h>
#include <linux/kernel.h>
+#include <linux/regmap.h>
#include <linux/errno.h>
#include <linux/slab.h>
#include <linux/spmi.h>
+#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_device.h>
@@ -194,7 +196,8 @@ struct pon_regulator {
};
struct qpnp_pon {
- struct spmi_device *spmi;
+ struct platform_device *pdev;
+ struct regmap *regmap;
struct input_dev *pon_input;
struct qpnp_pon_config *pon_cfg;
struct pon_regulator *pon_reg_cfg;
@@ -205,7 +208,6 @@ struct qpnp_pon {
int pon_power_off_reason;
int num_pon_reg;
int num_pon_config;
- int reg_count;
u32 dbc;
u32 uvlo;
int warm_reset_poff_type;
@@ -302,24 +304,12 @@ static int
qpnp_pon_masked_write(struct qpnp_pon *pon, u16 addr, u8 mask, u8 val)
{
int rc;
- u8 reg;
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- addr, &reg, 1);
- if (rc) {
- dev_err(&pon->spmi->dev,
- "Unable to read from addr=%hx, rc(%d)\n",
- addr, rc);
- return rc;
- }
-
- reg &= ~mask;
- reg |= val & mask;
- rc = spmi_ext_register_writel(pon->spmi->ctrl, pon->spmi->sid,
- addr, &reg, 1);
+ rc = regmap_update_bits(pon->regmap, addr, mask, val);
if (rc)
- dev_err(&pon->spmi->dev,
- "Unable to write to addr=%hx, rc(%d)\n", addr, rc);
+ dev_err(&pon->pdev->dev,
+ "Unable to regmap_update_bits to addr=%hx, rc(%d)\n",
+ addr, rc);
return rc;
}
@@ -360,7 +350,7 @@ int qpnp_pon_set_restart_reason(enum pon_restart_reason reason)
rc = qpnp_pon_masked_write(pon, QPNP_PON_SOFT_RB_SPARE(pon),
PON_MASK(7, 2), (reason << 2));
if (rc)
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to write to addr=%x, rc(%d)\n",
QPNP_PON_SOFT_RB_SPARE(pon), rc);
return rc;
@@ -406,7 +396,7 @@ static int qpnp_pon_set_dbc(struct qpnp_pon *pon, u32 delay)
QPNP_PON_DBC_DELAY_MASK(pon),
delay_reg);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to set PON debounce\n");
+ dev_err(&pon->pdev->dev, "Unable to set PON debounce\n");
goto unlock;
}
@@ -485,7 +475,7 @@ static int qpnp_pon_reset_config(struct qpnp_pon *pon,
rc = qpnp_pon_masked_write(pon, rst_en_reg, QPNP_PON_RESET_EN, 0);
if (rc)
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to write to addr=%hx, rc(%d)\n",
rst_en_reg, rc);
@@ -499,18 +489,18 @@ static int qpnp_pon_reset_config(struct qpnp_pon *pon,
rc = qpnp_pon_masked_write(pon, QPNP_PON_PS_HOLD_RST_CTL(pon),
QPNP_PON_POWER_OFF_MASK, type);
if (rc)
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to write to addr=%x, rc(%d)\n",
QPNP_PON_PS_HOLD_RST_CTL(pon), rc);
rc = qpnp_pon_masked_write(pon, rst_en_reg, QPNP_PON_RESET_EN,
QPNP_PON_RESET_EN);
if (rc)
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to write to addr=%hx, rc(%d)\n",
rst_en_reg, rc);
- dev_dbg(&pon->spmi->dev, "power off type = 0x%02X\n", type);
+ dev_dbg(&pon->pdev->dev, "power off type = 0x%02X\n", type);
return rc;
}
@@ -537,7 +527,8 @@ int qpnp_pon_system_pwr_off(enum pon_power_off_type type)
rc = qpnp_pon_reset_config(pon, type);
if (rc) {
- dev_err(&pon->spmi->dev, "Error configuring main PON rc: %d\n",
+ dev_err(&pon->pdev->dev,
+ "Error configuring main PON rc: %d\n",
rc);
return rc;
}
@@ -552,12 +543,13 @@ int qpnp_pon_system_pwr_off(enum pon_power_off_type type)
goto out;
list_for_each_entry_safe(pon, tmp, &spon_dev_list, list) {
- dev_emerg(&pon->spmi->dev,
+ dev_emerg(&pon->pdev->dev,
"PMIC@SID%d: configuring PON for reset\n",
- pon->spmi->sid);
+ to_spmi_device(pon->pdev->dev.parent)->usid);
rc = qpnp_pon_reset_config(pon, type);
if (rc) {
- dev_err(&pon->spmi->dev, "Error configuring secondary PON rc: %d\n",
+ dev_err(&pon->pdev->dev,
+ "Error configuring secondary PON rc: %d\n",
rc);
goto out;
}
@@ -608,7 +600,7 @@ int qpnp_pon_wd_config(bool enable)
rc = qpnp_pon_masked_write(pon, QPNP_PON_WD_RST_S2_CTL2(pon),
QPNP_PON_WD_EN, enable ? QPNP_PON_WD_EN : 0);
if (rc)
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to write to addr=%x, rc(%d)\n",
QPNP_PON_WD_RST_S2_CTL2(pon), rc);
@@ -622,7 +614,7 @@ static int qpnp_pon_get_trigger_config(enum pon_trigger_source pon_src,
struct qpnp_pon *pon = sys_reset_dev;
int rc;
u16 addr;
- u8 val;
+ int val;
u8 mask;
if (!pon)
@@ -640,8 +632,8 @@ static int qpnp_pon_get_trigger_config(enum pon_trigger_source pon_src,
mask = QPNP_PON_SMPL_EN;
}
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- addr, &val, 1);
+
+ rc = regmap_read(pon->regmap, addr, &val);
if (rc)
dev_err(&pon->spmi->dev,
"Unable to read from addr=%hx, rc(%d)\n",
@@ -671,7 +663,7 @@ int qpnp_pon_trigger_config(enum pon_trigger_source pon_src, bool enable)
return -EPROBE_DEFER;
if (pon_src < PON_SMPL || pon_src > PON_KPDPWR_N) {
- dev_err(&pon->spmi->dev, "Invalid PON source\n");
+ dev_err(&pon->pdev->dev, "Invalid PON source\n");
return -EINVAL;
}
@@ -679,13 +671,15 @@ int qpnp_pon_trigger_config(enum pon_trigger_source pon_src, bool enable)
rc = qpnp_pon_masked_write(pon, QPNP_PON_SMPL_CTL(pon),
QPNP_PON_SMPL_EN, enable ? QPNP_PON_SMPL_EN : 0);
if (rc)
- dev_err(&pon->spmi->dev, "Unable to write to addr=%x, rc(%d)\n",
+ dev_err(&pon->pdev->dev,
+ "Unable to write to addr=%x, rc(%d)\n",
QPNP_PON_SMPL_CTL(pon), rc);
} else {
rc = qpnp_pon_masked_write(pon, QPNP_PON_TRIGGER_EN(pon),
BIT(pon_src), enable ? BIT(pon_src) : 0);
if (rc)
- dev_err(&pon->spmi->dev, "Unable to write to addr=%x, rc(%d)\n",
+ dev_err(&pon->pdev->dev,
+ "Unable to write to addr=%x, rc(%d)\n",
QPNP_PON_TRIGGER_EN(pon), rc);
}
@@ -702,34 +696,35 @@ static int qpnp_pon_store_and_clear_warm_reset(struct qpnp_pon *pon)
{
int rc;
u8 reg = 0;
+ uint val;
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_PON_WARM_RESET_REASON1(pon),
- &pon->warm_reset_reason1, 1);
+ rc = regmap_read(pon->regmap, QPNP_PON_WARM_RESET_REASON1(pon),
+ &val);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to read addr=%x, rc(%d)\n",
+ dev_err(&pon->pdev->dev, "Unable to read addr=%x, rc(%d)\n",
QPNP_PON_WARM_RESET_REASON1(pon), rc);
return rc;
}
+ pon->warm_reset_reason1 = (u8)val;
if (is_pon_gen1(pon) || pon->subtype == PON_1REG) {
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_PON_WARM_RESET_REASON2(pon),
- &pon->warm_reset_reason2, 1);
+ rc = regmap_read(pon->regmap, QPNP_PON_WARM_RESET_REASON2(pon),
+ &val);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read addr=%x, rc(%d)\n",
QPNP_PON_WARM_RESET_REASON2(pon), rc);
return rc;
}
+ pon->warm_reset_reason2 = (u8)val;
}
- if (of_property_read_bool(pon->spmi->dev.of_node,
+ if (of_property_read_bool(pon->pdev->dev.of_node,
"qcom,clear-warm-reset")) {
- rc = spmi_ext_register_writel(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_PON_WARM_RESET_REASON1(pon), &reg, 1);
+ rc = regmap_write(pon->regmap,
+ QPNP_PON_WARM_RESET_REASON1(pon), reg);
if (rc)
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to write to addr=%hx, rc(%d)\n",
QPNP_PON_WARM_RESET_REASON1(pon), rc);
}
@@ -755,8 +750,9 @@ qpnp_pon_input_dispatch(struct qpnp_pon *pon, u32 pon_type)
{
int rc;
struct qpnp_pon_config *cfg = NULL;
- u8 pon_rt_sts = 0, pon_rt_bit = 0;
+ u8 pon_rt_bit = 0;
u32 key_status;
+ uint pon_rt_sts;
cfg = qpnp_get_cfg(pon, pon_type);
if (!cfg)
@@ -767,10 +763,9 @@ qpnp_pon_input_dispatch(struct qpnp_pon *pon, u32 pon_type)
return 0;
/* check the RT status to get the current status of the line */
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_PON_RT_STS(pon), &pon_rt_sts, 1);
+ rc = regmap_read(pon->regmap, QPNP_PON_RT_STS(pon), &pon_rt_sts);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to read PON RT status\n");
+ dev_err(&pon->pdev->dev, "Unable to read PON RT status\n");
return rc;
}
@@ -818,7 +813,7 @@ static irqreturn_t qpnp_kpdpwr_irq(int irq, void *_pon)
rc = qpnp_pon_input_dispatch(pon, PON_KPDPWR);
if (rc)
- dev_err(&pon->spmi->dev, "Unable to send input event\n");
+ dev_err(&pon->pdev->dev, "Unable to send input event\n");
return IRQ_HANDLED;
}
@@ -835,7 +830,7 @@ static irqreturn_t qpnp_resin_irq(int irq, void *_pon)
rc = qpnp_pon_input_dispatch(pon, PON_RESIN);
if (rc)
- dev_err(&pon->spmi->dev, "Unable to send input event\n");
+ dev_err(&pon->pdev->dev, "Unable to send input event\n");
return IRQ_HANDLED;
}
@@ -851,7 +846,7 @@ static irqreturn_t qpnp_cblpwr_irq(int irq, void *_pon)
rc = qpnp_pon_input_dispatch(pon, PON_CBLPWR);
if (rc)
- dev_err(&pon->spmi->dev, "Unable to send input event\n");
+ dev_err(&pon->pdev->dev, "Unable to send input event\n");
return IRQ_HANDLED;
}
@@ -860,16 +855,15 @@ static void print_pon_reg(struct qpnp_pon *pon, u16 offset)
{
int rc;
u16 addr;
- u8 reg;
+ uint reg;
addr = pon->base + offset;
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- addr, &reg, 1);
+ rc = regmap_read(pon->regmap, addr, &reg);
if (rc)
- dev_emerg(&pon->spmi->dev,
+ dev_emerg(&pon->pdev->dev,
"Unable to read reg at 0x%04hx\n", addr);
else
- dev_emerg(&pon->spmi->dev, "reg@0x%04hx: %02hhx\n", addr, reg);
+ dev_emerg(&pon->pdev->dev, "reg@0x%04hx: %02hhx\n", addr, reg);
}
#define PON_PBL_STATUS 0x7
@@ -913,14 +907,14 @@ static irqreturn_t qpnp_pmic_wd_bark_irq(int irq, void *_pon)
static void bark_work_func(struct work_struct *work)
{
int rc;
- u8 pon_rt_sts = 0;
+ uint pon_rt_sts = 0;
struct qpnp_pon_config *cfg;
struct qpnp_pon *pon =
container_of(work, struct qpnp_pon, bark_work.work);
cfg = qpnp_get_cfg(pon, PON_RESIN);
if (!cfg) {
- dev_err(&pon->spmi->dev, "Invalid config pointer\n");
+ dev_err(&pon->pdev->dev, "Invalid config pointer\n");
goto err_return;
}
@@ -928,16 +922,15 @@ static void bark_work_func(struct work_struct *work)
rc = qpnp_pon_masked_write(pon, cfg->s2_cntl2_addr,
QPNP_PON_S2_CNTL_EN, QPNP_PON_S2_CNTL_EN);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to configure S2 enable\n");
+ dev_err(&pon->pdev->dev, "Unable to configure S2 enable\n");
goto err_return;
}
/* bark RT status update delay */
msleep(100);
/* read the bark RT status */
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_PON_RT_STS(pon), &pon_rt_sts, 1);
+ rc = regmap_read(pon->regmap, QPNP_PON_RT_STS(pon), &pon_rt_sts);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to read PON RT status\n");
+ dev_err(&pon->pdev->dev, "Unable to read PON RT status\n");
goto err_return;
}
@@ -951,7 +944,7 @@ static void bark_work_func(struct work_struct *work)
rc = qpnp_pon_masked_write(pon, cfg->s2_cntl2_addr,
QPNP_PON_S2_CNTL_EN, 0);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to configure S2 enable\n");
goto err_return;
}
@@ -974,7 +967,7 @@ static irqreturn_t qpnp_resin_bark_irq(int irq, void *_pon)
cfg = qpnp_get_cfg(pon, PON_RESIN);
if (!cfg) {
- dev_err(&pon->spmi->dev, "Invalid config pointer\n");
+ dev_err(&pon->pdev->dev, "Invalid config pointer\n");
goto err_exit;
}
@@ -982,7 +975,7 @@ static irqreturn_t qpnp_resin_bark_irq(int irq, void *_pon)
rc = qpnp_pon_masked_write(pon, cfg->s2_cntl2_addr,
QPNP_PON_S2_CNTL_EN, 0);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to configure S2 enable\n");
+ dev_err(&pon->pdev->dev, "Unable to configure S2 enable\n");
goto err_exit;
}
@@ -1021,7 +1014,7 @@ qpnp_config_pull(struct qpnp_pon *pon, struct qpnp_pon_config *cfg)
rc = qpnp_pon_masked_write(pon, QPNP_PON_PULL_CTL(pon),
pull_bit, cfg->pull_up ? pull_bit : 0);
if (rc)
- dev_err(&pon->spmi->dev, "Unable to config pull-up\n");
+ dev_err(&pon->pdev->dev, "Unable to config pull-up\n");
return rc;
}
@@ -1053,7 +1046,7 @@ qpnp_config_reset(struct qpnp_pon *pon, struct qpnp_pon_config *cfg)
rc = qpnp_pon_masked_write(pon, cfg->s2_cntl2_addr,
QPNP_PON_S2_CNTL_EN, 0);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to configure S2 enable\n");
+ dev_err(&pon->pdev->dev, "Unable to configure S2 enable\n");
return rc;
}
@@ -1067,7 +1060,7 @@ qpnp_config_reset(struct qpnp_pon *pon, struct qpnp_pon_config *cfg)
rc = qpnp_pon_masked_write(pon, s1_timer_addr,
QPNP_PON_S1_TIMER_MASK, i);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to configure S1 timer\n");
+ dev_err(&pon->pdev->dev, "Unable to configure S1 timer\n");
return rc;
}
@@ -1080,14 +1073,15 @@ qpnp_config_reset(struct qpnp_pon *pon, struct qpnp_pon_config *cfg)
rc = qpnp_pon_masked_write(pon, s2_timer_addr,
QPNP_PON_S2_TIMER_MASK, i);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to configure S2 timer\n");
+ dev_err(&pon->pdev->dev, "Unable to configure S2 timer\n");
return rc;
}
rc = qpnp_pon_masked_write(pon, cfg->s2_cntl_addr,
QPNP_PON_S2_CNTL_TYPE_MASK, (u8)cfg->s2_type);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to configure S2 reset type\n");
+ dev_err(&pon->pdev->dev,
+ "Unable to configure S2 reset type\n");
return rc;
}
@@ -1095,7 +1089,7 @@ qpnp_config_reset(struct qpnp_pon *pon, struct qpnp_pon_config *cfg)
rc = qpnp_pon_masked_write(pon, cfg->s2_cntl2_addr,
QPNP_PON_S2_CNTL_EN, QPNP_PON_S2_CNTL_EN);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to configure S2 enable\n");
+ dev_err(&pon->pdev->dev, "Unable to configure S2 enable\n");
return rc;
}
@@ -1109,22 +1103,22 @@ qpnp_pon_request_irqs(struct qpnp_pon *pon, struct qpnp_pon_config *cfg)
switch (cfg->pon_type) {
case PON_KPDPWR:
- rc = devm_request_irq(&pon->spmi->dev, cfg->state_irq,
+ rc = devm_request_irq(&pon->pdev->dev, cfg->state_irq,
qpnp_kpdpwr_irq,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
"qpnp_kpdpwr_status", pon);
if (rc < 0) {
- dev_err(&pon->spmi->dev, "Can't request %d IRQ\n",
+ dev_err(&pon->pdev->dev, "Can't request %d IRQ\n",
cfg->state_irq);
return rc;
}
if (cfg->use_bark) {
- rc = devm_request_irq(&pon->spmi->dev, cfg->bark_irq,
+ rc = devm_request_irq(&pon->pdev->dev, cfg->bark_irq,
qpnp_kpdpwr_bark_irq,
IRQF_TRIGGER_RISING,
"qpnp_kpdpwr_bark", pon);
if (rc < 0) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Can't request %d IRQ\n",
cfg->bark_irq);
return rc;
@@ -1132,22 +1126,22 @@ qpnp_pon_request_irqs(struct qpnp_pon *pon, struct qpnp_pon_config *cfg)
}
break;
case PON_RESIN:
- rc = devm_request_irq(&pon->spmi->dev, cfg->state_irq,
+ rc = devm_request_irq(&pon->pdev->dev, cfg->state_irq,
qpnp_resin_irq,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
"qpnp_resin_status", pon);
if (rc < 0) {
- dev_err(&pon->spmi->dev, "Can't request %d IRQ\n",
+ dev_err(&pon->pdev->dev, "Can't request %d IRQ\n",
cfg->state_irq);
return rc;
}
if (cfg->use_bark) {
- rc = devm_request_irq(&pon->spmi->dev, cfg->bark_irq,
+ rc = devm_request_irq(&pon->pdev->dev, cfg->bark_irq,
qpnp_resin_bark_irq,
IRQF_TRIGGER_RISING,
"qpnp_resin_bark", pon);
if (rc < 0) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Can't request %d IRQ\n",
cfg->bark_irq);
return rc;
@@ -1155,24 +1149,24 @@ qpnp_pon_request_irqs(struct qpnp_pon *pon, struct qpnp_pon_config *cfg)
}
break;
case PON_CBLPWR:
- rc = devm_request_irq(&pon->spmi->dev, cfg->state_irq,
+ rc = devm_request_irq(&pon->pdev->dev, cfg->state_irq,
qpnp_cblpwr_irq,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
"qpnp_cblpwr_status", pon);
if (rc < 0) {
- dev_err(&pon->spmi->dev, "Can't request %d IRQ\n",
+ dev_err(&pon->pdev->dev, "Can't request %d IRQ\n",
cfg->state_irq);
return rc;
}
break;
case PON_KPDPWR_RESIN:
if (cfg->use_bark) {
- rc = devm_request_irq(&pon->spmi->dev, cfg->bark_irq,
+ rc = devm_request_irq(&pon->pdev->dev, cfg->bark_irq,
qpnp_kpdpwr_resin_bark_irq,
IRQF_TRIGGER_RISING,
"qpnp_kpdpwr_resin_bark", pon);
if (rc < 0) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Can't request %d IRQ\n",
cfg->bark_irq);
return rc;
@@ -1200,7 +1194,7 @@ qpnp_pon_config_input(struct qpnp_pon *pon, struct qpnp_pon_config *cfg)
if (!pon->pon_input) {
pon->pon_input = input_allocate_device();
if (!pon->pon_input) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Can't allocate pon input device\n");
return -ENOMEM;
}
@@ -1220,17 +1214,17 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
int rc = 0, i = 0, pmic_wd_bark_irq;
struct device_node *pp = NULL;
struct qpnp_pon_config *cfg;
- u8 pmic_type;
- u8 revid_rev4;
+ uint pmic_type;
+ uint revid_rev4;
if (!pon->num_pon_config) {
- dev_dbg(&pon->spmi->dev, "num_pon_config: %d\n",
+ dev_dbg(&pon->pdev->dev, "num_pon_config: %d\n",
pon->num_pon_config);
return 0;
}
/* iterate through the list of pon configs */
- for_each_available_child_of_node(pon->spmi->dev.of_node, pp) {
+ for_each_available_child_of_node(pon->pdev->dev.of_node, pp) {
if (!of_find_property(pp, "qcom,pon-type", NULL))
continue;
@@ -1238,16 +1232,16 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
rc = of_property_read_u32(pp, "qcom,pon-type", &cfg->pon_type);
if (rc) {
- dev_err(&pon->spmi->dev, "PON type not specified\n");
+ dev_err(&pon->pdev->dev, "PON type not specified\n");
return rc;
}
switch (cfg->pon_type) {
case PON_KPDPWR:
- cfg->state_irq = spmi_get_irq_byname(pon->spmi,
- NULL, "kpdpwr");
+ cfg->state_irq = platform_get_irq_byname(pon->pdev,
+ "kpdpwr");
if (cfg->state_irq < 0) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to get kpdpwr irq\n");
return cfg->state_irq;
}
@@ -1257,10 +1251,10 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
if (rc) {
if (rc == -EINVAL) {
- dev_dbg(&pon->spmi->dev,
+ dev_dbg(&pon->pdev->dev,
"'qcom,support-reset' DT property doesn't exist\n");
} else {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read 'qcom,support-reset'\n");
return rc;
}
@@ -1271,10 +1265,11 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
cfg->use_bark = of_property_read_bool(pp,
"qcom,use-bark");
if (cfg->use_bark) {
- cfg->bark_irq = spmi_get_irq_byname(pon->spmi,
- NULL, "kpdpwr-bark");
+ cfg->bark_irq
+ = platform_get_irq_byname(pon->pdev,
+ "kpdpwr-bark");
if (cfg->bark_irq < 0) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to get kpdpwr-bark irq\n");
return cfg->bark_irq;
}
@@ -1296,10 +1291,10 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
break;
case PON_RESIN:
- cfg->state_irq = spmi_get_irq_byname(pon->spmi,
- NULL, "resin");
+ cfg->state_irq = platform_get_irq_byname(pon->pdev,
+ "resin");
if (cfg->state_irq < 0) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to get resin irq\n");
return cfg->bark_irq;
}
@@ -1309,10 +1304,10 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
if (rc) {
if (rc == -EINVAL) {
- dev_dbg(&pon->spmi->dev,
+ dev_dbg(&pon->pdev->dev,
"'qcom,support-reset' DT property doesn't exist\n");
} else {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read 'qcom,support-reset'\n");
return rc;
}
@@ -1323,24 +1318,23 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
cfg->use_bark = of_property_read_bool(pp,
"qcom,use-bark");
- rc = spmi_ext_register_readl(pon->spmi->ctrl,
- pon->spmi->sid, PMIC_VERSION_REG,
- &pmic_type, 1);
+ rc = regmap_read(pon->regmap, PMIC_VERSION_REG,
+ &pmic_type);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read PMIC type\n");
return rc;
}
if (pmic_type == PMIC_VER_8941) {
- rc = spmi_ext_register_readl(pon->spmi->ctrl,
- pon->spmi->sid, PMIC_VERSION_REV4_REG,
- &revid_rev4, 1);
+ rc = regmap_read(pon->regmap,
+ PMIC_VERSION_REV4_REG,
+ &revid_rev4);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read PMIC revision ID\n");
return rc;
}
@@ -1355,10 +1349,11 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
}
if (cfg->use_bark) {
- cfg->bark_irq = spmi_get_irq_byname(pon->spmi,
- NULL, "resin-bark");
+ cfg->bark_irq
+ = platform_get_irq_byname(pon->pdev,
+ "resin-bark");
if (cfg->bark_irq < 0) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to get resin-bark irq\n");
return cfg->bark_irq;
}
@@ -1376,10 +1371,10 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
break;
case PON_CBLPWR:
- cfg->state_irq = spmi_get_irq_byname(pon->spmi,
- NULL, "cblpwr");
+ cfg->state_irq = platform_get_irq_byname(pon->pdev,
+ "cblpwr");
if (cfg->state_irq < 0) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to get cblpwr irq\n");
return rc;
}
@@ -1390,10 +1385,10 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
if (rc) {
if (rc == -EINVAL) {
- dev_dbg(&pon->spmi->dev,
+ dev_dbg(&pon->pdev->dev,
"'qcom,support-reset' DT property doesn't exist\n");
} else {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read 'qcom,support-reset'\n");
return rc;
}
@@ -1404,10 +1399,11 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
cfg->use_bark = of_property_read_bool(pp,
"qcom,use-bark");
if (cfg->use_bark) {
- cfg->bark_irq = spmi_get_irq_byname(pon->spmi,
- NULL, "kpdpwr-resin-bark");
+ cfg->bark_irq
+ = platform_get_irq_byname(pon->pdev,
+ "kpdpwr-resin-bark");
if (cfg->bark_irq < 0) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to get kpdpwr-resin-bark irq\n");
return cfg->bark_irq;
}
@@ -1425,7 +1421,7 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
break;
default:
- dev_err(&pon->spmi->dev, "PON RESET %d not supported",
+ dev_err(&pon->pdev->dev, "PON RESET %d not supported",
cfg->pon_type);
return -EINVAL;
}
@@ -1438,40 +1434,39 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
rc = of_property_read_u32(pp, "qcom,s1-timer",
&cfg->s1_timer);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read s1-timer\n");
return rc;
}
if (cfg->s1_timer > QPNP_PON_S1_TIMER_MAX) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Incorrect S1 debounce time\n");
return -EINVAL;
}
rc = of_property_read_u32(pp, "qcom,s2-timer",
&cfg->s2_timer);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read s2-timer\n");
return rc;
}
if (cfg->s2_timer > QPNP_PON_S2_TIMER_MAX) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Incorrect S2 debounce time\n");
return -EINVAL;
}
rc = of_property_read_u32(pp, "qcom,s2-type",
&cfg->s2_type);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read s2-type\n");
return rc;
}
if (cfg->s2_type > QPNP_PON_RESET_TYPE_MAX) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Incorrect reset type specified\n");
return -EINVAL;
}
-
}
/*
* Get the standard-key parameters. This might not be
@@ -1479,8 +1474,7 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
*/
rc = of_property_read_u32(pp, "linux,code", &cfg->key_code);
if (rc && rc != -EINVAL) {
- dev_err(&pon->spmi->dev,
- "Unable to read key-code\n");
+ dev_err(&pon->pdev->dev, "Unable to read key-code\n");
return rc;
}
/* Register key configuration */
@@ -1492,20 +1486,20 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
/* get the pull-up configuration */
rc = of_property_read_u32(pp, "qcom,pull-up", &cfg->pull_up);
if (rc && rc != -EINVAL) {
- dev_err(&pon->spmi->dev, "Unable to read pull-up\n");
+ dev_err(&pon->pdev->dev, "Unable to read pull-up\n");
return rc;
}
}
- pmic_wd_bark_irq = spmi_get_irq_byname(pon->spmi, NULL, "pmic-wd-bark");
+ pmic_wd_bark_irq = platform_get_irq_byname(pon->pdev, "pmic-wd-bark");
/* request the pmic-wd-bark irq only if it is defined */
if (pmic_wd_bark_irq >= 0) {
- rc = devm_request_irq(&pon->spmi->dev, pmic_wd_bark_irq,
+ rc = devm_request_irq(&pon->pdev->dev, pmic_wd_bark_irq,
qpnp_pmic_wd_bark_irq,
IRQF_TRIGGER_RISING,
"qpnp_pmic_wd_bark", pon);
if (rc < 0) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Can't request %d IRQ\n",
pmic_wd_bark_irq);
goto free_input_dev;
@@ -1516,7 +1510,7 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
if (pon->pon_input) {
rc = input_register_device(pon->pon_input);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Can't register pon key: %d\n", rc);
goto free_input_dev;
}
@@ -1527,7 +1521,7 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
/* Configure the pull-up */
rc = qpnp_config_pull(pon, cfg);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to config pull-up\n");
+ dev_err(&pon->pdev->dev, "Unable to config pull-up\n");
goto unreg_input_dev;
}
@@ -1536,7 +1530,7 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
if (cfg->support_reset) {
rc = qpnp_config_reset(pon, cfg);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to config pon reset\n");
goto unreg_input_dev;
}
@@ -1547,7 +1541,7 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
cfg->s2_cntl2_addr,
QPNP_PON_S2_CNTL_EN, 0);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to disable S2 reset\n");
goto unreg_input_dev;
}
@@ -1557,12 +1551,12 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
rc = qpnp_pon_request_irqs(pon, cfg);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to request-irq's\n");
+ dev_err(&pon->pdev->dev, "Unable to request-irq's\n");
goto unreg_input_dev;
}
}
- device_init_wakeup(&pon->spmi->dev, 1);
+ device_init_wakeup(&pon->pdev->dev, 1);
return rc;
@@ -1588,7 +1582,7 @@ static int pon_spare_regulator_enable(struct regulator_dev *rdev)
rc = qpnp_pon_masked_write(pon_reg->pon, pon_reg->pon->base +
pon_reg->addr, value, value);
if (rc)
- dev_err(&pon_reg->pon->spmi->dev, "Unable to write to %x\n",
+ dev_err(&pon_reg->pon->pdev->dev, "Unable to write to %x\n",
pon_reg->pon->base + pon_reg->addr);
else
pon_reg->enabled = true;
@@ -1608,7 +1602,7 @@ static int pon_spare_regulator_disable(struct regulator_dev *rdev)
rc = qpnp_pon_masked_write(pon_reg->pon, pon_reg->pon->base +
pon_reg->addr, mask, 0);
if (rc)
- dev_err(&pon_reg->pon->spmi->dev, "Unable to write to %x\n",
+ dev_err(&pon_reg->pon->pdev->dev, "Unable to write to %x\n",
pon_reg->pon->base + pon_reg->addr);
else
pon_reg->enabled = false;
@@ -1634,7 +1628,7 @@ static int pon_regulator_init(struct qpnp_pon *pon)
struct regulator_init_data *init_data;
struct regulator_config reg_cfg = {};
struct device_node *node = NULL;
- struct device *dev = &pon->spmi->dev;
+ struct device *dev = &pon->pdev->dev;
struct pon_regulator *pon_reg;
if (!pon->num_pon_reg)
@@ -1749,15 +1743,14 @@ static int qpnp_pon_debugfs_uvlo_dload_get(char *buf,
{
struct qpnp_pon *pon = sys_reset_dev;
int rc = 0;
- u8 reg;
+ uint reg;
if (!pon)
return -ENODEV;
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_PON_XVDD_RB_SPARE(pon), &reg, 1);
+ rc = regmap_read(pon->regmap, QPNP_PON_XVDD_RB_SPARE(pon), &reg);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read addr=%x, rc(%d)\n",
QPNP_PON_XVDD_RB_SPARE(pon), rc);
return rc;
@@ -1772,7 +1765,7 @@ static int qpnp_pon_debugfs_uvlo_dload_set(const char *val,
{
struct qpnp_pon *pon = sys_reset_dev;
int rc = 0;
- u8 reg;
+ uint reg;
if (!pon)
return -ENODEV;
@@ -1783,10 +1776,9 @@ static int qpnp_pon_debugfs_uvlo_dload_set(const char *val,
return rc;
}
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_PON_XVDD_RB_SPARE(pon), &reg, 1);
+ rc = regmap_read(pon->regmap, QPNP_PON_XVDD_RB_SPARE(pon), &reg);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read addr=%x, rc(%d)\n",
QPNP_PON_XVDD_RB_SPARE(pon), rc);
return rc;
@@ -1796,10 +1788,9 @@ static int qpnp_pon_debugfs_uvlo_dload_set(const char *val,
if (*(bool *)kp->arg)
reg |= QPNP_PON_UVLO_DLOAD_EN;
- rc = spmi_ext_register_writel(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_PON_XVDD_RB_SPARE(pon), &reg, 1);
+ rc = regmap_write(pon->regmap, QPNP_PON_XVDD_RB_SPARE(pon), reg);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to write to addr=%hx, rc(%d)\n",
QPNP_PON_XVDD_RB_SPARE(pon), rc);
return rc;
@@ -1841,36 +1832,38 @@ static int qpnp_pon_debugfs_uvlo_set(void *data, u64 val)
DEFINE_SIMPLE_ATTRIBUTE(qpnp_pon_debugfs_uvlo_fops, qpnp_pon_debugfs_uvlo_get,
qpnp_pon_debugfs_uvlo_set, "0x%02llx\n");
-static void qpnp_pon_debugfs_init(struct spmi_device *spmi)
+static void qpnp_pon_debugfs_init(struct platform_device *pdev)
{
- struct qpnp_pon *pon = dev_get_drvdata(&spmi->dev);
+ struct qpnp_pon *pon = dev_get_drvdata(&pdev->dev);
struct dentry *ent;
- pon->debugfs = debugfs_create_dir(dev_name(&spmi->dev), NULL);
+ pon->debugfs = debugfs_create_dir(dev_name(&pdev->dev), NULL);
if (!pon->debugfs) {
- dev_err(&pon->spmi->dev, "Unable to create debugfs directory\n");
+ dev_err(&pon->pdev->dev,
+ "Unable to create debugfs directory\n");
} else {
ent = debugfs_create_file("uvlo_panic",
S_IFREG | S_IWUSR | S_IRUGO,
pon->debugfs, pon, &qpnp_pon_debugfs_uvlo_fops);
if (!ent)
- dev_err(&pon->spmi->dev, "Unable to create uvlo_panic debugfs file.\n");
+ dev_err(&pon->pdev->dev,
+ "Unable to create uvlo_panic debugfs file.\n");
}
}
-static void qpnp_pon_debugfs_remove(struct spmi_device *spmi)
+static void qpnp_pon_debugfs_remove(struct platform_device *pdev)
{
- struct qpnp_pon *pon = dev_get_drvdata(&spmi->dev);
+ struct qpnp_pon *pon = dev_get_drvdata(&pdev->dev);
debugfs_remove_recursive(pon->debugfs);
}
#else
-static void qpnp_pon_debugfs_init(struct spmi_device *spmi)
+static void qpnp_pon_debugfs_init(struct platform_device *pdev)
{}
-static void qpnp_pon_debugfs_remove(struct spmi_device *spmi)
+static void qpnp_pon_debugfs_remove(struct platform_device *pdev)
{}
#endif
@@ -1878,96 +1871,104 @@ static int read_gen2_pon_off_reason(struct qpnp_pon *pon, u16 *reason,
int *reason_index_offset)
{
int rc;
- u8 buf[2], reg;
+ int buf[2], reg;
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_PON_OFF_REASON(pon),
- &reg, 1);
+ rc = regmap_read(pon->regmap,
+ QPNP_PON_OFF_REASON(pon),
+ &reg);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to read PON_OFF_REASON reg rc:%d\n",
+ dev_err(&pon->pdev->dev, "Unable to read PON_OFF_REASON reg rc:%d\n",
rc);
return rc;
}
if (reg & QPNP_GEN2_POFF_SEQ) {
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_POFF_REASON1(pon),
- buf, 1);
+ rc = regmap_read(pon->regmap,
+ QPNP_POFF_REASON1(pon),
+ buf);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to read POFF_REASON1 reg rc:%d\n",
+ dev_err(&pon->pdev->dev, "Unable to read POFF_REASON1 reg rc:%d\n",
rc);
return rc;
}
- *reason = buf[0];
+ *reason = (u8)buf[0];
*reason_index_offset = 0;
} else if (reg & QPNP_GEN2_FAULT_SEQ) {
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_FAULT_REASON1(pon),
- buf, 2);
+ rc = regmap_bulk_read(pon->regmap,
+ QPNP_FAULT_REASON1(pon),
+ buf, 2);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to read FAULT_REASON regs rc:%d\n",
+ dev_err(&pon->pdev->dev, "Unable to read FAULT_REASON regs rc:%d\n",
rc);
return rc;
}
- *reason = buf[0] | (buf[1] << 8);
+ *reason = (u8)buf[0] | (u16)(buf[1] << 8);
*reason_index_offset = POFF_REASON_FAULT_OFFSET;
} else if (reg & QPNP_GEN2_S3_RESET_SEQ) {
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_S3_RESET_REASON(pon),
- buf, 1);
+ rc = regmap_read(pon->regmap,
+ QPNP_S3_RESET_REASON(pon),
+ buf);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to read S3_RESET_REASON reg rc:%d\n",
+ dev_err(&pon->pdev->dev, "Unable to read S3_RESET_REASON reg rc:%d\n",
rc);
return rc;
}
- *reason = buf[0];
+ *reason = (u8)buf[0];
*reason_index_offset = POFF_REASON_S3_RESET_OFFSET;
}
return 0;
}
-static int qpnp_pon_probe(struct spmi_device *spmi)
+static int qpnp_pon_probe(struct platform_device *pdev)
{
struct qpnp_pon *pon;
- struct resource *pon_resource;
+ unsigned int base;
struct device_node *node = NULL;
u32 delay = 0, s3_debounce = 0;
int rc, sys_reset, index;
int reason_index_offset = 0;
- u8 pon_sts = 0, buf[2];
+ u8 buf[2];
+ uint pon_sts = 0;
u16 poff_sts = 0;
const char *s3_src;
u8 s3_src_reg;
unsigned long flags;
+ uint temp = 0;
- pon = devm_kzalloc(&spmi->dev, sizeof(struct qpnp_pon),
- GFP_KERNEL);
- if (!pon) {
- dev_err(&spmi->dev, "Can't allocate qpnp_pon\n");
+ pon = devm_kzalloc(&pdev->dev, sizeof(struct qpnp_pon), GFP_KERNEL);
+ if (!pon)
return -ENOMEM;
+
+ pon->regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ if (!pon->regmap) {
+ dev_err(&pdev->dev, "Couldn't get parent's regmap\n");
+ return -EINVAL;
}
- sys_reset = of_property_read_bool(spmi->dev.of_node,
+ sys_reset = of_property_read_bool(pdev->dev.of_node,
"qcom,system-reset");
if (sys_reset && sys_reset_dev) {
- dev_err(&spmi->dev, "qcom,system-reset property can only be specified for one device on the system\n");
+ dev_err(&pdev->dev,
+ "qcom,system-reset property can only be specified for one device on the system\n");
return -EINVAL;
} else if (sys_reset) {
sys_reset_dev = pon;
}
- pon->spmi = spmi;
+ pon->pdev = pdev;
- pon_resource = spmi_get_resource(spmi, NULL, IORESOURCE_MEM, 0);
- if (!pon_resource) {
- dev_err(&spmi->dev, "Unable to get PON base address\n");
- return -ENXIO;
+ rc = of_property_read_u32(pdev->dev.of_node, "reg", &base);
+ if (rc < 0) {
+ dev_err(&pdev->dev,
+ "Couldn't find reg in node = %s rc = %d\n",
+ pdev->dev.of_node->full_name, rc);
+ return rc;
}
- pon->base = pon_resource->start;
+ pon->base = base;
/* get the total number of pon configurations */
- for_each_available_child_of_node(spmi->dev.of_node, node) {
+ for_each_available_child_of_node(pdev->dev.of_node, node) {
if (of_find_property(node, "regulator-name", NULL)) {
pon->num_pon_reg++;
} else if (of_find_property(node, "qcom,pon-type", NULL)) {
@@ -1979,43 +1980,47 @@ static int qpnp_pon_probe(struct spmi_device *spmi)
}
pr_debug("PON@SID %d: num_pon_config: %d num_pon_reg: %d\n",
- pon->spmi->sid, pon->num_pon_config, pon->num_pon_reg);
+ to_spmi_device(pon->pdev->dev.parent)->usid,
+ pon->num_pon_config, pon->num_pon_reg);
rc = pon_regulator_init(pon);
if (rc) {
- dev_err(&pon->spmi->dev, "Error in pon_regulator_init rc: %d\n",
+ dev_err(&pdev->dev, "Error in pon_regulator_init rc: %d\n",
rc);
return rc;
}
if (!pon->num_pon_config)
/* No PON config., do not register the driver */
- dev_info(&spmi->dev, "No PON config. specified\n");
+ dev_info(&pdev->dev, "No PON config. specified\n");
else
- pon->pon_cfg = devm_kzalloc(&spmi->dev,
+ pon->pon_cfg = devm_kzalloc(&pdev->dev,
sizeof(struct qpnp_pon_config) *
pon->num_pon_config, GFP_KERNEL);
/* Read PON_PERPH_SUBTYPE register to get PON type */
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
+ rc = regmap_read(pon->regmap,
QPNP_PON_PERPH_SUBTYPE(pon),
- &pon->subtype, 1);
+ &temp);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read PON_PERPH_SUBTYPE register rc: %d\n",
rc);
return rc;
}
+ pon->subtype = temp;
/* Check if it is rev B */
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_PON_REVISION2(pon), &pon->pon_ver, 1);
+ rc = regmap_read(pon->regmap,
+ QPNP_PON_REVISION2(pon), &temp);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read addr=%x, rc(%d)\n",
QPNP_PON_REVISION2(pon), rc);
return rc;
}
+
+ pon->pon_ver = temp;
if (is_pon_gen1(pon)) {
if (pon->pon_ver == 0)
pon->pon_ver = QPNP_PON_GEN1_V1;
@@ -2026,7 +2031,7 @@ static int qpnp_pon_probe(struct spmi_device *spmi)
} else if (pon->subtype == PON_1REG) {
pon->pon_ver = QPNP_PON_GEN1_V2;
} else {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Invalid PON_PERPH_SUBTYPE value %x\n",
pon->subtype);
return -EINVAL;
@@ -2037,17 +2042,17 @@ static int qpnp_pon_probe(struct spmi_device *spmi)
rc = qpnp_pon_store_and_clear_warm_reset(pon);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to store/clear WARM_RESET_REASONx registers rc: %d\n",
rc);
return rc;
}
/* PON reason */
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_PON_REASON1(pon), &pon_sts, 1);
+ rc = regmap_read(pon->regmap, QPNP_PON_REASON1(pon), &pon_sts);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to read PON_REASON1 reg rc: %d\n",
+ dev_err(&pon->pdev->dev,
+ "Unable to read PON_RESASON1 reg rc: %d\n",
rc);
return rc;
}
@@ -2055,14 +2060,16 @@ static int qpnp_pon_probe(struct spmi_device *spmi)
index = ffs(pon_sts) - 1;
cold_boot = !qpnp_pon_is_warm_reset();
if (index >= ARRAY_SIZE(qpnp_pon_reason) || index < 0) {
- dev_info(&pon->spmi->dev,
+ dev_info(&pon->pdev->dev,
"PMIC@SID%d Power-on reason: Unknown and '%s' boot\n",
- pon->spmi->sid, cold_boot ? "cold" : "warm");
+ to_spmi_device(pon->pdev->dev.parent)->usid,
+ cold_boot ? "cold" : "warm");
} else {
pon->pon_trigger_reason = index;
- dev_info(&pon->spmi->dev,
+ dev_info(&pon->pdev->dev,
"PMIC@SID%d Power-on reason: %s and '%s' boot\n",
- pon->spmi->sid, qpnp_pon_reason[index],
+ to_spmi_device(pon->pdev->dev.parent)->usid,
+ qpnp_pon_reason[index],
cold_boot ? "cold" : "warm");
}
@@ -2073,11 +2080,10 @@ static int qpnp_pon_probe(struct spmi_device *spmi)
if (rc)
return rc;
} else {
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_POFF_REASON1(pon),
- buf, 2);
+ rc = regmap_bulk_read(pon->regmap, QPNP_POFF_REASON1(pon),
+ buf, 2);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to read POFF_REASON regs rc:%d\n",
+ dev_err(&pon->pdev->dev, "Unable to read POFF_REASON regs rc:%d\n",
rc);
return rc;
}
@@ -2085,36 +2091,37 @@ static int qpnp_pon_probe(struct spmi_device *spmi)
}
index = ffs(poff_sts) - 1 + reason_index_offset;
if (index >= ARRAY_SIZE(qpnp_poff_reason) || index < 0) {
- dev_info(&pon->spmi->dev,
+ dev_info(&pon->pdev->dev,
"PMIC@SID%d: Unknown power-off reason\n",
- pon->spmi->sid);
+ to_spmi_device(pon->pdev->dev.parent)->usid);
} else {
pon->pon_power_off_reason = index;
- dev_info(&pon->spmi->dev,
+ dev_info(&pon->pdev->dev,
"PMIC@SID%d: Power-off reason: %s\n",
- pon->spmi->sid,
+ to_spmi_device(pon->pdev->dev.parent)->usid,
qpnp_poff_reason[index]);
}
if (pon->pon_trigger_reason == PON_SMPL ||
pon->pon_power_off_reason == QPNP_POFF_REASON_UVLO) {
- if (of_property_read_bool(spmi->dev.of_node,
+ if (of_property_read_bool(pdev->dev.of_node,
"qcom,uvlo-panic"))
panic("An UVLO was occurred.");
}
/* program s3 debounce */
- rc = of_property_read_u32(pon->spmi->dev.of_node,
+ rc = of_property_read_u32(pon->pdev->dev.of_node,
"qcom,s3-debounce", &s3_debounce);
if (rc) {
if (rc != -EINVAL) {
- dev_err(&pon->spmi->dev, "Unable to read s3 timer rc:%d\n",
+ dev_err(&pon->pdev->dev,
+ "Unable to read s3 timer rc:%d\n",
rc);
return rc;
}
} else {
if (s3_debounce > QPNP_PON_S3_TIMER_SECS_MAX) {
- dev_info(&pon->spmi->dev,
+ dev_info(&pon->pdev->dev,
"Exceeded S3 max value, set it to max\n");
s3_debounce = QPNP_PON_S3_TIMER_SECS_MAX;
}
@@ -2127,7 +2134,7 @@ static int qpnp_pon_probe(struct spmi_device *spmi)
rc = qpnp_pon_masked_write(pon, QPNP_PON_SEC_ACCESS(pon),
0xFF, QPNP_PON_SEC_UNLOCK);
if (rc) {
- dev_err(&spmi->dev, "Unable to do SEC_ACCESS rc:%d\n",
+ dev_err(&pdev->dev, "Unable to do SEC_ACCESS rc:%d\n",
rc);
return rc;
}
@@ -2135,7 +2142,8 @@ static int qpnp_pon_probe(struct spmi_device *spmi)
rc = qpnp_pon_masked_write(pon, QPNP_PON_S3_DBC_CTL(pon),
QPNP_PON_S3_DBC_DELAY_MASK, s3_debounce);
if (rc) {
- dev_err(&spmi->dev, "Unable to set S3 debounce rc:%d\n",
+ dev_err(&pdev->dev,
+ "Unable to set S3 debounce rc:%d\n",
rc);
return rc;
}
@@ -2143,10 +2151,10 @@ static int qpnp_pon_probe(struct spmi_device *spmi)
/* program s3 source */
s3_src = "kpdpwr-and-resin";
- rc = of_property_read_string(pon->spmi->dev.of_node,
+ rc = of_property_read_string(pon->pdev->dev.of_node,
"qcom,s3-src", &s3_src);
if (rc && rc != -EINVAL) {
- dev_err(&pon->spmi->dev, "Unable to read s3 timer rc: %d\n",
+ dev_err(&pon->pdev->dev, "Unable to read s3 timer rc: %d\n",
rc);
return rc;
}
@@ -2168,27 +2176,29 @@ static int qpnp_pon_probe(struct spmi_device *spmi)
rc = qpnp_pon_masked_write(pon, QPNP_PON_S3_SRC(pon),
QPNP_PON_S3_SRC_MASK, s3_src_reg);
if (rc) {
- dev_err(&spmi->dev, "Unable to program s3 source rc: %d\n", rc);
+ dev_err(&pdev->dev, "Unable to program s3 source rc: %d\n",
+ rc);
return rc;
}
- dev_set_drvdata(&spmi->dev, pon);
+ dev_set_drvdata(&pdev->dev, pon);
INIT_DELAYED_WORK(&pon->bark_work, bark_work_func);
/* register the PON configurations */
rc = qpnp_pon_config_init(pon);
if (rc) {
- dev_err(&spmi->dev,
+ dev_err(&pdev->dev,
"Unable to initialize PON configurations rc: %d\n", rc);
return rc;
}
- rc = of_property_read_u32(pon->spmi->dev.of_node,
+ rc = of_property_read_u32(pon->pdev->dev.of_node,
"qcom,pon-dbc-delay", &delay);
if (rc) {
if (rc != -EINVAL) {
- dev_err(&spmi->dev, "Unable to read debounce delay rc: %d\n",
+ dev_err(&pdev->dev,
+ "Unable to read debounce delay rc: %d\n",
rc);
return rc;
}
@@ -2196,65 +2206,65 @@ static int qpnp_pon_probe(struct spmi_device *spmi)
rc = qpnp_pon_set_dbc(pon, delay);
}
- rc = of_property_read_u32(pon->spmi->dev.of_node,
+ rc = of_property_read_u32(pon->pdev->dev.of_node,
"qcom,warm-reset-poweroff-type",
&pon->warm_reset_poff_type);
if (rc) {
if (rc != -EINVAL) {
- dev_err(&spmi->dev, "Unable to read warm reset poweroff type rc: %d\n",
+ dev_err(&pdev->dev, "Unable to read warm reset poweroff type rc: %d\n",
rc);
return rc;
}
pon->warm_reset_poff_type = -EINVAL;
} else if (pon->warm_reset_poff_type <= PON_POWER_OFF_RESERVED ||
pon->warm_reset_poff_type >= PON_POWER_OFF_MAX_TYPE) {
- dev_err(&spmi->dev, "Invalid warm-reset-poweroff-type\n");
+ dev_err(&pdev->dev, "Invalid warm-reset-poweroff-type\n");
pon->warm_reset_poff_type = -EINVAL;
}
- rc = of_property_read_u32(pon->spmi->dev.of_node,
+ rc = of_property_read_u32(pon->pdev->dev.of_node,
"qcom,hard-reset-poweroff-type",
&pon->hard_reset_poff_type);
if (rc) {
if (rc != -EINVAL) {
- dev_err(&spmi->dev, "Unable to read hard reset poweroff type rc: %d\n",
+ dev_err(&pdev->dev, "Unable to read hard reset poweroff type rc: %d\n",
rc);
return rc;
}
pon->hard_reset_poff_type = -EINVAL;
} else if (pon->hard_reset_poff_type <= PON_POWER_OFF_RESERVED ||
pon->hard_reset_poff_type >= PON_POWER_OFF_MAX_TYPE) {
- dev_err(&spmi->dev, "Invalid hard-reset-poweroff-type\n");
+ dev_err(&pdev->dev, "Invalid hard-reset-poweroff-type\n");
pon->hard_reset_poff_type = -EINVAL;
}
- rc = of_property_read_u32(pon->spmi->dev.of_node,
+ rc = of_property_read_u32(pon->pdev->dev.of_node,
"qcom,shutdown-poweroff-type",
&pon->shutdown_poff_type);
if (rc) {
if (rc != -EINVAL) {
- dev_err(&spmi->dev, "Unable to read shutdown poweroff type rc: %d\n",
+ dev_err(&pdev->dev, "Unable to read shutdown poweroff type rc: %d\n",
rc);
return rc;
}
pon->shutdown_poff_type = -EINVAL;
} else if (pon->shutdown_poff_type <= PON_POWER_OFF_RESERVED ||
pon->shutdown_poff_type >= PON_POWER_OFF_MAX_TYPE) {
- dev_err(&spmi->dev, "Invalid shutdown-poweroff-type\n");
+ dev_err(&pdev->dev, "Invalid shutdown-poweroff-type\n");
pon->shutdown_poff_type = -EINVAL;
}
- rc = device_create_file(&spmi->dev, &dev_attr_debounce_us);
+ rc = device_create_file(&pdev->dev, &dev_attr_debounce_us);
if (rc) {
- dev_err(&spmi->dev, "sys file creation failed rc: %d\n",
- rc);
+ dev_err(&pdev->dev, "sys file creation failed rc: %d\n", rc);
return rc;
}
- if (of_property_read_bool(spmi->dev.of_node,
+ if (of_property_read_bool(pdev->dev.of_node,
"qcom,secondary-pon-reset")) {
if (sys_reset) {
- dev_err(&spmi->dev, "qcom,system-reset property shouldn't be used along with qcom,secondary-pon-reset property\n");
+ dev_err(&pdev->dev,
+ "qcom,system-reset property shouldn't be used along with qcom,secondary-pon-reset property\n");
return -EINVAL;
}
spin_lock_irqsave(&spon_list_slock, flags);
@@ -2266,26 +2276,25 @@ static int qpnp_pon_probe(struct spmi_device *spmi)
}
/* config whether store the hard reset reason */
- pon->store_hard_reset_reason = of_property_read_bool(
- spmi->dev.of_node,
+ pon->store_hard_reset_reason = of_property_read_bool(pdev->dev.of_node,
"qcom,store-hard-reset-reason");
- qpnp_pon_debugfs_init(spmi);
+ qpnp_pon_debugfs_init(pdev);
return 0;
}
-static int qpnp_pon_remove(struct spmi_device *spmi)
+static int qpnp_pon_remove(struct platform_device *pdev)
{
- struct qpnp_pon *pon = dev_get_drvdata(&spmi->dev);
+ struct qpnp_pon *pon = dev_get_drvdata(&pdev->dev);
unsigned long flags;
- device_remove_file(&spmi->dev, &dev_attr_debounce_us);
+ device_remove_file(&pdev->dev, &dev_attr_debounce_us);
cancel_delayed_work_sync(&pon->bark_work);
if (pon->pon_input)
input_unregister_device(pon->pon_input);
- qpnp_pon_debugfs_remove(spmi);
+ qpnp_pon_debugfs_remove(pdev);
if (pon->is_spon) {
spin_lock_irqsave(&spon_list_slock, flags);
list_del(&pon->list);
@@ -2299,10 +2308,10 @@ static struct of_device_id spmi_match_table[] = {
{}
};
-static struct spmi_driver qpnp_pon_driver = {
+static struct platform_driver qpnp_pon_driver = {
.driver = {
- .name = "qcom,qpnp-power-on",
- .of_match_table = spmi_match_table,
+ .name = "qcom,qpnp-power-on",
+ .of_match_table = spmi_match_table,
},
.probe = qpnp_pon_probe,
.remove = qpnp_pon_remove,
@@ -2310,13 +2319,13 @@ static struct spmi_driver qpnp_pon_driver = {
static int __init qpnp_pon_init(void)
{
- return spmi_driver_register(&qpnp_pon_driver);
+ return platform_driver_register(&qpnp_pon_driver);
}
subsys_initcall(qpnp_pon_init);
static void __exit qpnp_pon_exit(void)
{
- return spmi_driver_unregister(&qpnp_pon_driver);
+ return platform_driver_unregister(&qpnp_pon_driver);
}
module_exit(qpnp_pon_exit);
diff --git a/drivers/platform/msm/qpnp-revid.c b/drivers/platform/msm/qpnp-revid.c
index 4c16a77e9749..0706572d2777 100644
--- a/drivers/platform/msm/qpnp-revid.c
+++ b/drivers/platform/msm/qpnp-revid.c
@@ -13,8 +13,11 @@
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/spmi.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
#include <linux/err.h>
#include <linux/qpnp/qpnp-revid.h>
+#include <linux/of.h>
#define REVID_REVISION1 0x0
#define REVID_REVISION2 0x1
@@ -66,17 +69,17 @@ static struct of_device_id qpnp_revid_match_table[] = {
{}
};
-static u8 qpnp_read_byte(struct spmi_device *spmi, u16 addr)
+static u8 qpnp_read_byte(struct regmap *regmap, u16 addr)
{
int rc;
- u8 val;
+ int val;
- rc = spmi_ext_register_readl(spmi->ctrl, spmi->sid, addr, &val, 1);
+ rc = regmap_read(regmap, addr, &val);
if (rc) {
- pr_err("SPMI read failed rc=%d\n", rc);
+ pr_err("read failed rc=%d\n", rc);
return 0;
}
- return val;
+ return (u8)val;
}
/**
@@ -145,51 +148,60 @@ static size_t build_pmic_string(char *buf, size_t n, int sid,
#define PMIC_PERIPHERAL_TYPE 0x51
#define PMIC_STRING_MAXLENGTH 80
-static int qpnp_revid_probe(struct spmi_device *spmi)
+static int qpnp_revid_probe(struct platform_device *pdev)
{
u8 rev1, rev2, rev3, rev4, pmic_type, pmic_subtype, pmic_status;
u8 option1, option2, option3, option4, spare0;
- struct resource *resource;
+ unsigned int base;
+ int rc;
char pmic_string[PMIC_STRING_MAXLENGTH] = {'\0'};
struct revid_chip *revid_chip;
+ struct regmap *regmap;
- resource = spmi_get_resource(spmi, NULL, IORESOURCE_MEM, 0);
- if (!resource) {
- pr_err("Unable to get spmi resource for REVID\n");
+ regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ if (!regmap) {
+ dev_err(&pdev->dev, "Couldn't get parent's regmap\n");
return -EINVAL;
}
- pmic_type = qpnp_read_byte(spmi, resource->start + REVID_TYPE);
+
+ rc = of_property_read_u32(pdev->dev.of_node, "reg", &base);
+ if (rc < 0) {
+ dev_err(&pdev->dev,
+ "Couldn't find reg in node = %s rc = %d\n",
+ pdev->dev.of_node->full_name, rc);
+ return rc;
+ }
+ pmic_type = qpnp_read_byte(regmap, base + REVID_TYPE);
if (pmic_type != PMIC_PERIPHERAL_TYPE) {
pr_err("Invalid REVID peripheral type: %02X\n", pmic_type);
return -EINVAL;
}
- rev1 = qpnp_read_byte(spmi, resource->start + REVID_REVISION1);
- rev2 = qpnp_read_byte(spmi, resource->start + REVID_REVISION2);
- rev3 = qpnp_read_byte(spmi, resource->start + REVID_REVISION3);
- rev4 = qpnp_read_byte(spmi, resource->start + REVID_REVISION4);
+ rev1 = qpnp_read_byte(regmap, base + REVID_REVISION1);
+ rev2 = qpnp_read_byte(regmap, base + REVID_REVISION2);
+ rev3 = qpnp_read_byte(regmap, base + REVID_REVISION3);
+ rev4 = qpnp_read_byte(regmap, base + REVID_REVISION4);
- pmic_subtype = qpnp_read_byte(spmi, resource->start + REVID_SUBTYPE);
+ pmic_subtype = qpnp_read_byte(regmap, base + REVID_SUBTYPE);
if (pmic_subtype != PMD9655_PERIPHERAL_SUBTYPE)
- pmic_status = qpnp_read_byte(spmi,
- resource->start + REVID_STATUS1);
+ pmic_status = qpnp_read_byte(regmap, base + REVID_STATUS1);
else
pmic_status = 0;
/* special case for PMI8937 */
if (pmic_subtype == PMI8950_PERIPHERAL_SUBTYPE) {
/* read spare register */
- spare0 = qpnp_read_byte(spmi, resource->start + REVID_SPARE_0);
+ spare0 = qpnp_read_byte(regmap, base + REVID_SPARE_0);
if (spare0)
pmic_subtype = PMI8937_PERIPHERAL_SUBTYPE;
}
- revid_chip = devm_kzalloc(&spmi->dev, sizeof(struct revid_chip),
+ revid_chip = devm_kzalloc(&pdev->dev, sizeof(struct revid_chip),
GFP_KERNEL);
if (!revid_chip)
return -ENOMEM;
- revid_chip->dev_node = spmi->dev.of_node;
+ revid_chip->dev_node = pdev->dev.of_node;
revid_chip->data.rev1 = rev1;
revid_chip->data.rev2 = rev2;
revid_chip->data.rev3 = rev3;
@@ -211,14 +223,15 @@ static int qpnp_revid_probe(struct spmi_device *spmi)
option3 = (pmic_status >> 4) & 0x3;
option4 = (pmic_status >> 6) & 0x3;
- build_pmic_string(pmic_string, PMIC_STRING_MAXLENGTH, spmi->sid,
+ build_pmic_string(pmic_string, PMIC_STRING_MAXLENGTH,
+ to_spmi_device(pdev->dev.parent)->usid,
pmic_subtype, rev1, rev2, rev3, rev4);
pr_info("%s options: %d, %d, %d, %d\n",
pmic_string, option1, option2, option3, option4);
return 0;
}
-static struct spmi_driver qpnp_revid_driver = {
+static struct platform_driver qpnp_revid_driver = {
.probe = qpnp_revid_probe,
.driver = {
.name = QPNP_REVID_DEV_NAME,
@@ -229,12 +242,12 @@ static struct spmi_driver qpnp_revid_driver = {
static int __init qpnp_revid_init(void)
{
- return spmi_driver_register(&qpnp_revid_driver);
+ return platform_driver_register(&qpnp_revid_driver);
}
static void __exit qpnp_revid_exit(void)
{
- return spmi_driver_unregister(&qpnp_revid_driver);
+ return platform_driver_unregister(&qpnp_revid_driver);
}
subsys_initcall(qpnp_revid_init);
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-06 02:20:11 +0000