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path: root/drivers/platform/msm/qpnp-power-on.c
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Diffstat (limited to 'drivers/platform/msm/qpnp-power-on.c')
-rw-r--r--drivers/platform/msm/qpnp-power-on.c547
1 files changed, 278 insertions, 269 deletions
diff --git a/drivers/platform/msm/qpnp-power-on.c b/drivers/platform/msm/qpnp-power-on.c
index 964ecfd483ed..135c484d071e 100644
--- a/drivers/platform/msm/qpnp-power-on.c
+++ b/drivers/platform/msm/qpnp-power-on.c
@@ -14,9 +14,11 @@
#include <linux/init.h>
#include <linux/debugfs.h>
#include <linux/kernel.h>
+#include <linux/regmap.h>
#include <linux/errno.h>
#include <linux/slab.h>
#include <linux/spmi.h>
+#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_device.h>
@@ -194,7 +196,8 @@ struct pon_regulator {
};
struct qpnp_pon {
- struct spmi_device *spmi;
+ struct platform_device *pdev;
+ struct regmap *regmap;
struct input_dev *pon_input;
struct qpnp_pon_config *pon_cfg;
struct pon_regulator *pon_reg_cfg;
@@ -205,7 +208,6 @@ struct qpnp_pon {
int pon_power_off_reason;
int num_pon_reg;
int num_pon_config;
- int reg_count;
u32 dbc;
u32 uvlo;
int warm_reset_poff_type;
@@ -302,24 +304,12 @@ static int
qpnp_pon_masked_write(struct qpnp_pon *pon, u16 addr, u8 mask, u8 val)
{
int rc;
- u8 reg;
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- addr, &reg, 1);
- if (rc) {
- dev_err(&pon->spmi->dev,
- "Unable to read from addr=%hx, rc(%d)\n",
- addr, rc);
- return rc;
- }
-
- reg &= ~mask;
- reg |= val & mask;
- rc = spmi_ext_register_writel(pon->spmi->ctrl, pon->spmi->sid,
- addr, &reg, 1);
+ rc = regmap_update_bits(pon->regmap, addr, mask, val);
if (rc)
- dev_err(&pon->spmi->dev,
- "Unable to write to addr=%hx, rc(%d)\n", addr, rc);
+ dev_err(&pon->pdev->dev,
+ "Unable to regmap_update_bits to addr=%hx, rc(%d)\n",
+ addr, rc);
return rc;
}
@@ -360,7 +350,7 @@ int qpnp_pon_set_restart_reason(enum pon_restart_reason reason)
rc = qpnp_pon_masked_write(pon, QPNP_PON_SOFT_RB_SPARE(pon),
PON_MASK(7, 2), (reason << 2));
if (rc)
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to write to addr=%x, rc(%d)\n",
QPNP_PON_SOFT_RB_SPARE(pon), rc);
return rc;
@@ -406,7 +396,7 @@ static int qpnp_pon_set_dbc(struct qpnp_pon *pon, u32 delay)
QPNP_PON_DBC_DELAY_MASK(pon),
delay_reg);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to set PON debounce\n");
+ dev_err(&pon->pdev->dev, "Unable to set PON debounce\n");
goto unlock;
}
@@ -485,7 +475,7 @@ static int qpnp_pon_reset_config(struct qpnp_pon *pon,
rc = qpnp_pon_masked_write(pon, rst_en_reg, QPNP_PON_RESET_EN, 0);
if (rc)
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to write to addr=%hx, rc(%d)\n",
rst_en_reg, rc);
@@ -499,18 +489,18 @@ static int qpnp_pon_reset_config(struct qpnp_pon *pon,
rc = qpnp_pon_masked_write(pon, QPNP_PON_PS_HOLD_RST_CTL(pon),
QPNP_PON_POWER_OFF_MASK, type);
if (rc)
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to write to addr=%x, rc(%d)\n",
QPNP_PON_PS_HOLD_RST_CTL(pon), rc);
rc = qpnp_pon_masked_write(pon, rst_en_reg, QPNP_PON_RESET_EN,
QPNP_PON_RESET_EN);
if (rc)
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to write to addr=%hx, rc(%d)\n",
rst_en_reg, rc);
- dev_dbg(&pon->spmi->dev, "power off type = 0x%02X\n", type);
+ dev_dbg(&pon->pdev->dev, "power off type = 0x%02X\n", type);
return rc;
}
@@ -537,7 +527,8 @@ int qpnp_pon_system_pwr_off(enum pon_power_off_type type)
rc = qpnp_pon_reset_config(pon, type);
if (rc) {
- dev_err(&pon->spmi->dev, "Error configuring main PON rc: %d\n",
+ dev_err(&pon->pdev->dev,
+ "Error configuring main PON rc: %d\n",
rc);
return rc;
}
@@ -552,12 +543,13 @@ int qpnp_pon_system_pwr_off(enum pon_power_off_type type)
goto out;
list_for_each_entry_safe(pon, tmp, &spon_dev_list, list) {
- dev_emerg(&pon->spmi->dev,
+ dev_emerg(&pon->pdev->dev,
"PMIC@SID%d: configuring PON for reset\n",
- pon->spmi->sid);
+ to_spmi_device(pon->pdev->dev.parent)->usid);
rc = qpnp_pon_reset_config(pon, type);
if (rc) {
- dev_err(&pon->spmi->dev, "Error configuring secondary PON rc: %d\n",
+ dev_err(&pon->pdev->dev,
+ "Error configuring secondary PON rc: %d\n",
rc);
goto out;
}
@@ -608,7 +600,7 @@ int qpnp_pon_wd_config(bool enable)
rc = qpnp_pon_masked_write(pon, QPNP_PON_WD_RST_S2_CTL2(pon),
QPNP_PON_WD_EN, enable ? QPNP_PON_WD_EN : 0);
if (rc)
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to write to addr=%x, rc(%d)\n",
QPNP_PON_WD_RST_S2_CTL2(pon), rc);
@@ -622,7 +614,7 @@ static int qpnp_pon_get_trigger_config(enum pon_trigger_source pon_src,
struct qpnp_pon *pon = sys_reset_dev;
int rc;
u16 addr;
- u8 val;
+ int val;
u8 mask;
if (!pon)
@@ -640,8 +632,8 @@ static int qpnp_pon_get_trigger_config(enum pon_trigger_source pon_src,
mask = QPNP_PON_SMPL_EN;
}
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- addr, &val, 1);
+
+ rc = regmap_read(pon->regmap, addr, &val);
if (rc)
dev_err(&pon->spmi->dev,
"Unable to read from addr=%hx, rc(%d)\n",
@@ -671,7 +663,7 @@ int qpnp_pon_trigger_config(enum pon_trigger_source pon_src, bool enable)
return -EPROBE_DEFER;
if (pon_src < PON_SMPL || pon_src > PON_KPDPWR_N) {
- dev_err(&pon->spmi->dev, "Invalid PON source\n");
+ dev_err(&pon->pdev->dev, "Invalid PON source\n");
return -EINVAL;
}
@@ -679,13 +671,15 @@ int qpnp_pon_trigger_config(enum pon_trigger_source pon_src, bool enable)
rc = qpnp_pon_masked_write(pon, QPNP_PON_SMPL_CTL(pon),
QPNP_PON_SMPL_EN, enable ? QPNP_PON_SMPL_EN : 0);
if (rc)
- dev_err(&pon->spmi->dev, "Unable to write to addr=%x, rc(%d)\n",
+ dev_err(&pon->pdev->dev,
+ "Unable to write to addr=%x, rc(%d)\n",
QPNP_PON_SMPL_CTL(pon), rc);
} else {
rc = qpnp_pon_masked_write(pon, QPNP_PON_TRIGGER_EN(pon),
BIT(pon_src), enable ? BIT(pon_src) : 0);
if (rc)
- dev_err(&pon->spmi->dev, "Unable to write to addr=%x, rc(%d)\n",
+ dev_err(&pon->pdev->dev,
+ "Unable to write to addr=%x, rc(%d)\n",
QPNP_PON_TRIGGER_EN(pon), rc);
}
@@ -702,34 +696,35 @@ static int qpnp_pon_store_and_clear_warm_reset(struct qpnp_pon *pon)
{
int rc;
u8 reg = 0;
+ uint val;
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_PON_WARM_RESET_REASON1(pon),
- &pon->warm_reset_reason1, 1);
+ rc = regmap_read(pon->regmap, QPNP_PON_WARM_RESET_REASON1(pon),
+ &val);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to read addr=%x, rc(%d)\n",
+ dev_err(&pon->pdev->dev, "Unable to read addr=%x, rc(%d)\n",
QPNP_PON_WARM_RESET_REASON1(pon), rc);
return rc;
}
+ pon->warm_reset_reason1 = (u8)val;
if (is_pon_gen1(pon) || pon->subtype == PON_1REG) {
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_PON_WARM_RESET_REASON2(pon),
- &pon->warm_reset_reason2, 1);
+ rc = regmap_read(pon->regmap, QPNP_PON_WARM_RESET_REASON2(pon),
+ &val);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read addr=%x, rc(%d)\n",
QPNP_PON_WARM_RESET_REASON2(pon), rc);
return rc;
}
+ pon->warm_reset_reason2 = (u8)val;
}
- if (of_property_read_bool(pon->spmi->dev.of_node,
+ if (of_property_read_bool(pon->pdev->dev.of_node,
"qcom,clear-warm-reset")) {
- rc = spmi_ext_register_writel(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_PON_WARM_RESET_REASON1(pon), &reg, 1);
+ rc = regmap_write(pon->regmap,
+ QPNP_PON_WARM_RESET_REASON1(pon), reg);
if (rc)
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to write to addr=%hx, rc(%d)\n",
QPNP_PON_WARM_RESET_REASON1(pon), rc);
}
@@ -755,8 +750,9 @@ qpnp_pon_input_dispatch(struct qpnp_pon *pon, u32 pon_type)
{
int rc;
struct qpnp_pon_config *cfg = NULL;
- u8 pon_rt_sts = 0, pon_rt_bit = 0;
+ u8 pon_rt_bit = 0;
u32 key_status;
+ uint pon_rt_sts;
cfg = qpnp_get_cfg(pon, pon_type);
if (!cfg)
@@ -767,10 +763,9 @@ qpnp_pon_input_dispatch(struct qpnp_pon *pon, u32 pon_type)
return 0;
/* check the RT status to get the current status of the line */
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_PON_RT_STS(pon), &pon_rt_sts, 1);
+ rc = regmap_read(pon->regmap, QPNP_PON_RT_STS(pon), &pon_rt_sts);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to read PON RT status\n");
+ dev_err(&pon->pdev->dev, "Unable to read PON RT status\n");
return rc;
}
@@ -818,7 +813,7 @@ static irqreturn_t qpnp_kpdpwr_irq(int irq, void *_pon)
rc = qpnp_pon_input_dispatch(pon, PON_KPDPWR);
if (rc)
- dev_err(&pon->spmi->dev, "Unable to send input event\n");
+ dev_err(&pon->pdev->dev, "Unable to send input event\n");
return IRQ_HANDLED;
}
@@ -835,7 +830,7 @@ static irqreturn_t qpnp_resin_irq(int irq, void *_pon)
rc = qpnp_pon_input_dispatch(pon, PON_RESIN);
if (rc)
- dev_err(&pon->spmi->dev, "Unable to send input event\n");
+ dev_err(&pon->pdev->dev, "Unable to send input event\n");
return IRQ_HANDLED;
}
@@ -851,7 +846,7 @@ static irqreturn_t qpnp_cblpwr_irq(int irq, void *_pon)
rc = qpnp_pon_input_dispatch(pon, PON_CBLPWR);
if (rc)
- dev_err(&pon->spmi->dev, "Unable to send input event\n");
+ dev_err(&pon->pdev->dev, "Unable to send input event\n");
return IRQ_HANDLED;
}
@@ -860,16 +855,15 @@ static void print_pon_reg(struct qpnp_pon *pon, u16 offset)
{
int rc;
u16 addr;
- u8 reg;
+ uint reg;
addr = pon->base + offset;
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- addr, &reg, 1);
+ rc = regmap_read(pon->regmap, addr, &reg);
if (rc)
- dev_emerg(&pon->spmi->dev,
+ dev_emerg(&pon->pdev->dev,
"Unable to read reg at 0x%04hx\n", addr);
else
- dev_emerg(&pon->spmi->dev, "reg@0x%04hx: %02hhx\n", addr, reg);
+ dev_emerg(&pon->pdev->dev, "reg@0x%04hx: %02hhx\n", addr, reg);
}
#define PON_PBL_STATUS 0x7
@@ -913,14 +907,14 @@ static irqreturn_t qpnp_pmic_wd_bark_irq(int irq, void *_pon)
static void bark_work_func(struct work_struct *work)
{
int rc;
- u8 pon_rt_sts = 0;
+ uint pon_rt_sts = 0;
struct qpnp_pon_config *cfg;
struct qpnp_pon *pon =
container_of(work, struct qpnp_pon, bark_work.work);
cfg = qpnp_get_cfg(pon, PON_RESIN);
if (!cfg) {
- dev_err(&pon->spmi->dev, "Invalid config pointer\n");
+ dev_err(&pon->pdev->dev, "Invalid config pointer\n");
goto err_return;
}
@@ -928,16 +922,15 @@ static void bark_work_func(struct work_struct *work)
rc = qpnp_pon_masked_write(pon, cfg->s2_cntl2_addr,
QPNP_PON_S2_CNTL_EN, QPNP_PON_S2_CNTL_EN);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to configure S2 enable\n");
+ dev_err(&pon->pdev->dev, "Unable to configure S2 enable\n");
goto err_return;
}
/* bark RT status update delay */
msleep(100);
/* read the bark RT status */
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_PON_RT_STS(pon), &pon_rt_sts, 1);
+ rc = regmap_read(pon->regmap, QPNP_PON_RT_STS(pon), &pon_rt_sts);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to read PON RT status\n");
+ dev_err(&pon->pdev->dev, "Unable to read PON RT status\n");
goto err_return;
}
@@ -951,7 +944,7 @@ static void bark_work_func(struct work_struct *work)
rc = qpnp_pon_masked_write(pon, cfg->s2_cntl2_addr,
QPNP_PON_S2_CNTL_EN, 0);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to configure S2 enable\n");
goto err_return;
}
@@ -974,7 +967,7 @@ static irqreturn_t qpnp_resin_bark_irq(int irq, void *_pon)
cfg = qpnp_get_cfg(pon, PON_RESIN);
if (!cfg) {
- dev_err(&pon->spmi->dev, "Invalid config pointer\n");
+ dev_err(&pon->pdev->dev, "Invalid config pointer\n");
goto err_exit;
}
@@ -982,7 +975,7 @@ static irqreturn_t qpnp_resin_bark_irq(int irq, void *_pon)
rc = qpnp_pon_masked_write(pon, cfg->s2_cntl2_addr,
QPNP_PON_S2_CNTL_EN, 0);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to configure S2 enable\n");
+ dev_err(&pon->pdev->dev, "Unable to configure S2 enable\n");
goto err_exit;
}
@@ -1021,7 +1014,7 @@ qpnp_config_pull(struct qpnp_pon *pon, struct qpnp_pon_config *cfg)
rc = qpnp_pon_masked_write(pon, QPNP_PON_PULL_CTL(pon),
pull_bit, cfg->pull_up ? pull_bit : 0);
if (rc)
- dev_err(&pon->spmi->dev, "Unable to config pull-up\n");
+ dev_err(&pon->pdev->dev, "Unable to config pull-up\n");
return rc;
}
@@ -1053,7 +1046,7 @@ qpnp_config_reset(struct qpnp_pon *pon, struct qpnp_pon_config *cfg)
rc = qpnp_pon_masked_write(pon, cfg->s2_cntl2_addr,
QPNP_PON_S2_CNTL_EN, 0);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to configure S2 enable\n");
+ dev_err(&pon->pdev->dev, "Unable to configure S2 enable\n");
return rc;
}
@@ -1067,7 +1060,7 @@ qpnp_config_reset(struct qpnp_pon *pon, struct qpnp_pon_config *cfg)
rc = qpnp_pon_masked_write(pon, s1_timer_addr,
QPNP_PON_S1_TIMER_MASK, i);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to configure S1 timer\n");
+ dev_err(&pon->pdev->dev, "Unable to configure S1 timer\n");
return rc;
}
@@ -1080,14 +1073,15 @@ qpnp_config_reset(struct qpnp_pon *pon, struct qpnp_pon_config *cfg)
rc = qpnp_pon_masked_write(pon, s2_timer_addr,
QPNP_PON_S2_TIMER_MASK, i);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to configure S2 timer\n");
+ dev_err(&pon->pdev->dev, "Unable to configure S2 timer\n");
return rc;
}
rc = qpnp_pon_masked_write(pon, cfg->s2_cntl_addr,
QPNP_PON_S2_CNTL_TYPE_MASK, (u8)cfg->s2_type);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to configure S2 reset type\n");
+ dev_err(&pon->pdev->dev,
+ "Unable to configure S2 reset type\n");
return rc;
}
@@ -1095,7 +1089,7 @@ qpnp_config_reset(struct qpnp_pon *pon, struct qpnp_pon_config *cfg)
rc = qpnp_pon_masked_write(pon, cfg->s2_cntl2_addr,
QPNP_PON_S2_CNTL_EN, QPNP_PON_S2_CNTL_EN);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to configure S2 enable\n");
+ dev_err(&pon->pdev->dev, "Unable to configure S2 enable\n");
return rc;
}
@@ -1109,22 +1103,22 @@ qpnp_pon_request_irqs(struct qpnp_pon *pon, struct qpnp_pon_config *cfg)
switch (cfg->pon_type) {
case PON_KPDPWR:
- rc = devm_request_irq(&pon->spmi->dev, cfg->state_irq,
+ rc = devm_request_irq(&pon->pdev->dev, cfg->state_irq,
qpnp_kpdpwr_irq,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
"qpnp_kpdpwr_status", pon);
if (rc < 0) {
- dev_err(&pon->spmi->dev, "Can't request %d IRQ\n",
+ dev_err(&pon->pdev->dev, "Can't request %d IRQ\n",
cfg->state_irq);
return rc;
}
if (cfg->use_bark) {
- rc = devm_request_irq(&pon->spmi->dev, cfg->bark_irq,
+ rc = devm_request_irq(&pon->pdev->dev, cfg->bark_irq,
qpnp_kpdpwr_bark_irq,
IRQF_TRIGGER_RISING,
"qpnp_kpdpwr_bark", pon);
if (rc < 0) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Can't request %d IRQ\n",
cfg->bark_irq);
return rc;
@@ -1132,22 +1126,22 @@ qpnp_pon_request_irqs(struct qpnp_pon *pon, struct qpnp_pon_config *cfg)
}
break;
case PON_RESIN:
- rc = devm_request_irq(&pon->spmi->dev, cfg->state_irq,
+ rc = devm_request_irq(&pon->pdev->dev, cfg->state_irq,
qpnp_resin_irq,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
"qpnp_resin_status", pon);
if (rc < 0) {
- dev_err(&pon->spmi->dev, "Can't request %d IRQ\n",
+ dev_err(&pon->pdev->dev, "Can't request %d IRQ\n",
cfg->state_irq);
return rc;
}
if (cfg->use_bark) {
- rc = devm_request_irq(&pon->spmi->dev, cfg->bark_irq,
+ rc = devm_request_irq(&pon->pdev->dev, cfg->bark_irq,
qpnp_resin_bark_irq,
IRQF_TRIGGER_RISING,
"qpnp_resin_bark", pon);
if (rc < 0) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Can't request %d IRQ\n",
cfg->bark_irq);
return rc;
@@ -1155,24 +1149,24 @@ qpnp_pon_request_irqs(struct qpnp_pon *pon, struct qpnp_pon_config *cfg)
}
break;
case PON_CBLPWR:
- rc = devm_request_irq(&pon->spmi->dev, cfg->state_irq,
+ rc = devm_request_irq(&pon->pdev->dev, cfg->state_irq,
qpnp_cblpwr_irq,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
"qpnp_cblpwr_status", pon);
if (rc < 0) {
- dev_err(&pon->spmi->dev, "Can't request %d IRQ\n",
+ dev_err(&pon->pdev->dev, "Can't request %d IRQ\n",
cfg->state_irq);
return rc;
}
break;
case PON_KPDPWR_RESIN:
if (cfg->use_bark) {
- rc = devm_request_irq(&pon->spmi->dev, cfg->bark_irq,
+ rc = devm_request_irq(&pon->pdev->dev, cfg->bark_irq,
qpnp_kpdpwr_resin_bark_irq,
IRQF_TRIGGER_RISING,
"qpnp_kpdpwr_resin_bark", pon);
if (rc < 0) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Can't request %d IRQ\n",
cfg->bark_irq);
return rc;
@@ -1200,7 +1194,7 @@ qpnp_pon_config_input(struct qpnp_pon *pon, struct qpnp_pon_config *cfg)
if (!pon->pon_input) {
pon->pon_input = input_allocate_device();
if (!pon->pon_input) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Can't allocate pon input device\n");
return -ENOMEM;
}
@@ -1220,17 +1214,17 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
int rc = 0, i = 0, pmic_wd_bark_irq;
struct device_node *pp = NULL;
struct qpnp_pon_config *cfg;
- u8 pmic_type;
- u8 revid_rev4;
+ uint pmic_type;
+ uint revid_rev4;
if (!pon->num_pon_config) {
- dev_dbg(&pon->spmi->dev, "num_pon_config: %d\n",
+ dev_dbg(&pon->pdev->dev, "num_pon_config: %d\n",
pon->num_pon_config);
return 0;
}
/* iterate through the list of pon configs */
- for_each_available_child_of_node(pon->spmi->dev.of_node, pp) {
+ for_each_available_child_of_node(pon->pdev->dev.of_node, pp) {
if (!of_find_property(pp, "qcom,pon-type", NULL))
continue;
@@ -1238,16 +1232,16 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
rc = of_property_read_u32(pp, "qcom,pon-type", &cfg->pon_type);
if (rc) {
- dev_err(&pon->spmi->dev, "PON type not specified\n");
+ dev_err(&pon->pdev->dev, "PON type not specified\n");
return rc;
}
switch (cfg->pon_type) {
case PON_KPDPWR:
- cfg->state_irq = spmi_get_irq_byname(pon->spmi,
- NULL, "kpdpwr");
+ cfg->state_irq = platform_get_irq_byname(pon->pdev,
+ "kpdpwr");
if (cfg->state_irq < 0) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to get kpdpwr irq\n");
return cfg->state_irq;
}
@@ -1257,10 +1251,10 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
if (rc) {
if (rc == -EINVAL) {
- dev_dbg(&pon->spmi->dev,
+ dev_dbg(&pon->pdev->dev,
"'qcom,support-reset' DT property doesn't exist\n");
} else {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read 'qcom,support-reset'\n");
return rc;
}
@@ -1271,10 +1265,11 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
cfg->use_bark = of_property_read_bool(pp,
"qcom,use-bark");
if (cfg->use_bark) {
- cfg->bark_irq = spmi_get_irq_byname(pon->spmi,
- NULL, "kpdpwr-bark");
+ cfg->bark_irq
+ = platform_get_irq_byname(pon->pdev,
+ "kpdpwr-bark");
if (cfg->bark_irq < 0) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to get kpdpwr-bark irq\n");
return cfg->bark_irq;
}
@@ -1296,10 +1291,10 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
break;
case PON_RESIN:
- cfg->state_irq = spmi_get_irq_byname(pon->spmi,
- NULL, "resin");
+ cfg->state_irq = platform_get_irq_byname(pon->pdev,
+ "resin");
if (cfg->state_irq < 0) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to get resin irq\n");
return cfg->bark_irq;
}
@@ -1309,10 +1304,10 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
if (rc) {
if (rc == -EINVAL) {
- dev_dbg(&pon->spmi->dev,
+ dev_dbg(&pon->pdev->dev,
"'qcom,support-reset' DT property doesn't exist\n");
} else {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read 'qcom,support-reset'\n");
return rc;
}
@@ -1323,24 +1318,23 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
cfg->use_bark = of_property_read_bool(pp,
"qcom,use-bark");
- rc = spmi_ext_register_readl(pon->spmi->ctrl,
- pon->spmi->sid, PMIC_VERSION_REG,
- &pmic_type, 1);
+ rc = regmap_read(pon->regmap, PMIC_VERSION_REG,
+ &pmic_type);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read PMIC type\n");
return rc;
}
if (pmic_type == PMIC_VER_8941) {
- rc = spmi_ext_register_readl(pon->spmi->ctrl,
- pon->spmi->sid, PMIC_VERSION_REV4_REG,
- &revid_rev4, 1);
+ rc = regmap_read(pon->regmap,
+ PMIC_VERSION_REV4_REG,
+ &revid_rev4);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read PMIC revision ID\n");
return rc;
}
@@ -1355,10 +1349,11 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
}
if (cfg->use_bark) {
- cfg->bark_irq = spmi_get_irq_byname(pon->spmi,
- NULL, "resin-bark");
+ cfg->bark_irq
+ = platform_get_irq_byname(pon->pdev,
+ "resin-bark");
if (cfg->bark_irq < 0) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to get resin-bark irq\n");
return cfg->bark_irq;
}
@@ -1376,10 +1371,10 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
break;
case PON_CBLPWR:
- cfg->state_irq = spmi_get_irq_byname(pon->spmi,
- NULL, "cblpwr");
+ cfg->state_irq = platform_get_irq_byname(pon->pdev,
+ "cblpwr");
if (cfg->state_irq < 0) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to get cblpwr irq\n");
return rc;
}
@@ -1390,10 +1385,10 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
if (rc) {
if (rc == -EINVAL) {
- dev_dbg(&pon->spmi->dev,
+ dev_dbg(&pon->pdev->dev,
"'qcom,support-reset' DT property doesn't exist\n");
} else {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read 'qcom,support-reset'\n");
return rc;
}
@@ -1404,10 +1399,11 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
cfg->use_bark = of_property_read_bool(pp,
"qcom,use-bark");
if (cfg->use_bark) {
- cfg->bark_irq = spmi_get_irq_byname(pon->spmi,
- NULL, "kpdpwr-resin-bark");
+ cfg->bark_irq
+ = platform_get_irq_byname(pon->pdev,
+ "kpdpwr-resin-bark");
if (cfg->bark_irq < 0) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to get kpdpwr-resin-bark irq\n");
return cfg->bark_irq;
}
@@ -1425,7 +1421,7 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
break;
default:
- dev_err(&pon->spmi->dev, "PON RESET %d not supported",
+ dev_err(&pon->pdev->dev, "PON RESET %d not supported",
cfg->pon_type);
return -EINVAL;
}
@@ -1438,40 +1434,39 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
rc = of_property_read_u32(pp, "qcom,s1-timer",
&cfg->s1_timer);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read s1-timer\n");
return rc;
}
if (cfg->s1_timer > QPNP_PON_S1_TIMER_MAX) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Incorrect S1 debounce time\n");
return -EINVAL;
}
rc = of_property_read_u32(pp, "qcom,s2-timer",
&cfg->s2_timer);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read s2-timer\n");
return rc;
}
if (cfg->s2_timer > QPNP_PON_S2_TIMER_MAX) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Incorrect S2 debounce time\n");
return -EINVAL;
}
rc = of_property_read_u32(pp, "qcom,s2-type",
&cfg->s2_type);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read s2-type\n");
return rc;
}
if (cfg->s2_type > QPNP_PON_RESET_TYPE_MAX) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Incorrect reset type specified\n");
return -EINVAL;
}
-
}
/*
* Get the standard-key parameters. This might not be
@@ -1479,8 +1474,7 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
*/
rc = of_property_read_u32(pp, "linux,code", &cfg->key_code);
if (rc && rc != -EINVAL) {
- dev_err(&pon->spmi->dev,
- "Unable to read key-code\n");
+ dev_err(&pon->pdev->dev, "Unable to read key-code\n");
return rc;
}
/* Register key configuration */
@@ -1492,20 +1486,20 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
/* get the pull-up configuration */
rc = of_property_read_u32(pp, "qcom,pull-up", &cfg->pull_up);
if (rc && rc != -EINVAL) {
- dev_err(&pon->spmi->dev, "Unable to read pull-up\n");
+ dev_err(&pon->pdev->dev, "Unable to read pull-up\n");
return rc;
}
}
- pmic_wd_bark_irq = spmi_get_irq_byname(pon->spmi, NULL, "pmic-wd-bark");
+ pmic_wd_bark_irq = platform_get_irq_byname(pon->pdev, "pmic-wd-bark");
/* request the pmic-wd-bark irq only if it is defined */
if (pmic_wd_bark_irq >= 0) {
- rc = devm_request_irq(&pon->spmi->dev, pmic_wd_bark_irq,
+ rc = devm_request_irq(&pon->pdev->dev, pmic_wd_bark_irq,
qpnp_pmic_wd_bark_irq,
IRQF_TRIGGER_RISING,
"qpnp_pmic_wd_bark", pon);
if (rc < 0) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Can't request %d IRQ\n",
pmic_wd_bark_irq);
goto free_input_dev;
@@ -1516,7 +1510,7 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
if (pon->pon_input) {
rc = input_register_device(pon->pon_input);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Can't register pon key: %d\n", rc);
goto free_input_dev;
}
@@ -1527,7 +1521,7 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
/* Configure the pull-up */
rc = qpnp_config_pull(pon, cfg);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to config pull-up\n");
+ dev_err(&pon->pdev->dev, "Unable to config pull-up\n");
goto unreg_input_dev;
}
@@ -1536,7 +1530,7 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
if (cfg->support_reset) {
rc = qpnp_config_reset(pon, cfg);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to config pon reset\n");
goto unreg_input_dev;
}
@@ -1547,7 +1541,7 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
cfg->s2_cntl2_addr,
QPNP_PON_S2_CNTL_EN, 0);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to disable S2 reset\n");
goto unreg_input_dev;
}
@@ -1557,12 +1551,12 @@ static int qpnp_pon_config_init(struct qpnp_pon *pon)
rc = qpnp_pon_request_irqs(pon, cfg);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to request-irq's\n");
+ dev_err(&pon->pdev->dev, "Unable to request-irq's\n");
goto unreg_input_dev;
}
}
- device_init_wakeup(&pon->spmi->dev, 1);
+ device_init_wakeup(&pon->pdev->dev, 1);
return rc;
@@ -1588,7 +1582,7 @@ static int pon_spare_regulator_enable(struct regulator_dev *rdev)
rc = qpnp_pon_masked_write(pon_reg->pon, pon_reg->pon->base +
pon_reg->addr, value, value);
if (rc)
- dev_err(&pon_reg->pon->spmi->dev, "Unable to write to %x\n",
+ dev_err(&pon_reg->pon->pdev->dev, "Unable to write to %x\n",
pon_reg->pon->base + pon_reg->addr);
else
pon_reg->enabled = true;
@@ -1608,7 +1602,7 @@ static int pon_spare_regulator_disable(struct regulator_dev *rdev)
rc = qpnp_pon_masked_write(pon_reg->pon, pon_reg->pon->base +
pon_reg->addr, mask, 0);
if (rc)
- dev_err(&pon_reg->pon->spmi->dev, "Unable to write to %x\n",
+ dev_err(&pon_reg->pon->pdev->dev, "Unable to write to %x\n",
pon_reg->pon->base + pon_reg->addr);
else
pon_reg->enabled = false;
@@ -1634,7 +1628,7 @@ static int pon_regulator_init(struct qpnp_pon *pon)
struct regulator_init_data *init_data;
struct regulator_config reg_cfg = {};
struct device_node *node = NULL;
- struct device *dev = &pon->spmi->dev;
+ struct device *dev = &pon->pdev->dev;
struct pon_regulator *pon_reg;
if (!pon->num_pon_reg)
@@ -1749,15 +1743,14 @@ static int qpnp_pon_debugfs_uvlo_dload_get(char *buf,
{
struct qpnp_pon *pon = sys_reset_dev;
int rc = 0;
- u8 reg;
+ uint reg;
if (!pon)
return -ENODEV;
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_PON_XVDD_RB_SPARE(pon), &reg, 1);
+ rc = regmap_read(pon->regmap, QPNP_PON_XVDD_RB_SPARE(pon), &reg);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read addr=%x, rc(%d)\n",
QPNP_PON_XVDD_RB_SPARE(pon), rc);
return rc;
@@ -1772,7 +1765,7 @@ static int qpnp_pon_debugfs_uvlo_dload_set(const char *val,
{
struct qpnp_pon *pon = sys_reset_dev;
int rc = 0;
- u8 reg;
+ uint reg;
if (!pon)
return -ENODEV;
@@ -1783,10 +1776,9 @@ static int qpnp_pon_debugfs_uvlo_dload_set(const char *val,
return rc;
}
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_PON_XVDD_RB_SPARE(pon), &reg, 1);
+ rc = regmap_read(pon->regmap, QPNP_PON_XVDD_RB_SPARE(pon), &reg);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read addr=%x, rc(%d)\n",
QPNP_PON_XVDD_RB_SPARE(pon), rc);
return rc;
@@ -1796,10 +1788,9 @@ static int qpnp_pon_debugfs_uvlo_dload_set(const char *val,
if (*(bool *)kp->arg)
reg |= QPNP_PON_UVLO_DLOAD_EN;
- rc = spmi_ext_register_writel(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_PON_XVDD_RB_SPARE(pon), &reg, 1);
+ rc = regmap_write(pon->regmap, QPNP_PON_XVDD_RB_SPARE(pon), reg);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to write to addr=%hx, rc(%d)\n",
QPNP_PON_XVDD_RB_SPARE(pon), rc);
return rc;
@@ -1841,36 +1832,38 @@ static int qpnp_pon_debugfs_uvlo_set(void *data, u64 val)
DEFINE_SIMPLE_ATTRIBUTE(qpnp_pon_debugfs_uvlo_fops, qpnp_pon_debugfs_uvlo_get,
qpnp_pon_debugfs_uvlo_set, "0x%02llx\n");
-static void qpnp_pon_debugfs_init(struct spmi_device *spmi)
+static void qpnp_pon_debugfs_init(struct platform_device *pdev)
{
- struct qpnp_pon *pon = dev_get_drvdata(&spmi->dev);
+ struct qpnp_pon *pon = dev_get_drvdata(&pdev->dev);
struct dentry *ent;
- pon->debugfs = debugfs_create_dir(dev_name(&spmi->dev), NULL);
+ pon->debugfs = debugfs_create_dir(dev_name(&pdev->dev), NULL);
if (!pon->debugfs) {
- dev_err(&pon->spmi->dev, "Unable to create debugfs directory\n");
+ dev_err(&pon->pdev->dev,
+ "Unable to create debugfs directory\n");
} else {
ent = debugfs_create_file("uvlo_panic",
S_IFREG | S_IWUSR | S_IRUGO,
pon->debugfs, pon, &qpnp_pon_debugfs_uvlo_fops);
if (!ent)
- dev_err(&pon->spmi->dev, "Unable to create uvlo_panic debugfs file.\n");
+ dev_err(&pon->pdev->dev,
+ "Unable to create uvlo_panic debugfs file.\n");
}
}
-static void qpnp_pon_debugfs_remove(struct spmi_device *spmi)
+static void qpnp_pon_debugfs_remove(struct platform_device *pdev)
{
- struct qpnp_pon *pon = dev_get_drvdata(&spmi->dev);
+ struct qpnp_pon *pon = dev_get_drvdata(&pdev->dev);
debugfs_remove_recursive(pon->debugfs);
}
#else
-static void qpnp_pon_debugfs_init(struct spmi_device *spmi)
+static void qpnp_pon_debugfs_init(struct platform_device *pdev)
{}
-static void qpnp_pon_debugfs_remove(struct spmi_device *spmi)
+static void qpnp_pon_debugfs_remove(struct platform_device *pdev)
{}
#endif
@@ -1878,96 +1871,104 @@ static int read_gen2_pon_off_reason(struct qpnp_pon *pon, u16 *reason,
int *reason_index_offset)
{
int rc;
- u8 buf[2], reg;
+ int buf[2], reg;
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_PON_OFF_REASON(pon),
- &reg, 1);
+ rc = regmap_read(pon->regmap,
+ QPNP_PON_OFF_REASON(pon),
+ &reg);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to read PON_OFF_REASON reg rc:%d\n",
+ dev_err(&pon->pdev->dev, "Unable to read PON_OFF_REASON reg rc:%d\n",
rc);
return rc;
}
if (reg & QPNP_GEN2_POFF_SEQ) {
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_POFF_REASON1(pon),
- buf, 1);
+ rc = regmap_read(pon->regmap,
+ QPNP_POFF_REASON1(pon),
+ buf);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to read POFF_REASON1 reg rc:%d\n",
+ dev_err(&pon->pdev->dev, "Unable to read POFF_REASON1 reg rc:%d\n",
rc);
return rc;
}
- *reason = buf[0];
+ *reason = (u8)buf[0];
*reason_index_offset = 0;
} else if (reg & QPNP_GEN2_FAULT_SEQ) {
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_FAULT_REASON1(pon),
- buf, 2);
+ rc = regmap_bulk_read(pon->regmap,
+ QPNP_FAULT_REASON1(pon),
+ buf, 2);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to read FAULT_REASON regs rc:%d\n",
+ dev_err(&pon->pdev->dev, "Unable to read FAULT_REASON regs rc:%d\n",
rc);
return rc;
}
- *reason = buf[0] | (buf[1] << 8);
+ *reason = (u8)buf[0] | (u16)(buf[1] << 8);
*reason_index_offset = POFF_REASON_FAULT_OFFSET;
} else if (reg & QPNP_GEN2_S3_RESET_SEQ) {
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_S3_RESET_REASON(pon),
- buf, 1);
+ rc = regmap_read(pon->regmap,
+ QPNP_S3_RESET_REASON(pon),
+ buf);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to read S3_RESET_REASON reg rc:%d\n",
+ dev_err(&pon->pdev->dev, "Unable to read S3_RESET_REASON reg rc:%d\n",
rc);
return rc;
}
- *reason = buf[0];
+ *reason = (u8)buf[0];
*reason_index_offset = POFF_REASON_S3_RESET_OFFSET;
}
return 0;
}
-static int qpnp_pon_probe(struct spmi_device *spmi)
+static int qpnp_pon_probe(struct platform_device *pdev)
{
struct qpnp_pon *pon;
- struct resource *pon_resource;
+ unsigned int base;
struct device_node *node = NULL;
u32 delay = 0, s3_debounce = 0;
int rc, sys_reset, index;
int reason_index_offset = 0;
- u8 pon_sts = 0, buf[2];
+ u8 buf[2];
+ uint pon_sts = 0;
u16 poff_sts = 0;
const char *s3_src;
u8 s3_src_reg;
unsigned long flags;
+ uint temp = 0;
- pon = devm_kzalloc(&spmi->dev, sizeof(struct qpnp_pon),
- GFP_KERNEL);
- if (!pon) {
- dev_err(&spmi->dev, "Can't allocate qpnp_pon\n");
+ pon = devm_kzalloc(&pdev->dev, sizeof(struct qpnp_pon), GFP_KERNEL);
+ if (!pon)
return -ENOMEM;
+
+ pon->regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ if (!pon->regmap) {
+ dev_err(&pdev->dev, "Couldn't get parent's regmap\n");
+ return -EINVAL;
}
- sys_reset = of_property_read_bool(spmi->dev.of_node,
+ sys_reset = of_property_read_bool(pdev->dev.of_node,
"qcom,system-reset");
if (sys_reset && sys_reset_dev) {
- dev_err(&spmi->dev, "qcom,system-reset property can only be specified for one device on the system\n");
+ dev_err(&pdev->dev,
+ "qcom,system-reset property can only be specified for one device on the system\n");
return -EINVAL;
} else if (sys_reset) {
sys_reset_dev = pon;
}
- pon->spmi = spmi;
+ pon->pdev = pdev;
- pon_resource = spmi_get_resource(spmi, NULL, IORESOURCE_MEM, 0);
- if (!pon_resource) {
- dev_err(&spmi->dev, "Unable to get PON base address\n");
- return -ENXIO;
+ rc = of_property_read_u32(pdev->dev.of_node, "reg", &base);
+ if (rc < 0) {
+ dev_err(&pdev->dev,
+ "Couldn't find reg in node = %s rc = %d\n",
+ pdev->dev.of_node->full_name, rc);
+ return rc;
}
- pon->base = pon_resource->start;
+ pon->base = base;
/* get the total number of pon configurations */
- for_each_available_child_of_node(spmi->dev.of_node, node) {
+ for_each_available_child_of_node(pdev->dev.of_node, node) {
if (of_find_property(node, "regulator-name", NULL)) {
pon->num_pon_reg++;
} else if (of_find_property(node, "qcom,pon-type", NULL)) {
@@ -1979,43 +1980,47 @@ static int qpnp_pon_probe(struct spmi_device *spmi)
}
pr_debug("PON@SID %d: num_pon_config: %d num_pon_reg: %d\n",
- pon->spmi->sid, pon->num_pon_config, pon->num_pon_reg);
+ to_spmi_device(pon->pdev->dev.parent)->usid,
+ pon->num_pon_config, pon->num_pon_reg);
rc = pon_regulator_init(pon);
if (rc) {
- dev_err(&pon->spmi->dev, "Error in pon_regulator_init rc: %d\n",
+ dev_err(&pdev->dev, "Error in pon_regulator_init rc: %d\n",
rc);
return rc;
}
if (!pon->num_pon_config)
/* No PON config., do not register the driver */
- dev_info(&spmi->dev, "No PON config. specified\n");
+ dev_info(&pdev->dev, "No PON config. specified\n");
else
- pon->pon_cfg = devm_kzalloc(&spmi->dev,
+ pon->pon_cfg = devm_kzalloc(&pdev->dev,
sizeof(struct qpnp_pon_config) *
pon->num_pon_config, GFP_KERNEL);
/* Read PON_PERPH_SUBTYPE register to get PON type */
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
+ rc = regmap_read(pon->regmap,
QPNP_PON_PERPH_SUBTYPE(pon),
- &pon->subtype, 1);
+ &temp);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read PON_PERPH_SUBTYPE register rc: %d\n",
rc);
return rc;
}
+ pon->subtype = temp;
/* Check if it is rev B */
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_PON_REVISION2(pon), &pon->pon_ver, 1);
+ rc = regmap_read(pon->regmap,
+ QPNP_PON_REVISION2(pon), &temp);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to read addr=%x, rc(%d)\n",
QPNP_PON_REVISION2(pon), rc);
return rc;
}
+
+ pon->pon_ver = temp;
if (is_pon_gen1(pon)) {
if (pon->pon_ver == 0)
pon->pon_ver = QPNP_PON_GEN1_V1;
@@ -2026,7 +2031,7 @@ static int qpnp_pon_probe(struct spmi_device *spmi)
} else if (pon->subtype == PON_1REG) {
pon->pon_ver = QPNP_PON_GEN1_V2;
} else {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Invalid PON_PERPH_SUBTYPE value %x\n",
pon->subtype);
return -EINVAL;
@@ -2037,17 +2042,17 @@ static int qpnp_pon_probe(struct spmi_device *spmi)
rc = qpnp_pon_store_and_clear_warm_reset(pon);
if (rc) {
- dev_err(&pon->spmi->dev,
+ dev_err(&pon->pdev->dev,
"Unable to store/clear WARM_RESET_REASONx registers rc: %d\n",
rc);
return rc;
}
/* PON reason */
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_PON_REASON1(pon), &pon_sts, 1);
+ rc = regmap_read(pon->regmap, QPNP_PON_REASON1(pon), &pon_sts);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to read PON_REASON1 reg rc: %d\n",
+ dev_err(&pon->pdev->dev,
+ "Unable to read PON_RESASON1 reg rc: %d\n",
rc);
return rc;
}
@@ -2055,14 +2060,16 @@ static int qpnp_pon_probe(struct spmi_device *spmi)
index = ffs(pon_sts) - 1;
cold_boot = !qpnp_pon_is_warm_reset();
if (index >= ARRAY_SIZE(qpnp_pon_reason) || index < 0) {
- dev_info(&pon->spmi->dev,
+ dev_info(&pon->pdev->dev,
"PMIC@SID%d Power-on reason: Unknown and '%s' boot\n",
- pon->spmi->sid, cold_boot ? "cold" : "warm");
+ to_spmi_device(pon->pdev->dev.parent)->usid,
+ cold_boot ? "cold" : "warm");
} else {
pon->pon_trigger_reason = index;
- dev_info(&pon->spmi->dev,
+ dev_info(&pon->pdev->dev,
"PMIC@SID%d Power-on reason: %s and '%s' boot\n",
- pon->spmi->sid, qpnp_pon_reason[index],
+ to_spmi_device(pon->pdev->dev.parent)->usid,
+ qpnp_pon_reason[index],
cold_boot ? "cold" : "warm");
}
@@ -2073,11 +2080,10 @@ static int qpnp_pon_probe(struct spmi_device *spmi)
if (rc)
return rc;
} else {
- rc = spmi_ext_register_readl(pon->spmi->ctrl, pon->spmi->sid,
- QPNP_POFF_REASON1(pon),
- buf, 2);
+ rc = regmap_bulk_read(pon->regmap, QPNP_POFF_REASON1(pon),
+ buf, 2);
if (rc) {
- dev_err(&pon->spmi->dev, "Unable to read POFF_REASON regs rc:%d\n",
+ dev_err(&pon->pdev->dev, "Unable to read POFF_REASON regs rc:%d\n",
rc);
return rc;
}
@@ -2085,36 +2091,37 @@ static int qpnp_pon_probe(struct spmi_device *spmi)
}
index = ffs(poff_sts) - 1 + reason_index_offset;
if (index >= ARRAY_SIZE(qpnp_poff_reason) || index < 0) {
- dev_info(&pon->spmi->dev,
+ dev_info(&pon->pdev->dev,
"PMIC@SID%d: Unknown power-off reason\n",
- pon->spmi->sid);
+ to_spmi_device(pon->pdev->dev.parent)->usid);
} else {
pon->pon_power_off_reason = index;
- dev_info(&pon->spmi->dev,
+ dev_info(&pon->pdev->dev,
"PMIC@SID%d: Power-off reason: %s\n",
- pon->spmi->sid,
+ to_spmi_device(pon->pdev->dev.parent)->usid,
qpnp_poff_reason[index]);
}
if (pon->pon_trigger_reason == PON_SMPL ||
pon->pon_power_off_reason == QPNP_POFF_REASON_UVLO) {
- if (of_property_read_bool(spmi->dev.of_node,
+ if (of_property_read_bool(pdev->dev.of_node,
"qcom,uvlo-panic"))
panic("An UVLO was occurred.");
}
/* program s3 debounce */
- rc = of_property_read_u32(pon->spmi->dev.of_node,
+ rc = of_property_read_u32(pon->pdev->dev.of_node,
"qcom,s3-debounce", &s3_debounce);
if (rc) {
if (rc != -EINVAL) {
- dev_err(&pon->spmi->dev, "Unable to read s3 timer rc:%d\n",
+ dev_err(&pon->pdev->dev,
+ "Unable to read s3 timer rc:%d\n",
rc);
return rc;
}
} else {
if (s3_debounce > QPNP_PON_S3_TIMER_SECS_MAX) {
- dev_info(&pon->spmi->dev,
+ dev_info(&pon->pdev->dev,
"Exceeded S3 max value, set it to max\n");
s3_debounce = QPNP_PON_S3_TIMER_SECS_MAX;
}
@@ -2127,7 +2134,7 @@ static int qpnp_pon_probe(struct spmi_device *spmi)
rc = qpnp_pon_masked_write(pon, QPNP_PON_SEC_ACCESS(pon),
0xFF, QPNP_PON_SEC_UNLOCK);
if (rc) {
- dev_err(&spmi->dev, "Unable to do SEC_ACCESS rc:%d\n",
+ dev_err(&pdev->dev, "Unable to do SEC_ACCESS rc:%d\n",
rc);
return rc;
}
@@ -2135,7 +2142,8 @@ static int qpnp_pon_probe(struct spmi_device *spmi)
rc = qpnp_pon_masked_write(pon, QPNP_PON_S3_DBC_CTL(pon),
QPNP_PON_S3_DBC_DELAY_MASK, s3_debounce);
if (rc) {
- dev_err(&spmi->dev, "Unable to set S3 debounce rc:%d\n",
+ dev_err(&pdev->dev,
+ "Unable to set S3 debounce rc:%d\n",
rc);
return rc;
}
@@ -2143,10 +2151,10 @@ static int qpnp_pon_probe(struct spmi_device *spmi)
/* program s3 source */
s3_src = "kpdpwr-and-resin";
- rc = of_property_read_string(pon->spmi->dev.of_node,
+ rc = of_property_read_string(pon->pdev->dev.of_node,
"qcom,s3-src", &s3_src);
if (rc && rc != -EINVAL) {
- dev_err(&pon->spmi->dev, "Unable to read s3 timer rc: %d\n",
+ dev_err(&pon->pdev->dev, "Unable to read s3 timer rc: %d\n",
rc);
return rc;
}
@@ -2168,27 +2176,29 @@ static int qpnp_pon_probe(struct spmi_device *spmi)
rc = qpnp_pon_masked_write(pon, QPNP_PON_S3_SRC(pon),
QPNP_PON_S3_SRC_MASK, s3_src_reg);
if (rc) {
- dev_err(&spmi->dev, "Unable to program s3 source rc: %d\n", rc);
+ dev_err(&pdev->dev, "Unable to program s3 source rc: %d\n",
+ rc);
return rc;
}
- dev_set_drvdata(&spmi->dev, pon);
+ dev_set_drvdata(&pdev->dev, pon);
INIT_DELAYED_WORK(&pon->bark_work, bark_work_func);
/* register the PON configurations */
rc = qpnp_pon_config_init(pon);
if (rc) {
- dev_err(&spmi->dev,
+ dev_err(&pdev->dev,
"Unable to initialize PON configurations rc: %d\n", rc);
return rc;
}
- rc = of_property_read_u32(pon->spmi->dev.of_node,
+ rc = of_property_read_u32(pon->pdev->dev.of_node,
"qcom,pon-dbc-delay", &delay);
if (rc) {
if (rc != -EINVAL) {
- dev_err(&spmi->dev, "Unable to read debounce delay rc: %d\n",
+ dev_err(&pdev->dev,
+ "Unable to read debounce delay rc: %d\n",
rc);
return rc;
}
@@ -2196,65 +2206,65 @@ static int qpnp_pon_probe(struct spmi_device *spmi)
rc = qpnp_pon_set_dbc(pon, delay);
}
- rc = of_property_read_u32(pon->spmi->dev.of_node,
+ rc = of_property_read_u32(pon->pdev->dev.of_node,
"qcom,warm-reset-poweroff-type",
&pon->warm_reset_poff_type);
if (rc) {
if (rc != -EINVAL) {
- dev_err(&spmi->dev, "Unable to read warm reset poweroff type rc: %d\n",
+ dev_err(&pdev->dev, "Unable to read warm reset poweroff type rc: %d\n",
rc);
return rc;
}
pon->warm_reset_poff_type = -EINVAL;
} else if (pon->warm_reset_poff_type <= PON_POWER_OFF_RESERVED ||
pon->warm_reset_poff_type >= PON_POWER_OFF_MAX_TYPE) {
- dev_err(&spmi->dev, "Invalid warm-reset-poweroff-type\n");
+ dev_err(&pdev->dev, "Invalid warm-reset-poweroff-type\n");
pon->warm_reset_poff_type = -EINVAL;
}
- rc = of_property_read_u32(pon->spmi->dev.of_node,
+ rc = of_property_read_u32(pon->pdev->dev.of_node,
"qcom,hard-reset-poweroff-type",
&pon->hard_reset_poff_type);
if (rc) {
if (rc != -EINVAL) {
- dev_err(&spmi->dev, "Unable to read hard reset poweroff type rc: %d\n",
+ dev_err(&pdev->dev, "Unable to read hard reset poweroff type rc: %d\n",
rc);
return rc;
}
pon->hard_reset_poff_type = -EINVAL;
} else if (pon->hard_reset_poff_type <= PON_POWER_OFF_RESERVED ||
pon->hard_reset_poff_type >= PON_POWER_OFF_MAX_TYPE) {
- dev_err(&spmi->dev, "Invalid hard-reset-poweroff-type\n");
+ dev_err(&pdev->dev, "Invalid hard-reset-poweroff-type\n");
pon->hard_reset_poff_type = -EINVAL;
}
- rc = of_property_read_u32(pon->spmi->dev.of_node,
+ rc = of_property_read_u32(pon->pdev->dev.of_node,
"qcom,shutdown-poweroff-type",
&pon->shutdown_poff_type);
if (rc) {
if (rc != -EINVAL) {
- dev_err(&spmi->dev, "Unable to read shutdown poweroff type rc: %d\n",
+ dev_err(&pdev->dev, "Unable to read shutdown poweroff type rc: %d\n",
rc);
return rc;
}
pon->shutdown_poff_type = -EINVAL;
} else if (pon->shutdown_poff_type <= PON_POWER_OFF_RESERVED ||
pon->shutdown_poff_type >= PON_POWER_OFF_MAX_TYPE) {
- dev_err(&spmi->dev, "Invalid shutdown-poweroff-type\n");
+ dev_err(&pdev->dev, "Invalid shutdown-poweroff-type\n");
pon->shutdown_poff_type = -EINVAL;
}
- rc = device_create_file(&spmi->dev, &dev_attr_debounce_us);
+ rc = device_create_file(&pdev->dev, &dev_attr_debounce_us);
if (rc) {
- dev_err(&spmi->dev, "sys file creation failed rc: %d\n",
- rc);
+ dev_err(&pdev->dev, "sys file creation failed rc: %d\n", rc);
return rc;
}
- if (of_property_read_bool(spmi->dev.of_node,
+ if (of_property_read_bool(pdev->dev.of_node,
"qcom,secondary-pon-reset")) {
if (sys_reset) {
- dev_err(&spmi->dev, "qcom,system-reset property shouldn't be used along with qcom,secondary-pon-reset property\n");
+ dev_err(&pdev->dev,
+ "qcom,system-reset property shouldn't be used along with qcom,secondary-pon-reset property\n");
return -EINVAL;
}
spin_lock_irqsave(&spon_list_slock, flags);
@@ -2266,26 +2276,25 @@ static int qpnp_pon_probe(struct spmi_device *spmi)
}
/* config whether store the hard reset reason */
- pon->store_hard_reset_reason = of_property_read_bool(
- spmi->dev.of_node,
+ pon->store_hard_reset_reason = of_property_read_bool(pdev->dev.of_node,
"qcom,store-hard-reset-reason");
- qpnp_pon_debugfs_init(spmi);
+ qpnp_pon_debugfs_init(pdev);
return 0;
}
-static int qpnp_pon_remove(struct spmi_device *spmi)
+static int qpnp_pon_remove(struct platform_device *pdev)
{
- struct qpnp_pon *pon = dev_get_drvdata(&spmi->dev);
+ struct qpnp_pon *pon = dev_get_drvdata(&pdev->dev);
unsigned long flags;
- device_remove_file(&spmi->dev, &dev_attr_debounce_us);
+ device_remove_file(&pdev->dev, &dev_attr_debounce_us);
cancel_delayed_work_sync(&pon->bark_work);
if (pon->pon_input)
input_unregister_device(pon->pon_input);
- qpnp_pon_debugfs_remove(spmi);
+ qpnp_pon_debugfs_remove(pdev);
if (pon->is_spon) {
spin_lock_irqsave(&spon_list_slock, flags);
list_del(&pon->list);
@@ -2299,10 +2308,10 @@ static struct of_device_id spmi_match_table[] = {
{}
};
-static struct spmi_driver qpnp_pon_driver = {
+static struct platform_driver qpnp_pon_driver = {
.driver = {
- .name = "qcom,qpnp-power-on",
- .of_match_table = spmi_match_table,
+ .name = "qcom,qpnp-power-on",
+ .of_match_table = spmi_match_table,
},
.probe = qpnp_pon_probe,
.remove = qpnp_pon_remove,
@@ -2310,13 +2319,13 @@ static struct spmi_driver qpnp_pon_driver = {
static int __init qpnp_pon_init(void)
{
- return spmi_driver_register(&qpnp_pon_driver);
+ return platform_driver_register(&qpnp_pon_driver);
}
subsys_initcall(qpnp_pon_init);
static void __exit qpnp_pon_exit(void)
{
- return spmi_driver_unregister(&qpnp_pon_driver);
+ return platform_driver_unregister(&qpnp_pon_driver);
}
module_exit(qpnp_pon_exit);
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-26 18:12:09 +0000