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| author | Srinivas Ramana <sramana@codeaurora.org> | 2016-11-30 13:29:21 +0530 |
|---|---|---|
| committer | Srinivas Ramana <sramana@codeaurora.org> | 2016-12-02 14:13:19 +0530 |
| commit | f443c3468818e97154b5a537a923a60f314e59b0 (patch) | |
| tree | fb2be3d21a68a091e4d09d7b584230e024deaab7 /tools/perf/scripts/python/syscall-counts.py | |
| parent | c3f3cfdb7f56ad40c33dc306083872c9e8b0c615 (diff) | |
ARM: dts: msm: Add cpu cache nodes for msmtriton
Add cpu cache nodes to represent the cache hierarchy and
to specify the dump size of each cache.
While at it also add the cache dump nodes which will enable
reserving the memory for cache dumps.
Change-Id: I1d80ac853eb283c411985ceebd0dc31ed046836a
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions