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| author | Srinivas Ramana <sramana@codeaurora.org> | 2016-11-16 16:51:55 +0530 |
|---|---|---|
| committer | Srinivas Ramana <sramana@codeaurora.org> | 2016-12-01 18:47:00 +0530 |
| commit | c3f3cfdb7f56ad40c33dc306083872c9e8b0c615 (patch) | |
| tree | 74a66159bcca95a5a403ed2938754199361e3034 /tools/perf/scripts/python/syscall-counts.py | |
| parent | a27b2f17890884a05b18ae69c7eae079cdde4b16 (diff) | |
ARM: dts: msm: Add cpu cache nodes for msmfalcon
Add cpu cache nodes to represent the cache hierarchy and
to specify the dump size of each cache.
While at it also add the cache dump nodes which will enable
reserving the memory for cache dumps.
Change-Id: I06eead417b77c74a6e12e6f6b5251c0c7e62c96b
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions