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| author | Chandan Uddaraju <chandanu@codeaurora.org> | 2016-11-08 12:12:04 -0800 |
|---|---|---|
| committer | Chandan Uddaraju <chandanu@codeaurora.org> | 2016-11-08 17:01:39 -0800 |
| commit | fa8b3ea588393dd1e40fdd29c4bd3cd1c33fbc55 (patch) | |
| tree | 18640d1b7c433cf6ace172ee42ccc17daa4e8d5e /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | 85700def840db9686a220416cbca746f9cfac01d (diff) | |
clk: msm: mdss: fix divider configuration for 5.4 Ghz link rate
Update the FRAC_START3 register settings for 5.4 GHz link
rate in Display-Port PLL driver. This is needed for accurate
link and pixel clock values.
Change-Id: Ib6a0ee570fe2d5a1d43296e792a354ca25b1d82c
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions