diff options
| author | Chandan Uddaraju <chandanu@codeaurora.org> | 2016-11-08 12:12:04 -0800 |
|---|---|---|
| committer | Chandan Uddaraju <chandanu@codeaurora.org> | 2016-11-08 17:01:39 -0800 |
| commit | fa8b3ea588393dd1e40fdd29c4bd3cd1c33fbc55 (patch) | |
| tree | 18640d1b7c433cf6ace172ee42ccc17daa4e8d5e | |
| parent | 85700def840db9686a220416cbca746f9cfac01d (diff) | |
clk: msm: mdss: fix divider configuration for 5.4 Ghz link rate
Update the FRAC_START3 register settings for 5.4 GHz link
rate in Display-Port PLL driver. This is needed for accurate
link and pixel clock values.
Change-Id: Ib6a0ee570fe2d5a1d43296e792a354ca25b1d82c
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
| -rw-r--r-- | drivers/clk/msm/mdss/mdss-dp-pll-cobalt-util.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/msm/mdss/mdss-dp-pll-cobalt-util.c b/drivers/clk/msm/mdss/mdss-dp-pll-cobalt-util.c index a574a9cd2b5a..ea972ec11593 100644 --- a/drivers/clk/msm/mdss/mdss-dp-pll-cobalt-util.c +++ b/drivers/clk/msm/mdss/mdss-dp-pll-cobalt-util.c @@ -275,7 +275,7 @@ int dp_config_vco_rate(struct dp_pll_vco_clk *vco, unsigned long rate) MDSS_PLL_REG_W(dp_res->pll_base, QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00); MDSS_PLL_REG_W(dp_res->pll_base, - QSERDES_COM_DIV_FRAC_START3_MODE0, 0xa0); + QSERDES_COM_DIV_FRAC_START3_MODE0, 0x0a); MDSS_PLL_REG_W(dp_res->pll_base, QSERDES_COM_CMN_CONFIG, 0x12); MDSS_PLL_REG_W(dp_res->pll_base, |