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authorVikash Garodia <vgarodia@codeaurora.org>2017-02-17 13:07:39 +0530
committerVikash Garodia <vgarodia@codeaurora.org>2017-02-17 13:22:48 +0530
commit23ed5efc60cc59b6b8d251f3844155fa5df6ed9e (patch)
treeb0df2a06d6ce9b30cd91914e4beffb69602fb010 /kernel/trace/trace_functions_graph.c
parent2aa89ab3ff59a788321bc6af782d639cfc8dab1f (diff)
ARM: dts: msm: Fix DCVS load for SDM660
DCVS table specifies the low and high load interms of mbs per sec. Clock frequency is derived from this load alongwith cycles required per mb. For starlord, the DCVS low load was incorrect which made the decoder session to run in SVS instead of SVS+. The change now fix it to proper load. Change-Id: I46dd772aa349b94a75472477e24cabe80c088165 CRs-Fixed: 2007776 Signed-off-by: Vikash Garodia <vgarodia@codeaurora.org>
Diffstat (limited to 'kernel/trace/trace_functions_graph.c')
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