diff options
| author | Vikash Garodia <vgarodia@codeaurora.org> | 2017-02-17 13:07:39 +0530 |
|---|---|---|
| committer | Vikash Garodia <vgarodia@codeaurora.org> | 2017-02-17 13:22:48 +0530 |
| commit | 23ed5efc60cc59b6b8d251f3844155fa5df6ed9e (patch) | |
| tree | b0df2a06d6ce9b30cd91914e4beffb69602fb010 | |
| parent | 2aa89ab3ff59a788321bc6af782d639cfc8dab1f (diff) | |
ARM: dts: msm: Fix DCVS load for SDM660
DCVS table specifies the low and high load interms
of mbs per sec. Clock frequency is derived from
this load alongwith cycles required per mb. For
starlord, the DCVS low load was incorrect which
made the decoder session to run in SVS instead
of SVS+. The change now fix it to proper load.
Change-Id: I46dd772aa349b94a75472477e24cabe80c088165
CRs-Fixed: 2007776
Signed-off-by: Vikash Garodia <vgarodia@codeaurora.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/sdm660-vidc.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/qcom/sdm660-vidc.dtsi b/arch/arm/boot/dts/qcom/sdm660-vidc.dtsi index 82e6a5be4d10..5f8def7d233f 100644 --- a/arch/arm/boot/dts/qcom/sdm660-vidc.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-vidc.dtsi @@ -43,7 +43,7 @@ qcom,dcvs-tbl = /* Dec UHD@30 All decoder - NOM to SVS+ */ - <897600 734400 979200 0x3f00000c>, + <897600 783360 979200 0x3f00000c>, /* Dec DCI@24 HEVC - NOM to SVS+ */ <816000 734400 829440 0x0c000000>, |