Promotion of kernel.lnx.4.4-161227.

CRs      Change ID                                   Subject
--------------------------------------------------------------------------------------------------------------
1104858   I482bbf480d4129cdc6a1dfe08f37a1ec56c3131e   clk: qcom: Add FORCE_ENABLE_RCGR & CLK_ENABLE_HAND_OFF f
1104679   I53ac153ba9f7ae81bb0657b17e0e798fd3fe4f48   power_supply: Add SOC_REPORTING_READY property
1104679   I415e322e99bacd61c4e9ac921643d87d3eec4b3e   power: qpnp-fg-gen3: add SOC_REPORTING_READY property
1068294   I779074d0aba35827e1a8264385149967cb9973f3   regulator: cpr4-mmss: Add mmss CPR platform specific dri
1105323   I073ab59cc4ef1b71545a9e77b76d94f09d659aac   msm_11ad: Add option to enable SMMU fastmap
1102641   I39a1266f4158e71238f374b6cba49e1a8c2b1a3b   leds: qpnp-wled: Update WLED config
1104760   I2f9b4e9d45f95066ec93bb5fab179a14bc2c62ee   power: reset: Store KASLR offset in IMEM
986540   I711354941b4168f3f6ffe2d29185597bdad4da89   spi: spi_qsd: Fix the register peek/poke debug feature
1102726   I806456737485dfcbca8a71d59db0927bbd843708   clk: qcom: add MDSS PLL support for msmfalcon
1093863   I47cfe2cd7d93ba5db57365cf250c600dac22bab1   i2c-msm-v2:Synchronise runtime PM callback operations
1102841   I2661a639c19dd451f22c9a29d7d75d9b3fb98114   msm: mdss: Initialize mdss v3 pp driver ops for msmfalco
1101084   I334fd782a2c5d604cafb94f44832d9c700891ba2   msm: thermal: Update error handling of device offline
1105169   Ib089e7ddd38d0d15285ed65c8a29039451cfc3c5   ARM: dts: msm: Add initial support for msm8998 QRD SKUK
1104865   Ib1291524c53c4ec757a494a1e08cb0925720e1a6   msm: rtb: record counter timestamp for every log record
1081961   I5680dc5333c9664e1316c29a91e29231f15eb4f1   defconfig: msm: Add support for CPU OSM clock
1094763   Ifd41990058f8bbce8ba488770ffbfcd9b6067ad6   ASoC: msm: add support for WCD interrupt config via LPI
1103739   Ie5474c42ccdd88df4c101b2113ca8d924eddf037   usb: phy: qusb2: Switch to SE clk from diff clk upon sus
1068294   I2111fe55c9335d57ac91f18f4a4fb3689d80660d   defconfig: Compile GFX LDO regulator driver for msmfalco
1046799   I47db9f66c95846dbff882f631b915655c33c3d55   spi: spi_qsd: Don't restrict first transfer in FIFO mode
1104607   Ie85f7ede2d91767d0d5d20c90a481e6365ad7189   ARM: dts: msm: Add thermal mitigation properties to msmt
1104981   I476397d88e0f9d2b32ae375afc6f15eca4b9ec95   ARM: dts: msm: Add initial support for msm8998 QRD SKUK
1098662   I214bb19385f855af61da628fdf1cf7efc5dd08d6   msm: mdss: dp: fix calculation of link rate
1102900   Ide652165711eec23644d36837f3847d896293709   msm: mdss: Add mdss capabilities for msmfalcon
1104876   I9a707d953a85c16c9c5be82fd36960b49da36e3c   smcinvoke: support listener service request
1104976   Ic8c9657752271026d796ecd6c3b9f9f46f831f37   ARM: dts: msm: update icnss device node for msm8998-inte
1052835   I7f1419c8f7fd7c371767f6921afe0cd8cfaad18f   msm: camera: Change %p into %pK
1081961   I0aca021e51ef9ae59dedce855430a63937eb98c6   ARM: dts: msm: Add support for CPU clocks for msmfalcon
1076516   I290ec786bbe5c45873265ea74290eefcd3d16cb1   msm: mdss: dp: add support for PHY compliance tests
1100632   Iab69062336966e61683117a17974f46cd8f513aa   ARM: dts: msm: Allocate memory for diag client for msmfa
1103405   Iaaa69a56f13db9304640f115863bb882c72551a8   ARM: dts: msm: Update VA range for venus_ns and modify c
1083444   Ie2702223379b9c77ce4fe30376d446c63223dbc8   diag: dci: Fix possible dangling reference
1102776   I77f8e6de6f1b5c447a3516380c51db9c7129d2f3   spcom: abort any read() operation on SSR
1094456   Ib5247f6bceb1f555c03103f061af089755b2de62   clk: introduce CLK_ENABLE_HAND_OFF flag
1094763   Ib17d8bbd5894be5fbf3fa0cafdbec958abc42649   ARM: dts: msm: Enable audio internal codec nodes for msm
1103891   Iec6247a69c3258660eae398d6e3fe8215e3f254a   ARM: dts: msm: Add TP device node into msm8998 interpose
1104880 868394   I885ae66be2d8cca17bcc0b87b7635a71c734e4b2   usb/xhci: Add support for EHSET tests for host complianc
1094456   I7d527571c2eb4d53d58d82126989bd673de12e2d   clk: move check for CLK_ENABLE_HAND_OFF at unused tree
1093271   I472449c52bff40d48f7d65b05e145cc47cba9357   msm: crypto: fix AEAD issues for HW crypto driver on msm
1105038   I45d13b40fab9bf6686277c0c26a07668410cdfb2   usb: gadget: u_data_ipa: Fix condition check for IPA pip
1081961   I389cc9e93a26a434be752cf74444d6c0985ff36d   clk: qcom: Support CPU clock for OSM for common clock fr
1104001   Ib4cc69afb32a7654bbdd98f2efff901729c4d3da   clk: qcom: Add voltage voting for MSM8996 GCC driver
1104876   Ifeed957b99d2becd986629f60e145d6fdb717244   qseecom: support listener request for smcinvoke
1105100   Ic64d89b960c5effada93118d67a30cc051640be2   ARM: dts: msm: set rcu_expedited for msmfalcon and msmtr
1104853   If624bf14e8588e50fa6a97d29b528d7d02ef64dc   ARM: dts: msm: disable soft hot JEITA for 8998 QRD SKUK
1099484   I58c30a50c7834e7897daa2849b9885b3e797cf07   ARM: dts: msm: enable vdd and vdd-io for sdhc_2 on msm89
1099101   I41ab0baf1bbe6ccda6b8da2ecd077bea2a388e56   ASoC: msm: Check prepare state to avoid duplicate channe
1104977   I575aecb616a56974ec2680e5888190adb40c969a   ARM: dts: msm: set wled string/full scale current for QR
1092969   I6e315eec256f01c143ffc8b463279f2b30e64610   input: qpnp-power-on: Set ship mode in system_pwr_off
1104886   Ic44359e224e0f9070238748bd9b16eed35974ba6   ARM: dts: msm: add support of PM3FALCON based MSMFALCON
1097878   I3f895deaae3acf329088cf8135859cc41e781763   drivers: soc: qcom: Add error handling in function avtim
1104880   I88f2748f0c8cf96fe7f6ab9ebaa82d51ec97f4fd   defconfig: msmcortex: Enable EHSET Test Fixture device d
1104760   I456c62764c88149b785ecf1d65691ea5a775c1db   ARM: dts: msm: Add kaslr offset IMEM entry for msm8998
1104607   I780f9187256596d6f5d93b3847dc98a3c410a51e   ARM: dts: msm: Configure lmh hardware for msmtriton
1104928   I6aad9916c92d2f775632406374dbb803063148de   input: misc: fix heap overflow issue in hbtp_input.c
1101260   I6d59c7804d0dac5087e9b0e6c4a0cdacb5ddf3db   ARM: dts: msm: Add support for new flash mode on msm8998
1100528   I1fd7b7e7324b79544608a9d9ce73aa53608d1f3e   RM: dts: Update SD card Detect GPIO for msmfalcon
1104880   I638ca552f6dae735147378f3e6f6068e0003094b   usb: xhci: Add support for SINGLE_STEP_SET_FEATURE test
1103468   I547d792b38649aa1d60525b0dc335791b37989fd   msm: kgsl: Do a midframe sampling of power stats if enab
1104607   Id65a720d20fb34b9b5dccf8626af00a1d0519ce3   ARM: dts: msm: Add thermal sensor info for msmtriton
1100213   I29572841624c1cb96d85e2dcfe620b455867d41e   ARM: dts: msm: add devfreq nodes to msmfalcon target
1100018   I8e7c4be090107618cd6cbac394a57f109f8a1ced   usb: gadget: f_qc_rndis: Fix double-free in qcrndis_free
1084177   I2bbe7be3daedef45a5990c23168df5185e72e82f   msm: sensor: correcting return value for get actuator in
1102137   I2fce80cec72e3bd8b1561fd46fa1a1520cddd294   msm: mdss: dp: fix handling of link training mutex
1102584   Idd40a0b471293048833b34dda3ac5044a87fc3c9   ASoC: wcd934x: Fix headset TX mode setting
1103939   I03e4a8e10452ef53d8e35e7cee44bdf51f53483b   ARM: dts: msm: Add support for home hard key at QRD8998H
1098041   I8cc22af138a343cd387f4400cff487faa66b3da0   ASoC: wcd934x: Update class-H parameters based on headph
1095411   Ie639a26543e2f20b61d6dfc73b3bcbd6a43b24be   msm: mdss: Move PP programming after mdp wait for ping p
1093271   I406a41ac961757d31209ae0a0a4b4d9cc4d31a1e   defconfig: msm: disable CRYPTO_DEC_QCE device on msm8998
1104183   I58e19def0042022046e730dd97008a9e1c25b6d6   icnss: Add EXEC permission when assigning the MSA0 back
1104001   Ie596ddee60aac3e6fc996f9a3e8dc988b0f4aa88   clk: qcom: Add smd-rpm voter & voter branch clocks for M
1102726   I49efddea0228e3129d36eabc102d6df0fcd53d12   ARM: dts: msm: add mdss node for msmfalcon target
1099101   I1e76eb2e1c575b433e3899ae2471719bf68ab1c1   ASoC: msm: decrement slim channel ref to set the propert
1105246   I4de26881620dde4230d0a907bd0fd39bebe2bb3d   wil6210: missing reinit_completion in wmi_call

Change-Id: I0c6d90c668b09a08de714b3bcd03e1e513f1853a
CRs-Fixed: 1102584, 986540, 1104976, 1076516, 1104977, 1100018, 1102841, 1105100, 1104880, 1102900, 1081961, 1103939, 1104865, 1104679, 1105169, 1084177, 1105038, 1102641, 1099484, 1046799, 1052835, 1102137, 1098662, 1104853, 1098041, 1095411, 1083444, 1100632, 1104981, 1104858, 1100213, 1104607, 1093271, 1104928, 1102726, 1104876, 1093863, 1099101, 1103891, 1092969, 868394, 1094763, 1105246, 1103739, 1105323, 1094456, 1104760, 1101260, 1100528, 1097878, 1104886, 1104001, 1103468, 1102776, 1068294, 1101084, 1104183, 1103405

6 files changed, 261 insertions, 231 deletions

diff --git a/include/dt-bindings/clock/qcom,cpu-osm.h b/include/dt-bindings/clock/qcom,cpu-osm.h
new file mode 100644
index 000000000000..71745fab287a
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,cpu-osm.h
@@ -0,0 +1,23 @@
+/*
+ *  Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_CPU_OSM_H
+#define _DT_BINDINGS_CLK_MSM_CPU_OSM_H
+
+/* CPU clock IDs */
+#define SYS_APCSAUX_CLK_GCC	0
+#define PWRCL_CLK		1
+#define PERFCL_CLK		2
+#define OSM_CLK_SRC		3
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h
index f66264a2beb4..efed312fe914 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8996.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8996.h
@@ -14,238 +14,239 @@
 #ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H
 #define _DT_BINDINGS_CLK_MSM_GCC_8996_H
 
-#define GPLL0_EARLY						0
-#define GPLL0							1
-#define GPLL1_EARLY						2
-#define GPLL1							3
-#define GPLL2_EARLY						4
-#define GPLL2							5
-#define GPLL3_EARLY						6
-#define GPLL3							7
-#define GPLL4_EARLY						8
-#define GPLL4							9
-#define SYSTEM_NOC_CLK_SRC					10
-#define CONFIG_NOC_CLK_SRC					11
-#define PERIPH_NOC_CLK_SRC					12
-#define MMSS_BIMC_GFX_CLK_SRC					13
-#define USB30_MASTER_CLK_SRC					14
-#define USB30_MOCK_UTMI_CLK_SRC					15
-#define USB3_PHY_AUX_CLK_SRC					16
-#define USB20_MASTER_CLK_SRC					17
-#define USB20_MOCK_UTMI_CLK_SRC					18
-#define SDCC1_APPS_CLK_SRC					19
-#define SDCC1_ICE_CORE_CLK_SRC					20
-#define SDCC2_APPS_CLK_SRC					21
-#define SDCC3_APPS_CLK_SRC					22
-#define SDCC4_APPS_CLK_SRC					23
-#define BLSP1_QUP1_SPI_APPS_CLK_SRC				24
-#define BLSP1_QUP1_I2C_APPS_CLK_SRC				25
-#define BLSP1_UART1_APPS_CLK_SRC				26
-#define BLSP1_QUP2_SPI_APPS_CLK_SRC				27
-#define BLSP1_QUP2_I2C_APPS_CLK_SRC				28
-#define BLSP1_UART2_APPS_CLK_SRC				29
-#define BLSP1_QUP3_SPI_APPS_CLK_SRC				30
-#define BLSP1_QUP3_I2C_APPS_CLK_SRC				31
-#define BLSP1_UART3_APPS_CLK_SRC				32
-#define BLSP1_QUP4_SPI_APPS_CLK_SRC				33
-#define BLSP1_QUP4_I2C_APPS_CLK_SRC				34
-#define BLSP1_UART4_APPS_CLK_SRC				35
-#define BLSP1_QUP5_SPI_APPS_CLK_SRC				36
-#define BLSP1_QUP5_I2C_APPS_CLK_SRC				37
-#define BLSP1_UART5_APPS_CLK_SRC				38
-#define BLSP1_QUP6_SPI_APPS_CLK_SRC				39
-#define BLSP1_QUP6_I2C_APPS_CLK_SRC				40
-#define BLSP1_UART6_APPS_CLK_SRC				41
-#define BLSP2_QUP1_SPI_APPS_CLK_SRC				42
-#define BLSP2_QUP1_I2C_APPS_CLK_SRC				43
-#define BLSP2_UART1_APPS_CLK_SRC				44
-#define BLSP2_QUP2_SPI_APPS_CLK_SRC				45
-#define BLSP2_QUP2_I2C_APPS_CLK_SRC				46
-#define BLSP2_UART2_APPS_CLK_SRC				47
-#define BLSP2_QUP3_SPI_APPS_CLK_SRC				48
-#define BLSP2_QUP3_I2C_APPS_CLK_SRC				49
-#define BLSP2_UART3_APPS_CLK_SRC				50
-#define BLSP2_QUP4_SPI_APPS_CLK_SRC				51
-#define BLSP2_QUP4_I2C_APPS_CLK_SRC				52
-#define BLSP2_UART4_APPS_CLK_SRC				53
-#define BLSP2_QUP5_SPI_APPS_CLK_SRC				54
-#define BLSP2_QUP5_I2C_APPS_CLK_SRC				55
-#define BLSP2_UART5_APPS_CLK_SRC				56
-#define BLSP2_QUP6_SPI_APPS_CLK_SRC				57
-#define BLSP2_QUP6_I2C_APPS_CLK_SRC				58
-#define BLSP2_UART6_APPS_CLK_SRC				59
-#define PDM2_CLK_SRC						60
-#define TSIF_REF_CLK_SRC					61
-#define CE1_CLK_SRC						62
-#define GCC_SLEEP_CLK_SRC					63
-#define BIMC_CLK_SRC						64
-#define HMSS_AHB_CLK_SRC					65
-#define BIMC_HMSS_AXI_CLK_SRC					66
-#define HMSS_RBCPR_CLK_SRC					67
-#define HMSS_GPLL0_CLK_SRC					68
-#define GP1_CLK_SRC						69
-#define GP2_CLK_SRC						70
-#define GP3_CLK_SRC						71
-#define PCIE_AUX_CLK_SRC					72
-#define UFS_AXI_CLK_SRC						73
-#define UFS_ICE_CORE_CLK_SRC					74
-#define QSPI_SER_CLK_SRC					75
-#define GCC_SYS_NOC_AXI_CLK					76
-#define GCC_SYS_NOC_HMSS_AHB_CLK				77
-#define GCC_SNOC_CNOC_AHB_CLK					78
-#define GCC_SNOC_PNOC_AHB_CLK					79
-#define GCC_SYS_NOC_AT_CLK					80
-#define GCC_SYS_NOC_USB3_AXI_CLK				81
-#define GCC_SYS_NOC_UFS_AXI_CLK					82
-#define GCC_CFG_NOC_AHB_CLK					83
-#define GCC_PERIPH_NOC_AHB_CLK					84
-#define GCC_PERIPH_NOC_USB20_AHB_CLK				85
-#define GCC_TIC_CLK						86
-#define GCC_IMEM_AXI_CLK					87
-#define GCC_MMSS_SYS_NOC_AXI_CLK				88
-#define GCC_MMSS_NOC_CFG_AHB_CLK				89
-#define GCC_MMSS_BIMC_GFX_CLK					90
-#define GCC_USB30_MASTER_CLK					91
-#define GCC_USB30_SLEEP_CLK					92
-#define GCC_USB30_MOCK_UTMI_CLK					93
-#define GCC_USB3_PHY_AUX_CLK					94
-#define GCC_USB3_PHY_PIPE_CLK					95
-#define GCC_USB20_MASTER_CLK					96
-#define GCC_USB20_SLEEP_CLK					97
-#define GCC_USB20_MOCK_UTMI_CLK					98
-#define GCC_USB_PHY_CFG_AHB2PHY_CLK				99
-#define GCC_SDCC1_APPS_CLK					100
-#define GCC_SDCC1_AHB_CLK					101
-#define GCC_SDCC1_ICE_CORE_CLK					102
-#define GCC_SDCC2_APPS_CLK					103
-#define GCC_SDCC2_AHB_CLK					104
-#define GCC_SDCC3_APPS_CLK					105
-#define GCC_SDCC3_AHB_CLK					106
-#define GCC_SDCC4_APPS_CLK					107
-#define GCC_SDCC4_AHB_CLK					108
-#define GCC_BLSP1_AHB_CLK					109
-#define GCC_BLSP1_SLEEP_CLK					110
-#define GCC_BLSP1_QUP1_SPI_APPS_CLK				111
-#define GCC_BLSP1_QUP1_I2C_APPS_CLK				112
-#define GCC_BLSP1_UART1_APPS_CLK				113
-#define GCC_BLSP1_QUP2_SPI_APPS_CLK				114
-#define GCC_BLSP1_QUP2_I2C_APPS_CLK				115
-#define GCC_BLSP1_UART2_APPS_CLK				116
-#define GCC_BLSP1_QUP3_SPI_APPS_CLK				117
-#define GCC_BLSP1_QUP3_I2C_APPS_CLK				118
-#define GCC_BLSP1_UART3_APPS_CLK				119
-#define GCC_BLSP1_QUP4_SPI_APPS_CLK				120
-#define GCC_BLSP1_QUP4_I2C_APPS_CLK				121
-#define GCC_BLSP1_UART4_APPS_CLK				122
-#define GCC_BLSP1_QUP5_SPI_APPS_CLK				123
-#define GCC_BLSP1_QUP5_I2C_APPS_CLK				124
-#define GCC_BLSP1_UART5_APPS_CLK				125
-#define GCC_BLSP1_QUP6_SPI_APPS_CLK				126
-#define GCC_BLSP1_QUP6_I2C_APPS_CLK				127
-#define GCC_BLSP1_UART6_APPS_CLK				128
-#define GCC_BLSP2_AHB_CLK					129
-#define GCC_BLSP2_SLEEP_CLK					130
-#define GCC_BLSP2_QUP1_SPI_APPS_CLK				131
-#define GCC_BLSP2_QUP1_I2C_APPS_CLK				132
-#define GCC_BLSP2_UART1_APPS_CLK				133
-#define GCC_BLSP2_QUP2_SPI_APPS_CLK				134
-#define GCC_BLSP2_QUP2_I2C_APPS_CLK				135
-#define GCC_BLSP2_UART2_APPS_CLK				136
-#define GCC_BLSP2_QUP3_SPI_APPS_CLK				137
-#define GCC_BLSP2_QUP3_I2C_APPS_CLK				138
-#define GCC_BLSP2_UART3_APPS_CLK				139
-#define GCC_BLSP2_QUP4_SPI_APPS_CLK				140
-#define GCC_BLSP2_QUP4_I2C_APPS_CLK				141
-#define GCC_BLSP2_UART4_APPS_CLK				142
-#define GCC_BLSP2_QUP5_SPI_APPS_CLK				143
-#define GCC_BLSP2_QUP5_I2C_APPS_CLK				144
-#define GCC_BLSP2_UART5_APPS_CLK				145
-#define GCC_BLSP2_QUP6_SPI_APPS_CLK				146
-#define GCC_BLSP2_QUP6_I2C_APPS_CLK				147
-#define GCC_BLSP2_UART6_APPS_CLK				148
-#define GCC_PDM_AHB_CLK						149
-#define GCC_PDM_XO4_CLK						150
-#define GCC_PDM2_CLK						151
-#define GCC_PRNG_AHB_CLK					152
-#define GCC_TSIF_AHB_CLK					153
-#define GCC_TSIF_REF_CLK					154
-#define GCC_TSIF_INACTIVITY_TIMERS_CLK				155
-#define GCC_TCSR_AHB_CLK					156
-#define GCC_BOOT_ROM_AHB_CLK					157
-#define GCC_MSG_RAM_AHB_CLK					158
-#define GCC_TLMM_AHB_CLK					159
-#define GCC_TLMM_CLK						160
-#define GCC_MPM_AHB_CLK						161
-#define GCC_SPMI_SER_CLK					162
-#define GCC_SPMI_CNOC_AHB_CLK					163
-#define GCC_CE1_CLK						164
-#define GCC_CE1_AXI_CLK						165
-#define GCC_CE1_AHB_CLK						166
-#define GCC_BIMC_HMSS_AXI_CLK					167
-#define GCC_BIMC_GFX_CLK					168
-#define GCC_HMSS_AHB_CLK					169
-#define GCC_HMSS_SLV_AXI_CLK					170
-#define GCC_HMSS_MSTR_AXI_CLK					171
-#define GCC_HMSS_RBCPR_CLK					172
-#define GCC_GP1_CLK						173
-#define GCC_GP2_CLK						174
-#define GCC_GP3_CLK						175
-#define GCC_PCIE_0_SLV_AXI_CLK					176
-#define GCC_PCIE_0_MSTR_AXI_CLK					177
-#define GCC_PCIE_0_CFG_AHB_CLK					178
-#define GCC_PCIE_0_AUX_CLK					179
-#define GCC_PCIE_0_PIPE_CLK					180
-#define GCC_PCIE_1_SLV_AXI_CLK					181
-#define GCC_PCIE_1_MSTR_AXI_CLK					182
-#define GCC_PCIE_1_CFG_AHB_CLK					183
-#define GCC_PCIE_1_AUX_CLK					184
-#define GCC_PCIE_1_PIPE_CLK					185
-#define GCC_PCIE_2_SLV_AXI_CLK					186
-#define GCC_PCIE_2_MSTR_AXI_CLK					187
-#define GCC_PCIE_2_CFG_AHB_CLK					188
-#define GCC_PCIE_2_AUX_CLK					189
-#define GCC_PCIE_2_PIPE_CLK					190
-#define GCC_PCIE_PHY_CFG_AHB_CLK				191
-#define GCC_PCIE_PHY_AUX_CLK					192
-#define GCC_UFS_AXI_CLK						193
-#define GCC_UFS_AHB_CLK						194
-#define GCC_UFS_TX_CFG_CLK					195
-#define GCC_UFS_RX_CFG_CLK					196
-#define GCC_UFS_TX_SYMBOL_0_CLK					197
-#define GCC_UFS_RX_SYMBOL_0_CLK					198
-#define GCC_UFS_RX_SYMBOL_1_CLK					199
-#define GCC_UFS_UNIPRO_CORE_CLK					200
-#define GCC_UFS_ICE_CORE_CLK					201
-#define GCC_UFS_SYS_CLK_CORE_CLK				202
-#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK				203
-#define GCC_AGGRE0_SNOC_AXI_CLK					204
-#define GCC_AGGRE0_CNOC_AHB_CLK					205
-#define GCC_SMMU_AGGRE0_AXI_CLK					206
-#define GCC_SMMU_AGGRE0_AHB_CLK					207
-#define GCC_AGGRE1_PNOC_AHB_CLK					208
-#define GCC_AGGRE2_UFS_AXI_CLK					209
-#define GCC_AGGRE2_USB3_AXI_CLK					210
-#define GCC_QSPI_AHB_CLK					211
-#define GCC_QSPI_SER_CLK					212
-#define GCC_USB3_CLKREF_CLK					213
-#define GCC_HDMI_CLKREF_CLK					214
-#define GCC_UFS_CLKREF_CLK					215
-#define GCC_PCIE_CLKREF_CLK					216
-#define GCC_RX2_USB2_CLKREF_CLK					217
-#define GCC_RX1_USB2_CLKREF_CLK					218
-#define GCC_AGGRE0_NOC_QOSGEN_EXTREF_CLK			219
-#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK			220
-#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK			221
-#define GCC_EDP_CLKREF_CLK					222
-#define GCC_MSS_CFG_AHB_CLK					223
-#define GCC_MSS_Q6_BIMC_AXI_CLK					224
-#define GCC_MSS_SNOC_AXI_CLK					225
-#define GCC_MSS_MNOC_BIMC_AXI_CLK				226
-#define GCC_DCC_AHB_ALK						227
-#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK				228
-#define GCC_MMSS_GPLL0_DIV_CLK					229
-#define GPLL0_OUT_MSSCC						230
+/* Hardware/Dummy/Voter clocks */
+#define GCC_XO							0
+#define GCC_CE1_AHB_M_CLK					1
+#define GCC_CE1_AXI_M_CLK					2
+#define GCC_GPLL0_EARLY_DIV					3
+#define GCC_UFS_TX_CFG_CLK_SRC					4
+#define GCC_UFS_RX_CFG_CLK_SRC					5
+#define GCC_UFS_ICE_CORE_PDIV_CLK_SRC				6
 
+/* RCGs and Branches */
+#define GPLL0_EARLY						7
+#define GPLL0							8
+#define GPLL4_EARLY						9
+#define GPLL4							10
+#define SYSTEM_NOC_CLK_SRC					11
+#define CONFIG_NOC_CLK_SRC					12
+#define PERIPH_NOC_CLK_SRC					13
+#define MMSS_BIMC_GFX_CLK_SRC					14
+#define USB30_MASTER_CLK_SRC					15
+#define USB30_MOCK_UTMI_CLK_SRC					16
+#define USB3_PHY_AUX_CLK_SRC					17
+#define USB20_MASTER_CLK_SRC					18
+#define USB20_MOCK_UTMI_CLK_SRC					19
+#define SDCC1_APPS_CLK_SRC					20
+#define SDCC1_ICE_CORE_CLK_SRC					21
+#define SDCC2_APPS_CLK_SRC					22
+#define SDCC3_APPS_CLK_SRC					23
+#define SDCC4_APPS_CLK_SRC					24
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC				25
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC				26
+#define BLSP1_UART1_APPS_CLK_SRC				27
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC				28
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC				29
+#define BLSP1_UART2_APPS_CLK_SRC				30
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC				31
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC				32
+#define BLSP1_UART3_APPS_CLK_SRC				33
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC				34
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC				35
+#define BLSP1_UART4_APPS_CLK_SRC				36
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC				37
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC				38
+#define BLSP1_UART5_APPS_CLK_SRC				39
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC				40
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC				41
+#define BLSP1_UART6_APPS_CLK_SRC				42
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC				43
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC				44
+#define BLSP2_UART1_APPS_CLK_SRC				45
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC				46
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC				47
+#define BLSP2_UART2_APPS_CLK_SRC				48
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC				49
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC				50
+#define BLSP2_UART3_APPS_CLK_SRC				51
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC				52
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC				53
+#define BLSP2_UART4_APPS_CLK_SRC				54
+#define BLSP2_QUP5_SPI_APPS_CLK_SRC				55
+#define BLSP2_QUP5_I2C_APPS_CLK_SRC				56
+#define BLSP2_UART5_APPS_CLK_SRC				57
+#define BLSP2_QUP6_SPI_APPS_CLK_SRC				58
+#define BLSP2_QUP6_I2C_APPS_CLK_SRC				59
+#define BLSP2_UART6_APPS_CLK_SRC				60
+#define PDM2_CLK_SRC						61
+#define TSIF_REF_CLK_SRC					62
+#define CE1_CLK_SRC						63
+#define GCC_SLEEP_CLK_SRC					64
+#define BIMC_CLK_SRC						65
+#define HMSS_AHB_CLK_SRC					66
+#define BIMC_HMSS_AXI_CLK_SRC					67
+#define HMSS_RBCPR_CLK_SRC					68
+#define HMSS_GPLL0_CLK_SRC					69
+#define GP1_CLK_SRC						70
+#define GP2_CLK_SRC						71
+#define GP3_CLK_SRC						72
+#define PCIE_AUX_CLK_SRC					73
+#define UFS_AXI_CLK_SRC						74
+#define UFS_ICE_CORE_CLK_SRC					75
+#define QSPI_SER_CLK_SRC					76
+#define GCC_SYS_NOC_AXI_CLK					77
+#define GCC_SYS_NOC_HMSS_AHB_CLK				78
+#define GCC_SNOC_CNOC_AHB_CLK					79
+#define GCC_SNOC_PNOC_AHB_CLK					80
+#define GCC_SYS_NOC_AT_CLK					81
+#define GCC_SYS_NOC_USB3_AXI_CLK				82
+#define GCC_SYS_NOC_UFS_AXI_CLK					83
+#define GCC_CFG_NOC_AHB_CLK					84
+#define GCC_PERIPH_NOC_AHB_CLK					85
+#define GCC_PERIPH_NOC_USB20_AHB_CLK				86
+#define GCC_TIC_CLK						87
+#define GCC_IMEM_AXI_CLK					88
+#define GCC_MMSS_SYS_NOC_AXI_CLK				89
+#define GCC_MMSS_NOC_CFG_AHB_CLK				90
+#define GCC_MMSS_BIMC_GFX_CLK					91
+#define GCC_USB30_MASTER_CLK					92
+#define GCC_USB30_SLEEP_CLK					93
+#define GCC_USB30_MOCK_UTMI_CLK					94
+#define GCC_USB3_PHY_AUX_CLK					95
+#define GCC_USB3_PHY_PIPE_CLK					96
+#define GCC_USB20_MASTER_CLK					97
+#define GCC_USB20_SLEEP_CLK					98
+#define GCC_USB20_MOCK_UTMI_CLK					99
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK				100
+#define GCC_SDCC1_APPS_CLK					101
+#define GCC_SDCC1_AHB_CLK					102
+#define GCC_SDCC1_ICE_CORE_CLK					103
+#define GCC_SDCC2_APPS_CLK					104
+#define GCC_SDCC2_AHB_CLK					105
+#define GCC_SDCC3_APPS_CLK					106
+#define GCC_SDCC3_AHB_CLK					107
+#define GCC_SDCC4_APPS_CLK					108
+#define GCC_SDCC4_AHB_CLK					109
+#define GCC_BLSP1_AHB_CLK					110
+#define GCC_BLSP1_SLEEP_CLK					111
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK				112
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK				113
+#define GCC_BLSP1_UART1_APPS_CLK				114
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK				115
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK				116
+#define GCC_BLSP1_UART2_APPS_CLK				117
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK				118
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK				119
+#define GCC_BLSP1_UART3_APPS_CLK				120
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK				121
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK				122
+#define GCC_BLSP1_UART4_APPS_CLK				123
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK				124
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK				125
+#define GCC_BLSP1_UART5_APPS_CLK				126
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK				127
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK				128
+#define GCC_BLSP1_UART6_APPS_CLK				129
+#define GCC_BLSP2_AHB_CLK					130
+#define GCC_BLSP2_SLEEP_CLK					131
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK				132
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK				133
+#define GCC_BLSP2_UART1_APPS_CLK				134
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK				135
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK				136
+#define GCC_BLSP2_UART2_APPS_CLK				137
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK				138
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK				139
+#define GCC_BLSP2_UART3_APPS_CLK				140
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK				141
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK				142
+#define GCC_BLSP2_UART4_APPS_CLK				143
+#define GCC_BLSP2_QUP5_SPI_APPS_CLK				144
+#define GCC_BLSP2_QUP5_I2C_APPS_CLK				145
+#define GCC_BLSP2_UART5_APPS_CLK				146
+#define GCC_BLSP2_QUP6_SPI_APPS_CLK				147
+#define GCC_BLSP2_QUP6_I2C_APPS_CLK				148
+#define GCC_BLSP2_UART6_APPS_CLK				149
+#define GCC_PDM_AHB_CLK						150
+#define GCC_PDM_XO4_CLK						151
+#define GCC_PDM2_CLK						152
+#define GCC_PRNG_AHB_CLK					153
+#define GCC_TSIF_AHB_CLK					154
+#define GCC_TSIF_REF_CLK					155
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK				156
+#define GCC_TCSR_AHB_CLK					157
+#define GCC_BOOT_ROM_AHB_CLK					158
+#define GCC_MSG_RAM_AHB_CLK					159
+#define GCC_TLMM_AHB_CLK					160
+#define GCC_TLMM_CLK						161
+#define GCC_MPM_AHB_CLK						162
+#define GCC_SPMI_SER_CLK					163
+#define GCC_SPMI_CNOC_AHB_CLK					164
+#define GCC_BIMC_HMSS_AXI_CLK					165
+#define GCC_BIMC_GFX_CLK					166
+#define GCC_HMSS_AHB_CLK					167
+#define GCC_HMSS_SLV_AXI_CLK					168
+#define GCC_HMSS_MSTR_AXI_CLK					169
+#define GCC_HMSS_RBCPR_CLK					170
+#define GCC_GP1_CLK						171
+#define GCC_GP2_CLK						172
+#define GCC_GP3_CLK						173
+#define GCC_PCIE_0_SLV_AXI_CLK					174
+#define GCC_PCIE_0_MSTR_AXI_CLK					175
+#define GCC_PCIE_0_CFG_AHB_CLK					176
+#define GCC_PCIE_0_AUX_CLK					177
+#define GCC_PCIE_0_PIPE_CLK					178
+#define GCC_PCIE_1_SLV_AXI_CLK					179
+#define GCC_PCIE_1_MSTR_AXI_CLK					180
+#define GCC_PCIE_1_CFG_AHB_CLK					181
+#define GCC_PCIE_1_AUX_CLK					182
+#define GCC_PCIE_1_PIPE_CLK					183
+#define GCC_PCIE_2_SLV_AXI_CLK					184
+#define GCC_PCIE_2_MSTR_AXI_CLK					185
+#define GCC_PCIE_2_CFG_AHB_CLK					186
+#define GCC_PCIE_2_AUX_CLK					187
+#define GCC_PCIE_2_PIPE_CLK					188
+#define GCC_PCIE_PHY_CFG_AHB_CLK				189
+#define GCC_PCIE_PHY_AUX_CLK					190
+#define GCC_UFS_AXI_CLK						191
+#define GCC_UFS_AHB_CLK						192
+#define GCC_UFS_TX_CFG_CLK					193
+#define GCC_UFS_RX_CFG_CLK					194
+#define GCC_UFS_TX_SYMBOL_0_CLK					195
+#define GCC_UFS_RX_SYMBOL_0_CLK					196
+#define GCC_UFS_RX_SYMBOL_1_CLK					197
+#define GCC_UFS_UNIPRO_CORE_CLK					198
+#define GCC_UFS_ICE_CORE_CLK					199
+#define GCC_UFS_SYS_CLK_CORE_CLK				200
+#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK				201
+#define GCC_AGGRE0_SNOC_AXI_CLK					202
+#define GCC_AGGRE0_CNOC_AHB_CLK					203
+#define GCC_SMMU_AGGRE0_AXI_CLK					204
+#define GCC_SMMU_AGGRE0_AHB_CLK					205
+#define GCC_AGGRE2_UFS_AXI_CLK					206
+#define GCC_AGGRE2_USB3_AXI_CLK					207
+#define GCC_QSPI_AHB_CLK					208
+#define GCC_QSPI_SER_CLK					209
+#define GCC_USB3_CLKREF_CLK					210
+#define GCC_HDMI_CLKREF_CLK					211
+#define GCC_UFS_CLKREF_CLK					212
+#define GCC_PCIE_CLKREF_CLK					213
+#define GCC_RX2_USB2_CLKREF_CLK					214
+#define GCC_RX1_USB2_CLKREF_CLK					215
+#define GCC_AGGRE0_NOC_QOSGEN_EXTREF_CLK			216
+#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK			217
+#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK			218
+#define GCC_EDP_CLKREF_CLK					219
+#define GCC_MSS_CFG_AHB_CLK					220
+#define GCC_MSS_Q6_BIMC_AXI_CLK					221
+#define GCC_MSS_SNOC_AXI_CLK					222
+#define GCC_MSS_MNOC_BIMC_AXI_CLK				223
+#define GCC_DCC_AHB_CLK						224
+#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK				225
+#define GCC_MMSS_GPLL0_DIV_CLK					226
+#define GPLL0_OUT_MSSCC_CLK					227
+
+/* Block resets */
 #define GCC_SYSTEM_NOC_BCR					0
 #define GCC_CONFIG_NOC_BCR					1
 #define GCC_PERIPH_NOC_BCR					2
diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h
index bcaa1a552e8e..0f0c6300642c 100644
--- a/include/dt-bindings/clock/qcom,rpmcc.h
+++ b/include/dt-bindings/clock/qcom,rpmcc.h
@@ -128,5 +128,6 @@
 #define  CXO_PIL_SSC_CLK			83
 #define  CXO_PIL_CDSP_CLK			84
 #define  CNOC_PERIPH_KEEPALIVE_A_CLK		85
+#define  MMSSNOC_A_CLK_CPU_VOTE			86
 
 #endif
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 744167a9ca8b..f91991b97888 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -33,6 +33,9 @@
 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
 #define CLK_RECALC_NEW_RATES	BIT(9) /* recalc rates after notifications */
 #define CLK_IS_CRITICAL		BIT(11) /* do not gate, ever */
+#define CLK_ENABLE_HAND_OFF	BIT(12) /* enable clock when registered.
+					   hand-off enable_count & prepare_count
+					   to first consumer that enables clk */
 #define CLK_IS_MEASURE          BIT(14) /* measure clock */
 
 struct clk;
diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h
index 9b6359241018..20280ff20e52 100644
--- a/include/linux/power_supply.h
+++ b/include/linux/power_supply.h
@@ -227,6 +227,7 @@ enum power_supply_property {
 	POWER_SUPPLY_PROP_PARALLEL_PERCENT,
 	POWER_SUPPLY_PROP_PE_START,
 	POWER_SUPPLY_PROP_SET_SHIP_MODE,
+	POWER_SUPPLY_PROP_SOC_REPORTING_READY,
 	/* Local extensions of type int64_t */
 	POWER_SUPPLY_PROP_CHARGE_COUNTER_EXT,
 	/* Properties of type `const char *' */
diff --git a/include/uapi/linux/msm_mdp.h b/include/uapi/linux/msm_mdp.h
index 20b879c2e5fc..4df3845c159c 100644
--- a/include/uapi/linux/msm_mdp.h
+++ b/include/uapi/linux/msm_mdp.h
@@ -118,6 +118,7 @@
 #define MDSS_MDP_HW_REV_116	MDSS_MDP_REV(1, 16, 0) /* msmtitanium */
 #define MDSS_MDP_HW_REV_300	MDSS_MDP_REV(3, 0, 0)  /* msm8998 */
 #define MDSS_MDP_HW_REV_301	MDSS_MDP_REV(3, 0, 1)  /* msm8998 v1.0 */
+#define MDSS_MDP_HW_REV_320	MDSS_MDP_REV(3, 2, 0)  /* msmfalcon */
 
 enum {
 	NOTIFY_UPDATE_INIT,