From da5c2e07e74d4e4d1f9548a22461b7eb1c46fae8 Mon Sep 17 00:00:00 2001 From: "Sravan Kumar D.V.N" Date: Tue, 6 Dec 2016 20:41:38 +0530 Subject: msm: mdss: Initialize mdss v3 pp driver ops for msmfalcon Define MDSS hw version and initialize mdss v3 pp driver ops for msmfalcon CRs-Fixed: 1102841 Change-Id: I2661a639c19dd451f22c9a29d7d75d9b3fb98114 Signed-off-by: Sravan Kumar D.V.N --- include/uapi/linux/msm_mdp.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/uapi/linux/msm_mdp.h b/include/uapi/linux/msm_mdp.h index 20b879c2e5fc..4df3845c159c 100644 --- a/include/uapi/linux/msm_mdp.h +++ b/include/uapi/linux/msm_mdp.h @@ -118,6 +118,7 @@ #define MDSS_MDP_HW_REV_116 MDSS_MDP_REV(1, 16, 0) /* msmtitanium */ #define MDSS_MDP_HW_REV_300 MDSS_MDP_REV(3, 0, 0) /* msm8998 */ #define MDSS_MDP_HW_REV_301 MDSS_MDP_REV(3, 0, 1) /* msm8998 v1.0 */ +#define MDSS_MDP_HW_REV_320 MDSS_MDP_REV(3, 2, 0) /* msmfalcon */ enum { NOTIFY_UPDATE_INIT, -- cgit v1.2.3 From 79871232a8109132dfadf64bb7e13890fa342340 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Thu, 17 Nov 2016 11:20:23 +0530 Subject: clk: qcom: Support CPU clock for OSM for common clock framework Following list of changes have been made - Update the clock osm to register to common clock framework - Update clock ops as per common clock framework - cleanup unused function (clk_osm_setup_osm_was) - Fix tabs for macro definitions - Add clocks ids for power and perf clock for clients Change-Id: I389cc9e93a26a434be752cf74444d6c0985ff36d Signed-off-by: Taniya Das --- include/dt-bindings/clock/qcom,cpu-osm.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,cpu-osm.h (limited to 'include') diff --git a/include/dt-bindings/clock/qcom,cpu-osm.h b/include/dt-bindings/clock/qcom,cpu-osm.h new file mode 100644 index 000000000000..71745fab287a --- /dev/null +++ b/include/dt-bindings/clock/qcom,cpu-osm.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_CPU_OSM_H +#define _DT_BINDINGS_CLK_MSM_CPU_OSM_H + +/* CPU clock IDs */ +#define SYS_APCSAUX_CLK_GCC 0 +#define PWRCL_CLK 1 +#define PERFCL_CLK 2 +#define OSM_CLK_SRC 3 + +#endif -- cgit v1.2.3 From d8d0e55ed104252f0295767d5e2e026c93404870 Mon Sep 17 00:00:00 2001 From: Michael Turquette Date: Thu, 17 Nov 2016 18:47:30 +0530 Subject: clk: introduce CLK_ENABLE_HAND_OFF flag Some clocks are critical to system operation (e.g. cpu, memory, etc) and should not be gated until a driver that knows best claims such a clock and expressly gates that clock through the normal clk.h api. The typical way to handle this is for the clk driver or some other early code to call clk_prepare_enable on this important clock as soon as it is registered and before the clk_disable_unused garbage collector kicks in. This patch introduces a formal way to handle this scenario that is provided by the clk framework. Clk driver authors can set the CLK_ENABLE_HAND_OFF flag in their clk data, which will cause the clk to be enabled in clk_register(). Then when the first clk consumer driver comes along and calls clk_get() & clk_prepare_enable(), the reference counts taken during clk registration are transfered (or handed off) to the clk consumer. At this point handling the clk is the same as any other clock which as not set the new CLK_ENABLE_HAND_OFF flag. In fact no changes to any clock consumer driver are needed for this to work. Change-Id: Ib5247f6bceb1f555c03103f061af089755b2de62 Signed-off-by: Michael Turquette Patch-mainline: patchwork.kernel.org @ 02/11/16, 9:19 Signed-off-by: Taniya Das --- include/linux/clk-provider.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 744167a9ca8b..f91991b97888 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -33,6 +33,9 @@ #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ +#define CLK_ENABLE_HAND_OFF BIT(12) /* enable clock when registered. + hand-off enable_count & prepare_count + to first consumer that enables clk */ #define CLK_IS_MEASURE BIT(14) /* measure clock */ struct clk; -- cgit v1.2.3 From 5207bf3492f9e48c9e45fbe9cac65ae292bfe2ca Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Wed, 14 Dec 2016 15:05:22 -0800 Subject: power_supply: Add SOC_REPORTING_READY property Add SOC_REORTING_READY property to indicate if the SOC is ready to be reported. Change-Id: I53ac153ba9f7ae81bb0657b17e0e798fd3fe4f48 Signed-off-by: Subbaraman Narayanamurthy --- include/linux/power_supply.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h index 9b6359241018..20280ff20e52 100644 --- a/include/linux/power_supply.h +++ b/include/linux/power_supply.h @@ -227,6 +227,7 @@ enum power_supply_property { POWER_SUPPLY_PROP_PARALLEL_PERCENT, POWER_SUPPLY_PROP_PE_START, POWER_SUPPLY_PROP_SET_SHIP_MODE, + POWER_SUPPLY_PROP_SOC_REPORTING_READY, /* Local extensions of type int64_t */ POWER_SUPPLY_PROP_CHARGE_COUNTER_EXT, /* Properties of type `const char *' */ -- cgit v1.2.3 From 83f20c061222d2b59f940ad83660484877d2cfec Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Wed, 21 Dec 2016 13:25:52 +0530 Subject: clk: qcom: Add voltage voting for MSM8996 GCC driver Global Clock Controller(GCC) needs to vote for volatge level on rail for the clock frequencies, so add voltage voting in GCC. Also clean up clock flags and parent info for few clocks. Change-Id: Ib4cc69afb32a7654bbdd98f2efff901729c4d3da Signed-off-by: Odelu Kukatla --- include/dt-bindings/clock/qcom,gcc-msm8996.h | 463 ++++++++++++++------------- 1 file changed, 232 insertions(+), 231 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h index f66264a2beb4..efed312fe914 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8996.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8996.h @@ -14,238 +14,239 @@ #ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H #define _DT_BINDINGS_CLK_MSM_GCC_8996_H -#define GPLL0_EARLY 0 -#define GPLL0 1 -#define GPLL1_EARLY 2 -#define GPLL1 3 -#define GPLL2_EARLY 4 -#define GPLL2 5 -#define GPLL3_EARLY 6 -#define GPLL3 7 -#define GPLL4_EARLY 8 -#define GPLL4 9 -#define SYSTEM_NOC_CLK_SRC 10 -#define CONFIG_NOC_CLK_SRC 11 -#define PERIPH_NOC_CLK_SRC 12 -#define MMSS_BIMC_GFX_CLK_SRC 13 -#define USB30_MASTER_CLK_SRC 14 -#define USB30_MOCK_UTMI_CLK_SRC 15 -#define USB3_PHY_AUX_CLK_SRC 16 -#define USB20_MASTER_CLK_SRC 17 -#define USB20_MOCK_UTMI_CLK_SRC 18 -#define SDCC1_APPS_CLK_SRC 19 -#define SDCC1_ICE_CORE_CLK_SRC 20 -#define SDCC2_APPS_CLK_SRC 21 -#define SDCC3_APPS_CLK_SRC 22 -#define SDCC4_APPS_CLK_SRC 23 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 24 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 25 -#define BLSP1_UART1_APPS_CLK_SRC 26 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 27 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 28 -#define BLSP1_UART2_APPS_CLK_SRC 29 -#define BLSP1_QUP3_SPI_APPS_CLK_SRC 30 -#define BLSP1_QUP3_I2C_APPS_CLK_SRC 31 -#define BLSP1_UART3_APPS_CLK_SRC 32 -#define BLSP1_QUP4_SPI_APPS_CLK_SRC 33 -#define BLSP1_QUP4_I2C_APPS_CLK_SRC 34 -#define BLSP1_UART4_APPS_CLK_SRC 35 -#define BLSP1_QUP5_SPI_APPS_CLK_SRC 36 -#define BLSP1_QUP5_I2C_APPS_CLK_SRC 37 -#define BLSP1_UART5_APPS_CLK_SRC 38 -#define BLSP1_QUP6_SPI_APPS_CLK_SRC 39 -#define BLSP1_QUP6_I2C_APPS_CLK_SRC 40 -#define BLSP1_UART6_APPS_CLK_SRC 41 -#define BLSP2_QUP1_SPI_APPS_CLK_SRC 42 -#define BLSP2_QUP1_I2C_APPS_CLK_SRC 43 -#define BLSP2_UART1_APPS_CLK_SRC 44 -#define BLSP2_QUP2_SPI_APPS_CLK_SRC 45 -#define BLSP2_QUP2_I2C_APPS_CLK_SRC 46 -#define BLSP2_UART2_APPS_CLK_SRC 47 -#define BLSP2_QUP3_SPI_APPS_CLK_SRC 48 -#define BLSP2_QUP3_I2C_APPS_CLK_SRC 49 -#define BLSP2_UART3_APPS_CLK_SRC 50 -#define BLSP2_QUP4_SPI_APPS_CLK_SRC 51 -#define BLSP2_QUP4_I2C_APPS_CLK_SRC 52 -#define BLSP2_UART4_APPS_CLK_SRC 53 -#define BLSP2_QUP5_SPI_APPS_CLK_SRC 54 -#define BLSP2_QUP5_I2C_APPS_CLK_SRC 55 -#define BLSP2_UART5_APPS_CLK_SRC 56 -#define BLSP2_QUP6_SPI_APPS_CLK_SRC 57 -#define BLSP2_QUP6_I2C_APPS_CLK_SRC 58 -#define BLSP2_UART6_APPS_CLK_SRC 59 -#define PDM2_CLK_SRC 60 -#define TSIF_REF_CLK_SRC 61 -#define CE1_CLK_SRC 62 -#define GCC_SLEEP_CLK_SRC 63 -#define BIMC_CLK_SRC 64 -#define HMSS_AHB_CLK_SRC 65 -#define BIMC_HMSS_AXI_CLK_SRC 66 -#define HMSS_RBCPR_CLK_SRC 67 -#define HMSS_GPLL0_CLK_SRC 68 -#define GP1_CLK_SRC 69 -#define GP2_CLK_SRC 70 -#define GP3_CLK_SRC 71 -#define PCIE_AUX_CLK_SRC 72 -#define UFS_AXI_CLK_SRC 73 -#define UFS_ICE_CORE_CLK_SRC 74 -#define QSPI_SER_CLK_SRC 75 -#define GCC_SYS_NOC_AXI_CLK 76 -#define GCC_SYS_NOC_HMSS_AHB_CLK 77 -#define GCC_SNOC_CNOC_AHB_CLK 78 -#define GCC_SNOC_PNOC_AHB_CLK 79 -#define GCC_SYS_NOC_AT_CLK 80 -#define GCC_SYS_NOC_USB3_AXI_CLK 81 -#define GCC_SYS_NOC_UFS_AXI_CLK 82 -#define GCC_CFG_NOC_AHB_CLK 83 -#define GCC_PERIPH_NOC_AHB_CLK 84 -#define GCC_PERIPH_NOC_USB20_AHB_CLK 85 -#define GCC_TIC_CLK 86 -#define GCC_IMEM_AXI_CLK 87 -#define GCC_MMSS_SYS_NOC_AXI_CLK 88 -#define GCC_MMSS_NOC_CFG_AHB_CLK 89 -#define GCC_MMSS_BIMC_GFX_CLK 90 -#define GCC_USB30_MASTER_CLK 91 -#define GCC_USB30_SLEEP_CLK 92 -#define GCC_USB30_MOCK_UTMI_CLK 93 -#define GCC_USB3_PHY_AUX_CLK 94 -#define GCC_USB3_PHY_PIPE_CLK 95 -#define GCC_USB20_MASTER_CLK 96 -#define GCC_USB20_SLEEP_CLK 97 -#define GCC_USB20_MOCK_UTMI_CLK 98 -#define GCC_USB_PHY_CFG_AHB2PHY_CLK 99 -#define GCC_SDCC1_APPS_CLK 100 -#define GCC_SDCC1_AHB_CLK 101 -#define GCC_SDCC1_ICE_CORE_CLK 102 -#define GCC_SDCC2_APPS_CLK 103 -#define GCC_SDCC2_AHB_CLK 104 -#define GCC_SDCC3_APPS_CLK 105 -#define GCC_SDCC3_AHB_CLK 106 -#define GCC_SDCC4_APPS_CLK 107 -#define GCC_SDCC4_AHB_CLK 108 -#define GCC_BLSP1_AHB_CLK 109 -#define GCC_BLSP1_SLEEP_CLK 110 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 111 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 112 -#define GCC_BLSP1_UART1_APPS_CLK 113 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 114 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 115 -#define GCC_BLSP1_UART2_APPS_CLK 116 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 117 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 118 -#define GCC_BLSP1_UART3_APPS_CLK 119 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 120 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 121 -#define GCC_BLSP1_UART4_APPS_CLK 122 -#define GCC_BLSP1_QUP5_SPI_APPS_CLK 123 -#define GCC_BLSP1_QUP5_I2C_APPS_CLK 124 -#define GCC_BLSP1_UART5_APPS_CLK 125 -#define GCC_BLSP1_QUP6_SPI_APPS_CLK 126 -#define GCC_BLSP1_QUP6_I2C_APPS_CLK 127 -#define GCC_BLSP1_UART6_APPS_CLK 128 -#define GCC_BLSP2_AHB_CLK 129 -#define GCC_BLSP2_SLEEP_CLK 130 -#define GCC_BLSP2_QUP1_SPI_APPS_CLK 131 -#define GCC_BLSP2_QUP1_I2C_APPS_CLK 132 -#define GCC_BLSP2_UART1_APPS_CLK 133 -#define GCC_BLSP2_QUP2_SPI_APPS_CLK 134 -#define GCC_BLSP2_QUP2_I2C_APPS_CLK 135 -#define GCC_BLSP2_UART2_APPS_CLK 136 -#define GCC_BLSP2_QUP3_SPI_APPS_CLK 137 -#define GCC_BLSP2_QUP3_I2C_APPS_CLK 138 -#define GCC_BLSP2_UART3_APPS_CLK 139 -#define GCC_BLSP2_QUP4_SPI_APPS_CLK 140 -#define GCC_BLSP2_QUP4_I2C_APPS_CLK 141 -#define GCC_BLSP2_UART4_APPS_CLK 142 -#define GCC_BLSP2_QUP5_SPI_APPS_CLK 143 -#define GCC_BLSP2_QUP5_I2C_APPS_CLK 144 -#define GCC_BLSP2_UART5_APPS_CLK 145 -#define GCC_BLSP2_QUP6_SPI_APPS_CLK 146 -#define GCC_BLSP2_QUP6_I2C_APPS_CLK 147 -#define GCC_BLSP2_UART6_APPS_CLK 148 -#define GCC_PDM_AHB_CLK 149 -#define GCC_PDM_XO4_CLK 150 -#define GCC_PDM2_CLK 151 -#define GCC_PRNG_AHB_CLK 152 -#define GCC_TSIF_AHB_CLK 153 -#define GCC_TSIF_REF_CLK 154 -#define GCC_TSIF_INACTIVITY_TIMERS_CLK 155 -#define GCC_TCSR_AHB_CLK 156 -#define GCC_BOOT_ROM_AHB_CLK 157 -#define GCC_MSG_RAM_AHB_CLK 158 -#define GCC_TLMM_AHB_CLK 159 -#define GCC_TLMM_CLK 160 -#define GCC_MPM_AHB_CLK 161 -#define GCC_SPMI_SER_CLK 162 -#define GCC_SPMI_CNOC_AHB_CLK 163 -#define GCC_CE1_CLK 164 -#define GCC_CE1_AXI_CLK 165 -#define GCC_CE1_AHB_CLK 166 -#define GCC_BIMC_HMSS_AXI_CLK 167 -#define GCC_BIMC_GFX_CLK 168 -#define GCC_HMSS_AHB_CLK 169 -#define GCC_HMSS_SLV_AXI_CLK 170 -#define GCC_HMSS_MSTR_AXI_CLK 171 -#define GCC_HMSS_RBCPR_CLK 172 -#define GCC_GP1_CLK 173 -#define GCC_GP2_CLK 174 -#define GCC_GP3_CLK 175 -#define GCC_PCIE_0_SLV_AXI_CLK 176 -#define GCC_PCIE_0_MSTR_AXI_CLK 177 -#define GCC_PCIE_0_CFG_AHB_CLK 178 -#define GCC_PCIE_0_AUX_CLK 179 -#define GCC_PCIE_0_PIPE_CLK 180 -#define GCC_PCIE_1_SLV_AXI_CLK 181 -#define GCC_PCIE_1_MSTR_AXI_CLK 182 -#define GCC_PCIE_1_CFG_AHB_CLK 183 -#define GCC_PCIE_1_AUX_CLK 184 -#define GCC_PCIE_1_PIPE_CLK 185 -#define GCC_PCIE_2_SLV_AXI_CLK 186 -#define GCC_PCIE_2_MSTR_AXI_CLK 187 -#define GCC_PCIE_2_CFG_AHB_CLK 188 -#define GCC_PCIE_2_AUX_CLK 189 -#define GCC_PCIE_2_PIPE_CLK 190 -#define GCC_PCIE_PHY_CFG_AHB_CLK 191 -#define GCC_PCIE_PHY_AUX_CLK 192 -#define GCC_UFS_AXI_CLK 193 -#define GCC_UFS_AHB_CLK 194 -#define GCC_UFS_TX_CFG_CLK 195 -#define GCC_UFS_RX_CFG_CLK 196 -#define GCC_UFS_TX_SYMBOL_0_CLK 197 -#define GCC_UFS_RX_SYMBOL_0_CLK 198 -#define GCC_UFS_RX_SYMBOL_1_CLK 199 -#define GCC_UFS_UNIPRO_CORE_CLK 200 -#define GCC_UFS_ICE_CORE_CLK 201 -#define GCC_UFS_SYS_CLK_CORE_CLK 202 -#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK 203 -#define GCC_AGGRE0_SNOC_AXI_CLK 204 -#define GCC_AGGRE0_CNOC_AHB_CLK 205 -#define GCC_SMMU_AGGRE0_AXI_CLK 206 -#define GCC_SMMU_AGGRE0_AHB_CLK 207 -#define GCC_AGGRE1_PNOC_AHB_CLK 208 -#define GCC_AGGRE2_UFS_AXI_CLK 209 -#define GCC_AGGRE2_USB3_AXI_CLK 210 -#define GCC_QSPI_AHB_CLK 211 -#define GCC_QSPI_SER_CLK 212 -#define GCC_USB3_CLKREF_CLK 213 -#define GCC_HDMI_CLKREF_CLK 214 -#define GCC_UFS_CLKREF_CLK 215 -#define GCC_PCIE_CLKREF_CLK 216 -#define GCC_RX2_USB2_CLKREF_CLK 217 -#define GCC_RX1_USB2_CLKREF_CLK 218 -#define GCC_AGGRE0_NOC_QOSGEN_EXTREF_CLK 219 -#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 220 -#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 221 -#define GCC_EDP_CLKREF_CLK 222 -#define GCC_MSS_CFG_AHB_CLK 223 -#define GCC_MSS_Q6_BIMC_AXI_CLK 224 -#define GCC_MSS_SNOC_AXI_CLK 225 -#define GCC_MSS_MNOC_BIMC_AXI_CLK 226 -#define GCC_DCC_AHB_ALK 227 -#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK 228 -#define GCC_MMSS_GPLL0_DIV_CLK 229 -#define GPLL0_OUT_MSSCC 230 +/* Hardware/Dummy/Voter clocks */ +#define GCC_XO 0 +#define GCC_CE1_AHB_M_CLK 1 +#define GCC_CE1_AXI_M_CLK 2 +#define GCC_GPLL0_EARLY_DIV 3 +#define GCC_UFS_TX_CFG_CLK_SRC 4 +#define GCC_UFS_RX_CFG_CLK_SRC 5 +#define GCC_UFS_ICE_CORE_PDIV_CLK_SRC 6 +/* RCGs and Branches */ +#define GPLL0_EARLY 7 +#define GPLL0 8 +#define GPLL4_EARLY 9 +#define GPLL4 10 +#define SYSTEM_NOC_CLK_SRC 11 +#define CONFIG_NOC_CLK_SRC 12 +#define PERIPH_NOC_CLK_SRC 13 +#define MMSS_BIMC_GFX_CLK_SRC 14 +#define USB30_MASTER_CLK_SRC 15 +#define USB30_MOCK_UTMI_CLK_SRC 16 +#define USB3_PHY_AUX_CLK_SRC 17 +#define USB20_MASTER_CLK_SRC 18 +#define USB20_MOCK_UTMI_CLK_SRC 19 +#define SDCC1_APPS_CLK_SRC 20 +#define SDCC1_ICE_CORE_CLK_SRC 21 +#define SDCC2_APPS_CLK_SRC 22 +#define SDCC3_APPS_CLK_SRC 23 +#define SDCC4_APPS_CLK_SRC 24 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 25 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 26 +#define BLSP1_UART1_APPS_CLK_SRC 27 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 28 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 29 +#define BLSP1_UART2_APPS_CLK_SRC 30 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 31 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 32 +#define BLSP1_UART3_APPS_CLK_SRC 33 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 34 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 35 +#define BLSP1_UART4_APPS_CLK_SRC 36 +#define BLSP1_QUP5_SPI_APPS_CLK_SRC 37 +#define BLSP1_QUP5_I2C_APPS_CLK_SRC 38 +#define BLSP1_UART5_APPS_CLK_SRC 39 +#define BLSP1_QUP6_SPI_APPS_CLK_SRC 40 +#define BLSP1_QUP6_I2C_APPS_CLK_SRC 41 +#define BLSP1_UART6_APPS_CLK_SRC 42 +#define BLSP2_QUP1_SPI_APPS_CLK_SRC 43 +#define BLSP2_QUP1_I2C_APPS_CLK_SRC 44 +#define BLSP2_UART1_APPS_CLK_SRC 45 +#define BLSP2_QUP2_SPI_APPS_CLK_SRC 46 +#define BLSP2_QUP2_I2C_APPS_CLK_SRC 47 +#define BLSP2_UART2_APPS_CLK_SRC 48 +#define BLSP2_QUP3_SPI_APPS_CLK_SRC 49 +#define BLSP2_QUP3_I2C_APPS_CLK_SRC 50 +#define BLSP2_UART3_APPS_CLK_SRC 51 +#define BLSP2_QUP4_SPI_APPS_CLK_SRC 52 +#define BLSP2_QUP4_I2C_APPS_CLK_SRC 53 +#define BLSP2_UART4_APPS_CLK_SRC 54 +#define BLSP2_QUP5_SPI_APPS_CLK_SRC 55 +#define BLSP2_QUP5_I2C_APPS_CLK_SRC 56 +#define BLSP2_UART5_APPS_CLK_SRC 57 +#define BLSP2_QUP6_SPI_APPS_CLK_SRC 58 +#define BLSP2_QUP6_I2C_APPS_CLK_SRC 59 +#define BLSP2_UART6_APPS_CLK_SRC 60 +#define PDM2_CLK_SRC 61 +#define TSIF_REF_CLK_SRC 62 +#define CE1_CLK_SRC 63 +#define GCC_SLEEP_CLK_SRC 64 +#define BIMC_CLK_SRC 65 +#define HMSS_AHB_CLK_SRC 66 +#define BIMC_HMSS_AXI_CLK_SRC 67 +#define HMSS_RBCPR_CLK_SRC 68 +#define HMSS_GPLL0_CLK_SRC 69 +#define GP1_CLK_SRC 70 +#define GP2_CLK_SRC 71 +#define GP3_CLK_SRC 72 +#define PCIE_AUX_CLK_SRC 73 +#define UFS_AXI_CLK_SRC 74 +#define UFS_ICE_CORE_CLK_SRC 75 +#define QSPI_SER_CLK_SRC 76 +#define GCC_SYS_NOC_AXI_CLK 77 +#define GCC_SYS_NOC_HMSS_AHB_CLK 78 +#define GCC_SNOC_CNOC_AHB_CLK 79 +#define GCC_SNOC_PNOC_AHB_CLK 80 +#define GCC_SYS_NOC_AT_CLK 81 +#define GCC_SYS_NOC_USB3_AXI_CLK 82 +#define GCC_SYS_NOC_UFS_AXI_CLK 83 +#define GCC_CFG_NOC_AHB_CLK 84 +#define GCC_PERIPH_NOC_AHB_CLK 85 +#define GCC_PERIPH_NOC_USB20_AHB_CLK 86 +#define GCC_TIC_CLK 87 +#define GCC_IMEM_AXI_CLK 88 +#define GCC_MMSS_SYS_NOC_AXI_CLK 89 +#define GCC_MMSS_NOC_CFG_AHB_CLK 90 +#define GCC_MMSS_BIMC_GFX_CLK 91 +#define GCC_USB30_MASTER_CLK 92 +#define GCC_USB30_SLEEP_CLK 93 +#define GCC_USB30_MOCK_UTMI_CLK 94 +#define GCC_USB3_PHY_AUX_CLK 95 +#define GCC_USB3_PHY_PIPE_CLK 96 +#define GCC_USB20_MASTER_CLK 97 +#define GCC_USB20_SLEEP_CLK 98 +#define GCC_USB20_MOCK_UTMI_CLK 99 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 100 +#define GCC_SDCC1_APPS_CLK 101 +#define GCC_SDCC1_AHB_CLK 102 +#define GCC_SDCC1_ICE_CORE_CLK 103 +#define GCC_SDCC2_APPS_CLK 104 +#define GCC_SDCC2_AHB_CLK 105 +#define GCC_SDCC3_APPS_CLK 106 +#define GCC_SDCC3_AHB_CLK 107 +#define GCC_SDCC4_APPS_CLK 108 +#define GCC_SDCC4_AHB_CLK 109 +#define GCC_BLSP1_AHB_CLK 110 +#define GCC_BLSP1_SLEEP_CLK 111 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 112 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 113 +#define GCC_BLSP1_UART1_APPS_CLK 114 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 115 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 116 +#define GCC_BLSP1_UART2_APPS_CLK 117 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 118 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 119 +#define GCC_BLSP1_UART3_APPS_CLK 120 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 121 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 122 +#define GCC_BLSP1_UART4_APPS_CLK 123 +#define GCC_BLSP1_QUP5_SPI_APPS_CLK 124 +#define GCC_BLSP1_QUP5_I2C_APPS_CLK 125 +#define GCC_BLSP1_UART5_APPS_CLK 126 +#define GCC_BLSP1_QUP6_SPI_APPS_CLK 127 +#define GCC_BLSP1_QUP6_I2C_APPS_CLK 128 +#define GCC_BLSP1_UART6_APPS_CLK 129 +#define GCC_BLSP2_AHB_CLK 130 +#define GCC_BLSP2_SLEEP_CLK 131 +#define GCC_BLSP2_QUP1_SPI_APPS_CLK 132 +#define GCC_BLSP2_QUP1_I2C_APPS_CLK 133 +#define GCC_BLSP2_UART1_APPS_CLK 134 +#define GCC_BLSP2_QUP2_SPI_APPS_CLK 135 +#define GCC_BLSP2_QUP2_I2C_APPS_CLK 136 +#define GCC_BLSP2_UART2_APPS_CLK 137 +#define GCC_BLSP2_QUP3_SPI_APPS_CLK 138 +#define GCC_BLSP2_QUP3_I2C_APPS_CLK 139 +#define GCC_BLSP2_UART3_APPS_CLK 140 +#define GCC_BLSP2_QUP4_SPI_APPS_CLK 141 +#define GCC_BLSP2_QUP4_I2C_APPS_CLK 142 +#define GCC_BLSP2_UART4_APPS_CLK 143 +#define GCC_BLSP2_QUP5_SPI_APPS_CLK 144 +#define GCC_BLSP2_QUP5_I2C_APPS_CLK 145 +#define GCC_BLSP2_UART5_APPS_CLK 146 +#define GCC_BLSP2_QUP6_SPI_APPS_CLK 147 +#define GCC_BLSP2_QUP6_I2C_APPS_CLK 148 +#define GCC_BLSP2_UART6_APPS_CLK 149 +#define GCC_PDM_AHB_CLK 150 +#define GCC_PDM_XO4_CLK 151 +#define GCC_PDM2_CLK 152 +#define GCC_PRNG_AHB_CLK 153 +#define GCC_TSIF_AHB_CLK 154 +#define GCC_TSIF_REF_CLK 155 +#define GCC_TSIF_INACTIVITY_TIMERS_CLK 156 +#define GCC_TCSR_AHB_CLK 157 +#define GCC_BOOT_ROM_AHB_CLK 158 +#define GCC_MSG_RAM_AHB_CLK 159 +#define GCC_TLMM_AHB_CLK 160 +#define GCC_TLMM_CLK 161 +#define GCC_MPM_AHB_CLK 162 +#define GCC_SPMI_SER_CLK 163 +#define GCC_SPMI_CNOC_AHB_CLK 164 +#define GCC_BIMC_HMSS_AXI_CLK 165 +#define GCC_BIMC_GFX_CLK 166 +#define GCC_HMSS_AHB_CLK 167 +#define GCC_HMSS_SLV_AXI_CLK 168 +#define GCC_HMSS_MSTR_AXI_CLK 169 +#define GCC_HMSS_RBCPR_CLK 170 +#define GCC_GP1_CLK 171 +#define GCC_GP2_CLK 172 +#define GCC_GP3_CLK 173 +#define GCC_PCIE_0_SLV_AXI_CLK 174 +#define GCC_PCIE_0_MSTR_AXI_CLK 175 +#define GCC_PCIE_0_CFG_AHB_CLK 176 +#define GCC_PCIE_0_AUX_CLK 177 +#define GCC_PCIE_0_PIPE_CLK 178 +#define GCC_PCIE_1_SLV_AXI_CLK 179 +#define GCC_PCIE_1_MSTR_AXI_CLK 180 +#define GCC_PCIE_1_CFG_AHB_CLK 181 +#define GCC_PCIE_1_AUX_CLK 182 +#define GCC_PCIE_1_PIPE_CLK 183 +#define GCC_PCIE_2_SLV_AXI_CLK 184 +#define GCC_PCIE_2_MSTR_AXI_CLK 185 +#define GCC_PCIE_2_CFG_AHB_CLK 186 +#define GCC_PCIE_2_AUX_CLK 187 +#define GCC_PCIE_2_PIPE_CLK 188 +#define GCC_PCIE_PHY_CFG_AHB_CLK 189 +#define GCC_PCIE_PHY_AUX_CLK 190 +#define GCC_UFS_AXI_CLK 191 +#define GCC_UFS_AHB_CLK 192 +#define GCC_UFS_TX_CFG_CLK 193 +#define GCC_UFS_RX_CFG_CLK 194 +#define GCC_UFS_TX_SYMBOL_0_CLK 195 +#define GCC_UFS_RX_SYMBOL_0_CLK 196 +#define GCC_UFS_RX_SYMBOL_1_CLK 197 +#define GCC_UFS_UNIPRO_CORE_CLK 198 +#define GCC_UFS_ICE_CORE_CLK 199 +#define GCC_UFS_SYS_CLK_CORE_CLK 200 +#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK 201 +#define GCC_AGGRE0_SNOC_AXI_CLK 202 +#define GCC_AGGRE0_CNOC_AHB_CLK 203 +#define GCC_SMMU_AGGRE0_AXI_CLK 204 +#define GCC_SMMU_AGGRE0_AHB_CLK 205 +#define GCC_AGGRE2_UFS_AXI_CLK 206 +#define GCC_AGGRE2_USB3_AXI_CLK 207 +#define GCC_QSPI_AHB_CLK 208 +#define GCC_QSPI_SER_CLK 209 +#define GCC_USB3_CLKREF_CLK 210 +#define GCC_HDMI_CLKREF_CLK 211 +#define GCC_UFS_CLKREF_CLK 212 +#define GCC_PCIE_CLKREF_CLK 213 +#define GCC_RX2_USB2_CLKREF_CLK 214 +#define GCC_RX1_USB2_CLKREF_CLK 215 +#define GCC_AGGRE0_NOC_QOSGEN_EXTREF_CLK 216 +#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 217 +#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 218 +#define GCC_EDP_CLKREF_CLK 219 +#define GCC_MSS_CFG_AHB_CLK 220 +#define GCC_MSS_Q6_BIMC_AXI_CLK 221 +#define GCC_MSS_SNOC_AXI_CLK 222 +#define GCC_MSS_MNOC_BIMC_AXI_CLK 223 +#define GCC_DCC_AHB_CLK 224 +#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK 225 +#define GCC_MMSS_GPLL0_DIV_CLK 226 +#define GPLL0_OUT_MSSCC_CLK 227 + +/* Block resets */ #define GCC_SYSTEM_NOC_BCR 0 #define GCC_CONFIG_NOC_BCR 1 #define GCC_PERIPH_NOC_BCR 2 -- cgit v1.2.3 From 999531d98eb2c6b5afcd7f934631b6f4465691e9 Mon Sep 17 00:00:00 2001 From: Amit Nischal Date: Wed, 21 Dec 2016 17:33:38 +0530 Subject: clk: qcom: Add smd-rpm voter & voter branch clocks for MSM8996 MSM8996 requires the voter & voter branch clocks to be available for clients to be able to enable/disable and set rate on these clocks. Also add support for keeping active set vote on mmssnoc and pnoc voter clocks. Change-Id: Ie596ddee60aac3e6fc996f9a3e8dc988b0f4aa88 Signed-off-by: Amit Nischal --- include/dt-bindings/clock/qcom,rpmcc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h index bcaa1a552e8e..0f0c6300642c 100644 --- a/include/dt-bindings/clock/qcom,rpmcc.h +++ b/include/dt-bindings/clock/qcom,rpmcc.h @@ -128,5 +128,6 @@ #define CXO_PIL_SSC_CLK 83 #define CXO_PIL_CDSP_CLK 84 #define CNOC_PERIPH_KEEPALIVE_A_CLK 85 +#define MMSSNOC_A_CLK_CPU_VOTE 86 #endif -- cgit v1.2.3