ARM: dts: msm: Add and update the dummy clocks for MSMfalcon/MSMtriton

For MSMfalcon and MSMtriton, clock consumers requires dummy
rpmcc, gcc, mmss and gfx clocks for their operation so add
the support for registering dummy clocks as follows:
  - Add clock-output-names property for the rpmcc, gcc, mmss
    and gfx clock controller nodes.
  - Add reset-cells property for clock controller nodes.
  - Add two fixed clock nodes named as xo_board and sleep_clk.
  - Remove RPM clock IDs from qcom,gcc-msmfalcon.h.
  - Modify RPM clock names as per qcom,rpmcc.h file.

Change-Id: I06262fe271ab6ba81d4fa5f67315fd1b54edee8c
Signed-off-by: Amit Nischal <anischal@codeaurora.org>

1 files changed, 0 insertions, 48 deletions

diff --git a/include/dt-bindings/clock/qcom,gcc-msmfalcon.h b/include/dt-bindings/clock/qcom,gcc-msmfalcon.h
index 0bbcbd28af33..609a20422ed1 100644
--- a/include/dt-bindings/clock/qcom,gcc-msmfalcon.h
+++ b/include/dt-bindings/clock/qcom,gcc-msmfalcon.h
@@ -207,52 +207,4 @@
 #define GCC_USB_30_BCR                           7
 #define GCC_USB_PHY_CFG_AHB2PHY_BCR              8
 
-/* RPM controlled clocks */
-#define RPM_CE1_CLK				1
-#define RPM_CE1_A_CLK				2
-#define RPM_CXO_CLK_SRC				3
-#define RPM_BIMC_CLK				4
-#define RPM_BIMC_A_CLK				5
-#define RPM_CNOC_CLK				6
-#define RPM_CNOC_A_CLK				7
-#define RPM_SNOC_CLK				8
-#define RPM_SNOC_A_CLK				9
-#define RPM_CNOC_PERIPH_CLK			10
-#define RPM_CNOC_PERIPH_A_CLK			11
-#define RPM_CNOC_PERIPH_KEEPALIVE_A_CLK		12
-#define RPM_LN_BB_CLK1				13
-#define RPM_LN_BB_CLK1_AO			14
-#define RPM_LN_BB_CLK1_PIN			15
-#define RPM_LN_BB_CLK1_PIN_AO			16
-#define RPM_BIMC_MSMBUS_CLK			17
-#define RPM_BIMC_MSMBUS_A_CLK			18
-#define RPM_CNOC_MSMBUS_CLK			19
-#define RPM_CNOC_MSMBUS_A_CLK			20
-#define RPM_CXO_CLK_SRC_AO			21
-#define RPM_CXO_DWC3_CLK			22
-#define RPM_CXO_LPM_CLK				23
-#define RPM_CXO_OTG_CLK				24
-#define RPM_CXO_PIL_LPASS_CLK			25
-#define RPM_CXO_PIL_SSC_CLK			26
-#define RPM_CXO_PIL_SPSS_CLK			27
-#define RPM_DIV_CLK1				28
-#define RPM_DIV_CLK1_AO				29
-#define RPM_IPA_CLK				30
-#define RPM_IPA_A_CLK				31
-#define RPM_MCD_CE1_CLK				32
-#define RPM_MMSSNOC_AXI_CLK			33
-#define RPM_MMSSNOC_AXI_A_CLK			34
-#define RPM_QCEDEV_CE1_CLK			35
-#define RPM_QCRYPTO_CE1_CLK			36
-#define RPM_QDSS_CLK				37
-#define RPM_QDSS_A_CLK				38
-#define RPM_QSEECOM_CE1_CLK			39
-#define RPM_RF_CLK2				40
-#define RPM_RF_CLK2_AO				41
-#define RPM_SCM_CE1_CLK				42
-#define RPM_SNOC_MSMBUS_CLK			43
-#define RPM_SNOC_MSMBUS_A_CLK			44
-#define RPM_AGGRE2_NOC_CLK			45
-#define RPM_AGGRE2_NOC_A_CLK			46
-
 #endif