ARM: dts: msm: Add and update the dummy clocks for MSMfalcon/MSMtriton

For MSMfalcon and MSMtriton, clock consumers requires dummy
rpmcc, gcc, mmss and gfx clocks for their operation so add
the support for registering dummy clocks as follows:
  - Add clock-output-names property for the rpmcc, gcc, mmss
    and gfx clock controller nodes.
  - Add reset-cells property for clock controller nodes.
  - Add two fixed clock nodes named as xo_board and sleep_clk.
  - Remove RPM clock IDs from qcom,gcc-msmfalcon.h.
  - Modify RPM clock names as per qcom,rpmcc.h file.

Change-Id: I06262fe271ab6ba81d4fa5f67315fd1b54edee8c
Signed-off-by: Amit Nischal <anischal@codeaurora.org>

5 files changed, 123 insertions, 113 deletions

diff --git a/arch/arm/boot/dts/qcom/msmfalcon-bus.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-bus.dtsi
index 11f602d842bc..cb5fce378b6c 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-bus.dtsi
+++ b/arch/arm/boot/dts/qcom/msmfalcon-bus.dtsi
@@ -39,8 +39,8 @@
 			qcom,qos-off = <4096>;
 			qcom,base-offset = <16384>;
 			clock-names = "bus_clk", "bus_a_clk";
-			clocks = <&clock_gcc RPM_AGGRE2_NOC_CLK>,
-				<&clock_gcc RPM_AGGRE2_NOC_A_CLK>;
+			clocks = <&clock_rpmcc RPM_AGGR2_NOC_CLK>,
+				<&clock_rpmcc RPM_AGGR2_NOC_A_CLK>;
 		};
 
 		fab_bimc: fab-bimc {
@@ -52,8 +52,8 @@
 			qcom,bypass-qos-prg;
 			qcom,util-fact = <153>;
 			clock-names = "bus_clk", "bus_a_clk";
-			clocks = <&clock_gcc RPM_BIMC_MSMBUS_CLK>,
-				<&clock_gcc RPM_BIMC_MSMBUS_A_CLK>;
+			clocks = <&clock_rpmcc BIMC_MSMBUS_CLK>,
+				<&clock_rpmcc BIMC_MSMBUS_A_CLK>;
 		};
 
 		fab_cnoc: fab-cnoc {
@@ -64,8 +64,8 @@
 			qcom,bypass-qos-prg;
 			qcom,bus-type = <1>;
 			clock-names = "bus_clk", "bus_a_clk";
-			clocks = <&clock_gcc RPM_CNOC_MSMBUS_CLK>,
-				<&clock_gcc RPM_CNOC_MSMBUS_A_CLK>;
+			clocks = <&clock_rpmcc CNOC_MSMBUS_CLK>,
+				<&clock_rpmcc CNOC_MSMBUS_A_CLK>;
 		};
 
 		fab_gnoc: fab-gnoc {
@@ -87,8 +87,8 @@
 			qcom,base-offset = <20480>;
 			qcom,util-fact = <154>;
 			clock-names = "bus_clk", "bus_a_clk";
-			clocks = <&clock_gcc RPM_MMSSNOC_AXI_CLK>,
-				<&clock_gcc RPM_MMSSNOC_AXI_A_CLK>;
+			clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>,
+				<&clock_rpmcc MMSSNOC_AXI_A_CLK>;
 		};
 
 		fab_snoc: fab-snoc {
@@ -101,8 +101,8 @@
 			qcom,qos-off = <4096>;
 			qcom,base-offset = <24576>;
 			clock-names = "bus_clk", "bus_a_clk";
-			clocks = <&clock_gcc RPM_SNOC_MSMBUS_CLK>,
-				<&clock_gcc RPM_SNOC_MSMBUS_A_CLK>;
+			clocks = <&clock_rpmcc SNOC_MSMBUS_CLK>,
+				<&clock_rpmcc SNOC_MSMBUS_A_CLK>;
 		};
 
 		fab_mnoc_ahb: fab-mnoc-ahb {
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-coresight.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-coresight.dtsi
index b60d4013dad8..3826b00bf09e 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-coresight.dtsi
+++ b/arch/arm/boot/dts/qcom/msmfalcon-coresight.dtsi
@@ -30,8 +30,8 @@
 
 		coresight-name = "coresight-tmc-etr";
 
-		clocks = <&clock_gcc RPM_QDSS_CLK>,
-			 <&clock_gcc RPM_QDSS_A_CLK>;
+		clocks = <&clock_rpmcc RPM_QDSS_CLK>,
+			 <&clock_rpmcc RPM_QDSS_A_CLK>;
 		clock-names = "apb_pclk", "core_a_clk";
 
 		port{
@@ -80,8 +80,8 @@
 
 		coresight-ctis = <&cti0 &cti8>;
 
-		clocks = <&clock_gcc RPM_QDSS_CLK>,
-			 <&clock_gcc RPM_QDSS_A_CLK>;
+		clocks = <&clock_rpmcc RPM_QDSS_CLK>,
+			 <&clock_rpmcc RPM_QDSS_A_CLK>;
 		clock-names = "apb_pclk", "core_a_clk";
 
 		ports{
@@ -115,8 +115,8 @@
 
 		coresight-name = "coresight-funnel-merg";
 
-		clocks = <&clock_gcc RPM_QDSS_CLK>,
-			 <&clock_gcc RPM_QDSS_A_CLK>;
+		clocks = <&clock_rpmcc RPM_QDSS_CLK>,
+			 <&clock_rpmcc RPM_QDSS_A_CLK>;
 		clock-names = "apb_pclk", "core_a_clk";
 
 		ports {
@@ -150,8 +150,8 @@
 
 		coresight-name = "coresight-funnel-in0";
 
-		clocks = <&clock_gcc RPM_QDSS_CLK>,
-			 <&clock_gcc RPM_QDSS_A_CLK>;
+		clocks = <&clock_rpmcc RPM_QDSS_CLK>,
+			 <&clock_rpmcc RPM_QDSS_A_CLK>;
 		clock-names = "apb_pclk", "core_a_clk";
 
 		ports {
@@ -193,8 +193,8 @@
 
 		coresight-name = "coresight-stm";
 
-		clocks = <&clock_gcc RPM_QDSS_CLK>,
-			 <&clock_gcc RPM_QDSS_A_CLK>;
+		clocks = <&clock_rpmcc RPM_QDSS_CLK>,
+			 <&clock_rpmcc RPM_QDSS_A_CLK>;
 		clock-names = "apb_pclk", "core_a_clk";
 
 		port{
@@ -211,8 +211,8 @@
 
 		coresight-name = "coresight-cti0";
 
-		clocks = <&clock_gcc RPM_QDSS_CLK>,
-			 <&clock_gcc RPM_QDSS_A_CLK>;
+		clocks = <&clock_rpmcc RPM_QDSS_CLK>,
+			 <&clock_rpmcc RPM_QDSS_A_CLK>;
 		clock-names = "core_clk", "core_a_clk";
 	};
 
@@ -223,8 +223,8 @@
 
 		coresight-name = "coresight-cti1";
 
-		clocks = <&clock_gcc RPM_QDSS_CLK>,
-			 <&clock_gcc RPM_QDSS_A_CLK>;
+		clocks = <&clock_rpmcc RPM_QDSS_CLK>,
+			 <&clock_rpmcc RPM_QDSS_A_CLK>;
 		clock-names = "core_clk", "core_a_clk";
 	};
 
@@ -235,8 +235,8 @@
 
 		coresight-name = "coresight-cti2";
 
-		clocks = <&clock_gcc RPM_QDSS_CLK>,
-			 <&clock_gcc RPM_QDSS_A_CLK>;
+		clocks = <&clock_rpmcc RPM_QDSS_CLK>,
+			 <&clock_rpmcc RPM_QDSS_A_CLK>;
 		clock-names = "core_clk", "core_a_clk";
 	};
 
@@ -247,8 +247,8 @@
 
 		coresight-name = "coresight-cti3";
 
-		clocks = <&clock_gcc RPM_QDSS_CLK>,
-			 <&clock_gcc RPM_QDSS_A_CLK>;
+		clocks = <&clock_rpmcc RPM_QDSS_CLK>,
+			 <&clock_rpmcc RPM_QDSS_A_CLK>;
 		clock-names = "core_clk", "core_a_clk";
 	};
 
@@ -259,8 +259,8 @@
 
 		coresight-name = "coresight-cti4";
 
-		clocks = <&clock_gcc RPM_QDSS_CLK>,
-			 <&clock_gcc RPM_QDSS_A_CLK>;
+		clocks = <&clock_rpmcc RPM_QDSS_CLK>,
+			 <&clock_rpmcc RPM_QDSS_A_CLK>;
 		clock-names = "core_clk", "core_a_clk";
 	};
 
@@ -271,8 +271,8 @@
 
 		coresight-name = "coresight-cti5";
 
-		clocks = <&clock_gcc RPM_QDSS_CLK>,
-			 <&clock_gcc RPM_QDSS_A_CLK>;
+		clocks = <&clock_rpmcc RPM_QDSS_CLK>,
+			 <&clock_rpmcc RPM_QDSS_A_CLK>;
 		clock-names = "core_clk", "core_a_clk";
 	};
 
@@ -283,8 +283,8 @@
 
 		coresight-name = "coresight-cti6";
 
-		clocks = <&clock_gcc RPM_QDSS_CLK>,
-			 <&clock_gcc RPM_QDSS_A_CLK>;
+		clocks = <&clock_rpmcc RPM_QDSS_CLK>,
+			 <&clock_rpmcc RPM_QDSS_A_CLK>;
 		clock-names = "core_clk", "core_a_clk";
 	};
 
@@ -295,8 +295,8 @@
 
 		coresight-name = "coresight-cti7";
 
-		clocks = <&clock_gcc RPM_QDSS_CLK>,
-			 <&clock_gcc RPM_QDSS_A_CLK>;
+		clocks = <&clock_rpmcc RPM_QDSS_CLK>,
+			 <&clock_rpmcc RPM_QDSS_A_CLK>;
 		clock-names = "core_clk", "core_a_clk";
 	};
 
@@ -307,8 +307,8 @@
 
 		coresight-name = "coresight-cti8";
 
-		clocks = <&clock_gcc RPM_QDSS_CLK>,
-			 <&clock_gcc RPM_QDSS_A_CLK>;
+		clocks = <&clock_rpmcc RPM_QDSS_CLK>,
+			 <&clock_rpmcc RPM_QDSS_A_CLK>;
 		clock-names = "core_clk", "core_a_clk";
 	};
 
@@ -319,8 +319,8 @@
 
 		coresight-name = "coresight-cti9";
 
-		clocks = <&clock_gcc RPM_QDSS_CLK>,
-			 <&clock_gcc RPM_QDSS_A_CLK>;
+		clocks = <&clock_rpmcc RPM_QDSS_CLK>,
+			 <&clock_rpmcc RPM_QDSS_A_CLK>;
 		clock-names = "core_clk", "core_a_clk";
 	};
 
@@ -331,8 +331,8 @@
 
 		coresight-name = "coresight-cti10";
 
-		clocks = <&clock_gcc RPM_QDSS_CLK>,
-			 <&clock_gcc RPM_QDSS_A_CLK>;
+		clocks = <&clock_rpmcc RPM_QDSS_CLK>,
+			 <&clock_rpmcc RPM_QDSS_A_CLK>;
 		clock-names = "core_clk", "core_a_clk";
 	};
 
@@ -343,8 +343,8 @@
 
 		coresight-name = "coresight-cti11";
 
-		clocks = <&clock_gcc RPM_QDSS_CLK>,
-			 <&clock_gcc RPM_QDSS_A_CLK>;
+		clocks = <&clock_rpmcc RPM_QDSS_CLK>,
+			 <&clock_rpmcc RPM_QDSS_A_CLK>;
 		clock-names = "core_clk", "core_a_clk";
 	};
 
@@ -355,8 +355,8 @@
 
 		coresight-name = "coresight-cti12";
 
-		clocks = <&clock_gcc RPM_QDSS_CLK>,
-			 <&clock_gcc RPM_QDSS_A_CLK>;
+		clocks = <&clock_rpmcc RPM_QDSS_CLK>,
+			 <&clock_rpmcc RPM_QDSS_A_CLK>;
 		clock-names = "core_clk", "core_a_clk";
 	};
 
@@ -367,8 +367,8 @@
 
 		coresight-name = "coresight-cti13";
 
-		clocks = <&clock_gcc RPM_QDSS_CLK>,
-			 <&clock_gcc RPM_QDSS_A_CLK>;
+		clocks = <&clock_rpmcc RPM_QDSS_CLK>,
+			 <&clock_rpmcc RPM_QDSS_A_CLK>;
 		clock-names = "core_clk", "core_a_clk";
 	};
 
@@ -379,8 +379,8 @@
 
 		coresight-name = "coresight-cti14";
 
-		clocks = <&clock_gcc RPM_QDSS_CLK>,
-			 <&clock_gcc RPM_QDSS_A_CLK>;
+		clocks = <&clock_rpmcc RPM_QDSS_CLK>,
+			 <&clock_rpmcc RPM_QDSS_A_CLK>;
 		clock-names = "core_clk", "core_a_clk";
 	};
 
@@ -391,8 +391,8 @@
 
 		coresight-name = "coresight-cti15";
 
-		clocks = <&clock_gcc RPM_QDSS_CLK>,
-			 <&clock_gcc RPM_QDSS_A_CLK>;
+		clocks = <&clock_rpmcc RPM_QDSS_CLK>,
+			 <&clock_rpmcc RPM_QDSS_A_CLK>;
 		clock-names = "core_clk", "core_a_clk";
 	};
 
@@ -405,8 +405,8 @@
 
 		coresight-name = "coresight-funnel-qatb";
 
-		clocks = <&clock_gcc RPM_QDSS_CLK>,
-			 <&clock_gcc RPM_QDSS_A_CLK>;
+		clocks = <&clock_rpmcc RPM_QDSS_CLK>,
+			 <&clock_rpmcc RPM_QDSS_A_CLK>;
 		clock-names = "apb_pclk", "core_a_clk";
 
 		ports {
@@ -451,8 +451,8 @@
 				     <5 32>,
 				     <9 64>;
 
-		clocks = <&clock_gcc RPM_QDSS_CLK>,
-			 <&clock_gcc RPM_QDSS_A_CLK>;
+		clocks = <&clock_rpmcc RPM_QDSS_CLK>,
+			 <&clock_rpmcc RPM_QDSS_A_CLK>;
 		clock-names = "core_clk", "core_a_clk";
 
 		ports {
@@ -483,8 +483,8 @@
 
 		coresight-name = "coresight-tpdm-dcc";
 
-		clocks = <&clock_gcc RPM_QDSS_CLK>,
-			 <&clock_gcc RPM_QDSS_A_CLK>;
+		clocks = <&clock_rpmcc RPM_QDSS_CLK>,
+			 <&clock_rpmcc RPM_QDSS_A_CLK>;
 		clock-names = "core_clk", "core_a_clk";
 
 		port{
diff --git a/arch/arm/boot/dts/qcom/msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msmfalcon.dtsi
index 67748d6683c0..dcb58699ca7b 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon.dtsi
+++ b/arch/arm/boot/dts/qcom/msmfalcon.dtsi
@@ -14,6 +14,7 @@
 #include <dt-bindings/clock/qcom,gcc-msmfalcon.h>
 #include <dt-bindings/clock/qcom,gpu-msmfalcon.h>
 #include <dt-bindings/clock/qcom,mmcc-msmfalcon.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
 
@@ -135,6 +136,22 @@
 		};
 	};
 
+	clocks {
+		xo_board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <19200000>;
+			clock-output-names = "xo_board";
+		};
+
+		sleep_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32764>;
+			clock-output-names = "sleep_clk";
+		};
+	};
+
 	soc: soc { };
 
 	reserved-memory {
@@ -360,19 +377,31 @@
 		};
 	};
 
-	clock_gcc: qcom,dummycc {
+	clock_rpmcc: qcom,dummycc {
+		compatible = "qcom,dummycc";
+		clock-output-names = "rpmcc_clocks";
+		#clock-cells = <1>;
+	};
+
+	clock_gcc: clock-controller@100000 {
 		compatible = "qcom,dummycc";
+		clock-output-names = "gcc_clocks";
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
-	clock_mmss: qcom,dummycc {
+	clock_mmss: clock-controller@c8c0000 {
 		compatible = "qcom,dummycc";
+		clock-output-names = "mmss_clocks";
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
-	clock_gfx: qcom,dummycc {
+	clock_gfx: clock-controller@5065000 {
 		compatible = "qcom,dummycc";
+		clock-output-names = "gfx_clocks";
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 	qcom,ipc-spinlock@1f40000 {
@@ -398,7 +427,7 @@
 		      <0x10b4000 0x800>;
 		reg-names = "dcc-base", "dcc-ram-base";
 
-		clocks = <&clock_gcc RPM_QDSS_CLK>;
+		clocks = <&clock_rpmcc RPM_QDSS_CLK>;
 		clock-names = "dcc_clk";
 	};
 
diff --git a/arch/arm/boot/dts/qcom/msmtriton.dtsi b/arch/arm/boot/dts/qcom/msmtriton.dtsi
index 3f0d4cc48696..f847d00c2cc9 100644
--- a/arch/arm/boot/dts/qcom/msmtriton.dtsi
+++ b/arch/arm/boot/dts/qcom/msmtriton.dtsi
@@ -14,6 +14,7 @@
 #include <dt-bindings/clock/qcom,gcc-msmfalcon.h>
 #include <dt-bindings/clock/qcom,gpu-msmfalcon.h>
 #include <dt-bindings/clock/qcom,mmcc-msmfalcon.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
@@ -134,6 +135,22 @@
 		};
 	};
 
+	clocks {
+		xo_board {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <19200000>;
+			clock-output-names = "xo_board";
+		};
+
+		sleep_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <32764>;
+			clock-output-names = "sleep_clk";
+		};
+	};
+
 	soc: soc { };
 
 	reserved-memory {
@@ -308,19 +325,31 @@
 		};
 	};
 
-	clock_gcc: qcom,dummycc {
+	clock_rpmcc: qcom,dummycc {
+		compatible = "qcom,dummycc";
+		clock-output-names = "rpmcc_clocks";
+		#clock-cells = <1>;
+	};
+
+	clock_gcc: clock-controller@100000 {
 		compatible = "qcom,dummycc";
+		clock-output-names = "gcc_clocks";
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
-	clock_mmss: qcom,dummycc {
+	clock_mmss: clock-controller@c8c0000 {
 		compatible = "qcom,dummycc";
+		clock-output-names = "mmss_clocks";
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
-	clock_gfx: qcom,dummycc {
+	clock_gfx: clock-controller@5065000 {
 		compatible = "qcom,dummycc";
+		clock-output-names = "gfx_clocks";
 		#clock-cells = <1>;
+		#reset-cells = <1>;
 	};
 
 	qcom,ipc-spinlock@1f40000 {
diff --git a/include/dt-bindings/clock/qcom,gcc-msmfalcon.h b/include/dt-bindings/clock/qcom,gcc-msmfalcon.h
index 0bbcbd28af33..609a20422ed1 100644
--- a/include/dt-bindings/clock/qcom,gcc-msmfalcon.h
+++ b/include/dt-bindings/clock/qcom,gcc-msmfalcon.h
@@ -207,52 +207,4 @@
 #define GCC_USB_30_BCR                           7
 #define GCC_USB_PHY_CFG_AHB2PHY_BCR              8
 
-/* RPM controlled clocks */
-#define RPM_CE1_CLK				1
-#define RPM_CE1_A_CLK				2
-#define RPM_CXO_CLK_SRC				3
-#define RPM_BIMC_CLK				4
-#define RPM_BIMC_A_CLK				5
-#define RPM_CNOC_CLK				6
-#define RPM_CNOC_A_CLK				7
-#define RPM_SNOC_CLK				8
-#define RPM_SNOC_A_CLK				9
-#define RPM_CNOC_PERIPH_CLK			10
-#define RPM_CNOC_PERIPH_A_CLK			11
-#define RPM_CNOC_PERIPH_KEEPALIVE_A_CLK		12
-#define RPM_LN_BB_CLK1				13
-#define RPM_LN_BB_CLK1_AO			14
-#define RPM_LN_BB_CLK1_PIN			15
-#define RPM_LN_BB_CLK1_PIN_AO			16
-#define RPM_BIMC_MSMBUS_CLK			17
-#define RPM_BIMC_MSMBUS_A_CLK			18
-#define RPM_CNOC_MSMBUS_CLK			19
-#define RPM_CNOC_MSMBUS_A_CLK			20
-#define RPM_CXO_CLK_SRC_AO			21
-#define RPM_CXO_DWC3_CLK			22
-#define RPM_CXO_LPM_CLK				23
-#define RPM_CXO_OTG_CLK				24
-#define RPM_CXO_PIL_LPASS_CLK			25
-#define RPM_CXO_PIL_SSC_CLK			26
-#define RPM_CXO_PIL_SPSS_CLK			27
-#define RPM_DIV_CLK1				28
-#define RPM_DIV_CLK1_AO				29
-#define RPM_IPA_CLK				30
-#define RPM_IPA_A_CLK				31
-#define RPM_MCD_CE1_CLK				32
-#define RPM_MMSSNOC_AXI_CLK			33
-#define RPM_MMSSNOC_AXI_A_CLK			34
-#define RPM_QCEDEV_CE1_CLK			35
-#define RPM_QCRYPTO_CE1_CLK			36
-#define RPM_QDSS_CLK				37
-#define RPM_QDSS_A_CLK				38
-#define RPM_QSEECOM_CE1_CLK			39
-#define RPM_RF_CLK2				40
-#define RPM_RF_CLK2_AO				41
-#define RPM_SCM_CE1_CLK				42
-#define RPM_SNOC_MSMBUS_CLK			43
-#define RPM_SNOC_MSMBUS_A_CLK			44
-#define RPM_AGGRE2_NOC_CLK			45
-#define RPM_AGGRE2_NOC_A_CLK			46
-
 #endif