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| author | Andre Przywara <andre.przywara@arm.com> | 2016-06-28 18:07:29 +0100 |
|---|---|---|
| committer | Amit Pundir <amit.pundir@linaro.org> | 2016-10-12 17:34:22 +0530 |
| commit | 96836c618aeeefcaee43624cb53c7a2b1c394dae (patch) | |
| tree | eac9f3dace9bc9d90b9914ba6566610e119675f2 /include/linux/timerqueue.h | |
| parent | bef1ce21fc8fa72ef9816f863d79962f330fd0ad (diff) | |
UPSTREAM: arm64: include alternative handling in dcache_by_line_op
The newly introduced dcache_by_line_op macro is used at least in
one occassion at the moment to issue a "dc cvau" instruction,
which is affected by ARM errata 819472, 826319, 827319 and 824069.
Change the macro to allow for alternative patching in there to
protect affected Cortex-A53 cores.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[catalin.marinas@arm.com: indentation fixups]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Change-Id: I450594dc311b09b6b832b707a9abb357608cc6e4
(cherry picked from commit 823066d9edcdfe4cedb06216c2b1f91efaf68a87)
Signed-off-by: Sami Tolvanen <samitolvanen@google.com>
Diffstat (limited to 'include/linux/timerqueue.h')
0 files changed, 0 insertions, 0 deletions