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| author | Andre Przywara <andre.przywara@arm.com> | 2016-06-28 18:07:28 +0100 |
|---|---|---|
| committer | Amit Pundir <amit.pundir@linaro.org> | 2016-10-12 17:34:22 +0530 |
| commit | bef1ce21fc8fa72ef9816f863d79962f330fd0ad (patch) | |
| tree | 47569c5aa36fd8bb037834d594bb15838b1857ea /include/linux/timerqueue.h | |
| parent | 395caccf0eae01f40f41ea68b574bda5c64ac72c (diff) | |
UPSTREAM: arm64: fix "dc cvau" cache operation on errata-affected core
The ARM errata 819472, 826319, 827319 and 824069 for affected
Cortex-A53 cores demand to promote "dc cvau" instructions to
"dc civac" as well.
Attribute the usage of the instruction in __flush_cache_user_range
to also be covered by our alternative patching efforts.
For that we introduce an assembly macro which both deals with
alternatives while still tagging the instructions as USER.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Change-Id: If5e7933ba32331b2aa28fc5d9e019649452f0f6c
(cherry picked from commit 290622efc76ece22ef76a30bf117755891ab27f6)
Signed-off-by: Sami Tolvanen <samitolvanen@google.com>
Diffstat (limited to 'include/linux/timerqueue.h')
0 files changed, 0 insertions, 0 deletions