msm: Rename msmfalcon/apqfalcon to sdm660/sda660

Update the code name from msmfalcon/apqfalcon to sdm660/sda660.
As part of this, update the filename containing "falcon" and
files content containing "falcon".

Change-Id: Iec85862251b9e1b4dcc8bdce8b214ce87c0049bc
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>

10 files changed, 182 insertions, 182 deletions

diff --git a/drivers/clk/msm/Kconfig b/drivers/clk/msm/Kconfig
index bfb697347ec5..3829f6aec124 100644
--- a/drivers/clk/msm/Kconfig
+++ b/drivers/clk/msm/Kconfig
@@ -7,7 +7,7 @@ config COMMON_CLK_MSM
 	  This support clock controller used by MSM devices which support
 	  global, mmss and gpu clock controller.
 	  Say Y if you want to support the clocks exposed by the MSM on
-	  platforms such as msm8996, msm8998, msmfalcon etc.
+	  platforms such as msm8996, msm8998 etc.
 
 config MSM_CLK_CONTROLLER_V2
 	bool "QTI clock driver"
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index b5dd556b3f96..5a6b62892328 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -153,33 +153,33 @@ config MSM_MMCC_8996
 	  Say Y if you want to support multimedia devices such as display,
 	  graphics, video encode/decode, camera, etc.
 
-config MSM_GCC_FALCON
-	tristate "MSMFALCON Global Clock Controller"
+config MSM_GCC_660
+	tristate "SDM660 Global Clock Controller"
 	select QCOM_GDSC
 	depends on COMMON_CLK_QCOM
 	---help---
 	  Support for the global clock controller on Qualcomm Technologies, Inc
-	  MSMfalcon devices.
+	  SDM660 devices.
 	  Say Y if you want to use peripheral devices such as UART, SPI, I2C,
 	  USB, UFS, SD/eMMC, PCIe, etc.
 
-config MSM_GPUCC_FALCON
-	tristate "MSMFALCON Graphics Clock Controller"
-	select MSM_GCC_FALCON
+config MSM_GPUCC_660
+	tristate "SDM660 Graphics Clock Controller"
+	select MSM_GCC_660
 	depends on COMMON_CLK_QCOM
 	help
 	  Support for the graphics clock controller on Qualcomm Technologies, Inc
-	  MSMfalcon devices.
+	  SDM660 devices.
 	  Say Y if you want to support graphics controller devices which will
 	  be required to enable those device.
 
-config MSM_MMCC_FALCON
-	tristate "MSMFALCON Multimedia Clock Controller"
-	select MSM_GCC_FALCON
+config MSM_MMCC_660
+	tristate "SDM660 Multimedia Clock Controller"
+	select MSM_GCC_660
 	depends on COMMON_CLK_QCOM
 	help
 	  Support for the multimedia clock controller on Qualcomm Technologies, Inc
-	  MSMfalcon devices.
+	  SDM660 devices.
 	  Say Y if you want to support multimedia devices such as display,
 	  video encode/decode, camera, etc.
 
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index a63065c97319..481cda67974b 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -25,12 +25,12 @@ obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
 obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
 obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
 obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o
-obj-$(CONFIG_MSM_GCC_FALCON) += gcc-msmfalcon.o
+obj-$(CONFIG_MSM_GCC_660) += gcc-sdm660.o
 obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
 obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
 obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
-obj-$(CONFIG_MSM_GPUCC_FALCON) += gpucc-msmfalcon.o
-obj-$(CONFIG_MSM_MMCC_FALCON) += mmcc-msmfalcon.o
+obj-$(CONFIG_MSM_GPUCC_660) += gpucc-sdm660.o
+obj-$(CONFIG_MSM_MMCC_660) += mmcc-sdm660.o
 obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
 obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
 obj-$(CONFIG_KRAITCC) += krait-cc.o
diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
index d14c32bffe14..9332e99e642b 100644
--- a/drivers/clk/qcom/clk-smd-rpm.c
+++ b/drivers/clk/qcom/clk-smd-rpm.c
@@ -656,75 +656,75 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8996 = {
 	.num_clks = ARRAY_SIZE(msm8996_clks),
 };
 
-/* msmfalcon */
-DEFINE_CLK_SMD_RPM_BRANCH(msmfalcon, cxo, cxo_a, QCOM_SMD_RPM_MISC_CLK, 0,
+/* sdm660 */
+DEFINE_CLK_SMD_RPM_BRANCH(sdm660, cxo, cxo_a, QCOM_SMD_RPM_MISC_CLK, 0,
 								19200000);
-DEFINE_CLK_SMD_RPM(msmfalcon, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
-DEFINE_CLK_SMD_RPM(msmfalcon, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
-DEFINE_CLK_SMD_RPM(msmfalcon, cnoc_periph_clk, cnoc_periph_a_clk,
+DEFINE_CLK_SMD_RPM(sdm660, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
+DEFINE_CLK_SMD_RPM(sdm660, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
+DEFINE_CLK_SMD_RPM(sdm660, cnoc_periph_clk, cnoc_periph_a_clk,
 						QCOM_SMD_RPM_BUS_CLK, 0);
-DEFINE_CLK_SMD_RPM(msmfalcon, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
-DEFINE_CLK_SMD_RPM(msmfalcon, mmssnoc_axi_clk, mmssnoc_axi_a_clk,
+DEFINE_CLK_SMD_RPM(sdm660, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
+DEFINE_CLK_SMD_RPM(sdm660, mmssnoc_axi_clk, mmssnoc_axi_a_clk,
 						   QCOM_SMD_RPM_MMAXI_CLK, 0);
-DEFINE_CLK_SMD_RPM(msmfalcon, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
-DEFINE_CLK_SMD_RPM(msmfalcon, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
-DEFINE_CLK_SMD_RPM(msmfalcon, aggre2_noc_clk, aggre2_noc_a_clk,
+DEFINE_CLK_SMD_RPM(sdm660, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
+DEFINE_CLK_SMD_RPM(sdm660, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
+DEFINE_CLK_SMD_RPM(sdm660, aggre2_noc_clk, aggre2_noc_a_clk,
 						QCOM_SMD_RPM_AGGR_CLK, 2);
-DEFINE_CLK_SMD_RPM_QDSS(msmfalcon, qdss_clk, qdss_a_clk,
+DEFINE_CLK_SMD_RPM_QDSS(sdm660, qdss_clk, qdss_a_clk,
 						QCOM_SMD_RPM_MISC_CLK, 1);
-DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, rf_clk1, rf_clk1_ao, 4);
-DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, div_clk1, div_clk1_ao, 0xb);
-DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, ln_bb_clk1, ln_bb_clk1_ao, 0x1);
-DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, ln_bb_clk2, ln_bb_clk2_ao, 0x2);
-DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, ln_bb_clk3, ln_bb_clk3_ao, 0x3);
-
-DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, rf_clk1_pin, rf_clk1_ao_pin, 4);
-DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk1_pin,
+DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, rf_clk1, rf_clk1_ao, 4);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, div_clk1, div_clk1_ao, 0xb);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk1, ln_bb_clk1_ao, 0x1);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk2, ln_bb_clk2_ao, 0x2);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_ao, 0x3);
+
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, rf_clk1_pin, rf_clk1_ao_pin, 4);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk1_pin,
 							ln_bb_clk1_pin_ao, 0x1);
-DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk2_pin,
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk2_pin,
 							ln_bb_clk2_pin_ao, 0x2);
-DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk3_pin,
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin,
 							ln_bb_clk3_pin_ao, 0x3);
 
-static struct clk_hw *msmfalcon_clks[] = {
-	[RPM_XO_CLK_SRC]	= &msmfalcon_cxo.hw,
-	[RPM_XO_A_CLK_SRC]	= &msmfalcon_cxo_a.hw,
-	[RPM_SNOC_CLK]		= &msmfalcon_snoc_clk.hw,
-	[RPM_SNOC_A_CLK]	= &msmfalcon_snoc_a_clk.hw,
-	[RPM_BIMC_CLK]		= &msmfalcon_bimc_clk.hw,
-	[RPM_BIMC_A_CLK]	= &msmfalcon_bimc_a_clk.hw,
-	[RPM_QDSS_CLK]		= &msmfalcon_qdss_clk.hw,
-	[RPM_QDSS_A_CLK]	= &msmfalcon_qdss_a_clk.hw,
-	[RPM_RF_CLK1]		= &msmfalcon_rf_clk1.hw,
-	[RPM_RF_CLK1_A]		= &msmfalcon_rf_clk1_ao.hw,
-	[RPM_RF_CLK1_PIN]	= &msmfalcon_rf_clk1_pin.hw,
-	[RPM_RF_CLK1_A_PIN]	= &msmfalcon_rf_clk1_ao_pin.hw,
-	[RPM_AGGR2_NOC_CLK]	= &msmfalcon_aggre2_noc_clk.hw,
-	[RPM_AGGR2_NOC_A_CLK]	= &msmfalcon_aggre2_noc_a_clk.hw,
-	[RPM_CNOC_CLK]		= &msmfalcon_cnoc_clk.hw,
-	[RPM_CNOC_A_CLK]	= &msmfalcon_cnoc_a_clk.hw,
-	[RPM_IPA_CLK]		= &msmfalcon_ipa_clk.hw,
-	[RPM_IPA_A_CLK]		= &msmfalcon_ipa_a_clk.hw,
-	[RPM_CE1_CLK]		= &msmfalcon_ce1_clk.hw,
-	[RPM_CE1_A_CLK]		= &msmfalcon_ce1_a_clk.hw,
-	[RPM_DIV_CLK1]		= &msmfalcon_div_clk1.hw,
-	[RPM_DIV_CLK1_AO]	= &msmfalcon_div_clk1_ao.hw,
-	[RPM_LN_BB_CLK1]	= &msmfalcon_ln_bb_clk1.hw,
-	[RPM_LN_BB_CLK1]	= &msmfalcon_ln_bb_clk1_ao.hw,
-	[RPM_LN_BB_CLK1_PIN]	= &msmfalcon_ln_bb_clk1_pin.hw,
-	[RPM_LN_BB_CLK1_PIN_AO]	= &msmfalcon_ln_bb_clk1_pin_ao.hw,
-	[RPM_LN_BB_CLK2]	= &msmfalcon_ln_bb_clk2.hw,
-	[RPM_LN_BB_CLK2_AO]	= &msmfalcon_ln_bb_clk2_ao.hw,
-	[RPM_LN_BB_CLK2_PIN]	= &msmfalcon_ln_bb_clk2_pin.hw,
-	[RPM_LN_BB_CLK2_PIN_AO] = &msmfalcon_ln_bb_clk2_pin_ao.hw,
-	[RPM_LN_BB_CLK3]	= &msmfalcon_ln_bb_clk3.hw,
-	[RPM_LN_BB_CLK3_AO]	= &msmfalcon_ln_bb_clk3_ao.hw,
-	[RPM_LN_BB_CLK3_PIN]	= &msmfalcon_ln_bb_clk3_pin.hw,
-	[RPM_LN_BB_CLK3_PIN_AO] = &msmfalcon_ln_bb_clk3_pin_ao.hw,
-	[RPM_CNOC_PERIPH_CLK]	= &msmfalcon_cnoc_periph_clk.hw,
-	[RPM_CNOC_PERIPH_A_CLK] = &msmfalcon_cnoc_periph_a_clk.hw,
-	[MMSSNOC_AXI_CLK]	= &msmfalcon_mmssnoc_axi_clk.hw,
-	[MMSSNOC_AXI_A_CLK]	= &msmfalcon_mmssnoc_axi_a_clk.hw,
+static struct clk_hw *sdm660_clks[] = {
+	[RPM_XO_CLK_SRC]	= &sdm660_cxo.hw,
+	[RPM_XO_A_CLK_SRC]	= &sdm660_cxo_a.hw,
+	[RPM_SNOC_CLK]		= &sdm660_snoc_clk.hw,
+	[RPM_SNOC_A_CLK]	= &sdm660_snoc_a_clk.hw,
+	[RPM_BIMC_CLK]		= &sdm660_bimc_clk.hw,
+	[RPM_BIMC_A_CLK]	= &sdm660_bimc_a_clk.hw,
+	[RPM_QDSS_CLK]		= &sdm660_qdss_clk.hw,
+	[RPM_QDSS_A_CLK]	= &sdm660_qdss_a_clk.hw,
+	[RPM_RF_CLK1]		= &sdm660_rf_clk1.hw,
+	[RPM_RF_CLK1_A]		= &sdm660_rf_clk1_ao.hw,
+	[RPM_RF_CLK1_PIN]	= &sdm660_rf_clk1_pin.hw,
+	[RPM_RF_CLK1_A_PIN]	= &sdm660_rf_clk1_ao_pin.hw,
+	[RPM_AGGR2_NOC_CLK]	= &sdm660_aggre2_noc_clk.hw,
+	[RPM_AGGR2_NOC_A_CLK]	= &sdm660_aggre2_noc_a_clk.hw,
+	[RPM_CNOC_CLK]		= &sdm660_cnoc_clk.hw,
+	[RPM_CNOC_A_CLK]	= &sdm660_cnoc_a_clk.hw,
+	[RPM_IPA_CLK]		= &sdm660_ipa_clk.hw,
+	[RPM_IPA_A_CLK]		= &sdm660_ipa_a_clk.hw,
+	[RPM_CE1_CLK]		= &sdm660_ce1_clk.hw,
+	[RPM_CE1_A_CLK]		= &sdm660_ce1_a_clk.hw,
+	[RPM_DIV_CLK1]		= &sdm660_div_clk1.hw,
+	[RPM_DIV_CLK1_AO]	= &sdm660_div_clk1_ao.hw,
+	[RPM_LN_BB_CLK1]	= &sdm660_ln_bb_clk1.hw,
+	[RPM_LN_BB_CLK1]	= &sdm660_ln_bb_clk1_ao.hw,
+	[RPM_LN_BB_CLK1_PIN]	= &sdm660_ln_bb_clk1_pin.hw,
+	[RPM_LN_BB_CLK1_PIN_AO]	= &sdm660_ln_bb_clk1_pin_ao.hw,
+	[RPM_LN_BB_CLK2]	= &sdm660_ln_bb_clk2.hw,
+	[RPM_LN_BB_CLK2_AO]	= &sdm660_ln_bb_clk2_ao.hw,
+	[RPM_LN_BB_CLK2_PIN]	= &sdm660_ln_bb_clk2_pin.hw,
+	[RPM_LN_BB_CLK2_PIN_AO] = &sdm660_ln_bb_clk2_pin_ao.hw,
+	[RPM_LN_BB_CLK3]	= &sdm660_ln_bb_clk3.hw,
+	[RPM_LN_BB_CLK3_AO]	= &sdm660_ln_bb_clk3_ao.hw,
+	[RPM_LN_BB_CLK3_PIN]	= &sdm660_ln_bb_clk3_pin.hw,
+	[RPM_LN_BB_CLK3_PIN_AO] = &sdm660_ln_bb_clk3_pin_ao.hw,
+	[RPM_CNOC_PERIPH_CLK]	= &sdm660_cnoc_periph_clk.hw,
+	[RPM_CNOC_PERIPH_A_CLK] = &sdm660_cnoc_periph_a_clk.hw,
+	[MMSSNOC_AXI_CLK]	= &sdm660_mmssnoc_axi_clk.hw,
+	[MMSSNOC_AXI_A_CLK]	= &sdm660_mmssnoc_axi_a_clk.hw,
 
 	/* Voter Clocks */
 	[BIMC_MSMBUS_CLK]	= &bimc_msmbus_clk.hw,
@@ -746,16 +746,16 @@ static struct clk_hw *msmfalcon_clks[] = {
 	[CNOC_PERIPH_KEEPALIVE_A_CLK] = &cnoc_periph_keepalive_a_clk.hw,
 };
 
-static const struct rpm_smd_clk_desc rpm_clk_msmfalcon = {
-	.clks = msmfalcon_clks,
+static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {
+	.clks = sdm660_clks,
 	.num_rpm_clks = RPM_CNOC_PERIPH_A_CLK,
-	.num_clks = ARRAY_SIZE(msmfalcon_clks),
+	.num_clks = ARRAY_SIZE(sdm660_clks),
 };
 
 static const struct of_device_id rpm_smd_clk_match_table[] = {
 	{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916},
 	{ .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996},
-	{ .compatible = "qcom,rpmcc-msmfalcon", .data = &rpm_clk_msmfalcon},
+	{ .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
@@ -766,21 +766,21 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)
 	struct clk *clk;
 	struct rpm_cc *rcc;
 	struct clk_onecell_data *data;
-	int ret, is_8996 = 0, is_falcon = 0;
+	int ret, is_8996 = 0, is_660 = 0;
 	size_t num_clks, i;
 	struct clk_hw **hw_clks;
 	const struct rpm_smd_clk_desc *desc;
 
 	is_8996 = of_device_is_compatible(pdev->dev.of_node,
 						"qcom,rpmcc-msm8996");
-	is_falcon = of_device_is_compatible(pdev->dev.of_node,
-						"qcom,rpmcc-msmfalcon");
+	is_660 = of_device_is_compatible(pdev->dev.of_node,
+						"qcom,rpmcc-sdm660");
 	if (is_8996) {
 		ret = clk_vote_bimc(&msm8996_bimc_clk.hw, INT_MAX);
 		if (ret < 0)
 			return ret;
-	} else if (is_falcon) {
-		ret = clk_vote_bimc(&msmfalcon_bimc_clk.hw, INT_MAX);
+	} else if (is_660) {
+		ret = clk_vote_bimc(&sdm660_bimc_clk.hw, INT_MAX);
 		if (ret < 0)
 			return ret;
 	}
@@ -849,8 +849,8 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)
 		clk_prepare_enable(pnoc_keepalive_a_clk.hw.clk);
 
 		clk_prepare_enable(mmssnoc_a_clk_cpu_vote.hw.clk);
-	} else if (is_falcon) {
-		clk_prepare_enable(msmfalcon_cxo_a.hw.clk);
+	} else if (is_660) {
+		clk_prepare_enable(sdm660_cxo_a.hw.clk);
 
 		/* Hold an active set vote for the cnoc_periph resource */
 		clk_set_rate(cnoc_periph_keepalive_a_clk.hw.clk, 19200000);
diff --git a/drivers/clk/qcom/gcc-msmfalcon.c b/drivers/clk/qcom/gcc-sdm660.c
index 1e1c871ef22c..da4c6e8797d7 100644
--- a/drivers/clk/qcom/gcc-msmfalcon.c
+++ b/drivers/clk/qcom/gcc-sdm660.c
@@ -23,7 +23,7 @@
 #include <linux/of_device.h>
 #include <linux/regmap.h>
 #include <linux/reset-controller.h>
-#include <dt-bindings/clock/qcom,gcc-msmfalcon.h>
+#include <dt-bindings/clock/qcom,gcc-sdm660.h>
 
 #include "clk-alpha-pll.h"
 #include "clk-branch.h"
@@ -32,7 +32,7 @@
 #include "clk-regmap.h"
 #include "clk-rcg.h"
 #include "reset.h"
-#include "vdd-level-falcon.h"
+#include "vdd-level-660.h"
 
 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
 
@@ -2580,7 +2580,7 @@ static struct clk_fixed_factor gcc_ce1_axi_m_clk = {
 	},
 };
 
-struct clk_hw *gcc_msmfalcon_hws[] = {
+struct clk_hw *gcc_sdm660_hws[] = {
 	[GCC_XO] =      &xo.hw,
 	[GCC_GPLL0_EARLY_DIV] = &gpll0_out_early_div.hw,
 	[GCC_GPLL1_EARLY_DIV] = &gpll1_out_early_div.hw,
@@ -2588,7 +2588,7 @@ struct clk_hw *gcc_msmfalcon_hws[] = {
 	[GCC_CE1_AXI_M_CLK] = &gcc_ce1_axi_m_clk.hw,
 };
 
-static struct clk_regmap *gcc_falcon_clocks[] = {
+static struct clk_regmap *gcc_660_clocks[] = {
 	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
 	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
 	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
@@ -2728,7 +2728,7 @@ static struct clk_regmap *gcc_falcon_clocks[] = {
 					&hlos2_vote_turing_adsp_smmu_clk.clkr,
 };
 
-static const struct qcom_reset_map gcc_falcon_resets[] = {
+static const struct qcom_reset_map gcc_660_resets[] = {
 	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
 	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
 	[GCC_UFS_BCR] = { 0x75000 },
@@ -2740,7 +2740,7 @@ static const struct qcom_reset_map gcc_falcon_resets[] = {
 	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
 };
 
-static const struct regmap_config gcc_falcon_regmap_config = {
+static const struct regmap_config gcc_660_regmap_config = {
 	.reg_bits	= 32,
 	.reg_stride	= 4,
 	.val_bits	= 32,
@@ -2748,28 +2748,28 @@ static const struct regmap_config gcc_falcon_regmap_config = {
 	.fast_io	= true,
 };
 
-static const struct qcom_cc_desc gcc_falcon_desc = {
-	.config = &gcc_falcon_regmap_config,
-	.clks = gcc_falcon_clocks,
-	.num_clks = ARRAY_SIZE(gcc_falcon_clocks),
-	.hwclks = gcc_msmfalcon_hws,
-	.num_hwclks = ARRAY_SIZE(gcc_msmfalcon_hws),
-	.resets = gcc_falcon_resets,
-	.num_resets = ARRAY_SIZE(gcc_falcon_resets),
+static const struct qcom_cc_desc gcc_660_desc = {
+	.config = &gcc_660_regmap_config,
+	.clks = gcc_660_clocks,
+	.num_clks = ARRAY_SIZE(gcc_660_clocks),
+	.hwclks = gcc_sdm660_hws,
+	.num_hwclks = ARRAY_SIZE(gcc_sdm660_hws),
+	.resets = gcc_660_resets,
+	.num_resets = ARRAY_SIZE(gcc_660_resets),
 };
 
-static const struct of_device_id gcc_falcon_match_table[] = {
-	{ .compatible = "qcom,gcc-msmfalcon" },
+static const struct of_device_id gcc_660_match_table[] = {
+	{ .compatible = "qcom,gcc-sdm660" },
 	{ }
 };
-MODULE_DEVICE_TABLE(of, gcc_falcon_match_table);
+MODULE_DEVICE_TABLE(of, gcc_660_match_table);
 
-static int gcc_falcon_probe(struct platform_device *pdev)
+static int gcc_660_probe(struct platform_device *pdev)
 {
 	int ret = 0;
 	struct regmap *regmap;
 
-	regmap = qcom_cc_map(pdev, &gcc_falcon_desc);
+	regmap = qcom_cc_map(pdev, &gcc_660_desc);
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
 
@@ -2795,7 +2795,7 @@ static int gcc_falcon_probe(struct platform_device *pdev)
 		return PTR_ERR(vdd_dig_ao.regulator[0]);
 	}
 
-	ret = qcom_cc_really_probe(pdev, &gcc_falcon_desc, regmap);
+	ret = qcom_cc_really_probe(pdev, &gcc_660_desc, regmap);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed to register GCC clocks\n");
 		return ret;
@@ -2816,25 +2816,25 @@ static int gcc_falcon_probe(struct platform_device *pdev)
 	return ret;
 }
 
-static struct platform_driver gcc_falcon_driver = {
-	.probe		= gcc_falcon_probe,
+static struct platform_driver gcc_660_driver = {
+	.probe		= gcc_660_probe,
 	.driver		= {
-		.name	= "gcc-msmfalcon",
-		.of_match_table = gcc_falcon_match_table,
+		.name	= "gcc-sdm660",
+		.of_match_table = gcc_660_match_table,
 	},
 };
 
-static int __init gcc_falcon_init(void)
+static int __init gcc_660_init(void)
 {
-	return platform_driver_register(&gcc_falcon_driver);
+	return platform_driver_register(&gcc_660_driver);
 }
-core_initcall_sync(gcc_falcon_init);
+core_initcall_sync(gcc_660_init);
 
-static void __exit gcc_falcon_exit(void)
+static void __exit gcc_660_exit(void)
 {
-	platform_driver_unregister(&gcc_falcon_driver);
+	platform_driver_unregister(&gcc_660_driver);
 }
-module_exit(gcc_falcon_exit);
+module_exit(gcc_660_exit);
 
 /* Debug Mux for measure */
 static struct measure_clk_data debug_mux_priv = {
@@ -3210,11 +3210,11 @@ static struct clk_debug_mux gcc_debug_mux = {
 };
 
 static const struct of_device_id clk_debug_match_table[] = {
-	{ .compatible = "qcom,gcc-debug-msmfalcon" },
+	{ .compatible = "qcom,gcc-debug-sdm660" },
 	{}
 };
 
-static int clk_debug_falcon_probe(struct platform_device *pdev)
+static int clk_debug_660_probe(struct platform_device *pdev)
 {
 	struct resource *res;
 	struct clk *clk;
@@ -3307,16 +3307,16 @@ static int clk_debug_falcon_probe(struct platform_device *pdev)
 }
 
 static struct platform_driver clk_debug_driver = {
-	.probe = clk_debug_falcon_probe,
+	.probe = clk_debug_660_probe,
 	.driver = {
-		.name = "gcc-debug-msmfalcon",
+		.name = "gcc-debug-sdm660",
 		.of_match_table = clk_debug_match_table,
 		.owner = THIS_MODULE,
 	},
 };
 
-int __init clk_debug_falcon_init(void)
+int __init clk_debug_660_init(void)
 {
 	return platform_driver_register(&clk_debug_driver);
 }
-fs_initcall(clk_debug_falcon_init);
+fs_initcall(clk_debug_660_init);
diff --git a/drivers/clk/qcom/gpucc-msmfalcon.c b/drivers/clk/qcom/gpucc-sdm660.c
index 9b7dd907a6f3..b16b17451c76 100644
--- a/drivers/clk/qcom/gpucc-msmfalcon.c
+++ b/drivers/clk/qcom/gpucc-sdm660.c
@@ -22,7 +22,7 @@
 #include <linux/of_device.h>
 #include <linux/regmap.h>
 #include <linux/reset-controller.h>
-#include <dt-bindings/clock/qcom,gpu-msmfalcon.h>
+#include <dt-bindings/clock/qcom,gpu-sdm660.h>
 
 #include "clk-alpha-pll.h"
 #include "common.h"
@@ -30,7 +30,7 @@
 #include "clk-pll.h"
 #include "clk-rcg.h"
 #include "clk-branch.h"
-#include "vdd-level-falcon.h"
+#include "vdd-level-660.h"
 
 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
 #define F_GFX(f, s, h, m, n, sf) { (f), (s), (2 * (h) - 1), (m), (n), (sf) }
@@ -316,7 +316,7 @@ static struct clk_branch gpucc_rbcpr_clk = {
 	},
 };
 
-static struct clk_regmap *gpucc_falcon_clocks[] = {
+static struct clk_regmap *gpucc_660_clocks[] = {
 	[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
 	[GPU_PLL0_PLL] = &gpu_pll0_pll_out_main.clkr,
 	[GPU_PLL1_PLL] = &gpu_pll1_pll_out_main.clkr,
@@ -328,7 +328,7 @@ static struct clk_regmap *gpucc_falcon_clocks[] = {
 	[RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
 };
 
-static const struct regmap_config gpucc_falcon_regmap_config = {
+static const struct regmap_config gpucc_660_regmap_config = {
 	.reg_bits	= 32,
 	.reg_stride	= 4,
 	.val_bits	= 32,
@@ -336,18 +336,18 @@ static const struct regmap_config gpucc_falcon_regmap_config = {
 	.fast_io	= true,
 };
 
-static const struct qcom_cc_desc gpucc_falcon_desc = {
-	.config = &gpucc_falcon_regmap_config,
-	.clks = gpucc_falcon_clocks,
-	.num_clks = ARRAY_SIZE(gpucc_falcon_clocks),
+static const struct qcom_cc_desc gpucc_660_desc = {
+	.config = &gpucc_660_regmap_config,
+	.clks = gpucc_660_clocks,
+	.num_clks = ARRAY_SIZE(gpucc_660_clocks),
 };
 
-static const struct of_device_id gpucc_falcon_match_table[] = {
-	{ .compatible = "qcom,gpucc-msmfalcon" },
+static const struct of_device_id gpucc_660_match_table[] = {
+	{ .compatible = "qcom,gpucc-sdm660" },
 	{ .compatible = "qcom,gpucc-msmtriton" },
 	{ }
 };
-MODULE_DEVICE_TABLE(of, gpucc_falcon_match_table);
+MODULE_DEVICE_TABLE(of, gpucc_660_match_table);
 
 static int of_get_fmax_vdd_class(struct platform_device *pdev,
 		struct clk_hw *hw, char *prop_name, u32 index)
@@ -407,13 +407,13 @@ static int of_get_fmax_vdd_class(struct platform_device *pdev,
 	return 0;
 }
 
-static int gpucc_falcon_probe(struct platform_device *pdev)
+static int gpucc_660_probe(struct platform_device *pdev)
 {
 	int ret = 0;
 	struct regmap *regmap;
 	bool is_triton = 0;
 
-	regmap = qcom_cc_map(pdev, &gpucc_falcon_desc);
+	regmap = qcom_cc_map(pdev, &gpucc_660_desc);
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
 
@@ -464,7 +464,7 @@ static int gpucc_falcon_probe(struct platform_device *pdev)
 	clk_alpha_pll_configure(&gpu_pll1_pll_out_main, regmap,
 							&gpu_pll0_config);
 
-	ret = qcom_cc_really_probe(pdev, &gpucc_falcon_desc, regmap);
+	ret = qcom_cc_really_probe(pdev, &gpucc_660_desc, regmap);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed to register GPUCC clocks\n");
 		return ret;
@@ -477,22 +477,22 @@ static int gpucc_falcon_probe(struct platform_device *pdev)
 	return ret;
 }
 
-static struct platform_driver gpucc_falcon_driver = {
-	.probe		= gpucc_falcon_probe,
+static struct platform_driver gpucc_660_driver = {
+	.probe		= gpucc_660_probe,
 	.driver		= {
-		.name	= "gpucc-msmfalcon",
-		.of_match_table = gpucc_falcon_match_table,
+		.name	= "gpucc-sdm660",
+		.of_match_table = gpucc_660_match_table,
 	},
 };
 
-static int __init gpucc_falcon_init(void)
+static int __init gpucc_660_init(void)
 {
-	return platform_driver_register(&gpucc_falcon_driver);
+	return platform_driver_register(&gpucc_660_driver);
 }
-core_initcall_sync(gpucc_falcon_init);
+core_initcall_sync(gpucc_660_init);
 
-static void __exit gpucc_falcon_exit(void)
+static void __exit gpucc_660_exit(void)
 {
-	platform_driver_unregister(&gpucc_falcon_driver);
+	platform_driver_unregister(&gpucc_660_driver);
 }
-module_exit(gpucc_falcon_exit);
+module_exit(gpucc_660_exit);
diff --git a/drivers/clk/qcom/mdss/mdss-pll.c b/drivers/clk/qcom/mdss/mdss-pll.c
index b51ab4f21561..f356be38a25c 100644
--- a/drivers/clk/qcom/mdss/mdss-pll.c
+++ b/drivers/clk/qcom/mdss/mdss-pll.c
@@ -133,9 +133,9 @@ static int mdss_pll_resource_parse(struct platform_device *pdev,
 		pll_res->pll_interface_type = MDSS_DSI_PLL_8996;
 		pll_res->target_id = MDSS_PLL_TARGET_8996;
 		pll_res->revision = 2;
-	} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_msmfalcon")) {
+	} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_sdm660")) {
 		pll_res->pll_interface_type = MDSS_DSI_PLL_8996;
-		pll_res->target_id = MDSS_PLL_TARGET_MSMFALCON;
+		pll_res->target_id = MDSS_PLL_TARGET_SDM660;
 		pll_res->revision = 2;
 	} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8998")) {
 		pll_res->pll_interface_type = MDSS_DSI_PLL_8998;
@@ -382,7 +382,7 @@ static const struct of_device_id mdss_pll_dt_match[] = {
 	{.compatible = "qcom,mdss_hdmi_pll_8996_v3_1p8"},
 	{.compatible = "qcom,mdss_dp_pll_8998"},
 	{.compatible = "qcom,mdss_hdmi_pll_8998"},
-	{.compatible = "qcom,mdss_dsi_pll_msmfalcon"},
+	{.compatible = "qcom,mdss_dsi_pll_sdm660"},
 	{}
 };
 
diff --git a/drivers/clk/qcom/mdss/mdss-pll.h b/drivers/clk/qcom/mdss/mdss-pll.h
index 01664eaa815c..e0e62a0f379b 100644
--- a/drivers/clk/qcom/mdss/mdss-pll.h
+++ b/drivers/clk/qcom/mdss/mdss-pll.h
@@ -51,7 +51,7 @@ enum {
 
 enum {
 	MDSS_PLL_TARGET_8996,
-	MDSS_PLL_TARGET_MSMFALCON,
+	MDSS_PLL_TARGET_SDM660,
 };
 
 #define DFPS_MAX_NUM_OF_FRAME_RATES 20
diff --git a/drivers/clk/qcom/mmcc-msmfalcon.c b/drivers/clk/qcom/mmcc-sdm660.c
index 59dbebd825fd..daece455454c 100644
--- a/drivers/clk/qcom/mmcc-msmfalcon.c
+++ b/drivers/clk/qcom/mmcc-sdm660.c
@@ -21,7 +21,7 @@
 #include <linux/clk-provider.h>
 #include <linux/regmap.h>
 #include <linux/reset-controller.h>
-#include <dt-bindings/clock/qcom,mmcc-msmfalcon.h>
+#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
 
 #include "clk-alpha-pll.h"
 #include "clk-branch.h"
@@ -32,7 +32,7 @@
 #include "clk-regmap-divider.h"
 #include "clk-voter.h"
 #include "reset.h"
-#include "vdd-level-falcon.h"
+#include "vdd-level-660.h"
 
 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
 #define F_SLEW(f, s, h, m, n, src_freq) { (f), (s), (2 * (h) - 1), (m), (n), \
@@ -2816,12 +2816,12 @@ static struct clk_branch mmss_video_subcore0_clk = {
 	},
 };
 
-struct clk_hw *mmcc_msmfalcon_hws[] = {
+struct clk_hw *mmcc_sdm660_hws[] = {
 	[MMSS_CAMSS_JPEG0_VOTE_CLK] = &mmss_camss_jpeg0_vote_clk.hw,
 	[MMSS_CAMSS_JPEG0_DMA_VOTE_CLK] = &mmss_camss_jpeg0_dma_vote_clk.hw,
 };
 
-static struct clk_regmap *mmcc_falcon_clocks[] = {
+static struct clk_regmap *mmcc_660_clocks[] = {
 	[AHB_CLK_SRC] = &ahb_clk_src.clkr,
 	[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
 	[BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
@@ -2954,11 +2954,11 @@ static struct clk_regmap *mmcc_falcon_clocks[] = {
 	[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
 };
 
-static const struct qcom_reset_map mmcc_falcon_resets[] = {
+static const struct qcom_reset_map mmcc_660_resets[] = {
 	[CAMSS_MICRO_BCR] = { 0x3490 },
 };
 
-static const struct regmap_config mmcc_falcon_regmap_config = {
+static const struct regmap_config mmcc_660_regmap_config = {
 	.reg_bits	= 32,
 	.reg_stride	= 4,
 	.val_bits	= 32,
@@ -2966,28 +2966,28 @@ static const struct regmap_config mmcc_falcon_regmap_config = {
 	.fast_io	= true,
 };
 
-static const struct qcom_cc_desc mmcc_falcon_desc = {
-	.config = &mmcc_falcon_regmap_config,
-	.clks = mmcc_falcon_clocks,
-	.num_clks = ARRAY_SIZE(mmcc_falcon_clocks),
-	.hwclks = mmcc_msmfalcon_hws,
-	.num_hwclks = ARRAY_SIZE(mmcc_msmfalcon_hws),
-	.resets = mmcc_falcon_resets,
-	.num_resets = ARRAY_SIZE(mmcc_falcon_resets),
+static const struct qcom_cc_desc mmcc_660_desc = {
+	.config = &mmcc_660_regmap_config,
+	.clks = mmcc_660_clocks,
+	.num_clks = ARRAY_SIZE(mmcc_660_clocks),
+	.hwclks = mmcc_sdm660_hws,
+	.num_hwclks = ARRAY_SIZE(mmcc_sdm660_hws),
+	.resets = mmcc_660_resets,
+	.num_resets = ARRAY_SIZE(mmcc_660_resets),
 };
 
-static const struct of_device_id mmcc_falcon_match_table[] = {
-	{ .compatible = "qcom,mmcc-msmfalcon" },
+static const struct of_device_id mmcc_660_match_table[] = {
+	{ .compatible = "qcom,mmcc-sdm660" },
 	{ }
 };
-MODULE_DEVICE_TABLE(of, mmcc_falcon_match_table);
+MODULE_DEVICE_TABLE(of, mmcc_660_match_table);
 
-static int mmcc_falcon_probe(struct platform_device *pdev)
+static int mmcc_660_probe(struct platform_device *pdev)
 {
 	int ret = 0;
 	struct regmap *regmap;
 
-	regmap = qcom_cc_map(pdev, &mmcc_falcon_desc);
+	regmap = qcom_cc_map(pdev, &mmcc_660_desc);
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
 
@@ -3024,7 +3024,7 @@ static int mmcc_falcon_probe(struct platform_device *pdev)
 	clk_alpha_pll_configure(&mmpll8_pll_out_main, regmap, &mmpll8_config);
 	clk_alpha_pll_configure(&mmpll10_pll_out_main, regmap, &mmpll10_config);
 
-	ret = qcom_cc_really_probe(pdev, &mmcc_falcon_desc, regmap);
+	ret = qcom_cc_really_probe(pdev, &mmcc_660_desc, regmap);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed to register MMSS clocks\n");
 		return ret;
@@ -3035,22 +3035,22 @@ static int mmcc_falcon_probe(struct platform_device *pdev)
 	return ret;
 }
 
-static struct platform_driver mmcc_falcon_driver = {
-	.probe		= mmcc_falcon_probe,
+static struct platform_driver mmcc_660_driver = {
+	.probe		= mmcc_660_probe,
 	.driver		= {
-		.name	= "mmcc-msmfalcon",
-		.of_match_table = mmcc_falcon_match_table,
+		.name	= "mmcc-sdm660",
+		.of_match_table = mmcc_660_match_table,
 	},
 };
 
-static int __init mmcc_falcon_init(void)
+static int __init mmcc_660_init(void)
 {
-	return platform_driver_register(&mmcc_falcon_driver);
+	return platform_driver_register(&mmcc_660_driver);
 }
-core_initcall_sync(mmcc_falcon_init);
+core_initcall_sync(mmcc_660_init);
 
-static void __exit mmcc_falcon_exit(void)
+static void __exit mmcc_660_exit(void)
 {
-	platform_driver_unregister(&mmcc_falcon_driver);
+	platform_driver_unregister(&mmcc_660_driver);
 }
-module_exit(mmcc_falcon_exit);
+module_exit(mmcc_660_exit);
diff --git a/drivers/clk/qcom/vdd-level-falcon.h b/drivers/clk/qcom/vdd-level-660.h
index 75567dbe2329..f98a96033ea9 100644
--- a/drivers/clk/qcom/vdd-level-falcon.h
+++ b/drivers/clk/qcom/vdd-level-660.h
@@ -11,8 +11,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_FALCON_H
-#define __DRIVERS_CLK_QCOM_VDD_LEVEL_FALCON_H
+#ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_660_H
+#define __DRIVERS_CLK_QCOM_VDD_LEVEL_660_H
 
 #include <linux/regulator/rpm-smd-regulator.h>
 #include <linux/regulator/consumer.h>