msm: Rename msmfalcon/apqfalcon to sdm660/sda660

Update the code name from msmfalcon/apqfalcon to sdm660/sda660.
As part of this, update the filename containing "falcon" and
files content containing "falcon".

Change-Id: Iec85862251b9e1b4dcc8bdce8b214ce87c0049bc
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>

161 files changed, 1829 insertions, 1829 deletions

diff --git a/Documentation/devicetree/bindings/arm/msm/msm.txt b/Documentation/devicetree/bindings/arm/msm/msm.txt
index 9a96f74a8603..6dd0c2d9c011 100644
--- a/Documentation/devicetree/bindings/arm/msm/msm.txt
+++ b/Documentation/devicetree/bindings/arm/msm/msm.txt
@@ -89,11 +89,11 @@ SoCs:
 - MSMHAMSTER
   compatible = "qcom,msmhamster"
 
-- MSMFALCON
-  compatible = "qcom,msmfalcon"
+- SDM660
+  compatible = "qcom,sdm660"
 
-- APQFALCON
-  compatible = "qcom,apqfalcon"
+- SDA660
+  compatible = "qcom,sda660"
 
 - MSMTRITON
   compatible = "qcom,msmtriton"
@@ -263,13 +263,13 @@ compatible = "qcom,msm8998-qrd"
 compatible = "qcom,msmhamster-rumi"
 compatible = "qcom,msmhamster-cdp"
 compatible = "qcom,msmhamster-mtp"
-compatible = "qcom,msmfalcon-sim"
-compatible = "qcom,msmfalcon-rumi"
-compatible = "qcom,msmfalcon-cdp"
-compatible = "qcom,msmfalcon-mtp"
-compatible = "qcom,msmfalcon-qrd"
-compatible = "qcom,apqfalcon-mtp"
-compatible = "qcom,apqfalcon-cdp"
+compatible = "qcom,sdm660-sim"
+compatible = "qcom,sdm660-rumi"
+compatible = "qcom,sdm660-cdp"
+compatible = "qcom,sdm660-mtp"
+compatible = "qcom,sdm660-qrd"
+compatible = "qcom,sda660-mtp"
+compatible = "qcom,sda660-cdp"
 compatible = "qcom,msmtriton-rumi"
 compatible = "qcom,msm8952-rumi"
 compatible = "qcom,msm8952-sim"
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-dbg.txt b/Documentation/devicetree/bindings/clock/qcom,gcc-dbg.txt
index e1ccf69b751b..5c770864898a 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-dbg.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-dbg.txt
@@ -3,7 +3,7 @@ Qualcomm Technologies Inc Global Clock Debug Controller Binding
 
 Required properties :
 - compatible:	shall contain the following:
-			"qcom,gcc-debug-msmfalcon"
+			"qcom,gcc-debug-sdm660"
 
 - reg:		shall contain global clock controller
 	        base register offset location and length.
@@ -24,7 +24,7 @@ In the case where "qcom,cc-count" is > 1, the below needs to be defined.
 
 Example:
 	clock_gcc: clock-controller@100000 {
-		compatible = "qcom,gcc-msmfalcon", "syscon";
+		compatible = "qcom,gcc-sdm660", "syscon";
 		....
 	};
 
@@ -44,7 +44,7 @@ Example:
 	};
 
 	clock_debug: qcom,cc-debug@62000 {
-		compatible = "qcom,gcc-debug-msmfalcon";
+		compatible = "qcom,gcc-debug-sdm660";
 		reg = <0x62000 0x4>;
 		reg-names = "cc_offset";
 		clocks = <&clock_rpmcc  RPM_XO_CLK_SRC>;
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 1330d2bdc18d..479a83df3808 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -14,7 +14,7 @@ Required properties :
 			"qcom,gcc-msm8974pro"
 			"qcom,gcc-msm8974pro-ac"
 			"qcom,gcc-msm8996"
-			"qcom,gcc-msmfalcon"
+			"qcom,gcc-sdm660"
 
 - reg : shall contain base register location and length
 - #clock-cells : shall contain 1
diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt
index 4d8f87225230..8eadd50e09f6 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt
@@ -4,7 +4,7 @@ Qualcomm Technologies, Inc Graphics Clock & Reset Controller Binding
 Required properties :
 - compatible : shall contain only one of the following:
 
-			"qcom,gpucc-msmfalcon",
+			"qcom,gpucc-sdm660",
 			"qcom,gpucc-msmtriton"
 
 - reg : shall contain base register location and length
@@ -16,7 +16,7 @@ Optional properties :
 
 Example:
 	clock-controller@4000000 {
-		compatible = "qcom,gpucc-msmfalcon";
+		compatible = "qcom,gpucc-sdm660";
 		reg = <<0x5065000 0x10000>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
index 6aaf89c47781..4b1057288b2f 100644
--- a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
@@ -10,7 +10,7 @@ Required properties :
 			"qcom,mmcc-msm8960"
 			"qcom,mmcc-msm8974"
 			"qcom,mmcc-msm8996"
-			"qcom,mmcc-msmfalcon"
+			"qcom,mmcc-sdm660"
 
 - reg : shall contain base register location and length
 - #clock-cells : shall contain 1
diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
index f825a44e5911..685fb3aa2e61 100644
--- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
@@ -13,7 +13,7 @@ Required properties :
 			"qcom,rpmcc-msm8916", "qcom,rpmcc"
 			"qcom,rpmcc-apq8064", "qcom,rpmcc"
 			"qcom,rpmcc-msm8996", "qcom,rpmcc"
-			"qcom,rpmcc-msmfalcon", "qcom,rpmcc"
+			"qcom,rpmcc-sdm660", "qcom,rpmcc"
 
 - #clock-cells : shall contain 1
 
@@ -38,7 +38,7 @@ Example:
 		};
 	};
 
-	The below are applicable for MSM8996 & MSMFalcon.
+	The below are applicable for MSM8996 & SDM660.
 
 	rpmcc: clock-controller {
 		compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
diff --git a/Documentation/devicetree/bindings/fb/mdss-pll.txt b/Documentation/devicetree/bindings/fb/mdss-pll.txt
index e9e4a9af381b..5d9a703c4823 100644
--- a/Documentation/devicetree/bindings/fb/mdss-pll.txt
+++ b/Documentation/devicetree/bindings/fb/mdss-pll.txt
@@ -15,7 +15,7 @@ Required properties:
 			"qcom,mdss_hdmi_pll_8996_v2", "qcom,mdss_dsi_pll_8996_v2",
 			"qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_hdmi_pll_8996_v3_1p8",
 			"qcom,mdss_dsi_pll_8998", "qcom,mdss_dp_pll_8998",
-			"qcom,mdss_hdmi_pll_8998", "qcom,mdss_dsi_pll_msmfalcon"
+			"qcom,mdss_hdmi_pll_8998", "qcom,mdss_dsi_pll_sdm660"
 - cell-index:		Specifies the controller used
 - reg:			offset and length of the register set for the device.
 - reg-names :		names to refer to register sets related to this device
diff --git a/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt b/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt
index 581f1128355c..da54fb11ffd4 100644
--- a/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt
+++ b/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt
@@ -98,7 +98,7 @@ Optional properties:
 				  used if qcom,thermal-derate-en is specified.
 				  Allowed values are:
 				  0, 15, 30, 45 for pmi8998.
-				  0, 20, 40, 60 for pm2falcon.
+				  0, 20, 40, 60 for pm660l.
 - qcom,thermal-thrsh1		: Integer property to specify OTST1 threshold
 				  for thermal mitigation. Unit is in Celsius.
 				  Accepted values are:
diff --git a/Documentation/devicetree/bindings/leds/leds-qpnp-wled.txt b/Documentation/devicetree/bindings/leds/leds-qpnp-wled.txt
index 74cee0d6ba0d..a77a291a99da 100644
--- a/Documentation/devicetree/bindings/leds/leds-qpnp-wled.txt
+++ b/Documentation/devicetree/bindings/leds/leds-qpnp-wled.txt
@@ -28,13 +28,13 @@ Optional properties for WLED:
 - qcom,vref-uv		: maximum reference voltage in uV.
 			  For pmi8994/8952/8996, supported values are from 300000 to 675000
 			  with a step size of 25000, the default value is 350000.
-			  For pmi8998/pm2falcon, supported values are from 60000 to 397500
+			  For pmi8998/pm660l, supported values are from 60000 to 397500
 			  with a step size of 22500, the default value is 127500.
 - qcom,switch-freq-khz	: switch frequency in khz. default is 800.
 - qcom,ovp-mv		: Over voltage protection threshold in mV. Default is
 			  29500. Supported values are:
 			  - 31000, 29500, 19400, 17800 for pmi8994/8952/8996.
-			  - 31100, 29600, 19600, 18100 for pmi8998/pm2falcon.
+			  - 31100, 29600, 19600, 18100 for pmi8998/pm660l.
 			  Should only be used if qcom,disp-type-amoled is not
 			  specified.
 - qcom,ilim-ma		: Current limit threshold in mA.
@@ -42,7 +42,7 @@ Optional properties for WLED:
 			  and AMOLED is 385mA.
 			  Supported values are:
 			  - 105, 385, 660, 980, 1150, 1420, 1700, 1980.
-			  For pmi8998/pm2falcon, default value for LCD is
+			  For pmi8998/pm660l, default value for LCD is
 			  970mA and AMOLED is 620mA.
 			  Supported values are:
 			  - 105, 280, 450, 620, 970, 1150, 1300, 1500.
@@ -81,7 +81,7 @@ Optional properties if 'qcom,disp-type-amoled' is mentioned in DT:
 - qcom,vref-psm-mv	: reference psm voltage in mv. default for amoled is 450.
 - qcom,avdd-mode-spmi: Boolean property to enable AMOLED_VOUT programming via SPMI. If not specified,
 			AMOLED_VOUT is programmed via S-wire. This can be specified only for newer
-			PMICs like pmi8998/pm2falcon.
+			PMICs like pmi8998/pm660l.
 - qcom,avdd-target-voltage-mv: The voltage required for AMOLED_VOUT. Accepted values are in the range
 				of 5650 to 7900 in steps of 150. Default value is 7600. Unit is in mV.
 				For old revisions, accepted values are: 7900, 7600, 7300, 6400, 6100,
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msmfalcon-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-pinctrl.txt
index 929ba3ee688b..dbd4baf0825a 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,msmfalcon-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-pinctrl.txt
@@ -1,12 +1,12 @@
-Qualcomm Technologies, Inc. MSMFALCON TLMM block
+Qualcomm Technologies, Inc. SDM660 TLMM block
 
 This binding describes the Top Level Mode Multiplexer block found in the
-MSMFALCON platform.
+SDM660 platform.
 
 - compatible:
 	Usage: required
 	Value type: <string>
-	Definition: must be "qcom,msmfalcon-pinctrl"
+	Definition: must be "qcom,sdm660-pinctrl"
 
 - reg:
 	Usage: required
@@ -176,7 +176,7 @@ to specify in a pin configuration subnode:
 Example:
 
 	tlmm: pinctrl@01010000 {
-		compatible = "qcom,msmfalcon-pinctrl";
+		compatible = "qcom,sdm660-pinctrl";
 		reg = <0x01010000 0x300000>;
 		interrupts = <0 208 0>;
 		gpio-controller;
diff --git a/Documentation/devicetree/bindings/regulator/cpr4-mmss-ldo-regulator.txt b/Documentation/devicetree/bindings/regulator/cpr4-mmss-ldo-regulator.txt
index 41cec67b7627..851528517f4c 100644
--- a/Documentation/devicetree/bindings/regulator/cpr4-mmss-ldo-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/cpr4-mmss-ldo-regulator.txt
@@ -28,7 +28,7 @@ MMSS LDO specific properties:
 	Usage:      required
 	Value type: <string>
 	Definition: should be the following:
-		    "qcom,cpr4-msmfalcon-mmss-ldo-regulator".
+		    "qcom,cpr4-sdm660-mmss-ldo-regulator".
 
 - clocks
 	Usage:      required
@@ -71,7 +71,7 @@ MMSS specific properties:
 	Usage:      required
 	Value type: <u32>
 	Definition: Specifies the number of fuse corners. This value must be 6
-		    for msmfalcon GFX LDO. These fuse corners are: MinSVS,
+		    for sdm660 GFX LDO. These fuse corners are: MinSVS,
 		    LowSVS, SVS, SVSP, NOM and NOMP. The open-loop voltage fuses
 		    are allocated for LowSVS, SVS, NOM and NOMP corners. The
 		    open-loop voltages for MinSVS and SVSP are derived by
@@ -217,7 +217,7 @@ Example
 =======
 
 gfx_cpr: cpr4-ctrl@05061000 {
-	compatible = "qcom,cpr4-msmfalcon-mmss-ldo-regulator";
+	compatible = "qcom,cpr4-sdm660-mmss-ldo-regulator";
 	reg = <0x05061000 0x4000>, <0x00784000 0x1000>;
 	reg-names = "cpr_ctrl", "fuse_base";
 	interrupts = <GIC_SPI 285 IRQ_TYPE_EDGE_RISING>;
@@ -233,7 +233,7 @@ gfx_cpr: cpr4-ctrl@05061000 {
 
 	vdd-supply = <&gfx_stub_vreg>;
 	mem-acc-supply = <&gfx_mem_acc_vreg>;
-	system-supply = <&pm2falcon_s3_level>; /* vdd_cx */
+	system-supply = <&pm660l_s3_level>; /* vdd_cx */
 	qcom,voltage-step = <5000>;
 	vdd-thread0-ldo-supply = <&gfx_ldo_vreg>;
 
diff --git a/Documentation/devicetree/bindings/regulator/msm_gfx_ldo.txt b/Documentation/devicetree/bindings/regulator/msm_gfx_ldo.txt
index 42c735e26d66..dcbb120eea2a 100644
--- a/Documentation/devicetree/bindings/regulator/msm_gfx_ldo.txt
+++ b/Documentation/devicetree/bindings/regulator/msm_gfx_ldo.txt
@@ -9,7 +9,7 @@ This document describes the bindings that apply for the GFX LDO regulator.
 	Usage:      required
 	Value type: <string>
 	Definition: should be "qcom,msm8953-gfx-ldo" for MSM8953 and
-		    "qcom,msmfalcon-gfx-ldo" for MSMFALCON
+		    "qcom,sdm660-gfx-ldo" for SDM660
 
 - reg
 	Usage:      required
diff --git a/Documentation/devicetree/bindings/regulator/qpnp-lcdb-regulator.txt b/Documentation/devicetree/bindings/regulator/qpnp-lcdb-regulator.txt
index 68d23d0f5523..8b3a38da0834 100644
--- a/Documentation/devicetree/bindings/regulator/qpnp-lcdb-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/qpnp-lcdb-regulator.txt
@@ -209,7 +209,7 @@ Properties below are specific to BOOST subnode only.
 Example
 =======
 
-pm2falcon_lcdb: qpnp-lcdb@ec00 {
+pm660l_lcdb: qpnp-lcdb@ec00 {
 	compatible = "qcom,qpnp-lcdb-regulator";
 	#address-cells = <1>;
 	#size-cells = <1>;
diff --git a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt
index 8957ff9dc9ee..f71d1a909d07 100644
--- a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt
+++ b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt
@@ -1610,10 +1610,10 @@ Example:
 		asoc-wsa-codec-prefixes = "SpkrMono";
 	};
 
-* MSMFALCON ASoC Machine driver
+* SDM660 ASoC Machine driver
 
 Required properties:
-- compatible : "qcom,msmfalcon-asoc-snd"
+- compatible : "qcom,sdm660-asoc-snd"
 - qcom,model : The user-visible name of this sound card.
 - qcom,msm-hs-micbias-type : This property is used to recognize the headset
   micbias type, internal or external.
@@ -1666,8 +1666,8 @@ mclk frequency needs to be configured for internal and external PA.
 
 Example:
 	 sound {
-		compatible = "qcom,msmfalcon-asoc-snd";
-		qcom,model = "msmfalcon-snd-card";
+		compatible = "qcom,sdm660-asoc-snd";
+		qcom,model = "sdm660-snd-card";
 		qcom,msm-mclk-freq = <9600000>;
 		qcom,msm-mbhc-hphl-swh = <0>;
 		qcom,msm-mbhc-gnd-swh = <0>;
@@ -2151,11 +2151,11 @@ Example:
 		asoc-codec-names = "msm-stub-codec.1";
 	};
 
-* MSMFALCON ASoC Slimbus Machine driver
+* SDM660 ASoC Slimbus Machine driver
 
 Required properties:
-- compatible : "qcom,msmfalcon-asoc-snd-tasha" for tasha codec,
-		"qcom,msmfalcon-asoc-snd-tavil" for tavil codec.
+- compatible : "qcom,sdm660-asoc-snd-tasha" for tasha codec,
+		"qcom,sdm660-asoc-snd-tavil" for tavil codec.
 - qcom,model : The user-visible name of this sound card.
 - qcom,msm-mclk-freq : MCLK frequency value for external codec
 - qcom,msm-gpios : Lists down all the gpio sets that are supported.
@@ -2195,8 +2195,8 @@ Optional properties:
 Example:
 
 	sound-9335 {
-	compatible = "qcom,msmfalcon-asoc-snd-tasha";
-	qcom,model = "msmfalcon-tasha-snd-card";
+	compatible = "qcom,sdm660-asoc-snd-tasha";
+	qcom,model = "sdm660-tasha-snd-card";
 
 	qcom,audio-routing =
 		"RX_BIAS", "MCLK",
diff --git a/Documentation/devicetree/bindings/thermal/tsens.txt b/Documentation/devicetree/bindings/thermal/tsens.txt
index ada060d19a9b..b4183bace25d 100644
--- a/Documentation/devicetree/bindings/thermal/tsens.txt
+++ b/Documentation/devicetree/bindings/thermal/tsens.txt
@@ -31,7 +31,7 @@ Required properties:
 	       should be "qcom,msmgold-tsens" for gold TSENS driver.
 	       should be "qcom,msm8998-tsens" for 8998 TSENS driver.
 	       should be "qcom,msmhamster-tsens" for hamster TSENS driver.
-	       should be "qcom,msmfalcon-tsens" for falcon TSENS driver.
+	       should be "qcom,sdm660-tsens" for 660 TSENS driver.
 	       should be "qcom,msmtriton-tsens" for triton TSENS driver.
 	       The compatible property is used to identify the respective fusemap to use
 	       for the corresponding SoC.
diff --git a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt
index 66142b4cd880..f836fc7ab439 100644
--- a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt
+++ b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt
@@ -10,7 +10,7 @@ Required properties:
 - compatible        : compatible list, contains "qcom,ufs-phy-qmp-20nm"
 		      or "qcom,ufs-phy-qmp-14nm" or "qcom,ufs-phy-qmp-v3"
 		      or "qcom,ufs-phy-qrbtc-v2" or
-		      "qcom,ufs-phy-qmp-v3-falcon"
+		      "qcom,ufs-phy-qmp-v3-660"
 		      according to the relevant phy in use.
 - reg               : should contain PHY register address space (mandatory),
 - reg-names         : indicates various resources passed to driver (via reg proptery) by name.
diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile
index 9b702a7bf08e..262acc21ccff 100644
--- a/arch/arm/boot/dts/qcom/Makefile
+++ b/arch/arm/boot/dts/qcom/Makefile
@@ -130,36 +130,36 @@ dtb-$(CONFIG_ARCH_MSM8998) += msm8998-sim.dtb \
 	apq8998-v2.1-cdp.dtb \
 	apq8998-v2.1-qrd.dtb \
 	apq8998-v2.1-mediabox.dtb \
-	msm8998-v2.1-interposer-msmfalcon-cdp.dtb \
-	msm8998-v2.1-interposer-msmfalcon-mtp.dtb \
-	msm8998-v2.1-interposer-msmfalcon-qrd.dtb
+	msm8998-v2.1-interposer-sdm660-cdp.dtb \
+	msm8998-v2.1-interposer-sdm660-mtp.dtb \
+	msm8998-v2.1-interposer-sdm660-qrd.dtb
 
 dtb-$(CONFIG_ARCH_MSMHAMSTER) += msmhamster-rumi.dtb
 
-dtb-$(CONFIG_ARCH_MSMFALCON) += msmfalcon-sim.dtb \
-	msmfalcon-internal-codec-cdp.dtb \
-	msmfalcon-internal-codec-mtp.dtb \
-	msmfalcon-internal-codec-rcm.dtb \
-	msmfalcon-cdp.dtb \
-	msmfalcon-mtp.dtb \
-	msmfalcon-qrd.dtb \
-	msmfalcon-rcm.dtb \
-	msmfalcon-rumi.dtb \
-	msmfalcon-pm3falcon-cdp.dtb \
-	msmfalcon-pm3falcon-mtp.dtb \
-	msmfalcon-pm3falcon-qrd.dtb \
-	msmfalcon-pm3falcon-rcm.dtb \
-	msmfalcon-pm3falcon-rumi.dtb \
-	msmfalcon-internal-codec-pm3falcon-cdp.dtb \
-	msmfalcon-internal-codec-pm3falcon-mtp.dtb \
-	msmfalcon-internal-codec-pm3falcon-rcm.dtb \
-	msmfalcon-pm3falcon-sim.dtb \
-	apqfalcon-cdp.dtb \
-	apqfalcon-mtp.dtb \
-	apqfalcon-rcm.dtb \
-	apqfalcon-pm3falcon-cdp.dtb \
-	apqfalcon-pm3falcon-mtp.dtb \
-	apqfalcon-pm3falcon-rcm.dtb
+dtb-$(CONFIG_ARCH_SDM660) += sdm660-sim.dtb \
+	sdm660-internal-codec-cdp.dtb \
+	sdm660-internal-codec-mtp.dtb \
+	sdm660-internal-codec-rcm.dtb \
+	sdm660-cdp.dtb \
+	sdm660-mtp.dtb \
+	sdm660-qrd.dtb \
+	sdm660-rcm.dtb \
+	sdm660-rumi.dtb \
+	sdm660-pm660a-cdp.dtb \
+	sdm660-pm660a-mtp.dtb \
+	sdm660-pm660a-qrd.dtb \
+	sdm660-pm660a-rcm.dtb \
+	sdm660-pm660a-rumi.dtb \
+	sdm660-internal-codec-pm660a-cdp.dtb \
+	sdm660-internal-codec-pm660a-mtp.dtb \
+	sdm660-internal-codec-pm660a-rcm.dtb \
+	sdm660-pm660a-sim.dtb \
+	sda660-cdp.dtb \
+	sda660-mtp.dtb \
+	sda660-rcm.dtb \
+	sda660-pm660a-cdp.dtb \
+	sda660-pm660a-mtp.dtb \
+	sda660-pm660a-rcm.dtb
 
 dtb-$(CONFIG_ARCH_MSMTRITON) += msmtriton-rumi.dtb
 
diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-falcon.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-660.dtsi
index 713e1b1bc66a..874b97a3c965 100644
--- a/arch/arm/boot/dts/qcom/msm-arm-smmu-falcon.dtsi
+++ b/arch/arm/boot/dts/qcom/msm-arm-smmu-660.dtsi
@@ -10,8 +10,8 @@
  * GNU General Public License for more details.
  */
 
-#include <dt-bindings/clock/qcom,gcc-msmfalcon.h>
-#include <dt-bindings/clock/qcom,mmcc-msmfalcon.h>
+#include <dt-bindings/clock/qcom,gcc-sdm660.h>
+#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
 #include <dt-bindings/msm/msm-bus-ids.h>
 #include <dt-bindings/clock/qcom,rpmcc.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-impl-defs-falcon.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-impl-defs-660.dtsi
index f060f2d7008c..f060f2d7008c 100644
--- a/arch/arm/boot/dts/qcom/msm-arm-smmu-impl-defs-falcon.dtsi
+++ b/arch/arm/boot/dts/qcom/msm-arm-smmu-impl-defs-660.dtsi
diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-triton.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-triton.dtsi
index f4bf275dcc3c..4ab200d6b89d 100644
--- a/arch/arm/boot/dts/qcom/msm-arm-smmu-triton.dtsi
+++ b/arch/arm/boot/dts/qcom/msm-arm-smmu-triton.dtsi
@@ -10,8 +10,8 @@
 * GNU General Public License for more details.
 */
 
-#include "msm-arm-smmu-falcon.dtsi"
-#include "msm-arm-smmu-impl-defs-falcon.dtsi"
+#include "msm-arm-smmu-660.dtsi"
+#include "msm-arm-smmu-impl-defs-660.dtsi"
 
 &soc {
 	/delete-node/ arm,smmu-turing_q6@5180000;
diff --git a/arch/arm/boot/dts/qcom/msm-audio.dtsi b/arch/arm/boot/dts/qcom/msm-audio.dtsi
index 7a96e19c62c5..d86e77e2c7ee 100644
--- a/arch/arm/boot/dts/qcom/msm-audio.dtsi
+++ b/arch/arm/boot/dts/qcom/msm-audio.dtsi
@@ -571,8 +571,8 @@
 	};
 
 	tasha_snd: sound-9335 {
-		compatible = "qcom,msmfalcon-asoc-snd-tasha";
-		qcom,model = "msmfalcon-tasha-snd-card";
+		compatible = "qcom,sdm660-asoc-snd-tasha";
+		qcom,model = "sdm660-tasha-snd-card";
 		qcom,wcn-btfm;
 		qcom,mi2s-audio-intf;
 		qcom,auxpcm-audio-intf;
@@ -683,8 +683,8 @@
 	};
 
 	tavil_snd: sound-tavil {
-		compatible = "qcom,msmfalcon-asoc-snd-tavil";
-		qcom,model = "msmfalcon-tavil-snd-card";
+		compatible = "qcom,sdm660-asoc-snd-tavil";
+		qcom,model = "sdm660-tavil-snd-card";
 		qcom,wcn-btfm;
 		qcom,mi2s-audio-intf;
 		qcom,auxpcm-audio-intf;
@@ -792,8 +792,8 @@
 
 	int_codec: sound {
 		status = "disabled";
-		compatible = "qcom,msmfalcon-asoc-snd";
-		qcom,model = "msmfalcon-snd-card";
+		compatible = "qcom,sdm660-asoc-snd";
+		qcom,model = "sdm660-snd-card";
 		qcom,wcn-btfm;
 		qcom,mi2s-audio-intf;
 		qcom,auxpcm-audio-intf;
@@ -913,7 +913,7 @@
 
 	clock_audio: audio_ext_clk {
 		compatible = "qcom,audio-ref-clk";
-		qcom,audio-ref-clk-gpio = <&pmfalcon_gpios 3 0>;
+		qcom,audio-ref-clk-gpio = <&pm660_gpios 3 0>;
 		clock-names = "osr_clk";
 		clocks = <&clock_rpmcc AUDIO_PMI_CLK>;
 		qcom,node_has_rpm_clock;
diff --git a/arch/arm/boot/dts/qcom/msm-gdsc-falcon.dtsi b/arch/arm/boot/dts/qcom/msm-gdsc-660.dtsi
index 6550ddcad86c..6550ddcad86c 100644
--- a/arch/arm/boot/dts/qcom/msm-gdsc-falcon.dtsi
+++ b/arch/arm/boot/dts/qcom/msm-gdsc-660.dtsi
diff --git a/arch/arm/boot/dts/qcom/msm-pmfalcon-rpm-regulator.dtsi b/arch/arm/boot/dts/qcom/msm-pm660-rpm-regulator.dtsi
index 0b625bf04ef5..0f87d1390d5c 100644
--- a/arch/arm/boot/dts/qcom/msm-pmfalcon-rpm-regulator.dtsi
+++ b/arch/arm/boot/dts/qcom/msm-pm660-rpm-regulator.dtsi
@@ -20,7 +20,7 @@
 
 		regulator-s4 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pmfalcon_s4";
+			regulator-name = "pm660_s4";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -35,7 +35,7 @@
 
 		regulator-s5 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pmfalcon_s5";
+			regulator-name = "pm660_s5";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -50,7 +50,7 @@
 
 		regulator-s6 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pmfalcon_s6";
+			regulator-name = "pm660_s6";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -65,7 +65,7 @@
 
 		regulator-l1 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pmfalcon_l1";
+			regulator-name = "pm660_l1";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -80,7 +80,7 @@
 
 		regulator-l2 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pmfalcon_l2";
+			regulator-name = "pm660_l2";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -95,7 +95,7 @@
 
 		regulator-l3 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pmfalcon_l3";
+			regulator-name = "pm660_l3";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -110,7 +110,7 @@
 
 		regulator-l5 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pmfalcon_l5";
+			regulator-name = "pm660_l5";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -125,7 +125,7 @@
 
 		regulator-l6 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pmfalcon_l6";
+			regulator-name = "pm660_l6";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -140,7 +140,7 @@
 
 		regulator-l7 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pmfalcon_l7";
+			regulator-name = "pm660_l7";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -155,7 +155,7 @@
 
 		regulator-l8 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pmfalcon_l8";
+			regulator-name = "pm660_l8";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -170,7 +170,7 @@
 
 		regulator-l9 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pmfalcon_l9";
+			regulator-name = "pm660_l9";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -185,7 +185,7 @@
 
 		regulator-l10 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pmfalcon_l10";
+			regulator-name = "pm660_l10";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -200,7 +200,7 @@
 
 		regulator-l11 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pmfalcon_l11";
+			regulator-name = "pm660_l11";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -215,7 +215,7 @@
 
 		regulator-l12 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pmfalcon_l12";
+			regulator-name = "pm660_l12";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -230,7 +230,7 @@
 
 		regulator-l13 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pmfalcon_l13";
+			regulator-name = "pm660_l13";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -245,7 +245,7 @@
 
 		regulator-l14 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pmfalcon_l14";
+			regulator-name = "pm660_l14";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -260,7 +260,7 @@
 
 		regulator-l15 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pmfalcon_l15";
+			regulator-name = "pm660_l15";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -275,7 +275,7 @@
 
 		regulator-l17 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pmfalcon_l17";
+			regulator-name = "pm660_l17";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -290,7 +290,7 @@
 
 		regulator-l19 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pmfalcon_l19";
+			regulator-name = "pm660_l19";
 			qcom,set = <3>;
 			status = "disabled";
 		};
diff --git a/arch/arm/boot/dts/qcom/msm-pmfalcon.dtsi b/arch/arm/boot/dts/qcom/msm-pm660.dtsi
index 0168cb2cddb3..3674e2e5570b 100644
--- a/arch/arm/boot/dts/qcom/msm-pmfalcon.dtsi
+++ b/arch/arm/boot/dts/qcom/msm-pm660.dtsi
@@ -14,13 +14,13 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 
 &spmi_bus {
-	qcom,pmfalcon@0 {
+	qcom,pm660@0 {
 		compatible ="qcom,spmi-pmic";
 		reg = <0x0 SPMI_USID>;
 		#address-cells = <2>;
 		#size-cells = <0>;
 
-		pmfalcon_revid: qcom,revid@100 {
+		pm660_revid: qcom,revid@100 {
 			compatible = "qcom,qpnp-revid";
 			reg = <0x100 0x100>;
 		};
@@ -55,18 +55,18 @@
 			compatible = "qcom,qpnp-temp-alarm";
 			reg = <0x2400 0x100>;
 			interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
-			label = "pmfalcon_tz";
+			label = "pm660_tz";
 			qcom,channel-num = <6>;
-			qcom,temp_alarm-vadc = <&pmfalcon_vadc>;
+			qcom,temp_alarm-vadc = <&pm660_vadc>;
 		};
 
-		pmfalcon_gpios: gpios {
+		pm660_gpios: gpios {
 			compatible = "qcom,qpnp-pin";
 			gpio-controller;
 			#gpio-cells = <2>;
 			#address-cells = <1>;
 			#size-cells = <1>;
-			label = "pmfalcon-gpio";
+			label = "pm660-gpio";
 
 			gpio@c000 {
 				reg = <0xc000 0x100>;
@@ -147,28 +147,28 @@
 			};
 		};
 
-		pmfalcon_coincell: qcom,coincell@2800 {
+		pm660_coincell: qcom,coincell@2800 {
 			compatible = "qcom,qpnp-coincell";
 			reg = <0x2800 0x100>;
 		};
 
-		pmfalcon_rtc: qcom,pmfalcon_rtc {
+		pm660_rtc: qcom,pm660_rtc {
 			compatible = "qcom,qpnp-rtc";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			qcom,qpnp-rtc-write = <0>;
 			qcom,qpnp-rtc-alarm-pwrup = <0>;
 
-			qcom,pmfalcon_rtc_rw@6000 {
+			qcom,pm660_rtc_rw@6000 {
 				reg = <0x6000 0x100>;
 			};
-			qcom,pmfalcon_rtc_alarm@6100 {
+			qcom,pm660_rtc_alarm@6100 {
 				reg = <0x6100 0x100>;
 				interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
 			};
 		};
 
-		pmfalcon_vadc: vadc@3100 {
+		pm660_vadc: vadc@3100 {
 			compatible = "qcom,qpnp-vadc-hc";
 			reg = <0x3100 0x100>;
 			#address-cells = <1>;
@@ -282,17 +282,17 @@
 			};
 		};
 
-		pmfalcon_charger: qcom,qpnp-smb2 {
+		pm660_charger: qcom,qpnp-smb2 {
 			compatible = "qcom,qpnp-smb2";
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			qcom,pmic-revid = <&pmfalcon_revid>;
+			qcom,pmic-revid = <&pm660_revid>;
 
-			io-channels = <&pmfalcon_rradc 8>,
-				      <&pmfalcon_rradc 10>,
-				      <&pmfalcon_rradc 3>,
-				      <&pmfalcon_rradc 4>;
+			io-channels = <&pm660_rradc 8>,
+				      <&pm660_rradc 10>,
+				      <&pm660_rradc 3>,
+				      <&pm660_rradc 4>;
 			io-channel-names = "charger_temp",
 					   "charger_temp_max",
 					   "usbin_i",
@@ -411,10 +411,10 @@
 			};
 		};
 
-		pmfalcon_pdphy: qcom,usb-pdphy@1700 {
+		pm660_pdphy: qcom,usb-pdphy@1700 {
 			compatible = "qcom,qpnp-pdphy";
 			reg = <0x1700 0x100>;
-			vdd-pdphy-supply = <&pm2falcon_l7>;
+			vdd-pdphy-supply = <&pm660l_l7>;
 			vbus-supply = <&smb2_vbus>;
 			vconn-supply = <&smb2_vconn>;
 			interrupts = <0x0 0x17 0x0 IRQ_TYPE_EDGE_RISING>,
@@ -434,7 +434,7 @@
 					  "msg-rx-discarded";
 		};
 
-		pmfalcon_adc_tm: vadc@3400 {
+		pm660_adc_tm: vadc@3400 {
 			compatible = "qcom,qpnp-adc-tm-hc";
 			reg = <0x3400 0x100>;
 			#address-cells = <1>;
@@ -443,7 +443,7 @@
 			interrupt-names = "eoc-int-en-set";
 			qcom,adc-bit-resolution = <15>;
 			qcom,adc-vdd-reference = <1875>;
-			qcom,adc_tm-vadc = <&pmfalcon_vadc>;
+			qcom,adc_tm-vadc = <&pm660_vadc>;
 			qcom,decimation = <0>;
 			qcom,fast-avg-setup = <0>;
 
@@ -491,7 +491,7 @@
 			};
 		};
 
-		pmfalcon_rradc: rradc@4500 {
+		pm660_rradc: rradc@4500 {
 			compatible = "qcom,rradc";
 			reg = <0x4500 0x100>;
 			#address-cells = <1>;
@@ -499,12 +499,12 @@
 			#io-channel-cells = <1>;
 		};
 
-		pmfalcon_fg: qpnp,fg {
+		pm660_fg: qpnp,fg {
 			compatible = "qcom,fg-gen3";
 			#address-cells = <1>;
 			#size-cells = <1>;
-			qcom,pmic-revid = <&pmfalcon_revid>;
-			io-channels = <&pmfalcon_rradc 0>;
+			qcom,pmic-revid = <&pm660_revid>;
+			io-channels = <&pm660_rradc 0>;
 			io-channel-names = "rradc_batt_id";
 			qcom,rradc-base = <0x4500>;
 			qcom,fg-esr-timer-awake = <96>;
@@ -576,13 +576,13 @@
 		};
 	};
 
-	qcom,pmfalcon@1 {
+	qcom,pm660@1 {
 		compatible ="qcom,spmi-pmic";
 		reg = <0x1 SPMI_USID>;
 		#address-cells = <2>;
 		#size-cells = <0>;
 
-		pmfalcon_haptics: qcom,haptic@c000 {
+		pm660_haptics: qcom,haptic@c000 {
 			compatible = "qcom,qpnp-haptic";
 			reg = <0xc000 0x100>;
 			interrupts = <0x1 0xc0 0x0>,
diff --git a/arch/arm/boot/dts/qcom/msm-pm3falcon.dtsi b/arch/arm/boot/dts/qcom/msm-pm660a.dtsi
index f9a33fdc3e85..c43aa5425aae 100644
--- a/arch/arm/boot/dts/qcom/msm-pm3falcon.dtsi
+++ b/arch/arm/boot/dts/qcom/msm-pm660a.dtsi
@@ -11,11 +11,11 @@
  */
 
 /* Disable WLED */
-&pm2falcon_wled {
+&pm660l_wled {
 	status = "disabled";
 };
 
 /* disable LCDB */
-&pm2falcon_lcdb {
+&pm660l_lcdb {
 	status = "disabled";
 };
diff --git a/arch/arm/boot/dts/qcom/msm-pm2falcon-rpm-regulator.dtsi b/arch/arm/boot/dts/qcom/msm-pm660l-rpm-regulator.dtsi
index bc0793fec990..b10f8e559090 100644
--- a/arch/arm/boot/dts/qcom/msm-pm2falcon-rpm-regulator.dtsi
+++ b/arch/arm/boot/dts/qcom/msm-pm660l-rpm-regulator.dtsi
@@ -20,7 +20,7 @@
 
 		regulator-s1 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_s1";
+			regulator-name = "pm660l_s1";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -35,7 +35,7 @@
 
 		regulator-s2 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_s2";
+			regulator-name = "pm660l_s2";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -50,7 +50,7 @@
 
 		regulator-s3 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_s3";
+			regulator-name = "pm660l_s3";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -65,7 +65,7 @@
 
 		regulator-s5 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_s5";
+			regulator-name = "pm660l_s5";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -80,7 +80,7 @@
 
 		regulator-l1 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_l1";
+			regulator-name = "pm660l_l1";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -95,7 +95,7 @@
 
 		regulator-l2 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_l2";
+			regulator-name = "pm660l_l2";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -110,7 +110,7 @@
 
 		regulator-l3 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_l3";
+			regulator-name = "pm660l_l3";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -125,7 +125,7 @@
 
 		regulator-l4 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_l4";
+			regulator-name = "pm660l_l4";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -140,7 +140,7 @@
 
 		regulator-l5 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_l5";
+			regulator-name = "pm660l_l5";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -155,7 +155,7 @@
 
 		regulator-l6 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_l6";
+			regulator-name = "pm660l_l6";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -170,7 +170,7 @@
 
 		regulator-l7 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_l7";
+			regulator-name = "pm660l_l7";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -185,7 +185,7 @@
 
 		regulator-l8 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_l8";
+			regulator-name = "pm660l_l8";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -200,7 +200,7 @@
 
 		regulator-l9 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_l9";
+			regulator-name = "pm660l_l9";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -215,7 +215,7 @@
 
 		regulator-l10 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_l10";
+			regulator-name = "pm660l_l10";
 			qcom,set = <3>;
 			status = "disabled";
 		};
@@ -230,7 +230,7 @@
 
 		regulator-bob {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_bob";
+			regulator-name = "pm660l_bob";
 			qcom,set = <3>;
 			status = "disabled";
 		};
diff --git a/arch/arm/boot/dts/qcom/msm-pm2falcon.dtsi b/arch/arm/boot/dts/qcom/msm-pm660l.dtsi
index d3a920fff82e..a9820cfbc02c 100644
--- a/arch/arm/boot/dts/qcom/msm-pm2falcon.dtsi
+++ b/arch/arm/boot/dts/qcom/msm-pm660l.dtsi
@@ -15,13 +15,13 @@
 #include <dt-bindings/msm/power-on.h>
 
 &spmi_bus {
-	qcom,pm2falcon@2 {
+	qcom,pm660l@2 {
 		compatible = "qcom,spmi-pmic";
 		reg = <0x2 SPMI_USID>;
 		#address-cells = <2>;
 		#size-cells = <0>;
 
-		pm2falcon_revid: qcom,revid@100 {
+		pm660l_revid: qcom,revid@100 {
 			compatible = "qcom,qpnp-revid";
 			reg = <0x100 0x100>;
 		};
@@ -38,16 +38,16 @@
 			compatible = "qcom,qpnp-temp-alarm";
 			reg = <0x2400 0x100>;
 			interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
-			label = "pm2falcon_tz";
+			label = "pm660l_tz";
 		};
 
-		pm2falcon_gpios: gpios {
+		pm660l_gpios: gpios {
 			compatible = "qcom,qpnp-pin";
 			gpio-controller;
 			#gpio-cells = <2>;
 			#address-cells = <1>;
 			#size-cells = <1>;
-			label = "pm2falcon-gpio";
+			label = "pm660l-gpio";
 
 			gpio@c000 {
 				reg = <0xc000 0x100>;
@@ -124,13 +124,13 @@
 		};
 	};
 
-	pm2falcon_3: qcom,pm2falcon@3 {
+	pm660l_3: qcom,pm660l@3 {
 		compatible ="qcom,spmi-pmic";
 		reg = <0x3 SPMI_USID>;
 		#address-cells = <2>;
 		#size-cells = <0>;
 
-		pm2falcon_pwm_1: pwm@b100 {
+		pm660l_pwm_1: pwm@b100 {
 			compatible = "qcom,qpnp-pwm";
 			reg = <0xb100 0x100>,
 			      <0xb042 0x7e>;
@@ -143,7 +143,7 @@
 			#pwm-cells = <2>;
 		};
 
-		pm2falcon_pwm_2: pwm@b200 {
+		pm660l_pwm_2: pwm@b200 {
 			compatible = "qcom,qpnp-pwm";
 			reg = <0xb200 0x100>,
 			      <0xb042 0x7e>;
@@ -156,7 +156,7 @@
 			#pwm-cells = <2>;
 		};
 
-		pm2falcon_pwm_3: pwm@b300 {
+		pm660l_pwm_3: pwm@b300 {
 			compatible = "qcom,qpnp-pwm";
 			reg = <0xb300 0x100>,
 			      <0xb042 0x7e>;
@@ -169,7 +169,7 @@
 			#pwm-cells = <2>;
 		};
 
-		pm2falcon_pwm_4: pwm@b400 {
+		pm660l_pwm_4: pwm@b400 {
 			compatible = "qcom,qpnp-pwm";
 			reg = <0xb400 0x100>,
 			      <0xb042 0x7e>;
@@ -192,7 +192,7 @@
 				label = "rgb";
 				qcom,id = <3>;
 				qcom,mode = "pwm";
-				pwms = <&pm2falcon_pwm_3 0 0>;
+				pwms = <&pm660l_pwm_3 0 0>;
 				qcom,pwm-us = <1000>;
 				qcom,max-current = <12>;
 				qcom,default-state = "off";
@@ -205,7 +205,7 @@
 				label = "rgb";
 				qcom,id = <4>;
 				qcom,mode = "pwm";
-				pwms = <&pm2falcon_pwm_2 0 0>;
+				pwms = <&pm660l_pwm_2 0 0>;
 				qcom,pwm-us = <1000>;
 				qcom,max-current = <12>;
 				qcom,default-state = "off";
@@ -217,7 +217,7 @@
 				label = "rgb";
 				qcom,id = <5>;
 				qcom,mode = "pwm";
-				pwms = <&pm2falcon_pwm_1 0 0>;
+				pwms = <&pm660l_pwm_1 0 0>;
 				qcom,pwm-us = <1000>;
 				qcom,max-current = <12>;
 				qcom,default-state = "off";
@@ -226,7 +226,7 @@
 			};
 		};
 
-		pm2falcon_wled: qcom,leds@d800 {
+		pm660l_wled: qcom,leds@d800 {
 			compatible = "qcom,qpnp-wled";
 			reg = <0xd800 0x100>,
 				<0xd900 0x100>;
@@ -252,7 +252,7 @@
 			qcom,led-strings-list = [00 01 02];
 			qcom,en-ext-pfet-sc-pro;
 			qcom,loop-auto-gm-en;
-			qcom,pmic-revid = <&pm2falcon_revid>;
+			qcom,pmic-revid = <&pm660l_revid>;
 			status = "ok";
 		};
 
@@ -273,9 +273,9 @@
 			qcom,thermal-derate-en;
 			qcom,thermal-derate-current = <200 500 1000>;
 			qcom,isc-delay = <192>;
-			qcom,pmic-revid = <&pm2falcon_revid>;
+			qcom,pmic-revid = <&pm660l_revid>;
 
-			pm2falcon_flash0: qcom,flash_0 {
+			pm660l_flash0: qcom,flash_0 {
 				label = "flash";
 				qcom,led-name = "led:flash_0";
 				qcom,max-current = <1500>;
@@ -288,7 +288,7 @@
 				qcom,hdrm-vol-hi-lo-win-mv = <100>;
 			};
 
-			pm2falcon_flash1: qcom,flash_1 {
+			pm660l_flash1: qcom,flash_1 {
 				label = "flash";
 				qcom,led-name = "led:flash_1";
 				qcom,max-current = <1500>;
@@ -301,7 +301,7 @@
 				qcom,hdrm-vol-hi-lo-win-mv = <100>;
 			};
 
-			pm2falcon_flash2: qcom,flash_2 {
+			pm660l_flash2: qcom,flash_2 {
 				label = "flash";
 				qcom,led-name = "led:flash_2";
 				qcom,max-current = <750>;
@@ -317,7 +317,7 @@
 				pinctrl-1 = <&led_disable>;
 			};
 
-			pm2falcon_torch0: qcom,torch_0 {
+			pm660l_torch0: qcom,torch_0 {
 				label = "torch";
 				qcom,led-name = "led:torch_0";
 				qcom,max-current = <500>;
@@ -329,7 +329,7 @@
 				qcom,hdrm-vol-hi-lo-win-mv = <100>;
 			};
 
-			pm2falcon_torch1: qcom,torch_1 {
+			pm660l_torch1: qcom,torch_1 {
 				label = "torch";
 				qcom,led-name = "led:torch_1";
 				qcom,max-current = <500>;
@@ -341,7 +341,7 @@
 				qcom,hdrm-vol-hi-lo-win-mv = <100>;
 			};
 
-			pm2falcon_torch2: qcom,torch_2 {
+			pm660l_torch2: qcom,torch_2 {
 				label = "torch";
 				qcom,led-name = "led:torch_2";
 				qcom,max-current = <500>;
@@ -356,14 +356,14 @@
 				pinctrl-1 = <&led_disable>;
 			};
 
-			pm2falcon_switch0: qcom,led_switch_0 {
+			pm660l_switch0: qcom,led_switch_0 {
 				label = "switch";
 				qcom,led-name = "led:switch_0";
 				qcom,led-mask = <3>;
 				qcom,default-led-trigger = "switch0_trigger";
 			};
 
-			pm2falcon_switch1: qcom,led_switch_1 {
+			pm660l_switch1: qcom,led_switch_1 {
 				label = "switch";
 				qcom,led-name = "led:switch_1";
 				qcom,led-mask = <4>;
@@ -371,7 +371,7 @@
 			};
 		};
 
-		pm2falcon_lcdb: qpnp-lcdb@ec00 {
+		pm660l_lcdb: qpnp-lcdb@ec00 {
 			compatible = "qcom,qpnp-lcdb-regulator";
 			#address-cells = <1>;
 			#size-cells = <1>;
diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-cdp.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-cdp.dtsi
index 78ba56b3e3c2..52d0fdb4a523 100644
--- a/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-cdp.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-cdp.dtsi
@@ -45,18 +45,18 @@
 	led_flash0: qcom,camera-flash@0 {
 		cell-index = <0>;
 		compatible = "qcom,camera-flash";
-		qcom,flash-source = <&pm2falcon_flash0 &pm2falcon_flash1>;
-		qcom,torch-source = <&pm2falcon_torch0 &pm2falcon_torch1>;
-		qcom,switch-source = <&pm2falcon_switch0>;
+		qcom,flash-source = <&pm660l_flash0 &pm660l_flash1>;
+		qcom,torch-source = <&pm660l_torch0 &pm660l_torch1>;
+		qcom,switch-source = <&pm660l_switch0>;
 		status = "ok";
 	};
 
 	led_flash1: qcom,camera-flash@1 {
 		cell-index = <1>;
 		compatible = "qcom,camera-flash";
-		qcom,flash-source = <&pm2falcon_flash2>;
-		qcom,torch-source = <&pm2falcon_torch2>;
-		qcom,switch-source = <&pm2falcon_switch1>;
+		qcom,flash-source = <&pm660l_flash2>;
+		qcom,torch-source = <&pm660l_torch2>;
+		qcom,switch-source = <&pm660l_switch1>;
 		status = "ok";
 	};
 
@@ -77,9 +77,9 @@
 
 	qcom,csid@ca30000  {
 		qcom,csi-vdd-voltage = <1200000>;
-		qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>;
+		qcom,mipi-csi-vdd-supply = <&pm660_l1>;
 		gdscr-supply = <&gdsc_camss_top>;
-		vdd_sec-supply = <&pm2falcon_l1>;
+		vdd_sec-supply = <&pm660l_l1>;
 		bimc_smmu-supply = <&gdsc_bimc_smmu>;
 		qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu";
 		qcom,cam-vreg-min-voltage = <925000 0 0>;
@@ -91,9 +91,9 @@
 
 	qcom,csid@ca30400 {
 		qcom,csi-vdd-voltage = <1200000>;
-		qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>;
+		qcom,mipi-csi-vdd-supply = <&pm660_l1>;
 		gdscr-supply = <&gdsc_camss_top>;
-		vdd_sec-supply = <&pm2falcon_l1>;
+		vdd_sec-supply = <&pm660l_l1>;
 		bimc_smmu-supply = <&gdsc_bimc_smmu>;
 		qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu";
 		qcom,cam-vreg-min-voltage = <925000 0 0>;
@@ -105,9 +105,9 @@
 
 	qcom,csid@ca30800 {
 		qcom,csi-vdd-voltage = <1200000>;
-		qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>;
+		qcom,mipi-csi-vdd-supply = <&pm660_l1>;
 		gdscr-supply = <&gdsc_camss_top>;
-		vdd_sec-supply = <&pm2falcon_l1>;
+		vdd_sec-supply = <&pm660l_l1>;
 		bimc_smmu-supply = <&gdsc_bimc_smmu>;
 		qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu";
 		qcom,cam-vreg-min-voltage = <925000 0 0>;
@@ -119,9 +119,9 @@
 
 	qcom,csid@ca30c00 {
 		qcom,csi-vdd-voltage = <1200000>;
-		qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>;
+		qcom,mipi-csi-vdd-supply = <&pm660_l1>;
 		gdscr-supply = <&gdsc_camss_top>;
-		vdd_sec-supply = <&pm2falcon_l1>;
+		vdd_sec-supply = <&pm660l_l1>;
 		bimc_smmu-supply = <&gdsc_bimc_smmu>;
 		qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu";
 		qcom,cam-vreg-min-voltage = <925000 0 0>;
@@ -195,9 +195,9 @@
 		cell-index = <0>;
 		reg = <0>;
 		compatible = "qcom,eeprom";
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
@@ -212,7 +212,7 @@
 				&cam_actuator_vaf_suspend>;
 		gpios = <&tlmm 13 0>,
 			<&tlmm 30 0>,
-			<&pm2falcon_gpios 4 0>,
+			<&pm660l_gpios 4 0>,
 			<&tlmm 8 0>,
 			<&tlmm 27 0>;
 		qcom,gpio-reset = <1>;
@@ -240,9 +240,9 @@
 		cell-index = <2>;
 		reg = <0x2>;
 		compatible = "qcom,eeprom";
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
@@ -257,7 +257,7 @@
 				&cam_actuator_vaf_suspend>;
 		gpios = <&tlmm 14 0>,
 			<&tlmm 28 0>,
-			<&pmfalcon_gpios 3 0>,
+			<&pm660_gpios 3 0>,
 			<&tlmm 29 0>,
 			<&tlmm 27 0>;
 		qcom,gpio-reset = <1>;
@@ -292,9 +292,9 @@
 		qcom,actuator-src = <&actuator0>;
 		qcom,ois-src = <&ois0>;
 		qcom,eeprom-src = <&eeprom0>;
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
@@ -307,7 +307,7 @@
 				 &cam_sensor_rear_suspend>;
 		gpios = <&tlmm 13 0>,
 			<&tlmm 30 0>,
-			<&pm2falcon_gpios 4 0>,
+			<&pm660l_gpios 4 0>,
 			<&tlmm 8 0>;
 		qcom,gpio-reset = <1>;
 		qcom,gpio-vdig = <2>;
@@ -335,9 +335,9 @@
 		qcom,csiphy-sd-index = <1>;
 		qcom,csid-sd-index = <2>;
 		qcom,mount-angle = <90>;
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
@@ -350,7 +350,7 @@
 				 &cam_sensor_rear2_suspend>;
 		gpios = <&tlmm 15 0>,
 			<&tlmm 9 0>,
-			<&pm2falcon_gpios 3 0>,
+			<&pm660l_gpios 3 0>,
 			<&tlmm 8 0>;
 		qcom,gpio-reset = <1>;
 		qcom,gpio-vdig = <2>;
@@ -381,9 +381,9 @@
 		qcom,actuator-src = <&actuator1>;
 		qcom,led-flash-src = <&led_flash1>;
 		qcom,eeprom-src = <&eeprom2>;
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
@@ -396,7 +396,7 @@
 				 &cam_sensor_front_suspend>;
 		gpios = <&tlmm 14 0>,
 			<&tlmm 28 0>,
-			<&pm2falcon_gpios 3 0>,
+			<&pm660l_gpios 3 0>,
 			<&tlmm 8 0>;
 		qcom,gpio-reset = <1>;
 		qcom,gpio-vdig = <2>;
@@ -418,7 +418,7 @@
 	};
 };
 
-&pm2falcon_gpios {
+&pm660l_gpios {
 	gpio@c300 { /* GPIO4 -CAMERA SENSOR 0 VDIG*/
 		qcom,mode = <1>;                /* Output */
 		qcom,pull = <5>;                /* No Pull */
diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-mtp.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-mtp.dtsi
index 78ba56b3e3c2..52d0fdb4a523 100644
--- a/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-mtp.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-mtp.dtsi
@@ -45,18 +45,18 @@
 	led_flash0: qcom,camera-flash@0 {
 		cell-index = <0>;
 		compatible = "qcom,camera-flash";
-		qcom,flash-source = <&pm2falcon_flash0 &pm2falcon_flash1>;
-		qcom,torch-source = <&pm2falcon_torch0 &pm2falcon_torch1>;
-		qcom,switch-source = <&pm2falcon_switch0>;
+		qcom,flash-source = <&pm660l_flash0 &pm660l_flash1>;
+		qcom,torch-source = <&pm660l_torch0 &pm660l_torch1>;
+		qcom,switch-source = <&pm660l_switch0>;
 		status = "ok";
 	};
 
 	led_flash1: qcom,camera-flash@1 {
 		cell-index = <1>;
 		compatible = "qcom,camera-flash";
-		qcom,flash-source = <&pm2falcon_flash2>;
-		qcom,torch-source = <&pm2falcon_torch2>;
-		qcom,switch-source = <&pm2falcon_switch1>;
+		qcom,flash-source = <&pm660l_flash2>;
+		qcom,torch-source = <&pm660l_torch2>;
+		qcom,switch-source = <&pm660l_switch1>;
 		status = "ok";
 	};
 
@@ -77,9 +77,9 @@
 
 	qcom,csid@ca30000  {
 		qcom,csi-vdd-voltage = <1200000>;
-		qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>;
+		qcom,mipi-csi-vdd-supply = <&pm660_l1>;
 		gdscr-supply = <&gdsc_camss_top>;
-		vdd_sec-supply = <&pm2falcon_l1>;
+		vdd_sec-supply = <&pm660l_l1>;
 		bimc_smmu-supply = <&gdsc_bimc_smmu>;
 		qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu";
 		qcom,cam-vreg-min-voltage = <925000 0 0>;
@@ -91,9 +91,9 @@
 
 	qcom,csid@ca30400 {
 		qcom,csi-vdd-voltage = <1200000>;
-		qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>;
+		qcom,mipi-csi-vdd-supply = <&pm660_l1>;
 		gdscr-supply = <&gdsc_camss_top>;
-		vdd_sec-supply = <&pm2falcon_l1>;
+		vdd_sec-supply = <&pm660l_l1>;
 		bimc_smmu-supply = <&gdsc_bimc_smmu>;
 		qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu";
 		qcom,cam-vreg-min-voltage = <925000 0 0>;
@@ -105,9 +105,9 @@
 
 	qcom,csid@ca30800 {
 		qcom,csi-vdd-voltage = <1200000>;
-		qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>;
+		qcom,mipi-csi-vdd-supply = <&pm660_l1>;
 		gdscr-supply = <&gdsc_camss_top>;
-		vdd_sec-supply = <&pm2falcon_l1>;
+		vdd_sec-supply = <&pm660l_l1>;
 		bimc_smmu-supply = <&gdsc_bimc_smmu>;
 		qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu";
 		qcom,cam-vreg-min-voltage = <925000 0 0>;
@@ -119,9 +119,9 @@
 
 	qcom,csid@ca30c00 {
 		qcom,csi-vdd-voltage = <1200000>;
-		qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>;
+		qcom,mipi-csi-vdd-supply = <&pm660_l1>;
 		gdscr-supply = <&gdsc_camss_top>;
-		vdd_sec-supply = <&pm2falcon_l1>;
+		vdd_sec-supply = <&pm660l_l1>;
 		bimc_smmu-supply = <&gdsc_bimc_smmu>;
 		qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu";
 		qcom,cam-vreg-min-voltage = <925000 0 0>;
@@ -195,9 +195,9 @@
 		cell-index = <0>;
 		reg = <0>;
 		compatible = "qcom,eeprom";
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
@@ -212,7 +212,7 @@
 				&cam_actuator_vaf_suspend>;
 		gpios = <&tlmm 13 0>,
 			<&tlmm 30 0>,
-			<&pm2falcon_gpios 4 0>,
+			<&pm660l_gpios 4 0>,
 			<&tlmm 8 0>,
 			<&tlmm 27 0>;
 		qcom,gpio-reset = <1>;
@@ -240,9 +240,9 @@
 		cell-index = <2>;
 		reg = <0x2>;
 		compatible = "qcom,eeprom";
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
@@ -257,7 +257,7 @@
 				&cam_actuator_vaf_suspend>;
 		gpios = <&tlmm 14 0>,
 			<&tlmm 28 0>,
-			<&pmfalcon_gpios 3 0>,
+			<&pm660_gpios 3 0>,
 			<&tlmm 29 0>,
 			<&tlmm 27 0>;
 		qcom,gpio-reset = <1>;
@@ -292,9 +292,9 @@
 		qcom,actuator-src = <&actuator0>;
 		qcom,ois-src = <&ois0>;
 		qcom,eeprom-src = <&eeprom0>;
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
@@ -307,7 +307,7 @@
 				 &cam_sensor_rear_suspend>;
 		gpios = <&tlmm 13 0>,
 			<&tlmm 30 0>,
-			<&pm2falcon_gpios 4 0>,
+			<&pm660l_gpios 4 0>,
 			<&tlmm 8 0>;
 		qcom,gpio-reset = <1>;
 		qcom,gpio-vdig = <2>;
@@ -335,9 +335,9 @@
 		qcom,csiphy-sd-index = <1>;
 		qcom,csid-sd-index = <2>;
 		qcom,mount-angle = <90>;
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
@@ -350,7 +350,7 @@
 				 &cam_sensor_rear2_suspend>;
 		gpios = <&tlmm 15 0>,
 			<&tlmm 9 0>,
-			<&pm2falcon_gpios 3 0>,
+			<&pm660l_gpios 3 0>,
 			<&tlmm 8 0>;
 		qcom,gpio-reset = <1>;
 		qcom,gpio-vdig = <2>;
@@ -381,9 +381,9 @@
 		qcom,actuator-src = <&actuator1>;
 		qcom,led-flash-src = <&led_flash1>;
 		qcom,eeprom-src = <&eeprom2>;
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
@@ -396,7 +396,7 @@
 				 &cam_sensor_front_suspend>;
 		gpios = <&tlmm 14 0>,
 			<&tlmm 28 0>,
-			<&pm2falcon_gpios 3 0>,
+			<&pm660l_gpios 3 0>,
 			<&tlmm 8 0>;
 		qcom,gpio-reset = <1>;
 		qcom,gpio-vdig = <2>;
@@ -418,7 +418,7 @@
 	};
 };
 
-&pm2falcon_gpios {
+&pm660l_gpios {
 	gpio@c300 { /* GPIO4 -CAMERA SENSOR 0 VDIG*/
 		qcom,mode = <1>;                /* Output */
 		qcom,pull = <5>;                /* No Pull */
diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-qrd.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-qrd.dtsi
index d10c2a25b301..87b1146bd361 100644
--- a/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-qrd.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-qrd.dtsi
@@ -115,9 +115,9 @@
 
 	qcom,csid@ca30000  {
 		qcom,csi-vdd-voltage = <1200000>;
-		qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>;
+		qcom,mipi-csi-vdd-supply = <&pm660_l1>;
 		gdscr-supply = <&gdsc_camss_top>;
-		vdd_sec-supply = <&pm2falcon_l1>;
+		vdd_sec-supply = <&pm660l_l1>;
 		bimc_smmu-supply = <&gdsc_bimc_smmu>;
 		qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu";
 		qcom,cam-vreg-min-voltage = <925000 0 0>;
@@ -129,9 +129,9 @@
 
 	qcom,csid@ca30400 {
 		qcom,csi-vdd-voltage = <1200000>;
-		qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>;
+		qcom,mipi-csi-vdd-supply = <&pm660_l1>;
 		gdscr-supply = <&gdsc_camss_top>;
-		vdd_sec-supply = <&pm2falcon_l1>;
+		vdd_sec-supply = <&pm660l_l1>;
 		bimc_smmu-supply = <&gdsc_bimc_smmu>;
 		qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu";
 		qcom,cam-vreg-min-voltage = <925000 0 0>;
@@ -143,9 +143,9 @@
 
 	qcom,csid@ca30800 {
 		qcom,csi-vdd-voltage = <1200000>;
-		qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>;
+		qcom,mipi-csi-vdd-supply = <&pm660_l1>;
 		gdscr-supply = <&gdsc_camss_top>;
-		vdd_sec-supply = <&pm2falcon_l1>;
+		vdd_sec-supply = <&pm660l_l1>;
 		bimc_smmu-supply = <&gdsc_bimc_smmu>;
 		qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu";
 		qcom,cam-vreg-min-voltage = <925000 0 0>;
@@ -157,9 +157,9 @@
 
 	qcom,csid@ca30c00 {
 		qcom,csi-vdd-voltage = <1200000>;
-		qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>;
+		qcom,mipi-csi-vdd-supply = <&pm660_l1>;
 		gdscr-supply = <&gdsc_camss_top>;
-		vdd_sec-supply = <&pm2falcon_l1>;
+		vdd_sec-supply = <&pm660l_l1>;
 		bimc_smmu-supply = <&gdsc_bimc_smmu>;
 		qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu";
 		qcom,cam-vreg-min-voltage = <925000 0 0>;
@@ -233,9 +233,9 @@
 		cell-index = <0>;
 		reg = <0>;
 		compatible = "qcom,eeprom";
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1750000 3300000 1352000>;
 		qcom,cam-vreg-max-voltage = <1980000 3600000 1352000>;
@@ -248,7 +248,7 @@
 				&cam_sensor_rear_suspend>;
 		gpios = <&tlmm 13 0>,
 			<&tlmm 9 0>,
-			<&pm2falcon_gpios 4 0>,
+			<&pm660l_gpios 4 0>,
 			<&tlmm 8 0>;
 		qcom,gpio-reset = <1>;
 		qcom,gpio-vdig = <2>;
@@ -273,9 +273,9 @@
 		cell-index = <1>;
 		reg = <0x1>;
 		compatible = "qcom,eeprom";
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1750000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1980000 3600000 1350000>;
@@ -288,7 +288,7 @@
 				 &cam_sensor_rear2_suspend>;
 		gpios = <&tlmm 15 0>,
 			<&tlmm 30 0>,
-			<&pm2falcon_gpios 4 0>,
+			<&pm660l_gpios 4 0>,
 			<&tlmm 8 0>,
 			<&tlmm 27 0>;
 		qcom,gpio-reset = <1>;
@@ -316,9 +316,9 @@
 		cell-index = <2>;
 		reg = <0x2>;
 		compatible = "qcom,eeprom";
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 33000000 1352000>;
 		qcom,cam-vreg-max-voltage = <1950000 36000000 1352000>;
@@ -331,7 +331,7 @@
 				 &cam_sensor_front_suspend>;
 		gpios = <&tlmm 14 0>,
 			<&tlmm 28 0>,
-			<&pm2falcon_gpios 3 0>,
+			<&pm660l_gpios 3 0>,
 			<&tlmm 8 0>;
 		qcom,gpio-reset = <1>;
 		qcom,gpio-vdig = <2>;
@@ -362,9 +362,9 @@
 		qcom,actuator-src = <&actuator0>;
 		/*qcom,ois-src = <&ois0>;*/
 		qcom,eeprom-src = <&eeprom0>;
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
@@ -377,7 +377,7 @@
 				 &cam_sensor_rear_suspend>;
 		gpios = <&tlmm 13 0>,
 			<&tlmm 9 0>,
-			<&pm2falcon_gpios 4 0>,
+			<&pm660l_gpios 4 0>,
 			<&tlmm 8 0>;
 		qcom,gpio-reset = <1>;
 		qcom,gpio-vdig = <2>;
@@ -407,9 +407,9 @@
 		qcom,mount-angle = <90>;
 		qcom,actuator-src = <&actuator1>;
 		qcom,eeprom-src = <&eeprom1>;
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
@@ -422,7 +422,7 @@
 				 &cam_sensor_rear2_suspend>;
 		gpios = <&tlmm 15 0>,
 			<&tlmm 30 0>,
-			<&pm2falcon_gpios 4 0>,
+			<&pm660l_gpios 4 0>,
 			<&tlmm 8 0>;
 		qcom,gpio-reset = <1>;
 		qcom,gpio-vdig = <2>;
@@ -451,9 +451,9 @@
 		qcom,csid-sd-index = <2>;
 		qcom,mount-angle = <270>;
 		/*qcom,eeprom-src = <&eeprom2>;*/
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
@@ -466,7 +466,7 @@
 				 &cam_sensor_front_suspend>;
 		gpios = <&tlmm 14 0>,
 			<&tlmm 28 0>,
-			<&pm2falcon_gpios 3 0>,
+			<&pm660l_gpios 3 0>,
 			<&tlmm 8 0>;
 		qcom,gpio-reset = <1>;
 		qcom,gpio-vdig = <2>;
@@ -488,7 +488,7 @@
 	};
 };
 
-&pm2falcon_gpios {
+&pm660l_gpios {
 	gpio@c300 { /* GPIO4 -CAMERA SENSOR 0 VDIG*/
 		qcom,mode = <1>;                /* Output */
 		qcom,pull = <5>;                /* No Pull */
diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-pmfalcon.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-pm660.dtsi
index 74f43c15dd72..d29faacab5ee 100644
--- a/arch/arm/boot/dts/qcom/msm8998-interposer-pmfalcon.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8998-interposer-pm660.dtsi
@@ -234,8 +234,8 @@
 	};
 };
 
-#include "msm-pmfalcon.dtsi"
-#include "msm-pm2falcon.dtsi"
-#include "msm-pmfalcon-rpm-regulator.dtsi"
-#include "msm-pm2falcon-rpm-regulator.dtsi"
-#include "msmfalcon-regulator.dtsi"
+#include "msm-pm660.dtsi"
+#include "msm-pm660l.dtsi"
+#include "msm-pm660-rpm-regulator.dtsi"
+#include "msm-pm660l-rpm-regulator.dtsi"
+#include "sdm660-regulator.dtsi"
diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-audio.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-audio.dtsi
index b05707c6c585..c117bdbf5578 100644
--- a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-audio.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-audio.dtsi
@@ -11,9 +11,9 @@
  */
 
 #include "msm-audio.dtsi"
-#include "msmfalcon-audio.dtsi"
+#include "sdm660-audio.dtsi"
 
-&pm2falcon_3 {
+&pm660l_3 {
 	/delete-node/analog-codec;
 };
 
@@ -43,7 +43,7 @@
 };
 
 &clock_audio {
-	qcom,audio-ref-clk-gpio = <&pmfalcon_gpios 3 0>;
+	qcom,audio-ref-clk-gpio = <&pm660_gpios 3 0>;
 	clocks = <&clock_gcc clk_div_clk1>;
 	pinctrl-0 = <&spkr_i2s_clk_sleep>;
 	pinctrl-1 = <&spkr_i2s_clk_active>;
diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-cdp.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-cdp.dtsi
index 292bc07c679a..4bf3dc08ab3e 100644
--- a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-cdp.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-cdp.dtsi
@@ -18,9 +18,9 @@
 };
 
 &ufsphy1 {
-	vdda-phy-supply = <&pm2falcon_l1>;
-	vdda-pll-supply = <&pmfalcon_l1>;
-	vddp-ref-clk-supply = <&pmfalcon_l1>;
+	vdda-phy-supply = <&pm660l_l1>;
+	vdda-pll-supply = <&pm660_l1>;
+	vddp-ref-clk-supply = <&pm660_l1>;
 	vdda-phy-max-microamp = <51400>;
 	vdda-pll-max-microamp = <14600>;
 	vddp-ref-clk-max-microamp = <100>;
@@ -31,8 +31,8 @@
 &ufs1 {
 	vdd-hba-supply = <&gdsc_ufs>;
 	vdd-hba-fixed-regulator;
-	vcc-supply = <&pm2falcon_l4>;
-	vccq2-supply = <&pmfalcon_l8>;
+	vcc-supply = <&pm660l_l4>;
+	vccq2-supply = <&pm660_l8>;
 	vcc-max-microamp = <500000>;
 	vccq2-max-microamp = <600000>;
 	status = "ok";
@@ -43,11 +43,11 @@
 };
 
 &sdhc_2 {
-	vdd-supply = <&pm2falcon_l5>;
+	vdd-supply = <&pm660l_l5>;
 	qcom,vdd-voltage-level = <2950000 2950000>;
 	qcom,vdd-current-level = <200 800000>;
 
-	vdd-io-supply = <&pm2falcon_l2>;
+	vdd-io-supply = <&pm660l_l2>;
 	qcom,vdd-io-voltage-level = <1800000 2950000>;
 	qcom,vdd-io-current-level = <200 22000>;
 
@@ -185,13 +185,13 @@
 
 &mdss_dsi {
 	hw-config = "split_dsi";
-	vdda-1p2-supply = <&pmfalcon_l1>;
-	vdda-0p9-supply = <&pm2falcon_l1>;
+	vdda-1p2-supply = <&pm660_l1>;
+	vdda-0p9-supply = <&pm660l_l1>;
 };
 
 &mdss_dsi0 {
 	qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>;
-	wqhd-vddio-supply = <&pmfalcon_l11>;
+	wqhd-vddio-supply = <&pm660_l11>;
 	lab-supply = <&lcdb_ldo_vreg>;
 	ibb-supply = <&lcdb_ncp_vreg>;
 	pinctrl-names = "mdss_default", "mdss_sleep";
@@ -204,7 +204,7 @@
 
 &mdss_dsi1 {
 	qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>;
-	wqhd-vddio-supply = <&pmfalcon_l11>;
+	wqhd-vddio-supply = <&pm660_l11>;
 	lab-supply = <&lcdb_ldo_vreg>;
 	ibb-supply = <&lcdb_ncp_vreg>;
 	pinctrl-names = "mdss_default", "mdss_sleep";
@@ -342,8 +342,8 @@
 };
 
 &mdss_dp_ctrl {
-	vdda-1p2-supply = <&pmfalcon_l1>;
-	vdda-0p9-supply = <&pm2falcon_l1>;
+	vdda-1p2-supply = <&pm660_l1>;
+	vdda-0p9-supply = <&pm660l_l1>;
 	pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";
 	pinctrl-0 = <&mdss_dp_aux_active &mdss_dp_usbplug_cc_active>;
 	pinctrl-1 = <&mdss_dp_aux_suspend &mdss_dp_usbplug_cc_suspend>;
diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-mtp.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-mtp.dtsi
index 9a1e148c46a0..a9306475e24e 100644
--- a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-mtp.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-mtp.dtsi
@@ -19,9 +19,9 @@
 };
 
 &ufsphy1 {
-	vdda-phy-supply = <&pm2falcon_l1>;
-	vdda-pll-supply = <&pmfalcon_l1>;
-	vddp-ref-clk-supply = <&pmfalcon_l1>;
+	vdda-phy-supply = <&pm660l_l1>;
+	vdda-pll-supply = <&pm660_l1>;
+	vddp-ref-clk-supply = <&pm660_l1>;
 	vdda-phy-max-microamp = <51400>;
 	vdda-pll-max-microamp = <14600>;
 	vddp-ref-clk-max-microamp = <100>;
@@ -32,8 +32,8 @@
 &ufs1 {
 	vdd-hba-supply = <&gdsc_ufs>;
 	vdd-hba-fixed-regulator;
-	vcc-supply = <&pm2falcon_l4>;
-	vccq2-supply = <&pmfalcon_l8>;
+	vcc-supply = <&pm660l_l4>;
+	vccq2-supply = <&pm660_l8>;
 	vcc-max-microamp = <500000>;
 	vccq2-max-microamp = <600000>;
 	status = "ok";
@@ -44,11 +44,11 @@
 };
 
 &sdhc_2 {
-	vdd-supply = <&pm2falcon_l5>;
+	vdd-supply = <&pm660l_l5>;
 	qcom,vdd-voltage-level = <2950000 2950000>;
 	qcom,vdd-current-level = <200 800000>;
 
-	vdd-io-supply = <&pm2falcon_l2>;
+	vdd-io-supply = <&pm660l_l2>;
 	qcom,vdd-io-voltage-level = <1800000 2950000>;
 	qcom,vdd-io-current-level = <200 22000>;
 
@@ -196,8 +196,8 @@
 };
 
 &mdss_dp_ctrl {
-	vdda-1p2-supply = <&pmfalcon_l1>;
-	vdda-0p9-supply = <&pm2falcon_l1>;
+	vdda-1p2-supply = <&pm660_l1>;
+	vdda-0p9-supply = <&pm660l_l1>;
 	pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";
 	pinctrl-0 = <&mdss_dp_aux_active &mdss_dp_usbplug_cc_active>;
 	pinctrl-1 = <&mdss_dp_aux_suspend &mdss_dp_usbplug_cc_suspend>;
@@ -212,13 +212,13 @@
 
 &mdss_dsi {
 	hw-config = "split_dsi";
-	vdda-1p2-supply = <&pmfalcon_l1>;
-	vdda-0p9-supply = <&pm2falcon_l1>;
+	vdda-1p2-supply = <&pm660_l1>;
+	vdda-0p9-supply = <&pm660l_l1>;
 };
 
 &mdss_dsi0 {
 	qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>;
-	wqhd-vddio-supply = <&pmfalcon_l11>;
+	wqhd-vddio-supply = <&pm660_l11>;
 	lab-supply = <&lcdb_ldo_vreg>;
 	ibb-supply = <&lcdb_ncp_vreg>;
 	pinctrl-names = "mdss_default", "mdss_sleep";
@@ -231,7 +231,7 @@
 
 &mdss_dsi1 {
 	qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>;
-	wqhd-vddio-supply = <&pmfalcon_l11>;
+	wqhd-vddio-supply = <&pm660_l11>;
 	lab-supply = <&lcdb_ldo_vreg>;
 	ibb-supply = <&lcdb_ncp_vreg>;
 	pinctrl-names = "mdss_default", "mdss_sleep";
diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660.dtsi
index 347b924749fd..d6b278e2a789 100644
--- a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660.dtsi
@@ -343,10 +343,10 @@
 
 	bluetooth: bt_wcn3990 {
 		compatible = "qca,wcn3990";
-		qca,bt-vdd-core-supply = <&pmfalcon_l9_pin_ctrl>;
-		qca,bt-vdd-pa-supply = <&pmfalcon_l6_pin_ctrl>;
-		qca,bt-vdd-ldo-supply = <&pmfalcon_l19_pin_ctrl>;
-		qca,bt-chip-pwd-supply = <&pm2falcon_bob_pin1>;
+		qca,bt-vdd-core-supply = <&pm660_l9_pin_ctrl>;
+		qca,bt-vdd-pa-supply = <&pm660_l6_pin_ctrl>;
+		qca,bt-vdd-ldo-supply = <&pm660_l19_pin_ctrl>;
+		qca,bt-chip-pwd-supply = <&pm660l_bob_pin1>;
 		clocks = <&clock_gcc clk_rf_clk1>;
 		clock-names = "rf_clk1";
 
@@ -1872,7 +1872,7 @@
 					<61 512 240000 800000>;
 
 		qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
-		extcon = <&pmfalcon_pdphy>;
+		extcon = <&pm660_pdphy>;
 
 		clocks = <&clock_gcc clk_gcc_usb30_master_clk>,
 			<&clock_gcc clk_gcc_cfg_noc_usb3_axi_clk>,
@@ -1940,9 +1940,9 @@
 		      <0x01fcb24c 0x4>;
 		reg-names = "qusb_phy_base",
 				"tcsr_clamp_dig_n_1p8";
-		vdd-supply = <&pm2falcon_l1>;
-		vdda18-supply = <&pm2falcon_l10>;
-		vdda33-supply = <&pm2falcon_l7>;
+		vdd-supply = <&pm660l_l1>;
+		vdda18-supply = <&pm660l_l10>;
+		vdda33-supply = <&pm660l_l7>;
 		qcom,vdd-voltage-level = <0 880000 880000>;
 		qcom,qusb-phy-init-seq =
 				/* <value reg_offset> */
@@ -1970,8 +1970,8 @@
 		reg-names = "qmp_phy_base",
 			    "vls_clamp_reg",
 			    "tcsr_usb3_dp_phymode";
-		vdd-supply = <&pm2falcon_l1>;
-		core-supply = <&pmfalcon_l1>;
+		vdd-supply = <&pm660l_l1>;
+		core-supply = <&pm660_l1>;
 		qcom,vdd-voltage-level = <0 880000 880000>;
 		qcom,vbus-valid-override;
 		qcom,qmp-phy-init-seq =
@@ -2140,7 +2140,7 @@
 		reg = <0x17300000 0x00100>;
 		interrupts = <0 162 1>;
 
-		vdd_cx-supply = <&pm2falcon_s3_level>;
+		vdd_cx-supply = <&pm660l_s3_level>;
 		qcom,proxy-reg-names = "vdd_cx";
 		qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;
 
@@ -2195,9 +2195,9 @@
 					  "mnoc_axi_clk";
 
 		interrupts = <0 448 1>;
-		vdd_cx-supply = <&pm2falcon_s3_level>;
+		vdd_cx-supply = <&pm660l_s3_level>;
 		vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
-		vdd_mx-supply = <&pm2falcon_s5_level>;
+		vdd_mx-supply = <&pm660l_s5_level>;
 		vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
 		qcom,firmware-name = "modem";
 		qcom,pil-self-auth;
@@ -2606,7 +2606,7 @@
 		reg = <0x5c00000 0x4000>;
 		interrupts = <0 390 1>;
 
-		vdd_cx-supply = <&pm2falcon_l9_level>;
+		vdd_cx-supply = <&pm660l_l9_level>;
 		qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 0>;
 		qcom,proxy-reg-names = "vdd_cx";
 		qcom,keep-proxy-regs-on;
@@ -2908,8 +2908,8 @@
 			     <0 424 0 /* CE10 */ >,
 			     <0 425 0 /* CE11 */ >;
 		qcom,wlan-msa-memory = <0x100000>;
-		qcom,icnss-vadc = <&pmfalcon_vadc>;
-		qcom,icnss-adc_tm = <&pmfalcon_adc_tm>;
+		qcom,icnss-vadc = <&pm660_vadc>;
+		qcom,icnss-adc_tm = <&pm660_adc_tm>;
 	};
 
 	tspp: msm_tspp@0c1e7000 {
diff --git a/arch/arm/boot/dts/qcom/msm8998-v2-interposer-msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msm8998-v2-interposer-sdm660.dtsi
index dc548f8f499b..4edcd964f0b3 100644
--- a/arch/arm/boot/dts/qcom/msm8998-v2-interposer-msmfalcon.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8998-v2-interposer-sdm660.dtsi
@@ -16,7 +16,7 @@
  * msm8998.dtsi file.
  */
 
-#include "msm8998-interposer-msmfalcon.dtsi"
+#include "msm8998-interposer-sdm660.dtsi"
 #include "msm8998-v2-camera.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-cdp.dts b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-cdp.dts
index 5ea248f6f2dc..6884397bf0ba 100644
--- a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-cdp.dts
+++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-cdp.dts
@@ -13,41 +13,41 @@
 
 /dts-v1/;
 
-#include "msm8998-v2.1-interposer-msmfalcon.dtsi"
-#include "msm8998-interposer-msmfalcon-cdp.dtsi"
-#include "msm8998-interposer-pmfalcon.dtsi"
-#include "msm8998-interposer-msmfalcon-audio.dtsi"
+#include "msm8998-v2.1-interposer-sdm660.dtsi"
+#include "msm8998-interposer-sdm660-cdp.dtsi"
+#include "msm8998-interposer-pm660.dtsi"
+#include "msm8998-interposer-sdm660-audio.dtsi"
 #include "msm8998-interposer-camera-sensor-cdp.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. MSM 8998 v2.1 MSM FALCON Interposer CDP";
+	model = "Qualcomm Technologies, Inc. MSM 8998 v2.1 SDM 660 Interposer CDP";
 	compatible = "qcom,msm8998-cdp", "qcom,msm8998", "qcom,cdp";
 	qcom,board-id = <1 1>;
 };
 
-&pmfalcon_charger {
+&pm660_charger {
 	qcom,batteryless-platform;
 };
 
 &clock_gcc {
-	vdd_dig-supply = <&pm2falcon_s3_level>;
-	vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>;
+	vdd_dig-supply = <&pm660l_s3_level>;
+	vdd_dig_ao-supply = <&pm660l_s3_level_ao>;
 };
 
 &clock_mmss {
-	vdd_dig-supply = <&pm2falcon_s3_level>;
-	vdd_mmsscc_mx-supply = <&pm2falcon_s5_level>;
+	vdd_dig-supply = <&pm660l_s3_level>;
+	vdd_mmsscc_mx-supply = <&pm660l_s5_level>;
 };
 
 &clock_gpu {
-	vdd_dig-supply = <&pm2falcon_s3_level>;
+	vdd_dig-supply = <&pm660l_s3_level>;
 };
 
 &clock_gfx {
 	/* GFX Rail = CX */
-	vdd_gpucc-supply = <&pm2falcon_s3_level>;
-	vdd_mx-supply = <&pm2falcon_s5_level>;
-	vdd_gpu_mx-supply = <&pm2falcon_s5_level>;
+	vdd_gpucc-supply = <&pm660l_s3_level>;
+	vdd_mx-supply = <&pm660l_s5_level>;
+	vdd_gpu_mx-supply = <&pm660l_s5_level>;
 	qcom,gfxfreq-speedbin0 =
 		<         0 0                           0 >,
 		< 180000000 RPM_SMD_REGULATOR_LEVEL_MIN_SVS
@@ -83,31 +83,31 @@
 	clocks = <&clock_gfx clk_gfx3d_clk_src>;
 	qcom,force-enable-root-clk;
 	/* GFX Rail = CX */
-	parent-supply = <&pm2falcon_s3_level>;
+	parent-supply = <&pm660l_s3_level>;
 	status = "ok";
 };
 
 &usb3 {
-	extcon = <&pmfalcon_pdphy>;
+	extcon = <&pm660_pdphy>;
 };
 
 &qusb_phy0 {
-	vdd-supply = <&pm2falcon_l1>;
-	vdda18-supply = <&pmfalcon_l10>;
+	vdd-supply = <&pm660l_l1>;
+	vdda18-supply = <&pm660_l10>;
 	qcom,vdd-voltage-level = <0 925000 925000>;
-	vdda33-supply = <&pm2falcon_l7>;
+	vdda33-supply = <&pm660l_l7>;
 };
 
 &ssphy {
-	vdd-supply = <&pm2falcon_l1>;
+	vdd-supply = <&pm660l_l1>;
 	qcom,vdd-voltage-level = <0 925000 925000>;
-	core-supply = <&pmfalcon_l1>;
+	core-supply = <&pm660_l1>;
 };
 
 &mdss_dsi {
 	hw-config = "split_dsi";
-	vdda-1p2-supply = <&pmfalcon_l1>;
-	vdda-0p9-supply = <&pm2falcon_l1>;
+	vdda-1p2-supply = <&pm660_l1>;
+	vdda-0p9-supply = <&pm660l_l1>;
 
 	qcom,ctrl-supply-entries {
 		qcom,ctrl-supply-entry@0 {
@@ -126,7 +126,7 @@
 
 &mdss_dsi0 {
 	qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>;
-	wqhd-vddio-supply = <&pmfalcon_l11>;
+	wqhd-vddio-supply = <&pm660_l11>;
 	lab-supply = <&lcdb_ldo_vreg>;
 	ibb-supply = <&lcdb_ncp_vreg>;
 	pinctrl-names = "mdss_default", "mdss_sleep";
@@ -139,7 +139,7 @@
 
 &mdss_dsi1 {
 	qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>;
-	wqhd-vddio-supply = <&pmfalcon_l11>;
+	wqhd-vddio-supply = <&pm660_l11>;
 	lab-supply = <&lcdb_ldo_vreg>;
 	ibb-supply = <&lcdb_ncp_vreg>;
 	pinctrl-names = "mdss_default", "mdss_sleep";
@@ -150,6 +150,6 @@
 	qcom,panel-mode-gpio = <&tlmm 91 0>;
 };
 
-&pm2falcon_wled {
+&pm660l_wled {
 	qcom,led-strings-list = [01 02];
 };
diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-mtp.dts b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-mtp.dts
index 7c0c53033a44..2e5de95de0c5 100644
--- a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-mtp.dts
+++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-mtp.dts
@@ -13,41 +13,41 @@
 
 /dts-v1/;
 
-#include "msm8998-v2.1-interposer-msmfalcon.dtsi"
-#include "msm8998-interposer-msmfalcon-mtp.dtsi"
-#include "msm8998-interposer-pmfalcon.dtsi"
-#include "msm8998-interposer-msmfalcon-audio.dtsi"
+#include "msm8998-v2.1-interposer-sdm660.dtsi"
+#include "msm8998-interposer-sdm660-mtp.dtsi"
+#include "msm8998-interposer-pm660.dtsi"
+#include "msm8998-interposer-sdm660-audio.dtsi"
 #include "msm8998-interposer-camera-sensor-mtp.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. MSM 8998 v2.1 MSM FALCON Interposer MTP";
+	model = "Qualcomm Technologies, Inc. MSM 8998 v2.1 SDM 660 Interposer MTP";
 	compatible = "qcom,msm8998-mtp", "qcom,msm8998", "qcom,mtp";
 	qcom,board-id = <8 2>;
 };
 
-&pmfalcon_fg {
+&pm660_fg {
 	qcom,battery-data = <&mtp_batterydata>;
 };
 
 &clock_gcc {
-	vdd_dig-supply = <&pm2falcon_s3_level>;
-	vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>;
+	vdd_dig-supply = <&pm660l_s3_level>;
+	vdd_dig_ao-supply = <&pm660l_s3_level_ao>;
 };
 
 &clock_mmss {
-	vdd_dig-supply = <&pm2falcon_s3_level>;
-	vdd_mmsscc_mx-supply = <&pm2falcon_s5_level>;
+	vdd_dig-supply = <&pm660l_s3_level>;
+	vdd_mmsscc_mx-supply = <&pm660l_s5_level>;
 };
 
 &clock_gpu {
-	vdd_dig-supply = <&pm2falcon_s3_level>;
+	vdd_dig-supply = <&pm660l_s3_level>;
 };
 
 &clock_gfx {
 	/* GFX Rail = CX */
-	vdd_gpucc-supply = <&pm2falcon_s3_level>;
-	vdd_mx-supply = <&pm2falcon_s5_level>;
-	vdd_gpu_mx-supply = <&pm2falcon_s5_level>;
+	vdd_gpucc-supply = <&pm660l_s3_level>;
+	vdd_mx-supply = <&pm660l_s5_level>;
+	vdd_gpu_mx-supply = <&pm660l_s5_level>;
 	qcom,gfxfreq-speedbin0 =
 		<         0 0                           0 >,
 		< 180000000 RPM_SMD_REGULATOR_LEVEL_MIN_SVS
@@ -83,14 +83,14 @@
 	clocks = <&clock_gfx clk_gfx3d_clk_src>;
 	qcom,force-enable-root-clk;
 	/* GFX Rail = CX */
-	parent-supply = <&pm2falcon_s3_level>;
+	parent-supply = <&pm660l_s3_level>;
 	status = "ok";
 };
 
 &mdss_dsi {
 	hw-config = "split_dsi";
-	vdda-1p2-supply = <&pmfalcon_l1>;
-	vdda-0p9-supply = <&pm2falcon_l1>;
+	vdda-1p2-supply = <&pm660_l1>;
+	vdda-0p9-supply = <&pm660l_l1>;
 
 	qcom,ctrl-supply-entries {
 		qcom,ctrl-supply-entry@0 {
@@ -109,7 +109,7 @@
 
 &mdss_dsi0 {
 	qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>;
-	wqhd-vddio-supply = <&pmfalcon_l11>;
+	wqhd-vddio-supply = <&pm660_l11>;
 	lab-supply = <&lcdb_ldo_vreg>;
 	ibb-supply = <&lcdb_ncp_vreg>;
 	pinctrl-names = "mdss_default", "mdss_sleep";
@@ -122,7 +122,7 @@
 
 &mdss_dsi1 {
 	qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>;
-	wqhd-vddio-supply = <&pmfalcon_l11>;
+	wqhd-vddio-supply = <&pm660_l11>;
 	lab-supply = <&lcdb_ldo_vreg>;
 	ibb-supply = <&lcdb_ncp_vreg>;
 	pinctrl-names = "mdss_default", "mdss_sleep";
@@ -134,23 +134,23 @@
 };
 
 &usb3 {
-	extcon = <&pmfalcon_pdphy>;
+	extcon = <&pm660_pdphy>;
 };
 
 &qusb_phy0 {
-	vdd-supply = <&pm2falcon_l1>;
-	vdda18-supply = <&pmfalcon_l10>;
+	vdd-supply = <&pm660l_l1>;
+	vdda18-supply = <&pm660_l10>;
 	qcom,vdd-voltage-level = <0 925000 925000>;
-	vdda33-supply = <&pm2falcon_l7>;
+	vdda33-supply = <&pm660l_l7>;
 };
 
 &ssphy {
-	vdd-supply = <&pm2falcon_l1>;
+	vdd-supply = <&pm660l_l1>;
 	qcom,vdd-voltage-level = <0 925000 925000>;
-	core-supply = <&pmfalcon_l1>;
+	core-supply = <&pm660_l1>;
 };
 
-&pm2falcon_gpios {
+&pm660l_gpios {
 	/* GPIO 7 for VOL_UP */
 	gpio@c600 {
 		status = "okay";
@@ -170,7 +170,7 @@
 
 		vol_up {
 			label = "volume_up";
-			gpios = <&pm2falcon_gpios 7 0x1>;
+			gpios = <&pm660l_gpios 7 0x1>;
 			linux,input-type = <1>;
 			linux,code = <115>;
 			gpio-key,wakeup;
@@ -179,6 +179,6 @@
 	};
 };
 
-&pm2falcon_wled {
+&pm660l_wled {
 	qcom,led-strings-list = [01 02];
 };
diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dts b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-qrd.dts
index 3de548ed1446..9957adcc2336 100644
--- a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dts
+++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-qrd.dts
@@ -13,14 +13,14 @@
 
 /dts-v1/;
 
-#include "msm8998-v2.1-interposer-msmfalcon-qrd.dtsi"
-#include "msm8998-interposer-pmfalcon.dtsi"
-#include "msm8998-interposer-msmfalcon-audio.dtsi"
+#include "msm8998-v2.1-interposer-sdm660-qrd.dtsi"
+#include "msm8998-interposer-pm660.dtsi"
+#include "msm8998-interposer-sdm660-audio.dtsi"
 #include "msm8998-interposer-camera-sensor-qrd.dtsi"
 
 / {
 	model =
-	"Qualcomm Technologies, Inc. MSM 8998 v2.1 MSM FALCON Interposer QRD";
+	"Qualcomm Technologies, Inc. MSM 8998 v2.1 SDM 660 Interposer QRD";
 	compatible = "qcom,msm8998-qrd", "qcom,msm8998", "qcom,qrd";
 	qcom,board-id = <0x03000b 0x80>;
 };
@@ -44,24 +44,24 @@
 };
 
 &clock_gcc {
-	vdd_dig-supply = <&pm2falcon_s3_level>;
-	vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>;
+	vdd_dig-supply = <&pm660l_s3_level>;
+	vdd_dig_ao-supply = <&pm660l_s3_level_ao>;
 };
 
 &clock_mmss {
-	vdd_dig-supply = <&pm2falcon_s3_level>;
-	vdd_mmsscc_mx-supply = <&pm2falcon_s5_level>;
+	vdd_dig-supply = <&pm660l_s3_level>;
+	vdd_mmsscc_mx-supply = <&pm660l_s5_level>;
 };
 
 &clock_gpu {
-	vdd_dig-supply = <&pm2falcon_s3_level>;
+	vdd_dig-supply = <&pm660l_s3_level>;
 };
 
 &clock_gfx {
 	/* GFX Rail = CX */
-	vdd_gpucc-supply = <&pm2falcon_s3_level>;
-	vdd_mx-supply = <&pm2falcon_s5_level>;
-	vdd_gpu_mx-supply = <&pm2falcon_s5_level>;
+	vdd_gpucc-supply = <&pm660l_s3_level>;
+	vdd_mx-supply = <&pm660l_s5_level>;
+	vdd_gpu_mx-supply = <&pm660l_s5_level>;
 	qcom,gfxfreq-speedbin0 =
 		<         0 0                           0 >,
 		< 180000000 RPM_SMD_REGULATOR_LEVEL_MIN_SVS
@@ -97,33 +97,33 @@
 	clocks = <&clock_gfx clk_gfx3d_clk_src>;
 	qcom,force-enable-root-clk;
 	/* GFX Rail = CX */
-	parent-supply = <&pm2falcon_s3_level>;
+	parent-supply = <&pm660l_s3_level>;
 	status = "ok";
 };
 
 &usb3 {
-	extcon = <&pmfalcon_pdphy>;
+	extcon = <&pm660_pdphy>;
 };
 
 &qusb_phy0 {
-	vdd-supply = <&pm2falcon_l1>;
-	vdda18-supply = <&pmfalcon_l10>;
+	vdd-supply = <&pm660l_l1>;
+	vdda18-supply = <&pm660_l10>;
 	qcom,vdd-voltage-level = <0 925000 925000>;
-	vdda33-supply = <&pm2falcon_l7>;
+	vdda33-supply = <&pm660l_l7>;
 };
 
 &ssphy {
-	vdd-supply = <&pm2falcon_l1>;
+	vdd-supply = <&pm660l_l1>;
 	qcom,vdd-voltage-level = <0 925000 925000>;
-	core-supply = <&pmfalcon_l1>;
+	core-supply = <&pm660_l1>;
 };
 
 &sdhc_2 {
-	vdd-supply = <&pm2falcon_l5>;
-	vdd-io-supply = <&pm2falcon_l2>;
+	vdd-supply = <&pm660l_l5>;
+	vdd-io-supply = <&pm660l_l2>;
 };
 
-&pm2falcon_gpios {
+&pm660l_gpios {
 	/* GPIO 7 for VOL_UP */
 	gpio@c600 {
 		status = "ok";
@@ -143,7 +143,7 @@
 
 		vol_up {
 			label = "volume_up";
-			gpios = <&pm2falcon_gpios 7 0x1>;
+			gpios = <&pm660l_gpios 7 0x1>;
 			linux,input-type = <1>;
 			linux,code = <115>;
 			gpio-key,wakeup;
@@ -160,10 +160,10 @@
 	};
 };
 
-&pmfalcon_fg {
+&pm660_fg {
 	qcom,battery-data = <&qrd_batterydata>;
 };
 
-&pm2falcon_wled {
+&pm660l_wled {
 	qcom,led-strings-list = [00 01];
 };
diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dtsi b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-qrd.dtsi
index 9740e9c1b168..5a882c7eb27f 100644
--- a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-qrd.dtsi
@@ -11,16 +11,16 @@
  */
 
 #include <dt-bindings/interrupt-controller/irq.h>
-#include "msm8998-v2.1-interposer-msmfalcon.dtsi"
+#include "msm8998-v2.1-interposer-sdm660.dtsi"
 #include "msm8998-camera-sensor-mtp.dtsi"
 
 / {
 	bluetooth: bt_wcn3990 {
 		compatible = "qca,wcn3990";
-		qca,bt-vdd-core-supply = <&pmfalcon_l9_pin_ctrl>;
-		qca,bt-vdd-pa-supply = <&pmfalcon_l6_pin_ctrl>;
-		qca,bt-vdd-ldo-supply = <&pmfalcon_l19_pin_ctrl>;
-		qca,bt-chip-pwd-supply = <&pm2falcon_bob_pin1>;
+		qca,bt-vdd-core-supply = <&pm660_l9_pin_ctrl>;
+		qca,bt-vdd-pa-supply = <&pm660_l6_pin_ctrl>;
+		qca,bt-vdd-ldo-supply = <&pm660_l19_pin_ctrl>;
+		qca,bt-chip-pwd-supply = <&pm660l_bob_pin1>;
 		clocks = <&clock_gcc clk_rf_clk1>;
 		clock-names = "rf_clk1";
 
@@ -46,9 +46,9 @@
 };
 
 &ufsphy1 {
-	vdda-phy-supply = <&pm2falcon_l1>;
-	vdda-pll-supply = <&pmfalcon_l1>;
-	vddp-ref-clk-supply = <&pmfalcon_l1>;
+	vdda-phy-supply = <&pm660l_l1>;
+	vdda-pll-supply = <&pm660_l1>;
+	vddp-ref-clk-supply = <&pm660_l1>;
 	vdda-phy-max-uv = <925000>;
 	vdda-phy-min-uv = <800000>;
 	vdda-phy-max-microamp = <51400>;
@@ -61,8 +61,8 @@
 &ufs1 {
 	vdd-hba-supply = <&gdsc_ufs>;
 	vdd-hba-fixed-regulator;
-	vcc-supply = <&pm2falcon_l4>;
-	vccq2-supply = <&pmfalcon_l8>;
+	vcc-supply = <&pm660l_l4>;
+	vccq2-supply = <&pm660_l8>;
 	vcc-max-microamp = <500000>;
 	vccq2-max-microamp = <600000>;
 	status = "ok";
@@ -73,11 +73,11 @@
 };
 
 &sdhc_2 {
-	vdd-supply = <&pm2falcon_l5>;
+	vdd-supply = <&pm660l_l5>;
 	qcom,vdd-voltage-level = <2950000 2950000>;
 	qcom,vdd-current-level = <200 800000>;
 
-	vdd-io-supply = <&pm2falcon_l2>;
+	vdd-io-supply = <&pm660l_l2>;
 	qcom,vdd-io-voltage-level = <1800000 2950000>;
 	qcom,vdd-io-current-level = <200 22000>;
 
@@ -102,8 +102,8 @@
 		reg = <0x20>;
 		interrupt-parent = <&tlmm>;
 		interrupts = <125 0x2008>;
-		avdd-supply = <&pm2falcon_l3>;
-		vdd-supply = <&pmfalcon_l11>;
+		avdd-supply = <&pm660l_l3>;
+		vdd-supply = <&pm660_l11>;
 		synaptics,vdd-voltage = <1880000 1880000>;
 		synaptics,avdd-voltage = <3000000 3008000>;
 		synaptics,vdd-current = <40000>;
diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660.dtsi
index c2a393bd019d..8adbff55fead 100644
--- a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660.dtsi
@@ -10,7 +10,7 @@
  * GNU General Public License for more details.
  */
 
-#include "msm8998-v2-interposer-msmfalcon.dtsi"
+#include "msm8998-v2-interposer-sdm660.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. MSM8998 v2.1";
diff --git a/arch/arm/boot/dts/qcom/msmtriton-coresight.dtsi b/arch/arm/boot/dts/qcom/msmtriton-coresight.dtsi
index 796235ffd1be..e035cf85b9df 100644
--- a/arch/arm/boot/dts/qcom/msmtriton-coresight.dtsi
+++ b/arch/arm/boot/dts/qcom/msmtriton-coresight.dtsi
@@ -10,7 +10,7 @@
  * GNU General Public License for more details.
  */
 
-#include "msmfalcon-coresight.dtsi"
+#include "sdm660-coresight.dtsi"
 
 &etm0 {
 	cpu = <&CPU4>;
diff --git a/arch/arm/boot/dts/qcom/msmtriton-regulator.dtsi b/arch/arm/boot/dts/qcom/msmtriton-regulator.dtsi
index 2201a04cfbc1..73735159101d 100644
--- a/arch/arm/boot/dts/qcom/msmtriton-regulator.dtsi
+++ b/arch/arm/boot/dts/qcom/msmtriton-regulator.dtsi
@@ -13,7 +13,7 @@
 &rpm_bus {
 	rpm-regulator-smpa4 {
 		status = "okay";
-		pmfalcon_s4: regulator-s4 {
+		pm660_s4: regulator-s4 {
 			regulator-min-microvolt = <1805000>;
 			regulator-max-microvolt = <2040000>;
 			status = "okay";
@@ -22,7 +22,7 @@
 
 	rpm-regulator-smpa5 {
 		status = "okay";
-		pmfalcon_s5: regulator-s5 {
+		pm660_s5: regulator-s5 {
 			regulator-min-microvolt = <1350000>;
 			regulator-max-microvolt = <1350000>;
 			status = "okay";
@@ -31,7 +31,7 @@
 
 	rpm-regulator-smpa6 {
 		status = "okay";
-		pmfalcon_s6: regulator-s6 {
+		pm660_s6: regulator-s6 {
 			regulator-min-microvolt = <504000>;
 			regulator-max-microvolt = <992000>;
 			status = "okay";
@@ -40,7 +40,7 @@
 
 	rpm-regulator-smpb1 {
 		status = "okay";
-		pm2falcon_s1: regulator-s1 {
+		pm660l_s1: regulator-s1 {
 			regulator-min-microvolt = <1125000>;
 			regulator-max-microvolt = <1125000>;
 			status = "okay";
@@ -49,19 +49,19 @@
 
 	rpm-regulator-smpb2 {
 		status = "okay";
-		pm2falcon_s2: regulator-s2 {
+		pm660l_s2: regulator-s2 {
 			regulator-min-microvolt = <1050000>;
 			regulator-max-microvolt = <1050000>;
 			status = "okay";
 		};
 	};
 
-	/* PM2FALCON S3 + S4 - VDD_CX supply */
+	/* PM660L S3 + S4 - VDD_CX supply */
 	rpm-regulator-smpb3 {
 		status = "okay";
-		pm2falcon_s3_level: regulator-s3-level {
+		pm660l_s3_level: regulator-s3-level {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_s3_level";
+			regulator-name = "pm660l_s3_level";
 			qcom,set = <3>;
 			regulator-min-microvolt =
 				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
@@ -70,9 +70,9 @@
 			qcom,use-voltage-level;
 		};
 
-		pm2falcon_s3_floor_level: regulator-s3-floor-level {
+		pm660l_s3_floor_level: regulator-s3-floor-level {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_s3_floor_level";
+			regulator-name = "pm660l_s3_floor_level";
 			qcom,set = <3>;
 			regulator-min-microvolt =
 				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
@@ -82,9 +82,9 @@
 			qcom,always-send-voltage;
 		};
 
-		pm2falcon_s3_level_ao: regulator-s3-level-ao {
+		pm660l_s3_level_ao: regulator-s3-level-ao {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_s3_level_ao";
+			regulator-name = "pm660l_s3_level_ao";
 			qcom,set = <1>;
 			regulator-min-microvolt =
 				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
@@ -94,12 +94,12 @@
 		};
 	};
 
-	/* PM2FALCON S5 - VDD_MX supply */
+	/* PM660L S5 - VDD_MX supply */
 	rpm-regulator-smpb5 {
 		status = "okay";
-		pm2falcon_s5_level: regulator-s5-level {
+		pm660l_s5_level: regulator-s5-level {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_s5_level";
+			regulator-name = "pm660l_s5_level";
 			qcom,set = <3>;
 			regulator-min-microvolt =
 				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
@@ -108,9 +108,9 @@
 			qcom,use-voltage-level;
 		};
 
-		pm2falcon_s5_floor_level: regulator-s5-floor-level {
+		pm660l_s5_floor_level: regulator-s5-floor-level {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_s5_floor_level";
+			regulator-name = "pm660l_s5_floor_level";
 			qcom,set = <3>;
 			regulator-min-microvolt =
 				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
@@ -120,9 +120,9 @@
 			qcom,always-send-voltage;
 		};
 
-		pm2falcon_s5_level_ao: regulator-s5-level-ao {
+		pm660l_s5_level_ao: regulator-s5-level-ao {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_s5_level_ao";
+			regulator-name = "pm660l_s5_level_ao";
 			qcom,set = <1>;
 			regulator-min-microvolt =
 				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
@@ -134,7 +134,7 @@
 
 	rpm-regulator-ldoa1 {
 		status = "okay";
-		pmfalcon_l1: regulator-l1 {
+		pm660_l1: regulator-l1 {
 			regulator-min-microvolt = <1150000>;
 			regulator-max-microvolt = <1250000>;
 			status = "okay";
@@ -143,7 +143,7 @@
 
 	rpm-regulator-ldoa2 {
 		status = "okay";
-		pmfalcon_l2: regulator-l2 {
+		pm660_l2: regulator-l2 {
 			regulator-min-microvolt = <950000>;
 			regulator-max-microvolt = <1010000>;
 			status = "okay";
@@ -152,7 +152,7 @@
 
 	rpm-regulator-ldoa3 {
 		status = "okay";
-		pmfalcon_l3: regulator-l3 {
+		pm660_l3: regulator-l3 {
 			regulator-min-microvolt = <950000>;
 			regulator-max-microvolt = <1010000>;
 			status = "okay";
@@ -161,7 +161,7 @@
 
 	rpm-regulator-ldoa5 {
 		status = "okay";
-		pmfalcon_l5: regulator-l5 {
+		pm660_l5: regulator-l5 {
 			regulator-min-microvolt = <525000>;
 			regulator-max-microvolt = <950000>;
 			status = "okay";
@@ -170,15 +170,15 @@
 
 	rpm-regulator-ldoa6 {
 		status = "okay";
-		pmfalcon_l6: regulator-l6 {
+		pm660_l6: regulator-l6 {
 			regulator-min-microvolt = <1200000>;
 			regulator-max-microvolt = <1370000>;
 			status = "okay";
 		};
 
-		pmfalcon_l6_pin_ctrl: regulator-l6-pin-ctrl {
+		pm660_l6_pin_ctrl: regulator-l6-pin-ctrl {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pmfalcon_l6_pin_ctrl";
+			regulator-name = "pm660_l6_pin_ctrl";
 			qcom,set = <3>;
 			regulator-min-microvolt = <1200000>;
 			regulator-max-microvolt = <1370000>;
@@ -191,7 +191,7 @@
 
 	rpm-regulator-ldoa7 {
 		status = "okay";
-		pmfalcon_l7: regulator-l7 {
+		pm660_l7: regulator-l7 {
 			regulator-min-microvolt = <1200000>;
 			regulator-max-microvolt = <1200000>;
 			status = "okay";
@@ -200,7 +200,7 @@
 
 	rpm-regulator-ldoa8 {
 		status = "okay";
-		pmfalcon_l8: regulator-l8 {
+		pm660_l8: regulator-l8 {
 			regulator-min-microvolt = <1750000>;
 			regulator-max-microvolt = <1900000>;
 			status = "okay";
@@ -209,15 +209,15 @@
 
 	rpm-regulator-ldoa9 {
 		status = "okay";
-		pmfalcon_l9: regulator-l9 {
+		pm660_l9: regulator-l9 {
 			regulator-min-microvolt = <1750000>;
 			regulator-max-microvolt = <1900000>;
 			status = "okay";
 		};
 
-		pmfalcon_l9_pin_ctrl: regulator-l9-pin-ctrl {
+		pm660_l9_pin_ctrl: regulator-l9-pin-ctrl {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pmfalcon_l9_pin_ctrl";
+			regulator-name = "pm660_l9_pin_ctrl";
 			qcom,set = <3>;
 			regulator-min-microvolt = <1750000>;
 			regulator-max-microvolt = <1900000>;
@@ -230,7 +230,7 @@
 
 	rpm-regulator-ldoa10 {
 		status = "okay";
-		pmfalcon_l10: regulator-l10 {
+		pm660_l10: regulator-l10 {
 			regulator-min-microvolt = <1780000>;
 			regulator-max-microvolt = <1950000>;
 			status = "okay";
@@ -239,7 +239,7 @@
 
 	rpm-regulator-ldoa11 {
 		status = "okay";
-		pmfalcon_l11: regulator-l11 {
+		pm660_l11: regulator-l11 {
 			regulator-min-microvolt = <1780000>;
 			regulator-max-microvolt = <1950000>;
 			status = "okay";
@@ -248,7 +248,7 @@
 
 	rpm-regulator-ldoa12 {
 		status = "okay";
-		pmfalcon_l12: regulator-l12 {
+		pm660_l12: regulator-l12 {
 			regulator-min-microvolt = <1780000>;
 			regulator-max-microvolt = <1950000>;
 			status = "okay";
@@ -257,7 +257,7 @@
 
 	rpm-regulator-ldoa13 {
 		status = "okay";
-		pmfalcon_l13: regulator-l13 {
+		pm660_l13: regulator-l13 {
 			regulator-min-microvolt = <1780000>;
 			regulator-max-microvolt = <1950000>;
 			status = "okay";
@@ -266,7 +266,7 @@
 
 	rpm-regulator-ldoa14 {
 		status = "okay";
-		pmfalcon_l14: regulator-l14 {
+		pm660_l14: regulator-l14 {
 			regulator-min-microvolt = <1710000>;
 			regulator-max-microvolt = <1900000>;
 			status = "okay";
@@ -275,7 +275,7 @@
 
 	rpm-regulator-ldoa15 {
 		status = "okay";
-		pmfalcon_l15: regulator-l15 {
+		pm660_l15: regulator-l15 {
 			regulator-min-microvolt = <1650000>;
 			regulator-max-microvolt = <2950000>;
 			status = "okay";
@@ -284,7 +284,7 @@
 
 	rpm-regulator-ldoa17 {
 		status = "okay";
-		pmfalcon_l17: regulator-l17 {
+		pm660_l17: regulator-l17 {
 			regulator-min-microvolt = <1650000>;
 			regulator-max-microvolt = <2950000>;
 			status = "okay";
@@ -293,15 +293,15 @@
 
 	rpm-regulator-ldoa19 {
 		status = "okay";
-		pmfalcon_l19: regulator-l19 {
+		pm660_l19: regulator-l19 {
 			regulator-min-microvolt = <3200000>;
 			regulator-max-microvolt = <3400000>;
 			status = "okay";
 		};
 
-		pmfalcon_l19_pin_ctrl: regulator-l19-pin-ctrl {
+		pm660_l19_pin_ctrl: regulator-l19-pin-ctrl {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pmfalcon_l19_pin_ctrl";
+			regulator-name = "pm660_l19_pin_ctrl";
 			qcom,set = <3>;
 			regulator-min-microvolt = <3200000>;
 			regulator-max-microvolt = <3400000>;
@@ -314,7 +314,7 @@
 
 	rpm-regulator-ldob1 {
 		status = "okay";
-		pm2falcon_l1: regulator-l1 {
+		pm660l_l1: regulator-l1 {
 			regulator-min-microvolt = <800000>;
 			regulator-max-microvolt = <925000>;
 			status = "okay";
@@ -323,7 +323,7 @@
 
 	rpm-regulator-ldob2 {
 		status = "okay";
-		pm2falcon_l2: regulator-l2 {
+		pm660l_l2: regulator-l2 {
 			regulator-min-microvolt = <350000>;
 			regulator-max-microvolt = <3100000>;
 			status = "okay";
@@ -332,7 +332,7 @@
 
 	rpm-regulator-ldob3 {
 		status = "okay";
-		pm2falcon_l3: regulator-l3 {
+		pm660l_l3: regulator-l3 {
 			regulator-min-microvolt = <1710000>;
 			regulator-max-microvolt = <3600000>;
 			status = "okay";
@@ -341,7 +341,7 @@
 
 	rpm-regulator-ldob4 {
 		status = "okay";
-		pm2falcon_l4: regulator-l4 {
+		pm660l_l4: regulator-l4 {
 			regulator-min-microvolt = <1700000>;
 			regulator-max-microvolt = <2950000>;
 			status = "okay";
@@ -350,7 +350,7 @@
 
 	rpm-regulator-ldob5 {
 		status = "okay";
-		pm2falcon_l5: regulator-l5 {
+		pm660l_l5: regulator-l5 {
 			regulator-min-microvolt = <1721000>;
 			regulator-max-microvolt = <3600000>;
 			status = "okay";
@@ -359,7 +359,7 @@
 
 	rpm-regulator-ldob6 {
 		status = "okay";
-		pm2falcon_l6: regulator-l6 {
+		pm660l_l6: regulator-l6 {
 			regulator-min-microvolt = <1700000>;
 			regulator-max-microvolt = <3300000>;
 			status = "okay";
@@ -368,7 +368,7 @@
 
 	rpm-regulator-ldob7 {
 		status = "okay";
-		pm2falcon_l7: regulator-l7 {
+		pm660l_l7: regulator-l7 {
 			regulator-min-microvolt = <2700000>;
 			regulator-max-microvolt = <3125000>;
 			status = "okay";
@@ -377,19 +377,19 @@
 
 	rpm-regulator-ldob8 {
 		status = "okay";
-		pm2falcon_l8: regulator-l8 {
+		pm660l_l8: regulator-l8 {
 			regulator-min-microvolt = <3200000>;
 			regulator-max-microvolt = <3400000>;
 			status = "okay";
 		};
 	};
 
-	/* PM2FALCON L9 = VDD_SSC_CX supply */
+	/* PM660L L9 = VDD_SSC_CX supply */
 	rpm-regulator-ldob9 {
 		status = "okay";
-		pm2falcon_l9_level: regulator-l9-level {
+		pm660l_l9_level: regulator-l9-level {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_l9_level";
+			regulator-name = "pm660l_l9_level";
 			qcom,set = <3>;
 			regulator-min-microvolt =
 				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
@@ -398,9 +398,9 @@
 			qcom,use-voltage-level;
 		};
 
-		pm2falcon_l9_floor_level: regulator-l9-floor-level {
+		pm660l_l9_floor_level: regulator-l9-floor-level {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_l9_floor_level";
+			regulator-name = "pm660l_l9_floor_level";
 			qcom,set = <3>;
 			regulator-min-microvolt =
 				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
@@ -411,12 +411,12 @@
 		};
 	};
 
-	/* PM2FALCON L10 = VDD_SSC_MX supply */
+	/* PM660L L10 = VDD_SSC_MX supply */
 	rpm-regulator-ldob10 {
 		status = "okay";
-		pm2falcon_l10_level: regulator-l10-level {
+		pm660l_l10_level: regulator-l10-level {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_l10_level";
+			regulator-name = "pm660l_l10_level";
 			qcom,set = <3>;
 			regulator-min-microvolt =
 				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
@@ -425,9 +425,9 @@
 			qcom,use-voltage-level;
 		};
 
-		pm2falcon_l10_floor_level: regulator-l10-floor-level {
+		pm660l_l10_floor_level: regulator-l10-floor-level {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_l10_floor_level";
+			regulator-name = "pm660l_l10_floor_level";
 			qcom,set = <3>;
 			regulator-min-microvolt =
 				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
@@ -440,33 +440,33 @@
 
 	rpm-regulator-bobb {
 		status = "okay";
-		pm2falcon_bob: regulator-bob {
+		pm660l_bob: regulator-bob {
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3600000>;
 			status = "okay";
 		};
 
-		pm2falcon_bob_pin1: regulator-bob-pin1 {
+		pm660l_bob_pin1: regulator-bob-pin1 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_bob_pin1";
+			regulator-name = "pm660l_bob_pin1";
 			qcom,set = <3>;
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3600000>;
 			qcom,use-pin-ctrl-voltage1;
 		};
 
-		pm2falcon_bob_pin2: regulator-bob-pin2 {
+		pm660l_bob_pin2: regulator-bob-pin2 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_bob_pin2";
+			regulator-name = "pm660l_bob_pin2";
 			qcom,set = <3>;
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3600000>;
 			qcom,use-pin-ctrl-voltage2;
 		};
 
-		pm2falcon_bob_pin3: regulator-bob-pin3 {
+		pm660l_bob_pin3: regulator-bob-pin3 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_bob_pin3";
+			regulator-name = "pm660l_bob_pin3";
 			qcom,set = <3>;
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3600000>;
@@ -475,7 +475,7 @@
 	};
 };
 
-&pmfalcon_charger {
+&pm660_charger {
 	smb2_vbus: qcom,smb2-vbus {
 		regulator-name = "smb2-vbus";
 	};
diff --git a/arch/arm/boot/dts/qcom/msmtriton-rumi.dts b/arch/arm/boot/dts/qcom/msmtriton-rumi.dts
index a27ee2ac1ed5..797ba087d76c 100644
--- a/arch/arm/boot/dts/qcom/msmtriton-rumi.dts
+++ b/arch/arm/boot/dts/qcom/msmtriton-rumi.dts
@@ -14,7 +14,7 @@
 /dts-v1/;
 
 #include "msmtriton.dtsi"
-#include "msmfalcon-pinctrl.dtsi"
+#include "sdm660-pinctrl.dtsi"
 
 / {
 	model = "Qualcomm Technologies, Inc. MSM TRITON RUMI";
diff --git a/arch/arm/boot/dts/qcom/msmtriton.dtsi b/arch/arm/boot/dts/qcom/msmtriton.dtsi
index 4ef236d52911..0cea3cb973da 100644
--- a/arch/arm/boot/dts/qcom/msmtriton.dtsi
+++ b/arch/arm/boot/dts/qcom/msmtriton.dtsi
@@ -11,9 +11,9 @@
  */
 
 #include "skeleton64.dtsi"
-#include <dt-bindings/clock/qcom,gcc-msmfalcon.h>
-#include <dt-bindings/clock/qcom,gpu-msmfalcon.h>
-#include <dt-bindings/clock/qcom,mmcc-msmfalcon.h>
+#include <dt-bindings/clock/qcom,gcc-sdm660.h>
+#include <dt-bindings/clock/qcom,gpu-sdm660.h>
+#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
 #include <dt-bindings/clock/qcom,rpmcc.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
@@ -523,7 +523,7 @@
 		};
 		sensor_information12: qcom,sensor-information-12 {
 			qcom,sensor-type =  "alarm";
-			qcom,sensor-name = "pmfalcon_tz";
+			qcom,sensor-name = "pm660_tz";
 			qcom,scaling-factor = <1000>;
 		};
 		sensor_information13: qcom,sensor-information-13 {
@@ -598,7 +598,7 @@
 		qcom,vdd-restriction-temp = <5>;
 		qcom,vdd-restriction-temp-hysteresis = <10>;
 
-		vdd-dig-supply = <&pm2falcon_s3_floor_level>;
+		vdd-dig-supply = <&pm660l_s3_floor_level>;
 		vdd-gfx-supply = <&gfx_vreg_corner>;
 
 		qcom,vdd-dig-rstr{
@@ -734,25 +734,25 @@
 	};
 
 	clock_rpmcc: qcom,rpmcc {
-		compatible = "qcom,rpmcc-msmfalcon", "qcom,rpmcc";
+		compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
 		#clock-cells = <1>;
 	};
 
 	clock_gcc: clock-controller@100000 {
-		compatible = "qcom,gcc-msmfalcon", "syscon";
+		compatible = "qcom,gcc-sdm660", "syscon";
 		reg = <0x100000 0x94000>;
-		vdd_dig-supply = <&pm2falcon_s3_level>;
-		vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>;
+		vdd_dig-supply = <&pm660l_s3_level>;
+		vdd_dig_ao-supply = <&pm660l_s3_level_ao>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
 
 	clock_mmss: clock-controller@c8c0000 {
-		compatible = "qcom,mmcc-msmfalcon";
+		compatible = "qcom,mmcc-sdm660";
 		reg = <0xc8c0000 0x40000>;
-		vdd_mx_mmss-supply = <&pm2falcon_s5_level>;
-		vdd_dig_mmss-supply = <&pm2falcon_s3_level>;
-		vdda-supply = <&pmfalcon_l10>;
+		vdd_mx_mmss-supply = <&pm660l_s5_level>;
+		vdd_dig_mmss-supply = <&pm660l_s3_level>;
+		vdda-supply = <&pm660_l10>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
@@ -760,8 +760,8 @@
 	clock_gfx: clock-controller@5065000 {
 		compatible = "qcom,gpucc-msmtriton";
 		reg = <0x5065000 0x10000>;
-		vdd_dig_gfx-supply = <&pm2falcon_s3_level>;
-		vdd_mx_gfx-supply = <&pm2falcon_s5_level>;
+		vdd_dig_gfx-supply = <&pm660l_s3_level>;
+		vdd_mx_gfx-supply = <&pm660l_s5_level>;
 		vdd_gfx-supply = <&gfx_vreg_corner>;
 		qcom,gfxfreq-corner =
 			< 0         0>,
@@ -793,7 +793,7 @@
 	};
 
 	clock_debug: qcom,cc-debug@62000 {
-		compatible = "qcom,gcc-debug-msmfalcon";
+		compatible = "qcom,gcc-debug-sdm660";
 		reg = <0x62000 0x4>;
 		reg-names = "dbg_offset";
 		clocks = <&clock_rpmcc  RPM_XO_CLK_SRC>;
@@ -1017,7 +1017,7 @@
 		reg = <0x15700000 0x00100>;
 		interrupts = <0 162 1>;
 
-		vdd_cx-supply = <&pm2falcon_l9_level>;
+		vdd_cx-supply = <&pm660l_l9_level>;
 		qcom,proxy-reg-names = "vdd_cx";
 		qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;
 
@@ -1103,9 +1103,9 @@
 					 "mnoc_axi_clk";
 
 		interrupts = <0 448 1>;
-		vdd_cx-supply = <&pm2falcon_s3_level>;
+		vdd_cx-supply = <&pm660l_s3_level>;
 		vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
-		vdd_mx-supply = <&pm2falcon_s5_level>;
+		vdd_mx-supply = <&pm660l_s5_level>;
 		vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
 		qcom,firmware-name = "modem";
 		qcom,pil-self-auth;
@@ -1240,13 +1240,13 @@
 };
 
 #include "msmtriton-ion.dtsi"
-#include "msm-pmfalcon.dtsi"
-#include "msm-pm2falcon.dtsi"
-#include "msm-pmfalcon-rpm-regulator.dtsi"
-#include "msm-pm2falcon-rpm-regulator.dtsi"
+#include "msm-pm660.dtsi"
+#include "msm-pm660l.dtsi"
+#include "msm-pm660-rpm-regulator.dtsi"
+#include "msm-pm660l-rpm-regulator.dtsi"
 #include "msmtriton-regulator.dtsi"
-#include "msm-gdsc-falcon.dtsi"
-#include "msmfalcon-common.dtsi"
+#include "msm-gdsc-660.dtsi"
+#include "sdm660-common.dtsi"
 #include "msm-arm-smmu-triton.dtsi"
 
 &gdsc_usb30 {
diff --git a/arch/arm/boot/dts/qcom/apqfalcon-cdp.dts b/arch/arm/boot/dts/qcom/sda660-cdp.dts
index fc449860da0d..43e43f7f7125 100644
--- a/arch/arm/boot/dts/qcom/apqfalcon-cdp.dts
+++ b/arch/arm/boot/dts/qcom/sda660-cdp.dts
@@ -13,12 +13,12 @@
 
 /dts-v1/;
 
-#include "apqfalcon.dtsi"
-#include "msmfalcon-cdp.dtsi"
+#include "sda660.dtsi"
+#include "sdm660-cdp.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. APQ FALCON PMFALCON + PM2FALCON CDP";
-	compatible = "qcom,apqfalcon-cdp", "qcom,apqfalcon", "qcom,cdp";
+	model = "Qualcomm Technologies, Inc. SDA 660 PM660 + PM660L CDP";
+	compatible = "qcom,sda660-cdp", "qcom,sda660", "qcom,cdp";
 	qcom,board-id = <1 0>;
 	qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
 			<0x0001001b 0x0201011a 0x0 0x0>;
diff --git a/arch/arm/boot/dts/qcom/apqfalcon-mtp.dts b/arch/arm/boot/dts/qcom/sda660-mtp.dts
index c4f6e9fb30b9..0e14f3df9d8b 100644
--- a/arch/arm/boot/dts/qcom/apqfalcon-mtp.dts
+++ b/arch/arm/boot/dts/qcom/sda660-mtp.dts
@@ -13,12 +13,12 @@
 
 /dts-v1/;
 
-#include "apqfalcon.dtsi"
-#include "msmfalcon-mtp.dtsi"
+#include "sda660.dtsi"
+#include "sdm660-mtp.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. APQ FALCON PMFALCON + PM2FALCON MTP";
-	compatible = "qcom,apqfalcon-mtp", "qcom,apqfalcon", "qcom,mtp";
+	model = "Qualcomm Technologies, Inc. SDA 660 PM660 + PM660L MTP";
+	compatible = "qcom,sda660-mtp", "qcom,sda660", "qcom,mtp";
 	qcom,board-id = <8 0>;
 	qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
 			<0x0001001b 0x0201011a 0x0 0x0>;
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-cdp.dts b/arch/arm/boot/dts/qcom/sda660-pm660a-cdp.dts
index 3d3f8682941f..bfccd541e4b6 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-cdp.dts
+++ b/arch/arm/boot/dts/qcom/sda660-pm660a-cdp.dts
@@ -13,13 +13,13 @@
 
 /dts-v1/;
 
-#include "msmfalcon.dtsi"
-#include "msmfalcon-cdp.dtsi"
-#include "msm-pm3falcon.dtsi"
+#include "sda660.dtsi"
+#include "sdm660-cdp.dtsi"
+#include "msm-pm660a.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON CDP";
-	compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp";
+	model = "Qualcomm Technologies, Inc. SDA 660 PM660 + PM660A CDP";
+	compatible = "qcom,sda660-cdp", "qcom,sda660", "qcom,cdp";
 	qcom,board-id = <1 0>;
 	qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
 };
diff --git a/arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-mtp.dts b/arch/arm/boot/dts/qcom/sda660-pm660a-mtp.dts
index e7e8aeb9c2aa..1b7cfe1e1077 100644
--- a/arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-mtp.dts
+++ b/arch/arm/boot/dts/qcom/sda660-pm660a-mtp.dts
@@ -13,13 +13,13 @@
 
 /dts-v1/;
 
-#include "apqfalcon.dtsi"
-#include "msmfalcon-mtp.dtsi"
-#include "msm-pm3falcon.dtsi"
+#include "sda660.dtsi"
+#include "sdm660-mtp.dtsi"
+#include "msm-pm660a.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. APQ FALCON PMFALCON + PM3FALCON MTP";
-	compatible = "qcom,apqfalcon-mtp", "qcom,apqfalcon", "qcom,mtp";
+	model = "Qualcomm Technologies, Inc. SDA 660 PM660 + PM660A MTP";
+	compatible = "qcom,sda660-mtp", "qcom,sda660", "qcom,mtp";
 	qcom,board-id = <8 0>;
 	qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
 };
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-rcm.dts b/arch/arm/boot/dts/qcom/sda660-pm660a-rcm.dts
index c48124120d61..aa7a890fbe39 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-rcm.dts
+++ b/arch/arm/boot/dts/qcom/sda660-pm660a-rcm.dts
@@ -13,13 +13,13 @@
 
 /dts-v1/;
 
-#include "msmfalcon.dtsi"
-#include "msmfalcon-cdp.dtsi"
-#include "msm-pm3falcon.dtsi"
+#include "sda660.dtsi"
+#include "sdm660-cdp.dtsi"
+#include "msm-pm660a.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON RCM";
-	compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp";
+	model = "Qualcomm Technologies, Inc. SDA 660 PM660 + PM660A RCM";
+	compatible = "qcom,sda660-cdp", "qcom,sda660", "qcom,cdp";
 	qcom,board-id = <21 0>;
 	qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
 };
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-rcm.dts b/arch/arm/boot/dts/qcom/sda660-rcm.dts
index e4f59c735e70..73ea188c5221 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-rcm.dts
+++ b/arch/arm/boot/dts/qcom/sda660-rcm.dts
@@ -13,12 +13,12 @@
 
 /dts-v1/;
 
-#include "msmfalcon.dtsi"
-#include "msmfalcon-cdp.dtsi"
+#include "sda660.dtsi"
+#include "sdm660-cdp.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON RCM";
-	compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp";
+	model = "Qualcomm Technologies, Inc. SDA 660 PM660 + PM660L RCM";
+	compatible = "qcom,sda660-cdp", "qcom,sda660", "qcom,cdp";
 	qcom,board-id = <21 0>;
 	qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
 			<0x0001001b 0x0201011a 0x0 0x0>;
diff --git a/arch/arm/boot/dts/qcom/apqfalcon.dtsi b/arch/arm/boot/dts/qcom/sda660.dtsi
index d4dc066f6a79..d2919a9467dd 100644
--- a/arch/arm/boot/dts/qcom/apqfalcon.dtsi
+++ b/arch/arm/boot/dts/qcom/sda660.dtsi
@@ -10,10 +10,10 @@
  * GNU General Public License for more details.
  */
 
-#include "msmfalcon.dtsi"
+#include "sdm660.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. APQ FALCON";
-	compatible = "qcom,apqfalcon";
+	model = "Qualcomm Technologies, Inc. SDA 660";
+	compatible = "qcom,sda660";
 	qcom,msm-id = <324 0x0>;
 };
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-audio.dtsi b/arch/arm/boot/dts/qcom/sdm660-audio.dtsi
index df42ba124641..13ee40c71228 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-audio.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-audio.dtsi
@@ -11,8 +11,8 @@
  * GNU General Public License for more details.
  */
 
-#include "msmfalcon-wsa881x.dtsi"
-#include "msmfalcon-lpi.dtsi"
+#include "sdm660-wsa881x.dtsi"
+#include "sdm660-lpi.dtsi"
 
 &slim_aud {
 	status = "okay";
@@ -36,7 +36,7 @@
 		clocks = <&clock_audio AUDIO_PMI_CLK>,
 			<&clock_audio AUDIO_AP_CLK2>;
 
-		cdc-vdd-mic-bias-supply = <&pm2falcon_bob>;
+		cdc-vdd-mic-bias-supply = <&pm660l_bob>;
 		qcom,cdc-vdd-mic-bias-voltage = <3300000 3300000>;
 		qcom,cdc-vdd-mic-bias-current = <30400>;
 
@@ -68,7 +68,7 @@
 		clock-names = "wcd_clk";
 		clocks = <&clock_audio_lnbb AUDIO_PMIC_LNBB_CLK>;
 
-		cdc-vdd-mic-bias-supply = <&pm2falcon_bob>;
+		cdc-vdd-mic-bias-supply = <&pm660l_bob>;
 		qcom,cdc-vdd-mic-bias-voltage = <3300000 3300000>;
 		qcom,cdc-vdd-mic-bias-current = <30400>;
 
@@ -97,7 +97,7 @@
 	};
 };
 
-&pm2falcon_3 {
+&pm660l_3 {
 	pmic_analog_codec: analog-codec@f000 {
 		status = "disabled";
 		compatible = "qcom,pmic-analog-codec";
@@ -120,15 +120,15 @@
 				  "ins_rem_det",
 				  "mbhc_int";
 
-		cdc-vdda-cp-supply = <&pmfalcon_s4>;
+		cdc-vdda-cp-supply = <&pm660_s4>;
 		qcom,cdc-vdda-cp-voltage = <1900000 2050000>;
 		qcom,cdc-vdda-cp-current = <50000>;
 
-		cdc-vdd-pa-supply = <&pmfalcon_s4>;
+		cdc-vdd-pa-supply = <&pm660_s4>;
 		qcom,cdc-vdd-pa-voltage = <2040000 2040000>;
 		qcom,cdc-vdd-pa-current = <260000>;
 
-		cdc-vdd-mic-bias-supply = <&pm2falcon_l7>;
+		cdc-vdd-mic-bias-supply = <&pm660l_l7>;
 		qcom,cdc-vdd-mic-bias-voltage = <3125000 3125000>;
 		qcom,cdc-vdd-mic-bias-current = <5000>;
 
@@ -235,7 +235,7 @@
 	};
 };
 
-&pmfalcon_gpios {
+&pm660_gpios {
 	gpio@c200 {
 		status = "ok";
 		qcom,mode = <1>;
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-blsp.dtsi b/arch/arm/boot/dts/qcom/sdm660-blsp.dtsi
index c401d364409b..023c34d65680 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-blsp.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-blsp.dtsi
@@ -10,7 +10,7 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
-#include "msmfalcon-pinctrl.dtsi"
+#include "sdm660-pinctrl.dtsi"
 
 / {
 	aliases {
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-bus.dtsi b/arch/arm/boot/dts/qcom/sdm660-bus.dtsi
index 93c615639be9..93c615639be9 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-bus.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-bus.dtsi
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-camera-sensor-cdp.dtsi b/arch/arm/boot/dts/qcom/sdm660-camera-sensor-cdp.dtsi
index 63528e23160a..e31a863ae22d 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-camera-sensor-cdp.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-camera-sensor-cdp.dtsi
@@ -15,18 +15,18 @@
 	led_flash0: qcom,camera-flash@0 {
 		cell-index = <0>;
 		compatible = "qcom,camera-flash";
-		qcom,flash-source = <&pm2falcon_flash0 &pm2falcon_flash1>;
-		qcom,torch-source = <&pm2falcon_torch0 &pm2falcon_torch1>;
-		qcom,switch-source = <&pm2falcon_switch0>;
+		qcom,flash-source = <&pm660l_flash0 &pm660l_flash1>;
+		qcom,torch-source = <&pm660l_torch0 &pm660l_torch1>;
+		qcom,switch-source = <&pm660l_switch0>;
 		status = "ok";
 	};
 
 	led_flash1: qcom,camera-flash@1 {
 		cell-index = <1>;
 		compatible = "qcom,camera-flash";
-		qcom,flash-source = <&pm2falcon_flash2>;
-		qcom,torch-source = <&pm2falcon_torch2>;
-		qcom,switch-source = <&pm2falcon_switch1>;
+		qcom,flash-source = <&pm660l_flash2>;
+		qcom,torch-source = <&pm660l_torch2>;
+		qcom,switch-source = <&pm660l_switch1>;
 		status = "ok";
 	};
 };
@@ -97,9 +97,9 @@
 		cell-index = <0>;
 		reg = <0>;
 		compatible = "qcom,eeprom";
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
@@ -114,7 +114,7 @@
 				&cam_actuator_vaf_suspend>;
 		gpios = <&tlmm 32 0>,
 			<&tlmm 46 0>,
-			<&pm2falcon_gpios 4 0>,
+			<&pm660l_gpios 4 0>,
 			<&tlmm 51 0>,
 			<&tlmm 50 0>;
 		qcom,gpio-reset = <1>;
@@ -142,9 +142,9 @@
 		cell-index = <1>;
 		reg = <0x1>;
 		compatible = "qcom,eeprom";
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
@@ -157,7 +157,7 @@
 				&cam_sensor_rear2_suspend>;
 		gpios = <&tlmm 34 0>,
 		    <&tlmm 48 0>,
-		    <&pm2falcon_gpios 3 0>,
+		    <&pm660l_gpios 3 0>,
 		    <&tlmm 51 0>;
 		qcom,gpio-reset = <1>;
 		qcom,gpio-vdig = <2>;
@@ -182,9 +182,9 @@
 		cell-index = <2>;
 		reg = <0x2>;
 		compatible = "qcom,eeprom";
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
@@ -199,7 +199,7 @@
 				&cam_actuator_vaf_suspend>;
 		gpios = <&tlmm 33 0>,
 			<&tlmm 47 0>,
-			<&pmfalcon_gpios 3 0>,
+			<&pm660_gpios 3 0>,
 			<&tlmm 44 0>,
 			<&tlmm 50 0>;
 		qcom,gpio-reset = <1>;
@@ -234,9 +234,9 @@
 		qcom,actuator-src = <&actuator0>;
 		qcom,ois-src = <&ois0>;
 		qcom,eeprom-src = <&eeprom0>;
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
@@ -249,7 +249,7 @@
 				 &cam_sensor_rear_suspend>;
 		gpios = <&tlmm 32 0>,
 			<&tlmm 46 0>,
-			<&pm2falcon_gpios 4 0>,
+			<&pm660l_gpios 4 0>,
 			<&tlmm 51 0>;
 		qcom,gpio-reset = <1>;
 		qcom,gpio-vdig = <2>;
@@ -279,9 +279,9 @@
 		qcom,mount-angle = <90>;
 		qcom,actuator-src = <&actuator1>;
 		qcom,eeprom-src = <&eeprom1>;
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
@@ -294,7 +294,7 @@
 				 &cam_sensor_rear2_suspend>;
 		gpios = <&tlmm 34 0>,
 			<&tlmm 48 0>,
-			<&pm2falcon_gpios 3 0>,
+			<&pm660l_gpios 3 0>,
 			<&tlmm 51 0>;
 		qcom,gpio-reset = <1>;
 		qcom,gpio-vdig = <2>;
@@ -324,9 +324,9 @@
 		qcom,mount-angle = <90>;
 		qcom,actuator-src = <&actuator2>;
 		qcom,eeprom-src = <&eeprom2>;
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
@@ -339,7 +339,7 @@
 				 &cam_sensor_front_suspend>;
 		gpios = <&tlmm 33 0>,
 			<&tlmm 47 0>,
-			<&pm2falcon_gpios 3 0>,
+			<&pm660l_gpios 3 0>,
 			<&tlmm 51 0>;
 		qcom,gpio-reset = <1>;
 		qcom,gpio-vdig = <2>;
@@ -361,7 +361,7 @@
 	};
 };
 
-&pm2falcon_gpios {
+&pm660l_gpios {
 	gpio@c300 { /* GPIO4 -CAMERA SENSOR 0 VDIG*/
 		qcom,mode = <1>;                /* Output */
 		qcom,pull = <5>;                /* No Pull */
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-camera-sensor-mtp.dtsi b/arch/arm/boot/dts/qcom/sdm660-camera-sensor-mtp.dtsi
index 384807c4ef60..416cd99a81cb 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-camera-sensor-mtp.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-camera-sensor-mtp.dtsi
@@ -15,18 +15,18 @@
 	led_flash0: qcom,camera-flash@0 {
 		cell-index = <0>;
 		compatible = "qcom,camera-flash";
-		qcom,flash-source = <&pm2falcon_flash0 &pm2falcon_flash1>;
-		qcom,torch-source = <&pm2falcon_torch0 &pm2falcon_torch1>;
-		qcom,switch-source = <&pm2falcon_switch0>;
+		qcom,flash-source = <&pm660l_flash0 &pm660l_flash1>;
+		qcom,torch-source = <&pm660l_torch0 &pm660l_torch1>;
+		qcom,switch-source = <&pm660l_switch0>;
 		status = "ok";
 	};
 
 	led_flash1: qcom,camera-flash@1 {
 		cell-index = <1>;
 		compatible = "qcom,camera-flash";
-		qcom,flash-source = <&pm2falcon_flash2>;
-		qcom,torch-source = <&pm2falcon_torch2>;
-		qcom,switch-source = <&pm2falcon_switch1>;
+		qcom,flash-source = <&pm660l_flash2>;
+		qcom,torch-source = <&pm660l_torch2>;
+		qcom,switch-source = <&pm660l_switch1>;
 		status = "ok";
 	};
 };
@@ -97,9 +97,9 @@
 		cell-index = <0>;
 		reg = <0>;
 		compatible = "qcom,eeprom";
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
@@ -114,7 +114,7 @@
 				&cam_actuator_vaf_suspend>;
 		gpios = <&tlmm 32 0>,
 			<&tlmm 46 0>,
-			<&pm2falcon_gpios 4 0>,
+			<&pm660l_gpios 4 0>,
 			<&tlmm 51 0>,
 			<&tlmm 50 0>;
 		qcom,gpio-reset = <1>;
@@ -142,9 +142,9 @@
 		cell-index = <1>;
 		reg = <0x1>;
 		compatible = "qcom,eeprom";
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
@@ -157,7 +157,7 @@
 			&cam_sensor_rear2_suspend>;
 		gpios = <&tlmm 34 0>,
 		    <&tlmm 48 0>,
-		    <&pm2falcon_gpios 3 0>,
+		    <&pm660l_gpios 3 0>,
 		    <&tlmm 51 0>;
 		qcom,gpio-reset = <1>;
 		qcom,gpio-vdig = <2>;
@@ -182,9 +182,9 @@
 		cell-index = <2>;
 		reg = <0x2>;
 		compatible = "qcom,eeprom";
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
@@ -199,7 +199,7 @@
 				&cam_actuator_vaf_suspend>;
 		gpios = <&tlmm 33 0>,
 			<&tlmm 47 0>,
-			<&pmfalcon_gpios 3 0>,
+			<&pm660_gpios 3 0>,
 			<&tlmm 44 0>,
 			<&tlmm 50 0>;
 		qcom,gpio-reset = <1>;
@@ -234,9 +234,9 @@
 		qcom,actuator-src = <&actuator0>;
 		qcom,ois-src = <&ois0>;
 		qcom,eeprom-src = <&eeprom0>;
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
@@ -249,7 +249,7 @@
 				 &cam_sensor_rear_suspend>;
 		gpios = <&tlmm 32 0>,
 			<&tlmm 46 0>,
-			<&pm2falcon_gpios 4 0>,
+			<&pm660l_gpios 4 0>,
 			<&tlmm 51 0>;
 		qcom,gpio-reset = <1>;
 		qcom,gpio-vdig = <2>;
@@ -279,9 +279,9 @@
 		qcom,mount-angle = <90>;
 		qcom,actuator-src = <&actuator1>;
 		qcom,eeprom-src = <&eeprom1>;
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
@@ -294,7 +294,7 @@
 				 &cam_sensor_rear2_suspend>;
 		gpios = <&tlmm 34 0>,
 			<&tlmm 48 0>,
-			<&pm2falcon_gpios 3 0>,
+			<&pm660l_gpios 3 0>,
 			<&tlmm 51 0>;
 		qcom,gpio-reset = <1>;
 		qcom,gpio-vdig = <2>;
@@ -324,9 +324,9 @@
 		qcom,mount-angle = <90>;
 		qcom,actuator-src = <&actuator2>;
 		qcom,eeprom-src = <&eeprom2>;
-		cam_vio-supply = <&pmfalcon_l11>;
-		cam_vana-supply = <&pm2falcon_bob>;
-		cam_vdig-supply = <&pmfalcon_s5>;
+		cam_vio-supply = <&pm660_l11>;
+		cam_vana-supply = <&pm660l_bob>;
+		cam_vdig-supply = <&pm660_s5>;
 		qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
 		qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
 		qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
@@ -339,7 +339,7 @@
 				 &cam_sensor_front_suspend>;
 		gpios = <&tlmm 33 0>,
 			<&tlmm 47 0>,
-			<&pm2falcon_gpios 3 0>,
+			<&pm660l_gpios 3 0>,
 			<&tlmm 51 0>;
 		qcom,gpio-reset = <1>;
 		qcom,gpio-vdig = <2>;
@@ -361,7 +361,7 @@
 	};
 };
 
-&pm2falcon_gpios {
+&pm660l_gpios {
 	gpio@c300 { /* GPIO4 -CAMERA SENSOR 0 VDIG*/
 		qcom,mode = <1>;                /* Output */
 		qcom,pull = <5>;                /* No Pull */
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-camera.dtsi b/arch/arm/boot/dts/qcom/sdm660-camera.dtsi
index c16794550d88..09f5bec8ca62 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-camera.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-camera.dtsi
@@ -134,9 +134,9 @@
 		interrupts = <0 296 0>;
 		interrupt-names = "csid";
 		qcom,csi-vdd-voltage = <1200000>;
-		qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>;
+		qcom,mipi-csi-vdd-supply = <&pm660_l1>;
 		gdscr-supply = <&gdsc_camss_top>;
-		vdd_sec-supply = <&pm2falcon_l1>;
+		vdd_sec-supply = <&pm660l_l1>;
 		bimc_smmu-supply = <&gdsc_bimc_smmu>;
 		qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu";
 		qcom,cam-vreg-min-voltage = <925000 0 0>;
@@ -175,9 +175,9 @@
 		interrupts = <0 297 0>;
 		interrupt-names = "csid";
 		qcom,csi-vdd-voltage = <1200000>;
-		qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>;
+		qcom,mipi-csi-vdd-supply = <&pm660_l1>;
 		gdscr-supply = <&gdsc_camss_top>;
-		vdd_sec-supply = <&pm2falcon_l1>;
+		vdd_sec-supply = <&pm660l_l1>;
 		bimc_smmu-supply = <&gdsc_bimc_smmu>;
 		qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu";
 		qcom,cam-vreg-min-voltage = <925000 0 0>;
@@ -216,9 +216,9 @@
 		interrupts = <0 298 0>;
 		interrupt-names = "csid";
 		qcom,csi-vdd-voltage = <1200000>;
-		qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>;
+		qcom,mipi-csi-vdd-supply = <&pm660_l1>;
 		gdscr-supply = <&gdsc_camss_top>;
-		vdd_sec-supply = <&pm2falcon_l1>;
+		vdd_sec-supply = <&pm660l_l1>;
 		bimc_smmu-supply = <&gdsc_bimc_smmu>;
 		qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu";
 		qcom,cam-vreg-min-voltage = <925000 0 0>;
@@ -257,9 +257,9 @@
 		interrupts = <0 299 0>;
 		interrupt-names = "csid";
 		qcom,csi-vdd-voltage = <1200000>;
-		qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>;
+		qcom,mipi-csi-vdd-supply = <&pm660_l1>;
 		gdscr-supply = <&gdsc_camss_top>;
-		vdd_sec-supply = <&pm2falcon_l1>;
+		vdd_sec-supply = <&pm660l_l1>;
 		bimc_smmu-supply = <&gdsc_bimc_smmu>;
 		qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu";
 		qcom,cam-vreg-min-voltage = <925000 0 0>;
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-cdp.dts b/arch/arm/boot/dts/qcom/sdm660-cdp.dts
index ddcea8653983..8d338660a14a 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-cdp.dts
+++ b/arch/arm/boot/dts/qcom/sdm660-cdp.dts
@@ -13,12 +13,12 @@
 
 /dts-v1/;
 
-#include "msmfalcon.dtsi"
-#include "msmfalcon-cdp.dtsi"
+#include "sdm660.dtsi"
+#include "sdm660-cdp.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON CDP";
-	compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp";
+	model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L CDP";
+	compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp";
 	qcom,board-id = <1 0>;
 	qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
 			<0x0001001b 0x0201011a 0x0 0x0>;
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-cdp.dtsi b/arch/arm/boot/dts/qcom/sdm660-cdp.dtsi
index e1306bd78837..8304f3386c8a 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-cdp.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-cdp.dtsi
@@ -10,8 +10,8 @@
  * GNU General Public License for more details.
  */
 
-#include "msmfalcon-pinctrl.dtsi"
-#include "msmfalcon-camera-sensor-cdp.dtsi"
+#include "sdm660-pinctrl.dtsi"
+#include "sdm660-camera-sensor-cdp.dtsi"
 / {
 };
 
@@ -22,9 +22,9 @@
 };
 
 &ufsphy1 {
-	vdda-phy-supply = <&pm2falcon_l1>;
-	vdda-pll-supply = <&pmfalcon_l10>;
-	vddp-ref-clk-supply = <&pmfalcon_l1>;
+	vdda-phy-supply = <&pm660l_l1>;
+	vdda-pll-supply = <&pm660_l10>;
+	vddp-ref-clk-supply = <&pm660_l1>;
 	vdda-phy-max-microamp = <51400>;
 	vdda-pll-max-microamp = <14200>;
 	vddp-ref-clk-max-microamp = <100>;
@@ -35,8 +35,8 @@
 &ufs1 {
 	vdd-hba-supply = <&gdsc_ufs>;
 	vdd-hba-fixed-regulator;
-	vcc-supply = <&pm2falcon_l4>;
-	vccq2-supply = <&pmfalcon_l8>;
+	vcc-supply = <&pm660l_l4>;
+	vccq2-supply = <&pm660_l8>;
 	vcc-max-microamp = <500000>;
 	vccq2-max-microamp = <600000>;
 	status = "ok";
@@ -68,7 +68,7 @@
 	qcom,platform-te-gpio = <&tlmm 59 0>;
 };
 
-&pm2falcon_wled {
+&pm660l_wled {
 	qcom,led-strings-list = [01 02];
 };
 
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-common.dtsi b/arch/arm/boot/dts/qcom/sdm660-common.dtsi
index 1a7ec9fea452..a6bc326a6508 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-common.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-common.dtsi
@@ -35,7 +35,7 @@
 				<61 512 240000 800000>;
 
 		qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
-		extcon = <&pmfalcon_pdphy>;
+		extcon = <&pm660_pdphy>;
 		qcom,pm-qos-latency = <41>; /* CPU-CLUSTER-WFI-LVL latency +1 */
 
 		clocks = <&clock_gcc GCC_USB30_MASTER_CLK>,
@@ -140,9 +140,9 @@
 		reg-names = "qusb_phy_base",
 			"tcsr_clamp_dig_n_1p8",
 			"ref_clk_addr";
-		vdd-supply = <&pm2falcon_l1>;
-		vdda18-supply = <&pmfalcon_l10>;
-		vdda33-supply = <&pm2falcon_l7>;
+		vdd-supply = <&pm660l_l1>;
+		vdda18-supply = <&pm660_l10>;
+		vdda33-supply = <&pm660l_l7>;
 		qcom,vdd-voltage-level = <0 925000 925000>;
 		qcom,qusb-phy-init-seq = <0xf8 0x80
 					0xb3 0x84
@@ -176,8 +176,8 @@
 		reg-names = "qmp_phy_base",
 			"vls_clamp_reg",
 			"tcsr_usb3_dp_phymode";
-		vdd-supply = <&pm2falcon_l1>;
-		core-supply = <&pmfalcon_l10>;
+		vdd-supply = <&pm660l_l1>;
+		core-supply = <&pm660_l10>;
 		qcom,vdd-voltage-level = <0 925000 925000>;
 		vdd-core-voltage-level = <0 1800000 1800000>;
 		qcom,vbus-valid-override;
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-coresight.dtsi b/arch/arm/boot/dts/qcom/sdm660-coresight.dtsi
index 07f3743e8d1c..be625a15f4ec 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-coresight.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-coresight.dtsi
@@ -10,9 +10,9 @@
  * GNU General Public License for more details.
  */
 
-#include <dt-bindings/clock/qcom,gcc-msmfalcon.h>
-#include <dt-bindings/clock/qcom,gpu-msmfalcon.h>
-#include <dt-bindings/clock/qcom,mmcc-msmfalcon.h>
+#include <dt-bindings/clock/qcom,gcc-sdm660.h>
+#include <dt-bindings/clock/qcom,gpu-sdm660.h>
+#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
 
 &soc {
 	tmc_etr: tmc@6048000 {
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-gpu.dtsi b/arch/arm/boot/dts/qcom/sdm660-gpu.dtsi
index 5c11131b9ddf..5c11131b9ddf 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-gpu.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-gpu.dtsi
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-cdp.dts b/arch/arm/boot/dts/qcom/sdm660-internal-codec-cdp.dts
index ee3255ebe9f8..2a338d2ed07b 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-cdp.dts
+++ b/arch/arm/boot/dts/qcom/sdm660-internal-codec-cdp.dts
@@ -13,12 +13,12 @@
 
 /dts-v1/;
 
-#include "msmfalcon.dtsi"
-#include "msmfalcon-cdp.dtsi"
+#include "sdm660.dtsi"
+#include "sdm660-cdp.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON Int. Audio Codec CDP";
-	compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp";
+	model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L Int. Audio Codec CDP";
+	compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp";
 	qcom,board-id = <1 1>;
 	qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
 			<0x0001001b 0x0201011a 0x0 0x0>;
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-mtp.dts b/arch/arm/boot/dts/qcom/sdm660-internal-codec-mtp.dts
index 59611ab3e5ff..3518402bd0dc 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-mtp.dts
+++ b/arch/arm/boot/dts/qcom/sdm660-internal-codec-mtp.dts
@@ -13,12 +13,12 @@
 
 /dts-v1/;
 
-#include "msmfalcon.dtsi"
-#include "msmfalcon-mtp.dtsi"
+#include "sdm660.dtsi"
+#include "sdm660-mtp.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON Int. Audio Codec MTP";
-	compatible = "qcom,msmfalcon-mtp", "qcom,msmfalcon", "qcom,mtp";
+	model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L Int. Audio Codec MTP";
+	compatible = "qcom,sdm660-mtp", "qcom,sdm660", "qcom,mtp";
 	qcom,board-id = <8 1>;
 	qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
 			<0x0001001b 0x0201011a 0x0 0x0>;
@@ -61,7 +61,7 @@
 };
 
 &int_codec {
-	qcom,model = "msmfalcon-snd-card-mtp";
+	qcom,model = "sdm660-snd-card-mtp";
 	status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-pm3falcon-cdp.dts b/arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-cdp.dts
index fe91109a4a07..af0467cb3278 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-pm3falcon-cdp.dts
+++ b/arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-cdp.dts
@@ -13,13 +13,13 @@
 
 /dts-v1/;
 
-#include "msmfalcon.dtsi"
-#include "msmfalcon-cdp.dtsi"
-#include "msm-pm3falcon.dtsi"
+#include "sdm660.dtsi"
+#include "sdm660-cdp.dtsi"
+#include "msm-pm660a.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON Int. Audio Codec CDP";
-	compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp";
+	model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A Int. Audio Codec CDP";
+	compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp";
 	qcom,board-id = <1 1>;
 	qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
 };
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-pm3falcon-mtp.dts b/arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-mtp.dts
index 0653e898ec7d..c9e37963146c 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-pm3falcon-mtp.dts
+++ b/arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-mtp.dts
@@ -13,13 +13,13 @@
 
 /dts-v1/;
 
-#include "msmfalcon.dtsi"
-#include "msmfalcon-mtp.dtsi"
-#include "msm-pm3falcon.dtsi"
+#include "sdm660.dtsi"
+#include "sdm660-mtp.dtsi"
+#include "msm-pm660a.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON Int. Audio Codec MTP";
-	compatible = "qcom,msmfalcon-mtp", "qcom,msmfalcon", "qcom,mtp";
+	model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A Int. Audio Codec MTP";
+	compatible = "qcom,sdm660-mtp", "qcom,sdm660", "qcom,mtp";
 	qcom,board-id = <8 1>;
 	qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
 };
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-pm3falcon-rcm.dts b/arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-rcm.dts
index cb2b2239588d..d38f16d4f628 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-pm3falcon-rcm.dts
+++ b/arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-rcm.dts
@@ -13,13 +13,13 @@
 
 /dts-v1/;
 
-#include "msmfalcon.dtsi"
-#include "msmfalcon-cdp.dtsi"
-#include "msm-pm3falcon.dtsi"
+#include "sdm660.dtsi"
+#include "sdm660-cdp.dtsi"
+#include "msm-pm660a.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON Int. Audio Codec RCM";
-	compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp";
+	model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A Int. Audio Codec RCM";
+	compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp";
 	qcom,board-id = <21 1>;
 	qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
 };
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-rcm.dts b/arch/arm/boot/dts/qcom/sdm660-internal-codec-rcm.dts
index 1d67fe1129c7..eb171c66849b 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-rcm.dts
+++ b/arch/arm/boot/dts/qcom/sdm660-internal-codec-rcm.dts
@@ -13,12 +13,12 @@
 
 /dts-v1/;
 
-#include "msmfalcon.dtsi"
-#include "msmfalcon-cdp.dtsi"
+#include "sdm660.dtsi"
+#include "sdm660-cdp.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON Int. Audio Codec RCM";
-	compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp";
+	model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L Int. Audio Codec RCM";
+	compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp";
 	qcom,board-id = <21 1>;
 	qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
 			<0x0001001b 0x0201011a 0x0 0x0>;
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-ion.dtsi b/arch/arm/boot/dts/qcom/sdm660-ion.dtsi
index 00b9e61d01b8..00b9e61d01b8 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-ion.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-ion.dtsi
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-lpi.dtsi b/arch/arm/boot/dts/qcom/sdm660-lpi.dtsi
index 34946c07074b..34946c07074b 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-lpi.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-lpi.dtsi
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-mdss-panels.dtsi b/arch/arm/boot/dts/qcom/sdm660-mdss-panels.dtsi
index 28e5f6ba8b45..28e5f6ba8b45 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-mdss-panels.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-mdss-panels.dtsi
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-mdss-pll.dtsi b/arch/arm/boot/dts/qcom/sdm660-mdss-pll.dtsi
index 61baf6aff4b1..d2134c56541e 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-mdss-pll.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-mdss-pll.dtsi
@@ -12,7 +12,7 @@
 
 &soc {
 	mdss_dsi0_pll: qcom,mdss_dsi_pll@c994400 {
-		compatible = "qcom,mdss_dsi_pll_msmfalcon";
+		compatible = "qcom,mdss_dsi_pll_sdm660";
 		status = "ok";
 		label = "MDSS DSI 0 PLL";
 		cell-index = <0>;
@@ -47,7 +47,7 @@
 	};
 
 	mdss_dsi1_pll: qcom,mdss_dsi_pll@c996400 {
-		compatible = "qcom,mdss_dsi_pll_msmfalcon";
+		compatible = "qcom,mdss_dsi_pll_sdm660";
 		status = "ok";
 		label = "MDSS DSI 1 PLL";
 		cell-index = <1>;
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-mdss.dtsi b/arch/arm/boot/dts/qcom/sdm660-mdss.dtsi
index f7e1b053dbb2..ec14815a4be6 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-mdss.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-mdss.dtsi
@@ -265,8 +265,8 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		gdsc-supply = <&gdsc_mdss>;
-		vdda-1p2-supply = <&pmfalcon_l1>;
-		vdda-0p9-supply = <&pm2falcon_l1>;
+		vdda-1p2-supply = <&pm660_l1>;
+		vdda-0p9-supply = <&pm660l_l1>;
 		ranges = <0xc994000 0xc994000 0x400
 			0xc994400 0xc994400 0x588
 			0xc828000 0xc828000 0xac
@@ -351,7 +351,7 @@
 			reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys";
 
 			qcom,timing-db-mode;
-			wqhd-vddio-supply = <&pmfalcon_l11>;
+			wqhd-vddio-supply = <&pm660_l11>;
 			lab-supply = <&lcdb_ldo_vreg>;
 			ibb-supply = <&lcdb_ncp_vreg>;
 			qcom,mdss-mdp = <&mdss_mdp>;
@@ -391,7 +391,7 @@
 			reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys";
 
 			qcom,timing-db-mode;
-			wqhd-vddio-supply = <&pmfalcon_l11>;
+			wqhd-vddio-supply = <&pm660_l11>;
 			lab-supply = <&lcdb_ldo_vreg>;
 			ibb-supply = <&lcdb_ncp_vreg>;
 			qcom,mdss-mdp = <&mdss_mdp>;
@@ -446,8 +446,8 @@
 		qcom,mdss-fb-map = <&mdss_fb2>;
 
 		gdsc-supply = <&gdsc_mdss>;
-		vdda-1p2-supply = <&pmfalcon_l1>;
-		vdda-0p9-supply = <&pm2falcon_l1>;
+		vdda-1p2-supply = <&pm660_l1>;
+		vdda-0p9-supply = <&pm660l_l1>;
 
 		reg =	<0xc990000 0xa84>,
 			<0xc011000 0x910>,
@@ -576,4 +576,4 @@
 
 };
 
-#include "msmfalcon-mdss-panels.dtsi"
+#include "sdm660-mdss-panels.dtsi"
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-mtp.dts b/arch/arm/boot/dts/qcom/sdm660-mtp.dts
index cefe0d7c275b..3e5a6e1a38b9 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-mtp.dts
+++ b/arch/arm/boot/dts/qcom/sdm660-mtp.dts
@@ -13,12 +13,12 @@
 
 /dts-v1/;
 
-#include "msmfalcon.dtsi"
-#include "msmfalcon-mtp.dtsi"
+#include "sdm660.dtsi"
+#include "sdm660-mtp.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON MTP";
-	compatible = "qcom,msmfalcon-mtp", "qcom,msmfalcon", "qcom,mtp";
+	model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L MTP";
+	compatible = "qcom,sdm660-mtp", "qcom,sdm660", "qcom,mtp";
 	qcom,board-id = <8 0>;
 	qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
 			<0x0001001b 0x0201011a 0x0 0x0>;
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-mtp.dtsi b/arch/arm/boot/dts/qcom/sdm660-mtp.dtsi
index a9d77583b590..ef324de2de9f 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-mtp.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-mtp.dtsi
@@ -10,8 +10,8 @@
  * GNU General Public License for more details.
  */
 
-#include "msmfalcon-pinctrl.dtsi"
-#include "msmfalcon-camera-sensor-mtp.dtsi"
+#include "sdm660-pinctrl.dtsi"
+#include "sdm660-camera-sensor-mtp.dtsi"
 / {
 };
 
@@ -22,9 +22,9 @@
 };
 
 &ufsphy1 {
-	vdda-phy-supply = <&pm2falcon_l1>;
-	vdda-pll-supply = <&pmfalcon_l10>;
-	vddp-ref-clk-supply = <&pmfalcon_l1>;
+	vdda-phy-supply = <&pm660l_l1>;
+	vdda-pll-supply = <&pm660_l10>;
+	vddp-ref-clk-supply = <&pm660_l1>;
 	vdda-phy-max-microamp = <51400>;
 	vdda-pll-max-microamp = <14200>;
 	vddp-ref-clk-max-microamp = <100>;
@@ -35,8 +35,8 @@
 &ufs1 {
 	vdd-hba-supply = <&gdsc_ufs>;
 	vdd-hba-fixed-regulator;
-	vcc-supply = <&pm2falcon_l4>;
-	vccq2-supply = <&pmfalcon_l8>;
+	vcc-supply = <&pm660l_l4>;
+	vccq2-supply = <&pm660_l8>;
 	vcc-max-microamp = <500000>;
 	vccq2-max-microamp = <600000>;
 	status = "ok";
@@ -68,7 +68,7 @@
 	qcom,platform-te-gpio = <&tlmm 59 0>;
 };
 
-&pm2falcon_wled {
+&pm660l_wled {
 	qcom,led-strings-list = [01 02];
 };
 
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi b/arch/arm/boot/dts/qcom/sdm660-pinctrl.dtsi
index a54079413e7c..29343a243b9c 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-pinctrl.dtsi
@@ -12,7 +12,7 @@
 
 &soc {
 	tlmm: pinctrl@03000000 {
-		compatible = "qcom,msmfalcon-pinctrl";
+		compatible = "qcom,sdm660-pinctrl";
 		reg = <0x03000000 0xc00000>;
 		interrupts = <0 208 0>;
 		gpio-controller;
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pm.dtsi b/arch/arm/boot/dts/qcom/sdm660-pm.dtsi
index 6a9fc5bde361..6a9fc5bde361 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-pm.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-pm.dtsi
diff --git a/arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-cdp.dts b/arch/arm/boot/dts/qcom/sdm660-pm660a-cdp.dts
index 851533931a61..7621c8aef432 100644
--- a/arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-cdp.dts
+++ b/arch/arm/boot/dts/qcom/sdm660-pm660a-cdp.dts
@@ -13,13 +13,13 @@
 
 /dts-v1/;
 
-#include "apqfalcon.dtsi"
-#include "msmfalcon-cdp.dtsi"
-#include "msm-pm3falcon.dtsi"
+#include "sdm660.dtsi"
+#include "sdm660-cdp.dtsi"
+#include "msm-pm660a.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. APQ FALCON PMFALCON + PM3FALCON CDP";
-	compatible = "qcom,apqfalcon-cdp", "qcom,apqfalcon", "qcom,cdp";
+	model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A CDP";
+	compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp";
 	qcom,board-id = <1 0>;
 	qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
 };
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-mtp.dts b/arch/arm/boot/dts/qcom/sdm660-pm660a-mtp.dts
index 4e6bb7336f2b..1ea6dbde11ce 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-mtp.dts
+++ b/arch/arm/boot/dts/qcom/sdm660-pm660a-mtp.dts
@@ -13,13 +13,13 @@
 
 /dts-v1/;
 
-#include "msmfalcon.dtsi"
-#include "msmfalcon-mtp.dtsi"
-#include "msm-pm3falcon.dtsi"
+#include "sdm660.dtsi"
+#include "sdm660-mtp.dtsi"
+#include "msm-pm660a.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON MTP";
-	compatible = "qcom,msmfalcon-mtp", "qcom,msmfalcon", "qcom,mtp";
+	model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A MTP";
+	compatible = "qcom,sdm660-mtp", "qcom,sdm660", "qcom,mtp";
 	qcom,board-id = <8 0>;
 	qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
 };
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-qrd.dts b/arch/arm/boot/dts/qcom/sdm660-pm660a-qrd.dts
index e2d45f0d151e..b1078c53acdf 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-qrd.dts
+++ b/arch/arm/boot/dts/qcom/sdm660-pm660a-qrd.dts
@@ -13,13 +13,13 @@
 
 /dts-v1/;
 
-#include "msmfalcon.dtsi"
-#include "msmfalcon-qrd.dtsi"
-#include "msm-pm3falcon.dtsi"
+#include "sdm660.dtsi"
+#include "sdm660-qrd.dtsi"
+#include "msm-pm660a.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON QRD";
-	compatible = "qcom,msmfalcon-qrd", "qcom,msmfalcon", "qcom,qrd";
+	model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A QRD";
+	compatible = "qcom,sdm660-qrd", "qcom,sdm660", "qcom,qrd";
 	qcom,board-id = <0x1000b 0>;
 	qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
 };
diff --git a/arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-rcm.dts b/arch/arm/boot/dts/qcom/sdm660-pm660a-rcm.dts
index 68c4bd724ccd..0b65b4a3631c 100644
--- a/arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-rcm.dts
+++ b/arch/arm/boot/dts/qcom/sdm660-pm660a-rcm.dts
@@ -13,13 +13,13 @@
 
 /dts-v1/;
 
-#include "apqfalcon.dtsi"
-#include "msmfalcon-cdp.dtsi"
-#include "msm-pm3falcon.dtsi"
+#include "sdm660.dtsi"
+#include "sdm660-cdp.dtsi"
+#include "msm-pm660a.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. APQ FALCON PMFALCON + PM3FALCON RCM";
-	compatible = "qcom,apqfalcon-cdp", "qcom,apqfalcon", "qcom,cdp";
+	model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A RCM";
+	compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp";
 	qcom,board-id = <21 0>;
 	qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
 };
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-rumi.dts b/arch/arm/boot/dts/qcom/sdm660-pm660a-rumi.dts
index b81a92a4aa7c..16f1efb92f74 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-rumi.dts
+++ b/arch/arm/boot/dts/qcom/sdm660-pm660a-rumi.dts
@@ -13,13 +13,13 @@
 
 /dts-v1/;
 
-#include "msmfalcon.dtsi"
-#include "msmfalcon-pinctrl.dtsi"
-#include "msm-pm3falcon.dtsi"
+#include "sdm660.dtsi"
+#include "sdm660-pinctrl.dtsi"
+#include "msm-pm660a.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON RUMI";
-	compatible = "qcom,msmfalcon-rumi", "qcom,msmfalcon", "qcom,rumi";
+	model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A RUMI";
+	compatible = "qcom,sdm660-rumi", "qcom,sdm660", "qcom,rumi";
 	qcom,board-id = <15 0>;
 	qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
 
@@ -69,12 +69,12 @@
 
 &sdhc_1 {
 	/* device core power supply */
-	vdd-supply = <&pm2falcon_l4>;
+	vdd-supply = <&pm660l_l4>;
 	qcom,vdd-voltage-level = <2950000 2950000>;
 	qcom,vdd-current-level = <200 570000>;
 
 	/* device communication power supply */
-	vdd-io-supply = <&pmfalcon_l8>;
+	vdd-io-supply = <&pm660_l8>;
 	qcom,vdd-io-always-on;
 	qcom,vdd-io-lpm-sup;
 	qcom,vdd-io-voltage-level = <1800000 1800000>;
@@ -98,11 +98,11 @@
 	clock-output-names = "gcc_clocks";
 };
 
-&pmfalcon_charger {
+&pm660_charger {
 	status = "disabled";
 };
 
-&pmfalcon_fg {
+&pm660_fg {
 	status = "disabled";
 };
 
@@ -111,7 +111,7 @@
 	clock-output-names = "gfx_clocks";
 };
 
-&pmfalcon_pdphy {
+&pm660_pdphy {
 	status = "disabled";
 };
 
@@ -121,9 +121,9 @@
 };
 
 &ufsphy1 {
-	vdda-phy-supply = <&pm2falcon_l1>;
-	vdda-pll-supply = <&pmfalcon_l10>;
-	vddp-ref-clk-supply = <&pmfalcon_l1>;
+	vdda-phy-supply = <&pm660l_l1>;
+	vdda-pll-supply = <&pm660_l10>;
+	vddp-ref-clk-supply = <&pm660_l1>;
 	vdda-phy-max-microamp = <51400>;
 	vdda-pll-max-microamp = <14200>;
 	vddp-ref-clk-max-microamp = <100>;
@@ -133,8 +133,8 @@
 &ufs1 {
 	vdd-hba-supply = <&gdsc_ufs>;
 	vdd-hba-fixed-regulator;
-	vcc-supply = <&pm2falcon_l4>;
-	vccq2-supply = <&pmfalcon_l8>;
+	vcc-supply = <&pm660l_l4>;
+	vccq2-supply = <&pm660_l8>;
 	vcc-max-microamp = <500000>;
 	vccq2-max-microamp = <600000>;
 	qcom,disable-lpm;
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-sim.dts b/arch/arm/boot/dts/qcom/sdm660-pm660a-sim.dts
index b47c1d328201..2e2e1ac3993c 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-sim.dts
+++ b/arch/arm/boot/dts/qcom/sdm660-pm660a-sim.dts
@@ -13,13 +13,13 @@
 
 /dts-v1/;
 
-#include "msmfalcon.dtsi"
-#include "msmfalcon-pinctrl.dtsi"
-#include "msm-pm3falcon.dtsi"
+#include "sdm660.dtsi"
+#include "sdm660-pinctrl.dtsi"
+#include "msm-pm660a.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON SIM";
-	compatible = "qcom,msmfalcon-sim", "qcom,msmfalcon", "qcom,sim";
+	model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A SIM";
+	compatible = "qcom,sdm660-sim", "qcom,sdm660", "qcom,sim";
 	qcom,board-id = <16 0>;
 	qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
 
@@ -53,12 +53,12 @@
 
 &sdhc_1 {
 	/* device core power supply */
-	vdd-supply = <&pm2falcon_l4>;
+	vdd-supply = <&pm660l_l4>;
 	qcom,vdd-voltage-level = <2950000 2950000>;
 	qcom,vdd-current-level = <200 570000>;
 
 	/* device communication power supply */
-	vdd-io-supply = <&pmfalcon_l8>;
+	vdd-io-supply = <&pm660_l8>;
 	qcom,vdd-io-always-on;
 	qcom,vdd-io-lpm-sup;
 	qcom,vdd-io-voltage-level = <1800000 1800000>;
@@ -77,22 +77,22 @@
 	status = "ok";
 };
 
-&pmfalcon_charger {
+&pm660_charger {
 	status = "disabled";
 };
 
-&pmfalcon_fg {
+&pm660_fg {
 	status = "disabled";
 };
 
-&pmfalcon_pdphy {
+&pm660_pdphy {
 	status = "disabled";
 };
 
 &ufsphy1 {
-	vdda-phy-supply = <&pm2falcon_l1>;
-	vdda-pll-supply = <&pmfalcon_l10>;
-	vddp-ref-clk-supply = <&pmfalcon_l1>;
+	vdda-phy-supply = <&pm660l_l1>;
+	vdda-pll-supply = <&pm660_l10>;
+	vddp-ref-clk-supply = <&pm660_l1>;
 	vdda-phy-max-microamp = <51400>;
 	vdda-pll-max-microamp = <14200>;
 	vddp-ref-clk-max-microamp = <100>;
@@ -103,8 +103,8 @@
 &ufs1 {
 	vdd-hba-supply = <&gdsc_ufs>;
 	vdd-hba-fixed-regulator;
-	vcc-supply = <&pm2falcon_l4>;
-	vccq2-supply = <&pmfalcon_l8>;
+	vcc-supply = <&pm660l_l4>;
+	vccq2-supply = <&pm660_l8>;
 	vcc-max-microamp = <500000>;
 	vccq2-max-microamp = <600000>;
 	status = "ok";
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-qrd.dts b/arch/arm/boot/dts/qcom/sdm660-qrd.dts
index b97fdd18e229..29fc0d776fd0 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-qrd.dts
+++ b/arch/arm/boot/dts/qcom/sdm660-qrd.dts
@@ -13,12 +13,12 @@
 
 /dts-v1/;
 
-#include "msmfalcon.dtsi"
-#include "msmfalcon-qrd.dtsi"
+#include "sdm660.dtsi"
+#include "sdm660-qrd.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON QRD";
-	compatible = "qcom,msmfalcon-qrd", "qcom,msmfalcon", "qcom,qrd";
+	model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L QRD";
+	compatible = "qcom,sdm660-qrd", "qcom,sdm660", "qcom,qrd";
 	qcom,board-id = <0x1000b 0>;
 	qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
 			<0x0001001b 0x0201011a 0x0 0x0>;
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-qrd.dtsi b/arch/arm/boot/dts/qcom/sdm660-qrd.dtsi
index 3ec991b82bba..115b48568fe9 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-qrd.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-qrd.dtsi
@@ -10,7 +10,7 @@
  * GNU General Public License for more details.
  */
 
-#include "msmfalcon-pinctrl.dtsi"
+#include "sdm660-pinctrl.dtsi"
 / {
 };
 
diff --git a/arch/arm/boot/dts/qcom/apqfalcon-rcm.dts b/arch/arm/boot/dts/qcom/sdm660-rcm.dts
index 8f4b164c55ca..a3f9445d4164 100644
--- a/arch/arm/boot/dts/qcom/apqfalcon-rcm.dts
+++ b/arch/arm/boot/dts/qcom/sdm660-rcm.dts
@@ -13,12 +13,12 @@
 
 /dts-v1/;
 
-#include "apqfalcon.dtsi"
-#include "msmfalcon-cdp.dtsi"
+#include "sdm660.dtsi"
+#include "sdm660-cdp.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. APQ FALCON PMFALCON + PM2FALCON RCM";
-	compatible = "qcom,apqfalcon-cdp", "qcom,apqfalcon", "qcom,cdp";
+	model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L RCM";
+	compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp";
 	qcom,board-id = <21 0>;
 	qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
 			<0x0001001b 0x0201011a 0x0 0x0>;
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-regulator.dtsi b/arch/arm/boot/dts/qcom/sdm660-regulator.dtsi
index 02e61bcdd95c..4869a8af08d6 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-regulator.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-regulator.dtsi
@@ -13,7 +13,7 @@
 &rpm_bus {
 	rpm-regulator-smpa4 {
 		status = "okay";
-		pmfalcon_s4: regulator-s4 {
+		pm660_s4: regulator-s4 {
 			regulator-min-microvolt = <1805000>;
 			regulator-max-microvolt = <2040000>;
 			status = "okay";
@@ -22,7 +22,7 @@
 
 	rpm-regulator-smpa5 {
 		status = "okay";
-		pmfalcon_s5: regulator-s5 {
+		pm660_s5: regulator-s5 {
 			regulator-min-microvolt = <1350000>;
 			regulator-max-microvolt = <1350000>;
 			status = "okay";
@@ -31,7 +31,7 @@
 
 	rpm-regulator-smpa6 {
 		status = "okay";
-		pmfalcon_s6: regulator-s6 {
+		pm660_s6: regulator-s6 {
 			regulator-min-microvolt = <504000>;
 			regulator-max-microvolt = <992000>;
 			status = "okay";
@@ -40,7 +40,7 @@
 
 	rpm-regulator-smpb1 {
 		status = "okay";
-		pm2falcon_s1: regulator-s1 {
+		pm660l_s1: regulator-s1 {
 			regulator-min-microvolt = <1125000>;
 			regulator-max-microvolt = <1125000>;
 			status = "okay";
@@ -49,19 +49,19 @@
 
 	rpm-regulator-smpb2 {
 		status = "okay";
-		pm2falcon_s2: regulator-s2 {
+		pm660l_s2: regulator-s2 {
 			regulator-min-microvolt = <1050000>;
 			regulator-max-microvolt = <1050000>;
 			status = "okay";
 		};
 	};
 
-	/* PM2FALCON S3 + S4 - VDD_CX supply */
+	/* PM660L S3 + S4 - VDD_CX supply */
 	rpm-regulator-smpb3 {
 		status = "okay";
-		pm2falcon_s3_level: regulator-s3-level {
+		pm660l_s3_level: regulator-s3-level {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_s3_level";
+			regulator-name = "pm660l_s3_level";
 			qcom,set = <3>;
 			regulator-min-microvolt =
 				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
@@ -70,9 +70,9 @@
 			qcom,use-voltage-level;
 		};
 
-		pm2falcon_s3_floor_level: regulator-s3-floor-level {
+		pm660l_s3_floor_level: regulator-s3-floor-level {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_s3_floor_level";
+			regulator-name = "pm660l_s3_floor_level";
 			qcom,set = <3>;
 			regulator-min-microvolt =
 				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
@@ -82,9 +82,9 @@
 			qcom,always-send-voltage;
 		};
 
-		pm2falcon_s3_level_ao: regulator-s3-level-ao {
+		pm660l_s3_level_ao: regulator-s3-level-ao {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_s3_level_ao";
+			regulator-name = "pm660l_s3_level_ao";
 			qcom,set = <1>;
 			regulator-min-microvolt =
 				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
@@ -94,12 +94,12 @@
 		};
 	};
 
-	/* PM2FALCON S5 - VDD_MX supply */
+	/* PM660L S5 - VDD_MX supply */
 	rpm-regulator-smpb5 {
 		status = "okay";
-		pm2falcon_s5_level: regulator-s5-level {
+		pm660l_s5_level: regulator-s5-level {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_s5_level";
+			regulator-name = "pm660l_s5_level";
 			qcom,set = <3>;
 			regulator-min-microvolt =
 				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
@@ -108,9 +108,9 @@
 			qcom,use-voltage-level;
 		};
 
-		pm2falcon_s5_floor_level: regulator-s5-floor-level {
+		pm660l_s5_floor_level: regulator-s5-floor-level {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_s5_floor_level";
+			regulator-name = "pm660l_s5_floor_level";
 			qcom,set = <3>;
 			regulator-min-microvolt =
 				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
@@ -120,9 +120,9 @@
 			qcom,always-send-voltage;
 		};
 
-		pm2falcon_s5_level_ao: regulator-s5-level-ao {
+		pm660l_s5_level_ao: regulator-s5-level-ao {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_s5_level_ao";
+			regulator-name = "pm660l_s5_level_ao";
 			qcom,set = <1>;
 			regulator-min-microvolt =
 				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
@@ -134,7 +134,7 @@
 
 	rpm-regulator-ldoa1 {
 		status = "okay";
-		pmfalcon_l1: regulator-l1 {
+		pm660_l1: regulator-l1 {
 			regulator-min-microvolt = <1150000>;
 			regulator-max-microvolt = <1250000>;
 			status = "okay";
@@ -143,7 +143,7 @@
 
 	rpm-regulator-ldoa2 {
 		status = "okay";
-		pmfalcon_l2: regulator-l2 {
+		pm660_l2: regulator-l2 {
 			regulator-min-microvolt = <950000>;
 			regulator-max-microvolt = <1010000>;
 			status = "okay";
@@ -152,7 +152,7 @@
 
 	rpm-regulator-ldoa3 {
 		status = "okay";
-		pmfalcon_l3: regulator-l3 {
+		pm660_l3: regulator-l3 {
 			regulator-min-microvolt = <950000>;
 			regulator-max-microvolt = <1010000>;
 			status = "okay";
@@ -162,7 +162,7 @@
 	/* TODO: remove if ADRASTEA CX/MX not voted from APPS */
 	rpm-regulator-ldoa5 {
 		status = "okay";
-		pmfalcon_l5: regulator-l5 {
+		pm660_l5: regulator-l5 {
 			regulator-min-microvolt = <525000>;
 			regulator-max-microvolt = <950000>;
 			status = "okay";
@@ -171,15 +171,15 @@
 
 	rpm-regulator-ldoa6 {
 		status = "okay";
-		pmfalcon_l6: regulator-l6 {
+		pm660_l6: regulator-l6 {
 			regulator-min-microvolt = <1200000>;
 			regulator-max-microvolt = <1370000>;
 			status = "okay";
 		};
 
-		pmfalcon_l6_pin_ctrl: regulator-l6-pin-ctrl {
+		pm660_l6_pin_ctrl: regulator-l6-pin-ctrl {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pmfalcon_l6_pin_ctrl";
+			regulator-name = "pm660_l6_pin_ctrl";
 			qcom,set = <3>;
 			regulator-min-microvolt = <1200000>;
 			regulator-max-microvolt = <1370000>;
@@ -192,7 +192,7 @@
 
 	rpm-regulator-ldoa7 {
 		status = "okay";
-		pmfalcon_l7: regulator-l7 {
+		pm660_l7: regulator-l7 {
 			regulator-min-microvolt = <1200000>;
 			regulator-max-microvolt = <1200000>;
 			status = "okay";
@@ -201,7 +201,7 @@
 
 	rpm-regulator-ldoa8 {
 		status = "okay";
-		pmfalcon_l8: regulator-l8 {
+		pm660_l8: regulator-l8 {
 			regulator-min-microvolt = <1750000>;
 			regulator-max-microvolt = <1900000>;
 			status = "okay";
@@ -210,15 +210,15 @@
 
 	rpm-regulator-ldoa9 {
 		status = "okay";
-		pmfalcon_l9: regulator-l9 {
+		pm660_l9: regulator-l9 {
 			regulator-min-microvolt = <1750000>;
 			regulator-max-microvolt = <1900000>;
 			status = "okay";
 		};
 
-		pmfalcon_l9_pin_ctrl: regulator-l9-pin-ctrl {
+		pm660_l9_pin_ctrl: regulator-l9-pin-ctrl {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pmfalcon_l9_pin_ctrl";
+			regulator-name = "pm660_l9_pin_ctrl";
 			qcom,set = <3>;
 			regulator-min-microvolt = <1750000>;
 			regulator-max-microvolt = <1900000>;
@@ -231,7 +231,7 @@
 
 	rpm-regulator-ldoa10 {
 		status = "okay";
-		pmfalcon_l10: regulator-l10 {
+		pm660_l10: regulator-l10 {
 			regulator-min-microvolt = <1780000>;
 			regulator-max-microvolt = <1950000>;
 			status = "okay";
@@ -240,7 +240,7 @@
 
 	rpm-regulator-ldoa11 {
 		status = "okay";
-		pmfalcon_l11: regulator-l11 {
+		pm660_l11: regulator-l11 {
 			regulator-min-microvolt = <1780000>;
 			regulator-max-microvolt = <1950000>;
 			status = "okay";
@@ -249,7 +249,7 @@
 
 	rpm-regulator-ldoa12 {
 		status = "okay";
-		pmfalcon_l12: regulator-l12 {
+		pm660_l12: regulator-l12 {
 			regulator-min-microvolt = <1780000>;
 			regulator-max-microvolt = <1950000>;
 			status = "okay";
@@ -258,7 +258,7 @@
 
 	rpm-regulator-ldoa13 {
 		status = "okay";
-		pmfalcon_l13: regulator-l13 {
+		pm660_l13: regulator-l13 {
 			regulator-min-microvolt = <1780000>;
 			regulator-max-microvolt = <1950000>;
 			status = "okay";
@@ -267,7 +267,7 @@
 
 	rpm-regulator-ldoa14 {
 		status = "okay";
-		pmfalcon_l14: regulator-l14 {
+		pm660_l14: regulator-l14 {
 			regulator-min-microvolt = <1710000>;
 			regulator-max-microvolt = <1900000>;
 			status = "okay";
@@ -276,7 +276,7 @@
 
 	rpm-regulator-ldoa15 {
 		status = "okay";
-		pmfalcon_l15: regulator-l15 {
+		pm660_l15: regulator-l15 {
 			regulator-min-microvolt = <1650000>;
 			regulator-max-microvolt = <2950000>;
 			status = "okay";
@@ -285,7 +285,7 @@
 
 	rpm-regulator-ldoa17 {
 		status = "okay";
-		pmfalcon_l17: regulator-l17 {
+		pm660_l17: regulator-l17 {
 			regulator-min-microvolt = <1650000>;
 			regulator-max-microvolt = <2950000>;
 			status = "okay";
@@ -294,15 +294,15 @@
 
 	rpm-regulator-ldoa19 {
 		status = "okay";
-		pmfalcon_l19: regulator-l19 {
+		pm660_l19: regulator-l19 {
 			regulator-min-microvolt = <3200000>;
 			regulator-max-microvolt = <3400000>;
 			status = "okay";
 		};
 
-		pmfalcon_l19_pin_ctrl: regulator-l19-pin-ctrl {
+		pm660_l19_pin_ctrl: regulator-l19-pin-ctrl {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pmfalcon_l19_pin_ctrl";
+			regulator-name = "pm660_l19_pin_ctrl";
 			qcom,set = <3>;
 			regulator-min-microvolt = <3200000>;
 			regulator-max-microvolt = <3400000>;
@@ -315,7 +315,7 @@
 
 	rpm-regulator-ldob1 {
 		status = "okay";
-		pm2falcon_l1: regulator-l1 {
+		pm660l_l1: regulator-l1 {
 			regulator-min-microvolt = <800000>;
 			regulator-max-microvolt = <925000>;
 			status = "okay";
@@ -324,7 +324,7 @@
 
 	rpm-regulator-ldob2 {
 		status = "okay";
-		pm2falcon_l2: regulator-l2 {
+		pm660l_l2: regulator-l2 {
 			regulator-min-microvolt = <350000>;
 			regulator-max-microvolt = <3100000>;
 			status = "okay";
@@ -333,7 +333,7 @@
 
 	rpm-regulator-ldob3 {
 		status = "okay";
-		pm2falcon_l3: regulator-l3 {
+		pm660l_l3: regulator-l3 {
 			regulator-min-microvolt = <1710000>;
 			regulator-max-microvolt = <3600000>;
 			status = "okay";
@@ -342,7 +342,7 @@
 
 	rpm-regulator-ldob4 {
 		status = "okay";
-		pm2falcon_l4: regulator-l4 {
+		pm660l_l4: regulator-l4 {
 			regulator-min-microvolt = <1700000>;
 			regulator-max-microvolt = <2950000>;
 			status = "okay";
@@ -351,7 +351,7 @@
 
 	rpm-regulator-ldob5 {
 		status = "okay";
-		pm2falcon_l5: regulator-l5 {
+		pm660l_l5: regulator-l5 {
 			regulator-min-microvolt = <1721000>;
 			regulator-max-microvolt = <3600000>;
 			status = "okay";
@@ -360,7 +360,7 @@
 
 	rpm-regulator-ldob6 {
 		status = "okay";
-		pm2falcon_l6: regulator-l6 {
+		pm660l_l6: regulator-l6 {
 			regulator-min-microvolt = <1700000>;
 			regulator-max-microvolt = <3300000>;
 			status = "okay";
@@ -369,7 +369,7 @@
 
 	rpm-regulator-ldob7 {
 		status = "okay";
-		pm2falcon_l7: regulator-l7 {
+		pm660l_l7: regulator-l7 {
 			regulator-min-microvolt = <2700000>;
 			regulator-max-microvolt = <3125000>;
 			status = "okay";
@@ -378,19 +378,19 @@
 
 	rpm-regulator-ldob8 {
 		status = "okay";
-		pm2falcon_l8: regulator-l8 {
+		pm660l_l8: regulator-l8 {
 			regulator-min-microvolt = <3200000>;
 			regulator-max-microvolt = <3400000>;
 			status = "okay";
 		};
 	};
 
-	/* PM2FALCON L9 = VDD_SSC_CX supply */
+	/* PM660L L9 = VDD_SSC_CX supply */
 	rpm-regulator-ldob9 {
 		status = "okay";
-		pm2falcon_l9_level: regulator-l9-level {
+		pm660l_l9_level: regulator-l9-level {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_l9_level";
+			regulator-name = "pm660l_l9_level";
 			qcom,set = <3>;
 			regulator-min-microvolt =
 				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
@@ -399,9 +399,9 @@
 			qcom,use-voltage-level;
 		};
 
-		pm2falcon_l9_floor_level: regulator-l9-floor-level {
+		pm660l_l9_floor_level: regulator-l9-floor-level {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_l9_floor_level";
+			regulator-name = "pm660l_l9_floor_level";
 			qcom,set = <3>;
 			regulator-min-microvolt =
 				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
@@ -412,12 +412,12 @@
 		};
 	};
 
-	/* PM2FALCON L10 = VDD_SSC_MX supply */
+	/* PM660L L10 = VDD_SSC_MX supply */
 	rpm-regulator-ldob10 {
 		status = "okay";
-		pm2falcon_l10_level: regulator-l10-level {
+		pm660l_l10_level: regulator-l10-level {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_l10_level";
+			regulator-name = "pm660l_l10_level";
 			qcom,set = <3>;
 			regulator-min-microvolt =
 				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
@@ -426,9 +426,9 @@
 			qcom,use-voltage-level;
 		};
 
-		pm2falcon_l10_floor_level: regulator-l10-floor-level {
+		pm660l_l10_floor_level: regulator-l10-floor-level {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_l10_floor_level";
+			regulator-name = "pm660l_l10_floor_level";
 			qcom,set = <3>;
 			regulator-min-microvolt =
 				<RPM_SMD_REGULATOR_LEVEL_RETENTION>;
@@ -441,33 +441,33 @@
 
 	rpm-regulator-bobb {
 		status = "okay";
-		pm2falcon_bob: regulator-bob {
+		pm660l_bob: regulator-bob {
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3600000>;
 			status = "okay";
 		};
 
-		pm2falcon_bob_pin1: regulator-bob-pin1 {
+		pm660l_bob_pin1: regulator-bob-pin1 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_bob_pin1";
+			regulator-name = "pm660l_bob_pin1";
 			qcom,set = <3>;
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3600000>;
 			qcom,use-pin-ctrl-voltage1;
 		};
 
-		pm2falcon_bob_pin2: regulator-bob-pin2 {
+		pm660l_bob_pin2: regulator-bob-pin2 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_bob_pin2";
+			regulator-name = "pm660l_bob_pin2";
 			qcom,set = <3>;
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3600000>;
 			qcom,use-pin-ctrl-voltage2;
 		};
 
-		pm2falcon_bob_pin3: regulator-bob-pin3 {
+		pm660l_bob_pin3: regulator-bob-pin3 {
 			compatible = "qcom,rpm-smd-regulator";
-			regulator-name = "pm2falcon_bob_pin3";
+			regulator-name = "pm660l_bob_pin3";
 			qcom,set = <3>;
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3600000>;
@@ -476,7 +476,7 @@
 	};
 };
 
-&pmfalcon_charger {
+&pm660_charger {
 	smb2_vbus: qcom,smb2-vbus {
 		regulator-name = "smb2-vbus";
 	};
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts b/arch/arm/boot/dts/qcom/sdm660-rumi.dts
index c371ddeda563..f5759b6af7fd 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts
+++ b/arch/arm/boot/dts/qcom/sdm660-rumi.dts
@@ -13,12 +13,12 @@
 
 /dts-v1/;
 
-#include "msmfalcon.dtsi"
-#include "msmfalcon-pinctrl.dtsi"
+#include "sdm660.dtsi"
+#include "sdm660-pinctrl.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON RUMI";
-	compatible = "qcom,msmfalcon-rumi", "qcom,msmfalcon", "qcom,rumi";
+	model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L RUMI";
+	compatible = "qcom,sdm660-rumi", "qcom,sdm660", "qcom,rumi";
 	qcom,board-id = <15 0>;
 	qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
 			<0x0001001b 0x0201011a 0x0 0x0>;
@@ -69,12 +69,12 @@
 
 &sdhc_1 {
 	/* device core power supply */
-	vdd-supply = <&pm2falcon_l4>;
+	vdd-supply = <&pm660l_l4>;
 	qcom,vdd-voltage-level = <2950000 2950000>;
 	qcom,vdd-current-level = <200 570000>;
 
 	/* device communication power supply */
-	vdd-io-supply = <&pmfalcon_l8>;
+	vdd-io-supply = <&pm660_l8>;
 	qcom,vdd-io-always-on;
 	qcom,vdd-io-lpm-sup;
 	qcom,vdd-io-voltage-level = <1800000 1800000>;
@@ -98,11 +98,11 @@
 	clock-output-names = "gcc_clocks";
 };
 
-&pmfalcon_charger {
+&pm660_charger {
 	status = "disabled";
 };
 
-&pmfalcon_fg {
+&pm660_fg {
 	status = "disabled";
 };
 
@@ -111,7 +111,7 @@
 	clock-output-names = "gfx_clocks";
 };
 
-&pmfalcon_pdphy {
+&pm660_pdphy {
 	status = "disabled";
 };
 
@@ -121,9 +121,9 @@
 };
 
 &ufsphy1 {
-	vdda-phy-supply = <&pm2falcon_l1>;
-	vdda-pll-supply = <&pmfalcon_l10>;
-	vddp-ref-clk-supply = <&pmfalcon_l1>;
+	vdda-phy-supply = <&pm660l_l1>;
+	vdda-pll-supply = <&pm660_l10>;
+	vddp-ref-clk-supply = <&pm660_l1>;
 	vdda-phy-max-microamp = <51400>;
 	vdda-pll-max-microamp = <14200>;
 	vddp-ref-clk-max-microamp = <100>;
@@ -133,8 +133,8 @@
 &ufs1 {
 	vdd-hba-supply = <&gdsc_ufs>;
 	vdd-hba-fixed-regulator;
-	vcc-supply = <&pm2falcon_l4>;
-	vccq2-supply = <&pmfalcon_l8>;
+	vcc-supply = <&pm660l_l4>;
+	vccq2-supply = <&pm660_l8>;
 	vcc-max-microamp = <500000>;
 	vccq2-max-microamp = <600000>;
 	qcom,disable-lpm;
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-sim.dts b/arch/arm/boot/dts/qcom/sdm660-sim.dts
index 596aae818fab..bb896cb7437d 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-sim.dts
+++ b/arch/arm/boot/dts/qcom/sdm660-sim.dts
@@ -13,12 +13,12 @@
 
 /dts-v1/;
 
-#include "msmfalcon.dtsi"
-#include "msmfalcon-pinctrl.dtsi"
+#include "sdm660.dtsi"
+#include "sdm660-pinctrl.dtsi"
 
 / {
-	model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON SIM";
-	compatible = "qcom,msmfalcon-sim", "qcom,msmfalcon", "qcom,sim";
+	model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L SIM";
+	compatible = "qcom,sdm660-sim", "qcom,sdm660", "qcom,sim";
 	qcom,board-id = <16 0>;
 	qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
 			<0x0001001b 0x0201011a 0x0 0x0>;
@@ -53,12 +53,12 @@
 
 &sdhc_1 {
 	/* device core power supply */
-	vdd-supply = <&pm2falcon_l4>;
+	vdd-supply = <&pm660l_l4>;
 	qcom,vdd-voltage-level = <2950000 2950000>;
 	qcom,vdd-current-level = <200 570000>;
 
 	/* device communication power supply */
-	vdd-io-supply = <&pmfalcon_l8>;
+	vdd-io-supply = <&pm660_l8>;
 	qcom,vdd-io-always-on;
 	qcom,vdd-io-lpm-sup;
 	qcom,vdd-io-voltage-level = <1800000 1800000>;
@@ -77,22 +77,22 @@
 	status = "ok";
 };
 
-&pmfalcon_charger {
+&pm660_charger {
 	status = "disabled";
 };
 
-&pmfalcon_fg {
+&pm660_fg {
 	status = "disabled";
 };
 
-&pmfalcon_pdphy {
+&pm660_pdphy {
 	status = "disabled";
 };
 
 &ufsphy1 {
-	vdda-phy-supply = <&pm2falcon_l1>;
-	vdda-pll-supply = <&pmfalcon_l10>;
-	vddp-ref-clk-supply = <&pmfalcon_l1>;
+	vdda-phy-supply = <&pm660l_l1>;
+	vdda-pll-supply = <&pm660_l10>;
+	vddp-ref-clk-supply = <&pm660_l1>;
 	vdda-phy-max-microamp = <51400>;
 	vdda-pll-max-microamp = <14200>;
 	vddp-ref-clk-max-microamp = <100>;
@@ -103,8 +103,8 @@
 &ufs1 {
 	vdd-hba-supply = <&gdsc_ufs>;
 	vdd-hba-fixed-regulator;
-	vcc-supply = <&pm2falcon_l4>;
-	vccq2-supply = <&pmfalcon_l8>;
+	vcc-supply = <&pm660l_l4>;
+	vccq2-supply = <&pm660_l8>;
 	vcc-max-microamp = <500000>;
 	vccq2-max-microamp = <600000>;
 	status = "ok";
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-smp2p.dtsi b/arch/arm/boot/dts/qcom/sdm660-smp2p.dtsi
index b43fae954ec2..b43fae954ec2 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-smp2p.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-smp2p.dtsi
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-vidc.dtsi b/arch/arm/boot/dts/qcom/sdm660-vidc.dtsi
index 9a9c96f5181d..8e5561da5deb 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-vidc.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-vidc.dtsi
@@ -12,8 +12,8 @@
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/msm/msm-bus-ids.h>
-#include <dt-bindings/clock/qcom,gcc-msmfalcon.h>
-#include <dt-bindings/clock/qcom,mmcc-msmfalcon.h>
+#include <dt-bindings/clock/qcom,gcc-sdm660.h>
+#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
 #include <dt-bindings/clock/qcom,rpmcc.h>
 
 
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-wcd.dtsi b/arch/arm/boot/dts/qcom/sdm660-wcd.dtsi
index 006bf0175874..006bf0175874 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-wcd.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-wcd.dtsi
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-wsa881x.dtsi b/arch/arm/boot/dts/qcom/sdm660-wsa881x.dtsi
index 123f922facdd..a71aa7ded60b 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon-wsa881x.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-wsa881x.dtsi
@@ -10,7 +10,7 @@
  * GNU General Public License for more details.
  */
 
-#include "msmfalcon-wcd.dtsi"
+#include "sdm660-wcd.dtsi"
 
 &slim_aud {
 	tasha_codec {
diff --git a/arch/arm/boot/dts/qcom/msmfalcon.dtsi b/arch/arm/boot/dts/qcom/sdm660.dtsi
index b57e7d033c70..856608e4e47a 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660.dtsi
@@ -11,17 +11,17 @@
  */
 
 #include "skeleton64.dtsi"
-#include <dt-bindings/clock/qcom,gcc-msmfalcon.h>
-#include <dt-bindings/clock/qcom,gpu-msmfalcon.h>
-#include <dt-bindings/clock/qcom,mmcc-msmfalcon.h>
+#include <dt-bindings/clock/qcom,gcc-sdm660.h>
+#include <dt-bindings/clock/qcom,gpu-sdm660.h>
+#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
 #include <dt-bindings/clock/qcom,rpmcc.h>
 #include <dt-bindings/clock/audio-ext-clk.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
 
 / {
-	model = "Qualcomm Technologies, Inc. MSM FALCON";
-	compatible = "qcom,msmfalcon";
+	model = "Qualcomm Technologies, Inc. SDM 660";
+	compatible = "qcom,sdm660";
 	qcom,msm-id = <317 0x0>;
 	interrupt-parent = <&intc>;
 
@@ -327,10 +327,10 @@
 
 	bluetooth: bt_wcn3990 {
 		compatible = "qca,wcn3990";
-		qca,bt-vdd-core-supply = <&pmfalcon_l9_pin_ctrl>;
-		qca,bt-vdd-pa-supply = <&pmfalcon_l6_pin_ctrl>;
-		qca,bt-vdd-ldo-supply = <&pmfalcon_l19_pin_ctrl>;
-		qca,bt-chip-pwd-supply = <&pm2falcon_bob_pin1>;
+		qca,bt-vdd-core-supply = <&pm660_l9_pin_ctrl>;
+		qca,bt-vdd-pa-supply = <&pm660_l6_pin_ctrl>;
+		qca,bt-vdd-ldo-supply = <&pm660_l19_pin_ctrl>;
+		qca,bt-chip-pwd-supply = <&pm660l_bob_pin1>;
 		clocks = <&clock_rpmcc RPM_RF_CLK1>;
 		clock-names = "rf_clk1";
 
@@ -345,8 +345,8 @@
 	};
 };
 
-#include "msmfalcon-smp2p.dtsi"
-#include "msmfalcon-coresight.dtsi"
+#include "sdm660-smp2p.dtsi"
+#include "sdm660-coresight.dtsi"
 &soc {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -532,7 +532,7 @@
 	};
 
 	tsens: tsens@10ad000 {
-		compatible = "qcom,msmfalcon-tsens";
+		compatible = "qcom,sdm660-tsens";
 		reg = <0x10ad000 0x2000>,
 			<0x784240 0x1000>;
 		reg-names = "tsens_physical", "tsens_eeprom_physical";
@@ -628,7 +628,7 @@
 		};
 		sensor_information14: qcom,sensor-information-14 {
 			qcom,sensor-type =  "alarm";
-			qcom,sensor-name = "pmfalcon_tz";
+			qcom,sensor-name = "pm660_tz";
 			qcom,scaling-factor = <1000>;
 		};
 		sensor_information15: qcom,sensor-information-15 {
@@ -703,7 +703,7 @@
 		qcom,vdd-restriction-temp = <5>;
 		qcom,vdd-restriction-temp-hysteresis = <10>;
 
-		vdd-dig-supply = <&pm2falcon_s3_floor_level>;
+		vdd-dig-supply = <&pm660l_s3_floor_level>;
 		vdd-gfx-supply = <&gfx_vreg_corner>;
 
 		qcom,vdd-dig-rstr{
@@ -881,34 +881,34 @@
 	};
 
 	clock_rpmcc: qcom,rpmcc {
-		compatible = "qcom,rpmcc-msmfalcon", "qcom,rpmcc";
+		compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
 		#clock-cells = <1>;
 	};
 
 	clock_gcc: clock-controller@100000 {
-		compatible = "qcom,gcc-msmfalcon", "syscon";
+		compatible = "qcom,gcc-sdm660", "syscon";
 		reg = <0x100000 0x94000>;
-		vdd_dig-supply = <&pm2falcon_s3_level>;
-		vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>;
+		vdd_dig-supply = <&pm660l_s3_level>;
+		vdd_dig_ao-supply = <&pm660l_s3_level_ao>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
 
 	clock_mmss: clock-controller@c8c0000 {
-		compatible = "qcom,mmcc-msmfalcon";
+		compatible = "qcom,mmcc-sdm660";
 		reg = <0xc8c0000 0x40000>;
-		vdd_mx_mmss-supply = <&pm2falcon_s5_level>;
-		vdd_dig_mmss-supply = <&pm2falcon_s3_level>;
-		vdda-supply = <&pmfalcon_l10>;
+		vdd_mx_mmss-supply = <&pm660l_s5_level>;
+		vdd_dig_mmss-supply = <&pm660l_s3_level>;
+		vdda-supply = <&pm660_l10>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
 
 	clock_gfx: clock-controller@5065000 {
-		compatible = "qcom,gpucc-msmfalcon";
+		compatible = "qcom,gpucc-sdm660";
 		reg = <0x5065000 0x10000>;
-		vdd_dig_gfx-supply = <&pm2falcon_s3_level>;
-		vdd_mx_gfx-supply = <&pm2falcon_s5_level>;
+		vdd_dig_gfx-supply = <&pm660l_s3_level>;
+		vdd_mx_gfx-supply = <&pm660l_s5_level>;
 		vdd_gfx-supply = <&gfx_vreg_corner>;
 		qcom,gfxfreq-corner =
 			< 0         0>,
@@ -940,7 +940,7 @@
 	};
 
 	clock_debug: qcom,cc-debug@62000 {
-		compatible = "qcom,gcc-debug-msmfalcon";
+		compatible = "qcom,gcc-debug-sdm660";
 		reg = <0x62000 0x4>;
 		reg-names = "dbg_offset";
 		clocks = <&clock_rpmcc  RPM_XO_CLK_SRC>;
@@ -1083,7 +1083,7 @@
 		};
 	};
 
-	clock_cpu: qcom,clk-cpu-falcon@179c0000 {
+	clock_cpu: qcom,clk-cpu-660@179c0000 {
 		compatible = "qcom,clk-cpu-osm";
 		status = "disabled";
 		reg = <0x179c0000 0x4000>, <0x17916000 0x1000>,
@@ -1636,7 +1636,7 @@
 		reg = <0x15700000 0x00100>;
 		interrupts = <0 162 1>;
 
-		vdd_cx-supply = <&pm2falcon_l9_level>;
+		vdd_cx-supply = <&pm660l_l9_level>;
 		qcom,proxy-reg-names = "vdd_cx";
 		qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;
 
@@ -1668,7 +1668,7 @@
 		reg = <0x1a300000 0x00100>;
 		interrupts = <0 518 1>;
 
-		vdd_cx-supply = <&pm2falcon_s3_level>;
+		vdd_cx-supply = <&pm660l_s3_level>;
 		qcom,proxy-reg-names = "vdd_cx";
 		qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;
 
@@ -1725,9 +1725,9 @@
 					 "mnoc_axi_clk";
 
 		interrupts = <0 448 1>;
-		vdd_cx-supply = <&pm2falcon_s3_level>;
+		vdd_cx-supply = <&pm660l_s3_level>;
 		vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
-		vdd_mx-supply = <&pm2falcon_s5_level>;
+		vdd_mx-supply = <&pm660l_s5_level>;
 		vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
 		qcom,firmware-name = "modem";
 		qcom,pil-self-auth;
@@ -1951,7 +1951,7 @@
 	};
 
 	ufsphy1: ufsphy@1da7000 {
-		compatible = "qcom,ufs-phy-qmp-v3-falcon";
+		compatible = "qcom,ufs-phy-qmp-v3-660";
 		reg = <0x1da7000 0xdb8>;
 		reg-names = "phy_mem";
 		#phy-cells = <0>;
@@ -2132,18 +2132,18 @@
 	};
 };
 
-#include "msmfalcon-ion.dtsi"
-#include "msmfalcon-bus.dtsi"
-#include "msm-pmfalcon.dtsi"
-#include "msm-pm2falcon.dtsi"
-#include "msm-pmfalcon-rpm-regulator.dtsi"
-#include "msm-pm2falcon-rpm-regulator.dtsi"
-#include "msmfalcon-regulator.dtsi"
-#include "msm-gdsc-falcon.dtsi"
-#include "msmfalcon-gpu.dtsi"
-#include "msmfalcon-pm.dtsi"
+#include "sdm660-ion.dtsi"
+#include "sdm660-bus.dtsi"
+#include "msm-pm660.dtsi"
+#include "msm-pm660l.dtsi"
+#include "msm-pm660-rpm-regulator.dtsi"
+#include "msm-pm660l-rpm-regulator.dtsi"
+#include "sdm660-regulator.dtsi"
+#include "msm-gdsc-660.dtsi"
+#include "sdm660-gpu.dtsi"
+#include "sdm660-pm.dtsi"
 #include "msm-audio.dtsi"
-#include "msmfalcon-audio.dtsi"
+#include "sdm660-audio.dtsi"
 
 &gdsc_usb30 {
 	status = "ok";
@@ -2219,14 +2219,14 @@
 	status = "ok";
 };
 
-#include "msm-arm-smmu-falcon.dtsi"
-#include "msm-arm-smmu-impl-defs-falcon.dtsi"
-#include "msmfalcon-common.dtsi"
-#include "msmfalcon-blsp.dtsi"
-#include "msmfalcon-camera.dtsi"
-#include "msmfalcon-vidc.dtsi"
+#include "msm-arm-smmu-660.dtsi"
+#include "msm-arm-smmu-impl-defs-660.dtsi"
+#include "sdm660-common.dtsi"
+#include "sdm660-blsp.dtsi"
+#include "sdm660-camera.dtsi"
+#include "sdm660-vidc.dtsi"
 
-&pm2falcon_gpios {
+&pm660l_gpios {
 	/* GPIO 7 for VOL_UP */
 	gpio@c600 {
 		status = "okay";
@@ -2265,7 +2265,7 @@
 
 		vol_up {
 			label = "volume_up";
-			gpios = <&pm2falcon_gpios 7 0x1>;
+			gpios = <&pm660l_gpios 7 0x1>;
 			linux,input-type = <1>;
 			linux,code = <115>;
 			gpio-key,wakeup;
@@ -2274,5 +2274,5 @@
 	};
 };
 
-#include "msmfalcon-mdss.dtsi"
-#include "msmfalcon-mdss-pll.dtsi"
+#include "sdm660-mdss.dtsi"
+#include "sdm660-mdss-pll.dtsi"
diff --git a/arch/arm/configs/msmcortex_defconfig b/arch/arm/configs/msmcortex_defconfig
index 5e9afadeb7ae..c5c7d924aab6 100644
--- a/arch/arm/configs/msmcortex_defconfig
+++ b/arch/arm/configs/msmcortex_defconfig
@@ -38,7 +38,7 @@ CONFIG_MODULE_SIG_SHA512=y
 CONFIG_PARTITION_ADVANCED=y
 # CONFIG_IOSCHED_DEADLINE is not set
 CONFIG_ARCH_QCOM=y
-CONFIG_ARCH_MSMFALCON=y
+CONFIG_ARCH_SDM660=y
 CONFIG_SMP=y
 CONFIG_SCHED_MC=y
 CONFIG_NR_CPUS=8
@@ -289,7 +289,7 @@ CONFIG_SPI_QUP=y
 CONFIG_SPI_SPIDEV=y
 CONFIG_SPMI=y
 CONFIG_PINCTRL_MSM8998=y
-CONFIG_PINCTRL_MSMFALCON=y
+CONFIG_PINCTRL_SDM660=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_QPNP_PIN=y
 CONFIG_APSS_CORE_EA=y
diff --git a/arch/arm/configs/msmfalcon-perf_defconfig b/arch/arm/configs/sdm660-perf_defconfig
index 211ec1c6cabc..76cbdbac479a 100644
--- a/arch/arm/configs/msmfalcon-perf_defconfig
+++ b/arch/arm/configs/sdm660-perf_defconfig
@@ -46,7 +46,7 @@ CONFIG_MODULE_SIG_SHA512=y
 CONFIG_PARTITION_ADVANCED=y
 # CONFIG_IOSCHED_DEADLINE is not set
 CONFIG_ARCH_QCOM=y
-CONFIG_ARCH_MSMFALCON=y
+CONFIG_ARCH_SDM660=y
 CONFIG_ARCH_MSMTRITON=y
 CONFIG_ARM_KERNMEM_PERMS=y
 CONFIG_SMP=y
@@ -315,7 +315,7 @@ CONFIG_SPI=y
 CONFIG_SPI_QUP=y
 CONFIG_SPI_SPIDEV=y
 CONFIG_SPMI=y
-CONFIG_PINCTRL_MSMFALCON=y
+CONFIG_PINCTRL_SDM660=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_QPNP_PIN=y
 CONFIG_POWER_RESET=y
@@ -389,7 +389,7 @@ CONFIG_SND=y
 CONFIG_SND_USB_AUDIO=y
 CONFIG_SND_USB_AUDIO_QMI=y
 CONFIG_SND_SOC=y
-CONFIG_SND_SOC_FALCON=y
+CONFIG_SND_SOC_660=y
 CONFIG_UHID=y
 CONFIG_HID_APPLE=y
 CONFIG_HID_ELECOM=y
@@ -481,7 +481,7 @@ CONFIG_GPIO_USB_DETECT=y
 CONFIG_SEEMP_CORE=y
 CONFIG_USB_BAM=y
 CONFIG_QCOM_CLK_SMD_RPM=y
-CONFIG_MSM_GCC_FALCON=y
+CONFIG_MSM_GCC_660=y
 CONFIG_QCOM_MDSS_PLL=y
 CONFIG_REMOTE_SPINLOCK_MSM=y
 CONFIG_ARM_SMMU=y
diff --git a/arch/arm/configs/msmfalcon_defconfig b/arch/arm/configs/sdm660_defconfig
index 10981157afc3..40614f2b872b 100644
--- a/arch/arm/configs/msmfalcon_defconfig
+++ b/arch/arm/configs/sdm660_defconfig
@@ -46,7 +46,7 @@ CONFIG_MODULE_SIG_SHA512=y
 CONFIG_PARTITION_ADVANCED=y
 # CONFIG_IOSCHED_DEADLINE is not set
 CONFIG_ARCH_QCOM=y
-CONFIG_ARCH_MSMFALCON=y
+CONFIG_ARCH_SDM660=y
 CONFIG_ARCH_MSMTRITON=y
 CONFIG_ARM_KERNMEM_PERMS=y
 CONFIG_SMP=y
@@ -313,7 +313,7 @@ CONFIG_SPI=y
 CONFIG_SPI_QUP=y
 CONFIG_SPI_SPIDEV=y
 CONFIG_SPMI=y
-CONFIG_PINCTRL_MSMFALCON=y
+CONFIG_PINCTRL_SDM660=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_QPNP_PIN=y
 CONFIG_POWER_RESET=y
@@ -391,7 +391,7 @@ CONFIG_SND=y
 CONFIG_SND_USB_AUDIO=y
 CONFIG_SND_USB_AUDIO_QMI=y
 CONFIG_SND_SOC=y
-CONFIG_SND_SOC_FALCON=y
+CONFIG_SND_SOC_660=y
 CONFIG_UHID=y
 CONFIG_HID_APPLE=y
 CONFIG_HID_ELECOM=y
@@ -482,8 +482,8 @@ CONFIG_GPIO_USB_DETECT=y
 CONFIG_SEEMP_CORE=y
 CONFIG_USB_BAM=y
 CONFIG_QCOM_CLK_SMD_RPM=y
-CONFIG_MSM_GPUCC_FALCON=y
-CONFIG_MSM_MMCC_FALCON=y
+CONFIG_MSM_GPUCC_660=y
+CONFIG_MSM_MMCC_660=y
 CONFIG_CLOCK_CPU_OSM=y
 CONFIG_QCOM_MDSS_PLL=y
 CONFIG_REMOTE_SPINLOCK_MSM=y
diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig
index a4fba1af7744..1910acb1cce9 100644
--- a/arch/arm/mach-qcom/Kconfig
+++ b/arch/arm/mach-qcom/Kconfig
@@ -1,8 +1,8 @@
 if ARCH_QCOM
 menu "QCOM SoC Type"
 
-config ARCH_MSMFALCON
-        bool "Enable Support for MSMFALCON"
+config ARCH_SDM660
+        bool "Enable Support for SDM660"
 	select CLKDEV_LOOKUP
 	select HAVE_CLK
 	select HAVE_CLK_PREPARE
@@ -36,7 +36,7 @@ config ARCH_MSMFALCON
 	select GENERIC_IRQ_MIGRATION
 	select MSM_JTAGV8 if CORESIGHT_ETMV4
 	help
-	This enables support for the MSMFALCON chipset. If you do not
+	This enables support for the SDM660 chipset. If you do not
 	wish to build a kernel that runs on this chipset, say 'N' here.
 
 config ARCH_MSMTRITON
diff --git a/arch/arm/mach-qcom/Makefile b/arch/arm/mach-qcom/Makefile
index c5e30fff2b1e..c79ab416701c 100644
--- a/arch/arm/mach-qcom/Makefile
+++ b/arch/arm/mach-qcom/Makefile
@@ -1,4 +1,4 @@
 obj-y			:= board.o
 obj-$(CONFIG_USE_OF) += board-dt.o
-obj-$(CONFIG_ARCH_MSMFALCON) += board-falcon.o
+obj-$(CONFIG_ARCH_SDM660) += board-660.o
 obj-$(CONFIG_SMP)	+= platsmp.o
diff --git a/arch/arm/mach-qcom/board-falcon.c b/arch/arm/mach-qcom/board-660.c
index aec16886308d..f1bf7e08bbac 100644
--- a/arch/arm/mach-qcom/board-falcon.c
+++ b/arch/arm/mach-qcom/board-660.c
@@ -15,21 +15,21 @@
 #include <asm/mach/arch.h>
 #include "board-dt.h"
 
-static const char *msmfalcon_dt_match[] __initconst = {
-	"qcom,msmfalcon",
-	"qcom,apqfalcon",
+static const char *sdm660_dt_match[] __initconst = {
+	"qcom,sdm660",
+	"qcom,sda660",
 	NULL
 };
 
-static void __init msmfalcon_init(void)
+static void __init sdm660_init(void)
 {
 	board_dt_populate(NULL);
 }
 
-DT_MACHINE_START(MSMFALCON_DT,
-	"Qualcomm Technologies, Inc. MSM FALCON (Flattened Device Tree)")
-	.init_machine = msmfalcon_init,
-	.dt_compat = msmfalcon_dt_match,
+DT_MACHINE_START(SDM660_DT,
+	"Qualcomm Technologies, Inc. SDM 660 (Flattened Device Tree)")
+	.init_machine = sdm660_init,
+	.dt_compat = sdm660_dt_match,
 MACHINE_END
 
 static const char *msmtriton_dt_match[] __initconst = {
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 56b7f310ddbc..5d22639491c0 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -86,14 +86,14 @@ config ARCH_MSMHAMSTER
 	  If you do not wish to build a kernel that runs
 	  on this chipset,say 'N' here.
 
-config ARCH_MSMFALCON
-	bool "Enable Support for Qualcomm Technologies Inc MSMFALCON"
+config ARCH_SDM660
+	bool "Enable Support for Qualcomm Technologies Inc SDM660"
 	depends on ARCH_QCOM
 	select COMMON_CLK
 	select COMMON_CLK_QCOM
 	select QCOM_GDSC
 	help
-	  This enables support for the MSMFALCON chipset.
+	  This enables support for the SDM660 chipset.
 	  If you do not wish to build a kernel that runs
 	  on this chipset,say 'N' here.
 
diff --git a/arch/arm64/configs/msmcortex-perf_defconfig b/arch/arm64/configs/msmcortex-perf_defconfig
index 97a082dd4fcd..71d067b27ddd 100644
--- a/arch/arm64/configs/msmcortex-perf_defconfig
+++ b/arch/arm64/configs/msmcortex-perf_defconfig
@@ -308,7 +308,7 @@ CONFIG_SPI_QUP=y
 CONFIG_SPI_SPIDEV=y
 CONFIG_SPMI=y
 CONFIG_PINCTRL_MSM8998=y
-CONFIG_PINCTRL_MSMFALCON=y
+CONFIG_PINCTRL_SDM660=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_QPNP_PIN=y
diff --git a/arch/arm64/configs/msmcortex_defconfig b/arch/arm64/configs/msmcortex_defconfig
index 965a13caaeb5..02b9e08955f6 100644
--- a/arch/arm64/configs/msmcortex_defconfig
+++ b/arch/arm64/configs/msmcortex_defconfig
@@ -311,7 +311,7 @@ CONFIG_SPI_QUP=y
 CONFIG_SPI_SPIDEV=y
 CONFIG_SPMI=y
 CONFIG_PINCTRL_MSM8998=y
-CONFIG_PINCTRL_MSMFALCON=y
+CONFIG_PINCTRL_SDM660=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_QPNP_PIN=y
diff --git a/arch/arm64/configs/msmfalcon-perf_defconfig b/arch/arm64/configs/sdm660-perf_defconfig
index b84168e18478..239debeb6f0b 100644
--- a/arch/arm64/configs/msmfalcon-perf_defconfig
+++ b/arch/arm64/configs/sdm660-perf_defconfig
@@ -46,7 +46,7 @@ CONFIG_MODULE_SIG_FORCE=y
 CONFIG_MODULE_SIG_SHA512=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_ARCH_QCOM=y
-CONFIG_ARCH_MSMFALCON=y
+CONFIG_ARCH_SDM660=y
 CONFIG_ARCH_MSMTRITON=y
 CONFIG_PCI=y
 CONFIG_PCI_MSM=y
@@ -310,7 +310,7 @@ CONFIG_SPI_QUP=y
 CONFIG_SPI_SPIDEV=y
 CONFIG_SPMI=y
 CONFIG_PINCTRL_MSM8998=y
-CONFIG_PINCTRL_MSMFALCON=y
+CONFIG_PINCTRL_SDM660=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_QPNP_PIN=y
@@ -419,7 +419,7 @@ CONFIG_SND_USB_AUDIO=y
 CONFIG_SND_USB_AUDIO_QMI=y
 CONFIG_SND_SOC=y
 CONFIG_SND_SOC_MSM8998=y
-CONFIG_SND_SOC_FALCON=y
+CONFIG_SND_SOC_660=y
 CONFIG_UHID=y
 CONFIG_HID_APPLE=y
 CONFIG_HID_ELECOM=y
@@ -504,8 +504,8 @@ CONFIG_GPIO_USB_DETECT=y
 CONFIG_SEEMP_CORE=y
 CONFIG_USB_BAM=y
 CONFIG_QCOM_CLK_SMD_RPM=y
-CONFIG_MSM_GPUCC_FALCON=y
-CONFIG_MSM_MMCC_FALCON=y
+CONFIG_MSM_GPUCC_660=y
+CONFIG_MSM_MMCC_660=y
 CONFIG_CLOCK_CPU_OSM=y
 CONFIG_QCOM_MDSS_PLL=y
 CONFIG_REMOTE_SPINLOCK_MSM=y
diff --git a/arch/arm64/configs/msmfalcon_defconfig b/arch/arm64/configs/sdm660_defconfig
index ce91e8992b46..c5d93a065e87 100644
--- a/arch/arm64/configs/msmfalcon_defconfig
+++ b/arch/arm64/configs/sdm660_defconfig
@@ -47,7 +47,7 @@ CONFIG_MODULE_SIG_SHA512=y
 CONFIG_PARTITION_ADVANCED=y
 # CONFIG_IOSCHED_DEADLINE is not set
 CONFIG_ARCH_QCOM=y
-CONFIG_ARCH_MSMFALCON=y
+CONFIG_ARCH_SDM660=y
 CONFIG_ARCH_MSMTRITON=y
 CONFIG_PCI=y
 CONFIG_PCI_MSM=y
@@ -312,7 +312,7 @@ CONFIG_SPI=y
 CONFIG_SPI_QUP=y
 CONFIG_SPI_SPIDEV=y
 CONFIG_SPMI=y
-CONFIG_PINCTRL_MSMFALCON=y
+CONFIG_PINCTRL_SDM660=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_QPNP_PIN=y
@@ -421,7 +421,7 @@ CONFIG_SND_USB_AUDIO=y
 CONFIG_SND_USB_AUDIO_QMI=y
 CONFIG_SND_SOC=y
 CONFIG_SND_SOC_MSM8998=y
-CONFIG_SND_SOC_FALCON=y
+CONFIG_SND_SOC_660=y
 CONFIG_UHID=y
 CONFIG_HID_APPLE=y
 CONFIG_HID_ELECOM=y
@@ -513,8 +513,8 @@ CONFIG_GPIO_USB_DETECT=y
 CONFIG_SEEMP_CORE=y
 CONFIG_USB_BAM=y
 CONFIG_QCOM_CLK_SMD_RPM=y
-CONFIG_MSM_GPUCC_FALCON=y
-CONFIG_MSM_MMCC_FALCON=y
+CONFIG_MSM_GPUCC_660=y
+CONFIG_MSM_MMCC_660=y
 CONFIG_CLOCK_CPU_OSM=y
 CONFIG_QCOM_MDSS_PLL=y
 CONFIG_REMOTE_SPINLOCK_MSM=y
diff --git a/drivers/clk/msm/Kconfig b/drivers/clk/msm/Kconfig
index bfb697347ec5..3829f6aec124 100644
--- a/drivers/clk/msm/Kconfig
+++ b/drivers/clk/msm/Kconfig
@@ -7,7 +7,7 @@ config COMMON_CLK_MSM
 	  This support clock controller used by MSM devices which support
 	  global, mmss and gpu clock controller.
 	  Say Y if you want to support the clocks exposed by the MSM on
-	  platforms such as msm8996, msm8998, msmfalcon etc.
+	  platforms such as msm8996, msm8998 etc.
 
 config MSM_CLK_CONTROLLER_V2
 	bool "QTI clock driver"
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index b5dd556b3f96..5a6b62892328 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -153,33 +153,33 @@ config MSM_MMCC_8996
 	  Say Y if you want to support multimedia devices such as display,
 	  graphics, video encode/decode, camera, etc.
 
-config MSM_GCC_FALCON
-	tristate "MSMFALCON Global Clock Controller"
+config MSM_GCC_660
+	tristate "SDM660 Global Clock Controller"
 	select QCOM_GDSC
 	depends on COMMON_CLK_QCOM
 	---help---
 	  Support for the global clock controller on Qualcomm Technologies, Inc
-	  MSMfalcon devices.
+	  SDM660 devices.
 	  Say Y if you want to use peripheral devices such as UART, SPI, I2C,
 	  USB, UFS, SD/eMMC, PCIe, etc.
 
-config MSM_GPUCC_FALCON
-	tristate "MSMFALCON Graphics Clock Controller"
-	select MSM_GCC_FALCON
+config MSM_GPUCC_660
+	tristate "SDM660 Graphics Clock Controller"
+	select MSM_GCC_660
 	depends on COMMON_CLK_QCOM
 	help
 	  Support for the graphics clock controller on Qualcomm Technologies, Inc
-	  MSMfalcon devices.
+	  SDM660 devices.
 	  Say Y if you want to support graphics controller devices which will
 	  be required to enable those device.
 
-config MSM_MMCC_FALCON
-	tristate "MSMFALCON Multimedia Clock Controller"
-	select MSM_GCC_FALCON
+config MSM_MMCC_660
+	tristate "SDM660 Multimedia Clock Controller"
+	select MSM_GCC_660
 	depends on COMMON_CLK_QCOM
 	help
 	  Support for the multimedia clock controller on Qualcomm Technologies, Inc
-	  MSMfalcon devices.
+	  SDM660 devices.
 	  Say Y if you want to support multimedia devices such as display,
 	  video encode/decode, camera, etc.
 
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index a63065c97319..481cda67974b 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -25,12 +25,12 @@ obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
 obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
 obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
 obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o
-obj-$(CONFIG_MSM_GCC_FALCON) += gcc-msmfalcon.o
+obj-$(CONFIG_MSM_GCC_660) += gcc-sdm660.o
 obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
 obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
 obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
-obj-$(CONFIG_MSM_GPUCC_FALCON) += gpucc-msmfalcon.o
-obj-$(CONFIG_MSM_MMCC_FALCON) += mmcc-msmfalcon.o
+obj-$(CONFIG_MSM_GPUCC_660) += gpucc-sdm660.o
+obj-$(CONFIG_MSM_MMCC_660) += mmcc-sdm660.o
 obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
 obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
 obj-$(CONFIG_KRAITCC) += krait-cc.o
diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
index d14c32bffe14..9332e99e642b 100644
--- a/drivers/clk/qcom/clk-smd-rpm.c
+++ b/drivers/clk/qcom/clk-smd-rpm.c
@@ -656,75 +656,75 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8996 = {
 	.num_clks = ARRAY_SIZE(msm8996_clks),
 };
 
-/* msmfalcon */
-DEFINE_CLK_SMD_RPM_BRANCH(msmfalcon, cxo, cxo_a, QCOM_SMD_RPM_MISC_CLK, 0,
+/* sdm660 */
+DEFINE_CLK_SMD_RPM_BRANCH(sdm660, cxo, cxo_a, QCOM_SMD_RPM_MISC_CLK, 0,
 								19200000);
-DEFINE_CLK_SMD_RPM(msmfalcon, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
-DEFINE_CLK_SMD_RPM(msmfalcon, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
-DEFINE_CLK_SMD_RPM(msmfalcon, cnoc_periph_clk, cnoc_periph_a_clk,
+DEFINE_CLK_SMD_RPM(sdm660, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
+DEFINE_CLK_SMD_RPM(sdm660, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
+DEFINE_CLK_SMD_RPM(sdm660, cnoc_periph_clk, cnoc_periph_a_clk,
 						QCOM_SMD_RPM_BUS_CLK, 0);
-DEFINE_CLK_SMD_RPM(msmfalcon, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
-DEFINE_CLK_SMD_RPM(msmfalcon, mmssnoc_axi_clk, mmssnoc_axi_a_clk,
+DEFINE_CLK_SMD_RPM(sdm660, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
+DEFINE_CLK_SMD_RPM(sdm660, mmssnoc_axi_clk, mmssnoc_axi_a_clk,
 						   QCOM_SMD_RPM_MMAXI_CLK, 0);
-DEFINE_CLK_SMD_RPM(msmfalcon, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
-DEFINE_CLK_SMD_RPM(msmfalcon, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
-DEFINE_CLK_SMD_RPM(msmfalcon, aggre2_noc_clk, aggre2_noc_a_clk,
+DEFINE_CLK_SMD_RPM(sdm660, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
+DEFINE_CLK_SMD_RPM(sdm660, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
+DEFINE_CLK_SMD_RPM(sdm660, aggre2_noc_clk, aggre2_noc_a_clk,
 						QCOM_SMD_RPM_AGGR_CLK, 2);
-DEFINE_CLK_SMD_RPM_QDSS(msmfalcon, qdss_clk, qdss_a_clk,
+DEFINE_CLK_SMD_RPM_QDSS(sdm660, qdss_clk, qdss_a_clk,
 						QCOM_SMD_RPM_MISC_CLK, 1);
-DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, rf_clk1, rf_clk1_ao, 4);
-DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, div_clk1, div_clk1_ao, 0xb);
-DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, ln_bb_clk1, ln_bb_clk1_ao, 0x1);
-DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, ln_bb_clk2, ln_bb_clk2_ao, 0x2);
-DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, ln_bb_clk3, ln_bb_clk3_ao, 0x3);
-
-DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, rf_clk1_pin, rf_clk1_ao_pin, 4);
-DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk1_pin,
+DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, rf_clk1, rf_clk1_ao, 4);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, div_clk1, div_clk1_ao, 0xb);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk1, ln_bb_clk1_ao, 0x1);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk2, ln_bb_clk2_ao, 0x2);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_ao, 0x3);
+
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, rf_clk1_pin, rf_clk1_ao_pin, 4);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk1_pin,
 							ln_bb_clk1_pin_ao, 0x1);
-DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk2_pin,
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk2_pin,
 							ln_bb_clk2_pin_ao, 0x2);
-DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk3_pin,
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin,
 							ln_bb_clk3_pin_ao, 0x3);
 
-static struct clk_hw *msmfalcon_clks[] = {
-	[RPM_XO_CLK_SRC]	= &msmfalcon_cxo.hw,
-	[RPM_XO_A_CLK_SRC]	= &msmfalcon_cxo_a.hw,
-	[RPM_SNOC_CLK]		= &msmfalcon_snoc_clk.hw,
-	[RPM_SNOC_A_CLK]	= &msmfalcon_snoc_a_clk.hw,
-	[RPM_BIMC_CLK]		= &msmfalcon_bimc_clk.hw,
-	[RPM_BIMC_A_CLK]	= &msmfalcon_bimc_a_clk.hw,
-	[RPM_QDSS_CLK]		= &msmfalcon_qdss_clk.hw,
-	[RPM_QDSS_A_CLK]	= &msmfalcon_qdss_a_clk.hw,
-	[RPM_RF_CLK1]		= &msmfalcon_rf_clk1.hw,
-	[RPM_RF_CLK1_A]		= &msmfalcon_rf_clk1_ao.hw,
-	[RPM_RF_CLK1_PIN]	= &msmfalcon_rf_clk1_pin.hw,
-	[RPM_RF_CLK1_A_PIN]	= &msmfalcon_rf_clk1_ao_pin.hw,
-	[RPM_AGGR2_NOC_CLK]	= &msmfalcon_aggre2_noc_clk.hw,
-	[RPM_AGGR2_NOC_A_CLK]	= &msmfalcon_aggre2_noc_a_clk.hw,
-	[RPM_CNOC_CLK]		= &msmfalcon_cnoc_clk.hw,
-	[RPM_CNOC_A_CLK]	= &msmfalcon_cnoc_a_clk.hw,
-	[RPM_IPA_CLK]		= &msmfalcon_ipa_clk.hw,
-	[RPM_IPA_A_CLK]		= &msmfalcon_ipa_a_clk.hw,
-	[RPM_CE1_CLK]		= &msmfalcon_ce1_clk.hw,
-	[RPM_CE1_A_CLK]		= &msmfalcon_ce1_a_clk.hw,
-	[RPM_DIV_CLK1]		= &msmfalcon_div_clk1.hw,
-	[RPM_DIV_CLK1_AO]	= &msmfalcon_div_clk1_ao.hw,
-	[RPM_LN_BB_CLK1]	= &msmfalcon_ln_bb_clk1.hw,
-	[RPM_LN_BB_CLK1]	= &msmfalcon_ln_bb_clk1_ao.hw,
-	[RPM_LN_BB_CLK1_PIN]	= &msmfalcon_ln_bb_clk1_pin.hw,
-	[RPM_LN_BB_CLK1_PIN_AO]	= &msmfalcon_ln_bb_clk1_pin_ao.hw,
-	[RPM_LN_BB_CLK2]	= &msmfalcon_ln_bb_clk2.hw,
-	[RPM_LN_BB_CLK2_AO]	= &msmfalcon_ln_bb_clk2_ao.hw,
-	[RPM_LN_BB_CLK2_PIN]	= &msmfalcon_ln_bb_clk2_pin.hw,
-	[RPM_LN_BB_CLK2_PIN_AO] = &msmfalcon_ln_bb_clk2_pin_ao.hw,
-	[RPM_LN_BB_CLK3]	= &msmfalcon_ln_bb_clk3.hw,
-	[RPM_LN_BB_CLK3_AO]	= &msmfalcon_ln_bb_clk3_ao.hw,
-	[RPM_LN_BB_CLK3_PIN]	= &msmfalcon_ln_bb_clk3_pin.hw,
-	[RPM_LN_BB_CLK3_PIN_AO] = &msmfalcon_ln_bb_clk3_pin_ao.hw,
-	[RPM_CNOC_PERIPH_CLK]	= &msmfalcon_cnoc_periph_clk.hw,
-	[RPM_CNOC_PERIPH_A_CLK] = &msmfalcon_cnoc_periph_a_clk.hw,
-	[MMSSNOC_AXI_CLK]	= &msmfalcon_mmssnoc_axi_clk.hw,
-	[MMSSNOC_AXI_A_CLK]	= &msmfalcon_mmssnoc_axi_a_clk.hw,
+static struct clk_hw *sdm660_clks[] = {
+	[RPM_XO_CLK_SRC]	= &sdm660_cxo.hw,
+	[RPM_XO_A_CLK_SRC]	= &sdm660_cxo_a.hw,
+	[RPM_SNOC_CLK]		= &sdm660_snoc_clk.hw,
+	[RPM_SNOC_A_CLK]	= &sdm660_snoc_a_clk.hw,
+	[RPM_BIMC_CLK]		= &sdm660_bimc_clk.hw,
+	[RPM_BIMC_A_CLK]	= &sdm660_bimc_a_clk.hw,
+	[RPM_QDSS_CLK]		= &sdm660_qdss_clk.hw,
+	[RPM_QDSS_A_CLK]	= &sdm660_qdss_a_clk.hw,
+	[RPM_RF_CLK1]		= &sdm660_rf_clk1.hw,
+	[RPM_RF_CLK1_A]		= &sdm660_rf_clk1_ao.hw,
+	[RPM_RF_CLK1_PIN]	= &sdm660_rf_clk1_pin.hw,
+	[RPM_RF_CLK1_A_PIN]	= &sdm660_rf_clk1_ao_pin.hw,
+	[RPM_AGGR2_NOC_CLK]	= &sdm660_aggre2_noc_clk.hw,
+	[RPM_AGGR2_NOC_A_CLK]	= &sdm660_aggre2_noc_a_clk.hw,
+	[RPM_CNOC_CLK]		= &sdm660_cnoc_clk.hw,
+	[RPM_CNOC_A_CLK]	= &sdm660_cnoc_a_clk.hw,
+	[RPM_IPA_CLK]		= &sdm660_ipa_clk.hw,
+	[RPM_IPA_A_CLK]		= &sdm660_ipa_a_clk.hw,
+	[RPM_CE1_CLK]		= &sdm660_ce1_clk.hw,
+	[RPM_CE1_A_CLK]		= &sdm660_ce1_a_clk.hw,
+	[RPM_DIV_CLK1]		= &sdm660_div_clk1.hw,
+	[RPM_DIV_CLK1_AO]	= &sdm660_div_clk1_ao.hw,
+	[RPM_LN_BB_CLK1]	= &sdm660_ln_bb_clk1.hw,
+	[RPM_LN_BB_CLK1]	= &sdm660_ln_bb_clk1_ao.hw,
+	[RPM_LN_BB_CLK1_PIN]	= &sdm660_ln_bb_clk1_pin.hw,
+	[RPM_LN_BB_CLK1_PIN_AO]	= &sdm660_ln_bb_clk1_pin_ao.hw,
+	[RPM_LN_BB_CLK2]	= &sdm660_ln_bb_clk2.hw,
+	[RPM_LN_BB_CLK2_AO]	= &sdm660_ln_bb_clk2_ao.hw,
+	[RPM_LN_BB_CLK2_PIN]	= &sdm660_ln_bb_clk2_pin.hw,
+	[RPM_LN_BB_CLK2_PIN_AO] = &sdm660_ln_bb_clk2_pin_ao.hw,
+	[RPM_LN_BB_CLK3]	= &sdm660_ln_bb_clk3.hw,
+	[RPM_LN_BB_CLK3_AO]	= &sdm660_ln_bb_clk3_ao.hw,
+	[RPM_LN_BB_CLK3_PIN]	= &sdm660_ln_bb_clk3_pin.hw,
+	[RPM_LN_BB_CLK3_PIN_AO] = &sdm660_ln_bb_clk3_pin_ao.hw,
+	[RPM_CNOC_PERIPH_CLK]	= &sdm660_cnoc_periph_clk.hw,
+	[RPM_CNOC_PERIPH_A_CLK] = &sdm660_cnoc_periph_a_clk.hw,
+	[MMSSNOC_AXI_CLK]	= &sdm660_mmssnoc_axi_clk.hw,
+	[MMSSNOC_AXI_A_CLK]	= &sdm660_mmssnoc_axi_a_clk.hw,
 
 	/* Voter Clocks */
 	[BIMC_MSMBUS_CLK]	= &bimc_msmbus_clk.hw,
@@ -746,16 +746,16 @@ static struct clk_hw *msmfalcon_clks[] = {
 	[CNOC_PERIPH_KEEPALIVE_A_CLK] = &cnoc_periph_keepalive_a_clk.hw,
 };
 
-static const struct rpm_smd_clk_desc rpm_clk_msmfalcon = {
-	.clks = msmfalcon_clks,
+static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {
+	.clks = sdm660_clks,
 	.num_rpm_clks = RPM_CNOC_PERIPH_A_CLK,
-	.num_clks = ARRAY_SIZE(msmfalcon_clks),
+	.num_clks = ARRAY_SIZE(sdm660_clks),
 };
 
 static const struct of_device_id rpm_smd_clk_match_table[] = {
 	{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916},
 	{ .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996},
-	{ .compatible = "qcom,rpmcc-msmfalcon", .data = &rpm_clk_msmfalcon},
+	{ .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
@@ -766,21 +766,21 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)
 	struct clk *clk;
 	struct rpm_cc *rcc;
 	struct clk_onecell_data *data;
-	int ret, is_8996 = 0, is_falcon = 0;
+	int ret, is_8996 = 0, is_660 = 0;
 	size_t num_clks, i;
 	struct clk_hw **hw_clks;
 	const struct rpm_smd_clk_desc *desc;
 
 	is_8996 = of_device_is_compatible(pdev->dev.of_node,
 						"qcom,rpmcc-msm8996");
-	is_falcon = of_device_is_compatible(pdev->dev.of_node,
-						"qcom,rpmcc-msmfalcon");
+	is_660 = of_device_is_compatible(pdev->dev.of_node,
+						"qcom,rpmcc-sdm660");
 	if (is_8996) {
 		ret = clk_vote_bimc(&msm8996_bimc_clk.hw, INT_MAX);
 		if (ret < 0)
 			return ret;
-	} else if (is_falcon) {
-		ret = clk_vote_bimc(&msmfalcon_bimc_clk.hw, INT_MAX);
+	} else if (is_660) {
+		ret = clk_vote_bimc(&sdm660_bimc_clk.hw, INT_MAX);
 		if (ret < 0)
 			return ret;
 	}
@@ -849,8 +849,8 @@ static int rpm_smd_clk_probe(struct platform_device *pdev)
 		clk_prepare_enable(pnoc_keepalive_a_clk.hw.clk);
 
 		clk_prepare_enable(mmssnoc_a_clk_cpu_vote.hw.clk);
-	} else if (is_falcon) {
-		clk_prepare_enable(msmfalcon_cxo_a.hw.clk);
+	} else if (is_660) {
+		clk_prepare_enable(sdm660_cxo_a.hw.clk);
 
 		/* Hold an active set vote for the cnoc_periph resource */
 		clk_set_rate(cnoc_periph_keepalive_a_clk.hw.clk, 19200000);
diff --git a/drivers/clk/qcom/gcc-msmfalcon.c b/drivers/clk/qcom/gcc-sdm660.c
index 1e1c871ef22c..da4c6e8797d7 100644
--- a/drivers/clk/qcom/gcc-msmfalcon.c
+++ b/drivers/clk/qcom/gcc-sdm660.c
@@ -23,7 +23,7 @@
 #include <linux/of_device.h>
 #include <linux/regmap.h>
 #include <linux/reset-controller.h>
-#include <dt-bindings/clock/qcom,gcc-msmfalcon.h>
+#include <dt-bindings/clock/qcom,gcc-sdm660.h>
 
 #include "clk-alpha-pll.h"
 #include "clk-branch.h"
@@ -32,7 +32,7 @@
 #include "clk-regmap.h"
 #include "clk-rcg.h"
 #include "reset.h"
-#include "vdd-level-falcon.h"
+#include "vdd-level-660.h"
 
 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
 
@@ -2580,7 +2580,7 @@ static struct clk_fixed_factor gcc_ce1_axi_m_clk = {
 	},
 };
 
-struct clk_hw *gcc_msmfalcon_hws[] = {
+struct clk_hw *gcc_sdm660_hws[] = {
 	[GCC_XO] =      &xo.hw,
 	[GCC_GPLL0_EARLY_DIV] = &gpll0_out_early_div.hw,
 	[GCC_GPLL1_EARLY_DIV] = &gpll1_out_early_div.hw,
@@ -2588,7 +2588,7 @@ struct clk_hw *gcc_msmfalcon_hws[] = {
 	[GCC_CE1_AXI_M_CLK] = &gcc_ce1_axi_m_clk.hw,
 };
 
-static struct clk_regmap *gcc_falcon_clocks[] = {
+static struct clk_regmap *gcc_660_clocks[] = {
 	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
 	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
 	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
@@ -2728,7 +2728,7 @@ static struct clk_regmap *gcc_falcon_clocks[] = {
 					&hlos2_vote_turing_adsp_smmu_clk.clkr,
 };
 
-static const struct qcom_reset_map gcc_falcon_resets[] = {
+static const struct qcom_reset_map gcc_660_resets[] = {
 	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
 	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
 	[GCC_UFS_BCR] = { 0x75000 },
@@ -2740,7 +2740,7 @@ static const struct qcom_reset_map gcc_falcon_resets[] = {
 	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
 };
 
-static const struct regmap_config gcc_falcon_regmap_config = {
+static const struct regmap_config gcc_660_regmap_config = {
 	.reg_bits	= 32,
 	.reg_stride	= 4,
 	.val_bits	= 32,
@@ -2748,28 +2748,28 @@ static const struct regmap_config gcc_falcon_regmap_config = {
 	.fast_io	= true,
 };
 
-static const struct qcom_cc_desc gcc_falcon_desc = {
-	.config = &gcc_falcon_regmap_config,
-	.clks = gcc_falcon_clocks,
-	.num_clks = ARRAY_SIZE(gcc_falcon_clocks),
-	.hwclks = gcc_msmfalcon_hws,
-	.num_hwclks = ARRAY_SIZE(gcc_msmfalcon_hws),
-	.resets = gcc_falcon_resets,
-	.num_resets = ARRAY_SIZE(gcc_falcon_resets),
+static const struct qcom_cc_desc gcc_660_desc = {
+	.config = &gcc_660_regmap_config,
+	.clks = gcc_660_clocks,
+	.num_clks = ARRAY_SIZE(gcc_660_clocks),
+	.hwclks = gcc_sdm660_hws,
+	.num_hwclks = ARRAY_SIZE(gcc_sdm660_hws),
+	.resets = gcc_660_resets,
+	.num_resets = ARRAY_SIZE(gcc_660_resets),
 };
 
-static const struct of_device_id gcc_falcon_match_table[] = {
-	{ .compatible = "qcom,gcc-msmfalcon" },
+static const struct of_device_id gcc_660_match_table[] = {
+	{ .compatible = "qcom,gcc-sdm660" },
 	{ }
 };
-MODULE_DEVICE_TABLE(of, gcc_falcon_match_table);
+MODULE_DEVICE_TABLE(of, gcc_660_match_table);
 
-static int gcc_falcon_probe(struct platform_device *pdev)
+static int gcc_660_probe(struct platform_device *pdev)
 {
 	int ret = 0;
 	struct regmap *regmap;
 
-	regmap = qcom_cc_map(pdev, &gcc_falcon_desc);
+	regmap = qcom_cc_map(pdev, &gcc_660_desc);
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
 
@@ -2795,7 +2795,7 @@ static int gcc_falcon_probe(struct platform_device *pdev)
 		return PTR_ERR(vdd_dig_ao.regulator[0]);
 	}
 
-	ret = qcom_cc_really_probe(pdev, &gcc_falcon_desc, regmap);
+	ret = qcom_cc_really_probe(pdev, &gcc_660_desc, regmap);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed to register GCC clocks\n");
 		return ret;
@@ -2816,25 +2816,25 @@ static int gcc_falcon_probe(struct platform_device *pdev)
 	return ret;
 }
 
-static struct platform_driver gcc_falcon_driver = {
-	.probe		= gcc_falcon_probe,
+static struct platform_driver gcc_660_driver = {
+	.probe		= gcc_660_probe,
 	.driver		= {
-		.name	= "gcc-msmfalcon",
-		.of_match_table = gcc_falcon_match_table,
+		.name	= "gcc-sdm660",
+		.of_match_table = gcc_660_match_table,
 	},
 };
 
-static int __init gcc_falcon_init(void)
+static int __init gcc_660_init(void)
 {
-	return platform_driver_register(&gcc_falcon_driver);
+	return platform_driver_register(&gcc_660_driver);
 }
-core_initcall_sync(gcc_falcon_init);
+core_initcall_sync(gcc_660_init);
 
-static void __exit gcc_falcon_exit(void)
+static void __exit gcc_660_exit(void)
 {
-	platform_driver_unregister(&gcc_falcon_driver);
+	platform_driver_unregister(&gcc_660_driver);
 }
-module_exit(gcc_falcon_exit);
+module_exit(gcc_660_exit);
 
 /* Debug Mux for measure */
 static struct measure_clk_data debug_mux_priv = {
@@ -3210,11 +3210,11 @@ static struct clk_debug_mux gcc_debug_mux = {
 };
 
 static const struct of_device_id clk_debug_match_table[] = {
-	{ .compatible = "qcom,gcc-debug-msmfalcon" },
+	{ .compatible = "qcom,gcc-debug-sdm660" },
 	{}
 };
 
-static int clk_debug_falcon_probe(struct platform_device *pdev)
+static int clk_debug_660_probe(struct platform_device *pdev)
 {
 	struct resource *res;
 	struct clk *clk;
@@ -3307,16 +3307,16 @@ static int clk_debug_falcon_probe(struct platform_device *pdev)
 }
 
 static struct platform_driver clk_debug_driver = {
-	.probe = clk_debug_falcon_probe,
+	.probe = clk_debug_660_probe,
 	.driver = {
-		.name = "gcc-debug-msmfalcon",
+		.name = "gcc-debug-sdm660",
 		.of_match_table = clk_debug_match_table,
 		.owner = THIS_MODULE,
 	},
 };
 
-int __init clk_debug_falcon_init(void)
+int __init clk_debug_660_init(void)
 {
 	return platform_driver_register(&clk_debug_driver);
 }
-fs_initcall(clk_debug_falcon_init);
+fs_initcall(clk_debug_660_init);
diff --git a/drivers/clk/qcom/gpucc-msmfalcon.c b/drivers/clk/qcom/gpucc-sdm660.c
index 9b7dd907a6f3..b16b17451c76 100644
--- a/drivers/clk/qcom/gpucc-msmfalcon.c
+++ b/drivers/clk/qcom/gpucc-sdm660.c
@@ -22,7 +22,7 @@
 #include <linux/of_device.h>
 #include <linux/regmap.h>
 #include <linux/reset-controller.h>
-#include <dt-bindings/clock/qcom,gpu-msmfalcon.h>
+#include <dt-bindings/clock/qcom,gpu-sdm660.h>
 
 #include "clk-alpha-pll.h"
 #include "common.h"
@@ -30,7 +30,7 @@
 #include "clk-pll.h"
 #include "clk-rcg.h"
 #include "clk-branch.h"
-#include "vdd-level-falcon.h"
+#include "vdd-level-660.h"
 
 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
 #define F_GFX(f, s, h, m, n, sf) { (f), (s), (2 * (h) - 1), (m), (n), (sf) }
@@ -316,7 +316,7 @@ static struct clk_branch gpucc_rbcpr_clk = {
 	},
 };
 
-static struct clk_regmap *gpucc_falcon_clocks[] = {
+static struct clk_regmap *gpucc_660_clocks[] = {
 	[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
 	[GPU_PLL0_PLL] = &gpu_pll0_pll_out_main.clkr,
 	[GPU_PLL1_PLL] = &gpu_pll1_pll_out_main.clkr,
@@ -328,7 +328,7 @@ static struct clk_regmap *gpucc_falcon_clocks[] = {
 	[RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
 };
 
-static const struct regmap_config gpucc_falcon_regmap_config = {
+static const struct regmap_config gpucc_660_regmap_config = {
 	.reg_bits	= 32,
 	.reg_stride	= 4,
 	.val_bits	= 32,
@@ -336,18 +336,18 @@ static const struct regmap_config gpucc_falcon_regmap_config = {
 	.fast_io	= true,
 };
 
-static const struct qcom_cc_desc gpucc_falcon_desc = {
-	.config = &gpucc_falcon_regmap_config,
-	.clks = gpucc_falcon_clocks,
-	.num_clks = ARRAY_SIZE(gpucc_falcon_clocks),
+static const struct qcom_cc_desc gpucc_660_desc = {
+	.config = &gpucc_660_regmap_config,
+	.clks = gpucc_660_clocks,
+	.num_clks = ARRAY_SIZE(gpucc_660_clocks),
 };
 
-static const struct of_device_id gpucc_falcon_match_table[] = {
-	{ .compatible = "qcom,gpucc-msmfalcon" },
+static const struct of_device_id gpucc_660_match_table[] = {
+	{ .compatible = "qcom,gpucc-sdm660" },
 	{ .compatible = "qcom,gpucc-msmtriton" },
 	{ }
 };
-MODULE_DEVICE_TABLE(of, gpucc_falcon_match_table);
+MODULE_DEVICE_TABLE(of, gpucc_660_match_table);
 
 static int of_get_fmax_vdd_class(struct platform_device *pdev,
 		struct clk_hw *hw, char *prop_name, u32 index)
@@ -407,13 +407,13 @@ static int of_get_fmax_vdd_class(struct platform_device *pdev,
 	return 0;
 }
 
-static int gpucc_falcon_probe(struct platform_device *pdev)
+static int gpucc_660_probe(struct platform_device *pdev)
 {
 	int ret = 0;
 	struct regmap *regmap;
 	bool is_triton = 0;
 
-	regmap = qcom_cc_map(pdev, &gpucc_falcon_desc);
+	regmap = qcom_cc_map(pdev, &gpucc_660_desc);
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
 
@@ -464,7 +464,7 @@ static int gpucc_falcon_probe(struct platform_device *pdev)
 	clk_alpha_pll_configure(&gpu_pll1_pll_out_main, regmap,
 							&gpu_pll0_config);
 
-	ret = qcom_cc_really_probe(pdev, &gpucc_falcon_desc, regmap);
+	ret = qcom_cc_really_probe(pdev, &gpucc_660_desc, regmap);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed to register GPUCC clocks\n");
 		return ret;
@@ -477,22 +477,22 @@ static int gpucc_falcon_probe(struct platform_device *pdev)
 	return ret;
 }
 
-static struct platform_driver gpucc_falcon_driver = {
-	.probe		= gpucc_falcon_probe,
+static struct platform_driver gpucc_660_driver = {
+	.probe		= gpucc_660_probe,
 	.driver		= {
-		.name	= "gpucc-msmfalcon",
-		.of_match_table = gpucc_falcon_match_table,
+		.name	= "gpucc-sdm660",
+		.of_match_table = gpucc_660_match_table,
 	},
 };
 
-static int __init gpucc_falcon_init(void)
+static int __init gpucc_660_init(void)
 {
-	return platform_driver_register(&gpucc_falcon_driver);
+	return platform_driver_register(&gpucc_660_driver);
 }
-core_initcall_sync(gpucc_falcon_init);
+core_initcall_sync(gpucc_660_init);
 
-static void __exit gpucc_falcon_exit(void)
+static void __exit gpucc_660_exit(void)
 {
-	platform_driver_unregister(&gpucc_falcon_driver);
+	platform_driver_unregister(&gpucc_660_driver);
 }
-module_exit(gpucc_falcon_exit);
+module_exit(gpucc_660_exit);
diff --git a/drivers/clk/qcom/mdss/mdss-pll.c b/drivers/clk/qcom/mdss/mdss-pll.c
index b51ab4f21561..f356be38a25c 100644
--- a/drivers/clk/qcom/mdss/mdss-pll.c
+++ b/drivers/clk/qcom/mdss/mdss-pll.c
@@ -133,9 +133,9 @@ static int mdss_pll_resource_parse(struct platform_device *pdev,
 		pll_res->pll_interface_type = MDSS_DSI_PLL_8996;
 		pll_res->target_id = MDSS_PLL_TARGET_8996;
 		pll_res->revision = 2;
-	} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_msmfalcon")) {
+	} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_sdm660")) {
 		pll_res->pll_interface_type = MDSS_DSI_PLL_8996;
-		pll_res->target_id = MDSS_PLL_TARGET_MSMFALCON;
+		pll_res->target_id = MDSS_PLL_TARGET_SDM660;
 		pll_res->revision = 2;
 	} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8998")) {
 		pll_res->pll_interface_type = MDSS_DSI_PLL_8998;
@@ -382,7 +382,7 @@ static const struct of_device_id mdss_pll_dt_match[] = {
 	{.compatible = "qcom,mdss_hdmi_pll_8996_v3_1p8"},
 	{.compatible = "qcom,mdss_dp_pll_8998"},
 	{.compatible = "qcom,mdss_hdmi_pll_8998"},
-	{.compatible = "qcom,mdss_dsi_pll_msmfalcon"},
+	{.compatible = "qcom,mdss_dsi_pll_sdm660"},
 	{}
 };
 
diff --git a/drivers/clk/qcom/mdss/mdss-pll.h b/drivers/clk/qcom/mdss/mdss-pll.h
index 01664eaa815c..e0e62a0f379b 100644
--- a/drivers/clk/qcom/mdss/mdss-pll.h
+++ b/drivers/clk/qcom/mdss/mdss-pll.h
@@ -51,7 +51,7 @@ enum {
 
 enum {
 	MDSS_PLL_TARGET_8996,
-	MDSS_PLL_TARGET_MSMFALCON,
+	MDSS_PLL_TARGET_SDM660,
 };
 
 #define DFPS_MAX_NUM_OF_FRAME_RATES 20
diff --git a/drivers/clk/qcom/mmcc-msmfalcon.c b/drivers/clk/qcom/mmcc-sdm660.c
index 59dbebd825fd..daece455454c 100644
--- a/drivers/clk/qcom/mmcc-msmfalcon.c
+++ b/drivers/clk/qcom/mmcc-sdm660.c
@@ -21,7 +21,7 @@
 #include <linux/clk-provider.h>
 #include <linux/regmap.h>
 #include <linux/reset-controller.h>
-#include <dt-bindings/clock/qcom,mmcc-msmfalcon.h>
+#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
 
 #include "clk-alpha-pll.h"
 #include "clk-branch.h"
@@ -32,7 +32,7 @@
 #include "clk-regmap-divider.h"
 #include "clk-voter.h"
 #include "reset.h"
-#include "vdd-level-falcon.h"
+#include "vdd-level-660.h"
 
 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
 #define F_SLEW(f, s, h, m, n, src_freq) { (f), (s), (2 * (h) - 1), (m), (n), \
@@ -2816,12 +2816,12 @@ static struct clk_branch mmss_video_subcore0_clk = {
 	},
 };
 
-struct clk_hw *mmcc_msmfalcon_hws[] = {
+struct clk_hw *mmcc_sdm660_hws[] = {
 	[MMSS_CAMSS_JPEG0_VOTE_CLK] = &mmss_camss_jpeg0_vote_clk.hw,
 	[MMSS_CAMSS_JPEG0_DMA_VOTE_CLK] = &mmss_camss_jpeg0_dma_vote_clk.hw,
 };
 
-static struct clk_regmap *mmcc_falcon_clocks[] = {
+static struct clk_regmap *mmcc_660_clocks[] = {
 	[AHB_CLK_SRC] = &ahb_clk_src.clkr,
 	[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
 	[BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
@@ -2954,11 +2954,11 @@ static struct clk_regmap *mmcc_falcon_clocks[] = {
 	[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
 };
 
-static const struct qcom_reset_map mmcc_falcon_resets[] = {
+static const struct qcom_reset_map mmcc_660_resets[] = {
 	[CAMSS_MICRO_BCR] = { 0x3490 },
 };
 
-static const struct regmap_config mmcc_falcon_regmap_config = {
+static const struct regmap_config mmcc_660_regmap_config = {
 	.reg_bits	= 32,
 	.reg_stride	= 4,
 	.val_bits	= 32,
@@ -2966,28 +2966,28 @@ static const struct regmap_config mmcc_falcon_regmap_config = {
 	.fast_io	= true,
 };
 
-static const struct qcom_cc_desc mmcc_falcon_desc = {
-	.config = &mmcc_falcon_regmap_config,
-	.clks = mmcc_falcon_clocks,
-	.num_clks = ARRAY_SIZE(mmcc_falcon_clocks),
-	.hwclks = mmcc_msmfalcon_hws,
-	.num_hwclks = ARRAY_SIZE(mmcc_msmfalcon_hws),
-	.resets = mmcc_falcon_resets,
-	.num_resets = ARRAY_SIZE(mmcc_falcon_resets),
+static const struct qcom_cc_desc mmcc_660_desc = {
+	.config = &mmcc_660_regmap_config,
+	.clks = mmcc_660_clocks,
+	.num_clks = ARRAY_SIZE(mmcc_660_clocks),
+	.hwclks = mmcc_sdm660_hws,
+	.num_hwclks = ARRAY_SIZE(mmcc_sdm660_hws),
+	.resets = mmcc_660_resets,
+	.num_resets = ARRAY_SIZE(mmcc_660_resets),
 };
 
-static const struct of_device_id mmcc_falcon_match_table[] = {
-	{ .compatible = "qcom,mmcc-msmfalcon" },
+static const struct of_device_id mmcc_660_match_table[] = {
+	{ .compatible = "qcom,mmcc-sdm660" },
 	{ }
 };
-MODULE_DEVICE_TABLE(of, mmcc_falcon_match_table);
+MODULE_DEVICE_TABLE(of, mmcc_660_match_table);
 
-static int mmcc_falcon_probe(struct platform_device *pdev)
+static int mmcc_660_probe(struct platform_device *pdev)
 {
 	int ret = 0;
 	struct regmap *regmap;
 
-	regmap = qcom_cc_map(pdev, &mmcc_falcon_desc);
+	regmap = qcom_cc_map(pdev, &mmcc_660_desc);
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
 
@@ -3024,7 +3024,7 @@ static int mmcc_falcon_probe(struct platform_device *pdev)
 	clk_alpha_pll_configure(&mmpll8_pll_out_main, regmap, &mmpll8_config);
 	clk_alpha_pll_configure(&mmpll10_pll_out_main, regmap, &mmpll10_config);
 
-	ret = qcom_cc_really_probe(pdev, &mmcc_falcon_desc, regmap);
+	ret = qcom_cc_really_probe(pdev, &mmcc_660_desc, regmap);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed to register MMSS clocks\n");
 		return ret;
@@ -3035,22 +3035,22 @@ static int mmcc_falcon_probe(struct platform_device *pdev)
 	return ret;
 }
 
-static struct platform_driver mmcc_falcon_driver = {
-	.probe		= mmcc_falcon_probe,
+static struct platform_driver mmcc_660_driver = {
+	.probe		= mmcc_660_probe,
 	.driver		= {
-		.name	= "mmcc-msmfalcon",
-		.of_match_table = mmcc_falcon_match_table,
+		.name	= "mmcc-sdm660",
+		.of_match_table = mmcc_660_match_table,
 	},
 };
 
-static int __init mmcc_falcon_init(void)
+static int __init mmcc_660_init(void)
 {
-	return platform_driver_register(&mmcc_falcon_driver);
+	return platform_driver_register(&mmcc_660_driver);
 }
-core_initcall_sync(mmcc_falcon_init);
+core_initcall_sync(mmcc_660_init);
 
-static void __exit mmcc_falcon_exit(void)
+static void __exit mmcc_660_exit(void)
 {
-	platform_driver_unregister(&mmcc_falcon_driver);
+	platform_driver_unregister(&mmcc_660_driver);
 }
-module_exit(mmcc_falcon_exit);
+module_exit(mmcc_660_exit);
diff --git a/drivers/clk/qcom/vdd-level-falcon.h b/drivers/clk/qcom/vdd-level-660.h
index 75567dbe2329..f98a96033ea9 100644
--- a/drivers/clk/qcom/vdd-level-falcon.h
+++ b/drivers/clk/qcom/vdd-level-660.h
@@ -11,8 +11,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_FALCON_H
-#define __DRIVERS_CLK_QCOM_VDD_LEVEL_FALCON_H
+#ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_660_H
+#define __DRIVERS_CLK_QCOM_VDD_LEVEL_660_H
 
 #include <linux/regulator/rpm-smd-regulator.h>
 #include <linux/regulator/consumer.h>
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 11d88df37d31..d45df18a7019 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -372,18 +372,18 @@ config CRYPTO_DEV_QCRYPTO
 
 config CRYPTO_DEV_QCOM_MSM_QCE
         tristate "Qualcomm Crypto Engine (QCE) module"
-        select  CRYPTO_DEV_QCE50 if ARCH_APQ8084 || ARCH_MSM8916 || ARCH_MSM8994 || ARCH_MSM8996 || ARCH_MSM8992 || ARCH_MSMTITANIUM || ARCH_MSM8909 || ARCH_MSM8998 || ARCH_MSMFALCON || ARCH_MSMTRITON
+        select  CRYPTO_DEV_QCE50 if ARCH_APQ8084 || ARCH_MSM8916 || ARCH_MSM8994 || ARCH_MSM8996 || ARCH_MSM8992 || ARCH_MSMTITANIUM || ARCH_MSM8909 || ARCH_MSM8998 || ARCH_SDM660 || ARCH_MSMTRITON
         default n
         help
           This driver supports Qualcomm Crypto Engine in MSM7x30, MSM8660
           MSM8x55, MSM8960, MSM9615, MSM8916, MSM8994, MSM8996, FSM9900,
-		  MSMTITANINUM, APQ8084, MSM8998, MSMFALCON and MSMTRITON.
+		  MSMTITANINUM, APQ8084, MSM8998, SDM660 and MSMTRITON.
 
           To compile this driver as a module, choose M here: the
           For MSM7x30 MSM8660 and MSM8x55 the module is called qce
           For MSM8960, APQ8064 and MSM9615 the module is called qce40
           For MSM8974, MSM8916, MSM8994, MSM8996, MSM8992, MSMTITANIUM,
-		  APQ8084, MSM8998, MSMFALCON and MSMTRITON the module is called qce50.
+		  APQ8084, MSM8998, SDM660 and MSMTRITON the module is called qce50.
 
 config CRYPTO_DEV_QCEDEV
         tristate "QCEDEV Interface to CE module"
@@ -391,7 +391,7 @@ config CRYPTO_DEV_QCEDEV
         help
           This driver supports Qualcomm QCEDEV Crypto in MSM7x30, MSM8660,
           MSM8960, MSM9615, APQ8064, MSM8974, MSM8916, MSM8994, MSM8996,
-          APQ8084, MSM8998, MSMFALCON, MSMTRITON. This exposes the
+          APQ8084, MSM8998, SDM660, MSMTRITON. This exposes the
           interface to the QCE hardware accelerator via IOCTLs.
 
           To compile this driver as a module, choose M here: the
diff --git a/drivers/leds/leds-qpnp-flash-v2.c b/drivers/leds/leds-qpnp-flash-v2.c
index 674ca6161af9..aa59677c4b6a 100644
--- a/drivers/leds/leds-qpnp-flash-v2.c
+++ b/drivers/leds/leds-qpnp-flash-v2.c
@@ -1733,7 +1733,7 @@ static int qpnp_flash_led_parse_common_dt(struct qpnp_flash_led *led,
 	led->pdata->thermal_hysteresis = -EINVAL;
 	rc = of_property_read_u32(node, "qcom,thermal-hysteresis", &val);
 	if (!rc) {
-		if (led->pdata->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE)
+		if (led->pdata->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE)
 			val = THERMAL_HYST_TEMP_TO_VAL(val, 20);
 		else
 			val = THERMAL_HYST_TEMP_TO_VAL(val, 15);
diff --git a/drivers/leds/leds-qpnp-wled.c b/drivers/leds/leds-qpnp-wled.c
index 56750ac8e9e2..718badb16ea1 100644
--- a/drivers/leds/leds-qpnp-wled.c
+++ b/drivers/leds/leds-qpnp-wled.c
@@ -479,7 +479,7 @@ static int qpnp_wled_swire_avdd_config(struct qpnp_wled *wled)
 	u8 val;
 
 	if (wled->pmic_rev_id->pmic_subtype != PMI8998_SUBTYPE &&
-		wled->pmic_rev_id->pmic_subtype != PM2FALCON_SUBTYPE)
+		wled->pmic_rev_id->pmic_subtype != PM660L_SUBTYPE)
 		return 0;
 
 	if (!wled->disp_type_amoled || wled->avdd_mode_spmi)
@@ -1103,11 +1103,11 @@ static bool is_avdd_trim_adjustment_required(struct qpnp_wled *wled)
 	u8 reg = 0;
 
 	/*
-	 * AVDD trim adjustment is not required for pmi8998/pm2falcon and not
+	 * AVDD trim adjustment is not required for pmi8998/pm660l and not
 	 * supported for pmi8994.
 	 */
 	if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE ||
-		wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE ||
+		wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE ||
 		wled->pmic_rev_id->pmic_subtype == PMI8994_SUBTYPE)
 		return false;
 
@@ -1133,7 +1133,7 @@ static int qpnp_wled_gm_config(struct qpnp_wled *wled)
 
 	/* Configure the LOOP COMP GM register */
 	if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE ||
-			wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) {
+			wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) {
 		if (wled->loop_auto_gm_en)
 			reg |= QPNP_WLED_VLOOP_COMP_AUTO_GM_EN;
 
@@ -1179,7 +1179,7 @@ static int qpnp_wled_ovp_config(struct qpnp_wled *wled)
 		return 0;
 
 	if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE ||
-		wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE)
+		wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE)
 		ovp_table = qpnp_wled_ovp_thresholds_pmi8998;
 	else
 		ovp_table = qpnp_wled_ovp_thresholds_pmi8994;
@@ -1264,10 +1264,10 @@ static int qpnp_wled_avdd_mode_config(struct qpnp_wled *wled)
 
 	/*
 	 * At present, configuring the mode to SPMI/SWIRE for controlling
-	 * AVDD voltage is available only in pmi8998/pm2falcon.
+	 * AVDD voltage is available only in pmi8998/pm660l.
 	 */
 	if (wled->pmic_rev_id->pmic_subtype != PMI8998_SUBTYPE &&
-		wled->pmic_rev_id->pmic_subtype != PM2FALCON_SUBTYPE)
+		wled->pmic_rev_id->pmic_subtype != PM660L_SUBTYPE)
 		return 0;
 
 	/* AMOLED_VOUT should be configured for AMOLED */
@@ -1313,7 +1313,7 @@ static int qpnp_wled_ilim_config(struct qpnp_wled *wled)
 		wled->ilim_ma = PMI8994_WLED_ILIM_MIN_MA;
 
 	if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE ||
-		wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) {
+		wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) {
 		ilim_table = qpnp_wled_ilim_settings_pmi8998;
 		if (wled->ilim_ma > PMI8998_WLED_ILIM_MAX_MA)
 			wled->ilim_ma = PMI8998_WLED_ILIM_MAX_MA;
@@ -1352,7 +1352,7 @@ static int qpnp_wled_vref_config(struct qpnp_wled *wled)
 	u8 reg = 0;
 
 	if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE ||
-			wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE)
+			wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE)
 		vref_setting = vref_setting_pmi8998;
 	else
 		vref_setting = vref_setting_pmi8994;
@@ -1420,7 +1420,7 @@ static int qpnp_wled_config(struct qpnp_wled *wled)
 
 	/* Configure auto PFM mode for LCD mode only */
 	if ((wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE ||
-		wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE)
+		wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE)
 		&& !wled->disp_type_amoled) {
 		reg = 0;
 		reg |= wled->lcd_auto_pfm_thresh;
@@ -1563,7 +1563,7 @@ static int qpnp_wled_config(struct qpnp_wled *wled)
 		reg = QPNP_WLED_SINK_TEST5_DIG;
 	} else {
 		reg = QPNP_WLED_SINK_TEST5_HYB;
-		if (wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE)
+		if (wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE)
 			reg |= QPNP_WLED_SINK_TEST5_HVG_PULL_STR_BIT;
 	}
 
@@ -1816,7 +1816,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled)
 
 	if (wled->disp_type_amoled) {
 		if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE ||
-			wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE)
+			wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE)
 			wled->loop_ea_gm =
 				QPNP_WLED_LOOP_GM_DFLT_AMOLED_PMI8998;
 		else
@@ -1836,7 +1836,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled)
 	}
 
 	if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE ||
-		wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) {
+		wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) {
 		wled->loop_auto_gm_en =
 			of_property_read_bool(pdev->dev.of_node,
 					"qcom,loop-auto-gm-en");
@@ -1852,7 +1852,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled)
 	}
 
 	if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE ||
-		wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) {
+		wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) {
 
 		if (wled->pmic_rev_id->rev4 == PMI8998_V2P0_REV4)
 			wled->lcd_auto_pfm_en = false;
@@ -1905,7 +1905,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled)
 	}
 
 	if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE ||
-			wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE)
+			wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE)
 		wled->vref_uv = vref_setting_pmi8998.default_uv;
 	else
 		wled->vref_uv = vref_setting_pmi8994.default_uv;
@@ -1929,7 +1929,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled)
 	}
 
 	if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE ||
-		wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE)
+		wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE)
 		wled->ovp_mv = 29600;
 	else
 		wled->ovp_mv = 29500;
@@ -1943,7 +1943,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled)
 	}
 
 	if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE ||
-		wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) {
+		wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) {
 		if (wled->disp_type_amoled)
 			wled->ilim_ma = PMI8998_AMOLED_DFLT_ILIM_MA;
 		else
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 223339ff119d..e1ef353aa1e1 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -46,7 +46,7 @@ obj-$(CONFIG_PHY_QCOM_UFS) 	+= phy-qcom-ufs-qmp-20nm.o
 obj-$(CONFIG_PHY_QCOM_UFS) 	+= phy-qcom-ufs-qmp-14nm.o
 obj-$(CONFIG_PHY_QCOM_UFS) 	+= phy-qcom-ufs-qmp-v3.o
 obj-$(CONFIG_PHY_QCOM_UFS) 	+= phy-qcom-ufs-qrbtc-v2.o
-obj-$(CONFIG_PHY_QCOM_UFS) 	+= phy-qcom-ufs-qmp-v3-falcon.o
+obj-$(CONFIG_PHY_QCOM_UFS) 	+= phy-qcom-ufs-qmp-v3-660.o
 obj-$(CONFIG_PHY_TUSB1210)		+= phy-tusb1210.o
 obj-$(CONFIG_PHY_BRCMSTB_SATA)		+= phy-brcmstb-sata.o
 obj-$(CONFIG_PHY_PISTACHIO_USB)		+= phy-pistachio-usb.o
diff --git a/drivers/phy/phy-qcom-ufs-qmp-v3-falcon.c b/drivers/phy/phy-qcom-ufs-qmp-v3-660.c
index e88c00e01e0b..a0cb7d0896d1 100644
--- a/drivers/phy/phy-qcom-ufs-qmp-v3-falcon.c
+++ b/drivers/phy/phy-qcom-ufs-qmp-v3-660.c
@@ -12,12 +12,12 @@
  *
  */
 
-#include "phy-qcom-ufs-qmp-v3-falcon.h"
+#include "phy-qcom-ufs-qmp-v3-660.h"
 
-#define UFS_PHY_NAME "ufs_phy_qmp_v3_falcon"
+#define UFS_PHY_NAME "ufs_phy_qmp_v3_660"
 
 static
-int ufs_qcom_phy_qmp_v3_falcon_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
+int ufs_qcom_phy_qmp_v3_660_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
 					bool is_rate_B)
 {
 	int err;
@@ -55,9 +55,9 @@ out:
 	return err;
 }
 
-static int ufs_qcom_phy_qmp_v3_falcon_init(struct phy *generic_phy)
+static int ufs_qcom_phy_qmp_v3_660_init(struct phy *generic_phy)
 {
-	struct ufs_qcom_phy_qmp_v3_falcon *phy = phy_get_drvdata(generic_phy);
+	struct ufs_qcom_phy_qmp_v3_660 *phy = phy_get_drvdata(generic_phy);
 	struct ufs_qcom_phy *phy_common = &phy->common_cfg;
 	int err;
 
@@ -80,7 +80,7 @@ out:
 }
 
 static
-void ufs_qcom_phy_qmp_v3_falcon_power_control(struct ufs_qcom_phy *phy,
+void ufs_qcom_phy_qmp_v3_660_power_control(struct ufs_qcom_phy *phy,
 					 bool power_ctrl)
 {
 	if (!power_ctrl) {
@@ -104,7 +104,7 @@ void ufs_qcom_phy_qmp_v3_falcon_power_control(struct ufs_qcom_phy *phy,
 }
 
 static inline
-void ufs_qcom_phy_qmp_v3_falcon_set_tx_lane_enable(struct ufs_qcom_phy *phy,
+void ufs_qcom_phy_qmp_v3_660_set_tx_lane_enable(struct ufs_qcom_phy *phy,
 						   u32 val)
 {
 	/*
@@ -114,7 +114,7 @@ void ufs_qcom_phy_qmp_v3_falcon_set_tx_lane_enable(struct ufs_qcom_phy *phy,
 }
 
 static
-void ufs_qcom_phy_qmp_v3_falcon_ctrl_rx_linecfg(struct ufs_qcom_phy *phy,
+void ufs_qcom_phy_qmp_v3_660_ctrl_rx_linecfg(struct ufs_qcom_phy *phy,
 						bool ctrl)
 {
 	u32 temp;
@@ -131,7 +131,7 @@ void ufs_qcom_phy_qmp_v3_falcon_ctrl_rx_linecfg(struct ufs_qcom_phy *phy,
 	mb();
 }
 
-static inline void ufs_qcom_phy_qmp_v3_falcon_start_serdes(
+static inline void ufs_qcom_phy_qmp_v3_660_start_serdes(
 					struct ufs_qcom_phy *phy)
 {
 	u32 tmp;
@@ -144,7 +144,7 @@ static inline void ufs_qcom_phy_qmp_v3_falcon_start_serdes(
 	mb();
 }
 
-static int ufs_qcom_phy_qmp_v3_falcon_is_pcs_ready(
+static int ufs_qcom_phy_qmp_v3_660_is_pcs_ready(
 				struct ufs_qcom_phy *phy_common)
 {
 	int err = 0;
@@ -158,7 +158,7 @@ static int ufs_qcom_phy_qmp_v3_falcon_is_pcs_ready(
 	return err;
 }
 
-static void ufs_qcom_phy_qmp_v3_falcon_dbg_register_dump(
+static void ufs_qcom_phy_qmp_v3_660_dbg_register_dump(
 					struct ufs_qcom_phy *phy)
 {
 	ufs_qcom_phy_dump_regs(phy, COM_BASE, COM_SIZE,
@@ -171,30 +171,30 @@ static void ufs_qcom_phy_qmp_v3_falcon_dbg_register_dump(
 					"PHY TX0 Registers ");
 }
 
-struct phy_ops ufs_qcom_phy_qmp_v3_falcon_phy_ops = {
-	.init		= ufs_qcom_phy_qmp_v3_falcon_init,
+struct phy_ops ufs_qcom_phy_qmp_v3_660_phy_ops = {
+	.init		= ufs_qcom_phy_qmp_v3_660_init,
 	.exit		= ufs_qcom_phy_exit,
 	.power_on	= ufs_qcom_phy_power_on,
 	.power_off	= ufs_qcom_phy_power_off,
 	.owner		= THIS_MODULE,
 };
 
-struct ufs_qcom_phy_specific_ops phy_v3_falcon_ops = {
-	.calibrate_phy		= ufs_qcom_phy_qmp_v3_falcon_phy_calibrate,
-	.start_serdes		= ufs_qcom_phy_qmp_v3_falcon_start_serdes,
+struct ufs_qcom_phy_specific_ops phy_v3_660_ops = {
+	.calibrate_phy		= ufs_qcom_phy_qmp_v3_660_phy_calibrate,
+	.start_serdes		= ufs_qcom_phy_qmp_v3_660_start_serdes,
 	.is_physical_coding_sublayer_ready =
-				ufs_qcom_phy_qmp_v3_falcon_is_pcs_ready,
-	.set_tx_lane_enable	= ufs_qcom_phy_qmp_v3_falcon_set_tx_lane_enable,
-	.ctrl_rx_linecfg	= ufs_qcom_phy_qmp_v3_falcon_ctrl_rx_linecfg,
-	.power_control		= ufs_qcom_phy_qmp_v3_falcon_power_control,
-	.dbg_register_dump	= ufs_qcom_phy_qmp_v3_falcon_dbg_register_dump,
+				ufs_qcom_phy_qmp_v3_660_is_pcs_ready,
+	.set_tx_lane_enable	= ufs_qcom_phy_qmp_v3_660_set_tx_lane_enable,
+	.ctrl_rx_linecfg	= ufs_qcom_phy_qmp_v3_660_ctrl_rx_linecfg,
+	.power_control		= ufs_qcom_phy_qmp_v3_660_power_control,
+	.dbg_register_dump	= ufs_qcom_phy_qmp_v3_660_dbg_register_dump,
 };
 
-static int ufs_qcom_phy_qmp_v3_falcon_probe(struct platform_device *pdev)
+static int ufs_qcom_phy_qmp_v3_660_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct phy *generic_phy;
-	struct ufs_qcom_phy_qmp_v3_falcon *phy;
+	struct ufs_qcom_phy_qmp_v3_660 *phy;
 	int err = 0;
 
 	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
@@ -204,8 +204,8 @@ static int ufs_qcom_phy_qmp_v3_falcon_probe(struct platform_device *pdev)
 	}
 
 	generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg,
-				&ufs_qcom_phy_qmp_v3_falcon_phy_ops,
-				&phy_v3_falcon_ops);
+				&ufs_qcom_phy_qmp_v3_660_phy_ops,
+				&phy_v3_660_ops);
 
 	if (!generic_phy) {
 		dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n",
@@ -223,7 +223,7 @@ out:
 	return err;
 }
 
-static int ufs_qcom_phy_qmp_v3_falcon_remove(struct platform_device *pdev)
+static int ufs_qcom_phy_qmp_v3_660_remove(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct phy *generic_phy = to_phy(dev);
@@ -238,23 +238,23 @@ static int ufs_qcom_phy_qmp_v3_falcon_remove(struct platform_device *pdev)
 	return err;
 }
 
-static const struct of_device_id ufs_qcom_phy_qmp_v3_falcon_of_match[] = {
-	{.compatible = "qcom,ufs-phy-qmp-v3-falcon"},
+static const struct of_device_id ufs_qcom_phy_qmp_v3_660_of_match[] = {
+	{.compatible = "qcom,ufs-phy-qmp-v3-660"},
 	{},
 };
-MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_v3_falcon_of_match);
+MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_v3_660_of_match);
 
-static struct platform_driver ufs_qcom_phy_qmp_v3_falcon_driver = {
-	.probe = ufs_qcom_phy_qmp_v3_falcon_probe,
-	.remove = ufs_qcom_phy_qmp_v3_falcon_remove,
+static struct platform_driver ufs_qcom_phy_qmp_v3_660_driver = {
+	.probe = ufs_qcom_phy_qmp_v3_660_probe,
+	.remove = ufs_qcom_phy_qmp_v3_660_remove,
 	.driver = {
-		.of_match_table = ufs_qcom_phy_qmp_v3_falcon_of_match,
-		.name = "ufs_qcom_phy_qmp_v3_falcon",
+		.of_match_table = ufs_qcom_phy_qmp_v3_660_of_match,
+		.name = "ufs_qcom_phy_qmp_v3_660",
 		.owner = THIS_MODULE,
 	},
 };
 
-module_platform_driver(ufs_qcom_phy_qmp_v3_falcon_driver);
+module_platform_driver(ufs_qcom_phy_qmp_v3_660_driver);
 
-MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP v3 falcon");
+MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP v3 660");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/phy/phy-qcom-ufs-qmp-v3-falcon.h b/drivers/phy/phy-qcom-ufs-qmp-v3-660.h
index e64601cc6b22..8d0183d87e20 100644
--- a/drivers/phy/phy-qcom-ufs-qmp-v3-falcon.h
+++ b/drivers/phy/phy-qcom-ufs-qmp-v3-660.h
@@ -12,8 +12,8 @@
  *
  */
 
-#ifndef UFS_QCOM_PHY_QMP_V3_FALCON_H_
-#define UFS_QCOM_PHY_QMP_V3_FALCON_H_
+#ifndef UFS_QCOM_PHY_QMP_V3_660_H_
+#define UFS_QCOM_PHY_QMP_V3_660_H_
 
 #include "phy-qcom-ufs-i.h"
 
@@ -185,14 +185,14 @@
 #define UFS_PHY_RX_LINECFG_DISABLE_BIT		BIT(1)
 
 /*
- * This structure represents the v3 falcon specific phy.
+ * This structure represents the v3 660 specific phy.
  * common_cfg MUST remain the first field in this structure
  * in case extra fields are added. This way, when calling
  * get_ufs_qcom_phy() of generic phy, we can extract the
  * common phy structure (struct ufs_qcom_phy) out of it
  * regardless of the relevant specific phy.
  */
-struct ufs_qcom_phy_qmp_v3_falcon {
+struct ufs_qcom_phy_qmp_v3_660 {
 	struct ufs_qcom_phy common_cfg;
 };
 
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 68546eec7f61..3f9f58f57393 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -112,13 +112,13 @@ config PINCTRL_MSM8996
 	  This is the pinctrl, pinmux, pinconf and gpiolib driver for the
 	  Qualcomm TLMM block found in the Qualcomm MSM8996 platform.
 
-config PINCTRL_MSMFALCON
-	tristate "Qualcomm MSMFALCON pin controller driver"
+config PINCTRL_SDM660
+	tristate "Qualcomm SDM660 pin controller driver"
 	depends on GPIOLIB && OF
 	select PINCTRL_MSM
 	help
 	  This is the pinctrl, pinmux, pinconf and gpiolib driver for the
-	  Qualcomm TLMM block found in the Qualcomm MSMFALCON platform.
+	  Qualcomm TLMM block found in the Qualcomm SDM660 platform.
 
 config PINCTRL_WCD
 	tristate "Qualcomm Technologies, Inc WCD pin controller driver"
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index fa228c7243e2..502b91f455d7 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -14,6 +14,6 @@ obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
 obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
 obj-$(CONFIG_PINCTRL_MSM8996)	+= pinctrl-msm8996.o
 obj-$(CONFIG_PINCTRL_MSM8998)	+= pinctrl-msm8998.o
-obj-$(CONFIG_PINCTRL_MSMFALCON)	+= pinctrl-msmfalcon.o
+obj-$(CONFIG_PINCTRL_SDM660)	+= pinctrl-sdm660.o
 obj-$(CONFIG_PINCTRL_WCD)	+= pinctrl-wcd.o
 obj-$(CONFIG_PINCTRL_LPI)	+= pinctrl-lpi.o
diff --git a/drivers/pinctrl/qcom/pinctrl-msmfalcon.c b/drivers/pinctrl/qcom/pinctrl-sdm660.c
index 91bbce2ce1d1..4dbb4cae2fae 100644
--- a/drivers/pinctrl/qcom/pinctrl-msmfalcon.c
+++ b/drivers/pinctrl/qcom/pinctrl-sdm660.c
@@ -92,7 +92,7 @@
 		.intr_detection_bit = -1,		\
 		.intr_detection_width = -1,		\
 	}
-static const struct pinctrl_pin_desc msmfalcon_pins[] = {
+static const struct pinctrl_pin_desc sdm660_pins[] = {
 	PINCTRL_PIN(0, "GPIO_0"),
 	PINCTRL_PIN(1, "GPIO_1"),
 	PINCTRL_PIN(2, "GPIO_2"),
@@ -341,7 +341,7 @@ static const unsigned int sdc2_cmd_pins[] = { 118 };
 static const unsigned int sdc2_data_pins[] = { 119 };
 static const unsigned int sdc1_rclk_pins[] = { 120 };
 
-enum msmfalcon_functions {
+enum sdm660_functions {
 	msm_mux_blsp_spi1,
 	msm_mux_gpio,
 	msm_mux_blsp_uim1,
@@ -1259,7 +1259,7 @@ static const char * const LCD_PWR_groups[] = {
 	"gpio113",
 };
 
-static const struct msm_function msmfalcon_functions[] = {
+static const struct msm_function sdm660_functions[] = {
 	FUNCTION(blsp_spi1),
 	FUNCTION(gpio),
 	FUNCTION(blsp_uim1),
@@ -1486,7 +1486,7 @@ static const struct msm_function msmfalcon_functions[] = {
 	FUNCTION(LCD_PWR),
 };
 
-static const struct msm_pingroup msmfalcon_groups[] = {
+static const struct msm_pingroup sdm660_groups[] = {
 	PINGROUP(0, SOUTH, blsp_spi1, blsp_uart1, blsp_uim1, tgu_ch0, NA, NA,
 		 qdss_gpio4, atest_gpsadc1, NA),
 	PINGROUP(1, SOUTH, blsp_spi1, blsp_uart1, blsp_uim1, tgu_ch1, NA, NA,
@@ -1675,48 +1675,48 @@ static const struct msm_pingroup msmfalcon_groups[] = {
 	SDC_QDSD_PINGROUP(sdc1_rclk, 0x99a000, 15, 0),
 };
 
-static const struct msm_pinctrl_soc_data msmfalcon_pinctrl = {
-	.pins = msmfalcon_pins,
-	.npins = ARRAY_SIZE(msmfalcon_pins),
-	.functions = msmfalcon_functions,
-	.nfunctions = ARRAY_SIZE(msmfalcon_functions),
-	.groups = msmfalcon_groups,
-	.ngroups = ARRAY_SIZE(msmfalcon_groups),
+static const struct msm_pinctrl_soc_data sdm660_pinctrl = {
+	.pins = sdm660_pins,
+	.npins = ARRAY_SIZE(sdm660_pins),
+	.functions = sdm660_functions,
+	.nfunctions = ARRAY_SIZE(sdm660_functions),
+	.groups = sdm660_groups,
+	.ngroups = ARRAY_SIZE(sdm660_groups),
 	.ngpios = 114,
 };
 
-static int msmfalcon_pinctrl_probe(struct platform_device *pdev)
+static int sdm660_pinctrl_probe(struct platform_device *pdev)
 {
-	return msm_pinctrl_probe(pdev, &msmfalcon_pinctrl);
+	return msm_pinctrl_probe(pdev, &sdm660_pinctrl);
 }
 
-static const struct of_device_id msmfalcon_pinctrl_of_match[] = {
-	{ .compatible = "qcom,msmfalcon-pinctrl", },
+static const struct of_device_id sdm660_pinctrl_of_match[] = {
+	{ .compatible = "qcom,sdm660-pinctrl", },
 	{ },
 };
 
-static struct platform_driver msmfalcon_pinctrl_driver = {
+static struct platform_driver sdm660_pinctrl_driver = {
 	.driver = {
-		.name = "msmfalcon-pinctrl",
+		.name = "sdm660-pinctrl",
 		.owner = THIS_MODULE,
-		.of_match_table = msmfalcon_pinctrl_of_match,
+		.of_match_table = sdm660_pinctrl_of_match,
 	},
-	.probe = msmfalcon_pinctrl_probe,
+	.probe = sdm660_pinctrl_probe,
 	.remove = msm_pinctrl_remove,
 };
 
-static int __init msmfalcon_pinctrl_init(void)
+static int __init sdm660_pinctrl_init(void)
 {
-	return platform_driver_register(&msmfalcon_pinctrl_driver);
+	return platform_driver_register(&sdm660_pinctrl_driver);
 }
-arch_initcall(msmfalcon_pinctrl_init);
+arch_initcall(sdm660_pinctrl_init);
 
-static void __exit msmfalcon_pinctrl_exit(void)
+static void __exit sdm660_pinctrl_exit(void)
 {
-	platform_driver_unregister(&msmfalcon_pinctrl_driver);
+	platform_driver_unregister(&sdm660_pinctrl_driver);
 }
-module_exit(msmfalcon_pinctrl_exit);
+module_exit(sdm660_pinctrl_exit);
 
-MODULE_DESCRIPTION("QTI msmfalcon pinctrl driver");
+MODULE_DESCRIPTION("QTI sdm660 pinctrl driver");
 MODULE_LICENSE("GPL v2");
-MODULE_DEVICE_TABLE(of, msmfalcon_pinctrl_of_match);
+MODULE_DEVICE_TABLE(of, sdm660_pinctrl_of_match);
diff --git a/drivers/platform/msm/qpnp-revid.c b/drivers/platform/msm/qpnp-revid.c
index cfc8093fa3dd..6b5db58f856a 100644
--- a/drivers/platform/msm/qpnp-revid.c
+++ b/drivers/platform/msm/qpnp-revid.c
@@ -56,8 +56,8 @@ static const char *const pmic_names[] = {
 	[PMI8998_SUBTYPE] = "PMI8998",
 	[PM8005_SUBTYPE] = "PM8005",
 	[PM8937_SUBTYPE] = "PM8937",
-	[PM2FALCON_SUBTYPE] = "PM2FALCON",
-	[PMFALCON_SUBTYPE] = "PMFALCON",
+	[PM660L_SUBTYPE] = "PM660L",
+	[PM660_SUBTYPE] = "PM660",
 	[PMI8937_SUBTYPE] = "PMI8937",
 };
 
diff --git a/drivers/power/qcom-charger/qpnp-fg-gen3.c b/drivers/power/qcom-charger/qpnp-fg-gen3.c
index 7c1ece431beb..edd9b9ff28cf 100644
--- a/drivers/power/qcom-charger/qpnp-fg-gen3.c
+++ b/drivers/power/qcom-charger/qpnp-fg-gen3.c
@@ -3157,7 +3157,7 @@ static int fg_parse_dt(struct fg_chip *chip)
 			return -EINVAL;
 		}
 		break;
-	case PMFALCON_SUBTYPE:
+	case PM660_SUBTYPE:
 		chip->sp = pmi8998_v2_sram_params;
 		chip->alg_flags = pmi8998_v2_alg_flags;
 		break;
diff --git a/drivers/power/qcom-charger/qpnp-smb2.c b/drivers/power/qcom-charger/qpnp-smb2.c
index 90e3689086a6..463cbb7cb8ba 100644
--- a/drivers/power/qcom-charger/qpnp-smb2.c
+++ b/drivers/power/qcom-charger/qpnp-smb2.c
@@ -1453,7 +1453,7 @@ static int smb2_setup_wa_flags(struct smb2 *chip)
 		if (pmic_rev_id->rev4 == PMI8998_V2P0_REV4) /* PMI rev 2.0 */
 			chg->wa_flags |= TYPEC_CC2_REMOVAL_WA_BIT;
 		break;
-	case PMFALCON_SUBTYPE:
+	case PM660_SUBTYPE:
 		chip->chg.wa_flags |= BOOST_BACK_WA;
 		break;
 	default:
diff --git a/drivers/regulator/cpr4-mmss-ldo-regulator.c b/drivers/regulator/cpr4-mmss-ldo-regulator.c
index 9fa5c309b02a..69c11a9e5da2 100644
--- a/drivers/regulator/cpr4-mmss-ldo-regulator.c
+++ b/drivers/regulator/cpr4-mmss-ldo-regulator.c
@@ -36,10 +36,10 @@
 
 #include "cpr3-regulator.h"
 
-#define MSMFALCON_MMSS_FUSE_CORNERS	6
+#define SDM660_MMSS_FUSE_CORNERS	6
 
 /**
- * struct cpr4_msmfalcon_mmss_fuses - MMSS specific fuse data for MSMFALCON
+ * struct cpr4_sdm660_mmss_fuses - MMSS specific fuse data for SDM660
  * @init_voltage:	Initial (i.e. open-loop) voltage fuse parameter value
  *			for each fuse corner (raw, not converted to a voltage)
  * @offset_voltage:	The closed-loop voltage margin adjustment fuse parameter
@@ -55,19 +55,19 @@
  *
  * This struct holds the values for all of the fuses read from memory.
  */
-struct cpr4_msmfalcon_mmss_fuses {
-	u64	init_voltage[MSMFALCON_MMSS_FUSE_CORNERS];
-	u64	offset_voltage[MSMFALCON_MMSS_FUSE_CORNERS];
+struct cpr4_sdm660_mmss_fuses {
+	u64	init_voltage[SDM660_MMSS_FUSE_CORNERS];
+	u64	offset_voltage[SDM660_MMSS_FUSE_CORNERS];
 	u64	cpr_fusing_rev;
-	u64	ldo_enable[MSMFALCON_MMSS_FUSE_CORNERS];
+	u64	ldo_enable[SDM660_MMSS_FUSE_CORNERS];
 	u64	ldo_cpr_cl_enable;
 };
 
 /* Fuse combos 0 -  7 map to CPR fusing revision 0 - 7 */
-#define CPR4_MSMFALCON_MMSS_FUSE_COMBO_COUNT	8
+#define CPR4_SDM660_MMSS_FUSE_COMBO_COUNT	8
 
 /*
- * MSMFALCON MMSS fuse parameter locations:
+ * SDM660 MMSS fuse parameter locations:
  *
  * Structs are organized with the following dimensions:
  *	Outer: 0 to 3 for fuse corners from lowest to highest corner
@@ -79,7 +79,7 @@ struct cpr4_msmfalcon_mmss_fuses {
  *		a given parameter may correspond to different fuse rows.
  */
 static const struct cpr3_fuse_param
-msmfalcon_mmss_init_voltage_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = {
+sdm660_mmss_init_voltage_param[SDM660_MMSS_FUSE_CORNERS][2] = {
 	{{65, 39, 43}, {} },
 	{{65, 39, 43}, {} },
 	{{65, 34, 38}, {} },
@@ -88,13 +88,13 @@ msmfalcon_mmss_init_voltage_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = {
 	{{65, 24, 28}, {} },
 };
 
-static const struct cpr3_fuse_param msmfalcon_cpr_fusing_rev_param[] = {
+static const struct cpr3_fuse_param sdm660_cpr_fusing_rev_param[] = {
 	{71, 34, 36},
 	{},
 };
 
 static const struct cpr3_fuse_param
-msmfalcon_mmss_offset_voltage_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = {
+sdm660_mmss_offset_voltage_param[SDM660_MMSS_FUSE_CORNERS][2] = {
 	{{} },
 	{{} },
 	{{} },
@@ -104,7 +104,7 @@ msmfalcon_mmss_offset_voltage_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = {
 };
 
 static const struct cpr3_fuse_param
-msmfalcon_mmss_ldo_enable_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = {
+sdm660_mmss_ldo_enable_param[SDM660_MMSS_FUSE_CORNERS][2] = {
 	{{73, 62, 62}, {} },
 	{{73, 61, 61}, {} },
 	{{73, 60, 60}, {} },
@@ -113,15 +113,15 @@ msmfalcon_mmss_ldo_enable_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = {
 	{{73, 57, 57}, {} },
 };
 
-static const struct cpr3_fuse_param msmfalcon_ldo_cpr_cl_enable_param[] = {
+static const struct cpr3_fuse_param sdm660_ldo_cpr_cl_enable_param[] = {
 	{71, 38, 38},
 	{},
 };
 
-/* Additional MSMFALCON specific data: */
+/* Additional SDM660 specific data: */
 
 /* Open loop voltage fuse reference voltages in microvolts */
-static const int msmfalcon_mmss_fuse_ref_volt[MSMFALCON_MMSS_FUSE_CORNERS] = {
+static const int sdm660_mmss_fuse_ref_volt[SDM660_MMSS_FUSE_CORNERS] = {
 	584000,
 	644000,
 	724000,
@@ -130,36 +130,36 @@ static const int msmfalcon_mmss_fuse_ref_volt[MSMFALCON_MMSS_FUSE_CORNERS] = {
 	924000,
 };
 
-#define MSMFALCON_MMSS_FUSE_STEP_VOLT		10000
-#define MSMFALCON_MMSS_OFFSET_FUSE_STEP_VOLT	10000
-#define MSMFALCON_MMSS_VOLTAGE_FUSE_SIZE	5
+#define SDM660_MMSS_FUSE_STEP_VOLT		10000
+#define SDM660_MMSS_OFFSET_FUSE_STEP_VOLT	10000
+#define SDM660_MMSS_VOLTAGE_FUSE_SIZE	5
 
-#define MSMFALCON_MMSS_CPR_SENSOR_COUNT		11
+#define SDM660_MMSS_CPR_SENSOR_COUNT		11
 
-#define MSMFALCON_MMSS_CPR_CLOCK_RATE		19200000
+#define SDM660_MMSS_CPR_CLOCK_RATE		19200000
 
 /**
- * cpr4_msmfalcon_mmss_read_fuse_data() - load MMSS specific fuse parameter
+ * cpr4_sdm660_mmss_read_fuse_data() - load MMSS specific fuse parameter
  *		values
  * @vreg:		Pointer to the CPR3 regulator
  *
- * This function allocates a cpr4_msmfalcon_mmss_fuses struct, fills it with
+ * This function allocates a cpr4_sdm660_mmss_fuses struct, fills it with
  * values read out of hardware fuses, and finally copies common fuse values
  * into the regulator struct.
  *
  * Return: 0 on success, errno on failure
  */
-static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg)
+static int cpr4_sdm660_mmss_read_fuse_data(struct cpr3_regulator *vreg)
 {
 	void __iomem *base = vreg->thread->ctrl->fuse_base;
-	struct cpr4_msmfalcon_mmss_fuses *fuse;
+	struct cpr4_sdm660_mmss_fuses *fuse;
 	int i, rc;
 
 	fuse = devm_kzalloc(vreg->thread->ctrl->dev, sizeof(*fuse), GFP_KERNEL);
 	if (!fuse)
 		return -ENOMEM;
 
-	rc = cpr3_read_fuse_param(base, msmfalcon_cpr_fusing_rev_param,
+	rc = cpr3_read_fuse_param(base, sdm660_cpr_fusing_rev_param,
 			&fuse->cpr_fusing_rev);
 	if (rc) {
 		cpr3_err(vreg, "Unable to read CPR fusing revision fuse, rc=%d\n",
@@ -168,7 +168,7 @@ static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg)
 	}
 	cpr3_info(vreg, "CPR fusing revision = %llu\n", fuse->cpr_fusing_rev);
 
-	rc = cpr3_read_fuse_param(base, msmfalcon_ldo_cpr_cl_enable_param,
+	rc = cpr3_read_fuse_param(base, sdm660_ldo_cpr_cl_enable_param,
 			&fuse->ldo_cpr_cl_enable);
 	if (rc) {
 		cpr3_err(vreg, "Unable to read ldo cpr closed-loop enable fuse, rc=%d\n",
@@ -176,9 +176,9 @@ static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg)
 		return rc;
 	}
 
-	for (i = 0; i < MSMFALCON_MMSS_FUSE_CORNERS; i++) {
+	for (i = 0; i < SDM660_MMSS_FUSE_CORNERS; i++) {
 		rc = cpr3_read_fuse_param(base,
-			msmfalcon_mmss_init_voltage_param[i],
+			sdm660_mmss_init_voltage_param[i],
 			&fuse->init_voltage[i]);
 		if (rc) {
 			cpr3_err(vreg, "Unable to read fuse-corner %d initial voltage fuse, rc=%d\n",
@@ -187,7 +187,7 @@ static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg)
 		}
 
 		rc = cpr3_read_fuse_param(base,
-			msmfalcon_mmss_offset_voltage_param[i],
+			sdm660_mmss_offset_voltage_param[i],
 			&fuse->offset_voltage[i]);
 		if (rc) {
 			cpr3_err(vreg, "Unable to read fuse-corner %d offset voltage fuse, rc=%d\n",
@@ -196,7 +196,7 @@ static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg)
 		}
 
 		rc = cpr3_read_fuse_param(base,
-			msmfalcon_mmss_ldo_enable_param[i],
+			sdm660_mmss_ldo_enable_param[i],
 			&fuse->ldo_enable[i]);
 		if (rc) {
 			cpr3_err(vreg, "Unable to read fuse-corner %d ldo enable fuse, rc=%d\n",
@@ -206,31 +206,31 @@ static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg)
 	}
 
 	vreg->fuse_combo = fuse->cpr_fusing_rev;
-	if (vreg->fuse_combo >= CPR4_MSMFALCON_MMSS_FUSE_COMBO_COUNT) {
+	if (vreg->fuse_combo >= CPR4_SDM660_MMSS_FUSE_COMBO_COUNT) {
 		cpr3_err(vreg, "invalid CPR fuse combo = %d found, not in range 0 - %d\n",
 			vreg->fuse_combo,
-			CPR4_MSMFALCON_MMSS_FUSE_COMBO_COUNT - 1);
+			CPR4_SDM660_MMSS_FUSE_COMBO_COUNT - 1);
 		return -EINVAL;
 	}
 
 	vreg->cpr_rev_fuse	= fuse->cpr_fusing_rev;
-	vreg->fuse_corner_count	= MSMFALCON_MMSS_FUSE_CORNERS;
+	vreg->fuse_corner_count	= SDM660_MMSS_FUSE_CORNERS;
 	vreg->platform_fuses	= fuse;
 
 	return 0;
 }
 
 /**
- * cpr3_msmfalcon_mmss_calculate_open_loop_voltages() - calculate the open-loop
+ * cpr3_sdm660_mmss_calculate_open_loop_voltages() - calculate the open-loop
  *		voltage for each corner of a CPR3 regulator
  * @vreg:		Pointer to the CPR3 regulator
  *
  * Return: 0 on success, errno on failure
  */
-static int cpr4_msmfalcon_mmss_calculate_open_loop_voltages(
+static int cpr4_sdm660_mmss_calculate_open_loop_voltages(
 			struct cpr3_regulator *vreg)
 {
-	struct cpr4_msmfalcon_mmss_fuses *fuse = vreg->platform_fuses;
+	struct cpr4_sdm660_mmss_fuses *fuse = vreg->platform_fuses;
 	int i, rc = 0;
 	const int *ref_volt;
 	int *fuse_volt;
@@ -240,11 +240,11 @@ static int cpr4_msmfalcon_mmss_calculate_open_loop_voltages(
 	if (!fuse_volt)
 		return -ENOMEM;
 
-	ref_volt = msmfalcon_mmss_fuse_ref_volt;
+	ref_volt = sdm660_mmss_fuse_ref_volt;
 	for (i = 0; i < vreg->fuse_corner_count; i++) {
 		fuse_volt[i] = cpr3_convert_open_loop_voltage_fuse(ref_volt[i],
-			MSMFALCON_MMSS_FUSE_STEP_VOLT, fuse->init_voltage[i],
-			MSMFALCON_MMSS_VOLTAGE_FUSE_SIZE);
+			SDM660_MMSS_FUSE_STEP_VOLT, fuse->init_voltage[i],
+			SDM660_MMSS_VOLTAGE_FUSE_SIZE);
 		cpr3_info(vreg, "fuse_corner[%d] open-loop=%7d uV\n",
 			i, fuse_volt[i]);
 	}
@@ -298,7 +298,7 @@ done:
  */
 static int cpr4_mmss_parse_ldo_mode_data(struct cpr3_regulator *vreg)
 {
-	struct cpr4_msmfalcon_mmss_fuses *fuse = vreg->platform_fuses;
+	struct cpr4_sdm660_mmss_fuses *fuse = vreg->platform_fuses;
 	int i, rc = 0;
 	u32 *ldo_allowed;
 	char *prop_str = "qcom,cpr-corner-allow-ldo-mode";
@@ -341,7 +341,7 @@ done:
  */
 static int cpr4_mmss_parse_corner_operating_mode(struct cpr3_regulator *vreg)
 {
-	struct cpr4_msmfalcon_mmss_fuses *fuse = vreg->platform_fuses;
+	struct cpr4_sdm660_mmss_fuses *fuse = vreg->platform_fuses;
 	int i, rc = 0;
 	u32 *use_closed_loop;
 	char *prop_str = "qcom,cpr-corner-allow-closed-loop";
@@ -476,7 +476,7 @@ static int cpr4_mmss_init_thread(struct cpr3_thread *thread)
 	vreg->ldo_regulator_bypass = BHS_MODE;
 	vreg->ldo_type = CPR3_LDO300;
 
-	rc = cpr4_msmfalcon_mmss_read_fuse_data(vreg);
+	rc = cpr4_sdm660_mmss_read_fuse_data(vreg);
 	if (rc) {
 		cpr3_err(vreg, "unable to read CPR fuse data, rc=%d\n", rc);
 		return rc;
@@ -489,7 +489,7 @@ static int cpr4_mmss_init_thread(struct cpr3_thread *thread)
 		return rc;
 	}
 
-	rc = cpr4_msmfalcon_mmss_calculate_open_loop_voltages(vreg);
+	rc = cpr4_sdm660_mmss_calculate_open_loop_voltages(vreg);
 	if (rc) {
 		cpr3_err(vreg, "unable to calculate open-loop voltages, rc=%d\n",
 			rc);
@@ -548,7 +548,7 @@ static int cpr4_mmss_init_controller(struct cpr3_controller *ctrl)
 		return rc;
 	}
 
-	ctrl->sensor_count = MSMFALCON_MMSS_CPR_SENSOR_COUNT;
+	ctrl->sensor_count = SDM660_MMSS_CPR_SENSOR_COUNT;
 
 	/*
 	 * MMSS only has one thread (0) so the zeroed array does not need
@@ -559,7 +559,7 @@ static int cpr4_mmss_init_controller(struct cpr3_controller *ctrl)
 	if (!ctrl->sensor_owner)
 		return -ENOMEM;
 
-	ctrl->cpr_clock_rate = MSMFALCON_MMSS_CPR_CLOCK_RATE;
+	ctrl->cpr_clock_rate = SDM660_MMSS_CPR_CLOCK_RATE;
 	ctrl->ctrl_type = CPR_CTRL_TYPE_CPR4;
 	ctrl->support_ldo300_vreg = true;
 
@@ -572,7 +572,7 @@ static int cpr4_mmss_init_controller(struct cpr3_controller *ctrl)
 			     &ctrl->step_quot_fixed);
 	ctrl->use_dynamic_step_quot = !ctrl->step_quot_fixed;
 
-	/* iface_clk is optional for msmfalcon */
+	/* iface_clk is optional for sdm660 */
 	ctrl->iface_clk = NULL;
 	ctrl->bus_clk = devm_clk_get(ctrl->dev, "bus_clk");
 	if (IS_ERR(ctrl->bus_clk)) {
@@ -688,7 +688,7 @@ static int cpr4_mmss_regulator_resume(struct platform_device *pdev)
 /* Data corresponds to the SoC revision */
 static const struct of_device_id cpr4_mmss_regulator_match_table[] = {
 	{
-		.compatible = "qcom,cpr4-msmfalcon-mmss-ldo-regulator",
+		.compatible = "qcom,cpr4-sdm660-mmss-ldo-regulator",
 		.data = (void *)NULL,
 	},
 };
diff --git a/drivers/regulator/msm_gfx_ldo.c b/drivers/regulator/msm_gfx_ldo.c
index d2f743b8089a..265ca9ed5258 100644
--- a/drivers/regulator/msm_gfx_ldo.c
+++ b/drivers/regulator/msm_gfx_ldo.c
@@ -152,7 +152,7 @@ static struct ldo_config msm8953_ldo_config[] = {
 	{LDO_MAX_OFFSET,	LDO_MAX_OFFSET},
 };
 
-static struct ldo_config msmfalcon_ldo_config[] = {
+static struct ldo_config sdm660_ldo_config[] = {
 	{LDO_ATEST_REG,		0x00000080},
 	{LDO_CFG0_REG,		0x0100A600},
 	{LDO_CFG1_REG,		0x000000A0},
@@ -185,7 +185,7 @@ static const int msm8953_fuse_ref_volt[MSM8953_LDO_FUSE_CORNERS] = {
 
 enum {
 	MSM8953_SOC_ID,
-	MSMFALCON_SOC_ID,
+	SDM660_SOC_ID,
 };
 
 static int convert_open_loop_voltage_fuse(int ref_volt, int step_volt,
@@ -1516,8 +1516,8 @@ static const struct of_device_id msm_gfx_ldo_match_table[] = {
 		.data = (void *)(uintptr_t)MSM8953_SOC_ID,
 	},
 	{
-		.compatible = "qcom,msmfalcon-gfx-ldo",
-		.data = (void *)(uintptr_t)MSMFALCON_SOC_ID,
+		.compatible = "qcom,sdm660-gfx-ldo",
+		.data = (void *)(uintptr_t)SDM660_SOC_ID,
 	},
 	{}
 };
@@ -1572,8 +1572,8 @@ static int msm_gfx_ldo_probe(struct platform_device *pdev)
 			return rc;
 		}
 		break;
-	case MSMFALCON_SOC_ID:
-		ldo_vreg->ldo_init_config = msmfalcon_ldo_config;
+	case SDM660_SOC_ID:
+		ldo_vreg->ldo_init_config = sdm660_ldo_config;
 		ldo_vreg->ops_type = VOLTAGE;
 		init_data->constraints.valid_ops_mask
 			|= REGULATOR_CHANGE_BYPASS;
diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c
index bd58fcfe3061..ff5eca31323c 100644
--- a/drivers/soc/qcom/socinfo.c
+++ b/drivers/soc/qcom/socinfo.c
@@ -535,9 +535,9 @@ static struct msm_soc_info cpu_of_id[] = {
 	/* Hamster ID */
 	[306] = {MSM_CPU_HAMSTER, "MSMHAMSTER"},
 
-	/* falcon ID */
-	[317] = {MSM_CPU_FALCON, "MSMFALCON"},
-	[324] = {MSM_CPU_FALCON, "APQFALCON"},
+	/* 660 ID */
+	[317] = {MSM_CPU_660, "SDM660"},
+	[324] = {MSM_CPU_660, "SDA660"},
 
 	/* triton ID */
 	[318] = {MSM_CPU_TRITON, "MSMTRITON"},
@@ -1208,13 +1208,13 @@ static void * __init setup_dummy_socinfo(void)
 		dummy_socinfo.id = 306;
 		strlcpy(dummy_socinfo.build_id, "msmhamster - ",
 			sizeof(dummy_socinfo.build_id));
-	} else if (early_machine_is_msmfalcon()) {
+	} else if (early_machine_is_sdm660()) {
 		dummy_socinfo.id = 317;
-		strlcpy(dummy_socinfo.build_id, "msmfalcon - ",
+		strlcpy(dummy_socinfo.build_id, "sdm660 - ",
 			sizeof(dummy_socinfo.build_id));
-	} else if (early_machine_is_apqfalcon()) {
+	} else if (early_machine_is_sda660()) {
 		dummy_socinfo.id = 324;
-		strlcpy(dummy_socinfo.build_id, "apqfalcon - ",
+		strlcpy(dummy_socinfo.build_id, "sda660 - ",
 			sizeof(dummy_socinfo.build_id));
 	} else if (early_machine_is_msmtriton()) {
 		dummy_socinfo.id = 318;
diff --git a/drivers/thermal/msm-tsens.c b/drivers/thermal/msm-tsens.c
index 243b3229f53e..07a1fad03c31 100644
--- a/drivers/thermal/msm-tsens.c
+++ b/drivers/thermal/msm-tsens.c
@@ -937,7 +937,7 @@ static struct of_device_id tsens_match[] = {
 	{	.compatible = "qcom,msmhamster-tsens",
 		.data = (void *)TSENS_CALIB_FUSE_MAP_NONE,
 	},
-	{	.compatible = "qcom,msmfalcon-tsens",
+	{	.compatible = "qcom,sdm660-tsens",
 		.data = (void *)TSENS_CALIB_FUSE_MAP_NONE,
 	},
 	{	.compatible = "qcom,msmtriton-tsens",
@@ -5507,7 +5507,7 @@ static int get_device_tree_data(struct platform_device *pdev,
 		(!strcmp(id->compatible, "qcom,msm8998-tsens")))
 		tmdev->tsens_type = TSENS_TYPE3;
 	else if (!strcmp(id->compatible, "qcom,msmtitanium-tsens") ||
-		(!strcmp(id->compatible, "qcom,msmfalcon-tsens") ||
+		(!strcmp(id->compatible, "qcom,sdm660-tsens") ||
 		(!strcmp(id->compatible, "qcom,msmtriton-tsens") ||
 		(!strcmp(id->compatible, "qcom,msmhamster-tsens"))))) {
 		tmdev->tsens_type = TSENS_TYPE3;
@@ -5530,7 +5530,7 @@ static int get_device_tree_data(struct platform_device *pdev,
 		(!strcmp(id->compatible, "qcom,msm8937-tsens")) ||
 		(!strcmp(id->compatible, "qcom,msmtitanium-tsens")) ||
 		(!strcmp(id->compatible, "qcom,msm8998-tsens")) ||
-		(!strcmp(id->compatible, "qcom,msmfalcon-tsens") ||
+		(!strcmp(id->compatible, "qcom,sdm660-tsens") ||
 		(!strcmp(id->compatible, "qcom,msmtriton-tsens") ||
 		(!strcmp(id->compatible, "qcom,msmhamster-tsens")))))
 			tmdev->tsens_valid_status_check = true;
@@ -5547,7 +5547,7 @@ static int get_device_tree_data(struct platform_device *pdev,
 	if (!strcmp(id->compatible, "qcom,msm8996-tsens") ||
 		(!strcmp(id->compatible, "qcom,msm8998-tsens")) ||
 		(!strcmp(id->compatible, "qcom,msmhamster-tsens")) ||
-		(!strcmp(id->compatible, "qcom,msmfalcon-tsens") ||
+		(!strcmp(id->compatible, "qcom,sdm660-tsens") ||
 		(!strcmp(id->compatible, "qcom,msmtriton-tsens") ||
 		(!strcmp(id->compatible, "qcom,msmtitanium-tsens"))))) {
 		tmdev->tsens_critical_irq =
diff --git a/include/dt-bindings/clock/qcom,gcc-msmfalcon.h b/include/dt-bindings/clock/qcom,gcc-sdm660.h
index aa76fbad5083..4bf87f6c08bf 100644
--- a/include/dt-bindings/clock/qcom,gcc-msmfalcon.h
+++ b/include/dt-bindings/clock/qcom,gcc-sdm660.h
@@ -11,8 +11,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _DT_BINDINGS_CLK_MSM_GCC_FALCON_H
-#define _DT_BINDINGS_CLK_MSM_GCC_FALCON_H
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_660_H
+#define _DT_BINDINGS_CLK_MSM_GCC_660_H
 
 /* Hardware/Dummy/Voter clocks */
 #define GCC_XO					0
diff --git a/include/dt-bindings/clock/qcom,gpu-msmfalcon.h b/include/dt-bindings/clock/qcom,gpu-sdm660.h
index 2ef1e34db3a1..80b49d3420e3 100644
--- a/include/dt-bindings/clock/qcom,gpu-msmfalcon.h
+++ b/include/dt-bindings/clock/qcom,gpu-sdm660.h
@@ -11,8 +11,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _DT_BINDINGS_CLK_MSM_GPU_FALCON_H
-#define _DT_BINDINGS_CLK_MSM_GPU_FALCON_H
+#ifndef _DT_BINDINGS_CLK_MSM_GPU_660_H
+#define _DT_BINDINGS_CLK_MSM_GPU_660_H
 
 #define GFX3D_CLK_SRC						0
 #define GPU_PLL0_PLL						1
diff --git a/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h b/include/dt-bindings/clock/qcom,mmcc-sdm660.h
index 91309b4616a6..cc7c0033d6ea 100644
--- a/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h
+++ b/include/dt-bindings/clock/qcom,mmcc-sdm660.h
@@ -11,8 +11,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _DT_BINDINGS_CLK_MSM_MMCC_FALCON_H
-#define _DT_BINDINGS_CLK_MSM_MMCC_FALCON_H
+#ifndef _DT_BINDINGS_CLK_MSM_MMCC_660_H
+#define _DT_BINDINGS_CLK_MSM_MMCC_660_H
 
 #define MMSS_CAMSS_JPEG0_VOTE_CLK		 0
 #define MMSS_CAMSS_JPEG0_DMA_VOTE_CLK		 1
diff --git a/include/linux/qpnp/qpnp-revid.h b/include/linux/qpnp/qpnp-revid.h
index 8d9bbfd67992..4023e3a683d3 100644
--- a/include/linux/qpnp/qpnp-revid.h
+++ b/include/linux/qpnp/qpnp-revid.h
@@ -177,9 +177,9 @@
 /* PMI8998 */
 #define PMI8998_SUBTYPE	0x15
 
-/* PMFALCON */
-#define PM2FALCON_SUBTYPE	0x1A
-#define PMFALCON_SUBTYPE	0x1B
+/* PM660 */
+#define PM660L_SUBTYPE	0x1A
+#define PM660_SUBTYPE	0x1B
 
 #define PMI8998_V1P0_REV1	0x00
 #define PMI8998_V1P0_REV2	0x00
diff --git a/include/soc/qcom/socinfo.h b/include/soc/qcom/socinfo.h
index 3e5f7be53204..7cb8b0364596 100644
--- a/include/soc/qcom/socinfo.h
+++ b/include/soc/qcom/socinfo.h
@@ -94,10 +94,10 @@
 	of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,apq8998")
 #define early_machine_is_msmhamster()	\
 	of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msmhamster")
-#define early_machine_is_msmfalcon()	\
-	of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msmfalcon")
-#define early_machine_is_apqfalcon()	\
-	of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,apqfalcon")
+#define early_machine_is_sdm660()	\
+	of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,sdm660")
+#define early_machine_is_sda660()	\
+	of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,sda660")
 #define early_machine_is_msmtriton()	\
 	of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msmtriton")
 #else
@@ -136,8 +136,8 @@
 #define early_machine_is_msm8998()	0
 #define early_machine_is_apq8998()	0
 #define early_machine_is_msmhamster()	0
-#define early_machine_is_msmfalcon()	0
-#define early_machine_is_apqfalcon()	0
+#define early_machine_is_sdm660()	0
+#define early_machine_is_sda660()	0
 #define early_machine_is_msmtriton()	0
 #endif
 
@@ -197,7 +197,7 @@ enum msm_cpu {
 	MSM_CPU_8929,
 	MSM_CPU_8998,
 	MSM_CPU_HAMSTER,
-	MSM_CPU_FALCON,
+	MSM_CPU_660,
 	MSM_CPU_TRITON,
 };
 
diff --git a/include/uapi/linux/msm_mdp.h b/include/uapi/linux/msm_mdp.h
index 4df3845c159c..fca2a3c2d494 100644
--- a/include/uapi/linux/msm_mdp.h
+++ b/include/uapi/linux/msm_mdp.h
@@ -118,7 +118,7 @@
 #define MDSS_MDP_HW_REV_116	MDSS_MDP_REV(1, 16, 0) /* msmtitanium */
 #define MDSS_MDP_HW_REV_300	MDSS_MDP_REV(3, 0, 0)  /* msm8998 */
 #define MDSS_MDP_HW_REV_301	MDSS_MDP_REV(3, 0, 1)  /* msm8998 v1.0 */
-#define MDSS_MDP_HW_REV_320	MDSS_MDP_REV(3, 2, 0)  /* msmfalcon */
+#define MDSS_MDP_HW_REV_320	MDSS_MDP_REV(3, 2, 0)  /* sdm660 */
 
 enum {
 	NOTIFY_UPDATE_INIT,
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 26a5356fb30e..8d623d01425b 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -765,11 +765,11 @@ config SND_SOC_WCD_CPE
 
 config AUDIO_EXT_CLK
 	tristate
-	default y if SND_SOC_WCD9335=y || SND_SOC_WCD9330=y || SND_SOC_MSMFALCON_CDC=y
+	default y if SND_SOC_WCD9335=y || SND_SOC_WCD9330=y || SND_SOC_SDM660_CDC=y
 
 config SND_SOC_WCD_MBHC
 	tristate
-	default y if (SND_SOC_MSM8909_WCD=y || SND_SOC_MSMFALCON_CDC=y || SND_SOC_WCD9335=y) && SND_SOC_MDMCALIFORNIUM!=y
+	default y if (SND_SOC_MSM8909_WCD=y || SND_SOC_SDM660_CDC=y || SND_SOC_WCD9335=y) && SND_SOC_MDMCALIFORNIUM!=y
 
 config SND_SOC_WCD_DSP_MGR
 	tristate
@@ -994,7 +994,7 @@ config SND_SOC_MSM_HDMI_CODEC_RX
 	HDMI audio drivers should be built only if the platform
         supports hdmi panel.
 
-source "sound/soc/codecs/msmfalcon_cdc/Kconfig"
+source "sound/soc/codecs/sdm660_cdc/Kconfig"
 source "sound/soc/codecs/msm_sdw/Kconfig"
 
 endmenu
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 9dcdc517b9ea..5305cc6071e8 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -425,5 +425,5 @@ obj-$(CONFIG_SND_SOC_MSM_STUB)  += snd-soc-msm-stub.o
 # Amp
 obj-$(CONFIG_SND_SOC_MAX9877)	+= snd-soc-max9877.o
 obj-$(CONFIG_SND_SOC_TPA6130A2)	+= snd-soc-tpa6130a2.o
-obj-y += msmfalcon_cdc/
+obj-y += sdm660_cdc/
 obj-y += msm_sdw/
diff --git a/sound/soc/codecs/msmfalcon_cdc/Makefile b/sound/soc/codecs/msmfalcon_cdc/Makefile
deleted file mode 100644
index 814308d9f5b0..000000000000
--- a/sound/soc/codecs/msmfalcon_cdc/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-snd-soc-msmfalcon-cdc-objs := msm-analog-cdc.o msm-digital-cdc.o msmfalcon-regmap.o
-obj-$(CONFIG_SND_SOC_MSMFALCON_CDC) += snd-soc-msmfalcon-cdc.o msmfalcon-cdc-irq.o
diff --git a/sound/soc/codecs/msmfalcon_cdc/Kconfig b/sound/soc/codecs/sdm660_cdc/Kconfig
index dc461a619781..d370da3d2ad5 100644
--- a/sound/soc/codecs/msmfalcon_cdc/Kconfig
+++ b/sound/soc/codecs/sdm660_cdc/Kconfig
@@ -1,3 +1,3 @@
 
-config SND_SOC_MSMFALCON_CDC
+config SND_SOC_SDM660_CDC
 	tristate "MSM Internal PMIC based codec"
diff --git a/sound/soc/codecs/sdm660_cdc/Makefile b/sound/soc/codecs/sdm660_cdc/Makefile
new file mode 100644
index 000000000000..d846fae26054
--- /dev/null
+++ b/sound/soc/codecs/sdm660_cdc/Makefile
@@ -0,0 +1,2 @@
+snd-soc-sdm660-cdc-objs := msm-analog-cdc.o msm-digital-cdc.o sdm660-regmap.o
+obj-$(CONFIG_SND_SOC_SDM660_CDC) += snd-soc-sdm660-cdc.o sdm660-cdc-irq.o
diff --git a/sound/soc/codecs/msmfalcon_cdc/msm-analog-cdc.c b/sound/soc/codecs/sdm660_cdc/msm-analog-cdc.c
index 33c5e103dfe7..cee4720bbe31 100644
--- a/sound/soc/codecs/msmfalcon_cdc/msm-analog-cdc.c
+++ b/sound/soc/codecs/sdm660_cdc/msm-analog-cdc.c
@@ -28,17 +28,17 @@
 #include <sound/tlv.h>
 #include <sound/q6core.h>
 #include "msm-analog-cdc.h"
-#include "msmfalcon-cdc-irq.h"
-#include "msmfalcon-cdc-registers.h"
+#include "sdm660-cdc-irq.h"
+#include "sdm660-cdc-registers.h"
 #include "msm-cdc-common.h"
-#include "../../msm/msmfalcon-common.h"
+#include "../../msm/sdm660-common.h"
 #include "../wcd-mbhc-v2.h"
 
 #define DRV_NAME "pmic_analog_codec"
-#define MSMFALCON_CDC_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
+#define SDM660_CDC_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
 			SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
 			SNDRV_PCM_RATE_48000)
-#define MSMFALCON_CDC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
+#define SDM660_CDC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
 		SNDRV_PCM_FMTBIT_S24_LE)
 #define MSM_DIG_CDC_STRING_LEN 80
 #define MSM_ANLG_CDC_VERSION_ENTRY_SIZE 32
@@ -74,8 +74,8 @@ enum {
 #define MAX_BOOST_VOLTAGE 5550
 #define BOOST_VOLTAGE_STEP 50
 
-#define MSMFALCON_CDC_MBHC_BTN_COARSE_ADJ  100 /* in mV */
-#define MSMFALCON_CDC_MBHC_BTN_FINE_ADJ 12 /* in mV */
+#define SDM660_CDC_MBHC_BTN_COARSE_ADJ  100 /* in mV */
+#define SDM660_CDC_MBHC_BTN_FINE_ADJ 12 /* in mV */
 
 #define VOLTAGE_CONVERTER(value, min_value, step_size)\
 	((value - min_value)/step_size)
@@ -192,10 +192,10 @@ static const struct wcd_mbhc_intr intr_ids = {
 };
 
 static int msm_anlg_cdc_dt_parse_vreg_info(struct device *dev,
-					   struct msmfalcon_cdc_regulator *vreg,
+					   struct sdm660_cdc_regulator *vreg,
 					   const char *vreg_name,
 					   bool ondemand);
-static struct msmfalcon_cdc_pdata *msm_anlg_cdc_populate_dt_pdata(
+static struct sdm660_cdc_pdata *msm_anlg_cdc_populate_dt_pdata(
 						struct device *dev);
 static int msm_anlg_cdc_enable_ext_mb_source(struct wcd_mbhc *wcd_mbhc,
 					     bool turn_on);
@@ -208,21 +208,21 @@ static void msm_anlg_cdc_configure_cap(struct snd_soc_codec *codec,
 				       bool micbias1, bool micbias2);
 static bool msm_anlg_cdc_use_mb(struct snd_soc_codec *codec);
 
-static int get_codec_version(struct msmfalcon_cdc_priv *msmfalcon_cdc)
+static int get_codec_version(struct sdm660_cdc_priv *sdm660_cdc)
 {
-	if (msmfalcon_cdc->codec_version == DRAX_CDC)
+	if (sdm660_cdc->codec_version == DRAX_CDC)
 		return DRAX_CDC;
-	else if (msmfalcon_cdc->codec_version == DIANGU)
+	else if (sdm660_cdc->codec_version == DIANGU)
 		return DIANGU;
-	else if (msmfalcon_cdc->codec_version == CAJON_2_0)
+	else if (sdm660_cdc->codec_version == CAJON_2_0)
 		return CAJON_2_0;
-	else if (msmfalcon_cdc->codec_version == CAJON)
+	else if (sdm660_cdc->codec_version == CAJON)
 		return CAJON;
-	else if (msmfalcon_cdc->codec_version == CONGA)
+	else if (sdm660_cdc->codec_version == CONGA)
 		return CONGA;
-	else if (msmfalcon_cdc->pmic_rev == TOMBAK_2_0)
+	else if (sdm660_cdc->pmic_rev == TOMBAK_2_0)
 		return TOMBAK_2_0;
-	else if (msmfalcon_cdc->pmic_rev == TOMBAK_1_0)
+	else if (sdm660_cdc->pmic_rev == TOMBAK_1_0)
 		return TOMBAK_1_0;
 
 	pr_err("%s: unsupported codec version\n", __func__);
@@ -232,11 +232,11 @@ static int get_codec_version(struct msmfalcon_cdc_priv *msmfalcon_cdc)
 static void wcd_mbhc_meas_imped(struct snd_soc_codec *codec,
 				s16 *impedance_l, s16 *impedance_r)
 {
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
-	if ((msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_BOTH) ||
-	    (msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_HPHL)) {
+	if ((sdm660_cdc->imped_det_pin == WCD_MBHC_DET_BOTH) ||
+	    (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHL)) {
 		/* Enable ZDET_L_MEAS_EN */
 		snd_soc_update_bits(codec,
 				MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL,
@@ -251,8 +251,8 @@ static void wcd_mbhc_meas_imped(struct snd_soc_codec *codec,
 				MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL,
 				0x08, 0x00);
 	}
-	if ((msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_BOTH) ||
-	    (msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_HPHR)) {
+	if ((sdm660_cdc->imped_det_pin == WCD_MBHC_DET_BOTH) ||
+	    (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHR)) {
 		snd_soc_update_bits(codec,
 				MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL,
 				0x04, 0x04);
@@ -270,16 +270,16 @@ static void wcd_mbhc_meas_imped(struct snd_soc_codec *codec,
 static void msm_anlg_cdc_set_ref_current(struct snd_soc_codec *codec,
 					 enum wcd_curr_ref curr_ref)
 {
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
 	dev_dbg(codec->dev, "%s: curr_ref: %d\n", __func__, curr_ref);
 
-	if (get_codec_version(msmfalcon_cdc) < CAJON)
+	if (get_codec_version(sdm660_cdc) < CAJON)
 		dev_dbg(codec->dev, "%s: Setting ref current not required\n",
 			__func__);
 
-	msmfalcon_cdc->imped_i_ref = imped_i_ref[curr_ref];
+	sdm660_cdc->imped_i_ref = imped_i_ref[curr_ref];
 
 	switch (curr_ref) {
 	case I_h4_UA:
@@ -318,15 +318,15 @@ static bool msm_anlg_cdc_adj_ref_current(struct snd_soc_codec *codec,
 {
 	int i = 2;
 	s16 compare_imp = 0;
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
-	if (msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_HPHR)
+	if (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHR)
 		compare_imp = *impedance_r;
 	else
 		compare_imp = *impedance_l;
 
-	if (get_codec_version(msmfalcon_cdc) < CAJON) {
+	if (get_codec_version(sdm660_cdc) < CAJON) {
 		dev_dbg(codec->dev,
 			"%s: Reference current adjustment not required\n",
 			 __func__);
@@ -336,7 +336,7 @@ static bool msm_anlg_cdc_adj_ref_current(struct snd_soc_codec *codec,
 	while (compare_imp < imped_i_ref[i].min_val) {
 		msm_anlg_cdc_set_ref_current(codec, imped_i_ref[++i].curr_ref);
 		wcd_mbhc_meas_imped(codec, impedance_l, impedance_r);
-		compare_imp = (msmfalcon_cdc->imped_det_pin ==
+		compare_imp = (sdm660_cdc->imped_det_pin ==
 			       WCD_MBHC_DET_HPHR) ? *impedance_r : *impedance_l;
 		if (i >= I_1_UA)
 			break;
@@ -348,28 +348,28 @@ void msm_anlg_cdc_spk_ext_pa_cb(
 		int (*codec_spk_ext_pa)(struct snd_soc_codec *codec,
 			int enable), struct snd_soc_codec *codec)
 {
-	struct msmfalcon_cdc_priv *msmfalcon_cdc;
+	struct sdm660_cdc_priv *sdm660_cdc;
 
 	if (!codec) {
 		pr_err("%s: NULL codec pointer!\n", __func__);
 		return;
 	}
 
-	msmfalcon_cdc = snd_soc_codec_get_drvdata(codec);
+	sdm660_cdc = snd_soc_codec_get_drvdata(codec);
 
 	dev_dbg(codec->dev, "%s: Enter\n", __func__);
-	msmfalcon_cdc->codec_spk_ext_pa_cb = codec_spk_ext_pa;
+	sdm660_cdc->codec_spk_ext_pa_cb = codec_spk_ext_pa;
 }
 
 static void msm_anlg_cdc_compute_impedance(struct snd_soc_codec *codec, s16 l,
 					   s16 r, uint32_t *zl, uint32_t *zr,
 					   bool high)
 {
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 	uint32_t rl = 0, rr = 0;
-	struct wcd_imped_i_ref R = msmfalcon_cdc->imped_i_ref;
-	int codec_ver = get_codec_version(msmfalcon_cdc);
+	struct wcd_imped_i_ref R = sdm660_cdc->imped_i_ref;
+	int codec_ver = get_codec_version(sdm660_cdc);
 
 	switch (codec_ver) {
 	case TOMBAK_1_0:
@@ -393,17 +393,17 @@ static void msm_anlg_cdc_compute_impedance(struct snd_soc_codec *codec, s16 l,
 	case CAJON_2_0:
 	case DIANGU:
 	case DRAX_CDC:
-		if (msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_HPHL) {
+		if (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHL) {
 			rr = (uint32_t)(((DEFAULT_MULTIPLIER * (10 * r - 5)) -
 			   (DEFAULT_OFFSET * DEFAULT_GAIN))/DEFAULT_GAIN);
 			rl = (uint32_t)(((10000 * (R.multiplier * (10 * l - 5)))
 			      - R.offset * R.gain_adj)/(R.gain_adj * 100));
-		} else if (msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_HPHR) {
+		} else if (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHR) {
 			rr = (uint32_t)(((10000 * (R.multiplier * (10 * r - 5)))
 			      - R.offset * R.gain_adj)/(R.gain_adj * 100));
 			rl = (uint32_t)(((DEFAULT_MULTIPLIER * (10 * l - 5))-
 			   (DEFAULT_OFFSET * DEFAULT_GAIN))/DEFAULT_GAIN);
-		} else if (msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_NONE) {
+		} else if (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_NONE) {
 			rr = (uint32_t)(((DEFAULT_MULTIPLIER * (10 * r - 5)) -
 			   (DEFAULT_OFFSET * DEFAULT_GAIN))/DEFAULT_GAIN);
 			rl = (uint32_t)(((DEFAULT_MULTIPLIER * (10 * l - 5))-
@@ -427,7 +427,7 @@ static struct firmware_cal *msm_anlg_cdc_get_hwdep_fw_cal(
 		struct wcd_mbhc *wcd_mbhc,
 		enum wcd_cal_type type)
 {
-	struct msmfalcon_cdc_priv *msmfalcon_cdc;
+	struct sdm660_cdc_priv *sdm660_cdc;
 	struct firmware_cal *hwdep_cal;
 	struct snd_soc_codec *codec = wcd_mbhc->codec;
 
@@ -435,8 +435,8 @@ static struct firmware_cal *msm_anlg_cdc_get_hwdep_fw_cal(
 		pr_err("%s: NULL codec pointer\n", __func__);
 		return NULL;
 	}
-	msmfalcon_cdc = snd_soc_codec_get_drvdata(codec);
-	hwdep_cal = wcdcal_get_fw_cal(msmfalcon_cdc->fw_data, type);
+	sdm660_cdc = snd_soc_codec_get_drvdata(codec);
+	hwdep_cal = wcdcal_get_fw_cal(sdm660_cdc->fw_data, type);
 	if (!hwdep_cal) {
 		dev_err(codec->dev, "%s: cal not sent by %d\n",
 				__func__, type);
@@ -595,9 +595,9 @@ static void msm_anlg_cdc_mbhc_program_btn_thr(struct snd_soc_codec *codec,
 	btn_voltage = ((is_micbias) ? btn_high : btn_low);
 
 	for (i = 0; i <  num_btn; i++) {
-		course = (btn_voltage[i] / MSMFALCON_CDC_MBHC_BTN_COARSE_ADJ);
-		fine = ((btn_voltage[i] % MSMFALCON_CDC_MBHC_BTN_COARSE_ADJ) /
-				MSMFALCON_CDC_MBHC_BTN_FINE_ADJ);
+		course = (btn_voltage[i] / SDM660_CDC_MBHC_BTN_COARSE_ADJ);
+		fine = ((btn_voltage[i] % SDM660_CDC_MBHC_BTN_COARSE_ADJ) /
+				SDM660_CDC_MBHC_BTN_FINE_ADJ);
 
 		reg_val = (course << 5) | (fine << 2);
 		snd_soc_update_bits(codec, reg_addr, 0xFC, reg_val);
@@ -612,7 +612,7 @@ static void msm_anlg_cdc_mbhc_calc_impedance(struct wcd_mbhc *mbhc,
 					     uint32_t *zl, uint32_t *zr)
 {
 	struct snd_soc_codec *codec = mbhc->codec;
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 	s16 impedance_l, impedance_r;
 	s16 impedance_l_fixed;
@@ -627,7 +627,7 @@ static void msm_anlg_cdc_mbhc_calc_impedance(struct wcd_mbhc *mbhc,
 	reg3 = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_MICB_2_EN);
 	reg4 = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL);
 
-	msmfalcon_cdc->imped_det_pin = WCD_MBHC_DET_BOTH;
+	sdm660_cdc->imped_det_pin = WCD_MBHC_DET_BOTH;
 	mbhc->hph_type = WCD_MBHC_HPH_NONE;
 
 	/* disable FSM and micbias and enable pullup*/
@@ -673,21 +673,21 @@ static void msm_anlg_cdc_mbhc_calc_impedance(struct wcd_mbhc *mbhc,
 			snd_soc_update_bits(codec,
 				MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL,
 				0x03, 0x00);
-			msmfalcon_cdc->imped_det_pin = (impedance_l > 2 &&
+			sdm660_cdc->imped_det_pin = (impedance_l > 2 &&
 						      impedance_r > 2) ?
 						      WCD_MBHC_DET_NONE :
 						      ((impedance_l > 2) ?
 						      WCD_MBHC_DET_HPHR :
 						      WCD_MBHC_DET_HPHL);
-			if (msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_NONE)
+			if (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_NONE)
 				goto exit;
 		} else {
-			if (get_codec_version(msmfalcon_cdc) >= CAJON) {
+			if (get_codec_version(sdm660_cdc) >= CAJON) {
 				if (impedance_l == 63 && impedance_r == 63) {
 					dev_dbg(codec->dev,
 						"%s: HPHL and HPHR are floating\n",
 						 __func__);
-					msmfalcon_cdc->imped_det_pin =
+					sdm660_cdc->imped_det_pin =
 							WCD_MBHC_DET_NONE;
 					mbhc->hph_type = WCD_MBHC_HPH_NONE;
 				} else if (impedance_l == 63
@@ -695,7 +695,7 @@ static void msm_anlg_cdc_mbhc_calc_impedance(struct wcd_mbhc *mbhc,
 					dev_dbg(codec->dev,
 						"%s: Mono HS with HPHL floating\n",
 						 __func__);
-					msmfalcon_cdc->imped_det_pin =
+					sdm660_cdc->imped_det_pin =
 							WCD_MBHC_DET_HPHR;
 					mbhc->hph_type = WCD_MBHC_HPH_MONO;
 				} else if (impedance_r == 63 &&
@@ -703,7 +703,7 @@ static void msm_anlg_cdc_mbhc_calc_impedance(struct wcd_mbhc *mbhc,
 					dev_dbg(codec->dev,
 						"%s: Mono HS with HPHR floating\n",
 						 __func__);
-					msmfalcon_cdc->imped_det_pin =
+					sdm660_cdc->imped_det_pin =
 							WCD_MBHC_DET_HPHL;
 					mbhc->hph_type = WCD_MBHC_HPH_MONO;
 				} else if (impedance_l > 3 && impedance_r > 3 &&
@@ -717,7 +717,7 @@ static void msm_anlg_cdc_mbhc_calc_impedance(struct wcd_mbhc *mbhc,
 						dev_dbg(codec->dev,
 							"%s: Mono Headset\n",
 							__func__);
-						msmfalcon_cdc->imped_det_pin =
+						sdm660_cdc->imped_det_pin =
 							WCD_MBHC_DET_NONE;
 						mbhc->hph_type =
 							WCD_MBHC_HPH_MONO;
@@ -725,7 +725,7 @@ static void msm_anlg_cdc_mbhc_calc_impedance(struct wcd_mbhc *mbhc,
 					dev_dbg(codec->dev,
 						"%s: STEREO headset is found\n",
 						 __func__);
-					msmfalcon_cdc->imped_det_pin =
+					sdm660_cdc->imped_det_pin =
 							WCD_MBHC_DET_BOTH;
 					mbhc->hph_type = WCD_MBHC_HPH_STEREO;
 				}
@@ -777,8 +777,8 @@ static void msm_anlg_cdc_mbhc_calc_impedance(struct wcd_mbhc *mbhc,
 	 */
 
 	if (!min_range_used ||
-	    msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_HPHL ||
-	    msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_HPHR)
+	    sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHL ||
+	    sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHR)
 		goto exit;
 
 
@@ -875,7 +875,7 @@ static int msm_anlg_cdc_dig_register_notifier(void *handle,
 					      struct notifier_block *nblock,
 					      bool enable)
 {
-	struct msmfalcon_cdc *handle_cdc = handle;
+	struct sdm660_cdc *handle_cdc = handle;
 
 	if (enable)
 		return blocking_notifier_chain_register(&handle_cdc->notifier,
@@ -889,15 +889,15 @@ static int msm_anlg_cdc_mbhc_register_notifier(struct wcd_mbhc *wcd_mbhc,
 					       bool enable)
 {
 	struct snd_soc_codec *codec = wcd_mbhc->codec;
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
 	if (enable)
 		return blocking_notifier_chain_register(
-						&msmfalcon_cdc->notifier,
+						&sdm660_cdc->notifier,
 						nblock);
 
-	return blocking_notifier_chain_unregister(&msmfalcon_cdc->notifier,
+	return blocking_notifier_chain_unregister(&sdm660_cdc->notifier,
 						  nblock);
 }
 
@@ -945,27 +945,27 @@ static const uint32_t wcd_imped_val[] = {4, 8, 12, 13, 16,
 static void msm_anlg_cdc_dig_notifier_call(struct snd_soc_codec *codec,
 					const enum dig_cdc_notify_event event)
 {
-	struct msmfalcon_cdc *msmfalcon_cdc = codec->control_data;
+	struct sdm660_cdc *sdm660_cdc = codec->control_data;
 
 	pr_debug("%s: notifier call event %d\n", __func__, event);
-	blocking_notifier_call_chain(&msmfalcon_cdc->notifier,
+	blocking_notifier_call_chain(&sdm660_cdc->notifier,
 				     event, NULL);
 }
 
 static void msm_anlg_cdc_notifier_call(struct snd_soc_codec *codec,
 				       const enum wcd_notify_event event)
 {
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
 	dev_dbg(codec->dev, "%s: notifier call event %d\n", __func__, event);
-	blocking_notifier_call_chain(&msmfalcon_cdc->notifier, event,
-				     &msmfalcon_cdc->mbhc);
+	blocking_notifier_call_chain(&sdm660_cdc->notifier, event,
+				     &sdm660_cdc->mbhc);
 }
 
 static void msm_anlg_cdc_boost_on(struct snd_soc_codec *codec)
 {
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
 	snd_soc_update_bits(codec,
@@ -973,7 +973,7 @@ static void msm_anlg_cdc_boost_on(struct snd_soc_codec *codec)
 	snd_soc_write(codec, MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0xA5);
 	snd_soc_write(codec, MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3, 0x0F);
 	snd_soc_write(codec, MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL, 0x30);
-	if (get_codec_version(msmfalcon_cdc) < CAJON_2_0)
+	if (get_codec_version(sdm660_cdc) < CAJON_2_0)
 		snd_soc_write(codec, MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0x82);
 	else
 		snd_soc_write(codec, MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0xA2);
@@ -987,7 +987,7 @@ static void msm_anlg_cdc_boost_on(struct snd_soc_codec *codec)
 			    0x03, 0x03);
 	snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL,
 			    0xE1, 0xE1);
-	if (get_codec_version(msmfalcon_cdc) < CAJON_2_0) {
+	if (get_codec_version(sdm660_cdc) < CAJON_2_0) {
 		snd_soc_update_bits(codec, MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
 				    0x20, 0x20);
 		/* Wait for 1ms after clock ctl enable */
@@ -1021,10 +1021,10 @@ static void msm_anlg_cdc_boost_off(struct snd_soc_codec *codec)
 
 static void msm_anlg_cdc_bypass_on(struct snd_soc_codec *codec)
 {
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
-	if (get_codec_version(msmfalcon_cdc) < CAJON_2_0) {
+	if (get_codec_version(sdm660_cdc) < CAJON_2_0) {
 		snd_soc_write(codec,
 			MSM89XX_PMIC_ANALOG_SEC_ACCESS,
 			0xA5);
@@ -1058,10 +1058,10 @@ static void msm_anlg_cdc_bypass_on(struct snd_soc_codec *codec)
 
 static void msm_anlg_cdc_bypass_off(struct snd_soc_codec *codec)
 {
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
-	if (get_codec_version(msmfalcon_cdc) < CAJON_2_0) {
+	if (get_codec_version(sdm660_cdc) < CAJON_2_0) {
 		snd_soc_update_bits(codec,
 			MSM89XX_PMIC_ANALOG_BOOST_EN_CTL,
 			0x80, 0x00);
@@ -1087,13 +1087,13 @@ static void msm_anlg_cdc_bypass_off(struct snd_soc_codec *codec)
 static void msm_anlg_cdc_boost_mode_sequence(struct snd_soc_codec *codec,
 					     int flag)
 {
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
 	if (flag == EAR_PMU) {
-		switch (msmfalcon_cdc->boost_option) {
+		switch (sdm660_cdc->boost_option) {
 		case BOOST_SWITCH:
-			if (msmfalcon_cdc->ear_pa_boost_set) {
+			if (sdm660_cdc->ear_pa_boost_set) {
 				msm_anlg_cdc_boost_off(codec);
 				msm_anlg_cdc_bypass_on(codec);
 			}
@@ -1110,13 +1110,13 @@ static void msm_anlg_cdc_boost_mode_sequence(struct snd_soc_codec *codec,
 		default:
 			dev_err(codec->dev,
 				"%s: invalid boost option: %d\n", __func__,
-				msmfalcon_cdc->boost_option);
+				sdm660_cdc->boost_option);
 			break;
 		}
 	} else if (flag == EAR_PMD) {
-		switch (msmfalcon_cdc->boost_option) {
+		switch (sdm660_cdc->boost_option) {
 		case BOOST_SWITCH:
-			if (msmfalcon_cdc->ear_pa_boost_set)
+			if (sdm660_cdc->ear_pa_boost_set)
 				msm_anlg_cdc_bypass_off(codec);
 			break;
 		case BOOST_ALWAYS:
@@ -1133,13 +1133,13 @@ static void msm_anlg_cdc_boost_mode_sequence(struct snd_soc_codec *codec,
 		default:
 			dev_err(codec->dev,
 				"%s: invalid boost option: %d\n", __func__,
-				msmfalcon_cdc->boost_option);
+				sdm660_cdc->boost_option);
 			break;
 		}
 	} else if (flag == SPK_PMU) {
-		switch (msmfalcon_cdc->boost_option) {
+		switch (sdm660_cdc->boost_option) {
 		case BOOST_SWITCH:
-			if (msmfalcon_cdc->spk_boost_set) {
+			if (sdm660_cdc->spk_boost_set) {
 				msm_anlg_cdc_bypass_off(codec);
 				msm_anlg_cdc_boost_on(codec);
 			}
@@ -1156,13 +1156,13 @@ static void msm_anlg_cdc_boost_mode_sequence(struct snd_soc_codec *codec,
 		default:
 			dev_err(codec->dev,
 				"%s: invalid boost option: %d\n", __func__,
-				msmfalcon_cdc->boost_option);
+				sdm660_cdc->boost_option);
 			break;
 		}
 	} else if (flag == SPK_PMD) {
-		switch (msmfalcon_cdc->boost_option) {
+		switch (sdm660_cdc->boost_option) {
 		case BOOST_SWITCH:
-			if (msmfalcon_cdc->spk_boost_set) {
+			if (sdm660_cdc->spk_boost_set) {
 				msm_anlg_cdc_boost_off(codec);
 				/*
 				 * Add 40 ms sleep for the spk
@@ -1188,14 +1188,14 @@ static void msm_anlg_cdc_boost_mode_sequence(struct snd_soc_codec *codec,
 		default:
 			dev_err(codec->dev,
 				"%s: invalid boost option: %d\n", __func__,
-				msmfalcon_cdc->boost_option);
+				sdm660_cdc->boost_option);
 			break;
 		}
 	}
 }
 
 static int msm_anlg_cdc_dt_parse_vreg_info(struct device *dev,
-	struct msmfalcon_cdc_regulator *vreg, const char *vreg_name,
+	struct sdm660_cdc_regulator *vreg, const char *vreg_name,
 	bool ondemand)
 {
 	int len, ret = 0;
@@ -1250,7 +1250,7 @@ static int msm_anlg_cdc_dt_parse_vreg_info(struct device *dev,
 
 static void msm_anlg_cdc_dt_parse_boost_info(struct snd_soc_codec *codec)
 {
-	struct msmfalcon_cdc_priv *msmfalcon_cdc_priv =
+	struct sdm660_cdc_priv *sdm660_cdc_priv =
 		snd_soc_codec_get_drvdata(codec);
 	const char *prop_name = "qcom,cdc-boost-voltage";
 	int boost_voltage, ret;
@@ -1269,7 +1269,7 @@ static void msm_anlg_cdc_dt_parse_boost_info(struct snd_soc_codec *codec)
 		boost_voltage = DEFAULT_BOOST_VOLTAGE;
 	}
 
-	msmfalcon_cdc_priv->boost_voltage =
+	sdm660_cdc_priv->boost_voltage =
 		VOLTAGE_CONVERTER(boost_voltage, MIN_BOOST_VOLTAGE,
 				BOOST_VOLTAGE_STEP);
 	dev_dbg(codec->dev, "Boost voltage value is: %d\n",
@@ -1291,10 +1291,10 @@ static void msm_anlg_cdc_dt_parse_micbias_info(struct device *dev,
 	}
 }
 
-static struct msmfalcon_cdc_pdata *msm_anlg_cdc_populate_dt_pdata(
+static struct sdm660_cdc_pdata *msm_anlg_cdc_populate_dt_pdata(
 						struct device *dev)
 {
-	struct msmfalcon_cdc_pdata *pdata;
+	struct sdm660_cdc_pdata *pdata;
 	int ret, static_cnt, ond_cnt, idx, i;
 	const char *name = NULL;
 	const char *static_prop_name = "qcom,cdc-static-supplies";
@@ -1384,7 +1384,7 @@ static int msm_anlg_cdc_codec_enable_on_demand_supply(
 {
 	int ret = 0;
 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 	struct on_demand_supply *supply;
 
@@ -1396,9 +1396,9 @@ static int msm_anlg_cdc_codec_enable_on_demand_supply(
 	}
 	dev_dbg(codec->dev, "%s: supply: %s event: %d ref: %d\n",
 		__func__, on_demand_supply_name[w->shift], event,
-		atomic_read(&msmfalcon_cdc->on_demand_list[w->shift].ref));
+		atomic_read(&sdm660_cdc->on_demand_list[w->shift].ref));
 
-	supply = &msmfalcon_cdc->on_demand_list[w->shift];
+	supply = &sdm660_cdc->on_demand_list[w->shift];
 	WARN_ONCE(!supply->supply, "%s isn't defined\n",
 		  on_demand_supply_name[w->shift]);
 	if (!supply->supply) {
@@ -1462,7 +1462,7 @@ static int msm_anlg_cdc_codec_enable_charge_pump(struct snd_soc_dapm_widget *w,
 						 int event)
 {
 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
 	dev_dbg(codec->dev, "%s: event = %d\n", __func__, event);
@@ -1474,7 +1474,7 @@ static int msm_anlg_cdc_codec_enable_charge_pump(struct snd_soc_dapm_widget *w,
 					MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
 					0x80, 0x80);
 			msm_anlg_cdc_boost_mode_sequence(codec, EAR_PMU);
-		} else if (get_codec_version(msmfalcon_cdc) >= DIANGU) {
+		} else if (get_codec_version(sdm660_cdc) >= DIANGU) {
 			snd_soc_update_bits(codec,
 					MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
 					0x80, 0x80);
@@ -1495,10 +1495,10 @@ static int msm_anlg_cdc_codec_enable_charge_pump(struct snd_soc_dapm_widget *w,
 			snd_soc_update_bits(codec,
 					MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
 					0x80, 0x00);
-			if (msmfalcon_cdc->boost_option != BOOST_ALWAYS) {
+			if (sdm660_cdc->boost_option != BOOST_ALWAYS) {
 				dev_dbg(codec->dev,
 					"%s: boost_option:%d, tear down ear\n",
-					__func__, msmfalcon_cdc->boost_option);
+					__func__, sdm660_cdc->boost_option);
 				msm_anlg_cdc_boost_mode_sequence(codec,
 								 EAR_PMD);
 			}
@@ -1510,16 +1510,16 @@ static int msm_anlg_cdc_codec_enable_charge_pump(struct snd_soc_dapm_widget *w,
 			snd_soc_update_bits(codec,
 				MSM89XX_PMIC_ANALOG_RX_EAR_CTL, 0x80, 0x00);
 		} else {
-			if (get_codec_version(msmfalcon_cdc) < DIANGU)
+			if (get_codec_version(sdm660_cdc) < DIANGU)
 				snd_soc_update_bits(codec,
 					MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
 					0x40, 0x00);
-			if (msmfalcon_cdc->rx_bias_count == 0)
+			if (sdm660_cdc->rx_bias_count == 0)
 				snd_soc_update_bits(codec,
 					MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
 					0x80, 0x00);
 			dev_dbg(codec->dev, "%s: rx_bias_count = %d\n",
-					__func__, msmfalcon_cdc->rx_bias_count);
+					__func__, sdm660_cdc->rx_bias_count);
 		}
 		break;
 	}
@@ -1530,13 +1530,13 @@ static int msm_anlg_cdc_ear_pa_boost_get(struct snd_kcontrol *kcontrol,
 					 struct snd_ctl_elem_value *ucontrol)
 {
 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
 	ucontrol->value.integer.value[0] =
-		(msmfalcon_cdc->ear_pa_boost_set ? 1 : 0);
-	dev_dbg(codec->dev, "%s: msmfalcon_cdc->ear_pa_boost_set = %d\n",
-			__func__, msmfalcon_cdc->ear_pa_boost_set);
+		(sdm660_cdc->ear_pa_boost_set ? 1 : 0);
+	dev_dbg(codec->dev, "%s: sdm660_cdc->ear_pa_boost_set = %d\n",
+			__func__, sdm660_cdc->ear_pa_boost_set);
 	return 0;
 }
 
@@ -1544,12 +1544,12 @@ static int msm_anlg_cdc_ear_pa_boost_set(struct snd_kcontrol *kcontrol,
 					 struct snd_ctl_elem_value *ucontrol)
 {
 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
 	dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
 		__func__, ucontrol->value.integer.value[0]);
-	msmfalcon_cdc->ear_pa_boost_set =
+	sdm660_cdc->ear_pa_boost_set =
 		(ucontrol->value.integer.value[0] ? true : false);
 	return 0;
 }
@@ -1596,10 +1596,10 @@ static int msm_anlg_cdc_pa_gain_get(struct snd_kcontrol *kcontrol,
 {
 	u8 ear_pa_gain;
 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
-	if (get_codec_version(msmfalcon_cdc) >= DIANGU) {
+	if (get_codec_version(sdm660_cdc) >= DIANGU) {
 		ear_pa_gain = snd_soc_read(codec,
 					MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC);
 		ear_pa_gain = (ear_pa_gain >> 1) & 0x3;
@@ -1643,13 +1643,13 @@ static int msm_anlg_cdc_pa_gain_put(struct snd_kcontrol *kcontrol,
 {
 	u8 ear_pa_gain;
 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
 	dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
 		__func__, ucontrol->value.integer.value[0]);
 
-	if (get_codec_version(msmfalcon_cdc) >= DIANGU) {
+	if (get_codec_version(sdm660_cdc) >= DIANGU) {
 		switch (ucontrol->value.integer.value[0]) {
 		case 0:
 			ear_pa_gain = 0x06;
@@ -1691,20 +1691,20 @@ static int msm_anlg_cdc_hph_mode_get(struct snd_kcontrol *kcontrol,
 				     struct snd_ctl_elem_value *ucontrol)
 {
 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
-	if (msmfalcon_cdc->hph_mode == NORMAL_MODE) {
+	if (sdm660_cdc->hph_mode == NORMAL_MODE) {
 		ucontrol->value.integer.value[0] = 0;
-	} else if (msmfalcon_cdc->hph_mode == HD2_MODE) {
+	} else if (sdm660_cdc->hph_mode == HD2_MODE) {
 		ucontrol->value.integer.value[0] = 1;
 	} else  {
 		dev_err(codec->dev, "%s: ERROR: Default HPH Mode= %d\n",
-			__func__, msmfalcon_cdc->hph_mode);
+			__func__, sdm660_cdc->hph_mode);
 	}
 
-	dev_dbg(codec->dev, "%s: msmfalcon_cdc->hph_mode = %d\n", __func__,
-			msmfalcon_cdc->hph_mode);
+	dev_dbg(codec->dev, "%s: sdm660_cdc->hph_mode = %d\n", __func__,
+			sdm660_cdc->hph_mode);
 	return 0;
 }
 
@@ -1712,7 +1712,7 @@ static int msm_anlg_cdc_hph_mode_set(struct snd_kcontrol *kcontrol,
 				     struct snd_ctl_elem_value *ucontrol)
 {
 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
 	dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
@@ -1720,18 +1720,18 @@ static int msm_anlg_cdc_hph_mode_set(struct snd_kcontrol *kcontrol,
 
 	switch (ucontrol->value.integer.value[0]) {
 	case 0:
-		msmfalcon_cdc->hph_mode = NORMAL_MODE;
+		sdm660_cdc->hph_mode = NORMAL_MODE;
 		break;
 	case 1:
-		if (get_codec_version(msmfalcon_cdc) >= DIANGU)
-			msmfalcon_cdc->hph_mode = HD2_MODE;
+		if (get_codec_version(sdm660_cdc) >= DIANGU)
+			sdm660_cdc->hph_mode = HD2_MODE;
 		break;
 	default:
-		msmfalcon_cdc->hph_mode = NORMAL_MODE;
+		sdm660_cdc->hph_mode = NORMAL_MODE;
 		break;
 	}
-	dev_dbg(codec->dev, "%s: msmfalcon_cdc->hph_mode_set = %d\n",
-		__func__, msmfalcon_cdc->hph_mode);
+	dev_dbg(codec->dev, "%s: sdm660_cdc->hph_mode_set = %d\n",
+		__func__, sdm660_cdc->hph_mode);
 	return 0;
 }
 
@@ -1739,25 +1739,25 @@ static int msm_anlg_cdc_boost_option_get(struct snd_kcontrol *kcontrol,
 					 struct snd_ctl_elem_value *ucontrol)
 {
 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
-	if (msmfalcon_cdc->boost_option == BOOST_SWITCH) {
+	if (sdm660_cdc->boost_option == BOOST_SWITCH) {
 		ucontrol->value.integer.value[0] = 0;
-	} else if (msmfalcon_cdc->boost_option == BOOST_ALWAYS) {
+	} else if (sdm660_cdc->boost_option == BOOST_ALWAYS) {
 		ucontrol->value.integer.value[0] = 1;
-	} else if (msmfalcon_cdc->boost_option == BYPASS_ALWAYS) {
+	} else if (sdm660_cdc->boost_option == BYPASS_ALWAYS) {
 		ucontrol->value.integer.value[0] = 2;
-	} else if (msmfalcon_cdc->boost_option == BOOST_ON_FOREVER) {
+	} else if (sdm660_cdc->boost_option == BOOST_ON_FOREVER) {
 		ucontrol->value.integer.value[0] = 3;
 	} else  {
 		dev_err(codec->dev, "%s: ERROR: Unsupported Boost option= %d\n",
-			__func__, msmfalcon_cdc->boost_option);
+			__func__, sdm660_cdc->boost_option);
 		return -EINVAL;
 	}
 
-	dev_dbg(codec->dev, "%s: msmfalcon_cdc->boost_option = %d\n", __func__,
-			msmfalcon_cdc->boost_option);
+	dev_dbg(codec->dev, "%s: sdm660_cdc->boost_option = %d\n", __func__,
+			sdm660_cdc->boost_option);
 	return 0;
 }
 
@@ -1765,7 +1765,7 @@ static int msm_anlg_cdc_boost_option_set(struct snd_kcontrol *kcontrol,
 					 struct snd_ctl_elem_value *ucontrol)
 {
 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
 	dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
@@ -1773,26 +1773,26 @@ static int msm_anlg_cdc_boost_option_set(struct snd_kcontrol *kcontrol,
 
 	switch (ucontrol->value.integer.value[0]) {
 	case 0:
-		msmfalcon_cdc->boost_option = BOOST_SWITCH;
+		sdm660_cdc->boost_option = BOOST_SWITCH;
 		break;
 	case 1:
-		msmfalcon_cdc->boost_option = BOOST_ALWAYS;
+		sdm660_cdc->boost_option = BOOST_ALWAYS;
 		break;
 	case 2:
-		msmfalcon_cdc->boost_option = BYPASS_ALWAYS;
+		sdm660_cdc->boost_option = BYPASS_ALWAYS;
 		msm_anlg_cdc_bypass_on(codec);
 		break;
 	case 3:
-		msmfalcon_cdc->boost_option = BOOST_ON_FOREVER;
+		sdm660_cdc->boost_option = BOOST_ON_FOREVER;
 		msm_anlg_cdc_boost_on(codec);
 		break;
 	default:
 		pr_err("%s: invalid boost option: %d\n", __func__,
-					msmfalcon_cdc->boost_option);
+					sdm660_cdc->boost_option);
 		return -EINVAL;
 	}
-	dev_dbg(codec->dev, "%s: msmfalcon_cdc->boost_option_set = %d\n",
-		__func__, msmfalcon_cdc->boost_option);
+	dev_dbg(codec->dev, "%s: sdm660_cdc->boost_option_set = %d\n",
+		__func__, sdm660_cdc->boost_option);
 	return 0;
 }
 
@@ -1800,21 +1800,21 @@ static int msm_anlg_cdc_spk_boost_get(struct snd_kcontrol *kcontrol,
 				      struct snd_ctl_elem_value *ucontrol)
 {
 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
-	if (msmfalcon_cdc->spk_boost_set == false) {
+	if (sdm660_cdc->spk_boost_set == false) {
 		ucontrol->value.integer.value[0] = 0;
-	} else if (msmfalcon_cdc->spk_boost_set == true) {
+	} else if (sdm660_cdc->spk_boost_set == true) {
 		ucontrol->value.integer.value[0] = 1;
 	} else  {
 		dev_err(codec->dev, "%s: ERROR: Unsupported Speaker Boost = %d\n",
-				__func__, msmfalcon_cdc->spk_boost_set);
+				__func__, sdm660_cdc->spk_boost_set);
 		return -EINVAL;
 	}
 
-	dev_dbg(codec->dev, "%s: msmfalcon_cdc->spk_boost_set = %d\n", __func__,
-			msmfalcon_cdc->spk_boost_set);
+	dev_dbg(codec->dev, "%s: sdm660_cdc->spk_boost_set = %d\n", __func__,
+			sdm660_cdc->spk_boost_set);
 	return 0;
 }
 
@@ -1822,7 +1822,7 @@ static int msm_anlg_cdc_spk_boost_set(struct snd_kcontrol *kcontrol,
 				      struct snd_ctl_elem_value *ucontrol)
 {
 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
 	dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
@@ -1830,16 +1830,16 @@ static int msm_anlg_cdc_spk_boost_set(struct snd_kcontrol *kcontrol,
 
 	switch (ucontrol->value.integer.value[0]) {
 	case 0:
-		msmfalcon_cdc->spk_boost_set = false;
+		sdm660_cdc->spk_boost_set = false;
 		break;
 	case 1:
-		msmfalcon_cdc->spk_boost_set = true;
+		sdm660_cdc->spk_boost_set = true;
 		break;
 	default:
 		return -EINVAL;
 	}
-	dev_dbg(codec->dev, "%s: msmfalcon_cdc->spk_boost_set = %d\n",
-		__func__, msmfalcon_cdc->spk_boost_set);
+	dev_dbg(codec->dev, "%s: sdm660_cdc->spk_boost_set = %d\n",
+		__func__, sdm660_cdc->spk_boost_set);
 	return 0;
 }
 
@@ -1847,16 +1847,16 @@ static int msm_anlg_cdc_ext_spk_boost_get(struct snd_kcontrol *kcontrol,
 					  struct snd_ctl_elem_value *ucontrol)
 {
 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
-	if (msmfalcon_cdc->ext_spk_boost_set == false)
+	if (sdm660_cdc->ext_spk_boost_set == false)
 		ucontrol->value.integer.value[0] = 0;
 	else
 		ucontrol->value.integer.value[0] = 1;
 
-	dev_dbg(codec->dev, "%s: msmfalcon_cdc->ext_spk_boost_set = %d\n",
-				__func__, msmfalcon_cdc->ext_spk_boost_set);
+	dev_dbg(codec->dev, "%s: sdm660_cdc->ext_spk_boost_set = %d\n",
+				__func__, sdm660_cdc->ext_spk_boost_set);
 	return 0;
 }
 
@@ -1864,7 +1864,7 @@ static int msm_anlg_cdc_ext_spk_boost_set(struct snd_kcontrol *kcontrol,
 					  struct snd_ctl_elem_value *ucontrol)
 {
 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
 	dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
@@ -1872,16 +1872,16 @@ static int msm_anlg_cdc_ext_spk_boost_set(struct snd_kcontrol *kcontrol,
 
 	switch (ucontrol->value.integer.value[0]) {
 	case 0:
-		msmfalcon_cdc->ext_spk_boost_set = false;
+		sdm660_cdc->ext_spk_boost_set = false;
 		break;
 	case 1:
-		msmfalcon_cdc->ext_spk_boost_set = true;
+		sdm660_cdc->ext_spk_boost_set = true;
 		break;
 	default:
 		return -EINVAL;
 	}
-	dev_dbg(codec->dev, "%s: msmfalcon_cdc->spk_boost_set = %d\n",
-		__func__, msmfalcon_cdc->spk_boost_set);
+	dev_dbg(codec->dev, "%s: sdm660_cdc->spk_boost_set = %d\n",
+		__func__, sdm660_cdc->spk_boost_set);
 	return 0;
 }
 
@@ -1975,7 +1975,7 @@ static int tombak_hph_impedance_get(struct snd_kcontrol *kcontrol,
 	bool hphr;
 	struct soc_multi_mixer_control *mc;
 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
-	struct msmfalcon_cdc_priv *priv = snd_soc_codec_get_drvdata(codec);
+	struct sdm660_cdc_priv *priv = snd_soc_codec_get_drvdata(codec);
 
 	mc = (struct soc_multi_mixer_control *)(kcontrol->private_value);
 
@@ -2000,12 +2000,12 @@ static int tombak_get_hph_type(struct snd_kcontrol *kcontrol,
 			       struct snd_ctl_elem_value *ucontrol)
 {
 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
-	struct msmfalcon_cdc_priv *priv = snd_soc_codec_get_drvdata(codec);
+	struct sdm660_cdc_priv *priv = snd_soc_codec_get_drvdata(codec);
 	struct wcd_mbhc *mbhc;
 
 	if (!priv) {
 		dev_err(codec->dev,
-			"%s: msmfalcon_cdc-wcd private data is NULL\n",
+			"%s: sdm660_cdc-wcd private data is NULL\n",
 			 __func__);
 		return -EINVAL;
 	}
@@ -2129,7 +2129,7 @@ static const struct snd_kcontrol_new lo_mux[] = {
 static void msm_anlg_cdc_codec_enable_adc_block(struct snd_soc_codec *codec,
 					 int enable)
 {
-	struct msmfalcon_cdc_priv *wcd8x16 = snd_soc_codec_get_drvdata(codec);
+	struct sdm660_cdc_priv *wcd8x16 = snd_soc_codec_get_drvdata(codec);
 
 	dev_dbg(codec->dev, "%s %d\n", __func__, enable);
 
@@ -2238,7 +2238,7 @@ static int msm_anlg_cdc_codec_enable_spk_pa(struct snd_soc_dapm_widget *w,
 					    int event)
 {
 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
 	dev_dbg(codec->dev, "%s %d %s\n", __func__, event, w->name);
@@ -2248,9 +2248,9 @@ static int msm_anlg_cdc_codec_enable_spk_pa(struct snd_soc_dapm_widget *w,
 			MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
 		snd_soc_update_bits(codec,
 			MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, 0x01, 0x01);
-		switch (msmfalcon_cdc->boost_option) {
+		switch (sdm660_cdc->boost_option) {
 		case BOOST_SWITCH:
-			if (!msmfalcon_cdc->spk_boost_set)
+			if (!sdm660_cdc->spk_boost_set)
 				snd_soc_update_bits(codec,
 					MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL,
 					0x10, 0x10);
@@ -2266,23 +2266,23 @@ static int msm_anlg_cdc_codec_enable_spk_pa(struct snd_soc_dapm_widget *w,
 		default:
 			dev_err(codec->dev,
 				"%s: invalid boost option: %d\n", __func__,
-				msmfalcon_cdc->boost_option);
+				sdm660_cdc->boost_option);
 			break;
 		}
 		/* Wait for 1ms after SPK_DAC CTL setting */
 		usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
 		snd_soc_update_bits(codec,
 			MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, 0xE0, 0xE0);
-		if (get_codec_version(msmfalcon_cdc) != TOMBAK_1_0)
+		if (get_codec_version(sdm660_cdc) != TOMBAK_1_0)
 			snd_soc_update_bits(codec,
 				MSM89XX_PMIC_ANALOG_RX_EAR_CTL, 0x01, 0x01);
 		break;
 	case SND_SOC_DAPM_POST_PMU:
 		/* Wait for 1ms after SPK_VBAT_LDO Enable */
 		usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
-		switch (msmfalcon_cdc->boost_option) {
+		switch (sdm660_cdc->boost_option) {
 		case BOOST_SWITCH:
-			if (msmfalcon_cdc->spk_boost_set)
+			if (sdm660_cdc->spk_boost_set)
 				snd_soc_update_bits(codec,
 					MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL,
 					0xEF, 0xEF);
@@ -2304,7 +2304,7 @@ static int msm_anlg_cdc_codec_enable_spk_pa(struct snd_soc_dapm_widget *w,
 		default:
 			dev_err(codec->dev,
 				"%s: invalid boost option: %d\n", __func__,
-				msmfalcon_cdc->boost_option);
+				sdm660_cdc->boost_option);
 			break;
 		}
 		msm_anlg_cdc_dig_notifier_call(codec,
@@ -2320,12 +2320,12 @@ static int msm_anlg_cdc_codec_enable_spk_pa(struct snd_soc_dapm_widget *w,
 		usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
 		snd_soc_update_bits(codec,
 			MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x10, 0x10);
-		if (get_codec_version(msmfalcon_cdc) < CAJON_2_0)
+		if (get_codec_version(sdm660_cdc) < CAJON_2_0)
 			msm_anlg_cdc_boost_mode_sequence(codec, SPK_PMD);
 		snd_soc_update_bits(codec, w->reg, 0x80, 0x00);
-		switch (msmfalcon_cdc->boost_option) {
+		switch (sdm660_cdc->boost_option) {
 		case BOOST_SWITCH:
-			if (msmfalcon_cdc->spk_boost_set)
+			if (sdm660_cdc->spk_boost_set)
 				snd_soc_update_bits(codec,
 					MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL,
 					0xEF, 0x69);
@@ -2341,7 +2341,7 @@ static int msm_anlg_cdc_codec_enable_spk_pa(struct snd_soc_dapm_widget *w,
 		default:
 			dev_err(codec->dev,
 				"%s: invalid boost option: %d\n", __func__,
-				msmfalcon_cdc->boost_option);
+				sdm660_cdc->boost_option);
 			break;
 		}
 		break;
@@ -2354,12 +2354,12 @@ static int msm_anlg_cdc_codec_enable_spk_pa(struct snd_soc_dapm_widget *w,
 			MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, 0x01, 0x00);
 		snd_soc_update_bits(codec,
 			MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x10, 0x00);
-		if (get_codec_version(msmfalcon_cdc) != TOMBAK_1_0)
+		if (get_codec_version(sdm660_cdc) != TOMBAK_1_0)
 			snd_soc_update_bits(codec,
 				MSM89XX_PMIC_ANALOG_RX_EAR_CTL, 0x01, 0x00);
 		snd_soc_update_bits(codec,
 			MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
-		if (get_codec_version(msmfalcon_cdc) >= CAJON_2_0)
+		if (get_codec_version(sdm660_cdc) >= CAJON_2_0)
 			msm_anlg_cdc_boost_mode_sequence(codec, SPK_PMD);
 		break;
 	}
@@ -2371,7 +2371,7 @@ static int msm_anlg_cdc_codec_enable_dig_clk(struct snd_soc_dapm_widget *w,
 					     int event)
 {
 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 	struct msm_asoc_mach_data *pdata = NULL;
 
@@ -2385,7 +2385,7 @@ static int msm_anlg_cdc_codec_enable_dig_clk(struct snd_soc_dapm_widget *w,
 		snd_soc_update_bits(codec, w->reg, 0x80, 0x80);
 		break;
 	case SND_SOC_DAPM_POST_PMD:
-		if (msmfalcon_cdc->rx_bias_count == 0)
+		if (sdm660_cdc->rx_bias_count == 0)
 			snd_soc_update_bits(codec,
 					MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL,
 					0x80, 0x00);
@@ -2397,10 +2397,10 @@ static int msm_anlg_cdc_codec_enable_dig_clk(struct snd_soc_dapm_widget *w,
 
 static bool msm_anlg_cdc_use_mb(struct snd_soc_codec *codec)
 {
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
-	if (get_codec_version(msmfalcon_cdc) < CAJON)
+	if (get_codec_version(sdm660_cdc) < CAJON)
 		return true;
 	else
 		return false;
@@ -2409,10 +2409,10 @@ static bool msm_anlg_cdc_use_mb(struct snd_soc_codec *codec)
 static void msm_anlg_cdc_set_auto_zeroing(struct snd_soc_codec *codec,
 					  bool enable)
 {
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
-	if (get_codec_version(msmfalcon_cdc) < CONGA) {
+	if (get_codec_version(sdm660_cdc) < CONGA) {
 		if (enable)
 			/*
 			 * Set autozeroing for special headset detection and
@@ -2435,10 +2435,10 @@ static void msm_anlg_cdc_set_auto_zeroing(struct snd_soc_codec *codec,
 
 static void msm_anlg_cdc_trim_btn_reg(struct snd_soc_codec *codec)
 {
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
-	if (get_codec_version(msmfalcon_cdc) == TOMBAK_1_0) {
+	if (get_codec_version(sdm660_cdc) == TOMBAK_1_0) {
 		pr_debug("%s: This device needs to be trimmed\n", __func__);
 		/*
 		 * Calculate the trim value for each device used
@@ -2498,7 +2498,7 @@ static int msm_anlg_cdc_codec_enable_micbias(struct snd_soc_dapm_widget *w,
 					     int event)
 {
 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 				snd_soc_codec_get_drvdata(codec);
 	u16 micb_int_reg;
 	char *internal1_text = "Internal1";
@@ -2525,7 +2525,7 @@ static int msm_anlg_cdc_codec_enable_micbias(struct snd_soc_dapm_widget *w,
 	switch (event) {
 	case SND_SOC_DAPM_PRE_PMU:
 		if (strnstr(w->name, internal1_text, strlen(w->name))) {
-			if (get_codec_version(msmfalcon_cdc) >= CAJON)
+			if (get_codec_version(sdm660_cdc) >= CAJON)
 				snd_soc_update_bits(codec,
 					MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2,
 					0x02, 0x02);
@@ -2554,7 +2554,7 @@ static int msm_anlg_cdc_codec_enable_micbias(struct snd_soc_dapm_widget *w,
 
 		break;
 	case SND_SOC_DAPM_POST_PMU:
-		if (get_codec_version(msmfalcon_cdc) <= TOMBAK_2_0)
+		if (get_codec_version(sdm660_cdc) <= TOMBAK_2_0)
 			/*
 			 * Wait for 20ms post micbias enable
 			 * for version < tombak 2.0.
@@ -2599,7 +2599,7 @@ static int msm_anlg_cdc_codec_enable_micbias(struct snd_soc_dapm_widget *w,
 
 static void update_clkdiv(void *handle, int val)
 {
-	struct msmfalcon_cdc *handle_cdc = handle;
+	struct sdm660_cdc *handle_cdc = handle;
 	struct snd_soc_codec *codec = handle_cdc->codec;
 
 	snd_soc_update_bits(codec,
@@ -2609,24 +2609,24 @@ static void update_clkdiv(void *handle, int val)
 
 static int get_cdc_version(void *handle)
 {
-	struct msmfalcon_cdc *handle_cdc = handle;
+	struct sdm660_cdc *handle_cdc = handle;
 	struct snd_soc_codec *codec = handle_cdc->codec;
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
-	return get_codec_version(msmfalcon_cdc);
+	return get_codec_version(sdm660_cdc);
 }
 
-static int msmfalcon_wcd_codec_enable_vdd_spkr(struct snd_soc_dapm_widget *w,
+static int sdm660_wcd_codec_enable_vdd_spkr(struct snd_soc_dapm_widget *w,
 					       struct snd_kcontrol *kcontrol,
 					       int event)
 {
 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 	int ret = 0;
 
-	if (!msmfalcon_cdc->ext_spk_boost_set) {
+	if (!sdm660_cdc->ext_spk_boost_set) {
 		dev_dbg(codec->dev, "%s: ext_boost not supported/disabled\n",
 								__func__);
 		return 0;
@@ -2634,8 +2634,8 @@ static int msmfalcon_wcd_codec_enable_vdd_spkr(struct snd_soc_dapm_widget *w,
 	dev_dbg(codec->dev, "%s: %s %d\n", __func__, w->name, event);
 	switch (event) {
 	case SND_SOC_DAPM_PRE_PMU:
-		if (msmfalcon_cdc->spkdrv_reg) {
-			ret = regulator_enable(msmfalcon_cdc->spkdrv_reg);
+		if (sdm660_cdc->spkdrv_reg) {
+			ret = regulator_enable(sdm660_cdc->spkdrv_reg);
 			if (ret)
 				dev_err(codec->dev,
 					"%s Failed to enable spkdrv reg %s\n",
@@ -2643,8 +2643,8 @@ static int msmfalcon_wcd_codec_enable_vdd_spkr(struct snd_soc_dapm_widget *w,
 		}
 		break;
 	case SND_SOC_DAPM_POST_PMD:
-		if (msmfalcon_cdc->spkdrv_reg) {
-			ret = regulator_disable(msmfalcon_cdc->spkdrv_reg);
+		if (sdm660_cdc->spkdrv_reg) {
+			ret = regulator_disable(sdm660_cdc->spkdrv_reg);
 			if (ret)
 				dev_err(codec->dev,
 					"%s: Failed to disable spkdrv_reg %s\n",
@@ -2662,15 +2662,15 @@ static int msm_anlg_cdc_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
 					     int event)
 {
 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
 	dev_dbg(codec->dev, "%s %d\n", __func__, event);
 
 	switch (event) {
 	case SND_SOC_DAPM_PRE_PMU:
-		msmfalcon_cdc->rx_bias_count++;
-		if (msmfalcon_cdc->rx_bias_count == 1) {
+		sdm660_cdc->rx_bias_count++;
+		if (sdm660_cdc->rx_bias_count == 1) {
 			snd_soc_update_bits(codec,
 					MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC,
 					0x80, 0x80);
@@ -2680,8 +2680,8 @@ static int msm_anlg_cdc_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
 		}
 		break;
 	case SND_SOC_DAPM_POST_PMD:
-		msmfalcon_cdc->rx_bias_count--;
-		if (msmfalcon_cdc->rx_bias_count == 0) {
+		sdm660_cdc->rx_bias_count--;
+		if (sdm660_cdc->rx_bias_count == 0) {
 			snd_soc_update_bits(codec,
 					MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC,
 					0x01, 0x00);
@@ -2692,7 +2692,7 @@ static int msm_anlg_cdc_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
 		break;
 	}
 	dev_dbg(codec->dev, "%s rx_bias_count = %d\n",
-			__func__, msmfalcon_cdc->rx_bias_count);
+			__func__, sdm660_cdc->rx_bias_count);
 	return 0;
 }
 
@@ -2716,7 +2716,7 @@ static void wcd_imped_config(struct snd_soc_codec *codec,
 {
 	uint32_t value;
 	int codec_version;
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 				snd_soc_codec_get_drvdata(codec);
 
 	value = wcd_get_impedance_value(imped);
@@ -2728,7 +2728,7 @@ static void wcd_imped_config(struct snd_soc_codec *codec,
 		return;
 	}
 
-	codec_version = get_codec_version(msmfalcon_cdc);
+	codec_version = get_codec_version(sdm660_cdc);
 
 	if (set_gain) {
 		switch (codec_version) {
@@ -2789,22 +2789,22 @@ static int msm_anlg_cdc_hphl_dac_event(struct snd_soc_dapm_widget *w,
 {
 	uint32_t impedl, impedr;
 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 	int ret;
 
 	dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
-	ret = wcd_mbhc_get_impedance(&msmfalcon_cdc->mbhc,
+	ret = wcd_mbhc_get_impedance(&sdm660_cdc->mbhc,
 			&impedl, &impedr);
 
 	switch (event) {
 	case SND_SOC_DAPM_PRE_PMU:
-		if (get_codec_version(msmfalcon_cdc) > CAJON)
+		if (get_codec_version(sdm660_cdc) > CAJON)
 			snd_soc_update_bits(codec,
 				MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN,
 				0x08, 0x08);
-		if (get_codec_version(msmfalcon_cdc) == CAJON ||
-			get_codec_version(msmfalcon_cdc) == CAJON_2_0) {
+		if (get_codec_version(sdm660_cdc) == CAJON ||
+			get_codec_version(sdm660_cdc) == CAJON_2_0) {
 			snd_soc_update_bits(codec,
 				MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST,
 				0x80, 0x80);
@@ -2812,11 +2812,11 @@ static int msm_anlg_cdc_hphl_dac_event(struct snd_soc_dapm_widget *w,
 				MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST,
 				0x80, 0x80);
 		}
-		if (get_codec_version(msmfalcon_cdc) > CAJON)
+		if (get_codec_version(sdm660_cdc) > CAJON)
 			snd_soc_update_bits(codec,
 				MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN,
 				0x08, 0x00);
-		if (msmfalcon_cdc->hph_mode == HD2_MODE)
+		if (sdm660_cdc->hph_mode == HD2_MODE)
 			msm_anlg_cdc_dig_notifier_call(codec,
 					DIG_CDC_EVENT_PRE_RX1_INT_ON);
 		snd_soc_update_bits(codec,
@@ -2841,7 +2841,7 @@ static int msm_anlg_cdc_hphl_dac_event(struct snd_soc_dapm_widget *w,
 			MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
 		snd_soc_update_bits(codec,
 			MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x00);
-		if (msmfalcon_cdc->hph_mode == HD2_MODE)
+		if (sdm660_cdc->hph_mode == HD2_MODE)
 			msm_anlg_cdc_dig_notifier_call(codec,
 					DIG_CDC_EVENT_POST_RX1_INT_OFF);
 		break;
@@ -2905,14 +2905,14 @@ static int msm_anlg_cdc_hphr_dac_event(struct snd_soc_dapm_widget *w,
 				       int event)
 {
 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
 	dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event);
 
 	switch (event) {
 	case SND_SOC_DAPM_PRE_PMU:
-		if (msmfalcon_cdc->hph_mode == HD2_MODE)
+		if (sdm660_cdc->hph_mode == HD2_MODE)
 			msm_anlg_cdc_dig_notifier_call(codec,
 					DIG_CDC_EVENT_PRE_RX2_INT_ON);
 		snd_soc_update_bits(codec,
@@ -2931,7 +2931,7 @@ static int msm_anlg_cdc_hphr_dac_event(struct snd_soc_dapm_widget *w,
 			MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
 		snd_soc_update_bits(codec,
 			MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x00);
-		if (msmfalcon_cdc->hph_mode == HD2_MODE)
+		if (sdm660_cdc->hph_mode == HD2_MODE)
 			msm_anlg_cdc_dig_notifier_call(codec,
 					DIG_CDC_EVENT_POST_RX2_INT_OFF);
 		break;
@@ -2944,7 +2944,7 @@ static int msm_anlg_cdc_hph_pa_event(struct snd_soc_dapm_widget *w,
 				     int event)
 {
 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
 	dev_dbg(codec->dev, "%s: %s event = %d\n", __func__, w->name, event);
@@ -2997,7 +2997,7 @@ static int msm_anlg_cdc_hph_pa_event(struct snd_soc_dapm_widget *w,
 			msm_anlg_cdc_notifier_call(codec,
 					WCD_EVENT_PRE_HPHR_PA_OFF);
 		}
-		if (get_codec_version(msmfalcon_cdc) >= CAJON) {
+		if (get_codec_version(sdm660_cdc) >= CAJON) {
 			snd_soc_update_bits(codec,
 				MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_CNP,
 				0xF0, 0x30);
@@ -3006,12 +3006,12 @@ static int msm_anlg_cdc_hph_pa_event(struct snd_soc_dapm_widget *w,
 	case SND_SOC_DAPM_POST_PMD:
 		if (w->shift == 5) {
 			clear_bit(WCD_MBHC_HPHL_PA_OFF_ACK,
-				&msmfalcon_cdc->mbhc.hph_pa_dac_state);
+				&sdm660_cdc->mbhc.hph_pa_dac_state);
 			msm_anlg_cdc_notifier_call(codec,
 					WCD_EVENT_POST_HPHL_PA_OFF);
 		} else if (w->shift == 4) {
 			clear_bit(WCD_MBHC_HPHR_PA_OFF_ACK,
-				&msmfalcon_cdc->mbhc.hph_pa_dac_state);
+				&sdm660_cdc->mbhc.hph_pa_dac_state);
 			msm_anlg_cdc_notifier_call(codec,
 					WCD_EVENT_POST_HPHR_PA_OFF);
 		}
@@ -3106,7 +3106,7 @@ static const struct snd_soc_dapm_route audio_map[] = {
 static int msm_anlg_cdc_startup(struct snd_pcm_substream *substream,
 				struct snd_soc_dai *dai)
 {
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 		snd_soc_codec_get_drvdata(dai->codec);
 
 	dev_dbg(dai->codec->dev, "%s(): substream = %s  stream = %d\n",
@@ -3116,7 +3116,7 @@ static int msm_anlg_cdc_startup(struct snd_pcm_substream *substream,
 	 * If status_mask is BUS_DOWN it means SSR is not complete.
 	 * So return error.
 	 */
-	if (test_bit(BUS_DOWN, &msmfalcon_cdc->status_mask)) {
+	if (test_bit(BUS_DOWN, &sdm660_cdc->status_mask)) {
 		dev_err(dai->codec->dev, "Error, Device is not up post SSR\n");
 		return -EINVAL;
 	}
@@ -3134,20 +3134,20 @@ static void msm_anlg_cdc_shutdown(struct snd_pcm_substream *substream,
 int msm_anlg_cdc_mclk_enable(struct snd_soc_codec *codec,
 			     int mclk_enable, bool dapm)
 {
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
 	dev_dbg(codec->dev, "%s: mclk_enable = %u, dapm = %d\n",
 		__func__, mclk_enable, dapm);
 	if (mclk_enable) {
-		msmfalcon_cdc->int_mclk0_enabled = true;
+		sdm660_cdc->int_mclk0_enabled = true;
 		msm_anlg_cdc_codec_enable_clock_block(codec, 1);
 	} else {
-		if (!msmfalcon_cdc->int_mclk0_enabled) {
+		if (!sdm660_cdc->int_mclk0_enabled) {
 			dev_err(codec->dev, "Error, MCLK already diabled\n");
 			return -EINVAL;
 		}
-		msmfalcon_cdc->int_mclk0_enabled = false;
+		sdm660_cdc->int_mclk0_enabled = false;
 		msm_anlg_cdc_codec_enable_clock_block(codec, 0);
 	}
 	return 0;
@@ -3199,8 +3199,8 @@ static struct snd_soc_dai_driver msm_anlg_cdc_i2s_dai[] = {
 		.id = AIF1_PB,
 		.playback = {
 			.stream_name = "Playback",
-			.rates = MSMFALCON_CDC_RATES,
-			.formats = MSMFALCON_CDC_FORMATS,
+			.rates = SDM660_CDC_RATES,
+			.formats = SDM660_CDC_FORMATS,
 			.rate_max = 192000,
 			.rate_min = 8000,
 			.channels_min = 1,
@@ -3213,8 +3213,8 @@ static struct snd_soc_dai_driver msm_anlg_cdc_i2s_dai[] = {
 		.id = AIF1_CAP,
 		.capture = {
 			.stream_name = "Record",
-			.rates = MSMFALCON_CDC_RATES,
-			.formats = MSMFALCON_CDC_FORMATS,
+			.rates = SDM660_CDC_RATES,
+			.formats = SDM660_CDC_FORMATS,
 			.rate_max = 48000,
 			.rate_min = 8000,
 			.channels_min = 1,
@@ -3227,8 +3227,8 @@ static struct snd_soc_dai_driver msm_anlg_cdc_i2s_dai[] = {
 		.id = AIF3_SVA,
 		.capture = {
 			.stream_name = "RecordSVA",
-			.rates = MSMFALCON_CDC_RATES,
-			.formats = MSMFALCON_CDC_FORMATS,
+			.rates = SDM660_CDC_RATES,
+			.formats = SDM660_CDC_FORMATS,
 			.rate_max = 48000,
 			.rate_min = 8000,
 			.channels_min = 1,
@@ -3241,8 +3241,8 @@ static struct snd_soc_dai_driver msm_anlg_cdc_i2s_dai[] = {
 		.id = AIF2_VIFEED,
 		.capture = {
 			.stream_name = "VIfeed",
-			.rates = MSMFALCON_CDC_RATES,
-			.formats = MSMFALCON_CDC_FORMATS,
+			.rates = SDM660_CDC_RATES,
+			.formats = SDM660_CDC_FORMATS,
 			.rate_max = 48000,
 			.rate_min = 48000,
 			.channels_min = 2,
@@ -3279,7 +3279,7 @@ static int msm_anlg_cdc_codec_enable_spk_ext_pa(struct snd_soc_dapm_widget *w,
 						int event)
 {
 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
 	dev_dbg(codec->dev, "%s: %s event = %d\n", __func__, w->name, event);
@@ -3287,14 +3287,14 @@ static int msm_anlg_cdc_codec_enable_spk_ext_pa(struct snd_soc_dapm_widget *w,
 	case SND_SOC_DAPM_POST_PMU:
 		dev_dbg(codec->dev,
 			"%s: enable external speaker PA\n", __func__);
-		if (msmfalcon_cdc->codec_spk_ext_pa_cb)
-			msmfalcon_cdc->codec_spk_ext_pa_cb(codec, 1);
+		if (sdm660_cdc->codec_spk_ext_pa_cb)
+			sdm660_cdc->codec_spk_ext_pa_cb(codec, 1);
 		break;
 	case SND_SOC_DAPM_PRE_PMD:
 		dev_dbg(codec->dev,
 			"%s: enable external speaker PA\n", __func__);
-		if (msmfalcon_cdc->codec_spk_ext_pa_cb)
-			msmfalcon_cdc->codec_spk_ext_pa_cb(codec, 0);
+		if (sdm660_cdc->codec_spk_ext_pa_cb)
+			sdm660_cdc->codec_spk_ext_pa_cb(codec, 0);
 		break;
 	}
 	return 0;
@@ -3305,7 +3305,7 @@ static int msm_anlg_cdc_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
 					    int event)
 {
 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
 	switch (event) {
@@ -3315,10 +3315,10 @@ static int msm_anlg_cdc_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
 			__func__);
 		snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_EAR_CTL,
 			    0x80, 0x80);
-		if (get_codec_version(msmfalcon_cdc) < CONGA)
+		if (get_codec_version(sdm660_cdc) < CONGA)
 			snd_soc_update_bits(codec,
 			MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME, 0xFF, 0x2A);
-		if (get_codec_version(msmfalcon_cdc) >= DIANGU) {
+		if (get_codec_version(sdm660_cdc) >= DIANGU) {
 			snd_soc_update_bits(codec,
 			MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, 0x08, 0x00);
 			snd_soc_update_bits(codec,
@@ -3343,13 +3343,13 @@ static int msm_anlg_cdc_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
 				       DIG_CDC_EVENT_RX1_MUTE_ON);
 		/* Wait for 20ms for RX digital mute to take effect */
 		msleep(20);
-		if (msmfalcon_cdc->boost_option == BOOST_ALWAYS) {
+		if (sdm660_cdc->boost_option == BOOST_ALWAYS) {
 			dev_dbg(codec->dev,
 				"%s: boost_option:%d, tear down ear\n",
-				__func__, msmfalcon_cdc->boost_option);
+				__func__, sdm660_cdc->boost_option);
 			msm_anlg_cdc_boost_mode_sequence(codec, EAR_PMD);
 		}
-		if (get_codec_version(msmfalcon_cdc) >= DIANGU) {
+		if (get_codec_version(sdm660_cdc) >= DIANGU) {
 			snd_soc_update_bits(codec,
 				MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST, 0x04, 0x0);
 			snd_soc_update_bits(codec,
@@ -3364,10 +3364,10 @@ static int msm_anlg_cdc_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
 			    0x40, 0x00);
 		/* Wait for 7ms after EAR PA teardown */
 		usleep_range(7000, 7100);
-		if (get_codec_version(msmfalcon_cdc) < CONGA)
+		if (get_codec_version(sdm660_cdc) < CONGA)
 			snd_soc_update_bits(codec,
 			MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME, 0xFF, 0x16);
-		if (get_codec_version(msmfalcon_cdc) >= DIANGU)
+		if (get_codec_version(sdm660_cdc) >= DIANGU)
 			snd_soc_update_bits(codec,
 			MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, 0x08, 0x08);
 		break;
@@ -3452,7 +3452,7 @@ static const struct snd_soc_dapm_widget msm_anlg_cdc_dapm_widgets[] = {
 		msm_anlg_cdc_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU |
 		SND_SOC_DAPM_POST_PMD),
 	SND_SOC_DAPM_SUPPLY("VDD_SPKDRV", SND_SOC_NOPM, 0, 0,
-			    msmfalcon_wcd_codec_enable_vdd_spkr,
+			    sdm660_wcd_codec_enable_vdd_spkr,
 			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 	SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0),
 	SND_SOC_DAPM_SUPPLY("MICBIAS_REGULATOR", SND_SOC_NOPM,
@@ -3512,13 +3512,13 @@ static const struct snd_soc_dapm_widget msm_anlg_cdc_dapm_widgets[] = {
 	SND_SOC_DAPM_OUTPUT("ADC3_OUT"),
 };
 
-static const struct msmfalcon_cdc_reg_mask_val msm_anlg_cdc_reg_defaults[] = {
+static const struct sdm660_cdc_reg_mask_val msm_anlg_cdc_reg_defaults[] = {
 	MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x03),
 	MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0x82),
 	MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL, 0xE1),
 };
 
-static const struct msmfalcon_cdc_reg_mask_val
+static const struct sdm660_cdc_reg_mask_val
 					msm_anlg_cdc_reg_defaults_2_0[] = {
 	MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_SEC_ACCESS, 0xA5),
 	MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x0F),
@@ -3536,7 +3536,7 @@ static const struct msmfalcon_cdc_reg_mask_val
 	MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x80),
 };
 
-static const struct msmfalcon_cdc_reg_mask_val conga_wcd_reg_defaults[] = {
+static const struct sdm660_cdc_reg_mask_val conga_wcd_reg_defaults[] = {
 	MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_SEC_ACCESS, 0xA5),
 	MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x0F),
 	MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0xA5),
@@ -3551,7 +3551,7 @@ static const struct msmfalcon_cdc_reg_mask_val conga_wcd_reg_defaults[] = {
 	MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x80),
 };
 
-static const struct msmfalcon_cdc_reg_mask_val cajon_wcd_reg_defaults[] = {
+static const struct sdm660_cdc_reg_mask_val cajon_wcd_reg_defaults[] = {
 	MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_SEC_ACCESS, 0xA5),
 	MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x0F),
 	MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0xA5),
@@ -3569,7 +3569,7 @@ static const struct msmfalcon_cdc_reg_mask_val cajon_wcd_reg_defaults[] = {
 	MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x80),
 };
 
-static const struct msmfalcon_cdc_reg_mask_val cajon2p0_wcd_reg_defaults[] = {
+static const struct sdm660_cdc_reg_mask_val cajon2p0_wcd_reg_defaults[] = {
 	MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_SEC_ACCESS, 0xA5),
 	MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x0F),
 	MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0xA5),
@@ -3592,10 +3592,10 @@ static const struct msmfalcon_cdc_reg_mask_val cajon2p0_wcd_reg_defaults[] = {
 static void msm_anlg_cdc_update_reg_defaults(struct snd_soc_codec *codec)
 {
 	u32 i, version;
-	struct msmfalcon_cdc_priv *msmfalcon_cdc =
+	struct sdm660_cdc_priv *sdm660_cdc =
 					snd_soc_codec_get_drvdata(codec);
 
-	version = get_codec_version(msmfalcon_cdc);
+	version = get_codec_version(sdm660_cdc);
 	if (version == TOMBAK_1_0) {
 		for (i = 0; i < ARRAY_SIZE(msm_anlg_cdc_reg_defaults); i++)
 			snd_soc_write(codec, msm_anlg_cdc_reg_defaults[i].reg,
@@ -3624,7 +3624,7 @@ static void msm_anlg_cdc_update_reg_defaults(struct snd_soc_codec *codec)
 	}
 }
 
-static const struct msmfalcon_cdc_reg_mask_val
+static const struct sdm660_cdc_reg_mask_val
 	msm_anlg_cdc_codec_reg_init_val[] = {
 
 	/* Initialize current threshold to 350MA
@@ -3679,18 +3679,18 @@ static int msm_anlg_cdc_bringup(struct snd_soc_codec *codec)
 }
 
 static struct regulator *msm_anlg_cdc_find_regulator(
-				const struct msmfalcon_cdc *msmfalcon_cdc,
+				const struct sdm660_cdc *sdm660_cdc,
 				const char *name)
 {
 	int i;
 
-	for (i = 0; i < msmfalcon_cdc->num_of_supplies; i++) {
-		if (msmfalcon_cdc->supplies[i].supply &&
-		    !strcmp(msmfalcon_cdc->supplies[i].supply, name))
-			return msmfalcon_cdc->supplies[i].consumer;
+	for (i = 0; i < sdm660_cdc->num_of_supplies; i++) {
+		if (sdm660_cdc->supplies[i].supply &&
+		    !strcmp(sdm660_cdc->supplies[i].supply, name))
+			return sdm660_cdc->supplies[i].consumer;
 	}
 
-	dev_err(msmfalcon_cdc->dev, "Error: regulator not found:%s\n"
+	dev_err(sdm660_cdc->dev, "Error: regulator not found:%s\n"
 				, name);
 	return NULL;
 }
@@ -3698,7 +3698,7 @@ static struct regulator *msm_anlg_cdc_find_regulator(
 static int msm_anlg_cdc_device_down(struct snd_soc_codec *codec)
 {
 	struct msm_asoc_mach_data *pdata = NULL;
-	struct msmfalcon_cdc_priv *msmfalcon_cdc_priv =
+	struct sdm660_cdc_priv *sdm660_cdc_priv =
 		snd_soc_codec_get_drvdata(codec);
 	unsigned int tx_1_en;
 	unsigned int tx_2_en;
@@ -3714,7 +3714,7 @@ static int msm_anlg_cdc_device_down(struct snd_soc_codec *codec)
 		MSM89XX_PMIC_ANALOG_TX_1_EN, tx_1_en);
 	snd_soc_write(codec,
 		MSM89XX_PMIC_ANALOG_TX_2_EN, tx_2_en);
-	if (msmfalcon_cdc_priv->boost_option == BOOST_ON_FOREVER) {
+	if (sdm660_cdc_priv->boost_option == BOOST_ON_FOREVER) {
 		if ((snd_soc_read(codec, MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL)
 			& 0x80) == 0) {
 			msm_anlg_cdc_dig_notifier_call(codec,
@@ -3752,7 +3752,7 @@ static int msm_anlg_cdc_device_down(struct snd_soc_codec *codec)
 		}
 	}
 	msm_anlg_cdc_boost_off(codec);
-	msmfalcon_cdc_priv->hph_mode = NORMAL_MODE;
+	sdm660_cdc_priv->hph_mode = NORMAL_MODE;
 
 	/* 40ms to allow boost to discharge */
 	msleep(40);
@@ -3773,21 +3773,21 @@ static int msm_anlg_cdc_device_down(struct snd_soc_codec *codec)
 	msm_anlg_cdc_bringup(codec);
 	atomic_set(&pdata->int_mclk0_enabled, false);
 	msm_anlg_cdc_dig_notifier_call(codec, DIG_CDC_EVENT_SSR_DOWN);
-	set_bit(BUS_DOWN, &msmfalcon_cdc_priv->status_mask);
+	set_bit(BUS_DOWN, &sdm660_cdc_priv->status_mask);
 	snd_soc_card_change_online_state(codec->component.card, 0);
 	return 0;
 }
 
 static int msm_anlg_cdc_device_up(struct snd_soc_codec *codec)
 {
-	struct msmfalcon_cdc_priv *msmfalcon_cdc_priv =
+	struct sdm660_cdc_priv *sdm660_cdc_priv =
 		snd_soc_codec_get_drvdata(codec);
 	int ret = 0;
 
 	dev_dbg(codec->dev, "%s: device up!\n", __func__);
 
 	msm_anlg_cdc_dig_notifier_call(codec, DIG_CDC_EVENT_SSR_UP);
-	clear_bit(BUS_DOWN, &msmfalcon_cdc_priv->status_mask);
+	clear_bit(BUS_DOWN, &sdm660_cdc_priv->status_mask);
 	snd_soc_card_change_online_state(codec->component.card, 1);
 	/* delay is required to make sure sound card state updated */
 	usleep_range(5000, 5100);
@@ -3807,38 +3807,38 @@ static int msm_anlg_cdc_device_up(struct snd_soc_codec *codec)
 
 	msm_anlg_cdc_set_boost_v(codec);
 	msm_anlg_cdc_set_micb_v(codec);
-	if (msmfalcon_cdc_priv->boost_option == BOOST_ON_FOREVER)
+	if (sdm660_cdc_priv->boost_option == BOOST_ON_FOREVER)
 		msm_anlg_cdc_boost_on(codec);
-	else if (msmfalcon_cdc_priv->boost_option == BYPASS_ALWAYS)
+	else if (sdm660_cdc_priv->boost_option == BYPASS_ALWAYS)
 		msm_anlg_cdc_bypass_on(codec);
 
 	msm_anlg_cdc_configure_cap(codec, false, false);
-	wcd_mbhc_stop(&msmfalcon_cdc_priv->mbhc);
-	wcd_mbhc_deinit(&msmfalcon_cdc_priv->mbhc);
-	ret = wcd_mbhc_init(&msmfalcon_cdc_priv->mbhc, codec, &mbhc_cb,
+	wcd_mbhc_stop(&sdm660_cdc_priv->mbhc);
+	wcd_mbhc_deinit(&sdm660_cdc_priv->mbhc);
+	ret = wcd_mbhc_init(&sdm660_cdc_priv->mbhc, codec, &mbhc_cb,
 			    &intr_ids, wcd_mbhc_registers, true);
 	if (ret)
 		dev_err(codec->dev, "%s: mbhc initialization failed\n",
 			__func__);
 	else
-		wcd_mbhc_start(&msmfalcon_cdc_priv->mbhc,
-			msmfalcon_cdc_priv->mbhc.mbhc_cfg);
+		wcd_mbhc_start(&sdm660_cdc_priv->mbhc,
+			sdm660_cdc_priv->mbhc.mbhc_cfg);
 
 	return 0;
 }
 
-static int msmfalcon_cdc_notifier_service_cb(struct notifier_block *nb,
+static int sdm660_cdc_notifier_service_cb(struct notifier_block *nb,
 					     unsigned long opcode, void *ptr)
 {
 	struct snd_soc_codec *codec;
-	struct msmfalcon_cdc_priv *msmfalcon_cdc_priv =
-				container_of(nb, struct msmfalcon_cdc_priv,
+	struct sdm660_cdc_priv *sdm660_cdc_priv =
+				container_of(nb, struct sdm660_cdc_priv,
 					     audio_ssr_nb);
 	bool adsp_ready = false;
 	bool timedout;
 	unsigned long timeout;
 
-	codec = msmfalcon_cdc_priv->codec;
+	codec = sdm660_cdc_priv->codec;
 	dev_dbg(codec->dev, "%s: Service opcode 0x%lx\n", __func__, opcode);
 
 	switch (opcode) {
@@ -3888,19 +3888,19 @@ powerup:
 int msm_anlg_cdc_hs_detect(struct snd_soc_codec *codec,
 			   struct wcd_mbhc_config *mbhc_cfg)
 {
-	struct msmfalcon_cdc_priv *msmfalcon_cdc_priv =
+	struct sdm660_cdc_priv *sdm660_cdc_priv =
 		snd_soc_codec_get_drvdata(codec);
 
-	return wcd_mbhc_start(&msmfalcon_cdc_priv->mbhc, mbhc_cfg);
+	return wcd_mbhc_start(&sdm660_cdc_priv->mbhc, mbhc_cfg);
 }
 EXPORT_SYMBOL(msm_anlg_cdc_hs_detect);
 
 void msm_anlg_cdc_hs_detect_exit(struct snd_soc_codec *codec)
 {
-	struct msmfalcon_cdc_priv *msmfalcon_cdc_priv =
+	struct sdm660_cdc_priv *sdm660_cdc_priv =
 		snd_soc_codec_get_drvdata(codec);
 
-	wcd_mbhc_stop(&msmfalcon_cdc_priv->mbhc);
+	wcd_mbhc_stop(&sdm660_cdc_priv->mbhc);
 }
 EXPORT_SYMBOL(msm_anlg_cdc_hs_detect_exit);
 
@@ -3914,8 +3914,8 @@ EXPORT_SYMBOL(msm_anlg_cdc_update_int_spk_boost);
 static void msm_anlg_cdc_set_micb_v(struct snd_soc_codec *codec)
 {
 
-	struct msmfalcon_cdc *msmfalcon_cdc = codec->control_data;
-	struct msmfalcon_cdc_pdata *pdata = msmfalcon_cdc->dev->platform_data;
+	struct sdm660_cdc *sdm660_cdc = codec->control_data;
+	struct sdm660_cdc_pdata *pdata = sdm660_cdc->dev->platform_data;
 	u8 reg_val;
 
 	reg_val = VOLTAGE_CONVERTER(pdata->micbias.cfilt1_mv, MICBIAS_MIN_VAL,
@@ -3928,11 +3928,11 @@ static void msm_anlg_cdc_set_micb_v(struct snd_soc_codec *codec)
 
 static void msm_anlg_cdc_set_boost_v(struct snd_soc_codec *codec)
 {
-	struct msmfalcon_cdc_priv *msmfalcon_cdc_priv =
+	struct sdm660_cdc_priv *sdm660_cdc_priv =
 				snd_soc_codec_get_drvdata(codec);
 
 	snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_OUTPUT_VOLTAGE,
-			0x1F, msmfalcon_cdc_priv->boost_voltage);
+			0x1F, sdm660_cdc_priv->boost_voltage);
 }
 
 static void msm_anlg_cdc_configure_cap(struct snd_soc_codec *codec,
@@ -3975,17 +3975,17 @@ static ssize_t msm_anlg_codec_version_read(struct snd_info_entry *entry,
 					   char __user *buf, size_t count,
 					   loff_t pos)
 {
-	struct msmfalcon_cdc_priv *msmfalcon_cdc_priv;
+	struct sdm660_cdc_priv *sdm660_cdc_priv;
 	char buffer[MSM_ANLG_CDC_VERSION_ENTRY_SIZE];
 	int len = 0;
 
-	msmfalcon_cdc_priv = (struct msmfalcon_cdc_priv *) entry->private_data;
-	if (!msmfalcon_cdc_priv) {
-		pr_err("%s: msmfalcon_cdc_priv is null\n", __func__);
+	sdm660_cdc_priv = (struct sdm660_cdc_priv *) entry->private_data;
+	if (!sdm660_cdc_priv) {
+		pr_err("%s: sdm660_cdc_priv is null\n", __func__);
 		return -EINVAL;
 	}
 
-	switch (get_codec_version(msmfalcon_cdc_priv)) {
+	switch (get_codec_version(sdm660_cdc_priv)) {
 	case DRAX_CDC:
 	    len = snprintf(buffer, sizeof(buffer), "DRAX_CDC_1_0\n");
 	    break;
@@ -4014,18 +4014,18 @@ int msm_anlg_codec_info_create_codec_entry(struct snd_info_entry *codec_root,
 					   struct snd_soc_codec *codec)
 {
 	struct snd_info_entry *version_entry;
-	struct msmfalcon_cdc_priv *msmfalcon_cdc_priv;
+	struct sdm660_cdc_priv *sdm660_cdc_priv;
 	struct snd_soc_card *card;
 
 	if (!codec_root || !codec)
 		return -EINVAL;
 
-	msmfalcon_cdc_priv = snd_soc_codec_get_drvdata(codec);
+	sdm660_cdc_priv = snd_soc_codec_get_drvdata(codec);
 	card = codec->component.card;
-	msmfalcon_cdc_priv->entry = snd_register_module_info(codec_root->module,
+	sdm660_cdc_priv->entry = snd_register_module_info(codec_root->module,
 							     "pmic_analog",
 							     codec_root);
-	if (!msmfalcon_cdc_priv->entry) {
+	if (!sdm660_cdc_priv->entry) {
 		dev_dbg(codec->dev, "%s: failed to create pmic_analog entry\n",
 			__func__);
 		return -ENOMEM;
@@ -4033,14 +4033,14 @@ int msm_anlg_codec_info_create_codec_entry(struct snd_info_entry *codec_root,
 
 	version_entry = snd_info_create_card_entry(card->snd_card,
 						   "version",
-						   msmfalcon_cdc_priv->entry);
+						   sdm660_cdc_priv->entry);
 	if (!version_entry) {
 		dev_dbg(codec->dev, "%s: failed to create pmic_analog version entry\n",
 			__func__);
 		return -ENOMEM;
 	}
 
-	version_entry->private_data = msmfalcon_cdc_priv;
+	version_entry->private_data = sdm660_cdc_priv;
 	version_entry->size = MSM_ANLG_CDC_VERSION_ENTRY_SIZE;
 	version_entry->content = SNDRV_INFO_CONTENT_DATA;
 	version_entry->c.ops = &msm_anlg_codec_info_ops;
@@ -4049,70 +4049,70 @@ int msm_anlg_codec_info_create_codec_entry(struct snd_info_entry *codec_root,
 		snd_info_free_entry(version_entry);
 		return -ENOMEM;
 	}
-	msmfalcon_cdc_priv->version_entry = version_entry;
+	sdm660_cdc_priv->version_entry = version_entry;
 	return 0;
 }
 EXPORT_SYMBOL(msm_anlg_codec_info_create_codec_entry);
 
 static int msm_anlg_cdc_soc_probe(struct snd_soc_codec *codec)
 {
-	struct msmfalcon_cdc_priv *msmfalcon_cdc_priv;
-	struct msmfalcon_cdc *handle_cdc;
+	struct sdm660_cdc_priv *sdm660_cdc_priv;
+	struct sdm660_cdc *handle_cdc;
 	int ret;
 
-	msmfalcon_cdc_priv = devm_kzalloc(codec->dev,
-					  sizeof(struct msmfalcon_cdc_priv),
+	sdm660_cdc_priv = devm_kzalloc(codec->dev,
+					  sizeof(struct sdm660_cdc_priv),
 					  GFP_KERNEL);
-	if (!msmfalcon_cdc_priv)
+	if (!sdm660_cdc_priv)
 		return -ENOMEM;
 
 	codec->control_data = dev_get_drvdata(codec->dev);
-	snd_soc_codec_set_drvdata(codec, msmfalcon_cdc_priv);
-	msmfalcon_cdc_priv->codec = codec;
+	snd_soc_codec_set_drvdata(codec, sdm660_cdc_priv);
+	sdm660_cdc_priv->codec = codec;
 	handle_cdc = codec->control_data;
 	handle_cdc->codec = codec;
 
 	/* codec resmgr module init */
-	msmfalcon_cdc_priv->spkdrv_reg =
+	sdm660_cdc_priv->spkdrv_reg =
 				msm_anlg_cdc_find_regulator(codec->control_data,
 						MSM89XX_VDD_SPKDRV_NAME);
-	msmfalcon_cdc_priv->pmic_rev =
+	sdm660_cdc_priv->pmic_rev =
 				snd_soc_read(codec,
 					     MSM89XX_PMIC_DIGITAL_REVISION1);
-	msmfalcon_cdc_priv->codec_version =
+	sdm660_cdc_priv->codec_version =
 				snd_soc_read(codec,
 					MSM89XX_PMIC_DIGITAL_PERPH_SUBTYPE);
-	msmfalcon_cdc_priv->analog_major_rev =
+	sdm660_cdc_priv->analog_major_rev =
 				snd_soc_read(codec,
 					     MSM89XX_PMIC_ANALOG_REVISION4);
 
-	if (msmfalcon_cdc_priv->codec_version == CONGA) {
+	if (sdm660_cdc_priv->codec_version == CONGA) {
 		dev_dbg(codec->dev, "%s :Conga REV: %d\n", __func__,
-					msmfalcon_cdc_priv->codec_version);
-		msmfalcon_cdc_priv->ext_spk_boost_set = true;
+					sdm660_cdc_priv->codec_version);
+		sdm660_cdc_priv->ext_spk_boost_set = true;
 	} else {
 		dev_dbg(codec->dev, "%s :PMIC REV: %d\n", __func__,
-					msmfalcon_cdc_priv->pmic_rev);
-		if (msmfalcon_cdc_priv->pmic_rev == TOMBAK_1_0 &&
-			msmfalcon_cdc_priv->codec_version == CAJON_2_0) {
-			if (msmfalcon_cdc_priv->analog_major_rev == 0x02) {
-				msmfalcon_cdc_priv->codec_version = DRAX_CDC;
+					sdm660_cdc_priv->pmic_rev);
+		if (sdm660_cdc_priv->pmic_rev == TOMBAK_1_0 &&
+			sdm660_cdc_priv->codec_version == CAJON_2_0) {
+			if (sdm660_cdc_priv->analog_major_rev == 0x02) {
+				sdm660_cdc_priv->codec_version = DRAX_CDC;
 				dev_dbg(codec->dev,
 					"%s : Drax codec detected\n", __func__);
 			} else {
-				msmfalcon_cdc_priv->codec_version = DIANGU;
+				sdm660_cdc_priv->codec_version = DIANGU;
 				dev_dbg(codec->dev, "%s : Diangu detected\n",
 					__func__);
 			}
-		} else if (msmfalcon_cdc_priv->pmic_rev == TOMBAK_1_0 &&
+		} else if (sdm660_cdc_priv->pmic_rev == TOMBAK_1_0 &&
 			(snd_soc_read(codec, MSM89XX_PMIC_ANALOG_NCP_FBCTRL)
 			 & 0x80)) {
-			msmfalcon_cdc_priv->codec_version = CAJON;
+			sdm660_cdc_priv->codec_version = CAJON;
 			dev_dbg(codec->dev, "%s : Cajon detected\n", __func__);
-		} else if (msmfalcon_cdc_priv->pmic_rev == TOMBAK_2_0 &&
+		} else if (sdm660_cdc_priv->pmic_rev == TOMBAK_2_0 &&
 			(snd_soc_read(codec, MSM89XX_PMIC_ANALOG_NCP_FBCTRL)
 			 & 0x80)) {
-			msmfalcon_cdc_priv->codec_version = CAJON_2_0;
+			sdm660_cdc_priv->codec_version = CAJON_2_0;
 			dev_dbg(codec->dev, "%s : Cajon 2.0 detected\n",
 						__func__);
 		}
@@ -4121,8 +4121,8 @@ static int msm_anlg_cdc_soc_probe(struct snd_soc_codec *codec)
 	 * set to default boost option BOOST_SWITCH, user mixer path can change
 	 * it to BOOST_ALWAYS or BOOST_BYPASS based on solution chosen.
 	 */
-	msmfalcon_cdc_priv->boost_option = BOOST_SWITCH;
-	msmfalcon_cdc_priv->hph_mode = NORMAL_MODE;
+	sdm660_cdc_priv->boost_option = BOOST_SWITCH;
+	sdm660_cdc_priv->hph_mode = NORMAL_MODE;
 
 	msm_anlg_cdc_dt_parse_boost_info(codec);
 	msm_anlg_cdc_set_boost_v(codec);
@@ -4139,52 +4139,52 @@ static int msm_anlg_cdc_soc_probe(struct snd_soc_codec *codec)
 
 	wcd9xxx_spmi_set_codec(codec);
 
-	msmfalcon_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].supply =
+	sdm660_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].supply =
 				msm_anlg_cdc_find_regulator(
 				codec->control_data,
 				on_demand_supply_name[ON_DEMAND_MICBIAS]);
-	atomic_set(&msmfalcon_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].ref,
+	atomic_set(&sdm660_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].ref,
 		   0);
 
-	BLOCKING_INIT_NOTIFIER_HEAD(&msmfalcon_cdc_priv->notifier);
+	BLOCKING_INIT_NOTIFIER_HEAD(&sdm660_cdc_priv->notifier);
 
-	msmfalcon_cdc_priv->fw_data = devm_kzalloc(codec->dev,
-					sizeof(*(msmfalcon_cdc_priv->fw_data)),
+	sdm660_cdc_priv->fw_data = devm_kzalloc(codec->dev,
+					sizeof(*(sdm660_cdc_priv->fw_data)),
 					GFP_KERNEL);
-	if (!msmfalcon_cdc_priv->fw_data)
+	if (!sdm660_cdc_priv->fw_data)
 		return -ENOMEM;
 
-	set_bit(WCD9XXX_MBHC_CAL, msmfalcon_cdc_priv->fw_data->cal_bit);
-	ret = wcd_cal_create_hwdep(msmfalcon_cdc_priv->fw_data,
+	set_bit(WCD9XXX_MBHC_CAL, sdm660_cdc_priv->fw_data->cal_bit);
+	ret = wcd_cal_create_hwdep(sdm660_cdc_priv->fw_data,
 			WCD9XXX_CODEC_HWDEP_NODE, codec);
 	if (ret < 0) {
 		dev_err(codec->dev, "%s hwdep failed %d\n", __func__, ret);
 		return ret;
 	}
 
-	wcd_mbhc_init(&msmfalcon_cdc_priv->mbhc, codec, &mbhc_cb, &intr_ids,
+	wcd_mbhc_init(&sdm660_cdc_priv->mbhc, codec, &mbhc_cb, &intr_ids,
 		      wcd_mbhc_registers, true);
 
-	msmfalcon_cdc_priv->int_mclk0_enabled = false;
+	sdm660_cdc_priv->int_mclk0_enabled = false;
 	/*Update speaker boost configuration*/
-	msmfalcon_cdc_priv->spk_boost_set = spkr_boost_en;
+	sdm660_cdc_priv->spk_boost_set = spkr_boost_en;
 	pr_debug("%s: speaker boost configured = %d\n",
-			__func__, msmfalcon_cdc_priv->spk_boost_set);
+			__func__, sdm660_cdc_priv->spk_boost_set);
 
 	/* Set initial MICBIAS voltage level */
 	msm_anlg_cdc_set_micb_v(codec);
 
 	/* Set initial cap mode */
 	msm_anlg_cdc_configure_cap(codec, false, false);
-	msmfalcon_cdc_priv->audio_ssr_nb.notifier_call =
-				msmfalcon_cdc_notifier_service_cb;
+	sdm660_cdc_priv->audio_ssr_nb.notifier_call =
+				sdm660_cdc_notifier_service_cb;
 	ret = audio_notifier_register("pmic_analog_cdc",
 				      AUDIO_NOTIFIER_ADSP_DOMAIN,
-				      &msmfalcon_cdc_priv->audio_ssr_nb);
+				      &sdm660_cdc_priv->audio_ssr_nb);
 	if (ret < 0) {
 		pr_err("%s: Audio notifier register failed ret = %d\n",
 			__func__, ret);
-		wcd_mbhc_deinit(&msmfalcon_cdc_priv->mbhc);
+		wcd_mbhc_deinit(&sdm660_cdc_priv->mbhc);
 		return ret;
 	}
 	return 0;
@@ -4192,69 +4192,69 @@ static int msm_anlg_cdc_soc_probe(struct snd_soc_codec *codec)
 
 static int msm_anlg_cdc_soc_remove(struct snd_soc_codec *codec)
 {
-	struct msmfalcon_cdc_priv *msmfalcon_cdc_priv =
+	struct sdm660_cdc_priv *sdm660_cdc_priv =
 					snd_soc_codec_get_drvdata(codec);
 
-	msmfalcon_cdc_priv->spkdrv_reg = NULL;
-	msmfalcon_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].supply = NULL;
-	atomic_set(&msmfalcon_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].ref,
+	sdm660_cdc_priv->spkdrv_reg = NULL;
+	sdm660_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].supply = NULL;
+	atomic_set(&sdm660_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].ref,
 		   0);
-	wcd_mbhc_deinit(&msmfalcon_cdc_priv->mbhc);
+	wcd_mbhc_deinit(&sdm660_cdc_priv->mbhc);
 
 	return 0;
 }
 
 static int msm_anlg_cdc_enable_static_supplies_to_optimum(
-				struct msmfalcon_cdc *msmfalcon_cdc,
-				struct msmfalcon_cdc_pdata *pdata)
+				struct sdm660_cdc *sdm660_cdc,
+				struct sdm660_cdc_pdata *pdata)
 {
 	int i;
 	int ret = 0;
 
-	for (i = 0; i < msmfalcon_cdc->num_of_supplies; i++) {
+	for (i = 0; i < sdm660_cdc->num_of_supplies; i++) {
 		if (pdata->regulator[i].ondemand)
 			continue;
 		if (regulator_count_voltages(
-				msmfalcon_cdc->supplies[i].consumer) <=	0)
+				sdm660_cdc->supplies[i].consumer) <=	0)
 			continue;
 
 		ret = regulator_set_voltage(
-				msmfalcon_cdc->supplies[i].consumer,
+				sdm660_cdc->supplies[i].consumer,
 				pdata->regulator[i].min_uv,
 				pdata->regulator[i].max_uv);
 		if (ret) {
-			dev_err(msmfalcon_cdc->dev,
+			dev_err(sdm660_cdc->dev,
 				"Setting volt failed for regulator %s err %d\n",
-				msmfalcon_cdc->supplies[i].supply, ret);
+				sdm660_cdc->supplies[i].supply, ret);
 		}
 
-		ret = regulator_set_load(msmfalcon_cdc->supplies[i].consumer,
+		ret = regulator_set_load(sdm660_cdc->supplies[i].consumer,
 			pdata->regulator[i].optimum_ua);
-		dev_dbg(msmfalcon_cdc->dev, "Regulator %s set optimum mode\n",
-			 msmfalcon_cdc->supplies[i].supply);
+		dev_dbg(sdm660_cdc->dev, "Regulator %s set optimum mode\n",
+			 sdm660_cdc->supplies[i].supply);
 	}
 
 	return ret;
 }
 
 static int msm_anlg_cdc_disable_static_supplies_to_optimum(
-			struct msmfalcon_cdc *msmfalcon_cdc,
-			struct msmfalcon_cdc_pdata *pdata)
+			struct sdm660_cdc *sdm660_cdc,
+			struct sdm660_cdc_pdata *pdata)
 {
 	int i;
 	int ret = 0;
 
-	for (i = 0; i < msmfalcon_cdc->num_of_supplies; i++) {
+	for (i = 0; i < sdm660_cdc->num_of_supplies; i++) {
 		if (pdata->regulator[i].ondemand)
 			continue;
 		if (regulator_count_voltages(
-				msmfalcon_cdc->supplies[i].consumer) <=	0)
+				sdm660_cdc->supplies[i].consumer) <=	0)
 			continue;
-		regulator_set_voltage(msmfalcon_cdc->supplies[i].consumer, 0,
+		regulator_set_voltage(sdm660_cdc->supplies[i].consumer, 0,
 				pdata->regulator[i].max_uv);
-		regulator_set_load(msmfalcon_cdc->supplies[i].consumer, 0);
-		dev_dbg(msmfalcon_cdc->dev, "Regulator %s set optimum mode\n",
-				 msmfalcon_cdc->supplies[i].supply);
+		regulator_set_load(sdm660_cdc->supplies[i].consumer, 0);
+		dev_dbg(sdm660_cdc->dev, "Regulator %s set optimum mode\n",
+				 sdm660_cdc->supplies[i].supply);
 	}
 
 	return ret;
@@ -4263,9 +4263,9 @@ static int msm_anlg_cdc_disable_static_supplies_to_optimum(
 static int msm_anlg_cdc_suspend(struct snd_soc_codec *codec)
 {
 	struct msm_asoc_mach_data *pdata = NULL;
-	struct msmfalcon_cdc *msmfalcon_cdc = codec->control_data;
-	struct msmfalcon_cdc_pdata *msmfalcon_cdc_pdata =
-					msmfalcon_cdc->dev->platform_data;
+	struct sdm660_cdc *sdm660_cdc = codec->control_data;
+	struct sdm660_cdc_pdata *sdm660_cdc_pdata =
+					sdm660_cdc->dev->platform_data;
 
 	pdata = snd_soc_card_get_drvdata(codec->component.card);
 	pr_debug("%s: mclk cnt = %d, mclk_enabled = %d\n",
@@ -4280,21 +4280,21 @@ static int msm_anlg_cdc_suspend(struct snd_soc_codec *codec)
 		atomic_set(&pdata->int_mclk0_enabled, false);
 		mutex_unlock(&pdata->cdc_int_mclk0_mutex);
 	}
-	msm_anlg_cdc_disable_static_supplies_to_optimum(msmfalcon_cdc,
-							msmfalcon_cdc_pdata);
+	msm_anlg_cdc_disable_static_supplies_to_optimum(sdm660_cdc,
+							sdm660_cdc_pdata);
 	return 0;
 }
 
 static int msm_anlg_cdc_resume(struct snd_soc_codec *codec)
 {
 	struct msm_asoc_mach_data *pdata = NULL;
-	struct msmfalcon_cdc *msmfalcon_cdc = codec->control_data;
-	struct msmfalcon_cdc_pdata *msmfalcon_cdc_pdata =
-					msmfalcon_cdc->dev->platform_data;
+	struct sdm660_cdc *sdm660_cdc = codec->control_data;
+	struct sdm660_cdc_pdata *sdm660_cdc_pdata =
+					sdm660_cdc->dev->platform_data;
 
 	pdata = snd_soc_card_get_drvdata(codec->component.card);
-	msm_anlg_cdc_enable_static_supplies_to_optimum(msmfalcon_cdc,
-						       msmfalcon_cdc_pdata);
+	msm_anlg_cdc_enable_static_supplies_to_optimum(sdm660_cdc,
+						       sdm660_cdc_pdata);
 	return 0;
 }
 
@@ -4303,7 +4303,7 @@ static struct regmap *msm_anlg_get_regmap(struct device *dev)
 	return dev_get_regmap(dev->parent, NULL);
 }
 
-static struct snd_soc_codec_driver soc_codec_dev_msmfalcon_cdc = {
+static struct snd_soc_codec_driver soc_codec_dev_sdm660_cdc = {
 	.probe	= msm_anlg_cdc_soc_probe,
 	.remove	= msm_anlg_cdc_soc_remove,
 	.suspend = msm_anlg_cdc_suspend,
@@ -4318,24 +4318,24 @@ static struct snd_soc_codec_driver soc_codec_dev_msmfalcon_cdc = {
 	.get_regmap = msm_anlg_get_regmap,
 };
 
-static int msm_anlg_cdc_init_supplies(struct msmfalcon_cdc *msmfalcon_cdc,
-				struct msmfalcon_cdc_pdata *pdata)
+static int msm_anlg_cdc_init_supplies(struct sdm660_cdc *sdm660_cdc,
+				struct sdm660_cdc_pdata *pdata)
 {
 	int ret;
 	int i;
 
-	msmfalcon_cdc->supplies = devm_kzalloc(msmfalcon_cdc->dev,
+	sdm660_cdc->supplies = devm_kzalloc(sdm660_cdc->dev,
 					sizeof(struct regulator_bulk_data) *
 					ARRAY_SIZE(pdata->regulator),
 					GFP_KERNEL);
-	if (!msmfalcon_cdc->supplies) {
+	if (!sdm660_cdc->supplies) {
 		ret = -ENOMEM;
 		goto err;
 	}
 
-	msmfalcon_cdc->num_of_supplies = 0;
+	sdm660_cdc->num_of_supplies = 0;
 	if (ARRAY_SIZE(pdata->regulator) > MAX_REGULATOR) {
-		dev_err(msmfalcon_cdc->dev, "%s: Array Size out of bound\n",
+		dev_err(sdm660_cdc->dev, "%s: Array Size out of bound\n",
 			__func__);
 		ret = -EINVAL;
 		goto err;
@@ -4343,41 +4343,41 @@ static int msm_anlg_cdc_init_supplies(struct msmfalcon_cdc *msmfalcon_cdc,
 
 	for (i = 0; i < ARRAY_SIZE(pdata->regulator); i++) {
 		if (pdata->regulator[i].name) {
-			msmfalcon_cdc->supplies[i].supply =
+			sdm660_cdc->supplies[i].supply =
 						pdata->regulator[i].name;
-			msmfalcon_cdc->num_of_supplies++;
+			sdm660_cdc->num_of_supplies++;
 		}
 	}
 
-	ret = devm_regulator_bulk_get(msmfalcon_cdc->dev,
-				      msmfalcon_cdc->num_of_supplies,
-				      msmfalcon_cdc->supplies);
+	ret = devm_regulator_bulk_get(sdm660_cdc->dev,
+				      sdm660_cdc->num_of_supplies,
+				      sdm660_cdc->supplies);
 	if (ret != 0) {
-		dev_err(msmfalcon_cdc->dev,
+		dev_err(sdm660_cdc->dev,
 			"Failed to get supplies: err = %d\n",
 			ret);
 		goto err_supplies;
 	}
 
-	for (i = 0; i < msmfalcon_cdc->num_of_supplies; i++) {
+	for (i = 0; i < sdm660_cdc->num_of_supplies; i++) {
 		if (regulator_count_voltages(
-			msmfalcon_cdc->supplies[i].consumer) <= 0)
+			sdm660_cdc->supplies[i].consumer) <= 0)
 			continue;
-		ret = regulator_set_voltage(msmfalcon_cdc->supplies[i].consumer,
+		ret = regulator_set_voltage(sdm660_cdc->supplies[i].consumer,
 					    pdata->regulator[i].min_uv,
 					    pdata->regulator[i].max_uv);
 		if (ret) {
-			dev_err(msmfalcon_cdc->dev,
+			dev_err(sdm660_cdc->dev,
 				"Setting regulator voltage failed for regulator %s err = %d\n",
-				msmfalcon_cdc->supplies[i].supply, ret);
+				sdm660_cdc->supplies[i].supply, ret);
 			goto err_supplies;
 		}
-		ret = regulator_set_load(msmfalcon_cdc->supplies[i].consumer,
+		ret = regulator_set_load(sdm660_cdc->supplies[i].consumer,
 					 pdata->regulator[i].optimum_ua);
 		if (ret < 0) {
-			dev_err(msmfalcon_cdc->dev,
+			dev_err(sdm660_cdc->dev,
 				"Setting regulator optimum mode failed for regulator %s err = %d\n",
-				msmfalcon_cdc->supplies[i].supply, ret);
+				sdm660_cdc->supplies[i].supply, ret);
 			goto err_supplies;
 		} else {
 			ret = 0;
@@ -4387,65 +4387,65 @@ static int msm_anlg_cdc_init_supplies(struct msmfalcon_cdc *msmfalcon_cdc,
 	return ret;
 
 err_supplies:
-	kfree(msmfalcon_cdc->supplies);
+	kfree(sdm660_cdc->supplies);
 err:
 	return ret;
 }
 
 static int msm_anlg_cdc_enable_static_supplies(
-					struct msmfalcon_cdc *msmfalcon_cdc,
-					struct msmfalcon_cdc_pdata *pdata)
+					struct sdm660_cdc *sdm660_cdc,
+					struct sdm660_cdc_pdata *pdata)
 {
 	int i;
 	int ret = 0;
 
-	for (i = 0; i < msmfalcon_cdc->num_of_supplies; i++) {
+	for (i = 0; i < sdm660_cdc->num_of_supplies; i++) {
 		if (pdata->regulator[i].ondemand)
 			continue;
-		ret = regulator_enable(msmfalcon_cdc->supplies[i].consumer);
+		ret = regulator_enable(sdm660_cdc->supplies[i].consumer);
 		if (ret) {
-			dev_err(msmfalcon_cdc->dev, "Failed to enable %s\n",
-			       msmfalcon_cdc->supplies[i].supply);
+			dev_err(sdm660_cdc->dev, "Failed to enable %s\n",
+			       sdm660_cdc->supplies[i].supply);
 			break;
 		}
-		dev_dbg(msmfalcon_cdc->dev, "Enabled regulator %s\n",
-				 msmfalcon_cdc->supplies[i].supply);
+		dev_dbg(sdm660_cdc->dev, "Enabled regulator %s\n",
+				 sdm660_cdc->supplies[i].supply);
 	}
 
 	while (ret && --i)
 		if (!pdata->regulator[i].ondemand)
-			regulator_disable(msmfalcon_cdc->supplies[i].consumer);
+			regulator_disable(sdm660_cdc->supplies[i].consumer);
 	return ret;
 }
 
-static void msm_anlg_cdc_disable_supplies(struct msmfalcon_cdc *msmfalcon_cdc,
-				     struct msmfalcon_cdc_pdata *pdata)
+static void msm_anlg_cdc_disable_supplies(struct sdm660_cdc *sdm660_cdc,
+				     struct sdm660_cdc_pdata *pdata)
 {
 	int i;
 
-	regulator_bulk_disable(msmfalcon_cdc->num_of_supplies,
-			       msmfalcon_cdc->supplies);
-	for (i = 0; i < msmfalcon_cdc->num_of_supplies; i++) {
+	regulator_bulk_disable(sdm660_cdc->num_of_supplies,
+			       sdm660_cdc->supplies);
+	for (i = 0; i < sdm660_cdc->num_of_supplies; i++) {
 		if (regulator_count_voltages(
-				msmfalcon_cdc->supplies[i].consumer) <= 0)
+				sdm660_cdc->supplies[i].consumer) <= 0)
 			continue;
-		regulator_set_voltage(msmfalcon_cdc->supplies[i].consumer, 0,
+		regulator_set_voltage(sdm660_cdc->supplies[i].consumer, 0,
 				pdata->regulator[i].max_uv);
-		regulator_set_load(msmfalcon_cdc->supplies[i].consumer, 0);
+		regulator_set_load(sdm660_cdc->supplies[i].consumer, 0);
 	}
-	regulator_bulk_free(msmfalcon_cdc->num_of_supplies,
-			    msmfalcon_cdc->supplies);
-	kfree(msmfalcon_cdc->supplies);
+	regulator_bulk_free(sdm660_cdc->num_of_supplies,
+			    sdm660_cdc->supplies);
+	kfree(sdm660_cdc->supplies);
 }
 
-static const struct of_device_id msmfalcon_codec_of_match[] = {
+static const struct of_device_id sdm660_codec_of_match[] = {
 	{ .compatible = "qcom,pmic-analog-codec", },
 	{},
 };
 
 static void msm_anlg_add_child_devices(struct work_struct *work)
 {
-	struct msmfalcon_cdc *pdata;
+	struct sdm660_cdc *pdata;
 	struct platform_device *pdev;
 	struct device_node *node;
 	struct msm_dig_ctrl_data *dig_ctrl_data = NULL, *temp;
@@ -4453,7 +4453,7 @@ static void msm_anlg_add_child_devices(struct work_struct *work)
 	struct msm_dig_ctrl_platform_data *platdata;
 	char plat_dev_name[MSM_DIG_CDC_STRING_LEN];
 
-	pdata = container_of(work, struct msmfalcon_cdc,
+	pdata = container_of(work, struct sdm660_cdc,
 			     msm_anlg_add_child_devices_work);
 	if (!pdata) {
 		pr_err("%s: Memory for pdata does not exist\n",
@@ -4534,8 +4534,8 @@ err:
 static int msm_anlg_cdc_probe(struct platform_device *pdev)
 {
 	int ret = 0;
-	struct msmfalcon_cdc *msmfalcon_cdc = NULL;
-	struct msmfalcon_cdc_pdata *pdata;
+	struct sdm660_cdc *sdm660_cdc = NULL;
+	struct sdm660_cdc_pdata *pdata;
 	int adsp_state;
 
 	adsp_state = apr_get_subsys_state();
@@ -4561,21 +4561,21 @@ static int msm_anlg_cdc_probe(struct platform_device *pdev)
 			__func__);
 		goto rtn;
 	}
-	msmfalcon_cdc = devm_kzalloc(&pdev->dev, sizeof(struct msmfalcon_cdc),
+	sdm660_cdc = devm_kzalloc(&pdev->dev, sizeof(struct sdm660_cdc),
 				     GFP_KERNEL);
-	if (msmfalcon_cdc == NULL) {
+	if (sdm660_cdc == NULL) {
 		ret = -ENOMEM;
 		goto rtn;
 	}
 
-	msmfalcon_cdc->dev = &pdev->dev;
-	ret = msm_anlg_cdc_init_supplies(msmfalcon_cdc, pdata);
+	sdm660_cdc->dev = &pdev->dev;
+	ret = msm_anlg_cdc_init_supplies(sdm660_cdc, pdata);
 	if (ret) {
 		dev_err(&pdev->dev, "%s: Fail to enable Codec supplies\n",
 			__func__);
 		goto rtn;
 	}
-	ret = msm_anlg_cdc_enable_static_supplies(msmfalcon_cdc, pdata);
+	ret = msm_anlg_cdc_enable_static_supplies(sdm660_cdc, pdata);
 	if (ret) {
 		dev_err(&pdev->dev,
 			"%s: Fail to enable Codec pre-reset supplies\n",
@@ -4585,7 +4585,7 @@ static int msm_anlg_cdc_probe(struct platform_device *pdev)
 	/* Allow supplies to be ready */
 	usleep_range(5, 6);
 
-	dev_set_drvdata(&pdev->dev, msmfalcon_cdc);
+	dev_set_drvdata(&pdev->dev, sdm660_cdc);
 	if (wcd9xxx_spmi_irq_init()) {
 		dev_err(&pdev->dev,
 			"%s: irq initialization failed\n", __func__);
@@ -4595,7 +4595,7 @@ static int msm_anlg_cdc_probe(struct platform_device *pdev)
 	}
 
 	ret = snd_soc_register_codec(&pdev->dev,
-				     &soc_codec_dev_msmfalcon_cdc,
+				     &soc_codec_dev_sdm660_cdc,
 				     msm_anlg_cdc_i2s_dai,
 				     ARRAY_SIZE(msm_anlg_cdc_i2s_dai));
 	if (ret) {
@@ -4604,29 +4604,29 @@ static int msm_anlg_cdc_probe(struct platform_device *pdev)
 			__func__, ret);
 		goto err_supplies;
 	}
-	msmfalcon_cdc->dig_plat_data.handle = (void *) msmfalcon_cdc;
-	msmfalcon_cdc->dig_plat_data.update_clkdiv = update_clkdiv;
-	msmfalcon_cdc->dig_plat_data.get_cdc_version = get_cdc_version;
-	msmfalcon_cdc->dig_plat_data.register_notifier =
+	sdm660_cdc->dig_plat_data.handle = (void *) sdm660_cdc;
+	sdm660_cdc->dig_plat_data.update_clkdiv = update_clkdiv;
+	sdm660_cdc->dig_plat_data.get_cdc_version = get_cdc_version;
+	sdm660_cdc->dig_plat_data.register_notifier =
 					msm_anlg_cdc_dig_register_notifier;
-	INIT_WORK(&msmfalcon_cdc->msm_anlg_add_child_devices_work,
+	INIT_WORK(&sdm660_cdc->msm_anlg_add_child_devices_work,
 		  msm_anlg_add_child_devices);
-	schedule_work(&msmfalcon_cdc->msm_anlg_add_child_devices_work);
+	schedule_work(&sdm660_cdc->msm_anlg_add_child_devices_work);
 
 	return ret;
 err_supplies:
-	msm_anlg_cdc_disable_supplies(msmfalcon_cdc, pdata);
+	msm_anlg_cdc_disable_supplies(sdm660_cdc, pdata);
 rtn:
 	return ret;
 }
 
 static int msm_anlg_cdc_remove(struct platform_device *pdev)
 {
-	struct msmfalcon_cdc *msmfalcon_cdc = dev_get_drvdata(&pdev->dev);
-	struct msmfalcon_cdc_pdata *pdata = msmfalcon_cdc->dev->platform_data;
+	struct sdm660_cdc *sdm660_cdc = dev_get_drvdata(&pdev->dev);
+	struct sdm660_cdc_pdata *pdata = sdm660_cdc->dev->platform_data;
 
 	snd_soc_unregister_codec(&pdev->dev);
-	msm_anlg_cdc_disable_supplies(msmfalcon_cdc, pdata);
+	msm_anlg_cdc_disable_supplies(sdm660_cdc, pdata);
 	return 0;
 }
 
@@ -4634,7 +4634,7 @@ static struct platform_driver msm_anlg_codec_driver = {
 	.driver		= {
 		.owner          = THIS_MODULE,
 		.name           = DRV_NAME,
-		.of_match_table = of_match_ptr(msmfalcon_codec_of_match)
+		.of_match_table = of_match_ptr(sdm660_codec_of_match)
 	},
 	.probe          = msm_anlg_cdc_probe,
 	.remove         = msm_anlg_cdc_remove,
diff --git a/sound/soc/codecs/msmfalcon_cdc/msm-analog-cdc.h b/sound/soc/codecs/sdm660_cdc/msm-analog-cdc.h
index 112b544b7de8..e0626d3be971 100644
--- a/sound/soc/codecs/msmfalcon_cdc/msm-analog-cdc.h
+++ b/sound/soc/codecs/sdm660_cdc/msm-analog-cdc.h
@@ -17,7 +17,7 @@
 #include <sound/q6afe-v2.h>
 #include "../wcd-mbhc-v2.h"
 #include "../wcdcal-hwdep.h"
-#include "msmfalcon-cdc-registers.h"
+#include "sdm660-cdc-registers.h"
 
 #define MICBIAS_EXT_BYP_CAP 0x00
 #define MICBIAS_NO_EXT_BYP_CAP 0x01
@@ -83,14 +83,14 @@ struct wcd_micbias_setting {
 	bool bias2_is_headset_only;
 };
 
-enum msmfalcon_cdc_pid_current {
+enum sdm660_cdc_pid_current {
 	MSM89XX_PID_MIC_2P5_UA,
 	MSM89XX_PID_MIC_5_UA,
 	MSM89XX_PID_MIC_10_UA,
 	MSM89XX_PID_MIC_20_UA,
 };
 
-struct msmfalcon_cdc_reg_mask_val {
+struct sdm660_cdc_reg_mask_val {
 	u16	reg;
 	u8	mask;
 	u8	val;
@@ -132,7 +132,7 @@ enum {
 	CODEC_DELAY_1_1_MS  = 1100,
 };
 
-struct msmfalcon_cdc_regulator {
+struct sdm660_cdc_regulator {
 	const char *name;
 	int min_uv;
 	int max_uv;
@@ -154,7 +154,7 @@ struct wcd_imped_i_ref {
 	int offset;
 };
 
-enum msmfalcon_cdc_micbias_num {
+enum sdm660_cdc_micbias_num {
 	MSM89XX_MICBIAS1 = 0,
 };
 
@@ -172,7 +172,7 @@ struct msm_dig_ctrl_platform_data {
 				 bool enable);
 };
 
-struct msmfalcon_cdc {
+struct sdm660_cdc {
 	struct device *dev;
 	u32 num_of_supplies;
 	struct regulator_bulk_data *supplies;
@@ -184,12 +184,12 @@ struct msmfalcon_cdc {
 	struct blocking_notifier_head notifier;
 };
 
-struct msmfalcon_cdc_pdata {
+struct sdm660_cdc_pdata {
 	struct wcd_micbias_setting micbias;
-	struct msmfalcon_cdc_regulator regulator[MAX_REGULATOR];
+	struct sdm660_cdc_regulator regulator[MAX_REGULATOR];
 };
 
-struct msmfalcon_cdc_priv {
+struct sdm660_cdc_priv {
 	struct snd_soc_codec *codec;
 	u16 pmic_rev;
 	u16 codec_version;
@@ -230,7 +230,7 @@ extern int msm_anlg_cdc_hs_detect(struct snd_soc_codec *codec,
 
 extern void msm_anlg_cdc_hs_detect_exit(struct snd_soc_codec *codec);
 
-extern void msmfalcon_cdc_update_int_spk_boost(bool enable);
+extern void sdm660_cdc_update_int_spk_boost(bool enable);
 
 extern void msm_anlg_cdc_spk_ext_pa_cb(
 		int (*codec_spk_ext_pa)(struct snd_soc_codec *codec,
diff --git a/sound/soc/codecs/msmfalcon_cdc/msm-cdc-common.h b/sound/soc/codecs/sdm660_cdc/msm-cdc-common.h
index 9f2e9355197b..7a63a71ceeb1 100644
--- a/sound/soc/codecs/msmfalcon_cdc/msm-cdc-common.h
+++ b/sound/soc/codecs/sdm660_cdc/msm-cdc-common.h
@@ -11,7 +11,7 @@
  */
 
 #include <linux/regmap.h>
-#include "msmfalcon-cdc-registers.h"
+#include "sdm660-cdc-registers.h"
 
 extern struct reg_default
 		msm89xx_cdc_core_defaults[MSM89XX_CDC_CORE_CACHE_SIZE];
diff --git a/sound/soc/codecs/msmfalcon_cdc/msm-digital-cdc.c b/sound/soc/codecs/sdm660_cdc/msm-digital-cdc.c
index d036b82654f0..ac71e3c6d6a1 100644
--- a/sound/soc/codecs/msmfalcon_cdc/msm-digital-cdc.c
+++ b/sound/soc/codecs/sdm660_cdc/msm-digital-cdc.c
@@ -26,10 +26,10 @@
 #include <sound/soc.h>
 #include <sound/soc-dapm.h>
 #include <sound/tlv.h>
-#include "msmfalcon-cdc-registers.h"
+#include "sdm660-cdc-registers.h"
 #include "msm-digital-cdc.h"
 #include "msm-cdc-common.h"
-#include "../../msm/msmfalcon-common.h"
+#include "../../msm/sdm660-common.h"
 
 #define DRV_NAME "msm_digital_codec"
 #define MCLK_RATE_9P6MHZ        9600000
diff --git a/sound/soc/codecs/msmfalcon_cdc/msm-digital-cdc.h b/sound/soc/codecs/sdm660_cdc/msm-digital-cdc.h
index 4cb82cd421b0..4cb82cd421b0 100644
--- a/sound/soc/codecs/msmfalcon_cdc/msm-digital-cdc.h
+++ b/sound/soc/codecs/sdm660_cdc/msm-digital-cdc.h
diff --git a/sound/soc/codecs/msmfalcon_cdc/msmfalcon-cdc-irq.c b/sound/soc/codecs/sdm660_cdc/sdm660-cdc-irq.c
index 5ba2dac1ec20..63a715c5248c 100644
--- a/sound/soc/codecs/msmfalcon_cdc/msmfalcon-cdc-irq.c
+++ b/sound/soc/codecs/sdm660_cdc/sdm660-cdc-irq.c
@@ -26,8 +26,8 @@
 #include <soc/qcom/pm.h>
 #include <sound/soc.h>
 #include "msm-analog-cdc.h"
-#include "msmfalcon-cdc-irq.h"
-#include "msmfalcon-cdc-registers.h"
+#include "sdm660-cdc-irq.h"
+#include "sdm660-cdc-registers.h"
 
 #define MAX_NUM_IRQS 14
 #define NUM_IRQ_REGS 2
diff --git a/sound/soc/codecs/msmfalcon_cdc/msmfalcon-cdc-irq.h b/sound/soc/codecs/sdm660_cdc/sdm660-cdc-irq.h
index 659e52cc2a5e..659e52cc2a5e 100644
--- a/sound/soc/codecs/msmfalcon_cdc/msmfalcon-cdc-irq.h
+++ b/sound/soc/codecs/sdm660_cdc/sdm660-cdc-irq.h
diff --git a/sound/soc/codecs/msmfalcon_cdc/msmfalcon-cdc-registers.h b/sound/soc/codecs/sdm660_cdc/sdm660-cdc-registers.h
index 34c3d3333d6e..5e042e2d466a 100644
--- a/sound/soc/codecs/msmfalcon_cdc/msmfalcon-cdc-registers.h
+++ b/sound/soc/codecs/sdm660_cdc/sdm660-cdc-registers.h
@@ -9,8 +9,8 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
-#ifndef MSMFALCON_WCD_REGISTERS_H
-#define MSMFALCON_WCD_REGISTERS_H
+#ifndef SDM660_WCD_REGISTERS_H
+#define SDM660_WCD_REGISTERS_H
 
 #define CDC_DIG_BASE		0xF000
 #define CDC_ANA_BASE		0xF100
diff --git a/sound/soc/codecs/msmfalcon_cdc/msmfalcon-regmap.c b/sound/soc/codecs/sdm660_cdc/sdm660-regmap.c
index 5001c8da9877..1c3a8d2c2fd9 100644
--- a/sound/soc/codecs/msmfalcon_cdc/msmfalcon-regmap.c
+++ b/sound/soc/codecs/sdm660_cdc/sdm660-regmap.c
@@ -12,7 +12,7 @@
  */
 
 #include <linux/regmap.h>
-#include "msmfalcon-cdc-registers.h"
+#include "sdm660-cdc-registers.h"
 
 /*
  * Default register reset values that are common across different versions
diff --git a/sound/soc/msm/Kconfig b/sound/soc/msm/Kconfig
index 69d74a8703b6..835022b76b78 100644
--- a/sound/soc/msm/Kconfig
+++ b/sound/soc/msm/Kconfig
@@ -108,7 +108,7 @@ config SND_SOC_CPE
 	 listen on codec.
 
 config SND_SOC_INT_CODEC
-	tristate "SoC Machine driver for MSMFALCON_INT"
+	tristate "SoC Machine driver for SDM660_INT"
 	depends on ARCH_QCOM
 	select SND_SOC_QDSP6V2
 	select SND_SOC_MSM_STUB
@@ -121,7 +121,7 @@ config SND_SOC_INT_CODEC
 	select MSM_QDSP6V2_CODECS
 	select MSM_CDC_PINCTRL
 	select SND_SOC_MSM_SDW
-	select SND_SOC_MSMFALCON_CDC
+	select SND_SOC_SDM660_CDC
 	select QTI_PP
 	select DTS_SRS_TM
 	select DOLBY_DAP
@@ -129,7 +129,7 @@ config SND_SOC_INT_CODEC
 	select SND_HWDEP
 	select MSM_ULTRASOUND
 	select DTS_EAGLE
-	select SND_SOC_MSMFALCON_COMMON
+	select SND_SOC_SDM660_COMMON
 	select SND_SOC_COMPRESS
 	select PINCTRL_LPI
 	help
@@ -140,7 +140,7 @@ config SND_SOC_INT_CODEC
 	DAI-links
 
 config SND_SOC_EXT_CODEC
-	tristate "SoC Machine driver for MSMFALCON_EXT"
+	tristate "SoC Machine driver for SDM660_EXT"
 	depends on ARCH_QCOM
 	select SND_SOC_QDSP6V2
 	select SND_SOC_MSM_STUB
@@ -164,7 +164,7 @@ config SND_SOC_EXT_CODEC
 	select SND_HWDEP
 	select MSM_ULTRASOUND
 	select DTS_EAGLE
-	select SND_SOC_MSMFALCON_COMMON
+	select SND_SOC_SDM660_COMMON
 	select SND_SOC_COMPRESS
 	select PINCTRL_LPI
 	help
@@ -233,13 +233,13 @@ config SND_SOC_MSM8998
 	 the machine driver and the corresponding
 	 DAI-links
 
-config SND_SOC_FALCON
-	tristate "SoC Machine driver for MSMFALCON boards"
-	depends on ARCH_MSMFALCON
+config SND_SOC_660
+	tristate "SoC Machine driver for SDM660 boards"
+	depends on ARCH_SDM660
 	select SND_SOC_INT_CODEC
 	select SND_SOC_EXT_CODEC
 	help
-	 To add support for SoC audio on MSMFALCON.
+	 To add support for SoC audio on SDM660.
 	 This will enable sound soc drivers which
 	 interfaces with DSP, also it will enable
 	 the machine driver and the corresponding
diff --git a/sound/soc/msm/Makefile b/sound/soc/msm/Makefile
index d66f9eb79cea..cd63b491285c 100644
--- a/sound/soc/msm/Makefile
+++ b/sound/soc/msm/Makefile
@@ -20,16 +20,16 @@ obj-$(CONFIG_SND_SOC_MSM8996) += snd-soc-msm8996.o
 snd-soc-msm8998-objs := msm8998.o
 obj-$(CONFIG_SND_SOC_MSM8998) += snd-soc-msm8998.o
 
-# for MSMFALCON sound card driver
-snd-soc-msmfalcon-common-objs := msmfalcon-common.o
-obj-$(CONFIG_SND_SOC_MSMFALCON_COMMON) += snd-soc-msmfalcon-common.o
+# for SDM660 sound card driver
+snd-soc-sdm660-common-objs := sdm660-common.o
+obj-$(CONFIG_SND_SOC_SDM660_COMMON) += snd-soc-sdm660-common.o
 
-# for MSMFALCON sound card driver
-snd-soc-int-codec-objs := msmfalcon-internal.o
-obj-$(CONFIG_SND_SOC_INT_CODEC) += snd-soc-msmfalcon-common.o
+# for SDM660 sound card driver
+snd-soc-int-codec-objs := sdm660-internal.o
+obj-$(CONFIG_SND_SOC_INT_CODEC) += snd-soc-sdm660-common.o
 obj-$(CONFIG_SND_SOC_INT_CODEC) += snd-soc-int-codec.o
 
-# for MSMFALCON sound card driver
-snd-soc-ext-codec-objs := msmfalcon-external.o msmfalcon-ext-dai-links.o
-obj-$(CONFIG_SND_SOC_EXT_CODEC) += snd-soc-msmfalcon-common.o
+# for SDM660 sound card driver
+snd-soc-ext-codec-objs := sdm660-external.o sdm660-ext-dai-links.o
+obj-$(CONFIG_SND_SOC_EXT_CODEC) += snd-soc-sdm660-common.o
 obj-$(CONFIG_SND_SOC_EXT_CODEC) += snd-soc-ext-codec.o
diff --git a/sound/soc/msm/msmfalcon-common.c b/sound/soc/msm/sdm660-common.c
index 013127c48984..623b8c5c866a 100644
--- a/sound/soc/msm/msmfalcon-common.c
+++ b/sound/soc/msm/sdm660-common.c
@@ -16,13 +16,13 @@
 #include <sound/pcm_params.h>
 #include <sound/q6afe-v2.h>
 #include "qdsp6v2/msm-pcm-routing-v2.h"
-#include "msmfalcon-common.h"
-#include "msmfalcon-internal.h"
-#include "msmfalcon-external.h"
-#include "../codecs/msmfalcon_cdc/msm-analog-cdc.h"
+#include "sdm660-common.h"
+#include "sdm660-internal.h"
+#include "sdm660-external.h"
+#include "../codecs/sdm660_cdc/msm-analog-cdc.h"
 #include "../codecs/wsa881x.h"
 
-#define DRV_NAME "msmfalcon-asoc-snd"
+#define DRV_NAME "sdm660-asoc-snd"
 
 #define MSM_INT_DIGITAL_CODEC "msm-dig-codec"
 #define PMIC_INT_ANALOG_CODEC "analog-codec"
@@ -2658,12 +2658,12 @@ static void i2s_auxpcm_deinit(void)
 			mi2s_auxpcm_conf[count].pcm_i2s_sel_vt_addr);
 }
 
-static const struct of_device_id msmfalcon_asoc_machine_of_match[]  = {
-	{ .compatible = "qcom,msmfalcon-asoc-snd",
+static const struct of_device_id sdm660_asoc_machine_of_match[]  = {
+	{ .compatible = "qcom,sdm660-asoc-snd",
 	  .data = "internal_codec"},
-	{ .compatible = "qcom,msmfalcon-asoc-snd-tasha",
+	{ .compatible = "qcom,sdm660-asoc-snd-tasha",
 	  .data = "tasha_codec"},
-	{ .compatible = "qcom,msmfalcon-asoc-snd-tavil",
+	{ .compatible = "qcom,sdm660-asoc-snd-tavil",
 	  .data = "tavil_codec"},
 	{},
 };
@@ -2682,7 +2682,7 @@ static int msm_asoc_machine_probe(struct platform_device *pdev)
 	if (!pdata)
 		return -ENOMEM;
 
-	match = of_match_node(msmfalcon_asoc_machine_of_match,
+	match = of_match_node(sdm660_asoc_machine_of_match,
 			      pdev->dev.of_node);
 	if (!match)
 		goto err;
@@ -2821,19 +2821,19 @@ static int msm_asoc_machine_remove(struct platform_device *pdev)
 	return 0;
 }
 
-static struct platform_driver msmfalcon_asoc_machine_driver = {
+static struct platform_driver sdm660_asoc_machine_driver = {
 	.driver = {
 		.name = DRV_NAME,
 		.owner = THIS_MODULE,
 		.pm = &snd_soc_pm_ops,
-		.of_match_table = msmfalcon_asoc_machine_of_match,
+		.of_match_table = sdm660_asoc_machine_of_match,
 	},
 	.probe = msm_asoc_machine_probe,
 	.remove = msm_asoc_machine_remove,
 };
-module_platform_driver(msmfalcon_asoc_machine_driver);
+module_platform_driver(sdm660_asoc_machine_driver);
 
 MODULE_DESCRIPTION("ALSA SoC msm");
 MODULE_LICENSE("GPL v2");
 MODULE_ALIAS("platform:" DRV_NAME);
-MODULE_DEVICE_TABLE(of, msmfalcon_asoc_machine_of_match);
+MODULE_DEVICE_TABLE(of, sdm660_asoc_machine_of_match);
diff --git a/sound/soc/msm/msmfalcon-common.h b/sound/soc/msm/sdm660-common.h
index 3c18852cf897..71b6a0786549 100644
--- a/sound/soc/msm/msmfalcon-common.h
+++ b/sound/soc/msm/sdm660-common.h
@@ -66,7 +66,7 @@ enum {
 };
 
 extern const struct snd_kcontrol_new msm_common_snd_controls[];
-struct msmfalcon_codec {
+struct sdm660_codec {
 	void* (*get_afe_config_fn)(struct snd_soc_codec *codec,
 				   enum afe_config_type config_type);
 };
@@ -90,7 +90,7 @@ struct msm_asoc_mach_data {
 	struct device_node *dmic_gpio_p; /* used by pinctrl API */
 	struct device_node *ext_spk_gpio_p; /* used by pinctrl API */
 	struct snd_soc_codec *codec;
-	struct msmfalcon_codec msmfalcon_codec_fn;
+	struct sdm660_codec sdm660_codec_fn;
 	struct snd_info_entry *codec_root;
 	int spk_ext_pa_gpio;
 	int mclk_freq;
diff --git a/sound/soc/msm/msmfalcon-ext-dai-links.c b/sound/soc/msm/sdm660-ext-dai-links.c
index fc6d52233a33..3e29221fe00f 100644
--- a/sound/soc/msm/msmfalcon-ext-dai-links.c
+++ b/sound/soc/msm/sdm660-ext-dai-links.c
@@ -19,11 +19,11 @@
 #include <sound/pcm_params.h>
 #include "qdsp6v2/msm-pcm-routing-v2.h"
 #include "../codecs/wcd9335.h"
-#include "msmfalcon-common.h"
-#include "msmfalcon-external.h"
+#include "sdm660-common.h"
+#include "sdm660-external.h"
 
 #define DEV_NAME_STR_LEN            32
-#define __CHIPSET__ "MSMFALCON "
+#define __CHIPSET__ "SDM660 "
 #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
 
 #define WCN_CDC_SLIM_RX_CH_MAX 2
@@ -1882,7 +1882,7 @@ struct snd_soc_card *populate_snd_card_dailinks(struct device *dev,
 	if (strnstr(card->name, "tasha", strlen(card->name))) {
 		codec_ver = tasha_codec_ver();
 		if (codec_ver == WCD9326)
-			card->name = "msmfalcon-tashalite-snd-card";
+			card->name = "sdm660-tashalite-snd-card";
 
 		len1 = ARRAY_SIZE(msm_ext_common_fe_dai);
 		len2 = len1 + ARRAY_SIZE(msm_ext_tasha_fe_dai);
diff --git a/sound/soc/msm/msmfalcon-external.c b/sound/soc/msm/sdm660-external.c
index ef0b23e2e51e..f610eb53d5df 100644
--- a/sound/soc/msm/msmfalcon-external.c
+++ b/sound/soc/msm/sdm660-external.c
@@ -21,14 +21,14 @@
 #include <linux/qdsp6v2/audio_notifier.h>
 #include "qdsp6v2/msm-pcm-routing-v2.h"
 #include "msm-audio-pinctrl.h"
-#include "msmfalcon-common.h"
-#include "msmfalcon-external.h"
+#include "sdm660-common.h"
+#include "sdm660-external.h"
 #include "../codecs/wcd9335.h"
 #include "../codecs/wcd934x/wcd934x.h"
 #include "../codecs/wcd934x/wcd934x-mbhc.h"
 
-#define MSMFALCON_SPK_ON     1
-#define MSMFALCON_SPK_OFF    0
+#define SDM660_SPK_ON     1
+#define SDM660_SPK_OFF    0
 
 #define WCD9XXX_MBHC_DEF_BUTTONS    8
 #define WCD9XXX_MBHC_DEF_RLOADS     5
@@ -663,7 +663,7 @@ static void msm_ext_control(struct snd_soc_codec *codec)
 			snd_soc_codec_get_dapm(codec);
 
 	pr_debug("%s: msm_ext_spk_control = %d", __func__, msm_ext_spk_control);
-	if (msm_ext_spk_control == MSMFALCON_SPK_ON) {
+	if (msm_ext_spk_control == SDM660_SPK_ON) {
 		snd_soc_dapm_enable_pin(dapm, "Lineout_1 amp");
 		snd_soc_dapm_enable_pin(dapm, "Lineout_3 amp");
 	} else {
@@ -1281,7 +1281,7 @@ err_fail:
 	return ret;
 }
 
-static int msmfalcon_notifier_service_cb(struct notifier_block *this,
+static int sdm660_notifier_service_cb(struct notifier_block *this,
 					 unsigned long opcode, void *ptr)
 {
 	int ret;
@@ -1339,7 +1339,7 @@ done:
 }
 
 static struct notifier_block service_nb = {
-	.notifier_call  = msmfalcon_notifier_service_cb,
+	.notifier_call  = sdm660_notifier_service_cb,
 	.priority = -INT_MAX,
 };
 
@@ -1739,7 +1739,7 @@ void msm_ext_register_audio_notifier(void)
 {
 	int ret;
 
-	ret = audio_notifier_register("msmfalcon", AUDIO_NOTIFIER_ADSP_DOMAIN,
+	ret = audio_notifier_register("sdm660", AUDIO_NOTIFIER_ADSP_DOMAIN,
 				      &service_nb);
 	if (ret < 0)
 		pr_err("%s: Audio notifier register failed ret = %d\n",
diff --git a/sound/soc/msm/msmfalcon-external.h b/sound/soc/msm/sdm660-external.h
index fc82b628dfac..0ede06f0c082 100644
--- a/sound/soc/msm/msmfalcon-external.h
+++ b/sound/soc/msm/sdm660-external.h
@@ -10,8 +10,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __MSMFALCON_EXTERNAL
-#define __MSMFALCON_EXTERNAL
+#ifndef __SDM660_EXTERNAL
+#define __SDM660_EXTERNAL
 
 int msm_snd_hw_params(struct snd_pcm_substream *substream,
 		      struct snd_pcm_hw_params *params);
diff --git a/sound/soc/msm/msmfalcon-internal.c b/sound/soc/msm/sdm660-internal.c
index 5226e791fcff..aa094fe853ee 100644
--- a/sound/soc/msm/msmfalcon-internal.c
+++ b/sound/soc/msm/sdm660-internal.c
@@ -16,12 +16,12 @@
 #include <linux/mfd/msm-cdc-pinctrl.h>
 #include <sound/pcm_params.h>
 #include "qdsp6v2/msm-pcm-routing-v2.h"
-#include "msmfalcon-common.h"
-#include "../codecs/msmfalcon_cdc/msm-digital-cdc.h"
-#include "../codecs/msmfalcon_cdc/msm-analog-cdc.h"
+#include "sdm660-common.h"
+#include "../codecs/sdm660_cdc/msm-digital-cdc.h"
+#include "../codecs/sdm660_cdc/msm-analog-cdc.h"
 #include "../codecs/msm_sdw/msm_sdw.h"
 
-#define __CHIPSET__ "MSMFALCON "
+#define __CHIPSET__ "SDM660 "
 #define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
 
 #define DEFAULT_MCLK_RATE 9600000
@@ -2911,9 +2911,9 @@ ARRAY_SIZE(msm_mi2s_be_dai_links) +
 ARRAY_SIZE(msm_auxpcm_be_dai_links)+
 ARRAY_SIZE(msm_wcn_be_dai_links)];
 
-static struct snd_soc_card msmfalcon_card = {
-	/* snd_soc_card_msmfalcon */
-	.name		= "msmfalcon-snd-card",
+static struct snd_soc_card sdm660_card = {
+	/* snd_soc_card_sdm660 */
+	.name		= "sdm660-snd-card",
 	.dai_link	= msm_int_dai,
 	.num_links	= ARRAY_SIZE(msm_int_dai),
 };
@@ -2964,7 +2964,7 @@ static void msm_int_dt_parse_cap_info(struct platform_device *pdev,
 static struct snd_soc_card *msm_int_populate_sndcard_dailinks(
 						struct device *dev)
 {
-	struct snd_soc_card *card = &msmfalcon_card;
+	struct snd_soc_card *card = &sdm660_card;
 	struct snd_soc_dai_link *dailink;
 	int len1;
 
diff --git a/sound/soc/msm/msmfalcon-internal.h b/sound/soc/msm/sdm660-internal.h
index e5e3e7c66246..ccc62b8f33dc 100644
--- a/sound/soc/msm/msmfalcon-internal.h
+++ b/sound/soc/msm/sdm660-internal.h
@@ -10,8 +10,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __MSMFALCON_INTERNAL
-#define __MSMFALCON_INTERNAL
+#ifndef __SDM660_INTERNAL
+#define __SDM660_INTERNAL
 
 #include <sound/soc.h>