From da23c02138f79eacef6f8adfbf75db2a4a14f3ad Mon Sep 17 00:00:00 2001 From: Neeraj Upadhyay Date: Tue, 27 Dec 2016 19:03:35 +0530 Subject: msm: Rename msmfalcon/apqfalcon to sdm660/sda660 Update the code name from msmfalcon/apqfalcon to sdm660/sda660. As part of this, update the filename containing "falcon" and files content containing "falcon". Change-Id: Iec85862251b9e1b4dcc8bdce8b214ce87c0049bc Signed-off-by: Neeraj Upadhyay --- Documentation/devicetree/bindings/arm/msm/msm.txt | 22 +- .../devicetree/bindings/clock/qcom,gcc-dbg.txt | 6 +- .../devicetree/bindings/clock/qcom,gcc.txt | 2 +- .../devicetree/bindings/clock/qcom,gpucc.txt | 4 +- .../devicetree/bindings/clock/qcom,mmcc.txt | 2 +- .../devicetree/bindings/clock/qcom,rpmcc.txt | 4 +- Documentation/devicetree/bindings/fb/mdss-pll.txt | 2 +- .../bindings/leds/leds-qpnp-flash-v2.txt | 2 +- .../devicetree/bindings/leds/leds-qpnp-wled.txt | 8 +- .../bindings/pinctrl/qcom,msmfalcon-pinctrl.txt | 199 - .../bindings/pinctrl/qcom,sdm660-pinctrl.txt | 199 + .../bindings/regulator/cpr4-mmss-ldo-regulator.txt | 8 +- .../devicetree/bindings/regulator/msm_gfx_ldo.txt | 2 +- .../bindings/regulator/qpnp-lcdb-regulator.txt | 2 +- .../devicetree/bindings/sound/qcom-audio-dev.txt | 18 +- .../devicetree/bindings/thermal/tsens.txt | 2 +- Documentation/devicetree/bindings/ufs/ufs-qcom.txt | 2 +- arch/arm/boot/dts/qcom/Makefile | 54 +- arch/arm/boot/dts/qcom/apqfalcon-cdp.dts | 25 - arch/arm/boot/dts/qcom/apqfalcon-mtp.dts | 25 - arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-cdp.dts | 25 - arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-mtp.dts | 25 - arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-rcm.dts | 25 - arch/arm/boot/dts/qcom/apqfalcon-rcm.dts | 25 - arch/arm/boot/dts/qcom/apqfalcon.dtsi | 19 - arch/arm/boot/dts/qcom/msm-arm-smmu-660.dtsi | 212 + arch/arm/boot/dts/qcom/msm-arm-smmu-falcon.dtsi | 212 - .../boot/dts/qcom/msm-arm-smmu-impl-defs-660.dtsi | 409 ++ .../dts/qcom/msm-arm-smmu-impl-defs-falcon.dtsi | 409 -- arch/arm/boot/dts/qcom/msm-arm-smmu-triton.dtsi | 4 +- arch/arm/boot/dts/qcom/msm-audio.dtsi | 14 +- arch/arm/boot/dts/qcom/msm-gdsc-660.dtsi | 159 + arch/arm/boot/dts/qcom/msm-gdsc-falcon.dtsi | 159 - .../boot/dts/qcom/msm-pm2falcon-rpm-regulator.dtsi | 238 - arch/arm/boot/dts/qcom/msm-pm2falcon.dtsi | 395 -- arch/arm/boot/dts/qcom/msm-pm3falcon.dtsi | 21 - .../arm/boot/dts/qcom/msm-pm660-rpm-regulator.dtsi | 298 ++ arch/arm/boot/dts/qcom/msm-pm660.dtsi | 608 +++ arch/arm/boot/dts/qcom/msm-pm660a.dtsi | 21 + .../boot/dts/qcom/msm-pm660l-rpm-regulator.dtsi | 238 + arch/arm/boot/dts/qcom/msm-pm660l.dtsi | 395 ++ .../boot/dts/qcom/msm-pmfalcon-rpm-regulator.dtsi | 298 -- arch/arm/boot/dts/qcom/msm-pmfalcon.dtsi | 608 --- .../qcom/msm8998-interposer-camera-sensor-cdp.dtsi | 70 +- .../qcom/msm8998-interposer-camera-sensor-mtp.dtsi | 70 +- .../qcom/msm8998-interposer-camera-sensor-qrd.dtsi | 66 +- .../qcom/msm8998-interposer-msmfalcon-audio.dtsi | 69 - .../dts/qcom/msm8998-interposer-msmfalcon-cdp.dtsi | 512 --- .../dts/qcom/msm8998-interposer-msmfalcon-mtp.dtsi | 505 --- .../dts/qcom/msm8998-interposer-msmfalcon.dtsi | 3154 ------------- .../boot/dts/qcom/msm8998-interposer-pm660.dtsi | 241 + .../boot/dts/qcom/msm8998-interposer-pmfalcon.dtsi | 241 - .../dts/qcom/msm8998-interposer-sdm660-audio.dtsi | 69 + .../dts/qcom/msm8998-interposer-sdm660-cdp.dtsi | 512 +++ .../dts/qcom/msm8998-interposer-sdm660-mtp.dtsi | 505 +++ .../boot/dts/qcom/msm8998-interposer-sdm660.dtsi | 3154 +++++++++++++ .../dts/qcom/msm8998-v2-interposer-msmfalcon.dtsi | 851 ---- .../dts/qcom/msm8998-v2-interposer-sdm660.dtsi | 851 ++++ .../qcom/msm8998-v2.1-interposer-msmfalcon-cdp.dts | 155 - .../qcom/msm8998-v2.1-interposer-msmfalcon-mtp.dts | 184 - .../qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dts | 169 - .../msm8998-v2.1-interposer-msmfalcon-qrd.dtsi | 125 - .../qcom/msm8998-v2.1-interposer-msmfalcon.dtsi | 18 - .../qcom/msm8998-v2.1-interposer-sdm660-cdp.dts | 155 + .../qcom/msm8998-v2.1-interposer-sdm660-mtp.dts | 184 + .../qcom/msm8998-v2.1-interposer-sdm660-qrd.dts | 169 + .../qcom/msm8998-v2.1-interposer-sdm660-qrd.dtsi | 125 + .../dts/qcom/msm8998-v2.1-interposer-sdm660.dtsi | 18 + arch/arm/boot/dts/qcom/msmfalcon-audio.dtsi | 248 -- arch/arm/boot/dts/qcom/msmfalcon-blsp.dtsi | 569 --- arch/arm/boot/dts/qcom/msmfalcon-bus.dtsi | 1284 ------ .../boot/dts/qcom/msmfalcon-camera-sensor-cdp.dtsi | 384 -- .../boot/dts/qcom/msmfalcon-camera-sensor-mtp.dtsi | 384 -- arch/arm/boot/dts/qcom/msmfalcon-camera.dtsi | 850 ---- arch/arm/boot/dts/qcom/msmfalcon-cdp.dts | 25 - arch/arm/boot/dts/qcom/msmfalcon-cdp.dtsi | 95 - arch/arm/boot/dts/qcom/msmfalcon-common.dtsi | 324 -- arch/arm/boot/dts/qcom/msmfalcon-coresight.dtsi | 1849 -------- arch/arm/boot/dts/qcom/msmfalcon-gpu.dtsi | 271 -- .../boot/dts/qcom/msmfalcon-internal-codec-cdp.dts | 73 - .../boot/dts/qcom/msmfalcon-internal-codec-mtp.dts | 74 - .../msmfalcon-internal-codec-pm3falcon-cdp.dts | 25 - .../msmfalcon-internal-codec-pm3falcon-mtp.dts | 25 - .../msmfalcon-internal-codec-pm3falcon-rcm.dts | 25 - .../boot/dts/qcom/msmfalcon-internal-codec-rcm.dts | 73 - arch/arm/boot/dts/qcom/msmfalcon-ion.dtsi | 47 - arch/arm/boot/dts/qcom/msmfalcon-lpi.dtsi | 182 - arch/arm/boot/dts/qcom/msmfalcon-mdss-panels.dtsi | 83 - arch/arm/boot/dts/qcom/msmfalcon-mdss-pll.dtsi | 82 - arch/arm/boot/dts/qcom/msmfalcon-mdss.dtsi | 579 --- arch/arm/boot/dts/qcom/msmfalcon-mtp.dts | 25 - arch/arm/boot/dts/qcom/msmfalcon-mtp.dtsi | 99 - arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi | 1293 ------ arch/arm/boot/dts/qcom/msmfalcon-pm.dtsi | 821 ---- arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-cdp.dts | 25 - arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-mtp.dts | 25 - arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-qrd.dts | 25 - arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-rcm.dts | 25 - .../arm/boot/dts/qcom/msmfalcon-pm3falcon-rumi.dts | 146 - arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-sim.dts | 111 - arch/arm/boot/dts/qcom/msmfalcon-qrd.dts | 25 - arch/arm/boot/dts/qcom/msmfalcon-qrd.dtsi | 24 - arch/arm/boot/dts/qcom/msmfalcon-rcm.dts | 25 - arch/arm/boot/dts/qcom/msmfalcon-regulator.dtsi | 498 --- arch/arm/boot/dts/qcom/msmfalcon-rumi.dts | 146 - arch/arm/boot/dts/qcom/msmfalcon-sim.dts | 111 - arch/arm/boot/dts/qcom/msmfalcon-smp2p.dtsi | 244 - arch/arm/boot/dts/qcom/msmfalcon-vidc.dtsi | 264 -- arch/arm/boot/dts/qcom/msmfalcon-wcd.dtsi | 197 - arch/arm/boot/dts/qcom/msmfalcon-wsa881x.dtsi | 79 - arch/arm/boot/dts/qcom/msmfalcon.dtsi | 2278 ---------- arch/arm/boot/dts/qcom/msmtriton-coresight.dtsi | 2 +- arch/arm/boot/dts/qcom/msmtriton-regulator.dtsi | 134 +- arch/arm/boot/dts/qcom/msmtriton-rumi.dts | 2 +- arch/arm/boot/dts/qcom/msmtriton.dtsi | 50 +- arch/arm/boot/dts/qcom/sda660-cdp.dts | 25 + arch/arm/boot/dts/qcom/sda660-mtp.dts | 25 + arch/arm/boot/dts/qcom/sda660-pm660a-cdp.dts | 25 + arch/arm/boot/dts/qcom/sda660-pm660a-mtp.dts | 25 + arch/arm/boot/dts/qcom/sda660-pm660a-rcm.dts | 25 + arch/arm/boot/dts/qcom/sda660-rcm.dts | 25 + arch/arm/boot/dts/qcom/sda660.dtsi | 19 + arch/arm/boot/dts/qcom/sdm660-audio.dtsi | 248 ++ arch/arm/boot/dts/qcom/sdm660-blsp.dtsi | 569 +++ arch/arm/boot/dts/qcom/sdm660-bus.dtsi | 1284 ++++++ .../boot/dts/qcom/sdm660-camera-sensor-cdp.dtsi | 384 ++ .../boot/dts/qcom/sdm660-camera-sensor-mtp.dtsi | 384 ++ arch/arm/boot/dts/qcom/sdm660-camera.dtsi | 850 ++++ arch/arm/boot/dts/qcom/sdm660-cdp.dts | 25 + arch/arm/boot/dts/qcom/sdm660-cdp.dtsi | 95 + arch/arm/boot/dts/qcom/sdm660-common.dtsi | 324 ++ arch/arm/boot/dts/qcom/sdm660-coresight.dtsi | 1849 ++++++++ arch/arm/boot/dts/qcom/sdm660-gpu.dtsi | 271 ++ .../boot/dts/qcom/sdm660-internal-codec-cdp.dts | 73 + .../boot/dts/qcom/sdm660-internal-codec-mtp.dts | 74 + .../dts/qcom/sdm660-internal-codec-pm660a-cdp.dts | 25 + .../dts/qcom/sdm660-internal-codec-pm660a-mtp.dts | 25 + .../dts/qcom/sdm660-internal-codec-pm660a-rcm.dts | 25 + .../boot/dts/qcom/sdm660-internal-codec-rcm.dts | 73 + arch/arm/boot/dts/qcom/sdm660-ion.dtsi | 47 + arch/arm/boot/dts/qcom/sdm660-lpi.dtsi | 182 + arch/arm/boot/dts/qcom/sdm660-mdss-panels.dtsi | 83 + arch/arm/boot/dts/qcom/sdm660-mdss-pll.dtsi | 82 + arch/arm/boot/dts/qcom/sdm660-mdss.dtsi | 579 +++ arch/arm/boot/dts/qcom/sdm660-mtp.dts | 25 + arch/arm/boot/dts/qcom/sdm660-mtp.dtsi | 99 + arch/arm/boot/dts/qcom/sdm660-pinctrl.dtsi | 1293 ++++++ arch/arm/boot/dts/qcom/sdm660-pm.dtsi | 821 ++++ arch/arm/boot/dts/qcom/sdm660-pm660a-cdp.dts | 25 + arch/arm/boot/dts/qcom/sdm660-pm660a-mtp.dts | 25 + arch/arm/boot/dts/qcom/sdm660-pm660a-qrd.dts | 25 + arch/arm/boot/dts/qcom/sdm660-pm660a-rcm.dts | 25 + arch/arm/boot/dts/qcom/sdm660-pm660a-rumi.dts | 146 + arch/arm/boot/dts/qcom/sdm660-pm660a-sim.dts | 111 + arch/arm/boot/dts/qcom/sdm660-qrd.dts | 25 + arch/arm/boot/dts/qcom/sdm660-qrd.dtsi | 24 + arch/arm/boot/dts/qcom/sdm660-rcm.dts | 25 + arch/arm/boot/dts/qcom/sdm660-regulator.dtsi | 498 +++ arch/arm/boot/dts/qcom/sdm660-rumi.dts | 146 + arch/arm/boot/dts/qcom/sdm660-sim.dts | 111 + arch/arm/boot/dts/qcom/sdm660-smp2p.dtsi | 244 + arch/arm/boot/dts/qcom/sdm660-vidc.dtsi | 264 ++ arch/arm/boot/dts/qcom/sdm660-wcd.dtsi | 197 + arch/arm/boot/dts/qcom/sdm660-wsa881x.dtsi | 79 + arch/arm/boot/dts/qcom/sdm660.dtsi | 2278 ++++++++++ arch/arm/configs/msmcortex_defconfig | 4 +- arch/arm/configs/msmfalcon-perf_defconfig | 621 --- arch/arm/configs/msmfalcon_defconfig | 665 --- arch/arm/configs/sdm660-perf_defconfig | 621 +++ arch/arm/configs/sdm660_defconfig | 665 +++ arch/arm/mach-qcom/Kconfig | 6 +- arch/arm/mach-qcom/Makefile | 2 +- arch/arm/mach-qcom/board-660.c | 50 + arch/arm/mach-qcom/board-falcon.c | 50 - arch/arm64/Kconfig.platforms | 6 +- arch/arm64/configs/msmcortex-perf_defconfig | 2 +- arch/arm64/configs/msmcortex_defconfig | 2 +- arch/arm64/configs/msmfalcon-perf_defconfig | 645 --- arch/arm64/configs/msmfalcon_defconfig | 712 --- arch/arm64/configs/sdm660-perf_defconfig | 645 +++ arch/arm64/configs/sdm660_defconfig | 712 +++ drivers/clk/msm/Kconfig | 2 +- drivers/clk/qcom/Kconfig | 22 +- drivers/clk/qcom/Makefile | 6 +- drivers/clk/qcom/clk-smd-rpm.c | 142 +- drivers/clk/qcom/gcc-msmfalcon.c | 3322 -------------- drivers/clk/qcom/gcc-sdm660.c | 3322 ++++++++++++++ drivers/clk/qcom/gpucc-msmfalcon.c | 498 --- drivers/clk/qcom/gpucc-sdm660.c | 498 +++ drivers/clk/qcom/mdss/mdss-pll.c | 6 +- drivers/clk/qcom/mdss/mdss-pll.h | 2 +- drivers/clk/qcom/mmcc-msmfalcon.c | 3056 ------------- drivers/clk/qcom/mmcc-sdm660.c | 3056 +++++++++++++ drivers/clk/qcom/vdd-level-660.h | 152 + drivers/clk/qcom/vdd-level-falcon.h | 152 - drivers/crypto/Kconfig | 8 +- drivers/leds/leds-qpnp-flash-v2.c | 2 +- drivers/leds/leds-qpnp-wled.c | 34 +- drivers/phy/Makefile | 2 +- drivers/phy/phy-qcom-ufs-qmp-v3-660.c | 260 ++ drivers/phy/phy-qcom-ufs-qmp-v3-660.h | 283 ++ drivers/phy/phy-qcom-ufs-qmp-v3-falcon.c | 260 -- drivers/phy/phy-qcom-ufs-qmp-v3-falcon.h | 283 -- drivers/pinctrl/qcom/Kconfig | 6 +- drivers/pinctrl/qcom/Makefile | 2 +- drivers/pinctrl/qcom/pinctrl-msmfalcon.c | 1722 -------- drivers/pinctrl/qcom/pinctrl-sdm660.c | 1722 ++++++++ drivers/platform/msm/qpnp-revid.c | 4 +- drivers/power/qcom-charger/qpnp-fg-gen3.c | 2 +- drivers/power/qcom-charger/qpnp-smb2.c | 2 +- drivers/regulator/cpr4-mmss-ldo-regulator.c | 94 +- drivers/regulator/msm_gfx_ldo.c | 12 +- drivers/soc/qcom/socinfo.c | 14 +- drivers/thermal/msm-tsens.c | 8 +- include/dt-bindings/clock/qcom,gcc-msmfalcon.h | 212 - include/dt-bindings/clock/qcom,gcc-sdm660.h | 212 + include/dt-bindings/clock/qcom,gpu-msmfalcon.h | 45 - include/dt-bindings/clock/qcom,gpu-sdm660.h | 45 + include/dt-bindings/clock/qcom,mmcc-msmfalcon.h | 218 - include/dt-bindings/clock/qcom,mmcc-sdm660.h | 218 + include/linux/qpnp/qpnp-revid.h | 6 +- include/soc/qcom/socinfo.h | 14 +- include/uapi/linux/msm_mdp.h | 2 +- sound/soc/codecs/Kconfig | 6 +- sound/soc/codecs/Makefile | 2 +- sound/soc/codecs/msmfalcon_cdc/Kconfig | 3 - sound/soc/codecs/msmfalcon_cdc/Makefile | 2 - sound/soc/codecs/msmfalcon_cdc/msm-analog-cdc.c | 4645 -------------------- sound/soc/codecs/msmfalcon_cdc/msm-analog-cdc.h | 240 - sound/soc/codecs/msmfalcon_cdc/msm-cdc-common.h | 66 - sound/soc/codecs/msmfalcon_cdc/msm-digital-cdc.c | 2039 --------- sound/soc/codecs/msmfalcon_cdc/msm-digital-cdc.h | 93 - sound/soc/codecs/msmfalcon_cdc/msmfalcon-cdc-irq.c | 441 -- sound/soc/codecs/msmfalcon_cdc/msmfalcon-cdc-irq.h | 34 - .../codecs/msmfalcon_cdc/msmfalcon-cdc-registers.h | 603 --- sound/soc/codecs/msmfalcon_cdc/msmfalcon-regmap.c | 471 -- sound/soc/codecs/sdm660_cdc/Kconfig | 3 + sound/soc/codecs/sdm660_cdc/Makefile | 2 + sound/soc/codecs/sdm660_cdc/msm-analog-cdc.c | 4645 ++++++++++++++++++++ sound/soc/codecs/sdm660_cdc/msm-analog-cdc.h | 240 + sound/soc/codecs/sdm660_cdc/msm-cdc-common.h | 66 + sound/soc/codecs/sdm660_cdc/msm-digital-cdc.c | 2039 +++++++++ sound/soc/codecs/sdm660_cdc/msm-digital-cdc.h | 93 + sound/soc/codecs/sdm660_cdc/sdm660-cdc-irq.c | 441 ++ sound/soc/codecs/sdm660_cdc/sdm660-cdc-irq.h | 34 + sound/soc/codecs/sdm660_cdc/sdm660-cdc-registers.h | 603 +++ sound/soc/codecs/sdm660_cdc/sdm660-regmap.c | 471 ++ sound/soc/msm/Kconfig | 18 +- sound/soc/msm/Makefile | 18 +- sound/soc/msm/msmfalcon-common.c | 2839 ------------ sound/soc/msm/msmfalcon-common.h | 115 - sound/soc/msm/msmfalcon-ext-dai-links.c | 1968 --------- sound/soc/msm/msmfalcon-external.c | 1841 -------- sound/soc/msm/msmfalcon-external.h | 54 - sound/soc/msm/msmfalcon-internal.c | 3089 ------------- sound/soc/msm/msmfalcon-internal.h | 32 - sound/soc/msm/sdm660-common.c | 2839 ++++++++++++ sound/soc/msm/sdm660-common.h | 115 + sound/soc/msm/sdm660-ext-dai-links.c | 1968 +++++++++ sound/soc/msm/sdm660-external.c | 1841 ++++++++ sound/soc/msm/sdm660-external.h | 54 + sound/soc/msm/sdm660-internal.c | 3089 +++++++++++++ sound/soc/msm/sdm660-internal.h | 32 + 263 files changed, 54269 insertions(+), 54269 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,msmfalcon-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm660-pinctrl.txt delete mode 100644 arch/arm/boot/dts/qcom/apqfalcon-cdp.dts delete mode 100644 arch/arm/boot/dts/qcom/apqfalcon-mtp.dts delete mode 100644 arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-cdp.dts delete mode 100644 arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-mtp.dts delete mode 100644 arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-rcm.dts delete mode 100644 arch/arm/boot/dts/qcom/apqfalcon-rcm.dts delete mode 100644 arch/arm/boot/dts/qcom/apqfalcon.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm-arm-smmu-660.dtsi delete mode 100644 arch/arm/boot/dts/qcom/msm-arm-smmu-falcon.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm-arm-smmu-impl-defs-660.dtsi delete mode 100644 arch/arm/boot/dts/qcom/msm-arm-smmu-impl-defs-falcon.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm-gdsc-660.dtsi delete mode 100644 arch/arm/boot/dts/qcom/msm-gdsc-falcon.dtsi delete mode 100644 arch/arm/boot/dts/qcom/msm-pm2falcon-rpm-regulator.dtsi delete mode 100644 arch/arm/boot/dts/qcom/msm-pm2falcon.dtsi delete mode 100644 arch/arm/boot/dts/qcom/msm-pm3falcon.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm-pm660-rpm-regulator.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm-pm660.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm-pm660a.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm-pm660l-rpm-regulator.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm-pm660l.dtsi delete mode 100644 arch/arm/boot/dts/qcom/msm-pmfalcon-rpm-regulator.dtsi delete mode 100644 arch/arm/boot/dts/qcom/msm-pmfalcon.dtsi delete mode 100644 arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-audio.dtsi delete mode 100644 arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-cdp.dtsi delete mode 100644 arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-mtp.dtsi delete mode 100644 arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm8998-interposer-pm660.dtsi delete mode 100644 arch/arm/boot/dts/qcom/msm8998-interposer-pmfalcon.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-audio.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-cdp.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-mtp.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm8998-interposer-sdm660.dtsi delete mode 100644 arch/arm/boot/dts/qcom/msm8998-v2-interposer-msmfalcon.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm8998-v2-interposer-sdm660.dtsi delete mode 100644 arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-cdp.dts delete mode 100644 arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-mtp.dts delete mode 100644 arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dts delete mode 100644 arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dtsi delete mode 100644 arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon.dtsi create mode 100644 arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-cdp.dts create mode 100644 arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-mtp.dts create mode 100644 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sound/soc/msm/sdm660-ext-dai-links.c create mode 100644 sound/soc/msm/sdm660-external.c create mode 100644 sound/soc/msm/sdm660-external.h create mode 100644 sound/soc/msm/sdm660-internal.c create mode 100644 sound/soc/msm/sdm660-internal.h diff --git a/Documentation/devicetree/bindings/arm/msm/msm.txt b/Documentation/devicetree/bindings/arm/msm/msm.txt index 9a96f74a8603..6dd0c2d9c011 100644 --- a/Documentation/devicetree/bindings/arm/msm/msm.txt +++ b/Documentation/devicetree/bindings/arm/msm/msm.txt @@ -89,11 +89,11 @@ SoCs: - MSMHAMSTER compatible = "qcom,msmhamster" -- MSMFALCON - compatible = "qcom,msmfalcon" +- SDM660 + compatible = "qcom,sdm660" -- APQFALCON - compatible = "qcom,apqfalcon" +- SDA660 + compatible = "qcom,sda660" - MSMTRITON compatible = "qcom,msmtriton" @@ -263,13 +263,13 @@ compatible = "qcom,msm8998-qrd" compatible = "qcom,msmhamster-rumi" compatible = "qcom,msmhamster-cdp" compatible = "qcom,msmhamster-mtp" -compatible = "qcom,msmfalcon-sim" -compatible = "qcom,msmfalcon-rumi" -compatible = "qcom,msmfalcon-cdp" -compatible = "qcom,msmfalcon-mtp" -compatible = "qcom,msmfalcon-qrd" -compatible = "qcom,apqfalcon-mtp" -compatible = "qcom,apqfalcon-cdp" +compatible = "qcom,sdm660-sim" +compatible = "qcom,sdm660-rumi" +compatible = "qcom,sdm660-cdp" +compatible = "qcom,sdm660-mtp" +compatible = "qcom,sdm660-qrd" +compatible = "qcom,sda660-mtp" +compatible = "qcom,sda660-cdp" compatible = "qcom,msmtriton-rumi" compatible = "qcom,msm8952-rumi" compatible = "qcom,msm8952-sim" diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-dbg.txt b/Documentation/devicetree/bindings/clock/qcom,gcc-dbg.txt index e1ccf69b751b..5c770864898a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-dbg.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-dbg.txt @@ -3,7 +3,7 @@ Qualcomm Technologies Inc Global Clock Debug Controller Binding Required properties : - compatible: shall contain the following: - "qcom,gcc-debug-msmfalcon" + "qcom,gcc-debug-sdm660" - reg: shall contain global clock controller base register offset location and length. @@ -24,7 +24,7 @@ In the case where "qcom,cc-count" is > 1, the below needs to be defined. Example: clock_gcc: clock-controller@100000 { - compatible = "qcom,gcc-msmfalcon", "syscon"; + compatible = "qcom,gcc-sdm660", "syscon"; .... }; @@ -44,7 +44,7 @@ Example: }; clock_debug: qcom,cc-debug@62000 { - compatible = "qcom,gcc-debug-msmfalcon"; + compatible = "qcom,gcc-debug-sdm660"; reg = <0x62000 0x4>; reg-names = "cc_offset"; clocks = <&clock_rpmcc RPM_XO_CLK_SRC>; diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt index 1330d2bdc18d..479a83df3808 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt @@ -14,7 +14,7 @@ Required properties : "qcom,gcc-msm8974pro" "qcom,gcc-msm8974pro-ac" "qcom,gcc-msm8996" - "qcom,gcc-msmfalcon" + "qcom,gcc-sdm660" - reg : shall contain base register location and length - #clock-cells : shall contain 1 diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt index 4d8f87225230..8eadd50e09f6 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt @@ -4,7 +4,7 @@ Qualcomm Technologies, Inc Graphics Clock & Reset Controller Binding Required properties : - compatible : shall contain only one of the following: - "qcom,gpucc-msmfalcon", + "qcom,gpucc-sdm660", "qcom,gpucc-msmtriton" - reg : shall contain base register location and length @@ -16,7 +16,7 @@ Optional properties : Example: clock-controller@4000000 { - compatible = "qcom,gpucc-msmfalcon"; + compatible = "qcom,gpucc-sdm660"; reg = <<0x5065000 0x10000>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt index 6aaf89c47781..4b1057288b2f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt @@ -10,7 +10,7 @@ Required properties : "qcom,mmcc-msm8960" "qcom,mmcc-msm8974" "qcom,mmcc-msm8996" - "qcom,mmcc-msmfalcon" + "qcom,mmcc-sdm660" - reg : shall contain base register location and length - #clock-cells : shall contain 1 diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt index f825a44e5911..685fb3aa2e61 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt @@ -13,7 +13,7 @@ Required properties : "qcom,rpmcc-msm8916", "qcom,rpmcc" "qcom,rpmcc-apq8064", "qcom,rpmcc" "qcom,rpmcc-msm8996", "qcom,rpmcc" - "qcom,rpmcc-msmfalcon", "qcom,rpmcc" + "qcom,rpmcc-sdm660", "qcom,rpmcc" - #clock-cells : shall contain 1 @@ -38,7 +38,7 @@ Example: }; }; - The below are applicable for MSM8996 & MSMFalcon. + The below are applicable for MSM8996 & SDM660. rpmcc: clock-controller { compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; diff --git a/Documentation/devicetree/bindings/fb/mdss-pll.txt b/Documentation/devicetree/bindings/fb/mdss-pll.txt index e9e4a9af381b..5d9a703c4823 100644 --- a/Documentation/devicetree/bindings/fb/mdss-pll.txt +++ b/Documentation/devicetree/bindings/fb/mdss-pll.txt @@ -15,7 +15,7 @@ Required properties: "qcom,mdss_hdmi_pll_8996_v2", "qcom,mdss_dsi_pll_8996_v2", "qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_hdmi_pll_8996_v3_1p8", "qcom,mdss_dsi_pll_8998", "qcom,mdss_dp_pll_8998", - "qcom,mdss_hdmi_pll_8998", "qcom,mdss_dsi_pll_msmfalcon" + "qcom,mdss_hdmi_pll_8998", "qcom,mdss_dsi_pll_sdm660" - cell-index: Specifies the controller used - reg: offset and length of the register set for the device. - reg-names : names to refer to register sets related to this device diff --git a/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt b/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt index 581f1128355c..da54fb11ffd4 100644 --- a/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt +++ b/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt @@ -98,7 +98,7 @@ Optional properties: used if qcom,thermal-derate-en is specified. Allowed values are: 0, 15, 30, 45 for pmi8998. - 0, 20, 40, 60 for pm2falcon. + 0, 20, 40, 60 for pm660l. - qcom,thermal-thrsh1 : Integer property to specify OTST1 threshold for thermal mitigation. Unit is in Celsius. Accepted values are: diff --git a/Documentation/devicetree/bindings/leds/leds-qpnp-wled.txt b/Documentation/devicetree/bindings/leds/leds-qpnp-wled.txt index 74cee0d6ba0d..a77a291a99da 100644 --- a/Documentation/devicetree/bindings/leds/leds-qpnp-wled.txt +++ b/Documentation/devicetree/bindings/leds/leds-qpnp-wled.txt @@ -28,13 +28,13 @@ Optional properties for WLED: - qcom,vref-uv : maximum reference voltage in uV. For pmi8994/8952/8996, supported values are from 300000 to 675000 with a step size of 25000, the default value is 350000. - For pmi8998/pm2falcon, supported values are from 60000 to 397500 + For pmi8998/pm660l, supported values are from 60000 to 397500 with a step size of 22500, the default value is 127500. - qcom,switch-freq-khz : switch frequency in khz. default is 800. - qcom,ovp-mv : Over voltage protection threshold in mV. Default is 29500. Supported values are: - 31000, 29500, 19400, 17800 for pmi8994/8952/8996. - - 31100, 29600, 19600, 18100 for pmi8998/pm2falcon. + - 31100, 29600, 19600, 18100 for pmi8998/pm660l. Should only be used if qcom,disp-type-amoled is not specified. - qcom,ilim-ma : Current limit threshold in mA. @@ -42,7 +42,7 @@ Optional properties for WLED: and AMOLED is 385mA. Supported values are: - 105, 385, 660, 980, 1150, 1420, 1700, 1980. - For pmi8998/pm2falcon, default value for LCD is + For pmi8998/pm660l, default value for LCD is 970mA and AMOLED is 620mA. Supported values are: - 105, 280, 450, 620, 970, 1150, 1300, 1500. @@ -81,7 +81,7 @@ Optional properties if 'qcom,disp-type-amoled' is mentioned in DT: - qcom,vref-psm-mv : reference psm voltage in mv. default for amoled is 450. - qcom,avdd-mode-spmi: Boolean property to enable AMOLED_VOUT programming via SPMI. If not specified, AMOLED_VOUT is programmed via S-wire. This can be specified only for newer - PMICs like pmi8998/pm2falcon. + PMICs like pmi8998/pm660l. - qcom,avdd-target-voltage-mv: The voltage required for AMOLED_VOUT. Accepted values are in the range of 5650 to 7900 in steps of 150. Default value is 7600. Unit is in mV. For old revisions, accepted values are: 7900, 7600, 7300, 6400, 6100, diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msmfalcon-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msmfalcon-pinctrl.txt deleted file mode 100644 index 929ba3ee688b..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msmfalcon-pinctrl.txt +++ /dev/null @@ -1,199 +0,0 @@ -Qualcomm Technologies, Inc. MSMFALCON TLMM block - -This binding describes the Top Level Mode Multiplexer block found in the -MSMFALCON platform. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,msmfalcon-pinctrl" - -- reg: - Usage: required - Value type: - Definition: the base address and size of the TLMM register space. - -- interrupts: - Usage: required - Value type: - Definition: should specify the TLMM summary IRQ. - -- interrupt-controller: - Usage: required - Value type: - Definition: identifies this node as an interrupt controller - -- #interrupt-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-controller: - Usage: required - Value type: - Definition: identifies this node as a gpio controller - -- #gpio-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - - -PIN CONFIGURATION NODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of gpio pins affected by the properties specified in - this subnode. Valid pins are: - gpio0-gpio149, - sdc1_clk, - sdc1_cmd, - sdc1_data - sdc2_clk, - sdc2_cmd, - sdc2_data - sdc1_rclk, - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. Functions are only valid for gpio pins. - Valid values are: - - blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, - bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, - qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, - dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, - blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, - mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, - atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, - cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, - pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, - qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, - qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, - atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, - atest_usb20, atest_char0, dac_calib10, qdss_stm10, - qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, - blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, - qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, - qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, - dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, - qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, - dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, - dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, - dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, - dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, - sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, - qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, - uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, - blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, - qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, - blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, - cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, - blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, - qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, - isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, - qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, - sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, - gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, - qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, - tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, - qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, - sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, - sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, - ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, - blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, - pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, - qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, - qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, - gpio - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configued as no pull. - -- bias-pull-down: - Usage: optional - Value type: - Definition: The specified pins should be configued as pull down. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configued as pull up. - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - Not valid for sdc pins. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - Not valid for sdc pins. - -- drive-strength: - Usage: optional - Value type: - Definition: Selects the drive strength for the specified pins, in mA. - Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 - -Example: - - tlmm: pinctrl@01010000 { - compatible = "qcom,msmfalcon-pinctrl"; - reg = <0x01010000 0x300000>; - interrupts = <0 208 0>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - - uart_console_active: uart_console_active { - mux { - pins = "gpio4", "gpio5"; - function = "blsp_uart8"; - }; - - config { - pins = "gpio4", "gpio5"; - drive-strength = <2>; - bias-disable; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-pinctrl.txt new file mode 100644 index 000000000000..dbd4baf0825a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-pinctrl.txt @@ -0,0 +1,199 @@ +Qualcomm Technologies, Inc. SDM660 TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +SDM660 platform. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,sdm660-pinctrl" + +- reg: + Usage: required + Value type: + Definition: the base address and size of the TLMM register space. + +- interrupts: + Usage: required + Value type: + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +- gpio-controller: + Usage: required + Value type: + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: + Definition: List of gpio pins affected by the properties specified in + this subnode. Valid pins are: + gpio0-gpio149, + sdc1_clk, + sdc1_cmd, + sdc1_data + sdc2_clk, + sdc2_cmd, + sdc2_data + sdc1_rclk, + +- function: + Usage: required + Value type: + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values are: + + blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, + bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, + qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, + dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, + blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, + mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, + atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, + cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, + pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, + qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, + qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, + atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, + atest_usb20, atest_char0, dac_calib10, qdss_stm10, + qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, + blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, + qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, + qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, + dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, + qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, + dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, + dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, + dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, + dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, + sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, + qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, + uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, + blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, + qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, + blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, + cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, + blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, + qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, + isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, + qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, + sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, + gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, + qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, + tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, + qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, + sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, + sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, + ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, + blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, + pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, + qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, + qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, + gpio + +- bias-disable: + Usage: optional + Value type: + Definition: The specified pins should be configued as no pull. + +- bias-pull-down: + Usage: optional + Value type: + Definition: The specified pins should be configued as pull down. + +- bias-pull-up: + Usage: optional + Value type: + Definition: The specified pins should be configued as pull up. + +- output-high: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + high. + Not valid for sdc pins. + +- output-low: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + low. + Not valid for sdc pins. + +- drive-strength: + Usage: optional + Value type: + Definition: Selects the drive strength for the specified pins, in mA. + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 + +Example: + + tlmm: pinctrl@01010000 { + compatible = "qcom,sdm660-pinctrl"; + reg = <0x01010000 0x300000>; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + uart_console_active: uart_console_active { + mux { + pins = "gpio4", "gpio5"; + function = "blsp_uart8"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/regulator/cpr4-mmss-ldo-regulator.txt b/Documentation/devicetree/bindings/regulator/cpr4-mmss-ldo-regulator.txt index 41cec67b7627..851528517f4c 100644 --- a/Documentation/devicetree/bindings/regulator/cpr4-mmss-ldo-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/cpr4-mmss-ldo-regulator.txt @@ -28,7 +28,7 @@ MMSS LDO specific properties: Usage: required Value type: Definition: should be the following: - "qcom,cpr4-msmfalcon-mmss-ldo-regulator". + "qcom,cpr4-sdm660-mmss-ldo-regulator". - clocks Usage: required @@ -71,7 +71,7 @@ MMSS specific properties: Usage: required Value type: Definition: Specifies the number of fuse corners. This value must be 6 - for msmfalcon GFX LDO. These fuse corners are: MinSVS, + for sdm660 GFX LDO. These fuse corners are: MinSVS, LowSVS, SVS, SVSP, NOM and NOMP. The open-loop voltage fuses are allocated for LowSVS, SVS, NOM and NOMP corners. The open-loop voltages for MinSVS and SVSP are derived by @@ -217,7 +217,7 @@ Example ======= gfx_cpr: cpr4-ctrl@05061000 { - compatible = "qcom,cpr4-msmfalcon-mmss-ldo-regulator"; + compatible = "qcom,cpr4-sdm660-mmss-ldo-regulator"; reg = <0x05061000 0x4000>, <0x00784000 0x1000>; reg-names = "cpr_ctrl", "fuse_base"; interrupts = ; @@ -233,7 +233,7 @@ gfx_cpr: cpr4-ctrl@05061000 { vdd-supply = <&gfx_stub_vreg>; mem-acc-supply = <&gfx_mem_acc_vreg>; - system-supply = <&pm2falcon_s3_level>; /* vdd_cx */ + system-supply = <&pm660l_s3_level>; /* vdd_cx */ qcom,voltage-step = <5000>; vdd-thread0-ldo-supply = <&gfx_ldo_vreg>; diff --git a/Documentation/devicetree/bindings/regulator/msm_gfx_ldo.txt b/Documentation/devicetree/bindings/regulator/msm_gfx_ldo.txt index 42c735e26d66..dcbb120eea2a 100644 --- a/Documentation/devicetree/bindings/regulator/msm_gfx_ldo.txt +++ b/Documentation/devicetree/bindings/regulator/msm_gfx_ldo.txt @@ -9,7 +9,7 @@ This document describes the bindings that apply for the GFX LDO regulator. Usage: required Value type: Definition: should be "qcom,msm8953-gfx-ldo" for MSM8953 and - "qcom,msmfalcon-gfx-ldo" for MSMFALCON + "qcom,sdm660-gfx-ldo" for SDM660 - reg Usage: required diff --git a/Documentation/devicetree/bindings/regulator/qpnp-lcdb-regulator.txt b/Documentation/devicetree/bindings/regulator/qpnp-lcdb-regulator.txt index 68d23d0f5523..8b3a38da0834 100644 --- a/Documentation/devicetree/bindings/regulator/qpnp-lcdb-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/qpnp-lcdb-regulator.txt @@ -209,7 +209,7 @@ Properties below are specific to BOOST subnode only. Example ======= -pm2falcon_lcdb: qpnp-lcdb@ec00 { +pm660l_lcdb: qpnp-lcdb@ec00 { compatible = "qcom,qpnp-lcdb-regulator"; #address-cells = <1>; #size-cells = <1>; diff --git a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt index 8957ff9dc9ee..f71d1a909d07 100644 --- a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt +++ b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt @@ -1610,10 +1610,10 @@ Example: asoc-wsa-codec-prefixes = "SpkrMono"; }; -* MSMFALCON ASoC Machine driver +* SDM660 ASoC Machine driver Required properties: -- compatible : "qcom,msmfalcon-asoc-snd" +- compatible : "qcom,sdm660-asoc-snd" - qcom,model : The user-visible name of this sound card. - qcom,msm-hs-micbias-type : This property is used to recognize the headset micbias type, internal or external. @@ -1666,8 +1666,8 @@ mclk frequency needs to be configured for internal and external PA. Example: sound { - compatible = "qcom,msmfalcon-asoc-snd"; - qcom,model = "msmfalcon-snd-card"; + compatible = "qcom,sdm660-asoc-snd"; + qcom,model = "sdm660-snd-card"; qcom,msm-mclk-freq = <9600000>; qcom,msm-mbhc-hphl-swh = <0>; qcom,msm-mbhc-gnd-swh = <0>; @@ -2151,11 +2151,11 @@ Example: asoc-codec-names = "msm-stub-codec.1"; }; -* MSMFALCON ASoC Slimbus Machine driver +* SDM660 ASoC Slimbus Machine driver Required properties: -- compatible : "qcom,msmfalcon-asoc-snd-tasha" for tasha codec, - "qcom,msmfalcon-asoc-snd-tavil" for tavil codec. +- compatible : "qcom,sdm660-asoc-snd-tasha" for tasha codec, + "qcom,sdm660-asoc-snd-tavil" for tavil codec. - qcom,model : The user-visible name of this sound card. - qcom,msm-mclk-freq : MCLK frequency value for external codec - qcom,msm-gpios : Lists down all the gpio sets that are supported. @@ -2195,8 +2195,8 @@ Optional properties: Example: sound-9335 { - compatible = "qcom,msmfalcon-asoc-snd-tasha"; - qcom,model = "msmfalcon-tasha-snd-card"; + compatible = "qcom,sdm660-asoc-snd-tasha"; + qcom,model = "sdm660-tasha-snd-card"; qcom,audio-routing = "RX_BIAS", "MCLK", diff --git a/Documentation/devicetree/bindings/thermal/tsens.txt b/Documentation/devicetree/bindings/thermal/tsens.txt index ada060d19a9b..b4183bace25d 100644 --- a/Documentation/devicetree/bindings/thermal/tsens.txt +++ b/Documentation/devicetree/bindings/thermal/tsens.txt @@ -31,7 +31,7 @@ Required properties: should be "qcom,msmgold-tsens" for gold TSENS driver. should be "qcom,msm8998-tsens" for 8998 TSENS driver. should be "qcom,msmhamster-tsens" for hamster TSENS driver. - should be "qcom,msmfalcon-tsens" for falcon TSENS driver. + should be "qcom,sdm660-tsens" for 660 TSENS driver. should be "qcom,msmtriton-tsens" for triton TSENS driver. The compatible property is used to identify the respective fusemap to use for the corresponding SoC. diff --git a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt index 66142b4cd880..f836fc7ab439 100644 --- a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt +++ b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt @@ -10,7 +10,7 @@ Required properties: - compatible : compatible list, contains "qcom,ufs-phy-qmp-20nm" or "qcom,ufs-phy-qmp-14nm" or "qcom,ufs-phy-qmp-v3" or "qcom,ufs-phy-qrbtc-v2" or - "qcom,ufs-phy-qmp-v3-falcon" + "qcom,ufs-phy-qmp-v3-660" according to the relevant phy in use. - reg : should contain PHY register address space (mandatory), - reg-names : indicates various resources passed to driver (via reg proptery) by name. diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile index 9b702a7bf08e..262acc21ccff 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -130,36 +130,36 @@ dtb-$(CONFIG_ARCH_MSM8998) += msm8998-sim.dtb \ apq8998-v2.1-cdp.dtb \ apq8998-v2.1-qrd.dtb \ apq8998-v2.1-mediabox.dtb \ - msm8998-v2.1-interposer-msmfalcon-cdp.dtb \ - msm8998-v2.1-interposer-msmfalcon-mtp.dtb \ - msm8998-v2.1-interposer-msmfalcon-qrd.dtb + msm8998-v2.1-interposer-sdm660-cdp.dtb \ + msm8998-v2.1-interposer-sdm660-mtp.dtb \ + msm8998-v2.1-interposer-sdm660-qrd.dtb dtb-$(CONFIG_ARCH_MSMHAMSTER) += msmhamster-rumi.dtb -dtb-$(CONFIG_ARCH_MSMFALCON) += msmfalcon-sim.dtb \ - msmfalcon-internal-codec-cdp.dtb \ - msmfalcon-internal-codec-mtp.dtb \ - msmfalcon-internal-codec-rcm.dtb \ - msmfalcon-cdp.dtb \ - msmfalcon-mtp.dtb \ - msmfalcon-qrd.dtb \ - msmfalcon-rcm.dtb \ - msmfalcon-rumi.dtb \ - msmfalcon-pm3falcon-cdp.dtb \ - msmfalcon-pm3falcon-mtp.dtb \ - msmfalcon-pm3falcon-qrd.dtb \ - msmfalcon-pm3falcon-rcm.dtb \ - msmfalcon-pm3falcon-rumi.dtb \ - msmfalcon-internal-codec-pm3falcon-cdp.dtb \ - msmfalcon-internal-codec-pm3falcon-mtp.dtb \ - msmfalcon-internal-codec-pm3falcon-rcm.dtb \ - msmfalcon-pm3falcon-sim.dtb \ - apqfalcon-cdp.dtb \ - apqfalcon-mtp.dtb \ - apqfalcon-rcm.dtb \ - apqfalcon-pm3falcon-cdp.dtb \ - apqfalcon-pm3falcon-mtp.dtb \ - apqfalcon-pm3falcon-rcm.dtb +dtb-$(CONFIG_ARCH_SDM660) += sdm660-sim.dtb \ + sdm660-internal-codec-cdp.dtb \ + sdm660-internal-codec-mtp.dtb \ + sdm660-internal-codec-rcm.dtb \ + sdm660-cdp.dtb \ + sdm660-mtp.dtb \ + sdm660-qrd.dtb \ + sdm660-rcm.dtb \ + sdm660-rumi.dtb \ + sdm660-pm660a-cdp.dtb \ + sdm660-pm660a-mtp.dtb \ + sdm660-pm660a-qrd.dtb \ + sdm660-pm660a-rcm.dtb \ + sdm660-pm660a-rumi.dtb \ + sdm660-internal-codec-pm660a-cdp.dtb \ + sdm660-internal-codec-pm660a-mtp.dtb \ + sdm660-internal-codec-pm660a-rcm.dtb \ + sdm660-pm660a-sim.dtb \ + sda660-cdp.dtb \ + sda660-mtp.dtb \ + sda660-rcm.dtb \ + sda660-pm660a-cdp.dtb \ + sda660-pm660a-mtp.dtb \ + sda660-pm660a-rcm.dtb dtb-$(CONFIG_ARCH_MSMTRITON) += msmtriton-rumi.dtb diff --git a/arch/arm/boot/dts/qcom/apqfalcon-cdp.dts b/arch/arm/boot/dts/qcom/apqfalcon-cdp.dts deleted file mode 100644 index fc449860da0d..000000000000 --- a/arch/arm/boot/dts/qcom/apqfalcon-cdp.dts +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "apqfalcon.dtsi" -#include "msmfalcon-cdp.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. APQ FALCON PMFALCON + PM2FALCON CDP"; - compatible = "qcom,apqfalcon-cdp", "qcom,apqfalcon", "qcom,cdp"; - qcom,board-id = <1 0>; - qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, - <0x0001001b 0x0201011a 0x0 0x0>; -}; diff --git a/arch/arm/boot/dts/qcom/apqfalcon-mtp.dts b/arch/arm/boot/dts/qcom/apqfalcon-mtp.dts deleted file mode 100644 index c4f6e9fb30b9..000000000000 --- a/arch/arm/boot/dts/qcom/apqfalcon-mtp.dts +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "apqfalcon.dtsi" -#include "msmfalcon-mtp.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. APQ FALCON PMFALCON + PM2FALCON MTP"; - compatible = "qcom,apqfalcon-mtp", "qcom,apqfalcon", "qcom,mtp"; - qcom,board-id = <8 0>; - qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, - <0x0001001b 0x0201011a 0x0 0x0>; -}; diff --git a/arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-cdp.dts b/arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-cdp.dts deleted file mode 100644 index 851533931a61..000000000000 --- a/arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-cdp.dts +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "apqfalcon.dtsi" -#include "msmfalcon-cdp.dtsi" -#include "msm-pm3falcon.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. APQ FALCON PMFALCON + PM3FALCON CDP"; - compatible = "qcom,apqfalcon-cdp", "qcom,apqfalcon", "qcom,cdp"; - qcom,board-id = <1 0>; - qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; -}; diff --git a/arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-mtp.dts b/arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-mtp.dts deleted file mode 100644 index e7e8aeb9c2aa..000000000000 --- a/arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-mtp.dts +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "apqfalcon.dtsi" -#include "msmfalcon-mtp.dtsi" -#include "msm-pm3falcon.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. APQ FALCON PMFALCON + PM3FALCON MTP"; - compatible = "qcom,apqfalcon-mtp", "qcom,apqfalcon", "qcom,mtp"; - qcom,board-id = <8 0>; - qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; -}; diff --git a/arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-rcm.dts b/arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-rcm.dts deleted file mode 100644 index 68c4bd724ccd..000000000000 --- a/arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-rcm.dts +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "apqfalcon.dtsi" -#include "msmfalcon-cdp.dtsi" -#include "msm-pm3falcon.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. APQ FALCON PMFALCON + PM3FALCON RCM"; - compatible = "qcom,apqfalcon-cdp", "qcom,apqfalcon", "qcom,cdp"; - qcom,board-id = <21 0>; - qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; -}; diff --git a/arch/arm/boot/dts/qcom/apqfalcon-rcm.dts b/arch/arm/boot/dts/qcom/apqfalcon-rcm.dts deleted file mode 100644 index 8f4b164c55ca..000000000000 --- a/arch/arm/boot/dts/qcom/apqfalcon-rcm.dts +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "apqfalcon.dtsi" -#include "msmfalcon-cdp.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. APQ FALCON PMFALCON + PM2FALCON RCM"; - compatible = "qcom,apqfalcon-cdp", "qcom,apqfalcon", "qcom,cdp"; - qcom,board-id = <21 0>; - qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, - <0x0001001b 0x0201011a 0x0 0x0>; -}; diff --git a/arch/arm/boot/dts/qcom/apqfalcon.dtsi b/arch/arm/boot/dts/qcom/apqfalcon.dtsi deleted file mode 100644 index d4dc066f6a79..000000000000 --- a/arch/arm/boot/dts/qcom/apqfalcon.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "msmfalcon.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. APQ FALCON"; - compatible = "qcom,apqfalcon"; - qcom,msm-id = <324 0x0>; -}; diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-660.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-660.dtsi new file mode 100644 index 000000000000..874b97a3c965 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-arm-smmu-660.dtsi @@ -0,0 +1,212 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +&soc { + anoc2_smmu: arm,smmu-anoc2@16c0000 { + compatible = "qcom,smmu-v2"; + reg = <0x16c0000 0x40000>; + #iommu-cells = <1>; + qcom,register-save; + qcom,skip-init; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&clock_rpmcc RPM_AGGR2_NOC_CLK>; + clock-names = "smmu_aggr2_noc_clk"; + #clock-cells = <1>; + }; + + lpass_q6_smmu: arm,smmu-lpass_q6@5100000 { + compatible = "qcom,smmu-v2"; + reg = <0x5100000 0x40000>; + #iommu-cells = <1>; + qcom,register-save; + qcom,skip-init; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + vdd-supply = <&gdsc_hlos1_vote_lpass_adsp>; + clocks = <&clock_gcc HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; + clock-names = "lpass_q6_smmu_clk"; + #clock-cells = <1>; + }; + + mmss_bimc_smmu: arm,smmu-mmss@cd00000 { + compatible = "qcom,smmu-v2"; + reg = <0xcd00000 0x40000>; + #iommu-cells = <1>; + qcom,register-save; + qcom,no-smr-check; + qcom,skip-init; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + vdd-supply = <&gdsc_bimc_smmu>; + clocks = <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>; + clock-names = "mmss_mnoc_ahb_clk", + "mmssnoc_axi_clk", + "mmss_bimc_smmu_ahb_clk", + "mmss_bimc_smmu_axi_clk"; + #clock-cells = <1>; + qcom,bus-master-id = ; + }; + + kgsl_smmu: arm,smmu-kgsl@5040000 { + compatible = "qcom,smmu-v2"; + reg = <0x5040000 0x10000>; + #iommu-cells = <1>; + qcom,dynamic; + qcom,register-save; + qcom,skip-init; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + ; + vdd-supply = <&gdsc_gpu_cx>; + clocks = <&clock_gcc GCC_GPU_CFG_AHB_CLK>, + <&clock_gcc GCC_BIMC_GFX_CLK>, + <&clock_gcc GCC_GPU_BIMC_GFX_CLK>; + clock-names = "gcc_gpu_cfg_ahb_clk", + "gcc_bimc_gfx_clk", + "gcc_gpu_bimc_gfx_clk"; + #clock-cells = <1>; + }; + + turing_q6_smmu: arm,smmu-turing_q6@5180000 { + compatible = "qcom,smmu-v2"; + reg = <0x5180000 0x40000>; + #iommu-cells = <1>; + qcom,register-save; + qcom,skip-init; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + vdd-supply = <&gdsc_hlos1_vote_turing_adsp>; + clocks = <&clock_gcc HLOS1_VOTE_TURING_ADSP_SMMU_CLK>; + clock-names = "turing_q6_smmu_clk"; + #clock-cells = <1>; + }; + + iommu_test_device { + compatible = "iommu-debug-test"; + /* + * 42 shouldn't be used by anyone on the mmss_smmu. We just + * need _something_ here to get this node recognized by the + * SMMU driver. Our test uses ATOS, which doesn't use SIDs + * anyways, so using a dummy value is ok. + */ + iommus = <&mmss_bimc_smmu 42>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-falcon.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-falcon.dtsi deleted file mode 100644 index 713e1b1bc66a..000000000000 --- a/arch/arm/boot/dts/qcom/msm-arm-smmu-falcon.dtsi +++ /dev/null @@ -1,212 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -&soc { - anoc2_smmu: arm,smmu-anoc2@16c0000 { - compatible = "qcom,smmu-v2"; - reg = <0x16c0000 0x40000>; - #iommu-cells = <1>; - qcom,register-save; - qcom,skip-init; - #global-interrupts = <2>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&clock_rpmcc RPM_AGGR2_NOC_CLK>; - clock-names = "smmu_aggr2_noc_clk"; - #clock-cells = <1>; - }; - - lpass_q6_smmu: arm,smmu-lpass_q6@5100000 { - compatible = "qcom,smmu-v2"; - reg = <0x5100000 0x40000>; - #iommu-cells = <1>; - qcom,register-save; - qcom,skip-init; - #global-interrupts = <2>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - vdd-supply = <&gdsc_hlos1_vote_lpass_adsp>; - clocks = <&clock_gcc HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; - clock-names = "lpass_q6_smmu_clk"; - #clock-cells = <1>; - }; - - mmss_bimc_smmu: arm,smmu-mmss@cd00000 { - compatible = "qcom,smmu-v2"; - reg = <0xcd00000 0x40000>; - #iommu-cells = <1>; - qcom,register-save; - qcom,no-smr-check; - qcom,skip-init; - #global-interrupts = <2>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - vdd-supply = <&gdsc_bimc_smmu>; - clocks = <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_rpmcc MMSSNOC_AXI_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>; - clock-names = "mmss_mnoc_ahb_clk", - "mmssnoc_axi_clk", - "mmss_bimc_smmu_ahb_clk", - "mmss_bimc_smmu_axi_clk"; - #clock-cells = <1>; - qcom,bus-master-id = ; - }; - - kgsl_smmu: arm,smmu-kgsl@5040000 { - compatible = "qcom,smmu-v2"; - reg = <0x5040000 0x10000>; - #iommu-cells = <1>; - qcom,dynamic; - qcom,register-save; - qcom,skip-init; - #global-interrupts = <2>; - interrupts = , - , - , - , - , - , - , - , - , - ; - vdd-supply = <&gdsc_gpu_cx>; - clocks = <&clock_gcc GCC_GPU_CFG_AHB_CLK>, - <&clock_gcc GCC_BIMC_GFX_CLK>, - <&clock_gcc GCC_GPU_BIMC_GFX_CLK>; - clock-names = "gcc_gpu_cfg_ahb_clk", - "gcc_bimc_gfx_clk", - "gcc_gpu_bimc_gfx_clk"; - #clock-cells = <1>; - }; - - turing_q6_smmu: arm,smmu-turing_q6@5180000 { - compatible = "qcom,smmu-v2"; - reg = <0x5180000 0x40000>; - #iommu-cells = <1>; - qcom,register-save; - qcom,skip-init; - #global-interrupts = <2>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - vdd-supply = <&gdsc_hlos1_vote_turing_adsp>; - clocks = <&clock_gcc HLOS1_VOTE_TURING_ADSP_SMMU_CLK>; - clock-names = "turing_q6_smmu_clk"; - #clock-cells = <1>; - }; - - iommu_test_device { - compatible = "iommu-debug-test"; - /* - * 42 shouldn't be used by anyone on the mmss_smmu. We just - * need _something_ here to get this node recognized by the - * SMMU driver. Our test uses ATOS, which doesn't use SIDs - * anyways, so using a dummy value is ok. - */ - iommus = <&mmss_bimc_smmu 42>; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-impl-defs-660.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-impl-defs-660.dtsi new file mode 100644 index 000000000000..f060f2d7008c --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-arm-smmu-impl-defs-660.dtsi @@ -0,0 +1,409 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&kgsl_smmu { + attach-impl-defs = <0x6000 0x2378>, + <0x6060 0x1055>, + <0x678c 0x8>, + <0x6794 0x28>, + <0x6800 0x6>, + <0x6900 0x3ff>, + <0x6924 0x204>, + <0x6928 0x11000>, + <0x6930 0x800>, + <0x6960 0xffffffff>, + <0x6b64 0x1a5551>, + <0x6b68 0x9a82a382>; +}; + +&lpass_q6_smmu { + attach-impl-defs = <0x6000 0x2378>, + <0x6060 0x1055>, + <0x6070 0xe0>, + <0x6074 0xe0>, + <0x6078 0xe0>, + <0x607c 0xe0>, + <0x60f0 0xc0>, + <0x60f4 0xc8>, + <0x60f8 0xd0>, + <0x60fc 0xd8>, + <0x6170 0x0>, + <0x6174 0x30>, + <0x6178 0x60>, + <0x617c 0x90>, + <0x6270 0x0>, + <0x6274 0x2>, + <0x6278 0x4>, + <0x627c 0x6>, + <0x62f0 0x8>, + <0x62f4 0xe>, + <0x62f8 0x14>, + <0x62fc 0x1a>, + <0x6370 0x20>, + <0x6374 0x40>, + <0x6378 0x60>, + <0x637c 0x80>, + <0x6784 0x0>, + <0x678c 0x10>, + <0x67a0 0x0>, + <0x67a4 0x0>, + <0x67a8 0x20>, + <0x67b0 0x0>, + <0x67b4 0x8>, + <0x67b8 0xc8>, + <0x67d0 0x4>, + <0x67dc 0x8>, + <0x67e0 0x8>, + <0x6800 0x6>, + <0x6900 0x3ff>, + <0x6924 0x202>, + <0x6928 0x10a00>, + <0x6930 0x500>, + <0x6960 0xffffffff>, + <0x6b64 0x121151>, + <0x6b68 0xea800080>, + <0x6c00 0x0>, + <0x6c04 0x0>, + <0x6c08 0x0>, + <0x6c0c 0x0>, + <0x6c10 0x1>, + <0x6c14 0x1>, + <0x6c18 0x1>, + <0x6c1c 0x1>, + <0x6c20 0x2>, + <0x6c24 0x2>, + <0x6c28 0x2>, + <0x6c2c 0x2>, + <0x6c30 0x3>, + <0x6c34 0x3>, + <0x6c38 0x3>, + <0x6c3c 0x3>; +}; + +&turing_q6_smmu { + attach-impl-defs = <0x6000 0x2378>, + <0x6060 0x1055>, + <0x6070 0xe0>, + <0x6074 0xe0>, + <0x6078 0xe0>, + <0x607c 0xe0>, + <0x60f0 0xc0>, + <0x60f4 0xc8>, + <0x60f8 0xd0>, + <0x60fc 0xd8>, + <0x6170 0x0>, + <0x6174 0x30>, + <0x6178 0x60>, + <0x617c 0x90>, + <0x6270 0x0>, + <0x6274 0x2>, + <0x6278 0x4>, + <0x627c 0x6>, + <0x62f0 0x8>, + <0x62f4 0xe>, + <0x62f8 0x14>, + <0x62fc 0x1a>, + <0x6370 0x20>, + <0x6374 0x40>, + <0x6378 0x60>, + <0x637c 0x80>, + <0x6784 0x0>, + <0x678c 0x10>, + <0x67a0 0x0>, + <0x67a4 0x0>, + <0x67a8 0x20>, + <0x67b0 0x0>, + <0x67b4 0x8>, + <0x67b8 0xc8>, + <0x67d0 0x4>, + <0x67dc 0x8>, + <0x67e0 0x8>, + <0x6800 0x6>, + <0x6900 0x3ff>, + <0x6924 0x202>, + <0x6928 0x10a00>, + <0x6930 0x500>, + <0x6960 0xffffffff>, + <0x6b64 0x121151>, + <0x6b68 0xea800080>, + <0x6c00 0x0>, + <0x6c04 0x0>, + <0x6c08 0x0>, + <0x6c0c 0x0>, + <0x6c10 0x1>, + <0x6c14 0x1>, + <0x6c18 0x1>, + <0x6c1c 0x1>, + <0x6c20 0x2>, + <0x6c24 0x2>, + <0x6c28 0x2>, + <0x6c2c 0x2>, + <0x6c30 0x3>, + <0x6c34 0x3>, + <0x6c38 0x3>, + <0x6c3c 0x3>; +}; + +&mmss_bimc_smmu { + attach-impl-defs = <0x6000 0x2378>, + <0x6060 0x1055>, + <0x678c 0x28>, + <0x6794 0xe0>, + <0x6800 0x6>, + <0x6900 0x3ff>, + <0x6924 0x204>, + <0x6928 0x11002>, + <0x6930 0x800>, + <0x6960 0xffffffff>, + <0x6964 0xffffffff>, + <0x6968 0xffffffff>, + <0x696c 0xffffffff>, + <0x6b48 0x330330>, + <0x6b4c 0x81>, + <0x6b50 0x3333>, + <0x6b54 0x3333>, + <0x6b64 0x1a5555>, + <0x6b68 0xbaaa892a>, + <0x6b70 0x10100202>, + <0x6b74 0x10100202>, + <0x6b78 0x10100000>, + <0x6b80 0x20042004>, + <0x6b84 0x20042004>; +}; + +&anoc2_smmu { + attach-impl-defs = <0x6000 0x2378>, + <0x6060 0x1055>, + <0x6070 0xf>, + <0x6074 0x23>, + <0x6078 0x37>, + <0x607c 0x39>, + <0x6080 0x3f>, + <0x6084 0x6f>, + <0x6088 0x74>, + <0x608c 0x92>, + <0x6090 0xb0>, + <0x6094 0xf0>, + <0x6098 0xf0>, + <0x609c 0xf0>, + <0x60f0 0x0>, + <0x60f4 0x1>, + <0x60f8 0x3>, + <0x60fc 0x4>, + <0x6100 0x6>, + <0x6104 0x8>, + <0x6108 0x9>, + <0x610c 0xb>, + <0x6110 0xd>, + <0x6114 0xf>, + <0x6118 0xf>, + <0x611c 0xf>, + <0x6170 0x0>, + <0x6174 0x0>, + <0x6178 0x0>, + <0x617c 0x0>, + <0x6180 0x0>, + <0x6184 0x0>, + <0x6188 0x0>, + <0x618c 0x0>, + <0x6190 0x0>, + <0x6194 0x0>, + <0x6198 0x0>, + <0x619c 0x0>, + <0x6270 0x0>, + <0x6274 0x1>, + <0x6278 0x2>, + <0x627c 0x4>, + <0x6280 0x4>, + <0x6284 0x6>, + <0x6288 0x6>, + <0x628c 0xa>, + <0x6290 0xc>, + <0x6294 0xc>, + <0x6298 0xc>, + <0x629c 0xc>, + <0x62f0 0xc>, + <0x62f4 0x12>, + <0x62f8 0x18>, + <0x62fc 0x1a>, + <0x6300 0x1d>, + <0x6304 0x23>, + <0x6308 0x24>, + <0x630c 0x28>, + <0x6310 0x2c>, + <0x6314 0x30>, + <0x6318 0x30>, + <0x631c 0x30>, + <0x6370 0x30>, + <0x6374 0x35>, + <0x6378 0x3a>, + <0x637c 0x3e>, + <0x6380 0x46>, + <0x6384 0x50>, + <0x6388 0x55>, + <0x638c 0x5d>, + <0x6390 0x67>, + <0x6394 0x80>, + <0x6398 0x80>, + <0x639c 0x80>, + <0x678c 0x12>, + <0x6794 0x32>, + <0x67a0 0x0>, + <0x67a4 0xe1>, + <0x67a8 0xf0>, + <0x67b0 0x0>, + <0x67b4 0xc>, + <0x67b8 0x9c>, + <0x67d0 0x0>, + <0x67dc 0x4>, + <0x67e0 0x8>, + <0x6800 0x6>, + <0x6900 0x3ff>, + <0x6b48 0x330330>, + <0x6b4c 0x81>, + <0x6b50 0x1313>, + <0x6b64 0x121155>, + <0x6b68 0xcaa84920>, + <0x6b70 0xc0c0000>, + <0x6b74 0x8080000>, + <0x6b78 0x8080000>, + <0x6b80 0x20002000>, + <0x6b84 0x20002000>, + <0x6c00 0x5>, + <0x6c04 0x0>, + <0x6c08 0x5>, + <0x6c0c 0x0>, + <0x6c10 0x5>, + <0x6c14 0x0>, + <0x6c18 0x5>, + <0x6c1c 0x0>, + <0x6c20 0x5>, + <0x6c24 0x0>, + <0x6c28 0x0>, + <0x6c2c 0x0>, + <0x6c30 0x0>, + <0x6c34 0x0>, + <0x6c38 0x0>, + <0x6c3c 0x0>, + <0x6c40 0x0>, + <0x6c44 0x0>, + <0x6c48 0x0>, + <0x6c4c 0x0>, + <0x6c50 0x0>, + <0x6c54 0x0>, + <0x6c58 0x0>, + <0x6c5c 0x0>, + <0x6c60 0x0>, + <0x6c64 0x0>, + <0x6c68 0x0>, + <0x6c6c 0x0>, + <0x6c70 0x0>, + <0x6c74 0x0>, + <0x6c78 0x0>, + <0x6c7c 0x0>, + <0x6c80 0x0>, + <0x6c84 0x0>, + <0x6c88 0x0>, + <0x6c8c 0x0>, + <0x6c90 0x0>, + <0x6c94 0x0>, + <0x6c98 0x0>, + <0x6c9c 0x0>, + <0x6ca0 0x0>, + <0x6ca4 0x0>, + <0x6ca8 0x0>, + <0x6cac 0x0>, + <0x6cb0 0x0>, + <0x6cb4 0x0>, + <0x6cb8 0x0>, + <0x6cbc 0x0>, + <0x6cc0 0x0>, + <0x6cc4 0x0>, + <0x6cc8 0x0>, + <0x6ccc 0x0>, + <0x6cd0 0x0>, + <0x6cd4 0x0>, + <0x6cd8 0x0>, + <0x6cdc 0x0>, + <0x6ce0 0x0>, + <0x6ce4 0x0>, + <0x6ce8 0x0>, + <0x6cec 0x0>, + <0x6cf0 0x0>, + <0x6cf4 0x0>, + <0x6cf8 0x0>, + <0x6cfc 0x0>, + <0x6d00 0x3>, + <0x6d04 0x4>, + <0x6d08 0x4>, + <0x6d0c 0x0>, + <0x6d10 0x8>, + <0x6d14 0x8>, + <0x6d18 0x3>, + <0x6d1c 0x2>, + <0x6d20 0x4>, + <0x6d24 0x0>, + <0x6d28 0x4>, + <0x6d2c 0x0>, + <0x6d30 0x7>, + <0x6d34 0x0>, + <0x6d38 0x6>, + <0x6d3c 0x0>, + <0x6d40 0x0>, + <0x6d44 0x1>, + <0x6d48 0x4>, + <0x6d4c 0x0>, + <0x6d50 0x4>, + <0x6d54 0x0>, + <0x6d58 0x4>, + <0x6d5c 0x0>, + <0x6d60 0x0>, + <0x6d64 0x0>, + <0x6d68 0x0>, + <0x6d6c 0x0>, + <0x6d70 0x0>, + <0x6d74 0x0>, + <0x6d78 0x0>, + <0x6d7c 0x0>, + <0x6d80 0x0>, + <0x6d84 0x0>, + <0x6d88 0x0>, + <0x6d8c 0x0>, + <0x6d90 0x0>, + <0x6d94 0x0>, + <0x6d98 0x0>, + <0x6d9c 0x0>, + <0x6da0 0x0>, + <0x6da4 0x0>, + <0x6da8 0x0>, + <0x6dac 0x0>, + <0x6db0 0x0>, + <0x6db4 0x0>, + <0x6db8 0x0>, + <0x6dbc 0x0>, + <0x6dc0 0x0>, + <0x6dc4 0x0>, + <0x6dc8 0x0>, + <0x6dcc 0x0>, + <0x6dd0 0x0>, + <0x6dd4 0x0>, + <0x6dd8 0x0>, + <0x6ddc 0x0>, + <0x6de0 0x0>, + <0x6de4 0x0>, + <0x6de8 0x0>, + <0x6dec 0x0>, + <0x6df0 0x0>, + <0x6df4 0x0>, + <0x6df8 0x0>, + <0x6dfc 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-impl-defs-falcon.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-impl-defs-falcon.dtsi deleted file mode 100644 index f060f2d7008c..000000000000 --- a/arch/arm/boot/dts/qcom/msm-arm-smmu-impl-defs-falcon.dtsi +++ /dev/null @@ -1,409 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -&kgsl_smmu { - attach-impl-defs = <0x6000 0x2378>, - <0x6060 0x1055>, - <0x678c 0x8>, - <0x6794 0x28>, - <0x6800 0x6>, - <0x6900 0x3ff>, - <0x6924 0x204>, - <0x6928 0x11000>, - <0x6930 0x800>, - <0x6960 0xffffffff>, - <0x6b64 0x1a5551>, - <0x6b68 0x9a82a382>; -}; - -&lpass_q6_smmu { - attach-impl-defs = <0x6000 0x2378>, - <0x6060 0x1055>, - <0x6070 0xe0>, - <0x6074 0xe0>, - <0x6078 0xe0>, - <0x607c 0xe0>, - <0x60f0 0xc0>, - <0x60f4 0xc8>, - <0x60f8 0xd0>, - <0x60fc 0xd8>, - <0x6170 0x0>, - <0x6174 0x30>, - <0x6178 0x60>, - <0x617c 0x90>, - <0x6270 0x0>, - <0x6274 0x2>, - <0x6278 0x4>, - <0x627c 0x6>, - <0x62f0 0x8>, - <0x62f4 0xe>, - <0x62f8 0x14>, - <0x62fc 0x1a>, - <0x6370 0x20>, - <0x6374 0x40>, - <0x6378 0x60>, - <0x637c 0x80>, - <0x6784 0x0>, - <0x678c 0x10>, - <0x67a0 0x0>, - <0x67a4 0x0>, - <0x67a8 0x20>, - <0x67b0 0x0>, - <0x67b4 0x8>, - <0x67b8 0xc8>, - <0x67d0 0x4>, - <0x67dc 0x8>, - <0x67e0 0x8>, - <0x6800 0x6>, - <0x6900 0x3ff>, - <0x6924 0x202>, - <0x6928 0x10a00>, - <0x6930 0x500>, - <0x6960 0xffffffff>, - <0x6b64 0x121151>, - <0x6b68 0xea800080>, - <0x6c00 0x0>, - <0x6c04 0x0>, - <0x6c08 0x0>, - <0x6c0c 0x0>, - <0x6c10 0x1>, - <0x6c14 0x1>, - <0x6c18 0x1>, - <0x6c1c 0x1>, - <0x6c20 0x2>, - <0x6c24 0x2>, - <0x6c28 0x2>, - <0x6c2c 0x2>, - <0x6c30 0x3>, - <0x6c34 0x3>, - <0x6c38 0x3>, - <0x6c3c 0x3>; -}; - -&turing_q6_smmu { - attach-impl-defs = <0x6000 0x2378>, - <0x6060 0x1055>, - <0x6070 0xe0>, - <0x6074 0xe0>, - <0x6078 0xe0>, - <0x607c 0xe0>, - <0x60f0 0xc0>, - <0x60f4 0xc8>, - <0x60f8 0xd0>, - <0x60fc 0xd8>, - <0x6170 0x0>, - <0x6174 0x30>, - <0x6178 0x60>, - <0x617c 0x90>, - <0x6270 0x0>, - <0x6274 0x2>, - <0x6278 0x4>, - <0x627c 0x6>, - <0x62f0 0x8>, - <0x62f4 0xe>, - <0x62f8 0x14>, - <0x62fc 0x1a>, - <0x6370 0x20>, - <0x6374 0x40>, - <0x6378 0x60>, - <0x637c 0x80>, - <0x6784 0x0>, - <0x678c 0x10>, - <0x67a0 0x0>, - <0x67a4 0x0>, - <0x67a8 0x20>, - <0x67b0 0x0>, - <0x67b4 0x8>, - <0x67b8 0xc8>, - <0x67d0 0x4>, - <0x67dc 0x8>, - <0x67e0 0x8>, - <0x6800 0x6>, - <0x6900 0x3ff>, - <0x6924 0x202>, - <0x6928 0x10a00>, - <0x6930 0x500>, - <0x6960 0xffffffff>, - <0x6b64 0x121151>, - <0x6b68 0xea800080>, - <0x6c00 0x0>, - <0x6c04 0x0>, - <0x6c08 0x0>, - <0x6c0c 0x0>, - <0x6c10 0x1>, - <0x6c14 0x1>, - <0x6c18 0x1>, - <0x6c1c 0x1>, - <0x6c20 0x2>, - <0x6c24 0x2>, - <0x6c28 0x2>, - <0x6c2c 0x2>, - <0x6c30 0x3>, - <0x6c34 0x3>, - <0x6c38 0x3>, - <0x6c3c 0x3>; -}; - -&mmss_bimc_smmu { - attach-impl-defs = <0x6000 0x2378>, - <0x6060 0x1055>, - <0x678c 0x28>, - <0x6794 0xe0>, - <0x6800 0x6>, - <0x6900 0x3ff>, - <0x6924 0x204>, - <0x6928 0x11002>, - <0x6930 0x800>, - <0x6960 0xffffffff>, - <0x6964 0xffffffff>, - <0x6968 0xffffffff>, - <0x696c 0xffffffff>, - <0x6b48 0x330330>, - <0x6b4c 0x81>, - <0x6b50 0x3333>, - <0x6b54 0x3333>, - <0x6b64 0x1a5555>, - <0x6b68 0xbaaa892a>, - <0x6b70 0x10100202>, - <0x6b74 0x10100202>, - <0x6b78 0x10100000>, - <0x6b80 0x20042004>, - <0x6b84 0x20042004>; -}; - -&anoc2_smmu { - attach-impl-defs = <0x6000 0x2378>, - <0x6060 0x1055>, - <0x6070 0xf>, - <0x6074 0x23>, - <0x6078 0x37>, - <0x607c 0x39>, - <0x6080 0x3f>, - <0x6084 0x6f>, - <0x6088 0x74>, - <0x608c 0x92>, - <0x6090 0xb0>, - <0x6094 0xf0>, - <0x6098 0xf0>, - <0x609c 0xf0>, - <0x60f0 0x0>, - <0x60f4 0x1>, - <0x60f8 0x3>, - <0x60fc 0x4>, - <0x6100 0x6>, - <0x6104 0x8>, - <0x6108 0x9>, - <0x610c 0xb>, - <0x6110 0xd>, - <0x6114 0xf>, - <0x6118 0xf>, - <0x611c 0xf>, - <0x6170 0x0>, - <0x6174 0x0>, - <0x6178 0x0>, - <0x617c 0x0>, - <0x6180 0x0>, - <0x6184 0x0>, - <0x6188 0x0>, - <0x618c 0x0>, - <0x6190 0x0>, - <0x6194 0x0>, - <0x6198 0x0>, - <0x619c 0x0>, - <0x6270 0x0>, - <0x6274 0x1>, - <0x6278 0x2>, - <0x627c 0x4>, - <0x6280 0x4>, - <0x6284 0x6>, - <0x6288 0x6>, - <0x628c 0xa>, - <0x6290 0xc>, - <0x6294 0xc>, - <0x6298 0xc>, - <0x629c 0xc>, - <0x62f0 0xc>, - <0x62f4 0x12>, - <0x62f8 0x18>, - <0x62fc 0x1a>, - <0x6300 0x1d>, - <0x6304 0x23>, - <0x6308 0x24>, - <0x630c 0x28>, - <0x6310 0x2c>, - <0x6314 0x30>, - <0x6318 0x30>, - <0x631c 0x30>, - <0x6370 0x30>, - <0x6374 0x35>, - <0x6378 0x3a>, - <0x637c 0x3e>, - <0x6380 0x46>, - <0x6384 0x50>, - <0x6388 0x55>, - <0x638c 0x5d>, - <0x6390 0x67>, - <0x6394 0x80>, - <0x6398 0x80>, - <0x639c 0x80>, - <0x678c 0x12>, - <0x6794 0x32>, - <0x67a0 0x0>, - <0x67a4 0xe1>, - <0x67a8 0xf0>, - <0x67b0 0x0>, - <0x67b4 0xc>, - <0x67b8 0x9c>, - <0x67d0 0x0>, - <0x67dc 0x4>, - <0x67e0 0x8>, - <0x6800 0x6>, - <0x6900 0x3ff>, - <0x6b48 0x330330>, - <0x6b4c 0x81>, - <0x6b50 0x1313>, - <0x6b64 0x121155>, - <0x6b68 0xcaa84920>, - <0x6b70 0xc0c0000>, - <0x6b74 0x8080000>, - <0x6b78 0x8080000>, - <0x6b80 0x20002000>, - <0x6b84 0x20002000>, - <0x6c00 0x5>, - <0x6c04 0x0>, - <0x6c08 0x5>, - <0x6c0c 0x0>, - <0x6c10 0x5>, - <0x6c14 0x0>, - <0x6c18 0x5>, - <0x6c1c 0x0>, - <0x6c20 0x5>, - <0x6c24 0x0>, - <0x6c28 0x0>, - <0x6c2c 0x0>, - <0x6c30 0x0>, - <0x6c34 0x0>, - <0x6c38 0x0>, - <0x6c3c 0x0>, - <0x6c40 0x0>, - <0x6c44 0x0>, - <0x6c48 0x0>, - <0x6c4c 0x0>, - <0x6c50 0x0>, - <0x6c54 0x0>, - <0x6c58 0x0>, - <0x6c5c 0x0>, - <0x6c60 0x0>, - <0x6c64 0x0>, - <0x6c68 0x0>, - <0x6c6c 0x0>, - <0x6c70 0x0>, - <0x6c74 0x0>, - <0x6c78 0x0>, - <0x6c7c 0x0>, - <0x6c80 0x0>, - <0x6c84 0x0>, - <0x6c88 0x0>, - <0x6c8c 0x0>, - <0x6c90 0x0>, - <0x6c94 0x0>, - <0x6c98 0x0>, - <0x6c9c 0x0>, - <0x6ca0 0x0>, - <0x6ca4 0x0>, - <0x6ca8 0x0>, - <0x6cac 0x0>, - <0x6cb0 0x0>, - <0x6cb4 0x0>, - <0x6cb8 0x0>, - <0x6cbc 0x0>, - <0x6cc0 0x0>, - <0x6cc4 0x0>, - <0x6cc8 0x0>, - <0x6ccc 0x0>, - <0x6cd0 0x0>, - <0x6cd4 0x0>, - <0x6cd8 0x0>, - <0x6cdc 0x0>, - <0x6ce0 0x0>, - <0x6ce4 0x0>, - <0x6ce8 0x0>, - <0x6cec 0x0>, - <0x6cf0 0x0>, - <0x6cf4 0x0>, - <0x6cf8 0x0>, - <0x6cfc 0x0>, - <0x6d00 0x3>, - <0x6d04 0x4>, - <0x6d08 0x4>, - <0x6d0c 0x0>, - <0x6d10 0x8>, - <0x6d14 0x8>, - <0x6d18 0x3>, - <0x6d1c 0x2>, - <0x6d20 0x4>, - <0x6d24 0x0>, - <0x6d28 0x4>, - <0x6d2c 0x0>, - <0x6d30 0x7>, - <0x6d34 0x0>, - <0x6d38 0x6>, - <0x6d3c 0x0>, - <0x6d40 0x0>, - <0x6d44 0x1>, - <0x6d48 0x4>, - <0x6d4c 0x0>, - <0x6d50 0x4>, - <0x6d54 0x0>, - <0x6d58 0x4>, - <0x6d5c 0x0>, - <0x6d60 0x0>, - <0x6d64 0x0>, - <0x6d68 0x0>, - <0x6d6c 0x0>, - <0x6d70 0x0>, - <0x6d74 0x0>, - <0x6d78 0x0>, - <0x6d7c 0x0>, - <0x6d80 0x0>, - <0x6d84 0x0>, - <0x6d88 0x0>, - <0x6d8c 0x0>, - <0x6d90 0x0>, - <0x6d94 0x0>, - <0x6d98 0x0>, - <0x6d9c 0x0>, - <0x6da0 0x0>, - <0x6da4 0x0>, - <0x6da8 0x0>, - <0x6dac 0x0>, - <0x6db0 0x0>, - <0x6db4 0x0>, - <0x6db8 0x0>, - <0x6dbc 0x0>, - <0x6dc0 0x0>, - <0x6dc4 0x0>, - <0x6dc8 0x0>, - <0x6dcc 0x0>, - <0x6dd0 0x0>, - <0x6dd4 0x0>, - <0x6dd8 0x0>, - <0x6ddc 0x0>, - <0x6de0 0x0>, - <0x6de4 0x0>, - <0x6de8 0x0>, - <0x6dec 0x0>, - <0x6df0 0x0>, - <0x6df4 0x0>, - <0x6df8 0x0>, - <0x6dfc 0x0>; -}; diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-triton.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-triton.dtsi index f4bf275dcc3c..4ab200d6b89d 100644 --- a/arch/arm/boot/dts/qcom/msm-arm-smmu-triton.dtsi +++ b/arch/arm/boot/dts/qcom/msm-arm-smmu-triton.dtsi @@ -10,8 +10,8 @@ * GNU General Public License for more details. */ -#include "msm-arm-smmu-falcon.dtsi" -#include "msm-arm-smmu-impl-defs-falcon.dtsi" +#include "msm-arm-smmu-660.dtsi" +#include "msm-arm-smmu-impl-defs-660.dtsi" &soc { /delete-node/ arm,smmu-turing_q6@5180000; diff --git a/arch/arm/boot/dts/qcom/msm-audio.dtsi b/arch/arm/boot/dts/qcom/msm-audio.dtsi index 7a96e19c62c5..d86e77e2c7ee 100644 --- a/arch/arm/boot/dts/qcom/msm-audio.dtsi +++ b/arch/arm/boot/dts/qcom/msm-audio.dtsi @@ -571,8 +571,8 @@ }; tasha_snd: sound-9335 { - compatible = "qcom,msmfalcon-asoc-snd-tasha"; - qcom,model = "msmfalcon-tasha-snd-card"; + compatible = "qcom,sdm660-asoc-snd-tasha"; + qcom,model = "sdm660-tasha-snd-card"; qcom,wcn-btfm; qcom,mi2s-audio-intf; qcom,auxpcm-audio-intf; @@ -683,8 +683,8 @@ }; tavil_snd: sound-tavil { - compatible = "qcom,msmfalcon-asoc-snd-tavil"; - qcom,model = "msmfalcon-tavil-snd-card"; + compatible = "qcom,sdm660-asoc-snd-tavil"; + qcom,model = "sdm660-tavil-snd-card"; qcom,wcn-btfm; qcom,mi2s-audio-intf; qcom,auxpcm-audio-intf; @@ -792,8 +792,8 @@ int_codec: sound { status = "disabled"; - compatible = "qcom,msmfalcon-asoc-snd"; - qcom,model = "msmfalcon-snd-card"; + compatible = "qcom,sdm660-asoc-snd"; + qcom,model = "sdm660-snd-card"; qcom,wcn-btfm; qcom,mi2s-audio-intf; qcom,auxpcm-audio-intf; @@ -913,7 +913,7 @@ clock_audio: audio_ext_clk { compatible = "qcom,audio-ref-clk"; - qcom,audio-ref-clk-gpio = <&pmfalcon_gpios 3 0>; + qcom,audio-ref-clk-gpio = <&pm660_gpios 3 0>; clock-names = "osr_clk"; clocks = <&clock_rpmcc AUDIO_PMI_CLK>; qcom,node_has_rpm_clock; diff --git a/arch/arm/boot/dts/qcom/msm-gdsc-660.dtsi b/arch/arm/boot/dts/qcom/msm-gdsc-660.dtsi new file mode 100644 index 000000000000..6550ddcad86c --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-gdsc-660.dtsi @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + /* GCC GDSCs */ + gdsc_usb30: qcom,gdsc@10f004 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_usb30"; + reg = <0x10f004 0x4>; + status = "disabled"; + }; + + gdsc_ufs: qcom,gdsc@175004 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_ufs"; + reg = <0x175004 0x4>; + status = "disabled"; + }; + + gdsc_hlos1_vote_lpass_adsp: qcom,gdsc@17d034 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_hlos1_vote_lpass_adsp"; + reg = <0x17d034 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + gdsc_hlos1_vote_turing_adsp: qcom,gdsc@17d04c { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_hlos1_vote_turing_adsp"; + reg = <0x17d04c 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + gdsc_hlos2_vote_turing_adsp: qcom,gdsc@17e04c { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_hlos2_vote_turing_adsp"; + reg = <0x17e04c 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + /* MMSS GDSCs */ + bimc_smmu_hw_ctrl: syscon@c8ce024 { + compatible = "syscon"; + reg = <0xc8ce024 0x4>; + }; + + gdsc_bimc_smmu: qcom,gdsc@c8ce020 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_bimc_smmu"; + reg = <0xc8ce020 0x4>; + hw-ctrl-addr = <&bimc_smmu_hw_ctrl>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + gdsc_venus: qcom,gdsc@c8c1024 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_venus"; + reg = <0xc8c1024 0x4>; + status = "disabled"; + }; + + gdsc_venus_core0: qcom,gdsc@c8c1040 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_venus_core0"; + reg = <0xc8c1040 0x4>; + status = "disabled"; + }; + + gdsc_camss_top: qcom,gdsc@c8c34a0 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_camss_top"; + reg = <0xc8c34a0 0x4>; + status = "disabled"; + }; + + gdsc_vfe0: qcom,gdsc@c8c3664 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_vfe0"; + reg = <0xc8c3664 0x4>; + status = "disabled"; + }; + + gdsc_vfe1: qcom,gdsc@c8c3674 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_vfe1"; + reg = <0xc8c3674 0x4>; + status = "disabled"; + }; + + gdsc_cpp: qcom,gdsc@c8c36d4 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_cpp"; + reg = <0xc8c36d4 0x4>; + status = "disabled"; + }; + + gdsc_mdss: qcom,gdsc@c8c2304 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_mdss"; + reg = <0xc8c2304 0x4>; + status = "disabled"; + }; + + /* GPU GDSCs */ + gpu_cx_hw_ctrl: syscon@5066008 { + compatible = "syscon"; + reg = <0x5066008 0x4>; + }; + + gdsc_gpu_cx: qcom,gdsc@5066004 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_gpu_cx"; + reg = <0x5066004 0x4>; + hw-ctrl-addr = <&gpu_cx_hw_ctrl>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <2000>; + status = "disabled"; + }; + + /* GPU GX GDSCs */ + gpu_gx_domain_addr: syscon@5065130 { + compatible = "syscon"; + reg = <0x5065130 0x4>; + }; + + gpu_gx_sw_reset: syscon@5066090 { + compatible = "syscon"; + reg = <0x5066090 0x4>; + }; + + gdsc_gpu_gx: qcom,gdsc@5066094 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_gpu_gx"; + reg = <0x5066094 0x4>; + domain-addr = <&gpu_gx_domain_addr>; + sw-reset = <&gpu_gx_sw_reset>; + qcom,retain-periph; + qcom,reset-aon-logic; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm-gdsc-falcon.dtsi b/arch/arm/boot/dts/qcom/msm-gdsc-falcon.dtsi deleted file mode 100644 index 6550ddcad86c..000000000000 --- a/arch/arm/boot/dts/qcom/msm-gdsc-falcon.dtsi +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -&soc { - /* GCC GDSCs */ - gdsc_usb30: qcom,gdsc@10f004 { - compatible = "qcom,gdsc"; - regulator-name = "gdsc_usb30"; - reg = <0x10f004 0x4>; - status = "disabled"; - }; - - gdsc_ufs: qcom,gdsc@175004 { - compatible = "qcom,gdsc"; - regulator-name = "gdsc_ufs"; - reg = <0x175004 0x4>; - status = "disabled"; - }; - - gdsc_hlos1_vote_lpass_adsp: qcom,gdsc@17d034 { - compatible = "qcom,gdsc"; - regulator-name = "gdsc_hlos1_vote_lpass_adsp"; - reg = <0x17d034 0x4>; - qcom,no-status-check-on-disable; - qcom,gds-timeout = <500>; - status = "disabled"; - }; - - gdsc_hlos1_vote_turing_adsp: qcom,gdsc@17d04c { - compatible = "qcom,gdsc"; - regulator-name = "gdsc_hlos1_vote_turing_adsp"; - reg = <0x17d04c 0x4>; - qcom,no-status-check-on-disable; - qcom,gds-timeout = <500>; - status = "disabled"; - }; - - gdsc_hlos2_vote_turing_adsp: qcom,gdsc@17e04c { - compatible = "qcom,gdsc"; - regulator-name = "gdsc_hlos2_vote_turing_adsp"; - reg = <0x17e04c 0x4>; - qcom,no-status-check-on-disable; - qcom,gds-timeout = <500>; - status = "disabled"; - }; - - /* MMSS GDSCs */ - bimc_smmu_hw_ctrl: syscon@c8ce024 { - compatible = "syscon"; - reg = <0xc8ce024 0x4>; - }; - - gdsc_bimc_smmu: qcom,gdsc@c8ce020 { - compatible = "qcom,gdsc"; - regulator-name = "gdsc_bimc_smmu"; - reg = <0xc8ce020 0x4>; - hw-ctrl-addr = <&bimc_smmu_hw_ctrl>; - qcom,no-status-check-on-disable; - qcom,gds-timeout = <500>; - status = "disabled"; - }; - - gdsc_venus: qcom,gdsc@c8c1024 { - compatible = "qcom,gdsc"; - regulator-name = "gdsc_venus"; - reg = <0xc8c1024 0x4>; - status = "disabled"; - }; - - gdsc_venus_core0: qcom,gdsc@c8c1040 { - compatible = "qcom,gdsc"; - regulator-name = "gdsc_venus_core0"; - reg = <0xc8c1040 0x4>; - status = "disabled"; - }; - - gdsc_camss_top: qcom,gdsc@c8c34a0 { - compatible = "qcom,gdsc"; - regulator-name = "gdsc_camss_top"; - reg = <0xc8c34a0 0x4>; - status = "disabled"; - }; - - gdsc_vfe0: qcom,gdsc@c8c3664 { - compatible = "qcom,gdsc"; - regulator-name = "gdsc_vfe0"; - reg = <0xc8c3664 0x4>; - status = "disabled"; - }; - - gdsc_vfe1: qcom,gdsc@c8c3674 { - compatible = "qcom,gdsc"; - regulator-name = "gdsc_vfe1"; - reg = <0xc8c3674 0x4>; - status = "disabled"; - }; - - gdsc_cpp: qcom,gdsc@c8c36d4 { - compatible = "qcom,gdsc"; - regulator-name = "gdsc_cpp"; - reg = <0xc8c36d4 0x4>; - status = "disabled"; - }; - - gdsc_mdss: qcom,gdsc@c8c2304 { - compatible = "qcom,gdsc"; - regulator-name = "gdsc_mdss"; - reg = <0xc8c2304 0x4>; - status = "disabled"; - }; - - /* GPU GDSCs */ - gpu_cx_hw_ctrl: syscon@5066008 { - compatible = "syscon"; - reg = <0x5066008 0x4>; - }; - - gdsc_gpu_cx: qcom,gdsc@5066004 { - compatible = "qcom,gdsc"; - regulator-name = "gdsc_gpu_cx"; - reg = <0x5066004 0x4>; - hw-ctrl-addr = <&gpu_cx_hw_ctrl>; - qcom,no-status-check-on-disable; - qcom,gds-timeout = <2000>; - status = "disabled"; - }; - - /* GPU GX GDSCs */ - gpu_gx_domain_addr: syscon@5065130 { - compatible = "syscon"; - reg = <0x5065130 0x4>; - }; - - gpu_gx_sw_reset: syscon@5066090 { - compatible = "syscon"; - reg = <0x5066090 0x4>; - }; - - gdsc_gpu_gx: qcom,gdsc@5066094 { - compatible = "qcom,gdsc"; - regulator-name = "gdsc_gpu_gx"; - reg = <0x5066094 0x4>; - domain-addr = <&gpu_gx_domain_addr>; - sw-reset = <&gpu_gx_sw_reset>; - qcom,retain-periph; - qcom,reset-aon-logic; - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msm-pm2falcon-rpm-regulator.dtsi b/arch/arm/boot/dts/qcom/msm-pm2falcon-rpm-regulator.dtsi deleted file mode 100644 index bc0793fec990..000000000000 --- a/arch/arm/boot/dts/qcom/msm-pm2falcon-rpm-regulator.dtsi +++ /dev/null @@ -1,238 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -&rpm_bus { - rpm-regulator-smpb1 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "smpb"; - qcom,resource-id = <1>; - qcom,regulator-type = <1>; - status = "disabled"; - - regulator-s1 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s1"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-smpb2 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "smpb"; - qcom,resource-id = <2>; - qcom,regulator-type = <1>; - status = "disabled"; - - regulator-s2 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s2"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-smpb3 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "smpb"; - qcom,resource-id = <3>; - qcom,regulator-type = <1>; - status = "disabled"; - - regulator-s3 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s3"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-smpb5 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "smpb"; - qcom,resource-id = <5>; - qcom,regulator-type = <1>; - status = "disabled"; - - regulator-s5 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s5"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldob1 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldob"; - qcom,resource-id = <1>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l1 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l1"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldob2 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldob"; - qcom,resource-id = <2>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l2 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l2"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldob3 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldob"; - qcom,resource-id = <3>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l3 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l3"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldob4 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldob"; - qcom,resource-id = <4>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l4 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l4"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldob5 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldob"; - qcom,resource-id = <5>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l5 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l5"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldob6 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldob"; - qcom,resource-id = <6>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l6 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l6"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldob7 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldob"; - qcom,resource-id = <7>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l7 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l7"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldob8 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldob"; - qcom,resource-id = <8>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l8 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l8"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldob9 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "rwsc"; - qcom,resource-id = <0>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l9 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l9"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldob10 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "rwsm"; - qcom,resource-id = <0>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l10 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l10"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-bobb { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "bobb"; - qcom,resource-id = <1>; - qcom,regulator-type = <4>; - status = "disabled"; - - regulator-bob { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_bob"; - qcom,set = <3>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msm-pm2falcon.dtsi b/arch/arm/boot/dts/qcom/msm-pm2falcon.dtsi deleted file mode 100644 index d3a920fff82e..000000000000 --- a/arch/arm/boot/dts/qcom/msm-pm2falcon.dtsi +++ /dev/null @@ -1,395 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -&spmi_bus { - qcom,pm2falcon@2 { - compatible = "qcom,spmi-pmic"; - reg = <0x2 SPMI_USID>; - #address-cells = <2>; - #size-cells = <0>; - - pm2falcon_revid: qcom,revid@100 { - compatible = "qcom,qpnp-revid"; - reg = <0x100 0x100>; - }; - - qcom,power-on@800 { - compatible = "qcom,qpnp-power-on"; - reg = <0x800 0x100>; - qcom,secondary-pon-reset; - qcom,hard-reset-poweroff-type = - ; - }; - - qcom,temp-alarm@2400 { - compatible = "qcom,qpnp-temp-alarm"; - reg = <0x2400 0x100>; - interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; - label = "pm2falcon_tz"; - }; - - pm2falcon_gpios: gpios { - compatible = "qcom,qpnp-pin"; - gpio-controller; - #gpio-cells = <2>; - #address-cells = <1>; - #size-cells = <1>; - label = "pm2falcon-gpio"; - - gpio@c000 { - reg = <0xc000 0x100>; - qcom,pin-num = <1>; - status = "disabled"; - }; - - gpio@c100 { - reg = <0xc100 0x100>; - qcom,pin-num = <2>; - status = "disabled"; - }; - - gpio@c200 { - reg = <0xc200 0x100>; - qcom,pin-num = <3>; - status = "disabled"; - }; - - gpio@c300 { - reg = <0xc300 0x100>; - qcom,pin-num = <4>; - status = "disabled"; - }; - - gpio@c400 { - reg = <0xc400 0x100>; - qcom,pin-num = <5>; - status = "disabled"; - }; - - gpio@c500 { - reg = <0xc500 0x100>; - qcom,pin-num = <6>; - status = "disabled"; - }; - - gpio@c600 { - reg = <0xc600 0x100>; - qcom,pin-num = <7>; - status = "disabled"; - }; - - gpio@c700 { - reg = <0xc700 0x100>; - qcom,pin-num = <8>; - status = "disabled"; - }; - - gpio@c800 { - reg = <0xc800 0x100>; - qcom,pin-num = <9>; - status = "disabled"; - }; - - gpio@c900 { - reg = <0xc900 0x100>; - qcom,pin-num = <10>; - status = "disabled"; - }; - - gpio@ca00 { - reg = <0xca00 0x100>; - qcom,pin-num = <11>; - status = "disabled"; - }; - - gpio@cb00 { - reg = <0xcb00 0x100>; - qcom,pin-num = <12>; - status = "disabled"; - }; - - }; - }; - - pm2falcon_3: qcom,pm2falcon@3 { - compatible ="qcom,spmi-pmic"; - reg = <0x3 SPMI_USID>; - #address-cells = <2>; - #size-cells = <0>; - - pm2falcon_pwm_1: pwm@b100 { - compatible = "qcom,qpnp-pwm"; - reg = <0xb100 0x100>, - <0xb042 0x7e>; - reg-names = "qpnp-lpg-channel-base", - "qpnp-lpg-lut-base"; - qcom,channel-id = <1>; - qcom,lpg-lut-size = <0x7e>; - qcom,supported-sizes = <6>, <9>; - qcom,ramp-index = <0>; - #pwm-cells = <2>; - }; - - pm2falcon_pwm_2: pwm@b200 { - compatible = "qcom,qpnp-pwm"; - reg = <0xb200 0x100>, - <0xb042 0x7e>; - reg-names = "qpnp-lpg-channel-base", - "qpnp-lpg-lut-base"; - qcom,channel-id = <2>; - qcom,lpg-lut-size = <0x7e>; - qcom,supported-sizes = <6>, <9>; - qcom,ramp-index = <1>; - #pwm-cells = <2>; - }; - - pm2falcon_pwm_3: pwm@b300 { - compatible = "qcom,qpnp-pwm"; - reg = <0xb300 0x100>, - <0xb042 0x7e>; - reg-names = "qpnp-lpg-channel-base", - "qpnp-lpg-lut-base"; - qcom,channel-id = <3>; - qcom,lpg-lut-size = <0x7e>; - qcom,supported-sizes = <6>, <9>; - qcom,ramp-index = <2>; - #pwm-cells = <2>; - }; - - pm2falcon_pwm_4: pwm@b400 { - compatible = "qcom,qpnp-pwm"; - reg = <0xb400 0x100>, - <0xb042 0x7e>; - reg-names = "qpnp-lpg-channel-base", - "qpnp-lpg-lut-base"; - qcom,channel-id = <4>; - qcom,lpg-lut-size = <0x7e>; - qcom,supported-sizes = <6>, <9>; - qcom,ramp-index = <3>; - #pwm-cells = <2>; - status = "disabled"; - }; - - qcom,leds@d000 { - compatible = "qcom,leds-qpnp"; - reg = <0xd000 0x100>; - label = "rgb"; - - red_led: qcom,rgb_0 { - label = "rgb"; - qcom,id = <3>; - qcom,mode = "pwm"; - pwms = <&pm2falcon_pwm_3 0 0>; - qcom,pwm-us = <1000>; - qcom,max-current = <12>; - qcom,default-state = "off"; - linux,name = "red"; - linux,default-trigger = - "battery-charging"; - }; - - green_led: qcom,rgb_1 { - label = "rgb"; - qcom,id = <4>; - qcom,mode = "pwm"; - pwms = <&pm2falcon_pwm_2 0 0>; - qcom,pwm-us = <1000>; - qcom,max-current = <12>; - qcom,default-state = "off"; - linux,name = "green"; - linux,default-trigger = "battery-full"; - }; - - blue_led: qcom,rgb_2 { - label = "rgb"; - qcom,id = <5>; - qcom,mode = "pwm"; - pwms = <&pm2falcon_pwm_1 0 0>; - qcom,pwm-us = <1000>; - qcom,max-current = <12>; - qcom,default-state = "off"; - linux,name = "blue"; - linux,default-trigger = "boot-indication"; - }; - }; - - pm2falcon_wled: qcom,leds@d800 { - compatible = "qcom,qpnp-wled"; - reg = <0xd800 0x100>, - <0xd900 0x100>; - reg-names = "qpnp-wled-ctrl-base", - "qpnp-wled-sink-base"; - interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_BOTH>, - <0x3 0xd8 0x2 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "ovp-irq", "sc-irq"; - linux,name = "wled"; - linux,default-trigger = "bkl-trigger"; - qcom,fdbk-output = "auto"; - qcom,vref-uv = <127500>; - qcom,switch-freq-khz = <800>; - qcom,ovp-mv = <29600>; - qcom,ilim-ma = <970>; - qcom,boost-duty-ns = <26>; - qcom,mod-freq-khz = <9600>; - qcom,dim-mode = "hybrid"; - qcom,hyb-thres = <625>; - qcom,sync-dly-us = <800>; - qcom,fs-curr-ua = <25000>; - qcom,cons-sync-write-delay-us = <1000>; - qcom,led-strings-list = [00 01 02]; - qcom,en-ext-pfet-sc-pro; - qcom,loop-auto-gm-en; - qcom,pmic-revid = <&pm2falcon_revid>; - status = "ok"; - }; - - flash_led: qcom,leds@d300 { - compatible = "qcom,qpnp-flash-led-v2"; - reg = <0xd300 0x100>; - label = "flash"; - interrupts = <0x3 0xd3 0x0 IRQ_TYPE_EDGE_RISING>, - <0x3 0xd3 0x3 IRQ_TYPE_EDGE_RISING>, - <0x3 0xd3 0x4 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "led-fault-irq", - "all-ramp-down-done-irq", - "all-ramp-up-done-irq"; - qcom,hdrm-auto-mode; - qcom,short-circuit-det; - qcom,open-circuit-det; - qcom,vph-droop-det; - qcom,thermal-derate-en; - qcom,thermal-derate-current = <200 500 1000>; - qcom,isc-delay = <192>; - qcom,pmic-revid = <&pm2falcon_revid>; - - pm2falcon_flash0: qcom,flash_0 { - label = "flash"; - qcom,led-name = "led:flash_0"; - qcom,max-current = <1500>; - qcom,default-led-trigger = "flash0_trigger"; - qcom,id = <0>; - qcom,current-ma = <1000>; - qcom,duration-ms = <1280>; - qcom,ires-ua = <12500>; - qcom,hdrm-voltage-mv = <325>; - qcom,hdrm-vol-hi-lo-win-mv = <100>; - }; - - pm2falcon_flash1: qcom,flash_1 { - label = "flash"; - qcom,led-name = "led:flash_1"; - qcom,max-current = <1500>; - qcom,default-led-trigger = "flash1_trigger"; - qcom,id = <1>; - qcom,current-ma = <1000>; - qcom,duration-ms = <1280>; - qcom,ires-ua = <12500>; - qcom,hdrm-voltage-mv = <325>; - qcom,hdrm-vol-hi-lo-win-mv = <100>; - }; - - pm2falcon_flash2: qcom,flash_2 { - label = "flash"; - qcom,led-name = "led:flash_2"; - qcom,max-current = <750>; - qcom,default-led-trigger = "flash2_trigger"; - qcom,id = <2>; - qcom,current-ma = <500>; - qcom,duration-ms = <1280>; - qcom,ires-ua = <12500>; - qcom,hdrm-voltage-mv = <325>; - qcom,hdrm-vol-hi-lo-win-mv = <100>; - pinctrl-names = "led_enable","led_disable"; - pinctrl-0 = <&led_enable>; - pinctrl-1 = <&led_disable>; - }; - - pm2falcon_torch0: qcom,torch_0 { - label = "torch"; - qcom,led-name = "led:torch_0"; - qcom,max-current = <500>; - qcom,default-led-trigger = "torch0_trigger"; - qcom,id = <0>; - qcom,current-ma = <300>; - qcom,ires-ua = <12500>; - qcom,hdrm-voltage-mv = <325>; - qcom,hdrm-vol-hi-lo-win-mv = <100>; - }; - - pm2falcon_torch1: qcom,torch_1 { - label = "torch"; - qcom,led-name = "led:torch_1"; - qcom,max-current = <500>; - qcom,default-led-trigger = "torch1_trigger"; - qcom,id = <1>; - qcom,current-ma = <300>; - qcom,ires-ua = <12500>; - qcom,hdrm-voltage-mv = <325>; - qcom,hdrm-vol-hi-lo-win-mv = <100>; - }; - - pm2falcon_torch2: qcom,torch_2 { - label = "torch"; - qcom,led-name = "led:torch_2"; - qcom,max-current = <500>; - qcom,default-led-trigger = "torch2_trigger"; - qcom,id = <2>; - qcom,current-ma = <300>; - qcom,ires-ua = <12500>; - qcom,hdrm-voltage-mv = <325>; - qcom,hdrm-vol-hi-lo-win-mv = <100>; - pinctrl-names = "led_enable","led_disable"; - pinctrl-0 = <&led_enable>; - pinctrl-1 = <&led_disable>; - }; - - pm2falcon_switch0: qcom,led_switch_0 { - label = "switch"; - qcom,led-name = "led:switch_0"; - qcom,led-mask = <3>; - qcom,default-led-trigger = "switch0_trigger"; - }; - - pm2falcon_switch1: qcom,led_switch_1 { - label = "switch"; - qcom,led-name = "led:switch_1"; - qcom,led-mask = <4>; - qcom,default-led-trigger = "switch1_trigger"; - }; - }; - - pm2falcon_lcdb: qpnp-lcdb@ec00 { - compatible = "qcom,qpnp-lcdb-regulator"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0xec00 0x100>; - - lcdb_ldo_vreg: ldo { - label = "ldo"; - regulator-name = "lcdb_ldo"; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <6000000>; - }; - - lcdb_ncp_vreg: ncp { - label = "ncp"; - regulator-name = "lcdb_ncp"; - regulator-min-microvolt = <4000000>; - regulator-max-microvolt = <6000000>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msm-pm3falcon.dtsi b/arch/arm/boot/dts/qcom/msm-pm3falcon.dtsi deleted file mode 100644 index f9a33fdc3e85..000000000000 --- a/arch/arm/boot/dts/qcom/msm-pm3falcon.dtsi +++ /dev/null @@ -1,21 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Disable WLED */ -&pm2falcon_wled { - status = "disabled"; -}; - -/* disable LCDB */ -&pm2falcon_lcdb { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/qcom/msm-pm660-rpm-regulator.dtsi b/arch/arm/boot/dts/qcom/msm-pm660-rpm-regulator.dtsi new file mode 100644 index 000000000000..0f87d1390d5c --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-pm660-rpm-regulator.dtsi @@ -0,0 +1,298 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&rpm_bus { + rpm-regulator-smpa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <4>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660_s4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <5>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660_s5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <6>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660_s6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660_l1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660_l2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660_l3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660_l5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660_l6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660_l7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa8 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l8 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660_l8"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa9 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <9>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l9 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660_l9"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa10 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l10 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660_l10"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa11 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <11>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l11 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660_l11"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa12 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l12 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660_l12"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa13 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <13>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l13 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660_l13"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa14 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <14>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l14 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660_l14"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa15 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <15>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l15 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660_l15"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa17 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <17>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l17 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660_l17"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa19 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <19>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l19 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660_l19"; + qcom,set = <3>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm-pm660.dtsi b/arch/arm/boot/dts/qcom/msm-pm660.dtsi new file mode 100644 index 000000000000..3674e2e5570b --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-pm660.dtsi @@ -0,0 +1,608 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +&spmi_bus { + qcom,pm660@0 { + compatible ="qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm660_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>, + <0x0 0x8 0x1 IRQ_TYPE_NONE>, + <0x0 0x8 0x4 IRQ_TYPE_NONE>, + <0x0 0x8 0x5 IRQ_TYPE_NONE>; + interrupt-names = "kpdpwr", "resin", + "resin-bark", "kpdpwr-resin-bark"; + qcom,pon-dbc-delay = <15625>; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = <0>; + qcom,pull-up = <1>; + linux,code = <116>; + }; + + qcom,pon_2 { + qcom,pon-type = <1>; + qcom,pull-up = <1>; + linux,code = <114>; + }; + }; + + qcom,temp-alarm@2400 { + compatible = "qcom,qpnp-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + label = "pm660_tz"; + qcom,channel-num = <6>; + qcom,temp_alarm-vadc = <&pm660_vadc>; + }; + + pm660_gpios: gpios { + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm660-gpio"; + + gpio@c000 { + reg = <0xc000 0x100>; + qcom,pin-num = <1>; + status = "disabled"; + }; + + gpio@c100 { + reg = <0xc100 0x100>; + qcom,pin-num = <2>; + status = "disabled"; + }; + + gpio@c200 { + reg = <0xc200 0x100>; + qcom,pin-num = <3>; + status = "disabled"; + }; + + gpio@c300 { + reg = <0xc300 0x100>; + qcom,pin-num = <4>; + status = "disabled"; + }; + + gpio@c400 { + reg = <0xc400 0x100>; + qcom,pin-num = <5>; + status = "disabled"; + }; + + gpio@c500 { + reg = <0xc500 0x100>; + qcom,pin-num = <6>; + status = "disabled"; + }; + + gpio@c600 { + reg = <0xc600 0x100>; + qcom,pin-num = <7>; + status = "disabled"; + }; + + gpio@c700 { + reg = <0xc700 0x100>; + qcom,pin-num = <8>; + status = "disabled"; + }; + + gpio@c800 { + reg = <0xc800 0x100>; + qcom,pin-num = <9>; + status = "disabled"; + }; + + gpio@c900 { + reg = <0xc900 0x100>; + qcom,pin-num = <10>; + status = "disabled"; + }; + + gpio@ca00 { + reg = <0xca00 0x100>; + qcom,pin-num = <11>; + status = "disabled"; + }; + + gpio@cb00 { + reg = <0xcb00 0x100>; + qcom,pin-num = <12>; + status = "disabled"; + }; + + gpio@cc00 { + reg = <0xcc00 0x100>; + qcom,pin-num = <13>; + status = "disabled"; + }; + }; + + pm660_coincell: qcom,coincell@2800 { + compatible = "qcom,qpnp-coincell"; + reg = <0x2800 0x100>; + }; + + pm660_rtc: qcom,pm660_rtc { + compatible = "qcom,qpnp-rtc"; + #address-cells = <1>; + #size-cells = <1>; + qcom,qpnp-rtc-write = <0>; + qcom,qpnp-rtc-alarm-pwrup = <0>; + + qcom,pm660_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + qcom,pm660_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + }; + + pm660_vadc: vadc@3100 { + compatible = "qcom,qpnp-vadc-hc"; + reg = <0x3100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1875>; + + chan@6 { + label = "die_temp"; + reg = <6>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <3>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + qcom,cal-val = <0>; + }; + + chan@0 { + label = "ref_gnd"; + reg = <0>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + qcom,cal-val = <0>; + }; + + chan@1 { + label = "ref_1250v"; + reg = <1>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + qcom,cal-val = <0>; + }; + + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@85 { + label = "vcoin"; + reg = <0x85>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@4d { + label = "msm_therm"; + reg = <0x4d>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@1d { + label = "drax_temp"; + reg = <0x1d>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <3>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + qcom,cal-val = <0>; + }; + }; + + pm660_charger: qcom,qpnp-smb2 { + compatible = "qcom,qpnp-smb2"; + #address-cells = <1>; + #size-cells = <1>; + + qcom,pmic-revid = <&pm660_revid>; + + io-channels = <&pm660_rradc 8>, + <&pm660_rradc 10>, + <&pm660_rradc 3>, + <&pm660_rradc 4>; + io-channel-names = "charger_temp", + "charger_temp_max", + "usbin_i", + "usbin_v"; + + qcom,wipower-max-uw = <5000000>; + dpdm-supply = <&qusb_phy0>; + + qcom,thermal-mitigation + = <3000000 1500000 1000000 500000>; + + qcom,chgr@1000 { + reg = <0x1000 0x100>; + interrupts = <0x0 0x10 0x0 IRQ_TYPE_NONE>, + <0x0 0x10 0x1 IRQ_TYPE_NONE>, + <0x0 0x10 0x2 IRQ_TYPE_NONE>, + <0x0 0x10 0x3 IRQ_TYPE_NONE>, + <0x0 0x10 0x4 IRQ_TYPE_NONE>; + + interrupt-names = "chg-error", + "chg-state-change", + "step-chg-state-change", + "step-chg-soc-update-fail", + "step-chg-soc-update-request"; + }; + + qcom,otg@1100 { + reg = <0x1100 0x100>; + interrupts = <0x0 0x11 0x0 IRQ_TYPE_NONE>, + <0x0 0x11 0x1 IRQ_TYPE_NONE>, + <0x0 0x11 0x2 IRQ_TYPE_NONE>, + <0x0 0x11 0x3 IRQ_TYPE_NONE>; + + interrupt-names = "otg-fail", + "otg-overcurrent", + "otg-oc-dis-sw-sts", + "testmode-change-detect"; + }; + + qcom,bat-if@1200 { + reg = <0x1200 0x100>; + interrupts = <0x0 0x12 0x0 IRQ_TYPE_NONE>, + <0x0 0x12 0x1 IRQ_TYPE_NONE>, + <0x0 0x12 0x2 IRQ_TYPE_NONE>, + <0x0 0x12 0x3 IRQ_TYPE_NONE>, + <0x0 0x12 0x4 IRQ_TYPE_NONE>, + <0x0 0x12 0x5 IRQ_TYPE_NONE>; + + interrupt-names = "bat-temp", + "bat-ocp", + "bat-ov", + "bat-low", + "bat-therm-or-id-missing", + "bat-terminal-missing"; + }; + + qcom,usb-chgpth@1300 { + reg = <0x1300 0x100>; + interrupts = <0x0 0x13 0x0 IRQ_TYPE_NONE>, + <0x0 0x13 0x1 IRQ_TYPE_NONE>, + <0x0 0x13 0x2 IRQ_TYPE_NONE>, + <0x0 0x13 0x3 IRQ_TYPE_NONE>, + <0x0 0x13 0x4 IRQ_TYPE_NONE>, + <0x0 0x13 0x5 IRQ_TYPE_NONE>, + <0x0 0x13 0x6 IRQ_TYPE_NONE>, + <0x0 0x13 0x7 IRQ_TYPE_NONE>; + + interrupt-names = "usbin-collapse", + "usbin-lt-3p6v", + "usbin-uv", + "usbin-ov", + "usbin-plugin", + "usbin-src-change", + "usbin-icl-change", + "type-c-change"; + }; + + qcom,dc-chgpth@1400 { + reg = <0x1400 0x100>; + interrupts = <0x0 0x14 0x0 IRQ_TYPE_NONE>, + <0x0 0x14 0x1 IRQ_TYPE_NONE>, + <0x0 0x14 0x2 IRQ_TYPE_NONE>, + <0x0 0x14 0x3 IRQ_TYPE_NONE>, + <0x0 0x14 0x4 IRQ_TYPE_NONE>, + <0x0 0x14 0x5 IRQ_TYPE_NONE>, + <0x0 0x14 0x6 IRQ_TYPE_NONE>; + + interrupt-names = "dcin-collapse", + "dcin-lt-3p6v", + "dcin-uv", + "dcin-ov", + "dcin-plugin", + "div2-en-dg", + "dcin-icl-change"; + }; + + qcom,chgr-misc@1600 { + reg = <0x1600 0x100>; + interrupts = <0x0 0x16 0x0 IRQ_TYPE_NONE>, + <0x0 0x16 0x1 IRQ_TYPE_NONE>, + <0x0 0x16 0x2 IRQ_TYPE_NONE>, + <0x0 0x16 0x3 IRQ_TYPE_NONE>, + <0x0 0x16 0x4 IRQ_TYPE_NONE>, + <0x0 0x16 0x5 IRQ_TYPE_NONE>, + <0x0 0x16 0x6 IRQ_TYPE_NONE>, + <0x0 0x16 0x7 IRQ_TYPE_NONE>; + + interrupt-names = "wdog-snarl", + "wdog-bark", + "aicl-fail", + "aicl-done", + "high-duty-cycle", + "input-current-limiting", + "temperature-change", + "switcher-power-ok"; + }; + }; + + pm660_pdphy: qcom,usb-pdphy@1700 { + compatible = "qcom,qpnp-pdphy"; + reg = <0x1700 0x100>; + vdd-pdphy-supply = <&pm660l_l7>; + vbus-supply = <&smb2_vbus>; + vconn-supply = <&smb2_vconn>; + interrupts = <0x0 0x17 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x3 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x4 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x5 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x6 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "sig-tx", + "sig-rx", + "msg-tx", + "msg-rx", + "msg-tx-failed", + "msg-tx-discarded", + "msg-rx-discarded"; + }; + + pm660_adc_tm: vadc@3400 { + compatible = "qcom,qpnp-adc-tm-hc"; + reg = <0x3400 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + qcom,adc-bit-resolution = <15>; + qcom,adc-vdd-reference = <1875>; + qcom,adc_tm-vadc = <&pm660_vadc>; + qcom,decimation = <0>; + qcom,fast-avg-setup = <0>; + + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,btm-channel-number = <0x60>; + }; + + chan@4d { + label = "msm_therm"; + reg = <0x4d>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x68>; + qcom,thermal-node; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x70>; + qcom,thermal-node; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x78>; + qcom,thermal-node; + }; + }; + + pm660_rradc: rradc@4500 { + compatible = "qcom,rradc"; + reg = <0x4500 0x100>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + }; + + pm660_fg: qpnp,fg { + compatible = "qcom,fg-gen3"; + #address-cells = <1>; + #size-cells = <1>; + qcom,pmic-revid = <&pm660_revid>; + io-channels = <&pm660_rradc 0>; + io-channel-names = "rradc_batt_id"; + qcom,rradc-base = <0x4500>; + qcom,fg-esr-timer-awake = <96>; + qcom,fg-esr-timer-asleep = <256>; + qcom,cycle-counter-en; + status = "okay"; + + qcom,fg-batt-soc@4000 { + status = "okay"; + reg = <0x4000 0x100>; + interrupts = <0x0 0x40 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x40 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x40 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x40 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x40 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x40 0x5 + IRQ_TYPE_EDGE_RISING>, + <0x0 0x40 0x6 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x40 0x7 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "soc-update", + "soc-ready", + "bsoc-delta", + "msoc-delta", + "msoc-low", + "msoc-empty", + "msoc-high", + "msoc-full"; + }; + + qcom,fg-batt-info@4100 { + status = "okay"; + reg = <0x4100 0x100>; + interrupts = <0x0 0x41 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x41 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x41 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x41 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x41 0x6 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "vbatt-pred-delta", + "vbatt-low", + "esr-delta", + "batt-missing", + "batt-temp-delta"; + }; + + qcom,fg-memif@4400 { + status = "okay"; + reg = <0x4400 0x100>; + interrupts = <0x0 0x44 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x44 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x44 0x2 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "ima-rdy", + "mem-xcp", + "dma-grant"; + }; + }; + + bcl@4200 { + compatible = "qcom,msm-bcl-lmh"; + reg = <0x4200 0xff>, + <0x4300 0xff>; + reg-names = "fg_user_adc", + "fg_lmh"; + interrupts = <0x0 0x42 0x0 IRQ_TYPE_NONE>, + <0x0 0x42 0x2 IRQ_TYPE_NONE>; + interrupt-names = "bcl-high-ibat-int", + "bcl-low-vbat-int"; + qcom,vbat-polling-delay-ms = <100>; + qcom,ibat-polling-delay-ms = <100>; + }; + }; + + qcom,pm660@1 { + compatible ="qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm660_haptics: qcom,haptic@c000 { + compatible = "qcom,qpnp-haptic"; + reg = <0xc000 0x100>; + interrupts = <0x1 0xc0 0x0>, + <0x1 0xc0 0x1>; + interrupt-names = "sc-irq", "play-irq"; + qcom,actuator-type = "lra"; + qcom,play-mode = "direct"; + qcom,vmax-mv = <3200>; + qcom,ilim-ma = <800>; + qcom,wave-shape = "square"; + qcom,wave-play-rate-us = <6667>; + qcom,int-pwm-freq-khz = <505>; + qcom,sc-deb-cycles = <8>; + qcom,en-brake; + qcom,brake-pattern = [03 03 00 00]; + qcom,use-play-irq; + qcom,use-sc-irq; + qcom,lra-high-z = "opt1"; + qcom,lra-auto-res-mode = "qwd"; + qcom,lra-res-cal-period = <4>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm-pm660a.dtsi b/arch/arm/boot/dts/qcom/msm-pm660a.dtsi new file mode 100644 index 000000000000..c43aa5425aae --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-pm660a.dtsi @@ -0,0 +1,21 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Disable WLED */ +&pm660l_wled { + status = "disabled"; +}; + +/* disable LCDB */ +&pm660l_lcdb { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/qcom/msm-pm660l-rpm-regulator.dtsi b/arch/arm/boot/dts/qcom/msm-pm660l-rpm-regulator.dtsi new file mode 100644 index 000000000000..b10f8e559090 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-pm660l-rpm-regulator.dtsi @@ -0,0 +1,238 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&rpm_bus { + rpm-regulator-smpb1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpb"; + qcom,resource-id = <1>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_s1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpb2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpb"; + qcom,resource-id = <2>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_s2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpb3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpb"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_s3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpb5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpb"; + qcom,resource-id = <5>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_s5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldob1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldob"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_l1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldob2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldob"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_l2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldob3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldob"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_l3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldob4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldob"; + qcom,resource-id = <4>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_l4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldob5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldob"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_l5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldob6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldob"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_l6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldob7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldob"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_l7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldob8 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldob"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l8 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_l8"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldob9 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwsc"; + qcom,resource-id = <0>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l9 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_l9"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldob10 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwsm"; + qcom,resource-id = <0>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l10 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_l10"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-bobb { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "bobb"; + qcom,resource-id = <1>; + qcom,regulator-type = <4>; + status = "disabled"; + + regulator-bob { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_bob"; + qcom,set = <3>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm-pm660l.dtsi b/arch/arm/boot/dts/qcom/msm-pm660l.dtsi new file mode 100644 index 000000000000..a9820cfbc02c --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-pm660l.dtsi @@ -0,0 +1,395 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +&spmi_bus { + qcom,pm660l@2 { + compatible = "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm660l_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + qcom,secondary-pon-reset; + qcom,hard-reset-poweroff-type = + ; + }; + + qcom,temp-alarm@2400 { + compatible = "qcom,qpnp-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + label = "pm660l_tz"; + }; + + pm660l_gpios: gpios { + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm660l-gpio"; + + gpio@c000 { + reg = <0xc000 0x100>; + qcom,pin-num = <1>; + status = "disabled"; + }; + + gpio@c100 { + reg = <0xc100 0x100>; + qcom,pin-num = <2>; + status = "disabled"; + }; + + gpio@c200 { + reg = <0xc200 0x100>; + qcom,pin-num = <3>; + status = "disabled"; + }; + + gpio@c300 { + reg = <0xc300 0x100>; + qcom,pin-num = <4>; + status = "disabled"; + }; + + gpio@c400 { + reg = <0xc400 0x100>; + qcom,pin-num = <5>; + status = "disabled"; + }; + + gpio@c500 { + reg = <0xc500 0x100>; + qcom,pin-num = <6>; + status = "disabled"; + }; + + gpio@c600 { + reg = <0xc600 0x100>; + qcom,pin-num = <7>; + status = "disabled"; + }; + + gpio@c700 { + reg = <0xc700 0x100>; + qcom,pin-num = <8>; + status = "disabled"; + }; + + gpio@c800 { + reg = <0xc800 0x100>; + qcom,pin-num = <9>; + status = "disabled"; + }; + + gpio@c900 { + reg = <0xc900 0x100>; + qcom,pin-num = <10>; + status = "disabled"; + }; + + gpio@ca00 { + reg = <0xca00 0x100>; + qcom,pin-num = <11>; + status = "disabled"; + }; + + gpio@cb00 { + reg = <0xcb00 0x100>; + qcom,pin-num = <12>; + status = "disabled"; + }; + + }; + }; + + pm660l_3: qcom,pm660l@3 { + compatible ="qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm660l_pwm_1: pwm@b100 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb100 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", + "qpnp-lpg-lut-base"; + qcom,channel-id = <1>; + qcom,lpg-lut-size = <0x7e>; + qcom,supported-sizes = <6>, <9>; + qcom,ramp-index = <0>; + #pwm-cells = <2>; + }; + + pm660l_pwm_2: pwm@b200 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb200 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", + "qpnp-lpg-lut-base"; + qcom,channel-id = <2>; + qcom,lpg-lut-size = <0x7e>; + qcom,supported-sizes = <6>, <9>; + qcom,ramp-index = <1>; + #pwm-cells = <2>; + }; + + pm660l_pwm_3: pwm@b300 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb300 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", + "qpnp-lpg-lut-base"; + qcom,channel-id = <3>; + qcom,lpg-lut-size = <0x7e>; + qcom,supported-sizes = <6>, <9>; + qcom,ramp-index = <2>; + #pwm-cells = <2>; + }; + + pm660l_pwm_4: pwm@b400 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb400 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", + "qpnp-lpg-lut-base"; + qcom,channel-id = <4>; + qcom,lpg-lut-size = <0x7e>; + qcom,supported-sizes = <6>, <9>; + qcom,ramp-index = <3>; + #pwm-cells = <2>; + status = "disabled"; + }; + + qcom,leds@d000 { + compatible = "qcom,leds-qpnp"; + reg = <0xd000 0x100>; + label = "rgb"; + + red_led: qcom,rgb_0 { + label = "rgb"; + qcom,id = <3>; + qcom,mode = "pwm"; + pwms = <&pm660l_pwm_3 0 0>; + qcom,pwm-us = <1000>; + qcom,max-current = <12>; + qcom,default-state = "off"; + linux,name = "red"; + linux,default-trigger = + "battery-charging"; + }; + + green_led: qcom,rgb_1 { + label = "rgb"; + qcom,id = <4>; + qcom,mode = "pwm"; + pwms = <&pm660l_pwm_2 0 0>; + qcom,pwm-us = <1000>; + qcom,max-current = <12>; + qcom,default-state = "off"; + linux,name = "green"; + linux,default-trigger = "battery-full"; + }; + + blue_led: qcom,rgb_2 { + label = "rgb"; + qcom,id = <5>; + qcom,mode = "pwm"; + pwms = <&pm660l_pwm_1 0 0>; + qcom,pwm-us = <1000>; + qcom,max-current = <12>; + qcom,default-state = "off"; + linux,name = "blue"; + linux,default-trigger = "boot-indication"; + }; + }; + + pm660l_wled: qcom,leds@d800 { + compatible = "qcom,qpnp-wled"; + reg = <0xd800 0x100>, + <0xd900 0x100>; + reg-names = "qpnp-wled-ctrl-base", + "qpnp-wled-sink-base"; + interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x3 0xd8 0x2 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "ovp-irq", "sc-irq"; + linux,name = "wled"; + linux,default-trigger = "bkl-trigger"; + qcom,fdbk-output = "auto"; + qcom,vref-uv = <127500>; + qcom,switch-freq-khz = <800>; + qcom,ovp-mv = <29600>; + qcom,ilim-ma = <970>; + qcom,boost-duty-ns = <26>; + qcom,mod-freq-khz = <9600>; + qcom,dim-mode = "hybrid"; + qcom,hyb-thres = <625>; + qcom,sync-dly-us = <800>; + qcom,fs-curr-ua = <25000>; + qcom,cons-sync-write-delay-us = <1000>; + qcom,led-strings-list = [00 01 02]; + qcom,en-ext-pfet-sc-pro; + qcom,loop-auto-gm-en; + qcom,pmic-revid = <&pm660l_revid>; + status = "ok"; + }; + + flash_led: qcom,leds@d300 { + compatible = "qcom,qpnp-flash-led-v2"; + reg = <0xd300 0x100>; + label = "flash"; + interrupts = <0x3 0xd3 0x0 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd3 0x3 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd3 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "led-fault-irq", + "all-ramp-down-done-irq", + "all-ramp-up-done-irq"; + qcom,hdrm-auto-mode; + qcom,short-circuit-det; + qcom,open-circuit-det; + qcom,vph-droop-det; + qcom,thermal-derate-en; + qcom,thermal-derate-current = <200 500 1000>; + qcom,isc-delay = <192>; + qcom,pmic-revid = <&pm660l_revid>; + + pm660l_flash0: qcom,flash_0 { + label = "flash"; + qcom,led-name = "led:flash_0"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash0_trigger"; + qcom,id = <0>; + qcom,current-ma = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pm660l_flash1: qcom,flash_1 { + label = "flash"; + qcom,led-name = "led:flash_1"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash1_trigger"; + qcom,id = <1>; + qcom,current-ma = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pm660l_flash2: qcom,flash_2 { + label = "flash"; + qcom,led-name = "led:flash_2"; + qcom,max-current = <750>; + qcom,default-led-trigger = "flash2_trigger"; + qcom,id = <2>; + qcom,current-ma = <500>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + pinctrl-names = "led_enable","led_disable"; + pinctrl-0 = <&led_enable>; + pinctrl-1 = <&led_disable>; + }; + + pm660l_torch0: qcom,torch_0 { + label = "torch"; + qcom,led-name = "led:torch_0"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch0_trigger"; + qcom,id = <0>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pm660l_torch1: qcom,torch_1 { + label = "torch"; + qcom,led-name = "led:torch_1"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch1_trigger"; + qcom,id = <1>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pm660l_torch2: qcom,torch_2 { + label = "torch"; + qcom,led-name = "led:torch_2"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch2_trigger"; + qcom,id = <2>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + pinctrl-names = "led_enable","led_disable"; + pinctrl-0 = <&led_enable>; + pinctrl-1 = <&led_disable>; + }; + + pm660l_switch0: qcom,led_switch_0 { + label = "switch"; + qcom,led-name = "led:switch_0"; + qcom,led-mask = <3>; + qcom,default-led-trigger = "switch0_trigger"; + }; + + pm660l_switch1: qcom,led_switch_1 { + label = "switch"; + qcom,led-name = "led:switch_1"; + qcom,led-mask = <4>; + qcom,default-led-trigger = "switch1_trigger"; + }; + }; + + pm660l_lcdb: qpnp-lcdb@ec00 { + compatible = "qcom,qpnp-lcdb-regulator"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xec00 0x100>; + + lcdb_ldo_vreg: ldo { + label = "ldo"; + regulator-name = "lcdb_ldo"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + }; + + lcdb_ncp_vreg: ncp { + label = "ncp"; + regulator-name = "lcdb_ncp"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm-pmfalcon-rpm-regulator.dtsi b/arch/arm/boot/dts/qcom/msm-pmfalcon-rpm-regulator.dtsi deleted file mode 100644 index 0b625bf04ef5..000000000000 --- a/arch/arm/boot/dts/qcom/msm-pmfalcon-rpm-regulator.dtsi +++ /dev/null @@ -1,298 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -&rpm_bus { - rpm-regulator-smpa4 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "smpa"; - qcom,resource-id = <4>; - qcom,regulator-type = <1>; - status = "disabled"; - - regulator-s4 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_s4"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-smpa5 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "smpa"; - qcom,resource-id = <5>; - qcom,regulator-type = <1>; - status = "disabled"; - - regulator-s5 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_s5"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-smpa6 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "smpa"; - qcom,resource-id = <6>; - qcom,regulator-type = <1>; - status = "disabled"; - - regulator-s6 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_s6"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldoa1 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldoa"; - qcom,resource-id = <1>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l1 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l1"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldoa2 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldoa"; - qcom,resource-id = <2>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l2 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l2"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldoa3 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldoa"; - qcom,resource-id = <3>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l3 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l3"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldoa5 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldoa"; - qcom,resource-id = <5>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l5 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l5"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldoa6 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldoa"; - qcom,resource-id = <6>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l6 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l6"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldoa7 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldoa"; - qcom,resource-id = <7>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l7 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l7"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldoa8 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldoa"; - qcom,resource-id = <8>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l8 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l8"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldoa9 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldoa"; - qcom,resource-id = <9>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l9 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l9"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldoa10 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldoa"; - qcom,resource-id = <10>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l10 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l10"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldoa11 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldoa"; - qcom,resource-id = <11>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l11 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l11"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldoa12 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldoa"; - qcom,resource-id = <12>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l12 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l12"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldoa13 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldoa"; - qcom,resource-id = <13>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l13 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l13"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldoa14 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldoa"; - qcom,resource-id = <14>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l14 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l14"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldoa15 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldoa"; - qcom,resource-id = <15>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l15 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l15"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldoa17 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldoa"; - qcom,resource-id = <17>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l17 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l17"; - qcom,set = <3>; - status = "disabled"; - }; - }; - - rpm-regulator-ldoa19 { - compatible = "qcom,rpm-smd-regulator-resource"; - qcom,resource-name = "ldoa"; - qcom,resource-id = <19>; - qcom,regulator-type = <0>; - status = "disabled"; - - regulator-l19 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l19"; - qcom,set = <3>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msm-pmfalcon.dtsi b/arch/arm/boot/dts/qcom/msm-pmfalcon.dtsi deleted file mode 100644 index 0168cb2cddb3..000000000000 --- a/arch/arm/boot/dts/qcom/msm-pmfalcon.dtsi +++ /dev/null @@ -1,608 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -&spmi_bus { - qcom,pmfalcon@0 { - compatible ="qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <2>; - #size-cells = <0>; - - pmfalcon_revid: qcom,revid@100 { - compatible = "qcom,qpnp-revid"; - reg = <0x100 0x100>; - }; - - qcom,power-on@800 { - compatible = "qcom,qpnp-power-on"; - reg = <0x800 0x100>; - interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>, - <0x0 0x8 0x1 IRQ_TYPE_NONE>, - <0x0 0x8 0x4 IRQ_TYPE_NONE>, - <0x0 0x8 0x5 IRQ_TYPE_NONE>; - interrupt-names = "kpdpwr", "resin", - "resin-bark", "kpdpwr-resin-bark"; - qcom,pon-dbc-delay = <15625>; - qcom,system-reset; - qcom,store-hard-reset-reason; - - qcom,pon_1 { - qcom,pon-type = <0>; - qcom,pull-up = <1>; - linux,code = <116>; - }; - - qcom,pon_2 { - qcom,pon-type = <1>; - qcom,pull-up = <1>; - linux,code = <114>; - }; - }; - - qcom,temp-alarm@2400 { - compatible = "qcom,qpnp-temp-alarm"; - reg = <0x2400 0x100>; - interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; - label = "pmfalcon_tz"; - qcom,channel-num = <6>; - qcom,temp_alarm-vadc = <&pmfalcon_vadc>; - }; - - pmfalcon_gpios: gpios { - compatible = "qcom,qpnp-pin"; - gpio-controller; - #gpio-cells = <2>; - #address-cells = <1>; - #size-cells = <1>; - label = "pmfalcon-gpio"; - - gpio@c000 { - reg = <0xc000 0x100>; - qcom,pin-num = <1>; - status = "disabled"; - }; - - gpio@c100 { - reg = <0xc100 0x100>; - qcom,pin-num = <2>; - status = "disabled"; - }; - - gpio@c200 { - reg = <0xc200 0x100>; - qcom,pin-num = <3>; - status = "disabled"; - }; - - gpio@c300 { - reg = <0xc300 0x100>; - qcom,pin-num = <4>; - status = "disabled"; - }; - - gpio@c400 { - reg = <0xc400 0x100>; - qcom,pin-num = <5>; - status = "disabled"; - }; - - gpio@c500 { - reg = <0xc500 0x100>; - qcom,pin-num = <6>; - status = "disabled"; - }; - - gpio@c600 { - reg = <0xc600 0x100>; - qcom,pin-num = <7>; - status = "disabled"; - }; - - gpio@c700 { - reg = <0xc700 0x100>; - qcom,pin-num = <8>; - status = "disabled"; - }; - - gpio@c800 { - reg = <0xc800 0x100>; - qcom,pin-num = <9>; - status = "disabled"; - }; - - gpio@c900 { - reg = <0xc900 0x100>; - qcom,pin-num = <10>; - status = "disabled"; - }; - - gpio@ca00 { - reg = <0xca00 0x100>; - qcom,pin-num = <11>; - status = "disabled"; - }; - - gpio@cb00 { - reg = <0xcb00 0x100>; - qcom,pin-num = <12>; - status = "disabled"; - }; - - gpio@cc00 { - reg = <0xcc00 0x100>; - qcom,pin-num = <13>; - status = "disabled"; - }; - }; - - pmfalcon_coincell: qcom,coincell@2800 { - compatible = "qcom,qpnp-coincell"; - reg = <0x2800 0x100>; - }; - - pmfalcon_rtc: qcom,pmfalcon_rtc { - compatible = "qcom,qpnp-rtc"; - #address-cells = <1>; - #size-cells = <1>; - qcom,qpnp-rtc-write = <0>; - qcom,qpnp-rtc-alarm-pwrup = <0>; - - qcom,pmfalcon_rtc_rw@6000 { - reg = <0x6000 0x100>; - }; - qcom,pmfalcon_rtc_alarm@6100 { - reg = <0x6100 0x100>; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; - }; - }; - - pmfalcon_vadc: vadc@3100 { - compatible = "qcom,qpnp-vadc-hc"; - reg = <0x3100 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "eoc-int-en-set"; - qcom,adc-bit-resolution = <15>; - qcom,adc-vdd-reference = <1875>; - - chan@6 { - label = "die_temp"; - reg = <6>; - qcom,decimation = <2>; - qcom,pre-div-channel-scaling = <0>; - qcom,calibration-type = "absolute"; - qcom,scale-function = <3>; - qcom,hw-settle-time = <0>; - qcom,fast-avg-setup = <0>; - qcom,cal-val = <0>; - }; - - chan@0 { - label = "ref_gnd"; - reg = <0>; - qcom,decimation = <2>; - qcom,pre-div-channel-scaling = <0>; - qcom,calibration-type = "absolute"; - qcom,scale-function = <0>; - qcom,hw-settle-time = <0>; - qcom,fast-avg-setup = <0>; - qcom,cal-val = <0>; - }; - - chan@1 { - label = "ref_1250v"; - reg = <1>; - qcom,decimation = <2>; - qcom,pre-div-channel-scaling = <0>; - qcom,calibration-type = "absolute"; - qcom,scale-function = <0>; - qcom,hw-settle-time = <0>; - qcom,fast-avg-setup = <0>; - qcom,cal-val = <0>; - }; - - chan@83 { - label = "vph_pwr"; - reg = <0x83>; - qcom,decimation = <2>; - qcom,pre-div-channel-scaling = <1>; - qcom,calibration-type = "absolute"; - qcom,scale-function = <0>; - qcom,hw-settle-time = <0>; - qcom,fast-avg-setup = <0>; - }; - - chan@85 { - label = "vcoin"; - reg = <0x85>; - qcom,decimation = <2>; - qcom,pre-div-channel-scaling = <1>; - qcom,calibration-type = "absolute"; - qcom,scale-function = <0>; - qcom,hw-settle-time = <0>; - qcom,fast-avg-setup = <0>; - }; - - chan@4c { - label = "xo_therm"; - reg = <0x4c>; - qcom,decimation = <2>; - qcom,pre-div-channel-scaling = <0>; - qcom,calibration-type = "ratiometric"; - qcom,scale-function = <4>; - qcom,hw-settle-time = <2>; - qcom,fast-avg-setup = <0>; - }; - - chan@4d { - label = "msm_therm"; - reg = <0x4d>; - qcom,decimation = <2>; - qcom,pre-div-channel-scaling = <0>; - qcom,calibration-type = "ratiometric"; - qcom,scale-function = <2>; - qcom,hw-settle-time = <2>; - qcom,fast-avg-setup = <0>; - }; - - chan@51 { - label = "quiet_therm"; - reg = <0x51>; - qcom,decimation = <2>; - qcom,pre-div-channel-scaling = <0>; - qcom,calibration-type = "ratiometric"; - qcom,scale-function = <2>; - qcom,hw-settle-time = <2>; - qcom,fast-avg-setup = <0>; - }; - - chan@1d { - label = "drax_temp"; - reg = <0x1d>; - qcom,decimation = <2>; - qcom,pre-div-channel-scaling = <0>; - qcom,calibration-type = "absolute"; - qcom,scale-function = <3>; - qcom,hw-settle-time = <0>; - qcom,fast-avg-setup = <0>; - qcom,cal-val = <0>; - }; - }; - - pmfalcon_charger: qcom,qpnp-smb2 { - compatible = "qcom,qpnp-smb2"; - #address-cells = <1>; - #size-cells = <1>; - - qcom,pmic-revid = <&pmfalcon_revid>; - - io-channels = <&pmfalcon_rradc 8>, - <&pmfalcon_rradc 10>, - <&pmfalcon_rradc 3>, - <&pmfalcon_rradc 4>; - io-channel-names = "charger_temp", - "charger_temp_max", - "usbin_i", - "usbin_v"; - - qcom,wipower-max-uw = <5000000>; - dpdm-supply = <&qusb_phy0>; - - qcom,thermal-mitigation - = <3000000 1500000 1000000 500000>; - - qcom,chgr@1000 { - reg = <0x1000 0x100>; - interrupts = <0x0 0x10 0x0 IRQ_TYPE_NONE>, - <0x0 0x10 0x1 IRQ_TYPE_NONE>, - <0x0 0x10 0x2 IRQ_TYPE_NONE>, - <0x0 0x10 0x3 IRQ_TYPE_NONE>, - <0x0 0x10 0x4 IRQ_TYPE_NONE>; - - interrupt-names = "chg-error", - "chg-state-change", - "step-chg-state-change", - "step-chg-soc-update-fail", - "step-chg-soc-update-request"; - }; - - qcom,otg@1100 { - reg = <0x1100 0x100>; - interrupts = <0x0 0x11 0x0 IRQ_TYPE_NONE>, - <0x0 0x11 0x1 IRQ_TYPE_NONE>, - <0x0 0x11 0x2 IRQ_TYPE_NONE>, - <0x0 0x11 0x3 IRQ_TYPE_NONE>; - - interrupt-names = "otg-fail", - "otg-overcurrent", - "otg-oc-dis-sw-sts", - "testmode-change-detect"; - }; - - qcom,bat-if@1200 { - reg = <0x1200 0x100>; - interrupts = <0x0 0x12 0x0 IRQ_TYPE_NONE>, - <0x0 0x12 0x1 IRQ_TYPE_NONE>, - <0x0 0x12 0x2 IRQ_TYPE_NONE>, - <0x0 0x12 0x3 IRQ_TYPE_NONE>, - <0x0 0x12 0x4 IRQ_TYPE_NONE>, - <0x0 0x12 0x5 IRQ_TYPE_NONE>; - - interrupt-names = "bat-temp", - "bat-ocp", - "bat-ov", - "bat-low", - "bat-therm-or-id-missing", - "bat-terminal-missing"; - }; - - qcom,usb-chgpth@1300 { - reg = <0x1300 0x100>; - interrupts = <0x0 0x13 0x0 IRQ_TYPE_NONE>, - <0x0 0x13 0x1 IRQ_TYPE_NONE>, - <0x0 0x13 0x2 IRQ_TYPE_NONE>, - <0x0 0x13 0x3 IRQ_TYPE_NONE>, - <0x0 0x13 0x4 IRQ_TYPE_NONE>, - <0x0 0x13 0x5 IRQ_TYPE_NONE>, - <0x0 0x13 0x6 IRQ_TYPE_NONE>, - <0x0 0x13 0x7 IRQ_TYPE_NONE>; - - interrupt-names = "usbin-collapse", - "usbin-lt-3p6v", - "usbin-uv", - "usbin-ov", - "usbin-plugin", - "usbin-src-change", - "usbin-icl-change", - "type-c-change"; - }; - - qcom,dc-chgpth@1400 { - reg = <0x1400 0x100>; - interrupts = <0x0 0x14 0x0 IRQ_TYPE_NONE>, - <0x0 0x14 0x1 IRQ_TYPE_NONE>, - <0x0 0x14 0x2 IRQ_TYPE_NONE>, - <0x0 0x14 0x3 IRQ_TYPE_NONE>, - <0x0 0x14 0x4 IRQ_TYPE_NONE>, - <0x0 0x14 0x5 IRQ_TYPE_NONE>, - <0x0 0x14 0x6 IRQ_TYPE_NONE>; - - interrupt-names = "dcin-collapse", - "dcin-lt-3p6v", - "dcin-uv", - "dcin-ov", - "dcin-plugin", - "div2-en-dg", - "dcin-icl-change"; - }; - - qcom,chgr-misc@1600 { - reg = <0x1600 0x100>; - interrupts = <0x0 0x16 0x0 IRQ_TYPE_NONE>, - <0x0 0x16 0x1 IRQ_TYPE_NONE>, - <0x0 0x16 0x2 IRQ_TYPE_NONE>, - <0x0 0x16 0x3 IRQ_TYPE_NONE>, - <0x0 0x16 0x4 IRQ_TYPE_NONE>, - <0x0 0x16 0x5 IRQ_TYPE_NONE>, - <0x0 0x16 0x6 IRQ_TYPE_NONE>, - <0x0 0x16 0x7 IRQ_TYPE_NONE>; - - interrupt-names = "wdog-snarl", - "wdog-bark", - "aicl-fail", - "aicl-done", - "high-duty-cycle", - "input-current-limiting", - "temperature-change", - "switcher-power-ok"; - }; - }; - - pmfalcon_pdphy: qcom,usb-pdphy@1700 { - compatible = "qcom,qpnp-pdphy"; - reg = <0x1700 0x100>; - vdd-pdphy-supply = <&pm2falcon_l7>; - vbus-supply = <&smb2_vbus>; - vconn-supply = <&smb2_vconn>; - interrupts = <0x0 0x17 0x0 IRQ_TYPE_EDGE_RISING>, - <0x0 0x17 0x1 IRQ_TYPE_EDGE_RISING>, - <0x0 0x17 0x2 IRQ_TYPE_EDGE_RISING>, - <0x0 0x17 0x3 IRQ_TYPE_EDGE_RISING>, - <0x0 0x17 0x4 IRQ_TYPE_EDGE_RISING>, - <0x0 0x17 0x5 IRQ_TYPE_EDGE_RISING>, - <0x0 0x17 0x6 IRQ_TYPE_EDGE_RISING>; - - interrupt-names = "sig-tx", - "sig-rx", - "msg-tx", - "msg-rx", - "msg-tx-failed", - "msg-tx-discarded", - "msg-rx-discarded"; - }; - - pmfalcon_adc_tm: vadc@3400 { - compatible = "qcom,qpnp-adc-tm-hc"; - reg = <0x3400 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "eoc-int-en-set"; - qcom,adc-bit-resolution = <15>; - qcom,adc-vdd-reference = <1875>; - qcom,adc_tm-vadc = <&pmfalcon_vadc>; - qcom,decimation = <0>; - qcom,fast-avg-setup = <0>; - - chan@83 { - label = "vph_pwr"; - reg = <0x83>; - qcom,pre-div-channel-scaling = <1>; - qcom,calibration-type = "absolute"; - qcom,scale-function = <0>; - qcom,hw-settle-time = <0>; - qcom,btm-channel-number = <0x60>; - }; - - chan@4d { - label = "msm_therm"; - reg = <0x4d>; - qcom,pre-div-channel-scaling = <0>; - qcom,calibration-type = "ratiometric"; - qcom,scale-function = <2>; - qcom,hw-settle-time = <2>; - qcom,btm-channel-number = <0x68>; - qcom,thermal-node; - }; - - chan@51 { - label = "quiet_therm"; - reg = <0x51>; - qcom,pre-div-channel-scaling = <0>; - qcom,calibration-type = "ratiometric"; - qcom,scale-function = <2>; - qcom,hw-settle-time = <2>; - qcom,btm-channel-number = <0x70>; - qcom,thermal-node; - }; - - chan@4c { - label = "xo_therm"; - reg = <0x4c>; - qcom,pre-div-channel-scaling = <0>; - qcom,calibration-type = "ratiometric"; - qcom,scale-function = <4>; - qcom,hw-settle-time = <2>; - qcom,btm-channel-number = <0x78>; - qcom,thermal-node; - }; - }; - - pmfalcon_rradc: rradc@4500 { - compatible = "qcom,rradc"; - reg = <0x4500 0x100>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - }; - - pmfalcon_fg: qpnp,fg { - compatible = "qcom,fg-gen3"; - #address-cells = <1>; - #size-cells = <1>; - qcom,pmic-revid = <&pmfalcon_revid>; - io-channels = <&pmfalcon_rradc 0>; - io-channel-names = "rradc_batt_id"; - qcom,rradc-base = <0x4500>; - qcom,fg-esr-timer-awake = <96>; - qcom,fg-esr-timer-asleep = <256>; - qcom,cycle-counter-en; - status = "okay"; - - qcom,fg-batt-soc@4000 { - status = "okay"; - reg = <0x4000 0x100>; - interrupts = <0x0 0x40 0x0 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x40 0x1 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x40 0x2 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x40 0x3 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x40 0x4 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x40 0x5 - IRQ_TYPE_EDGE_RISING>, - <0x0 0x40 0x6 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x40 0x7 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "soc-update", - "soc-ready", - "bsoc-delta", - "msoc-delta", - "msoc-low", - "msoc-empty", - "msoc-high", - "msoc-full"; - }; - - qcom,fg-batt-info@4100 { - status = "okay"; - reg = <0x4100 0x100>; - interrupts = <0x0 0x41 0x0 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x41 0x1 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x41 0x2 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x41 0x3 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x41 0x6 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "vbatt-pred-delta", - "vbatt-low", - "esr-delta", - "batt-missing", - "batt-temp-delta"; - }; - - qcom,fg-memif@4400 { - status = "okay"; - reg = <0x4400 0x100>; - interrupts = <0x0 0x44 0x0 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x44 0x1 IRQ_TYPE_EDGE_BOTH>, - <0x0 0x44 0x2 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "ima-rdy", - "mem-xcp", - "dma-grant"; - }; - }; - - bcl@4200 { - compatible = "qcom,msm-bcl-lmh"; - reg = <0x4200 0xff>, - <0x4300 0xff>; - reg-names = "fg_user_adc", - "fg_lmh"; - interrupts = <0x0 0x42 0x0 IRQ_TYPE_NONE>, - <0x0 0x42 0x2 IRQ_TYPE_NONE>; - interrupt-names = "bcl-high-ibat-int", - "bcl-low-vbat-int"; - qcom,vbat-polling-delay-ms = <100>; - qcom,ibat-polling-delay-ms = <100>; - }; - }; - - qcom,pmfalcon@1 { - compatible ="qcom,spmi-pmic"; - reg = <0x1 SPMI_USID>; - #address-cells = <2>; - #size-cells = <0>; - - pmfalcon_haptics: qcom,haptic@c000 { - compatible = "qcom,qpnp-haptic"; - reg = <0xc000 0x100>; - interrupts = <0x1 0xc0 0x0>, - <0x1 0xc0 0x1>; - interrupt-names = "sc-irq", "play-irq"; - qcom,actuator-type = "lra"; - qcom,play-mode = "direct"; - qcom,vmax-mv = <3200>; - qcom,ilim-ma = <800>; - qcom,wave-shape = "square"; - qcom,wave-play-rate-us = <6667>; - qcom,int-pwm-freq-khz = <505>; - qcom,sc-deb-cycles = <8>; - qcom,en-brake; - qcom,brake-pattern = [03 03 00 00]; - qcom,use-play-irq; - qcom,use-sc-irq; - qcom,lra-high-z = "opt1"; - qcom,lra-auto-res-mode = "qwd"; - qcom,lra-res-cal-period = <4>; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-cdp.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-cdp.dtsi index 78ba56b3e3c2..52d0fdb4a523 100644 --- a/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-cdp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-cdp.dtsi @@ -45,18 +45,18 @@ led_flash0: qcom,camera-flash@0 { cell-index = <0>; compatible = "qcom,camera-flash"; - qcom,flash-source = <&pm2falcon_flash0 &pm2falcon_flash1>; - qcom,torch-source = <&pm2falcon_torch0 &pm2falcon_torch1>; - qcom,switch-source = <&pm2falcon_switch0>; + qcom,flash-source = <&pm660l_flash0 &pm660l_flash1>; + qcom,torch-source = <&pm660l_torch0 &pm660l_torch1>; + qcom,switch-source = <&pm660l_switch0>; status = "ok"; }; led_flash1: qcom,camera-flash@1 { cell-index = <1>; compatible = "qcom,camera-flash"; - qcom,flash-source = <&pm2falcon_flash2>; - qcom,torch-source = <&pm2falcon_torch2>; - qcom,switch-source = <&pm2falcon_switch1>; + qcom,flash-source = <&pm660l_flash2>; + qcom,torch-source = <&pm660l_torch2>; + qcom,switch-source = <&pm660l_switch1>; status = "ok"; }; @@ -77,9 +77,9 @@ qcom,csid@ca30000 { qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -91,9 +91,9 @@ qcom,csid@ca30400 { qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -105,9 +105,9 @@ qcom,csid@ca30800 { qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -119,9 +119,9 @@ qcom,csid@ca30c00 { qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -195,9 +195,9 @@ cell-index = <0>; reg = <0>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -212,7 +212,7 @@ &cam_actuator_vaf_suspend>; gpios = <&tlmm 13 0>, <&tlmm 30 0>, - <&pm2falcon_gpios 4 0>, + <&pm660l_gpios 4 0>, <&tlmm 8 0>, <&tlmm 27 0>; qcom,gpio-reset = <1>; @@ -240,9 +240,9 @@ cell-index = <2>; reg = <0x2>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -257,7 +257,7 @@ &cam_actuator_vaf_suspend>; gpios = <&tlmm 14 0>, <&tlmm 28 0>, - <&pmfalcon_gpios 3 0>, + <&pm660_gpios 3 0>, <&tlmm 29 0>, <&tlmm 27 0>; qcom,gpio-reset = <1>; @@ -292,9 +292,9 @@ qcom,actuator-src = <&actuator0>; qcom,ois-src = <&ois0>; qcom,eeprom-src = <&eeprom0>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -307,7 +307,7 @@ &cam_sensor_rear_suspend>; gpios = <&tlmm 13 0>, <&tlmm 30 0>, - <&pm2falcon_gpios 4 0>, + <&pm660l_gpios 4 0>, <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -335,9 +335,9 @@ qcom,csiphy-sd-index = <1>; qcom,csid-sd-index = <2>; qcom,mount-angle = <90>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -350,7 +350,7 @@ &cam_sensor_rear2_suspend>; gpios = <&tlmm 15 0>, <&tlmm 9 0>, - <&pm2falcon_gpios 3 0>, + <&pm660l_gpios 3 0>, <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -381,9 +381,9 @@ qcom,actuator-src = <&actuator1>; qcom,led-flash-src = <&led_flash1>; qcom,eeprom-src = <&eeprom2>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -396,7 +396,7 @@ &cam_sensor_front_suspend>; gpios = <&tlmm 14 0>, <&tlmm 28 0>, - <&pm2falcon_gpios 3 0>, + <&pm660l_gpios 3 0>, <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -418,7 +418,7 @@ }; }; -&pm2falcon_gpios { +&pm660l_gpios { gpio@c300 { /* GPIO4 -CAMERA SENSOR 0 VDIG*/ qcom,mode = <1>; /* Output */ qcom,pull = <5>; /* No Pull */ diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-mtp.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-mtp.dtsi index 78ba56b3e3c2..52d0fdb4a523 100644 --- a/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-mtp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-mtp.dtsi @@ -45,18 +45,18 @@ led_flash0: qcom,camera-flash@0 { cell-index = <0>; compatible = "qcom,camera-flash"; - qcom,flash-source = <&pm2falcon_flash0 &pm2falcon_flash1>; - qcom,torch-source = <&pm2falcon_torch0 &pm2falcon_torch1>; - qcom,switch-source = <&pm2falcon_switch0>; + qcom,flash-source = <&pm660l_flash0 &pm660l_flash1>; + qcom,torch-source = <&pm660l_torch0 &pm660l_torch1>; + qcom,switch-source = <&pm660l_switch0>; status = "ok"; }; led_flash1: qcom,camera-flash@1 { cell-index = <1>; compatible = "qcom,camera-flash"; - qcom,flash-source = <&pm2falcon_flash2>; - qcom,torch-source = <&pm2falcon_torch2>; - qcom,switch-source = <&pm2falcon_switch1>; + qcom,flash-source = <&pm660l_flash2>; + qcom,torch-source = <&pm660l_torch2>; + qcom,switch-source = <&pm660l_switch1>; status = "ok"; }; @@ -77,9 +77,9 @@ qcom,csid@ca30000 { qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -91,9 +91,9 @@ qcom,csid@ca30400 { qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -105,9 +105,9 @@ qcom,csid@ca30800 { qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -119,9 +119,9 @@ qcom,csid@ca30c00 { qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -195,9 +195,9 @@ cell-index = <0>; reg = <0>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -212,7 +212,7 @@ &cam_actuator_vaf_suspend>; gpios = <&tlmm 13 0>, <&tlmm 30 0>, - <&pm2falcon_gpios 4 0>, + <&pm660l_gpios 4 0>, <&tlmm 8 0>, <&tlmm 27 0>; qcom,gpio-reset = <1>; @@ -240,9 +240,9 @@ cell-index = <2>; reg = <0x2>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -257,7 +257,7 @@ &cam_actuator_vaf_suspend>; gpios = <&tlmm 14 0>, <&tlmm 28 0>, - <&pmfalcon_gpios 3 0>, + <&pm660_gpios 3 0>, <&tlmm 29 0>, <&tlmm 27 0>; qcom,gpio-reset = <1>; @@ -292,9 +292,9 @@ qcom,actuator-src = <&actuator0>; qcom,ois-src = <&ois0>; qcom,eeprom-src = <&eeprom0>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -307,7 +307,7 @@ &cam_sensor_rear_suspend>; gpios = <&tlmm 13 0>, <&tlmm 30 0>, - <&pm2falcon_gpios 4 0>, + <&pm660l_gpios 4 0>, <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -335,9 +335,9 @@ qcom,csiphy-sd-index = <1>; qcom,csid-sd-index = <2>; qcom,mount-angle = <90>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -350,7 +350,7 @@ &cam_sensor_rear2_suspend>; gpios = <&tlmm 15 0>, <&tlmm 9 0>, - <&pm2falcon_gpios 3 0>, + <&pm660l_gpios 3 0>, <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -381,9 +381,9 @@ qcom,actuator-src = <&actuator1>; qcom,led-flash-src = <&led_flash1>; qcom,eeprom-src = <&eeprom2>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -396,7 +396,7 @@ &cam_sensor_front_suspend>; gpios = <&tlmm 14 0>, <&tlmm 28 0>, - <&pm2falcon_gpios 3 0>, + <&pm660l_gpios 3 0>, <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -418,7 +418,7 @@ }; }; -&pm2falcon_gpios { +&pm660l_gpios { gpio@c300 { /* GPIO4 -CAMERA SENSOR 0 VDIG*/ qcom,mode = <1>; /* Output */ qcom,pull = <5>; /* No Pull */ diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-qrd.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-qrd.dtsi index d10c2a25b301..87b1146bd361 100644 --- a/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-qrd.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-qrd.dtsi @@ -115,9 +115,9 @@ qcom,csid@ca30000 { qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -129,9 +129,9 @@ qcom,csid@ca30400 { qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -143,9 +143,9 @@ qcom,csid@ca30800 { qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -157,9 +157,9 @@ qcom,csid@ca30c00 { qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -233,9 +233,9 @@ cell-index = <0>; reg = <0>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1750000 3300000 1352000>; qcom,cam-vreg-max-voltage = <1980000 3600000 1352000>; @@ -248,7 +248,7 @@ &cam_sensor_rear_suspend>; gpios = <&tlmm 13 0>, <&tlmm 9 0>, - <&pm2falcon_gpios 4 0>, + <&pm660l_gpios 4 0>, <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -273,9 +273,9 @@ cell-index = <1>; reg = <0x1>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1750000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1980000 3600000 1350000>; @@ -288,7 +288,7 @@ &cam_sensor_rear2_suspend>; gpios = <&tlmm 15 0>, <&tlmm 30 0>, - <&pm2falcon_gpios 4 0>, + <&pm660l_gpios 4 0>, <&tlmm 8 0>, <&tlmm 27 0>; qcom,gpio-reset = <1>; @@ -316,9 +316,9 @@ cell-index = <2>; reg = <0x2>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 33000000 1352000>; qcom,cam-vreg-max-voltage = <1950000 36000000 1352000>; @@ -331,7 +331,7 @@ &cam_sensor_front_suspend>; gpios = <&tlmm 14 0>, <&tlmm 28 0>, - <&pm2falcon_gpios 3 0>, + <&pm660l_gpios 3 0>, <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -362,9 +362,9 @@ qcom,actuator-src = <&actuator0>; /*qcom,ois-src = <&ois0>;*/ qcom,eeprom-src = <&eeprom0>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -377,7 +377,7 @@ &cam_sensor_rear_suspend>; gpios = <&tlmm 13 0>, <&tlmm 9 0>, - <&pm2falcon_gpios 4 0>, + <&pm660l_gpios 4 0>, <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -407,9 +407,9 @@ qcom,mount-angle = <90>; qcom,actuator-src = <&actuator1>; qcom,eeprom-src = <&eeprom1>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -422,7 +422,7 @@ &cam_sensor_rear2_suspend>; gpios = <&tlmm 15 0>, <&tlmm 30 0>, - <&pm2falcon_gpios 4 0>, + <&pm660l_gpios 4 0>, <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -451,9 +451,9 @@ qcom,csid-sd-index = <2>; qcom,mount-angle = <270>; /*qcom,eeprom-src = <&eeprom2>;*/ - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -466,7 +466,7 @@ &cam_sensor_front_suspend>; gpios = <&tlmm 14 0>, <&tlmm 28 0>, - <&pm2falcon_gpios 3 0>, + <&pm660l_gpios 3 0>, <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -488,7 +488,7 @@ }; }; -&pm2falcon_gpios { +&pm660l_gpios { gpio@c300 { /* GPIO4 -CAMERA SENSOR 0 VDIG*/ qcom,mode = <1>; /* Output */ qcom,pull = <5>; /* No Pull */ diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-audio.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-audio.dtsi deleted file mode 100644 index b05707c6c585..000000000000 --- a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-audio.dtsi +++ /dev/null @@ -1,69 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "msm-audio.dtsi" -#include "msmfalcon-audio.dtsi" - -&pm2falcon_3 { - /delete-node/analog-codec; -}; - -&soc { - /delete-node/msm-sdw-codec@152c1000; - /delete-node/sound; -}; - -&slim_aud { - tasha_codec { - clocks = <&clock_audio clk_audio_pmi_clk>, - <&clock_audio clk_audio_ap_clk2>; - }; - tavil_codec { - clocks = <&clock_audio_lnbb clk_audio_pmi_lnbb_clk>; - }; -}; - -&tasha_hph_en0 { - /delete-property/pinctrl-0; - /delete-property/pinctrl-1; -}; - -&tasha_hph_en1 { - /delete-property/pinctrl-0; - /delete-property/pinctrl-1; -}; - -&clock_audio { - qcom,audio-ref-clk-gpio = <&pmfalcon_gpios 3 0>; - clocks = <&clock_gcc clk_div_clk1>; - pinctrl-0 = <&spkr_i2s_clk_sleep>; - pinctrl-1 = <&spkr_i2s_clk_active>; -}; - -&clock_audio_lnbb { - clocks = <&clock_gcc clk_ln_bb_clk2>; -}; - -&wcd_rst_gpio { - qcom,cdc-rst-n-gpio = <&tlmm 64 0>; - pinctrl-0 = <&cdc_reset_active>; - pinctrl-1 = <&cdc_reset_sleep>; -}; - -&wcd9xxx_intc { - interrupt-parent = <&tlmm>; - qcom,gpio-connect = <&tlmm 54 0>; - pinctrl-names = "default"; - pinctrl-0 = <&wcd_intr_default>; - /delete-property/interrupts; - /delete-property/interrupt-names; -}; diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-cdp.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-cdp.dtsi deleted file mode 100644 index 292bc07c679a..000000000000 --- a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-cdp.dtsi +++ /dev/null @@ -1,512 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "msm8998-pinctrl.dtsi" -#include "msm8998-camera-sensor-cdp.dtsi" - -&blsp1_uart3_hs { - status = "ok"; -}; - -&ufsphy1 { - vdda-phy-supply = <&pm2falcon_l1>; - vdda-pll-supply = <&pmfalcon_l1>; - vddp-ref-clk-supply = <&pmfalcon_l1>; - vdda-phy-max-microamp = <51400>; - vdda-pll-max-microamp = <14600>; - vddp-ref-clk-max-microamp = <100>; - vddp-ref-clk-always-on; - status = "ok"; -}; - -&ufs1 { - vdd-hba-supply = <&gdsc_ufs>; - vdd-hba-fixed-regulator; - vcc-supply = <&pm2falcon_l4>; - vccq2-supply = <&pmfalcon_l8>; - vcc-max-microamp = <500000>; - vccq2-max-microamp = <600000>; - status = "ok"; -}; - -&ufs_ice { - status = "ok"; -}; - -&sdhc_2 { - vdd-supply = <&pm2falcon_l5>; - qcom,vdd-voltage-level = <2950000 2950000>; - qcom,vdd-current-level = <200 800000>; - - vdd-io-supply = <&pm2falcon_l2>; - qcom,vdd-io-voltage-level = <1800000 2950000>; - qcom,vdd-io-current-level = <200 22000>; - - pinctrl-names = "active", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - - qcom,clk-rates = <400000 20000000 25000000 - 50000000 100000000 200000000>; - qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; - - cd-gpios = <&tlmm 95 0x1>; - - status = "ok"; -}; - -&uartblsp2dm1 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&uart_console_active>; -}; - -&pm8998_gpios { - /* GPIO 5 for Home Key */ - gpio@c400 { - status = "okay"; - qcom,mode = <0>; - qcom,pull = <0>; - qcom,vin-sel = <0>; - qcom,src-sel = <0>; - qcom,out-strength = <1>; - }; - - /* GPIO 6 for Vol+ Key */ - gpio@c500 { - status = "okay"; - qcom,mode = <0>; - qcom,pull = <0>; - qcom,vin-sel = <0>; - qcom,src-sel = <0>; - qcom,out-strength = <1>; - }; - - /* GPIO 7 for Snapshot Key */ - gpio@c600 { - status = "okay"; - qcom,mode = <0>; - qcom,pull = <0>; - qcom,vin-sel = <0>; - qcom,src-sel = <0>; - qcom,out-strength = <1>; - }; - - /* GPIO 8 for Focus Key */ - gpio@c700 { - status = "okay"; - qcom,mode = <0>; - qcom,pull = <0>; - qcom,vin-sel = <0>; - qcom,src-sel = <0>; - qcom,out-strength = <1>; - }; - - gpio@cc00 { /* GPIO 13 */ - qcom,mode = <1>; - qcom,output-type = <0>; - qcom,pull = <5>; - qcom,vin-sel = <0>; - qcom,out-strength = <1>; - qcom,src-sel = <3>; - qcom,master-en = <1>; - status = "okay"; - }; - - /* GPIO 21 (NFC_CLK_REQ) */ - gpio@d400 { - qcom,mode = <0>; - qcom,vin-sel = <1>; - qcom,src-sel = <0>; - qcom,master-en = <1>; - status = "okay"; - }; -}; - -&i2c_5 { - status = "okay"; - synaptics@20 { - compatible = "synaptics,dsx"; - reg = <0x20>; - interrupt-parent = <&tlmm>; - interrupts = <125 0x2008>; - vdd-supply = <&pm8998_l6>; - avdd-supply = <&pm8998_l28>; - synaptics,vdd-voltage = <1808000 1808000>; - synaptics,avdd-voltage = <3008000 3008000>; - synaptics,vdd-current = <40000>; - synaptics,avdd-current = <20000>; - pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; - pinctrl-0 = <&ts_active>; - pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; - synaptics,display-coords = <0 0 1439 2559>; - synaptics,panel-coords = <0 0 1439 2559>; - synaptics,reset-gpio = <&tlmm 89 0x00>; - synaptics,irq-gpio = <&tlmm 125 0x2008>; - synaptics,disable-gpios; - synaptics,fw-name = "PR1702898-s3528t_60QHD_00400001.img"; - }; -}; - -&i2c_6 { /* BLSP1 QUP6 (NFC) */ - status = "okay"; - nq@28 { - compatible = "qcom,nq-nci"; - reg = <0x28>; - qcom,nq-irq = <&tlmm 92 0x00>; - qcom,nq-ven = <&tlmm 12 0x00>; - qcom,nq-firm = <&tlmm 93 0x00>; - qcom,nq-clkreq = <&pm8998_gpios 21 0x00>; - qcom,nq-esepwr = <&tlmm 116 0x00>; - interrupt-parent = <&tlmm>; - qcom,clk-src = "BBCLK3"; - interrupts = <92 0>; - interrupt-names = "nfc_irq"; - pinctrl-names = "nfc_active", "nfc_suspend"; - pinctrl-0 = <&nfc_int_active &nfc_enable_active>; - pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; - clocks = <&clock_gcc clk_ln_bb_clk3_pin>; - clock-names = "ref_clk"; - }; -}; - -&mdss_mdp { - qcom,mdss-pref-prim-intf = "dsi"; -}; - -&mdss_dsi { - hw-config = "split_dsi"; - vdda-1p2-supply = <&pmfalcon_l1>; - vdda-0p9-supply = <&pm2falcon_l1>; -}; - -&mdss_dsi0 { - qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; - wqhd-vddio-supply = <&pmfalcon_l11>; - lab-supply = <&lcdb_ldo_vreg>; - ibb-supply = <&lcdb_ncp_vreg>; - pinctrl-names = "mdss_default", "mdss_sleep"; - pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; - pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; - qcom,platform-reset-gpio = <&tlmm 94 0>; - qcom,platform-te-gpio = <&tlmm 10 0>; - qcom,panel-mode-gpio = <&tlmm 91 0>; -}; - -&mdss_dsi1 { - qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; - wqhd-vddio-supply = <&pmfalcon_l11>; - lab-supply = <&lcdb_ldo_vreg>; - ibb-supply = <&lcdb_ncp_vreg>; - pinctrl-names = "mdss_default", "mdss_sleep"; - pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; - pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; - qcom,platform-reset-gpio = <&tlmm 94 0>; - qcom,platform-te-gpio = <&tlmm 10 0>; - qcom,panel-mode-gpio = <&tlmm 91 0>; -}; - -&labibb { - status = "ok"; - qpnp,qpnp-labibb-mode = "lcd"; -}; - -&pmi8998_wled { - qcom,led-strings-list = [00 01]; -}; - -&dsi_dual_nt35597_video { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&dsi_dual_nt35597_cmd { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&dsi_dual_nt35597_truly_video { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&dsi_dual_nt35597_truly_cmd { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&dsi_nt35597_dsc_video { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&dsi_nt35597_dsc_cmd { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&dsi_sharp_4k_dsc_video { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&dsi_sharp_4k_dsc_cmd { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&dsi_dual_jdi_video { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,5v-boost-gpio = <&tlmm 51 0>; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&dsi_dual_jdi_cmd { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,5v-boost-gpio = <&tlmm 51 0>; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,partial-update-enabled; - qcom,panel-roi-alignment = <4 2 4 2 20 20>; -}; - -&dsi_sharp_1080_cmd { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&dsi_jdi_1080_vid { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; - qcom,5v-boost-gpio = <&tlmm 51 0>; -}; - -&dsi_dual_sharp_1080_120hz_cmd { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&mdss_hdmi_tx { - pinctrl-names = "hdmi_hpd_active", "hdmi_ddc_active", "hdmi_cec_active", - "hdmi_active", "hdmi_sleep"; - pinctrl-0 = <&mdss_hdmi_5v_active &mdss_hdmi_hpd_active - &mdss_hdmi_ddc_suspend &mdss_hdmi_cec_suspend>; - pinctrl-1 = <&mdss_hdmi_5v_active &mdss_hdmi_hpd_active - &mdss_hdmi_ddc_active &mdss_hdmi_cec_suspend>; - pinctrl-2 = <&mdss_hdmi_5v_active &mdss_hdmi_hpd_active - &mdss_hdmi_cec_active &mdss_hdmi_ddc_suspend>; - pinctrl-3 = <&mdss_hdmi_5v_active &mdss_hdmi_hpd_active - &mdss_hdmi_ddc_active &mdss_hdmi_cec_active>; - pinctrl-4 = <&mdss_hdmi_5v_suspend &mdss_hdmi_hpd_suspend - &mdss_hdmi_ddc_suspend &mdss_hdmi_cec_suspend>; -}; - -&mdss_dp_ctrl { - vdda-1p2-supply = <&pmfalcon_l1>; - vdda-0p9-supply = <&pm2falcon_l1>; - pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; - pinctrl-0 = <&mdss_dp_aux_active &mdss_dp_usbplug_cc_active>; - pinctrl-1 = <&mdss_dp_aux_suspend &mdss_dp_usbplug_cc_suspend>; - qcom,aux-en-gpio = <&tlmm 77 0>; - qcom,aux-sel-gpio = <&tlmm 78 0>; - qcom,usbplug-cc-gpio = <&tlmm 38 0>; -}; - -&pmi8998_charger { - qcom,batteryless-platform; -}; - -&pmi8998_haptics { - status = "okay"; -}; - -&pm8998_vadc { - chan@83 { - label = "vph_pwr"; - reg = <0x83>; - qcom,decimation = <2>; - qcom,pre-div-channel-scaling = <1>; - qcom,calibration-type = "absolute"; - qcom,scale-function = <0>; - qcom,hw-settle-time = <0>; - qcom,fast-avg-setup = <0>; - }; - - chan@85 { - label = "vcoin"; - reg = <0x85>; - qcom,decimation = <2>; - qcom,pre-div-channel-scaling = <1>; - qcom,calibration-type = "absolute"; - qcom,scale-function = <0>; - qcom,hw-settle-time = <0>; - qcom,fast-avg-setup = <0>; - }; - - chan@4c { - label = "xo_therm"; - reg = <0x4c>; - qcom,decimation = <2>; - qcom,pre-div-channel-scaling = <0>; - qcom,calibration-type = "ratiometric"; - qcom,scale-function = <4>; - qcom,hw-settle-time = <2>; - qcom,fast-avg-setup = <0>; - }; - - chan@4d { - label = "msm_therm"; - reg = <0x4d>; - qcom,decimation = <2>; - qcom,pre-div-channel-scaling = <0>; - qcom,calibration-type = "ratiometric"; - qcom,scale-function = <2>; - qcom,hw-settle-time = <2>; - qcom,fast-avg-setup = <0>; - }; - - chan@51 { - label = "quiet_therm"; - reg = <0x51>; - qcom,decimation = <2>; - qcom,pre-div-channel-scaling = <0>; - qcom,calibration-type = "ratiometric"; - qcom,scale-function = <2>; - qcom,hw-settle-time = <2>; - qcom,fast-avg-setup = <0>; - }; -}; - -&pm8998_adc_tm { - chan@83 { - label = "vph_pwr"; - reg = <0x83>; - qcom,pre-div-channel-scaling = <1>; - qcom,calibration-type = "absolute"; - qcom,scale-function = <0>; - qcom,hw-settle-time = <0>; - qcom,btm-channel-number = <0x60>; - }; - - chan@4d { - label = "msm_therm"; - reg = <0x4d>; - qcom,pre-div-channel-scaling = <0>; - qcom,calibration-type = "ratiometric"; - qcom,scale-function = <2>; - qcom,hw-settle-time = <2>; - qcom,btm-channel-number = <0x68>; - qcom,thermal-node; - }; - - chan@51 { - label = "quiet_therm"; - reg = <0x51>; - qcom,pre-div-channel-scaling = <0>; - qcom,calibration-type = "ratiometric"; - qcom,scale-function = <2>; - qcom,hw-settle-time = <2>; - qcom,btm-channel-number = <0x70>; - qcom,thermal-node; - }; - - chan@4c { - label = "xo_therm"; - reg = <0x4c>; - qcom,pre-div-channel-scaling = <0>; - qcom,calibration-type = "ratiometric"; - qcom,scale-function = <4>; - qcom,hw-settle-time = <2>; - qcom,btm-channel-number = <0x78>; - qcom,thermal-node; - }; -}; - -&wil6210 { - status = "ok"; -}; - -&soc { - gpio_keys { - compatible = "gpio-keys"; - input-name = "gpio-keys"; - status = "okay"; - - home { - label = "home"; - gpios = <&pm8998_gpios 5 0x1>; - linux,input-type = <1>; - linux,code = <102>; - gpio-key,wakeup; - debounce-interval = <15>; - - }; - - vol_up { - label = "volume_up"; - gpios = <&pm8998_gpios 6 0x1>; - linux,input-type = <1>; - linux,code = <115>; - gpio-key,wakeup; - debounce-interval = <15>; - }; - - cam_snapshot { - label = "cam_snapshot"; - gpios = <&pm8998_gpios 7 0x1>; - linux,input-type = <1>; - linux,code = <766>; - gpio-key,wakeup; - debounce-interval = <15>; - }; - - cam_focus { - label = "cam_focus"; - gpios = <&pm8998_gpios 8 0x1>; - linux,input-type = <1>; - linux,code = <528>; - gpio-key,wakeup; - debounce-interval = <15>; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-mtp.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-mtp.dtsi deleted file mode 100644 index 9a1e148c46a0..000000000000 --- a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-mtp.dtsi +++ /dev/null @@ -1,505 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include "msm8998-pinctrl.dtsi" -#include "msm8998-camera-sensor-mtp.dtsi" - -&blsp1_uart3_hs { - status = "ok"; -}; - -&ufsphy1 { - vdda-phy-supply = <&pm2falcon_l1>; - vdda-pll-supply = <&pmfalcon_l1>; - vddp-ref-clk-supply = <&pmfalcon_l1>; - vdda-phy-max-microamp = <51400>; - vdda-pll-max-microamp = <14600>; - vddp-ref-clk-max-microamp = <100>; - vddp-ref-clk-always-on; - status = "ok"; -}; - -&ufs1 { - vdd-hba-supply = <&gdsc_ufs>; - vdd-hba-fixed-regulator; - vcc-supply = <&pm2falcon_l4>; - vccq2-supply = <&pmfalcon_l8>; - vcc-max-microamp = <500000>; - vccq2-max-microamp = <600000>; - status = "ok"; -}; - -&ufs_ice { - status = "ok"; -}; - -&sdhc_2 { - vdd-supply = <&pm2falcon_l5>; - qcom,vdd-voltage-level = <2950000 2950000>; - qcom,vdd-current-level = <200 800000>; - - vdd-io-supply = <&pm2falcon_l2>; - qcom,vdd-io-voltage-level = <1800000 2950000>; - qcom,vdd-io-current-level = <200 22000>; - - pinctrl-names = "active", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - - qcom,clk-rates = <400000 20000000 25000000 - 50000000 100000000 200000000>; - qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; - - cd-gpios = <&tlmm 95 0x1>; - - status = "ok"; -}; - -&uartblsp2dm1 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&uart_console_active>; -}; - -&pm8998_gpios { - /* GPIO 6 for Vol+ Key */ - gpio@c500 { - status = "okay"; - qcom,mode = <0>; - qcom,pull = <0>; - qcom,vin-sel = <0>; - qcom,src-sel = <0>; - qcom,out-strength = <1>; - }; - - /* GPIO 7 for Snapshot Key */ - gpio@c600 { - status = "okay"; - qcom,mode = <0>; - qcom,pull = <0>; - qcom,vin-sel = <0>; - qcom,src-sel = <0>; - qcom,out-strength = <1>; - }; - - /* GPIO 8 for Focus Key */ - gpio@c700 { - status = "okay"; - qcom,mode = <0>; - qcom,pull = <0>; - qcom,vin-sel = <0>; - qcom,src-sel = <0>; - qcom,out-strength = <1>; - }; - - gpio@cc00 { /* GPIO 13 */ - qcom,mode = <1>; - qcom,output-type = <0>; - qcom,pull = <5>; - qcom,vin-sel = <0>; - qcom,out-strength = <1>; - qcom,src-sel = <3>; - qcom,master-en = <1>; - status = "okay"; - }; - - /* GPIO 21 (NFC_CLK_REQ) */ - gpio@d400 { - qcom,mode = <0>; - qcom,vin-sel = <1>; - qcom,src-sel = <0>; - qcom,master-en = <1>; - status = "okay"; - }; - - /* GPIO 18 SMB138X */ - gpio@d100 { - qcom,mode = <0>; - qcom,pull = <0>; - qcom,vin-sel = <0>; - qcom,src-sel = <0>; - qcom,master-en = <1>; - status = "okay"; - }; -}; - -&i2c_5 { - status = "okay"; - synaptics@20 { - compatible = "synaptics,dsx"; - reg = <0x20>; - interrupt-parent = <&tlmm>; - interrupts = <125 0x2008>; - vdd-supply = <&pm8998_l6>; - avdd-supply = <&pm8998_l28>; - synaptics,vdd-voltage = <1808000 1808000>; - synaptics,avdd-voltage = <3008000 3008000>; - synaptics,vdd-current = <40000>; - synaptics,avdd-current = <20000>; - pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; - pinctrl-0 = <&ts_active>; - pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; - synaptics,display-coords = <0 0 1439 2559>; - synaptics,panel-coords = <0 0 1439 2559>; - synaptics,reset-gpio = <&tlmm 89 0x00>; - synaptics,irq-gpio = <&tlmm 125 0x2008>; - synaptics,disable-gpios; - synaptics,fw-name = "PR1702898-s3528t_60QHD_00400001.img"; - }; -}; - -&i2c_6 { /* BLSP1 QUP6 (NFC) */ - status = "okay"; - nq@28 { - compatible = "qcom,nq-nci"; - reg = <0x28>; - qcom,nq-irq = <&tlmm 92 0x00>; - qcom,nq-ven = <&tlmm 12 0x00>; - qcom,nq-firm = <&tlmm 93 0x00>; - qcom,nq-clkreq = <&pm8998_gpios 21 0x00>; - qcom,nq-esepwr = <&tlmm 116 0x00>; - interrupt-parent = <&tlmm>; - qcom,clk-src = "BBCLK3"; - interrupts = <92 0>; - interrupt-names = "nfc_irq"; - pinctrl-names = "nfc_active", "nfc_suspend"; - pinctrl-0 = <&nfc_int_active &nfc_enable_active>; - pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; - clocks = <&clock_gcc clk_ln_bb_clk3_pin>; - clock-names = "ref_clk"; - }; -}; - -&mdss_hdmi_tx { - pinctrl-names = "hdmi_hpd_active", "hdmi_ddc_active", "hdmi_cec_active", - "hdmi_active", "hdmi_sleep"; - pinctrl-0 = <&mdss_hdmi_5v_active &mdss_hdmi_hpd_active - &mdss_hdmi_ddc_suspend &mdss_hdmi_cec_suspend>; - pinctrl-1 = <&mdss_hdmi_5v_active &mdss_hdmi_hpd_active - &mdss_hdmi_ddc_active &mdss_hdmi_cec_suspend>; - pinctrl-2 = <&mdss_hdmi_5v_active &mdss_hdmi_hpd_active - &mdss_hdmi_cec_active &mdss_hdmi_ddc_suspend>; - pinctrl-3 = <&mdss_hdmi_5v_active &mdss_hdmi_hpd_active - &mdss_hdmi_ddc_active &mdss_hdmi_cec_active>; - pinctrl-4 = <&mdss_hdmi_5v_suspend &mdss_hdmi_hpd_suspend - &mdss_hdmi_ddc_suspend &mdss_hdmi_cec_suspend>; -}; - -&mdss_dp_ctrl { - vdda-1p2-supply = <&pmfalcon_l1>; - vdda-0p9-supply = <&pm2falcon_l1>; - pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; - pinctrl-0 = <&mdss_dp_aux_active &mdss_dp_usbplug_cc_active>; - pinctrl-1 = <&mdss_dp_aux_suspend &mdss_dp_usbplug_cc_suspend>; - qcom,aux-en-gpio = <&tlmm 77 0>; - qcom,aux-sel-gpio = <&tlmm 78 0>; - qcom,usbplug-cc-gpio = <&tlmm 38 0>; -}; - -&mdss_mdp { - qcom,mdss-pref-prim-intf = "dsi"; -}; - -&mdss_dsi { - hw-config = "split_dsi"; - vdda-1p2-supply = <&pmfalcon_l1>; - vdda-0p9-supply = <&pm2falcon_l1>; -}; - -&mdss_dsi0 { - qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; - wqhd-vddio-supply = <&pmfalcon_l11>; - lab-supply = <&lcdb_ldo_vreg>; - ibb-supply = <&lcdb_ncp_vreg>; - pinctrl-names = "mdss_default", "mdss_sleep"; - pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; - pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; - qcom,platform-reset-gpio = <&tlmm 94 0>; - qcom,platform-te-gpio = <&tlmm 10 0>; - qcom,panel-mode-gpio = <&tlmm 91 0>; -}; - -&mdss_dsi1 { - qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; - wqhd-vddio-supply = <&pmfalcon_l11>; - lab-supply = <&lcdb_ldo_vreg>; - ibb-supply = <&lcdb_ncp_vreg>; - pinctrl-names = "mdss_default", "mdss_sleep"; - pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; - pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; - qcom,platform-reset-gpio = <&tlmm 94 0>; - qcom,platform-te-gpio = <&tlmm 10 0>; - qcom,panel-mode-gpio = <&tlmm 91 0>; -}; - -&labibb { - status = "ok"; - qpnp,qpnp-labibb-mode = "lcd"; -}; - -&pmi8998_wled { - qcom,led-strings-list = [00 01]; -}; - -&dsi_dual_nt35597_video { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&dsi_dual_nt35597_cmd { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&dsi_dual_nt35597_truly_video { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&dsi_dual_nt35597_truly_cmd { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&dsi_nt35597_dsc_video { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&dsi_nt35597_dsc_cmd { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&dsi_sharp_4k_dsc_video { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&dsi_sharp_4k_dsc_cmd { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&dsi_dual_jdi_video { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,5v-boost-gpio = <&tlmm 51 0>; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&dsi_dual_jdi_cmd { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,5v-boost-gpio = <&tlmm 51 0>; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&dsi_sharp_1080_cmd { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&dsi_jdi_1080_vid { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; - qcom,5v-boost-gpio = <&tlmm 51 0>; -}; - -&dsi_dual_sharp_1080_120hz_cmd { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&pmi8998_haptics { - status = "okay"; -}; - -&pm8998_vadc { - chan@83 { - label = "vph_pwr"; - reg = <0x83>; - qcom,decimation = <2>; - qcom,pre-div-channel-scaling = <1>; - qcom,calibration-type = "absolute"; - qcom,scale-function = <0>; - qcom,hw-settle-time = <0>; - qcom,fast-avg-setup = <0>; - }; - - chan@85 { - label = "vcoin"; - reg = <0x85>; - qcom,decimation = <2>; - qcom,pre-div-channel-scaling = <1>; - qcom,calibration-type = "absolute"; - qcom,scale-function = <0>; - qcom,hw-settle-time = <0>; - qcom,fast-avg-setup = <0>; - }; - - chan@4c { - label = "xo_therm"; - reg = <0x4c>; - qcom,decimation = <2>; - qcom,pre-div-channel-scaling = <0>; - qcom,calibration-type = "ratiometric"; - qcom,scale-function = <4>; - qcom,hw-settle-time = <2>; - qcom,fast-avg-setup = <0>; - }; - - chan@4d { - label = "msm_therm"; - reg = <0x4d>; - qcom,decimation = <2>; - qcom,pre-div-channel-scaling = <0>; - qcom,calibration-type = "ratiometric"; - qcom,scale-function = <2>; - qcom,hw-settle-time = <2>; - qcom,fast-avg-setup = <0>; - }; - - chan@51 { - label = "quiet_therm"; - reg = <0x51>; - qcom,decimation = <2>; - qcom,pre-div-channel-scaling = <0>; - qcom,calibration-type = "ratiometric"; - qcom,scale-function = <2>; - qcom,hw-settle-time = <2>; - qcom,fast-avg-setup = <0>; - }; -}; - -&pm8998_adc_tm { - chan@83 { - label = "vph_pwr"; - reg = <0x83>; - qcom,pre-div-channel-scaling = <1>; - qcom,calibration-type = "absolute"; - qcom,scale-function = <0>; - qcom,hw-settle-time = <0>; - qcom,btm-channel-number = <0x60>; - }; - - chan@4d { - label = "msm_therm"; - reg = <0x4d>; - qcom,pre-div-channel-scaling = <0>; - qcom,calibration-type = "ratiometric"; - qcom,scale-function = <2>; - qcom,hw-settle-time = <2>; - qcom,btm-channel-number = <0x68>; - qcom,thermal-node; - }; - - chan@51 { - label = "quiet_therm"; - reg = <0x51>; - qcom,pre-div-channel-scaling = <0>; - qcom,calibration-type = "ratiometric"; - qcom,scale-function = <2>; - qcom,hw-settle-time = <2>; - qcom,btm-channel-number = <0x70>; - qcom,thermal-node; - }; - - chan@4c { - label = "xo_therm"; - reg = <0x4c>; - qcom,pre-div-channel-scaling = <0>; - qcom,calibration-type = "ratiometric"; - qcom,scale-function = <4>; - qcom,hw-settle-time = <2>; - qcom,btm-channel-number = <0x78>; - qcom,thermal-node; - }; -}; - -&wil6210 { - status = "ok"; -}; - -&soc { - gpio_keys { - compatible = "gpio-keys"; - input-name = "gpio-keys"; - status = "okay"; - - vol_up { - label = "volume_up"; - gpios = <&pm8998_gpios 6 0x1>; - linux,input-type = <1>; - linux,code = <115>; - gpio-key,wakeup; - debounce-interval = <15>; - }; - - cam_snapshot { - label = "cam_snapshot"; - gpios = <&pm8998_gpios 7 0x1>; - linux,input-type = <1>; - linux,code = <766>; - gpio-key,wakeup; - debounce-interval = <15>; - }; - - cam_focus { - label = "cam_focus"; - gpios = <&pm8998_gpios 8 0x1>; - linux,input-type = <1>; - linux,code = <528>; - gpio-key,wakeup; - debounce-interval = <15>; - }; - }; -}; - -/{ - mtp_batterydata: qcom,battery-data { - qcom,batt-id-range-pct = <15>; - #include "fg-gen3-batterydata-itech-3000mah.dtsi" - #include "fg-gen3-batterydata-ascent-3450mah.dtsi" - }; -}; diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon.dtsi deleted file mode 100644 index 347b924749fd..000000000000 --- a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon.dtsi +++ /dev/null @@ -1,3154 +0,0 @@ -/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "skeleton64.dtsi" -#include -#include -#include - -/ { - model = "Qualcomm Technologies, Inc. MSM 8998"; - compatible = "qcom,msm8998"; - qcom,msm-id = <292 0x0>; - interrupt-parent = <&intc>; - - aliases { - serial0 = &uartblsp2dm1; - pci-domain0 = &pcie0; - sdhc2 = &sdhc_2; /* SDC2 SD card slot */ - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - chosen { - stdout-path = "serial0"; - bootargs = "rcupdate.rcu_expedited=1"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x0>; - qcom,limits-info = <&mitigation_profile0>; - qcom,lmh-dcvs = <&lmh_dcvs0>; - enable-method = "psci"; - efficiency = <1024>; - next-level-cache = <&L2_0>; - qcom,ea = <&ea0>; - L2_0: l2-cache { - compatible = "arm,arch-cache"; - cache-level = <2>; - /* A53 L2 dump not supported */ - qcom,dump-size = <0x0>; - }; - L1_I_0: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9040>; - }; - L1_D_0: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9040>; - }; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x1>; - qcom,limits-info = <&mitigation_profile1>; - qcom,lmh-dcvs = <&lmh_dcvs0>; - enable-method = "psci"; - efficiency = <1024>; - next-level-cache = <&L2_0>; - qcom,ea = <&ea1>; - L1_I_1: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9040>; - }; - L1_D_1: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9040>; - }; - }; - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x2>; - qcom,limits-info = <&mitigation_profile2>; - qcom,lmh-dcvs = <&lmh_dcvs0>; - enable-method = "psci"; - efficiency = <1024>; - next-level-cache = <&L2_0>; - qcom,ea = <&ea2>; - L1_I_2: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9040>; - }; - L1_D_2: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9040>; - }; - }; - - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x3>; - qcom,limits-info = <&mitigation_profile3>; - qcom,lmh-dcvs = <&lmh_dcvs0>; - enable-method = "psci"; - efficiency = <1024>; - next-level-cache = <&L2_0>; - qcom,ea = <&ea3>; - L1_I_3: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9040>; - }; - L1_D_3: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9040>; - }; - }; - - CPU4: cpu@100 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x100>; - qcom,limits-info = <&mitigation_profile4>; - qcom,lmh-dcvs = <&lmh_dcvs1>; - enable-method = "psci"; - efficiency = <1536>; - next-level-cache = <&L2_1>; - qcom,ea = <&ea4>; - L2_1: l2-cache { - compatible = "arm,arch-cache"; - cache-level = <2>; - }; - L1_I_100: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x12000>; - }; - L1_D_100: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x12000>; - }; - }; - - CPU5: cpu@101 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x101>; - qcom,limits-info = <&mitigation_profile5>; - qcom,lmh-dcvs = <&lmh_dcvs1>; - enable-method = "psci"; - efficiency = <1536>; - next-level-cache = <&L2_1>; - qcom,ea = <&ea5>; - L1_I_101: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x12000>; - }; - L1_D_101: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x12000>; - }; - }; - - CPU6: cpu@102 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x102>; - qcom,limits-info = <&mitigation_profile6>; - qcom,lmh-dcvs = <&lmh_dcvs1>; - enable-method = "psci"; - efficiency = <1536>; - next-level-cache = <&L2_1>; - qcom,ea = <&ea6>; - L1_I_102: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x12000>; - }; - L1_D_102: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x12000>; - }; - }; - - CPU7: cpu@103 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x103>; - qcom,limits-info = <&mitigation_profile7>; - qcom,lmh-dcvs = <&lmh_dcvs1>; - enable-method = "psci"; - efficiency = <1536>; - next-level-cache = <&L2_1>; - qcom,ea = <&ea7>; - L1_I_103: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x12000>; - }; - L1_D_103: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x12000>; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - }; - - cluster1 { - core0 { - cpu = <&CPU4>; - }; - - core1 { - cpu = <&CPU5>; - }; - - core2 { - cpu = <&CPU6>; - }; - - core3 { - cpu = <&CPU7>; - }; - }; - }; - }; - - soc: soc { }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - removed_regions: removed_regions@85800000 { - compatible = "removed-dma-pool"; - no-map; - reg = <0 0x85800000 0 0x3700000>; - }; - - pil_slpi_mem: pil_slpi_region@93800000 { - compatible = "removed-dma-pool"; - no-map; - reg = <0 0x93800000 0 0xf00000>; - }; - - pil_video_mem: pil_video_region@93300000 { - compatible = "removed-dma-pool"; - no-map; - reg = <0 0x93300000 0 0x500000>; - }; - - pil_adsp_mem: pil_adsp_region@91900000 { - compatible = "removed-dma-pool"; - no-map; - reg = <0 0x91900000 0 0x1a00000>; - }; - - modem_mem: modem_region@8ac00000 { - compatible = "removed-dma-pool"; - no-map; - reg = <0 0x8ac00000 0 0x6d00000>; - }; - - spss_mem: spss_region@8ab00000 { /* for SPSS-PIL */ - compatible = "removed-dma-pool"; - no-map; - reg = <0 0x8ab00000 0 0x100000>; - }; - - adsp_mem: adsp_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0 0x00000000 0 0xffffffff>; - reusable; - alignment = <0 0x400000>; - size = <0 0x800000>; - }; - - qseecom_mem: qseecom_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0 0x00000000 0 0xffffffff>; - reusable; - alignment = <0 0x400000>; - size = <0 0x1400000>; - }; - - sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ - compatible = "shared-dma-pool"; - alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */ - reusable; - alignment = <0 0x100000>; - size = <0 0x800000>; - }; - - secure_display_memory: secure_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0 0x00000000 0 0xffffffff>; - reusable; - alignment = <0 0x200000>; - size = <0 0x5c00000>; - }; - - /* global autoconfigured region for contiguous allocations */ - linux,cma { - compatible = "shared-dma-pool"; - alloc-ranges = <0 0x00000000 0 0xffffffff>; - reusable; - alignment = <0 0x400000>; - size = <0 0x2000000>; - linux,cma-default; - }; - - cont_splash_mem: splash_region@9d600000 { - reg = <0x0 0x9d600000 0x0 0x02400000>; - label = "cont_splash_mem"; - }; - }; - - bluetooth: bt_wcn3990 { - compatible = "qca,wcn3990"; - qca,bt-vdd-core-supply = <&pmfalcon_l9_pin_ctrl>; - qca,bt-vdd-pa-supply = <&pmfalcon_l6_pin_ctrl>; - qca,bt-vdd-ldo-supply = <&pmfalcon_l19_pin_ctrl>; - qca,bt-chip-pwd-supply = <&pm2falcon_bob_pin1>; - clocks = <&clock_gcc clk_rf_clk1>; - clock-names = "rf_clk1"; - - qca,bt-vdd-core-voltage-level = <1800000 1900000>; - qca,bt-vdd-pa-voltage-level = <1304000 1370000>; - qca,bt-vdd-ldo-voltage-level = <3312000 3400000>; - qca,bt-chip-pwd-voltage-level = <3600000 3600000>; - - qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ - qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ - qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */ - }; -}; - -#include "msm8998-smp2p.dtsi" -#include "msm-gdsc-8998.dtsi" - -&soc { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - reg = <0x17a00000 0x10000>, /* GICD */ - <0x17b00000 0x100000>; /* GICR * 8 */ - #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-controller; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x20000>; - interrupts = <1 9 4>; - - gic-its@0x17a20000{ - compatible = "arm,gic-v3-its"; - msi-contoller; - reg = <0x17a20000 0x20000>; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 1 0xf08>, - <1 2 0xf08>, - <1 3 0xf08>, - <1 0 0xf08>; - clock-frequency = <19200000>; - }; - - restart@10ac000 { - compatible = "qcom,pshold"; - reg = <0x10ac000 0x4>, - <0x1fd3000 0x4>; - reg-names = "pshold-base", "tcsr-boot-misc-detect"; - }; - - spmi_bus: qcom,spmi@800f000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x800f000 0x1000>, - <0x8400000 0x1000000>, - <0x9400000 0x1000000>, - <0xa400000 0x220000>, - <0x800a000 0x3000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; - - qcom,sps { - compatible = "qcom,msm_sps_4k"; - qcom,device-type = <3>; - qcom,pipe-attr-ee; - }; - - uartblsp1dm1: serial@0c170000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xc170000 0x1000>; - interrupts = <0 108 0>; - status = "disabled"; - clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>, - <&clock_gcc clk_gcc_blsp1_ahb_clk>; - clock-names = "core", "iface"; - }; - - uartblsp2dm1: serial@0c1b0000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xc1b0000 0x1000>; - interrupts = <0 114 0>; - status = "disabled"; - clocks = <&clock_gcc clk_gcc_blsp2_uart2_apps_clk>, - <&clock_gcc clk_gcc_blsp2_ahb_clk>; - clock-names = "core", "iface"; - }; - - slim_aud: slim@171c0000 { - cell-index = <1>; - compatible = "qcom,slim-ngd"; - reg = <0x171c0000 0x2C000>, - <0x17184000 0x32000>; - reg-names = "slimbus_physical", "slimbus_bam_physical"; - interrupts = <0 163 0>, <0 164 0>; - interrupt-names = "slimbus_irq", "slimbus_bam_irq"; - qcom,apps-ch-pipes = <0x00001f80>; - qcom,ea-pc = <0x210>; - }; - - slim_qca: slim@17240000 { - status = "ok"; - cell-index = <3>; - compatible = "qcom,slim-ngd"; - reg = <0x17240000 0x2C000>, - <0x17204000 0x26000>; - reg-names = "slimbus_physical", "slimbus_bam_physical"; - interrupts = <0 291 0>, <0 292 0>; - interrupt-names = "slimbus_irq", "slimbus_bam_irq"; - - /* Slimbus Slave DT for WCN3990 */ - btfmslim_codec: wcn3990 { - compatible = "qcom,btfmslim_slave"; - elemental-addr = [00 01 20 02 17 02]; - qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; - qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; - }; - }; - - timer@17920000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x17920000 0x1000>; - clock-frequency = <19200000>; - - frame@17921000 { - frame-number = <0>; - interrupts = <0 8 0x4>, - <0 7 0x4>; - reg = <0x17921000 0x1000>, - <0x17922000 0x1000>; - }; - - frame@17923000 { - frame-number = <1>; - interrupts = <0 9 0x4>; - reg = <0x17923000 0x1000>; - status = "disabled"; - }; - - frame@17924000 { - frame-number = <2>; - interrupts = <0 10 0x4>; - reg = <0x17924000 0x1000>; - status = "disabled"; - }; - - frame@17925000 { - frame-number = <3>; - interrupts = <0 11 0x4>; - reg = <0x17925000 0x1000>; - status = "disabled"; - }; - - frame@17926000 { - frame-number = <4>; - interrupts = <0 12 0x4>; - reg = <0x17926000 0x1000>; - status = "disabled"; - }; - - frame@17927000 { - frame-number = <5>; - interrupts = <0 13 0x4>; - reg = <0x17927000 0x1000>; - status = "disabled"; - }; - - frame@17928000 { - frame-number = <6>; - interrupts = <0 14 0x4>; - reg = <0x17928000 0x1000>; - status = "disabled"; - }; - }; - - cpubw: qcom,cpubw { - compatible = "qcom,devbw"; - governor = "performance"; - qcom,src-dst-ports = <1 512>; - qcom,active-only; - qcom,bw-tbl = - < 762 /* 100 MHz */ >, - < 1144 /* 150 MHz */ >, - < 1525 /* 200 MHz */ >, - < 2288 /* 300 MHz */ >, - < 3143 /* 412 MHz */ >, - < 4173 /* 547 MHz */ >, - < 5195 /* 681 MHz */ >, - < 5859 /* 768 MHz */ >, - < 7759 /* 1017 MHz */ >, - < 9887 /* 1296 MHz */ >, - < 11863 /* 1555 MHz */ >, - < 13763 /* 1804 MHz */ >; - }; - - bwmon: qcom,cpu-bwmon { - compatible = "qcom,bimc-bwmon3"; - reg = <0x01008000 0x300>, <0x01001000 0x200>; - reg-names = "base", "global_base"; - interrupts = <0 183 4>; - qcom,mport = <0>; - qcom,target-dev = <&cpubw>; - }; - - mincpubw: qcom,mincpubw { - compatible = "qcom,devbw"; - governor = "powersave"; - qcom,src-dst-ports = <1 512>; - qcom,active-only; - qcom,bw-tbl = - < 762 /* 100 MHz */ >, - < 1144 /* 150 MHz */ >, - < 1525 /* 200 MHz */ >, - < 2288 /* 300 MHz */ >, - < 3143 /* 412 MHz */ >, - < 4173 /* 547 MHz */ >, - < 5195 /* 681 MHz */ >, - < 5859 /* 768 MHz */ >, - < 7759 /* 1017 MHz */ >, - < 9887 /* 1296 MHz */ >, - < 11863 /* 1555 MHz */ >, - < 13763 /* 1804 MHz */ >; - }; - - memlat_cpu0: qcom,memlat-cpu0 { - compatible = "qcom,devbw"; - governor = "powersave"; - qcom,src-dst-ports = <1 512>; - qcom,active-only; - qcom,bw-tbl = - < 762 /* 100 MHz */ >, - < 1144 /* 150 MHz */ >, - < 1525 /* 200 MHz */ >, - < 2288 /* 300 MHz */ >, - < 3143 /* 412 MHz */ >, - < 4173 /* 547 MHz */ >, - < 5195 /* 681 MHz */ >, - < 5859 /* 768 MHz */ >, - < 7759 /* 1017 MHz */ >, - < 9887 /* 1296 MHz */ >, - < 11863 /* 1555 MHz */ >, - < 13763 /* 1804 MHz */ >; - }; - - memlat_cpu4: qcom,memlat-cpu4 { - compatible = "qcom,devbw"; - governor = "powersave"; - qcom,src-dst-ports = <1 512>; - qcom,active-only; - status = "ok"; - qcom,bw-tbl = - < 762 /* 100 MHz */ >, - < 1144 /* 150 MHz */ >, - < 1525 /* 200 MHz */ >, - < 2288 /* 300 MHz */ >, - < 3143 /* 412 MHz */ >, - < 4173 /* 547 MHz */ >, - < 5195 /* 681 MHz */ >, - < 5859 /* 768 MHz */ >, - < 7759 /* 1017 MHz */ >, - < 9887 /* 1296 MHz */ >, - < 11863 /* 1555 MHz */ >, - < 13763 /* 1804 MHz */ >; - }; - - qcom,arm-memlat-mon-0 { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; - qcom,target-dev = <&memlat_cpu0>; - qcom,core-dev-table = - < 300000 1525 >, - < 499200 3143 >, - < 1113600 4173 >, - < 1881600 5859 >; - }; - - qcom,arm-memlat-mon-4 { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; - qcom,target-dev = <&memlat_cpu4>; - qcom,core-dev-table = - < 300000 1525 >, - < 480000 3143 >, - < 900000 4173 >, - < 1017000 7759 >, - < 1296000 9887 >, - < 1555000 11863 >, - < 1804000 13763 >; - }; - - devfreq_cpufreq: devfreq-cpufreq { - mincpubw-cpufreq { - target-dev = <&mincpubw>; - cpu-to-dev-map-0 = - < 1881600 1525 >; - cpu-to-dev-map-4 = - < 2016000 1525 >, - < 2092800 5195 >; - }; - }; - - msm_cpufreq: qcom,msm-cpufreq { - compatible = "qcom,msm-cpufreq"; - clock-names = "cpu0_clk", "cpu1_clk", "cpu2_clk", - "cpu3_clk", "cpu4_clk", "cpu5_clk", - "cpu6_clk", "cpu7_clk"; - clocks = <&clock_cpu clk_pwrcl_clk>, - <&clock_cpu clk_pwrcl_clk>, - <&clock_cpu clk_pwrcl_clk>, - <&clock_cpu clk_pwrcl_clk>, - <&clock_cpu clk_perfcl_clk>, - <&clock_cpu clk_perfcl_clk>, - <&clock_cpu clk_perfcl_clk>, - <&clock_cpu clk_perfcl_clk>; - - qcom,governor-per-policy; - - qcom,cpufreq-table-0 = - < 300000 >, - < 345600 >, - < 422400 >, - < 499200 >, - < 576000 >, - < 633600 >, - < 710400 >, - < 806400 >, - < 883200 >, - < 960000 >, - < 1036800 >, - < 1113600 >, - < 1190400 >, - < 1248000 >, - < 1324800 >, - < 1401600 >, - < 1478400 >, - < 1574400 >, - < 1651200 >, - < 1728000 >, - < 1804800 >, - < 1881600 >; - - qcom,cpufreq-table-4 = - < 300000 >, - < 345600 >, - < 422400 >, - < 480000 >, - < 556800 >, - < 633600 >, - < 710400 >, - < 787200 >, - < 844800 >, - < 902400 >, - < 979200 >, - < 1056000 >, - < 1171200 >, - < 1248000 >, - < 1324800 >, - < 1401600 >, - < 1478400 >, - < 1536000 >, - < 1632000 >, - < 1708800 >, - < 1785600 >, - < 1862400 >, - < 1939200 >, - < 2016000 >, - < 2092800 >; - }; - - arm64-cpu-erp { - compatible = "arm,arm64-cpu-erp"; - interrupts = <0 43 4>, - <0 44 4>, - <0 41 4>, - <0 42 4>; - - interrupt-names = "pri-dbe-irq", - "sec-dbe-irq", - "pri-ext-irq", - "sec-ext-irq"; - - poll-delay-ms = <5000>; - }; - - clock_gcc: qcom,gcc@100000 { - compatible = "qcom,gcc-8998"; - reg = <0x100000 0xb0000>; - reg-names = "cc_base"; - vdd_dig-supply = <&pm8998_s1_level>; - vdd_dig_ao-supply = <&pm8998_s1_level_ao>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - clock_mmss: qcom,mmsscc@c8c0000 { - compatible = "qcom,mmsscc-8998"; - reg = <0xc8c0000 0x40000>; - reg-names = "cc_base"; - vdd_dig-supply = <&pm8998_s1_level>; - vdd_mmsscc_mx-supply = <&pm8998_s9_level>; - clock-names = "xo", "gpll0", "gpll0_div", - "pclk0_src", "pclk1_src", - "byte0_src", "byte1_src", - "dp_link_src", "dp_vco_div", - "extpclk_src"; - clocks = <&clock_gcc clk_cxo_clk_src>, - <&clock_gcc clk_gcc_mmss_gpll0_clk>, - <&clock_gcc clk_gcc_mmss_gpll0_div_clk>, - <&mdss_dsi0_pll clk_dsi0pll_pclk_mux>, - <&mdss_dsi1_pll clk_dsi1pll_pclk_mux>, - <&mdss_dsi0_pll clk_dsi0pll_byteclk_mux>, - <&mdss_dsi1_pll clk_dsi1pll_byteclk_mux>, - <&mdss_dp_pll clk_dp_link_2x_clk_divsel_five>, - <&mdss_dp_pll clk_vco_divided_clk_src_mux>, - <&mdss_hdmi_pll clk_hdmi_vco_clk>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - clock_gpu: qcom,gpucc@5065000 { - compatible = "qcom,gpucc-8998"; - reg = <0x5065000 0x9000>; - reg-names = "cc_base"; - vdd_dig-supply = <&pm8998_s1_level>; - clock-names = "xo_ao", "gpll0"; - clocks = <&clock_gcc clk_cxo_clk_src_ao>, - <&clock_gcc clk_gcc_gpu_gpll0_clk>; - #clock-cells = <1>; - }; - - clock_gfx: qcom,gfxcc@5065000 { - compatible = "qcom,gfxcc-8998"; - reg = <0x5065000 0x9000>; - reg-names = "cc_base"; - vdd_gpucc-supply = <&gfx_vreg>; - vdd_mx-supply = <&pm8998_s9_level>; - vdd_gpu_mx-supply = <&pm8998_s9_level>; - qcom,gfx3d_clk_src-opp-handle = <&msm_gpu>; - qcom,gfxfreq-speedbin0 = - < 0 0 0 >, - < 171000000 1 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 251000000 2 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 332000000 3 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 403000000 4 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 504000000 5 RPM_SMD_REGULATOR_LEVEL_NOM >, - < 650000000 6 RPM_SMD_REGULATOR_LEVEL_TURBO >; - qcom,gfxfreq-mx-speedbin0 = - < 0 0 >, - < 171000000 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 251000000 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 332000000 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 403000000 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 504000000 RPM_SMD_REGULATOR_LEVEL_NOM >, - < 650000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; - #clock-cells = <1>; - }; - - clock_cpu: qcom,cpu-clock-8998@179c0000 { - compatible = "qcom,cpu-clock-osm-msm8998-v1"; - reg = <0x179c0000 0x4000>, - <0x17916000 0x1000>, - <0x17816000 0x1000>, - <0x179d1000 0x1000>, - <0x00784130 0x8>, - <0x1791101c 0x8>; - reg-names = "osm", "pwrcl_pll", "perfcl_pll", - "apcs_common", "perfcl_efuse", "debug"; - - vdd-pwrcl-supply = <&apc0_pwrcl_vreg>; - vdd-perfcl-supply = <&apc1_perfcl_vreg>; - - interrupts = , - ; - interrupt-names = "pwrcl-irq", "perfcl-irq"; - - qcom,pwrcl-speedbin0-v0 = - < 300000000 0x0004000f 0x01200020 0x1 1 >, - < 345600000 0x05040012 0x02200020 0x1 2 >, - < 422400000 0x05040016 0x02200020 0x1 3 >, - < 499200000 0x0504001a 0x02200020 0x1 4 >, - < 576000000 0x0504001e 0x03200020 0x1 5 >, - < 633600000 0x05040021 0x03200020 0x1 6 >, - < 710400000 0x05040025 0x03200020 0x1 7 >, - < 806400000 0x0504002a 0x04200020 0x1 8 >, - < 883200000 0x0404002e 0x04250025 0x1 9 >, - < 960000000 0x04040032 0x05280028 0x1 10 >, - < 1036800000 0x04040036 0x052b002b 0x2 11 >, - < 1113600000 0x0404003a 0x052e002e 0x2 12 >, - < 1190400000 0x0404003e 0x06320032 0x2 13 >, - < 1248000000 0x04040041 0x06340034 0x2 14 >, - < 1324800000 0x04040045 0x06370037 0x2 15 >, - < 1401600000 0x04040049 0x073a003a 0x2 16 >, - < 1478400000 0x0404004d 0x073e003e 0x2 17 >, - < 1574400000 0x04040052 0x08420042 0x2 18 >, - < 1651200000 0x04040056 0x08450045 0x2 19 >, - < 1728000000 0x0404005a 0x08480048 0x2 20 >, - < 1804800000 0x0404005e 0x094b004b 0x3 21 >, - < 1881600000 0x04040062 0x094e004e 0x3 22 >; - - qcom,perfcl-speedbin0-v0 = - < 300000000 0x0004000f 0x01200020 0x1 1 >, - < 345600000 0x05040012 0x02200020 0x1 2 >, - < 422400000 0x05040016 0x02200020 0x1 3 >, - < 480000000 0x05040019 0x02200020 0x1 4 >, - < 556800000 0x0504001d 0x03200020 0x1 5 >, - < 633600000 0x05040021 0x03200020 0x1 6 >, - < 710400000 0x05040025 0x03200020 0x1 7 >, - < 787200000 0x05040029 0x04200020 0x1 8 >, - < 844800000 0x0404002c 0x04230023 0x1 9 >, - < 902400000 0x0404002f 0x04260026 0x1 10 >, - < 979200000 0x04040033 0x05290029 0x1 11 >, - < 1056000000 0x04040037 0x052c002c 0x1 12 >, - < 1171200000 0x0404003d 0x06310031 0x2 13 >, - < 1248000000 0x04040041 0x06340034 0x2 14 >, - < 1324800000 0x04040045 0x06370037 0x2 15 >, - < 1401600000 0x04040049 0x073a003a 0x2 16 >, - < 1478400000 0x0404004d 0x073e003e 0x2 17 >, - < 1536000000 0x04040050 0x07400040 0x2 18 >, - < 1632000000 0x04040055 0x08440044 0x2 19 >, - < 1708800000 0x04040059 0x08470047 0x2 20 >, - < 1785600000 0x0404005d 0x094a004a 0x2 21 >, - < 1862400000 0x04040061 0x094e004e 0x2 22 >, - < 1939200000 0x04040065 0x09510051 0x3 23 >, - < 2016000000 0x04040069 0x0a540054 0x3 24 >, - < 2092800000 0x0404006d 0x0a570057 0x3 25 >; - - qcom,up-timer = - <1000 1000>; - qcom,down-timer = - <1000 1000>; - qcom,pc-override-index = - <0 0>; - qcom,set-ret-inactive; - qcom,enable-llm-freq-vote; - qcom,llm-freq-up-timer = - <327675 327675>; - qcom,llm-freq-down-timer = - <327675 327675>; - qcom,enable-llm-volt-vote; - qcom,llm-volt-up-timer = - <327675 327675>; - qcom,llm-volt-down-timer = - <327675 327675>; - qcom,cc-reads = <10>; - qcom,cc-delay = <5>; - qcom,cc-factor = <100>; - qcom,osm-clk-rate = <200000000>; - qcom,xo-clk-rate = <19200000>; - - qcom,l-val-base = - <0x17916004 0x17816004>; - qcom,apcs-itm-present = - <0x179d143c 0x179d143c>; - qcom,apcs-pll-user-ctl = - <0x1791600c 0x1781600c>; - qcom,apcs-cfg-rcgr = - <0x17911054 0x17811054>; - qcom,apcs-cmd-rcgr = - <0x17911050 0x17811050>; - qcom,apm-mode-ctl = - <0x179d0004 0x179d0010>; - qcom,apm-ctrl-status = - <0x179d000c 0x179d0018>; - qcom,llm-sw-overr= - <0x8fff0036 0x8fff003a 0x0fff0036>, - <0x8fff003d 0x8fff0041 0x0fff003d>; - - qcom,apm-threshold-voltage = <832000>; - qcom,boost-fsm-en; - qcom,safe-fsm-en; - qcom,ps-fsm-en; - qcom,droop-fsm-en; - qcom,wfx-fsm-en; - qcom,pc-fsm-en; - - qcom,pwrcl-apcs-mem-acc-cfg = - <0x179d1360 0x179d1364 0x179d1364>; - qcom,perfcl-apcs-mem-acc-cfg = - <0x179d1368 0x179d136C 0x179d1370>; - qcom,pwrcl-apcs-mem-acc-val = - <0x00000000 0x80000000 0x80000000>, - <0x00000000 0x00000000 0x00000000>, - <0x00000000 0x00000001 0x00000001>; - qcom,perfcl-apcs-mem-acc-val = - <0x00000000 0x00000000 0x80000000>, - <0x00000000 0x00000000 0x00000000>, - <0x00000000 0x00000000 0x00000001>; - - clock-names = "aux_clk", "xo_ao"; - clocks = <&clock_gcc clk_hmss_gpll0_clk_src>, - <&clock_gcc clk_cxo_clk_src_ao>; - #clock-cells = <1>; - }; - - clock_debug: qcom,debugcc@162000 { - compatible = "qcom,cc-debug-8998"; - reg = <0x162000 0x4>; - reg-names = "cc_base"; - clock-names = "debug_gpu_clk", "debug_gfx_clk", - "debug_mmss_clk", "debug_cpu_clk"; - clocks = <&clock_gpu clk_gpucc_gcc_dbg_clk>, - <&clock_gfx clk_gfxcc_dbg_clk>, - <&clock_mmss clk_mmss_debug_mux>, - <&clock_cpu clk_cpu_debug_mux>; - #clock-cells = <1>; - }; - - qcom,rmtfs_sharedmem@0 { - compatible = "qcom,sharedmem-uio"; - reg = <0x0 0x00200000>; - reg-names = "rmtfs"; - qcom,client-id = <0x00000001>; - }; - - qcom,msm_gsi { - compatible = "qcom,msm_gsi"; - }; - - qcom,rmnet-ipa { - compatible = "qcom,rmnet-ipa3"; - qcom,rmnet-ipa-ssr; - qcom,ipa-loaduC; - qcom,ipa-advertise-sg-support; - }; - - ipa_hw: qcom,ipa@01e00000 { - compatible = "qcom,ipa"; - reg = <0x01e00000 0x34000>, - <0x01e84000 0x31fff>, - <0x01e04000 0x2c000>; - reg-names = "ipa-base", "bam-base", "gsi-base"; - interrupts = - <0 333 0>, - <0 432 0>, - <0 432 0>; - interrupt-names = "ipa-irq", "bam-irq", "gsi-irq"; - qcom,ipa-hw-ver = <11>; /* IPA core version = IPAv3.1 */ - qcom,ipa-hw-mode = <0>; /* IPA hw type = Normal */ - qcom,ee = <0>; - qcom,use-gsi; - qcom,use-ipa-tethering-bridge; - qcom,modem-cfg-emb-pipe-flt; - qcom,do-not-use-ch-gsi-20; - qcom,ipa-wdi2; - qcom,use-64-bit-dma-mask; - clocks = <&clock_gcc clk_ipa_clk>; - clock-names = "core_clk"; - qcom,arm-smmu; - qcom,smmu-disable-htw; - qcom,smmu-s1-bypass; - qcom,msm-bus,name = "ipa"; - qcom,msm-bus,num-cases = <4>; - qcom,msm-bus,num-paths = <4>; - qcom,msm-bus,vectors-KBps = - /* No vote */ - <90 512 0 0>, - <90 585 0 0>, - <1 676 0 0>, - /* SMMU smmu_aggre2_noc_clk */ - <81 10065 0 0>, - /* SVS */ - <90 512 80000 640000>, - <90 585 80000 640000>, - <1 676 80000 80000>, - /* SMMU smmu_aggre2_noc_clk */ - <81 10065 0 16000>, - /* NOMINAL */ - <90 512 206000 960000>, - <90 585 206000 960000>, - <1 676 206000 160000>, - /* SMMU smmu_aggre2_noc_clk */ - <81 10065 0 16000>, - /* TURBO */ - <90 512 206000 3600000>, - <90 585 206000 3600000>, - <1 676 206000 300000>, - /* SMMU smmu_aggre2_noc_clk */ - <81 10065 0 16000>; - qcom,bus-vector-names = "MIN", "SVS", "NOMINAL", "TURBO"; - - /* IPA RAM mmap */ - qcom,ipa-ram-mmap = < - 0x280 /* ofst_start; */ - 0x0 /* nat_ofst; */ - 0x0 /* nat_size; */ - 0x288 /* v4_flt_hash_ofst; */ - 0x78 /* v4_flt_hash_size; */ - 0x4000 /* v4_flt_hash_size_ddr; */ - 0x308 /* v4_flt_nhash_ofst; */ - 0x78 /* v4_flt_nhash_size; */ - 0x4000 /* v4_flt_nhash_size_ddr; */ - 0x388 /* v6_flt_hash_ofst; */ - 0x78 /* v6_flt_hash_size; */ - 0x4000 /* v6_flt_hash_size_ddr; */ - 0x408 /* v6_flt_nhash_ofst; */ - 0x78 /* v6_flt_nhash_size; */ - 0x4000 /* v6_flt_nhash_size_ddr; */ - 0xf /* v4_rt_num_index; */ - 0x0 /* v4_modem_rt_index_lo; */ - 0x7 /* v4_modem_rt_index_hi; */ - 0x8 /* v4_apps_rt_index_lo; */ - 0xe /* v4_apps_rt_index_hi; */ - 0x488 /* v4_rt_hash_ofst; */ - 0x78 /* v4_rt_hash_size; */ - 0x4000 /* v4_rt_hash_size_ddr; */ - 0x508 /* v4_rt_nhash_ofst; */ - 0x78 /* v4_rt_nhash_size; */ - 0x4000 /* v4_rt_nhash_size_ddr; */ - 0xf /* v6_rt_num_index; */ - 0x0 /* v6_modem_rt_index_lo; */ - 0x7 /* v6_modem_rt_index_hi; */ - 0x8 /* v6_apps_rt_index_lo; */ - 0xe /* v6_apps_rt_index_hi; */ - 0x588 /* v6_rt_hash_ofst; */ - 0x78 /* v6_rt_hash_size; */ - 0x4000 /* v6_rt_hash_size_ddr; */ - 0x608 /* v6_rt_nhash_ofst; */ - 0x78 /* v6_rt_nhash_size; */ - 0x4000 /* v6_rt_nhash_size_ddr; */ - 0x688 /* modem_hdr_ofst; */ - 0x140 /* modem_hdr_size; */ - 0x7c8 /* apps_hdr_ofst; */ - 0x0 /* apps_hdr_size; */ - 0x800 /* apps_hdr_size_ddr; */ - 0x7d0 /* modem_hdr_proc_ctx_ofst; */ - 0x200 /* modem_hdr_proc_ctx_size; */ - 0x9d0 /* apps_hdr_proc_ctx_ofst; */ - 0x200 /* apps_hdr_proc_ctx_size; */ - 0x0 /* apps_hdr_proc_ctx_size_ddr; */ - 0x0 /* modem_comp_decomp_ofst; diff */ - 0x0 /* modem_comp_decomp_size; diff */ - 0xbd8 /* modem_ofst; */ - 0x1424 /* modem_size; */ - 0x1ffc /* apps_v4_flt_hash_ofst; */ - 0x0 /* apps_v4_flt_hash_size; */ - 0x1ffc /* apps_v4_flt_nhash_ofst; */ - 0x0 /* apps_v4_flt_nhash_size; */ - 0x1ffc /* apps_v6_flt_hash_ofst; */ - 0x0 /* apps_v6_flt_hash_size; */ - 0x1ffc /* apps_v6_flt_nhash_ofst; */ - 0x0 /* apps_v6_flt_nhash_size; */ - 0x80 /* uc_info_ofst; */ - 0x200 /* uc_info_size; */ - 0x2000 /* end_ofst; */ - 0x1ffc /* apps_v4_rt_hash_ofst; */ - 0x0 /* apps_v4_rt_hash_size; */ - 0x1ffc /* apps_v4_rt_nhash_ofst; */ - 0x0 /* apps_v4_rt_nhash_size; */ - 0x1ffc /* apps_v6_rt_hash_ofst; */ - 0x0 /* apps_v6_rt_hash_size; */ - 0x1ffc /* apps_v6_rt_nhash_ofst; */ - 0x0 /* apps_v6_rt_nhash_size; */ - >; - - /* smp2p gpio information */ - qcom,smp2pgpio_map_ipa_1_out { - compatible = "qcom,smp2pgpio-map-ipa-1-out"; - gpios = <&smp2pgpio_ipa_1_out 0 0>; - }; - - qcom,smp2pgpio_map_ipa_1_in { - compatible = "qcom,smp2pgpio-map-ipa-1-in"; - gpios = <&smp2pgpio_ipa_1_in 0 0>; - }; - - ipa_smmu_ap: ipa_smmu_ap { - compatible = "qcom,ipa-smmu-ap-cb"; - iommus = <&anoc2_smmu 0x18e0>; - qcom,iova-mapping = <0x10000000 0x40000000>; - }; - - ipa_smmu_wlan: ipa_smmu_wlan { - compatible = "qcom,ipa-smmu-wlan-cb"; - iommus = <&anoc2_smmu 0x18e1>; - }; - - ipa_smmu_uc: ipa_smmu_uc { - compatible = "qcom,ipa-smmu-uc-cb"; - iommus = <&anoc2_smmu 0x18e2>; - qcom,iova-mapping = <0x40000000 0x20000000>; - }; - }; - - qcom,ipa_fws@1e08000 { - compatible = "qcom,pil-tz-generic"; - qcom,pas-id = <0xF>; - qcom,firmware-name = "ipa_fws"; - }; - - qcom,chd_silver { - compatible = "qcom,core-hang-detect"; - label = "silver"; - qcom,threshold-arr = <0x179880b0 0x179980b0 - 0x179a80b0 0x179b80b0>; - qcom,config-arr = <0x179880b8 0x179980b8 - 0x179a80b8 0x179b80b8>; - }; - - qcom,chd_gold { - compatible = "qcom,core-hang-detect"; - label = "gold"; - qcom,threshold-arr = <0x178880b0 0x178980b0 - 0x178a80b0 0x178b80b0>; - qcom,config-arr = <0x178880b8 0x178980b8 - 0x178a80b8 0x178b80b8>; - }; - - qcom,ipc-spinlock@1f40000 { - compatible = "qcom,ipc-spinlock-sfpb"; - reg = <0x1f40000 0x8000>; - qcom,num-locks = <8>; - }; - - qcom,ghd { - compatible = "qcom,gladiator-hang-detect"; - qcom,threshold-arr = <0x179d141c 0x179d1420 - 0x179d1424 0x179d1428 0x179d142c 0x179d1430>; - qcom,config-reg = <0x179d1434>; - }; - - qcom,msm-gladiator-v2@17900000 { - compatible = "qcom,msm-gladiator-v2"; - reg = <0x17900000 0xe000>; - reg-names = "gladiator_base"; - interrupts = <0 22 0>; - clock-names = "atb_clk"; - clocks = <&clock_gcc clk_qdss_clk>; - }; - - qcom,smem@86000000 { - compatible = "qcom,smem"; - reg = <0x86000000 0x200000>, - <0x17911008 0x4>, - <0x778000 0x7000>, - <0x1fd4000 0x8>; - reg-names = "smem", "irq-reg-base", "aux-mem1", - "smem_targ_info_reg"; - qcom,mpu-enabled; - }; - - qcom,msm-adsprpc-mem { - compatible = "qcom,msm-adsprpc-mem-region"; - memory-region = <&adsp_mem>; - }; - - qcom,msm_fastrpc { - compatible = "qcom,msm-fastrpc-adsp"; - qcom,fastrpc-glink; - - qcom,msm_fastrpc_cpz_cb1 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "adsprpc-smd"; - iommus = <&lpass_q6_smmu 2>; - qcom,secure-context-bank; - dma-coherent; - }; - qcom,msm_fastrpc_compute_cb1 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "adsprpc-smd"; - iommus = <&lpass_q6_smmu 8>; - dma-coherent; - }; - qcom,msm_fastrpc_compute_cb2 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "adsprpc-smd"; - iommus = <&lpass_q6_smmu 9>; - dma-coherent; - }; - qcom,msm_fastrpc_compute_cb3 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "adsprpc-smd"; - iommus = <&lpass_q6_smmu 10>; - dma-coherent; - }; - qcom,msm_fastrpc_compute_cb4 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "adsprpc-smd"; - iommus = <&lpass_q6_smmu 11>; - dma-coherent; - }; - qcom,msm_fastrpc_compute_cb6 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "adsprpc-smd"; - iommus = <&lpass_q6_smmu 5>; - dma-coherent; - }; - qcom,msm_fastrpc_compute_cb7 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "adsprpc-smd"; - iommus = <&lpass_q6_smmu 6>; - dma-coherent; - }; - qcom,msm_fastrpc_compute_cb8 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "adsprpc-smd"; - iommus = <&lpass_q6_smmu 7>; - dma-coherent; - }; - }; - - rpm_bus: qcom,rpm-smd { - compatible = "qcom,rpm-glink"; - qcom,glink-edge = "rpm"; - rpm-channel-name = "rpm_requests"; - }; - - glink_mpss: qcom,glink-ssr-modem { - compatible = "qcom,glink_ssr"; - label = "modem"; - qcom,edge = "mpss"; - qcom,notify-edges = <&glink_lpass>, <&glink_dsps>, <&glink_rpm>, - <&glink_spss>; - qcom,xprt = "smem"; - }; - - glink_lpass: qcom,glink-ssr-adsp { - compatible = "qcom,glink_ssr"; - label = "adsp"; - qcom,edge = "lpass"; - qcom,notify-edges = <&glink_mpss>, <&glink_dsps>, <&glink_rpm>, - <&glink_spss>; - qcom,xprt = "smem"; - }; - - glink_dsps: qcom,glink-ssr-dsps { - compatible = "qcom,glink_ssr"; - label = "slpi"; - qcom,edge = "dsps"; - qcom,notify-edges = <&glink_mpss>, <&glink_lpass>, <&glink_rpm>, - <&glink_spss>; - qcom,xprt = "smem"; - }; - - glink_rpm: qcom,glink-ssr-rpm { - compatible = "qcom,glink_ssr"; - label = "rpm"; - qcom,edge = "rpm"; - qcom,notify-edges = <&glink_lpass>, <&glink_mpss>, - <&glink_dsps>, <&glink_spss>; - qcom,xprt = "smem"; - }; - - glink_spss: qcom,glink-ssr-spss { - compatible = "qcom,glink_ssr"; - label = "spss"; - qcom,edge = "spss"; - qcom,notify-edges = <&glink_mpss>, <&glink_lpass>, - <&glink_dsps>, <&glink_rpm>; - qcom,xprt = "mailbox"; - }; - - qcom,glink-smem-native-xprt-modem@86000000 { - compatible = "qcom,glink-smem-native-xprt"; - reg = <0x86000000 0x200000>, - <0x17911008 0x4>; - reg-names = "smem", "irq-reg-base"; - qcom,irq-mask = <0x8000>; - interrupts = <0 452 1>; - label = "mpss"; - }; - - qcom,glink-smem-native-xprt-adsp@86000000 { - compatible = "qcom,glink-smem-native-xprt"; - reg = <0x86000000 0x200000>, - <0x17911008 0x4>; - reg-names = "smem", "irq-reg-base"; - qcom,irq-mask = <0x200>; - interrupts = <0 157 1>; - label = "lpass"; - }; - - qcom,glink-smem-native-xprt-dsps@86000000 { - compatible = "qcom,glink-smem-native-xprt"; - reg = <0x86000000 0x200000>, - <0x17911008 0x4>; - reg-names = "smem", "irq-reg-base"; - qcom,irq-mask = <0x8000000>; - interrupts = <0 179 1>; - label = "dsps"; - }; - - qcom,glink-smem-native-xprt-rpm@778000 { - compatible = "qcom,glink-rpm-native-xprt"; - reg = <0x778000 0x7000>, - <0x17911008 0x4>; - reg-names = "msgram", "irq-reg-base"; - qcom,irq-mask = <0x1>; - interrupts = <0 168 1>; - label = "rpm"; - }; - - qcom,glink-mailbox-xprt-spss@1d05008 { - compatible = "qcom,glink-mailbox-xprt"; - reg = <0x1d05008 0x8>, - <0x1d05010 0x4>, - <0x1d0501c 0x4>, - <0x1d06008 0x4>; - reg-names = "mbox-loc-addr", "mbox-loc-size", "irq-reg-base", - "irq-rx-reset"; - qcom,irq-mask = <0x1>; - interrupts = <0 348 4>; - label = "spss"; - qcom,tx-ring-size = <0x800>; - qcom,rx-ring-size = <0x800>; - }; - - glink_spi_xprt_wdsp: qcom,glink-spi-xprt-wdsp { - compatible = "qcom,glink-spi-xprt"; - label = "wdsp"; - qcom,remote-fifo-config = <&glink_fifo_wdsp>; - qcom,qos-config = <&glink_qos_wdsp>; - qcom,ramp-time = <0x10>, - <0x20>, - <0x30>, - <0x40>; - }; - - glink_fifo_wdsp: qcom,glink-fifo-config-wdsp { - compatible = "qcom,glink-fifo-config"; - qcom,out-read-idx-reg = <0x12000>; - qcom,out-write-idx-reg = <0x12004>; - qcom,in-read-idx-reg = <0x1200C>; - qcom,in-write-idx-reg = <0x12010>; - }; - - glink_qos_wdsp: qcom,glink-qos-config-wdsp { - compatible = "qcom,glink-qos-config"; - qcom,flow-info = <0x80 0x0>, - <0x70 0x1>, - <0x60 0x2>, - <0x50 0x3>; - qcom,mtu-size = <0x800>; - qcom,tput-stats-cycle = <0xa>; - }; - - qcom,glink_pkt { - compatible = "qcom,glinkpkt"; - - qcom,glinkpkt-at-mdm0 { - qcom,glinkpkt-transport = "smem"; - qcom,glinkpkt-edge = "mpss"; - qcom,glinkpkt-ch-name = "DS"; - qcom,glinkpkt-dev-name = "at_mdm0"; - }; - - qcom,glinkpkt-loopback_cntl { - qcom,glinkpkt-transport = "lloop"; - qcom,glinkpkt-edge = "local"; - qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT"; - qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl"; - }; - - qcom,glinkpkt-loopback_data { - qcom,glinkpkt-transport = "lloop"; - qcom,glinkpkt-edge = "local"; - qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT"; - qcom,glinkpkt-dev-name = "glink_pkt_loopback"; - }; - - qcom,glinkpkt-apr-apps2 { - qcom,glinkpkt-transport = "smem"; - qcom,glinkpkt-edge = "adsp"; - qcom,glinkpkt-ch-name = "apr_apps2"; - qcom,glinkpkt-dev-name = "apr_apps2"; - }; - - qcom,glinkpkt-data40-cntl { - qcom,glinkpkt-transport = "smem"; - qcom,glinkpkt-edge = "mpss"; - qcom,glinkpkt-ch-name = "DATA40_CNTL"; - qcom,glinkpkt-dev-name = "smdcntl8"; - }; - - qcom,glinkpkt-data1 { - qcom,glinkpkt-transport = "smem"; - qcom,glinkpkt-edge = "mpss"; - qcom,glinkpkt-ch-name = "DATA1"; - qcom,glinkpkt-dev-name = "smd7"; - }; - - qcom,glinkpkt-data4 { - qcom,glinkpkt-transport = "smem"; - qcom,glinkpkt-edge = "mpss"; - qcom,glinkpkt-ch-name = "DATA4"; - qcom,glinkpkt-dev-name = "smd8"; - }; - - qcom,glinkpkt-data11 { - qcom,glinkpkt-transport = "smem"; - qcom,glinkpkt-edge = "mpss"; - qcom,glinkpkt-ch-name = "DATA11"; - qcom,glinkpkt-dev-name = "smd11"; - }; - }; - - pcie0: qcom,pcie@01c00000 { - compatible = "qcom,pci-msm"; - cell-index = <0>; - - reg = <0x1c00000 0x2000>, - <0x1c06000 0x1000>, - <0x1b000000 0xf1d>, - <0x1b000f20 0xa8>, - <0x1b100000 0x100000>, - <0x1b200000 0x100000>, - <0x1b300000 0xd00000>; - - reg-names = "parf", "phy", "dm_core", "elbi", - "conf", "io", "bars"; - - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>, - <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; - interrupt-parent = <&pcie0>; - interrupts = <0 1 2 3 4 5>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0xffffffff>; - interrupt-map = <0 0 0 0 &intc 0 0 405 0 - 0 0 0 1 &intc 0 0 135 0 - 0 0 0 2 &intc 0 0 136 0 - 0 0 0 3 &intc 0 0 138 0 - 0 0 0 4 &intc 0 0 139 0 - 0 0 0 5 &intc 0 0 278 0>; - - interrupt-names = "int_msi", "int_a", "int_b", "int_c", - "int_d", "int_global_int"; - - qcom,phy-sequence = <0x804 0x01 0x00 - 0x034 0x14 0x00 - 0x138 0x30 0x00 - 0x048 0x0f 0x00 - 0x15c 0x06 0x00 - 0x090 0x01 0x00 - 0x088 0x20 0x00 - 0x0f0 0x00 0x00 - 0x0f8 0x01 0x00 - 0x0f4 0xc9 0x00 - 0x11c 0xff 0x00 - 0x120 0x3f 0x00 - 0x164 0x01 0x00 - 0x154 0x00 0x00 - 0x148 0x0a 0x00 - 0x05C 0x19 0x00 - 0x038 0x90 0x00 - 0x0b0 0x82 0x00 - 0x0c0 0x03 0x00 - 0x0bc 0x55 0x00 - 0x0b8 0x55 0x00 - 0x0a0 0x00 0x00 - 0x09c 0x0d 0x00 - 0x098 0x04 0x00 - 0x13c 0x00 0x00 - 0x060 0x08 0x00 - 0x068 0x16 0x00 - 0x070 0x34 0x00 - 0x15c 0x06 0x00 - 0x138 0x33 0x00 - 0x03c 0x02 0x00 - 0x040 0x0e 0x00 - 0x080 0x04 0x00 - 0x0dc 0x00 0x00 - 0x0d8 0x3f 0x00 - 0x00c 0x09 0x00 - 0x010 0x01 0x00 - 0x01c 0x40 0x00 - 0x020 0x01 0x00 - 0x014 0x02 0x00 - 0x018 0x00 0x00 - 0x024 0x7e 0x00 - 0x028 0x15 0x00 - 0x244 0x02 0x00 - 0x2a4 0x12 0x00 - 0x260 0x10 0x00 - 0x28c 0x06 0x00 - 0x504 0x03 0x00 - 0x500 0x1c 0x00 - 0x50c 0x14 0x00 - 0x4d4 0x0a 0x00 - 0x4d8 0x04 0x00 - 0x4dc 0x1a 0x00 - 0x434 0x4b 0x00 - 0x414 0x04 0x00 - 0x40c 0x04 0x00 - 0x4f8 0x00 0x00 - 0x4fc 0x80 0x00 - 0x51c 0x40 0x00 - 0x444 0x71 0x00 - 0x43c 0x40 0x00 - 0x854 0x04 0x00 - 0x62c 0x52 0x00 - 0x9ac 0x00 0x00 - 0x8a0 0x01 0x00 - 0x9e0 0x00 0x00 - 0x9dc 0x01 0x00 - 0x9a8 0x00 0x00 - 0x8a4 0x01 0x00 - 0x8a8 0x73 0x00 - 0x9d8 0x99 0x00 - 0x9b0 0x03 0x00 - 0x804 0x03 0x00 - 0x800 0x00 0x00 - 0x808 0x03 0x00>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_clkreq_default - &pcie0_perst_default - &pcie0_wake_default>; - - perst-gpio = <&tlmm 35 0>; - wake-gpio = <&tlmm 37 0>; - - gdsc-vdd-supply = <&gdsc_pcie_0>; - vreg-1.8-supply = <&pm8998_l2>; - vreg-0.9-supply = <&pm8998_l1>; - vreg-cx-supply = <&pm8998_s1_level>; - - qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>; - qcom,vreg-0.9-voltage-level = <880000 880000 24000>; - qcom,vreg-cx-voltage-level = ; - - qcom,ep-latency = <10>; - - qcom,ep-wakeirq; - - linux,pci-domain = <0>; - - qcom,pcie-phy-ver = <0x20>; - qcom,use-19p2mhz-aux-clk; - - iommus = <&anoc1_smmu>; - qcom,smmu-exist; - qcom,smmu-sid-base = <0x1480>; - - qcom,msm-bus,name = "pcie0"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <45 512 0 0>, - <45 512 500 800>; - - clocks = <&clock_gcc clk_gcc_pcie_0_pipe_clk>, - <&clock_gcc clk_ln_bb_clk1>, - <&clock_gcc clk_gcc_pcie_0_aux_clk>, - <&clock_gcc clk_gcc_pcie_0_cfg_ahb_clk>, - <&clock_gcc clk_gcc_pcie_0_mstr_axi_clk>, - <&clock_gcc clk_gcc_pcie_0_slv_axi_clk>, - <&clock_gcc clk_gcc_pcie_clkref_clk>; - - clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", - "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", - "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", - "pcie_0_ldo"; - - max-clock-frequency-hz = <0>, <0>, <19200000>, - <0>, <0>, <0>, <0>, <0>, <0>, - <0>, <0>, <0>, <0>, <0>, <0>, - <0>, <0>; - - resets = <&clock_gcc PCIE_PHY_BCR>, - <&clock_gcc PCIE_0_PHY_BCR>, - <&clock_gcc PCIE_0_PHY_BCR>; - - reset-names = "pcie_phy_reset", - "pcie_0_phy_reset", - "pcie_0_phy_pipe_reset"; - }; - - qcom,ipc_router { - compatible = "qcom,ipc_router"; - qcom,node-id = <1>; - }; - - qcom,ipc_router_modem_xprt { - compatible = "qcom,ipc_router_glink_xprt"; - qcom,ch-name = "IPCRTR"; - qcom,xprt-remote = "mpss"; - qcom,glink-xprt = "smem"; - qcom,xprt-linkid = <1>; - qcom,xprt-version = <1>; - qcom,fragmented-data; - }; - - qcom,ipc_router_q6_xprt { - compatible = "qcom,ipc_router_glink_xprt"; - qcom,ch-name = "IPCRTR"; - qcom,xprt-remote = "lpass"; - qcom,glink-xprt = "smem"; - qcom,xprt-linkid = <1>; - qcom,xprt-version = <1>; - qcom,fragmented-data; - }; - - qcom,ipc_router_dsps_xprt { - compatible = "qcom,ipc_router_glink_xprt"; - qcom,ch-name = "IPCRTR"; - qcom,xprt-remote = "dsps"; - qcom,glink-xprt = "smem"; - qcom,xprt-linkid = <1>; - qcom,xprt-version = <1>; - qcom,fragmented-data; - }; - - qcom,spcom { - compatible = "qcom,spcom"; - - /* predefined channels, remote side is server */ - qcom,spcom-ch-names = "sp_kernel" , "sp_ssr"; - status = "ok"; - }; - - spss_utils: qcom,spss_utils { - compatible = "qcom,spss-utils"; - /* spss test fuse physical address */ - qcom,spss-fuse-addr = <0x007841c4 0x4>; - qcom,spss-fuse-bit = <27>; - qcom,spss-test-firmware-name = "spss"; /* default name */ - qcom,spss-prod-firmware-name = "spss1p"; /* 8 chars max */ - status = "ok"; - }; - - sdhc_2: sdhci@c0a4900 { - compatible = "qcom,sdhci-msm"; - reg = <0xc0a4900 0x314>, <0xc0a4000 0x800>; - reg-names = "hc_mem", "core_mem"; - - interrupts = <0 125 0>, <0 221 0>; - interrupt-names = "hc_irq", "pwr_irq"; - - clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc clk_gcc_sdcc2_ahb_clk>, - <&clock_gcc clk_gcc_sdcc2_apps_clk>; - - qcom,large-address-bus; - qcom,bus-width = <4>; - qcom,cpu-dma-latency-us = <701>; - - qcom,devfreq,freq-table = <52000000 200000000>; - - qcom,msm-bus,name = "sdhc2"; - qcom,msm-bus,num-cases = <8>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */ - <81 512 1600 3200>, /* 400 KB/s*/ - <81 512 80000 160000>, /* 20 MB/s */ - <81 512 100000 200000>, /* 25 MB/s */ - <81 512 200000 400000>, /* 50 MB/s */ - <81 512 400000 800000>, /* 100 MB/s */ - <81 512 800000 800000>, /* 200 MB/s */ - <81 512 2048000 4096000>; /* Max. bandwidth */ - qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 - 100000000 200000000 4294967295>; - - status = "disabled"; - }; - - ufsphy1: ufsphy@1da7000 { - compatible = "qcom,ufs-phy-qmp-v3"; - reg = <0x1da7000 0xda8>; - reg-names = "phy_mem"; - #phy-cells = <0>; - clock-names = "ref_clk_src", - "ref_clk", - "ref_aux_clk"; - clocks = <&clock_gcc clk_ln_bb_clk1>, - <&clock_gcc clk_gcc_ufs_clkref_clk>, - <&clock_gcc clk_gcc_ufs_phy_aux_hw_ctl_clk>; - status = "disabled"; - }; - - ufs_ice: ufsice@1db0000 { - compatible = "qcom,ice"; - reg = <0x1db0000 0x8000>; - qcom,enable-ice-clk; - clock-names = "ufs_core_clk", - "bus_clk", - "iface_clk", - "ice_core_clk"; - clocks = <&clock_gcc clk_gcc_ufs_axi_clk>, - <&clock_gcc clk_gcc_aggre1_ufs_axi_clk>, - <&clock_gcc clk_gcc_ufs_ahb_clk>, - <&clock_gcc clk_gcc_ufs_ice_core_clk>; - qcom,op-freq-hz = <0>, - <0>, - <0>, - <300000000>; - vdd-hba-supply = <&gdsc_ufs>; - qcom,msm-bus,name = "ufs_ice_noc"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <1 650 0 0>, /* No vote */ - <1 650 1000 0>; /* Max. bandwidth */ - qcom,bus-vector-names = "MIN", - "MAX"; - qcom,instance-type = "ufs"; - status = "disabled"; - }; - - ufs1: ufshc@1da4000 { - compatible = "qcom,ufshc"; - reg = <0x1da4000 0x2500>; - interrupts = <0 265 0>; - phys = <&ufsphy1>; - phy-names = "ufsphy"; - ufs-qcom-crypto = <&ufs_ice>; - - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "core_clk_ice", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk"; - clocks = - <&clock_gcc clk_gcc_ufs_axi_hw_ctl_clk>, - <&clock_gcc clk_gcc_aggre1_ufs_axi_hw_ctl_clk>, - <&clock_gcc clk_gcc_ufs_ahb_clk>, - <&clock_gcc clk_gcc_ufs_unipro_core_hw_ctl_clk>, - <&clock_gcc clk_gcc_ufs_ice_core_hw_ctl_clk>, - <&clock_gcc clk_ln_bb_clk1>, - <&clock_gcc clk_gcc_ufs_tx_symbol_0_clk>, - <&clock_gcc clk_gcc_ufs_rx_symbol_0_clk>; - freq-table-hz = - <50000000 200000000>, - <0 0>, - <0 0>, - <37500000 150000000>, - <75000000 300000000>, - <0 0>, - <0 0>, - <0 0>; - - lanes-per-direction = <1>; - - qcom,msm-bus,name = "ufs1"; - qcom,msm-bus,num-cases = <22>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-KBps = - <95 512 0 0>, <1 650 0 0>, /* No vote */ - <95 512 922 0>, <1 650 1000 0>, /* PWM G1 */ - <95 512 1844 0>, <1 650 1000 0>, /* PWM G2 */ - <95 512 3688 0>, <1 650 1000 0>, /* PWM G3 */ - <95 512 7376 0>, <1 650 1000 0>, /* PWM G4 */ - <95 512 1844 0>, <1 650 1000 0>, /* PWM G1 L2 */ - <95 512 3688 0>, <1 650 1000 0>, /* PWM G2 L2 */ - <95 512 7376 0>, <1 650 1000 0>, /* PWM G3 L2 */ - <95 512 14752 0>, <1 650 1000 0>, /* PWM G4 L2 */ - <95 512 127796 0>, <1 650 1000 0>, /* HS G1 RA */ - <95 512 255591 0>, <1 650 1000 0>, /* HS G2 RA */ - <95 512 511181 0>, <1 650 1000 0>, /* HS G3 RA */ - <95 512 255591 0>, <1 650 1000 0>, /* HS G1 RA L2 */ - <95 512 511181 0>, <1 650 1000 0>, /* HS G2 RA L2 */ - <95 512 1022362 0>, <1 650 1000 0>, /* HS G3 RA L2 */ - <95 512 149422 0>, <1 650 1000 0>, /* HS G1 RB */ - <95 512 298189 0>, <1 650 1000 0>, /* HS G2 RB */ - <95 512 596378 0>, <1 650 1000 0>, /* HS G3 RB */ - <95 512 298189 0>, <1 650 1000 0>, /* HS G1 RB L2 */ - <95 512 596378 0>, <1 650 1000 0>, /* HS G2 RB L2 */ - <95 512 1192756 0>, <1 650 1000 0>, /* HS G3 RB L2 */ - <95 512 4096000 0>, <1 650 1000 0>; /* Max. bandwidth */ - qcom,bus-vector-names = "MIN", - "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", - "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", - "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", - "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", - "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", - "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", - "MAX"; - - /* PM QoS */ - qcom,pm-qos-cpu-groups = <0x0F 0xF0>; - qcom,pm-qos-cpu-group-latency-us = <70 70>; - qcom,pm-qos-default-cpu = <0>; - - resets = <&clock_gcc UFS_BCR>; - reset-names = "core_reset"; - - status = "disabled"; - }; - - usb3: ssusb@a800000 { - compatible = "qcom,dwc-usb3-msm"; - reg = <0x0a800000 0xf8c00>, - <0x0c016000 0x400>; - reg-names = "core_base", "ahb2phy_base"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - interrupts = <0 347 0>, <0 243 0>, <0 180 0>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", "pwr_event_irq"; - - USB3_GDSC-supply = <&gdsc_usb30>; - qcom,usb-dbm = <&dbm_1p5>; - qcom,msm-bus,name = "usb3"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <61 512 0 0>, - <61 512 240000 800000>; - - qcom,dwc-usb3-msm-tx-fifo-size = <21288>; - extcon = <&pmfalcon_pdphy>; - - clocks = <&clock_gcc clk_gcc_usb30_master_clk>, - <&clock_gcc clk_gcc_cfg_noc_usb3_axi_clk>, - <&clock_gcc clk_gcc_aggre1_usb3_axi_clk>, - <&clock_gcc clk_gcc_usb30_mock_utmi_clk>, - <&clock_gcc clk_gcc_usb30_sleep_clk>, - <&clock_gcc clk_cxo_dwc3_clk>; - - clock-names = "core_clk", "iface_clk", "bus_aggr_clk", - "utmi_clk", "sleep_clk", "xo"; - - qcom,core-clk-rate = <120000000>; - - resets = <&clock_gcc USB_30_BCR>; - reset-names = "core_reset"; - - dwc3@a800000 { - compatible = "snps,dwc3"; - reg = <0x0a800000 0xcd00>; - interrupt-parent = <&intc>; - interrupts = <0 131 0>; - usb-phy = <&qusb_phy0>, <&ssphy>; - tx-fifo-resize; - snps,nominal-elastic-buffer; - snps,hird_thresh = <0x10>; - snps,num-gsi-evt-buffs = <0x3>; - }; - - qcom,usbbam@a904000 { - compatible = "qcom,usb-bam-msm"; - reg = <0xa904000 0x17000>; - interrupt-parent = <&intc>; - interrupts = <0 132 0>; - - qcom,bam-type = <0>; - qcom,usb-bam-fifo-baseaddr = <0x146bb000>; - qcom,usb-bam-num-pipes = <8>; - qcom,ignore-core-reset-ack; - qcom,disable-clk-gating; - qcom,usb-bam-override-threshold = <0x4001>; - qcom,usb-bam-max-mbps-highspeed = <400>; - qcom,usb-bam-max-mbps-superspeed = <3600>; - qcom,reset-bam-on-connect; - - qcom,pipe0 { - label = "ssusb-qdss-in-0"; - qcom,usb-bam-mem-type = <2>; - qcom,dir = <1>; - qcom,pipe-num = <0>; - qcom,peer-bam = <0>; - qcom,peer-bam-physical-address = <0x6064000>; - qcom,src-bam-pipe-index = <0>; - qcom,dst-bam-pipe-index = <0>; - qcom,data-fifo-offset = <0x0>; - qcom,data-fifo-size = <0x1800>; - qcom,descriptor-fifo-offset = <0x1800>; - qcom,descriptor-fifo-size = <0x800>; - }; - }; - }; - - qusb_phy0: qusb@c012000 { - compatible = "qcom,qusb2phy-v2"; - reg = <0x0c012000 0x2a8>, - <0x01fcb24c 0x4>; - reg-names = "qusb_phy_base", - "tcsr_clamp_dig_n_1p8"; - vdd-supply = <&pm2falcon_l1>; - vdda18-supply = <&pm2falcon_l10>; - vdda33-supply = <&pm2falcon_l7>; - qcom,vdd-voltage-level = <0 880000 880000>; - qcom,qusb-phy-init-seq = - /* */ - <0x80 0x0 - 0x13 0x04 - 0x7c 0x18c - 0x80 0x2c - 0x0a 0x184 - 0x00 0x240>; - phy_type= "utmi"; - - clocks = <&clock_gcc clk_ln_bb_clk1>, - <&clock_gcc clk_gcc_rx1_usb2_clkref_clk>; - clock-names = "ref_clk_src", "ref_clk"; - - resets = <&clock_gcc QUSB2PHY_PRIM_BCR>; - reset-names = "phy_reset"; - }; - - ssphy: ssphy@c010000 { - compatible = "qcom,usb-ssphy-qmp-v2"; - reg = <0x0c010000 0xe0c>, - <0x01fcb244 0x4>, - <0x01fcb248 0x4>; - reg-names = "qmp_phy_base", - "vls_clamp_reg", - "tcsr_usb3_dp_phymode"; - vdd-supply = <&pm2falcon_l1>; - core-supply = <&pmfalcon_l1>; - qcom,vdd-voltage-level = <0 880000 880000>; - qcom,vbus-valid-override; - qcom,qmp-phy-init-seq = - /* */ - <0x138 0x30 0x00 - 0x034 0x04 0x01 - 0x080 0x14 0x00 - 0x03c 0x06 0x00 - 0x08c 0x08 0x00 - 0x15c 0x06 0x00 - 0x164 0x01 0x00 - 0x13c 0x80 0x00 - 0x0b0 0x82 0x00 - 0x0b8 0xab 0x00 - 0x0bc 0xea 0x00 - 0x0c0 0x02 0x00 - 0x060 0x06 0x00 - 0x068 0x16 0x00 - 0x070 0x36 0x00 - 0x0dc 0x00 0x00 - 0x0d8 0x3f 0x00 - 0x0f8 0x01 0x00 - 0x0f4 0xc9 0x00 - 0x148 0x0a 0x00 - 0x0a0 0x00 0x00 - 0x09c 0x34 0x00 - 0x098 0x15 0x00 - 0x090 0x04 0x00 - 0x154 0x00 0x00 - 0x094 0x00 0x00 - 0x0f0 0x00 0x00 - 0x00c 0x0a 0x00 - 0x048 0x07 0x00 - 0x0d0 0x80 0x00 - 0x184 0x01 0x00 - 0x010 0x01 0x00 - 0x01c 0x31 0x00 - 0x020 0x01 0x00 - 0x014 0x00 0x00 - 0x018 0x00 0x00 - 0x024 0x85 0x00 - 0x028 0x07 0x00 - 0x430 0x0b 0x00 - 0x4d4 0x0f 0x00 - 0x4d8 0x4e 0x00 - 0x4dc 0x18 0x00 - 0x4f8 0x07 0x00 - 0x4fc 0x80 0x00 - 0x504 0x43 0x00 - 0x50c 0x1c 0x00 - 0x434 0x75 0x00 - 0x43c 0x00 0x00 - 0x440 0x00 0x00 - 0x444 0x80 0x00 - 0x408 0x0a 0x00 - 0x414 0x06 0x00 - 0x500 0x00 0x00 - 0x4c0 0x03 0x00 - 0x564 0x05 0x00 - 0x830 0x0b 0x00 - 0x8d4 0x0f 0x00 - 0x8d8 0x4e 0x00 - 0x8dc 0x18 0x00 - 0x8f8 0x07 0x00 - 0x8fc 0x80 0x00 - 0x904 0x43 0x00 - 0x90c 0x1c 0x00 - 0x834 0x75 0x00 - 0x83c 0x00 0x00 - 0x840 0x00 0x00 - 0x844 0x80 0x00 - 0x808 0x0a 0x00 - 0x814 0x06 0x00 - 0x900 0x00 0x00 - 0x8c0 0x03 0x00 - 0x964 0x05 0x00 - 0x260 0x10 0x00 - 0x2a4 0x12 0x00 - 0x28c 0x16 0x00 - 0x244 0x00 0x00 - 0x660 0x10 0x00 - 0x6a4 0x12 0x00 - 0x68c 0x16 0x00 - 0x644 0x00 0x00 - 0xcc8 0x83 0x00 - 0xccc 0x09 0x00 - 0xcd0 0xa2 0x00 - 0xcd4 0x40 0x00 - 0xcc4 0x02 0x00 - 0xc80 0xd1 0x00 - 0xc84 0x1f 0x00 - 0xc88 0x47 0x00 - 0xc64 0x1b 0x00 - 0xc0c 0x9f 0x00 - 0xc10 0x9f 0x00 - 0xc14 0xb7 0x00 - 0xc18 0x4e 0x00 - 0xc1c 0x65 0x00 - 0xc20 0x6b 0x00 - 0xc24 0x15 0x00 - 0xc28 0x0d 0x00 - 0xc2c 0x15 0x00 - 0xc30 0x0d 0x00 - 0xc34 0x15 0x00 - 0xc38 0x0d 0x00 - 0xc3c 0x15 0x00 - 0xc40 0x0d 0x00 - 0xc44 0x15 0x00 - 0xc48 0x0d 0x00 - 0xc4c 0x15 0x00 - 0xc50 0x0d 0x00 - 0xc5c 0x02 0x00 - 0xca0 0x04 0x00 - 0xc8c 0x44 0x00 - 0xc70 0xe7 0x00 - 0xc74 0x03 0x00 - 0xc78 0x40 0x00 - 0xc7c 0x00 0x00 - 0xdd8 0x8a 0x00 - 0xcb8 0x75 0x00 - 0xcb0 0x86 0x00 - 0xcbc 0x13 0x00 - 0xffffffff 0xffffffff 0x00>; - - qcom,qmp-phy-reg-offset = - <0xd74 /* USB3_PHY_PCS_STATUS */ - 0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */ - 0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */ - 0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */ - 0xc00 /* USB3_PHY_SW_RESET */ - 0xc08 /* USB3_PHY_START */ - 0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */ - - clocks = <&clock_gcc clk_gcc_usb3_phy_aux_clk>, - <&clock_gcc clk_gcc_usb3_phy_pipe_clk>, - <&clock_gcc clk_ln_bb_clk1>, - <&clock_gcc clk_gcc_usb3_clkref_clk>; - - clock-names = "aux_clk", "pipe_clk", "ref_clk_src", - "ref_clk"; - - resets = <&clock_gcc USB3_PHY_BCR>, - <&clock_gcc USB3PHY_PHY_BCR>; - reset-names = "phy_reset", "phy_phy_reset"; - }; - - usb_audio_qmi_dev { - compatible = "qcom,usb-audio-qmi-dev"; - iommus = <&lpass_q6_smmu 12>; - qcom,usb-audio-stream-id = <12>; - qcom,usb-audio-intr-num = <2>; - }; - - dbm_1p5: dbm@a8f8000 { - compatible = "qcom,usb-dbm-1p5"; - reg = <0xa8f8000 0x300>; - qcom,reset-ep-after-lpm-resume; - }; - - usb_nop_phy: usb_nop_phy { - compatible = "usb-nop-xceiv"; - }; - - qcom,lpass@17300000 { - compatible = "qcom,pil-tz-generic"; - reg = <0x17300000 0x00100>; - interrupts = <0 162 1>; - - vdd_cx-supply = <&pm2falcon_s3_level>; - qcom,proxy-reg-names = "vdd_cx"; - qcom,vdd_cx-uV-uA = ; - - clocks = <&clock_gcc clk_cxo_pil_lpass_clk>; - clock-names = "xo"; - qcom,proxy-clock-names = "xo"; - - qcom,pas-id = <1>; - qcom,proxy-timeout-ms = <10000>; - qcom,smem-id = <423>; - qcom,sysmon-id = <1>; - status = "ok"; - qcom,ssctl-instance-id = <0x14>; - qcom,firmware-name = "adsp"; - memory-region = <&pil_adsp_mem>; - - /* GPIO inputs from lpass */ - qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>; - qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>; - qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>; - qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>; - - /* GPIO output to lpass */ - qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>; - }; - - pil_modem: qcom,mss@4080000 { - compatible = "qcom,pil-q6v55-mss"; - reg = <0x4080000 0x100>, - <0x1f63000 0x008>, - <0x1f65000 0x008>, - <0x1f64000 0x008>, - <0x4180000 0x020>, - <0x00179000 0x004>; - reg-names = "qdsp6_base", "halt_q6", "halt_modem", - "halt_nc", "rmb_base", "restart_reg"; - - clocks = <&clock_gcc clk_cxo_clk_src>, - <&clock_gcc clk_gcc_mss_cfg_ahb_clk>, - <&clock_gcc clk_gcc_bimc_mss_q6_axi_clk>, - <&clock_gcc clk_gcc_boot_rom_ahb_clk>, - <&clock_gcc clk_gpll0_out_msscc>, - <&clock_gcc clk_gcc_mss_snoc_axi_clk>, - <&clock_gcc clk_gcc_mss_mnoc_bimc_axi_clk>, - <&clock_gcc clk_qdss_clk>; - clock-names = "xo", "iface_clk", "bus_clk", - "mem_clk", "gpll0_mss_clk", "snoc_axi_clk", - "mnoc_axi_clk", "qdss_clk"; - qcom,proxy-clock-names = "xo", "qdss_clk"; - qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk", - "gpll0_mss_clk", "snoc_axi_clk", - "mnoc_axi_clk"; - - interrupts = <0 448 1>; - vdd_cx-supply = <&pm2falcon_s3_level>; - vdd_cx-voltage = ; - vdd_mx-supply = <&pm2falcon_s5_level>; - vdd_mx-uV = ; - qcom,firmware-name = "modem"; - qcom,pil-self-auth; - qcom,sysmon-id = <0>; - qcom,ssctl-instance-id = <0x12>; - qcom,override-acc; - qcom,qdsp6v62-1-2; - status = "ok"; - memory-region = <&modem_mem>; - qcom,mem-protect-id = <0xF>; - - /* GPIO inputs from mss */ - qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; - qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; - qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; - qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>; - qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>; - - /* GPIO output to mss */ - qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; - }; - - tsens0: tsens@10aa000 { - compatible = "qcom,msm8998-tsens"; - reg = <0x10aa000 0x2000>; - reg-names = "tsens_physical"; - interrupts = <0 458 0>, <0 445 0>; - interrupt-names = "tsens-upper-lower", "tsens-critical"; - qcom,client-id = <0 1 2 3 4 7 8 9 10 11 12 13>; - qcom,sensor-id = <0 1 2 3 4 7 8 9 10 11 12 13>; - qcom,sensors = <12>; - }; - - tsens1: tsens@10ad000 { - compatible = "qcom,msm8998-tsens"; - reg = <0x10ad000 0x2000>; - reg-names = "tsens_physical"; - interrupts = <0 184 0>, <0 430 0>; - interrupt-names = "tsens-upper-lower", "tsens-critical"; - qcom,client-id = <14 15 16 17 18 19 20 21>; - qcom,sensor-id = <0 1 3 4 5 6 7 2>; - qcom,sensors = <8>; - }; - - qcom,sensor-information { - compatible = "qcom,sensor-information"; - sensor_information0: qcom,sensor-information-0 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor0"; - qcom,scaling-factor = <10>; - }; - sensor_information1: qcom,sensor-information-1 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor1"; - qcom,scaling-factor = <10>; - }; - sensor_information2: qcom,sensor-information-2 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor2"; - qcom,scaling-factor = <10>; - }; - sensor_information3: qcom,sensor-information-3 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor3"; - qcom,scaling-factor = <10>; - }; - sensor_information4: qcom,sensor-information-4 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor4"; - qcom,scaling-factor = <10>; - }; - sensor_information7: qcom,sensor-information-7 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor7"; - qcom,scaling-factor = <10>; - }; - sensor_information8: qcom,sensor-information-8 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor8"; - qcom,scaling-factor = <10>; - }; - sensor_information9: qcom,sensor-information-9 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor9"; - qcom,scaling-factor = <10>; - }; - sensor_information10: qcom,sensor-information-10 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor10"; - qcom,scaling-factor = <10>; - }; - sensor_information11: qcom,sensor-information-11 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor11"; - qcom,scaling-factor = <10>; - }; - sensor_information12: qcom,sensor-information-12 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor12"; - qcom,scaling-factor = <10>; - }; - sensor_information13: qcom,sensor-information-13 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor13"; - qcom,scaling-factor = <10>; - qcom,alias-name = "gpu"; - }; - sensor_information14: qcom,sensor-information-14 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor14"; - qcom,scaling-factor = <10>; - }; - sensor_information15: qcom,sensor-information-15 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor15"; - qcom,scaling-factor = <10>; - }; - sensor_information16: qcom,sensor-information-16 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor16"; - qcom,alias-name = "pop_mem"; - qcom,scaling-factor = <10>; - }; - sensor_information17: qcom,sensor-information-17 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor17"; - qcom,scaling-factor = <10>; - }; - sensor_information18: qcom,sensor-information-18 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor18"; - qcom,scaling-factor = <10>; - }; - sensor_information19: qcom,sensor-information-19 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor19"; - qcom,scaling-factor = <10>; - }; - sensor_information20: qcom,sensor-information-20 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor20"; - qcom,scaling-factor = <10>; - }; - sensor_information21: qcom,sensor-information-21 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor21"; - qcom,scaling-factor = <10>; - }; - sensor_information22: qcom,sensor-information-22 { - qcom,sensor-type = "alarm"; - qcom,sensor-name = "pm8994_tz"; - qcom,scaling-factor = <1000>; - }; - sensor_information23: qcom,sensor-information-23 { - qcom,sensor-type = "adc"; - qcom,sensor-name = "msm_therm"; - }; - sensor_information24: qcom,sensor-information-24 { - qcom,sensor-type = "adc"; - qcom,sensor-name = "emmc_therm"; - }; - sensor_information25: qcom,sensor-information-25 { - qcom,sensor-type = "adc"; - qcom,sensor-name = "pa_therm0"; - }; - sensor_information26: qcom,sensor-information-26 { - qcom,sensor-type = "adc"; - qcom,sensor-name = "pa_therm1"; - }; - sensor_information27: qcom,sensor-information-27 { - qcom,sensor-type = "adc"; - qcom,sensor-name = "quiet_therm"; - }; - sensor_information28: qcom,sensor-information-28 { - qcom,sensor-type = "llm"; - qcom,sensor-name = "limits_sensor-01"; - }; - sensor_information29: qcom,sensor-information-29 { - qcom,sensor-type = "llm"; - qcom,sensor-name = "limits_sensor-02"; - }; - }; - - qcom_seecom: qseecom@86600000 { - compatible = "qcom,qseecom"; - reg = <0x86600000 0x2200000>; - reg-names = "secapp-region"; - qcom,hlos-num-ce-hw-instances = <1>; - qcom,hlos-ce-hw-instance = <0>; - qcom,qsee-ce-hw-instance = <0>; - qcom,disk-encrypt-pipe-pair = <2>; - qcom,support-fde; - qcom,no-clock-support; - qcom,appsbl-qseecom-support; - qcom,commonlib64-loaded-by-uefi; - qcom,msm-bus,name = "qseecom-noc"; - qcom,msm-bus,num-cases = <4>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <55 512 0 0>, - <55 512 0 0>, - <55 512 120000 1200000>, - <55 512 393600 3936000>; - clock-names = "core_clk_src", "core_clk", - "iface_clk", "bus_clk"; - clocks = <&clock_gcc clk_ce1_clk>, - <&clock_gcc clk_qseecom_ce1_clk>, - <&clock_gcc clk_gcc_ce1_ahb_m_clk>, - <&clock_gcc clk_gcc_ce1_axi_m_clk>; - qcom,ce-opp-freq = <171430000>; - qcom,qsee-reentrancy-support = <2>; - }; - - qcom_tzlog: tz-log@146BF720 { - compatible = "qcom,tz-log"; - reg = <0x146BF720 0x3000>; - qcom,hyplog-enabled; - hyplog-address-offset = <0x410>; /* 0x066BFB30 */ - hyplog-size-offset = <0x414>; /* 0x066BFB34 */ - }; - - qcom_crypto: qcrypto@1DE0000 { - compatible = "qcom,qcrypto"; - reg = <0x1DE0000 0x20000>, - <0x1DC4000 0x24000>; - reg-names = "crypto-base","crypto-bam-base"; - interrupts = <0 206 0>; - qcom,bam-pipe-pair = <2>; - qcom,ce-hw-instance = <0>; - qcom,ce-device = <0>; - qcom,bam-ee = <0>; - qcom,ce-hw-shared; - qcom,clk-mgmt-sus-res; - qcom,msm-bus,name = "qcrypto-noc"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <55 512 0 0>, - <55 512 3936000 393600>; - clock-names = "core_clk_src", "core_clk", - "iface_clk", "bus_clk"; - clocks = <&clock_gcc clk_qcrypto_ce1_clk>, - <&clock_gcc clk_qcrypto_ce1_clk>, - <&clock_gcc clk_gcc_ce1_ahb_m_clk>, - <&clock_gcc clk_gcc_ce1_axi_m_clk>; - qcom,ce-opp-freq = <171430000>; - qcom,use-sw-aes-cbc-ecb-ctr-algo; - qcom,use-sw-aes-xts-algo; - qcom,use-sw-aes-ccm-algo; - qcom,use-sw-ahash-algo; - qcom,use-sw-aead-algo; - qcom,use-sw-hmac-algo; - }; - - qcom_cedev: qcedev@1DE0000{ - compatible = "qcom,qcedev"; - reg = <0x1DE0000 0x20000>, - <0x1DC4000 0x24000>; - reg-names = "crypto-base","crypto-bam-base"; - interrupts = <0 206 0>; - qcom,bam-pipe-pair = <1>; - qcom,ce-hw-instance = <0>; - qcom,ce-device = <0>; - qcom,ce-hw-shared; - qcom,bam-ee = <0>; - qcom,msm-bus,name = "qcedev-noc"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <55 512 0 0>, - <55 512 3936000 393600>; - clock-names = "core_clk_src", "core_clk", - "iface_clk", "bus_clk"; - clocks = <&clock_gcc clk_qcedev_ce1_clk>, - <&clock_gcc clk_qcedev_ce1_clk>, - <&clock_gcc clk_gcc_ce1_ahb_m_clk>, - <&clock_gcc clk_gcc_ce1_axi_m_clk>; - qcom,ce-opp-freq = <171430000>; - }; - - qcom_rng: qrng@793000 { - compatible = "qcom,msm-rng"; - reg = <0x793000 0x1000>; - qcom,msm-rng-iface-clk; - qcom,no-qrng-config; - qcom,msm-bus,name = "msm-rng-noc"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <1 618 0 0>, /* No vote */ - <1 618 0 800>; /* 100 MB/s */ - clocks = <&clock_gcc clk_gcc_prng_ahb_clk>; - clock-names = "iface_clk"; - }; - - mitigation_profile0: qcom,limit_info-0 { - qcom,temperature-sensor = <&sensor_information1>; - qcom,hotplug-mitigation-enable; - }; - - mitigation_profile1: qcom,limit_info-1 { - qcom,temperature-sensor = <&sensor_information2>; - qcom,hotplug-mitigation-enable; - }; - - mitigation_profile2: qcom,limit_info-2 { - qcom,temperature-sensor = <&sensor_information3>; - qcom,hotplug-mitigation-enable; - }; - - mitigation_profile3: qcom,limit_info-3 { - qcom,temperature-sensor = <&sensor_information4>; - qcom,hotplug-mitigation-enable; - }; - - mitigation_profile4: qcom,limit_info-4 { - qcom,temperature-sensor = <&sensor_information7>; - qcom,hotplug-mitigation-enable; - }; - - mitigation_profile5: qcom,limit_info-5 { - qcom,temperature-sensor = <&sensor_information8>; - qcom,hotplug-mitigation-enable; - }; - - mitigation_profile6: qcom,limit_info-6 { - qcom,temperature-sensor = <&sensor_information9>; - qcom,hotplug-mitigation-enable; - }; - - mitigation_profile7: qcom,limit_info-7 { - qcom,temperature-sensor = <&sensor_information10>; - qcom,hotplug-mitigation-enable; - }; - - qcom,lmh { - compatible = "qcom,lmh_v1"; - interrupts = ; - }; - - qcom,msm-thermal { - compatible = "qcom,msm-thermal"; - qcom,sensor-id = <1>; - qcom,poll-ms = <100>; - qcom,therm-reset-temp = <115>; - qcom,core-limit-temp = <70>; - qcom,core-temp-hysteresis = <10>; - qcom,hotplug-temp = <105>; - qcom,hotplug-temp-hysteresis = <20>; - qcom,online-hotplug-core; - qcom,synchronous-cluster-id = <0 1>; - qcom,synchronous-cluster-map = <0 4 &CPU0 &CPU1 &CPU2 &CPU3>, - <1 4 &CPU4 &CPU5 &CPU6 &CPU7>; - clock-names = "osm"; - clocks = <&clock_cpu clk_pwrcl_clk>; - - qcom,vdd-restriction-temp = <5>; - qcom,vdd-restriction-temp-hysteresis = <10>; - - vdd-dig-supply = <&pm8998_s1_floor_level>; - vdd-gfx-supply = <&gfx_vreg>; - - qcom,vdd-dig-rstr{ - qcom,vdd-rstr-reg = "vdd-dig"; - qcom,levels = ; - /* Nominal, Super Turbo, Super Turbo */ - qcom,min-level = ; - /* No Request */ - }; - - qcom,vdd-gfx-rstr{ - qcom,vdd-rstr-reg = "vdd-gfx"; - qcom,levels = <5 6 6>; /* Nominal, Turbo, Turbo */ - qcom,min-level = <1>; /* No Request */ - }; - - msm_thermal_freq: qcom,vdd-apps-rstr{ - qcom,vdd-rstr-reg = "vdd-apps"; - qcom,levels = <1248000>; - qcom,freq-req; - }; - }; - - qcom,bcl { - compatible = "qcom,bcl"; - qcom,bcl-enable; - qcom,bcl-framework-interface; - qcom,bcl-freq-control-list = <&CPU4 &CPU5 &CPU6 &CPU7>; - qcom,bcl-hotplug-list = <&CPU4 &CPU5 &CPU6 &CPU7>; - qcom,bcl-soc-hotplug-list = <&CPU4 &CPU5 &CPU6 &CPU7>; - qcom,ibat-monitor { - qcom,low-threshold-uamp = <3400000>; - qcom,high-threshold-uamp = <4200000>; - qcom,mitigation-freq-khz = <576000>; - qcom,vph-high-threshold-uv = <3500000>; - qcom,vph-low-threshold-uv = <3300000>; - qcom,soc-low-threshold = <10>; - qcom,thermal-handle = <&msm_thermal_freq>; - }; - }; - - qcom,ssc@5c00000 { - compatible = "qcom,pil-tz-generic"; - reg = <0x5c00000 0x4000>; - interrupts = <0 390 1>; - - vdd_cx-supply = <&pm2falcon_l9_level>; - qcom,vdd_cx-uV-uA = ; - qcom,proxy-reg-names = "vdd_cx"; - qcom,keep-proxy-regs-on; - - clocks = <&clock_gcc clk_cxo_pil_ssc_clk>, - <&clock_gcc clk_aggre2_noc_clk>; - clock-names = "xo", "aggre2"; - qcom,proxy-clock-names = "xo", "aggre2"; - - qcom,pas-id = <12>; - qcom,proxy-timeout-ms = <10000>; - qcom,smem-id = <424>; - qcom,sysmon-id = <3>; - qcom,ssctl-instance-id = <0x16>; - qcom,firmware-name = "slpi"; - status = "ok"; - memory-region = <&pil_slpi_mem>; - - /* GPIO inputs from ssc */ - qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_3_in 0 0>; - qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_3_in 2 0>; - qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_3_in 1 0>; - qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_3_in 3 0>; - - /* GPIO output to ssc */ - qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_3_out 0 0>; - }; - - qcom,venus@cce0000 { - compatible = "qcom,pil-tz-generic"; - reg = <0xcce0000 0x4000>; - - vdd-supply = <&gdsc_venus>; - qcom,proxy-reg-names = "vdd"; - - clocks = <&clock_mmss clk_mmss_video_core_clk>, - <&clock_mmss clk_mmss_mnoc_ahb_clk>, - <&clock_mmss clk_mmss_video_ahb_clk>, - <&clock_gcc clk_mmssnoc_axi_clk>, - <&clock_mmss clk_mmss_video_axi_clk>, - <&clock_mmss clk_mmss_video_maxi_clk>; - clock-names = "core_clk", "mnoc_ahb_clk", "iface_clk", - "noc_axi_clk", "bus_clk", "maxi_clk"; - qcom,proxy-clock-names = "core_clk","mnoc_ahb_clk", - "iface_clk", "noc_axi_clk", "bus_clk", "maxi_clk"; - - qcom,pas-id = <9>; - qcom,msm-bus,name = "pil-venus"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <63 512 0 0>, - <63 512 0 304000>; - qcom,proxy-timeout-ms = <100>; - qcom,firmware-name = "venus"; - memory-region = <&pil_video_mem>; - status = "ok"; - }; - - wdog: qcom,wdt@17817000 { - compatible = "qcom,msm-watchdog"; - reg = <0x17817000 0x1000>; - reg-names = "wdt-base"; - interrupts = <0 3 0>, <0 4 0>; - qcom,bark-time = <11000>; - qcom,pet-time = <10000>; - qcom,ipi-ping; - qcom,wakeup-enable; - qcom,scandump-size = <0x40000>; - }; - - qcom,spss@1d00000 { - compatible = "qcom,pil-tz-generic"; - reg = <0x1d0101c 0x4>, - <0x1d01024 0x4>, - <0x1d01028 0x4>, - <0x1d0103c 0x4>, - <0x1d02030 0x4>; - reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", - "sp2soc_irq_mask", "rmb_err", "rmb_err_spare2"; - interrupts = <0 352 1>; - - vdd_cx-supply = <&pm8998_s1_level>; - qcom,proxy-reg-names = "vdd_cx"; - qcom,vdd_cx-uV-uA = ; - - clocks = <&clock_gcc clk_cxo_pil_spss_clk>; - clock-names = "xo"; - qcom,proxy-clock-names = "xo"; - qcom,pil-generic-irq-handler; - status = "ok"; - - qcom,pas-id = <14>; - qcom,proxy-timeout-ms = <10000>; - qcom,firmware-name = "spss"; - memory-region = <&spss_mem>; - qcom,spss-scsr-bits = <24 25>; - }; - - qcom,msm-rtb { - compatible = "qcom,msm-rtb"; - qcom,rtb-size = <0x100000>; - }; - - qcom,mpm2-sleep-counter@10a3000 { - compatible = "qcom,mpm2-sleep-counter"; - reg = <0x010a3000 0x1000>; - clock-frequency = <32768>; - }; - - qcom,msm-imem@146bf000 { - compatible = "qcom,msm-imem"; - reg = <0x146bf000 0x1000>; - ranges = <0x0 0x146bf000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - mem_dump_table@10 { - compatible = "qcom,msm-imem-mem_dump_table"; - reg = <0x10 8>; - }; - - dload_type@18 { - compatible = "qcom,msm-imem-dload-type"; - reg = <0x18 4>; - }; - - restart_reason@65c { - compatible = "qcom,msm-imem-restart_reason"; - reg = <0x65c 4>; - }; - - boot_stats@6b0 { - compatible = "qcom,msm-imem-boot_stats"; - reg = <0x6b0 32>; - }; - - pil@94c { - compatible = "qcom,msm-imem-pil"; - reg = <0x94c 200>; - }; - - diag_dload@c8 { - compatible = "qcom,msm-imem-diag-dload"; - reg = <0xc8 200>; - }; - }; - - cpu_pmu: cpu-pmu { - compatible = "arm,armv8-pmuv3"; - qcom,irq-is-percpu; - interrupts = <1 6 4>; - }; - - cpuss_dump { - compatible = "qcom,cpuss-dump"; - qcom,l1_i_cache0 { - qcom,dump-node = <&L1_I_0>; - qcom,dump-id = <0x60>; - }; - qcom,l1_i_cache1 { - qcom,dump-node = <&L1_I_1>; - qcom,dump-id = <0x61>; - }; - qcom,l1_i_cache2 { - qcom,dump-node = <&L1_I_2>; - qcom,dump-id = <0x62>; - }; - qcom,l1_i_cache3 { - qcom,dump-node = <&L1_I_3>; - qcom,dump-id = <0x63>; - }; - qcom,l1_i_cache100 { - qcom,dump-node = <&L1_I_100>; - qcom,dump-id = <0x64>; - }; - qcom,l1_i_cache101 { - qcom,dump-node = <&L1_I_101>; - qcom,dump-id = <0x65>; - }; - qcom,l1_i_cache102 { - qcom,dump-node = <&L1_I_102>; - qcom,dump-id = <0x66>; - }; - qcom,l1_i_cache103 { - qcom,dump-node = <&L1_I_103>; - qcom,dump-id = <0x67>; - }; - qcom,l1_d_cache0 { - qcom,dump-node = <&L1_D_0>; - qcom,dump-id = <0x80>; - }; - qcom,l1_d_cache1 { - qcom,dump-node = <&L1_D_1>; - qcom,dump-id = <0x81>; - }; - qcom,l1_d_cache2 { - qcom,dump-node = <&L1_D_2>; - qcom,dump-id = <0x82>; - }; - qcom,l1_d_cache3 { - qcom,dump-node = <&L1_D_3>; - qcom,dump-id = <0x83>; - }; - qcom,l1_d_cache100 { - qcom,dump-node = <&L1_D_100>; - qcom,dump-id = <0x84>; - }; - qcom,l1_d_cache101 { - qcom,dump-node = <&L1_D_101>; - qcom,dump-id = <0x85>; - }; - qcom,l1_d_cache102 { - qcom,dump-node = <&L1_D_102>; - qcom,dump-id = <0x86>; - }; - qcom,l1_d_cache103 { - qcom,dump-node = <&L1_D_103>; - qcom,dump-id = <0x87>; - }; - }; - - qcom,msm-ssc-sensors { - compatible = "qcom,msm-ssc-sensors"; - status = "ok"; - }; - - dcc: dcc@10b3000 { - compatible = "qcom,dcc"; - reg = <0x10b3000 0x1000>, - <0x10b4000 0x2000>; - reg-names = "dcc-base", "dcc-ram-base"; - - clocks = <&clock_gcc clk_gcc_dcc_ahb_clk>; - clock-names = "dcc_clk"; - }; - - qcom,msm-core@780000 { - compatible = "qcom,apss-core-ea"; - reg = <0x780000 0x1000>; - qcom,low-hyst-temp = <10>; - qcom,high-hyst-temp = <5>; - qcom,polling-interval = <50>; - - ea0: ea0 { - sensor = <&sensor_information1>; - }; - - ea1: ea1 { - sensor = <&sensor_information2>; - }; - - ea2: ea2 { - sensor = <&sensor_information3>; - }; - - ea3: ea3 { - sensor = <&sensor_information4>; - }; - - ea4: ea4 { - sensor = <&sensor_information7>; - }; - - ea5: ea5 { - sensor = <&sensor_information8>; - }; - - ea6: ea6 { - sensor = <&sensor_information9>; - }; - - ea7: ea7 { - sensor = <&sensor_information10>; - }; - - }; - - qcom,icnss@18800000 { - compatible = "qcom,icnss"; - reg = <0x18800000 0x800000>, - <0x10AC000 0x20>, - <0xa0000000 0x10000000>, - <0xb0000000 0x10000>; - reg-names = "membase", "mpm_config", - "smmu_iova_base", "smmu_iova_ipa"; - iommus = <&anoc2_smmu 0x1900>, - <&anoc2_smmu 0x1901>; - interrupts = <0 413 0 /* CE0 */ >, - <0 414 0 /* CE1 */ >, - <0 415 0 /* CE2 */ >, - <0 416 0 /* CE3 */ >, - <0 417 0 /* CE4 */ >, - <0 418 0 /* CE5 */ >, - <0 420 0 /* CE6 */ >, - <0 421 0 /* CE7 */ >, - <0 422 0 /* CE8 */ >, - <0 423 0 /* CE9 */ >, - <0 424 0 /* CE10 */ >, - <0 425 0 /* CE11 */ >; - qcom,wlan-msa-memory = <0x100000>; - qcom,icnss-vadc = <&pmfalcon_vadc>; - qcom,icnss-adc_tm = <&pmfalcon_adc_tm>; - }; - - tspp: msm_tspp@0c1e7000 { - compatible = "qcom,msm_tspp"; - reg = <0x0c1e7000 0x200>, /* MSM_TSIF0_PHYS */ - <0x0c1e8000 0x200>, /* MSM_TSIF1_PHYS */ - <0x0c1e9000 0x1000>, /* MSM_TSPP_PHYS */ - <0x0c1c4000 0x23000>; /* MSM_TSPP_BAM_PHYS */ - reg-names = "MSM_TSIF0_PHYS", - "MSM_TSIF1_PHYS", - "MSM_TSPP_PHYS", - "MSM_TSPP_BAM_PHYS"; - interrupts = <0 121 0>, /* TSIF_TSPP_IRQ */ - <0 119 0>, /* TSIF0_IRQ */ - <0 120 0>, /* TSIF1_IRQ */ - <0 122 0>; /* TSIF_BAM_IRQ */ - interrupt-names = "TSIF_TSPP_IRQ", - "TSIF0_IRQ", - "TSIF1_IRQ", - "TSIF_BAM_IRQ"; - - clock-names = "iface_clk", "ref_clk"; - clocks = <&clock_gcc clk_gcc_tsif_ahb_clk>, - <&clock_gcc clk_gcc_tsif_ref_clk>; - - qcom,msm-bus,name = "tsif"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <82 512 0 0>, /* No vote */ - <82 512 12288 24576>; - /* Max. bandwidth, 2xTSIF, each max of 96Mbps */ - - pinctrl-names = "disabled", - "tsif0-mode1", "tsif0-mode2", - "tsif1-mode1", "tsif1-mode2", - "dual-tsif-mode1", "dual-tsif-mode2"; - - pinctrl-0 = <>; /* disabled */ - pinctrl-1 = <&tsif0_signals_active>; /* tsif0-mode1 */ - pinctrl-2 = <&tsif0_signals_active - &tsif0_sync_active>; /* tsif0-mode2 */ - pinctrl-3 = <&tsif1_signals_active>; /* tsif1-mode1 */ - pinctrl-4 = <&tsif1_signals_active - &tsif1_sync_active>; /* tsif1-mode2 */ - pinctrl-5 = <&tsif0_signals_active - &tsif1_signals_active>; /* dual-tsif-mode1 */ - pinctrl-6 = <&tsif0_signals_active - &tsif0_sync_active - &tsif1_signals_active - &tsif1_sync_active>; /* dual-tsif-mode2 */ - }; - - wil6210: qcom,wil6210 { - compatible = "qcom,wil6210"; - qcom,pcie-parent = <&pcie0>; - qcom,wigig-en = <&tlmm 80 0>; - qcom,msm-bus,name = "wil6210"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <45 512 0 0>, - <45 512 600000 800000>; /* ~4.6Gbps (MCS12) */ - qcom,use-ext-supply; - vdd-supply= <&pm8998_s7>; - vddio-supply= <&pm8998_s5>; - qcom,use-ext-clocks; - clocks = <&clock_gcc clk_rf_clk3>, - <&clock_gcc clk_rf_clk3_pin>; - clock-names = "rf_clk3_clk", "rf_clk3_pin_clk"; - qcom,smmu-support; - status = "disabled"; - }; - - qcom,qsee_ipc_irq_bridge { - compatible = "qcom,qsee-ipc-irq-bridge"; - - qcom,qsee-ipc-irq-spss { - qcom,rx-irq-clr = <0x1d08008 0x4>; - qcom,rx-irq-clr-mask = <0x1>; - qcom,dev-name = "qsee_ipc_irq_spss"; - interrupts = <0 349 4>; - label = "spss"; - }; - }; -}; - -&clock_cpu { - lmh_dcvs0: qcom,limits-dcvs@0 { - compatible = "qcom,msm-hw-limits"; - interrupts = ; - }; - - lmh_dcvs1: qcom,limits-dcvs@1 { - compatible = "qcom,msm-hw-limits"; - interrupts = ; - }; -}; - -&gdsc_usb30 { - status = "ok"; -}; - -&gdsc_pcie_0 { - status = "ok"; -}; - -&gdsc_ufs { - status = "ok"; -}; - -&gdsc_bimc_smmu { - clock-names = "bus_clk"; - clocks = <&clock_mmss clk_mmss_bimc_smmu_axi_clk>; - proxy-supply = <&gdsc_bimc_smmu>; - qcom,proxy-consumer-enable; - status = "ok"; -}; - -&gdsc_hlos1_vote_lpass_adsp { - status = "ok"; -}; - -&gdsc_hlos1_vote_lpass_core { - status = "ok"; -}; - -&gdsc_venus { - status = "ok"; -}; - -&gdsc_venus_core0 { - status = "ok"; - qcom,support-hw-trigger; -}; - -&gdsc_venus_core1 { - status = "ok"; - qcom,support-hw-trigger; -}; - -&gdsc_camss_top { - status = "ok"; -}; - -&gdsc_vfe0 { - parent-supply = <&gdsc_camss_top>; - status = "ok"; -}; - -&gdsc_vfe1 { - parent-supply = <&gdsc_camss_top>; - status = "ok"; -}; - -&gdsc_cpp { - parent-supply = <&gdsc_camss_top>; - status = "ok"; -}; - -&gdsc_mdss { - proxy-supply = <&gdsc_mdss>; - qcom,proxy-consumer-enable; - status = "ok"; -}; - -&gdsc_gpu_gx { - clock-names = "core_root_clk"; - clocks = <&clock_gfx clk_gfx3d_clk_src>; - qcom,force-enable-root-clk; - parent-supply = <&gfx_vreg>; - status = "ok"; -}; - -&gdsc_gpu_cx { - status = "ok"; -}; - -#include "msm-pm8998.dtsi" -#include "msm-pmi8998.dtsi" -#include "msm-pm8005.dtsi" -#include "msm-pm8998-rpm-regulator.dtsi" -#include "msm8998-regulator.dtsi" - -#include "msm8998-pm.dtsi" -#include "msm-arm-smmu-8998.dtsi" -#include "msm-arm-smmu-impl-defs-8998.dtsi" -#include "msm8998-ion.dtsi" -#include "msm8998-camera.dtsi" -#include "msm8998-vidc.dtsi" -#include "msm8998-coresight.dtsi" -#include "msm8998-bus.dtsi" -#include "msm8998-gpu.dtsi" -#include "msm8998-pinctrl.dtsi" -#include "msm8998-mdss.dtsi" -#include "msm8998-mdss-pll.dtsi" -#include "msm8998-blsp.dtsi" -#include "msm-smb138x.dtsi" - -/* GPU overrides */ -&msm_gpu { - qcom,initial-pwrlevel = <0>; - - qcom,gpu-pwrlevels { - #address-cells = <1>; - #size-cells = <0>; - - compatible = "qcom,gpu-pwrlevels"; - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <332000000>; - qcom,bus-freq = <7>; - qcom,bus-min = <6>; - qcom,bus-max = <8>; - }; - - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <251000000>; - qcom,bus-freq = <4>; - qcom,bus-min = <3>; - qcom,bus-max = <5>; - }; - - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <171000000>; - qcom,bus-freq = <3>; - qcom,bus-min = <1>; - qcom,bus-max = <4>; - }; - - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <27000000>; - qcom,bus-freq = <0>; - qcom,bus-min = <0>; - qcom,bus-max = <0>; - }; - }; - -}; diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-pm660.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-pm660.dtsi new file mode 100644 index 000000000000..d29faacab5ee --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-pm660.dtsi @@ -0,0 +1,241 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&slim_aud { + tasha_codec { + /delete-property/cdc-vdd-buck-supply; + /delete-property/cdc-buck-sido-supply; + /delete-property/cdc-vdd-tx-h-supply; + /delete-property/cdc-vdd-rx-h-supply; + /delete-property/cdc-vddpx-1-supply; + }; + + tavil_codec { + /delete-property/cdc-vdd-buck-supply; + /delete-property/cdc-buck-sido-supply; + /delete-property/cdc-vdd-tx-h-supply; + /delete-property/cdc-vdd-rx-h-supply; + /delete-property/cdc-vddpx-1-supply; + }; +}; + + +&led_flash0 { + /delete-property/qcom,flash-source; + /delete-property/qcom,torch-source; + /delete-property/qcom,switch-source; +}; + +&led_flash1 { + /delete-property/qcom,flash-source; + /delete-property/qcom,torch-source; + /delete-property/qcom,switch-source; +}; + + +&eeprom1 { + /delete-property/cam_vio-supply; + /delete-property/cam_vana-supply; + /delete-property/cam_vdig-supply; +}; + +&eeprom2 { + /delete-property/cam_vio-supply; + /delete-property/cam_vana-supply; + /delete-property/cam_vdig-supply; + /delete-property/gpios; +}; + +&cci { + /delete-node/qcom,camera@1; + /delete-node/qcom,camera@2; + +}; + +&sdhc_2 { + /delete-property/vdd-supply; + /delete-property/vdd-io-supply; +}; + +&i2c_5 { + /delete-node/synaptics@20; +}; + +&i2c_6 { + /delete-node/nq@28; +}; + +&i2c_7 { + /delete-node/qcom,smb138x@8; +}; + +&clock_gcc { + /delete-property/vdd_dig-supply; + /delete-property/vdd_dig_ao-supply; +}; + +&clock_mmss { + /delete-property/vdd_dig-supply; + /delete-property/vdd_mmsscc_mx-supply; +}; + +&clock_gpu { + /delete-property/vdd_dig-supply; +}; + +&clock_gfx { + /delete-property/vdd_mx-supply; + /delete-property/vdd_gpu_mx-supply; +}; + +&pcie0 { + /delete-property/vreg-1.8-supply; + /delete-property/vreg-0.9-supply; + /delete-property/vreg-cx-supply; +}; + +&qusb_phy0 { + /delete-property/vdd-supply; + /delete-property/vdda18-supply; + /delete-property/vdda33-supply; +}; + +&ssphy { + /delete-property/vdd-supply; + /delete-property/core-supply; +}; + +&usb3 { + /delete-property/extcon; +}; + +&mdss_dsi { + /delete-property/vdda-1p2-supply; + /delete-property/vdda-0p9-supply; +}; + +&mdss_dsi0 { + /delete-property/wqhd-vddio-supply; + /delete-property/lab-supply; + /delete-property/ibb-supply; +}; + +&mdss_dsi1 { + /delete-property/wqhd-vddio-supply; + /delete-property/lab-supply; + /delete-property/ibb-supply; +}; + +&mdss_dp_ctrl { + /delete-property/vdda-1p2-supply; + /delete-property/vdda-0p9-supply; + /delete-property/qcom,dp-usbpd-detection; +}; + +&mdss_hdmi_pll { + /delete-property/vdda-pll-supply; + /delete-property/vdda-phy-supply; +}; + +&apc0_cpr { + /* disable aging and closed-loop */ + /delete-property/vdd-supply; + /delete-property/qcom,cpr-enable; + /delete-property/qcom,cpr-hw-closed-loop; + /delete-property/qcom,cpr-aging-ref-voltage; +}; + +&apc0_pwrcl_vreg { + /delete-property/qcom,cpr-aging-max-voltage-adjustment; + /delete-property/qcom,cpr-aging-ref-corner; + /delete-property/qcom,cpr-aging-ro-scaling-factor; + /delete-property/qcom,allow-aging-voltage-adjustment; + /delete-property/qcom,allow-aging-open-loop-voltage-adjustment; +}; + +&apc1_cpr { + /* disable aging and closed-loop */ + /delete-property/vdd-supply; + /delete-property/qcom,cpr-enable; + /delete-property/qcom,cpr-hw-closed-loop; + /delete-property/qcom,cpr-aging-ref-voltage; +}; + +&apc1_perfcl_vreg { + /delete-property/qcom,cpr-aging-max-voltage-adjustment; + /delete-property/qcom,cpr-aging-ref-corner; + /delete-property/qcom,cpr-aging-ro-scaling-factor; + /delete-property/qcom,allow-aging-voltage-adjustment; + /delete-property/qcom,allow-aging-open-loop-voltage-adjustment; +}; + +&gfx_cpr { + status = "disabled"; + + /* disable aging and closed-loop */ + /delete-property/vdd-supply; + /delete-property/qcom,cpr-enable; + /delete-property/qcom,cpr-aging-ref-voltage; + /delete-property/qcom,cpr-aging-allowed-reg-mask; + /delete-property/qcom,cpr-aging-allowed-reg-value; +}; + +&gfx_vreg { + status = "disabled"; + + /delete-property/qcom,cpr-aging-max-voltage-adjustment; + /delete-property/qcom,cpr-aging-ref-corner; + /delete-property/qcom,cpr-aging-ro-scaling-factor; + /delete-property/qcom,allow-aging-voltage-adjustment; + /delete-property/qcom,allow-aging-open-loop-voltage-adjustment; +}; + +&soc { + /delete-node/gpio_keys; + /delete-node/qcom,bcl; + /delete-node/qcom,msm-thermal; + /delete-node/qcom,spss@1d00000; + /delete-node/qcom,wil6210; + /delete-node/qcom,rpm-smd; + /delete-node/qcom,spmi@800f000; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-glink"; + qcom,glink-edge = "rpm"; + rpm-channel-name = "rpm_requests"; + }; + + spmi_bus: qcom,spmi@800f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x800f000 0x1000>, + <0x8400000 0x1000000>, + <0x9400000 0x1000000>, + <0xa400000 0x220000>, + <0x800a000 0x3000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; +}; + +#include "msm-pm660.dtsi" +#include "msm-pm660l.dtsi" +#include "msm-pm660-rpm-regulator.dtsi" +#include "msm-pm660l-rpm-regulator.dtsi" +#include "sdm660-regulator.dtsi" diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-pmfalcon.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-pmfalcon.dtsi deleted file mode 100644 index 74f43c15dd72..000000000000 --- a/arch/arm/boot/dts/qcom/msm8998-interposer-pmfalcon.dtsi +++ /dev/null @@ -1,241 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -&slim_aud { - tasha_codec { - /delete-property/cdc-vdd-buck-supply; - /delete-property/cdc-buck-sido-supply; - /delete-property/cdc-vdd-tx-h-supply; - /delete-property/cdc-vdd-rx-h-supply; - /delete-property/cdc-vddpx-1-supply; - }; - - tavil_codec { - /delete-property/cdc-vdd-buck-supply; - /delete-property/cdc-buck-sido-supply; - /delete-property/cdc-vdd-tx-h-supply; - /delete-property/cdc-vdd-rx-h-supply; - /delete-property/cdc-vddpx-1-supply; - }; -}; - - -&led_flash0 { - /delete-property/qcom,flash-source; - /delete-property/qcom,torch-source; - /delete-property/qcom,switch-source; -}; - -&led_flash1 { - /delete-property/qcom,flash-source; - /delete-property/qcom,torch-source; - /delete-property/qcom,switch-source; -}; - - -&eeprom1 { - /delete-property/cam_vio-supply; - /delete-property/cam_vana-supply; - /delete-property/cam_vdig-supply; -}; - -&eeprom2 { - /delete-property/cam_vio-supply; - /delete-property/cam_vana-supply; - /delete-property/cam_vdig-supply; - /delete-property/gpios; -}; - -&cci { - /delete-node/qcom,camera@1; - /delete-node/qcom,camera@2; - -}; - -&sdhc_2 { - /delete-property/vdd-supply; - /delete-property/vdd-io-supply; -}; - -&i2c_5 { - /delete-node/synaptics@20; -}; - -&i2c_6 { - /delete-node/nq@28; -}; - -&i2c_7 { - /delete-node/qcom,smb138x@8; -}; - -&clock_gcc { - /delete-property/vdd_dig-supply; - /delete-property/vdd_dig_ao-supply; -}; - -&clock_mmss { - /delete-property/vdd_dig-supply; - /delete-property/vdd_mmsscc_mx-supply; -}; - -&clock_gpu { - /delete-property/vdd_dig-supply; -}; - -&clock_gfx { - /delete-property/vdd_mx-supply; - /delete-property/vdd_gpu_mx-supply; -}; - -&pcie0 { - /delete-property/vreg-1.8-supply; - /delete-property/vreg-0.9-supply; - /delete-property/vreg-cx-supply; -}; - -&qusb_phy0 { - /delete-property/vdd-supply; - /delete-property/vdda18-supply; - /delete-property/vdda33-supply; -}; - -&ssphy { - /delete-property/vdd-supply; - /delete-property/core-supply; -}; - -&usb3 { - /delete-property/extcon; -}; - -&mdss_dsi { - /delete-property/vdda-1p2-supply; - /delete-property/vdda-0p9-supply; -}; - -&mdss_dsi0 { - /delete-property/wqhd-vddio-supply; - /delete-property/lab-supply; - /delete-property/ibb-supply; -}; - -&mdss_dsi1 { - /delete-property/wqhd-vddio-supply; - /delete-property/lab-supply; - /delete-property/ibb-supply; -}; - -&mdss_dp_ctrl { - /delete-property/vdda-1p2-supply; - /delete-property/vdda-0p9-supply; - /delete-property/qcom,dp-usbpd-detection; -}; - -&mdss_hdmi_pll { - /delete-property/vdda-pll-supply; - /delete-property/vdda-phy-supply; -}; - -&apc0_cpr { - /* disable aging and closed-loop */ - /delete-property/vdd-supply; - /delete-property/qcom,cpr-enable; - /delete-property/qcom,cpr-hw-closed-loop; - /delete-property/qcom,cpr-aging-ref-voltage; -}; - -&apc0_pwrcl_vreg { - /delete-property/qcom,cpr-aging-max-voltage-adjustment; - /delete-property/qcom,cpr-aging-ref-corner; - /delete-property/qcom,cpr-aging-ro-scaling-factor; - /delete-property/qcom,allow-aging-voltage-adjustment; - /delete-property/qcom,allow-aging-open-loop-voltage-adjustment; -}; - -&apc1_cpr { - /* disable aging and closed-loop */ - /delete-property/vdd-supply; - /delete-property/qcom,cpr-enable; - /delete-property/qcom,cpr-hw-closed-loop; - /delete-property/qcom,cpr-aging-ref-voltage; -}; - -&apc1_perfcl_vreg { - /delete-property/qcom,cpr-aging-max-voltage-adjustment; - /delete-property/qcom,cpr-aging-ref-corner; - /delete-property/qcom,cpr-aging-ro-scaling-factor; - /delete-property/qcom,allow-aging-voltage-adjustment; - /delete-property/qcom,allow-aging-open-loop-voltage-adjustment; -}; - -&gfx_cpr { - status = "disabled"; - - /* disable aging and closed-loop */ - /delete-property/vdd-supply; - /delete-property/qcom,cpr-enable; - /delete-property/qcom,cpr-aging-ref-voltage; - /delete-property/qcom,cpr-aging-allowed-reg-mask; - /delete-property/qcom,cpr-aging-allowed-reg-value; -}; - -&gfx_vreg { - status = "disabled"; - - /delete-property/qcom,cpr-aging-max-voltage-adjustment; - /delete-property/qcom,cpr-aging-ref-corner; - /delete-property/qcom,cpr-aging-ro-scaling-factor; - /delete-property/qcom,allow-aging-voltage-adjustment; - /delete-property/qcom,allow-aging-open-loop-voltage-adjustment; -}; - -&soc { - /delete-node/gpio_keys; - /delete-node/qcom,bcl; - /delete-node/qcom,msm-thermal; - /delete-node/qcom,spss@1d00000; - /delete-node/qcom,wil6210; - /delete-node/qcom,rpm-smd; - /delete-node/qcom,spmi@800f000; - - rpm_bus: qcom,rpm-smd { - compatible = "qcom,rpm-glink"; - qcom,glink-edge = "rpm"; - rpm-channel-name = "rpm_requests"; - }; - - spmi_bus: qcom,spmi@800f000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x800f000 0x1000>, - <0x8400000 0x1000000>, - <0x9400000 0x1000000>, - <0xa400000 0x220000>, - <0x800a000 0x3000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - }; -}; - -#include "msm-pmfalcon.dtsi" -#include "msm-pm2falcon.dtsi" -#include "msm-pmfalcon-rpm-regulator.dtsi" -#include "msm-pm2falcon-rpm-regulator.dtsi" -#include "msmfalcon-regulator.dtsi" diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-audio.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-audio.dtsi new file mode 100644 index 000000000000..c117bdbf5578 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-audio.dtsi @@ -0,0 +1,69 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msm-audio.dtsi" +#include "sdm660-audio.dtsi" + +&pm660l_3 { + /delete-node/analog-codec; +}; + +&soc { + /delete-node/msm-sdw-codec@152c1000; + /delete-node/sound; +}; + +&slim_aud { + tasha_codec { + clocks = <&clock_audio clk_audio_pmi_clk>, + <&clock_audio clk_audio_ap_clk2>; + }; + tavil_codec { + clocks = <&clock_audio_lnbb clk_audio_pmi_lnbb_clk>; + }; +}; + +&tasha_hph_en0 { + /delete-property/pinctrl-0; + /delete-property/pinctrl-1; +}; + +&tasha_hph_en1 { + /delete-property/pinctrl-0; + /delete-property/pinctrl-1; +}; + +&clock_audio { + qcom,audio-ref-clk-gpio = <&pm660_gpios 3 0>; + clocks = <&clock_gcc clk_div_clk1>; + pinctrl-0 = <&spkr_i2s_clk_sleep>; + pinctrl-1 = <&spkr_i2s_clk_active>; +}; + +&clock_audio_lnbb { + clocks = <&clock_gcc clk_ln_bb_clk2>; +}; + +&wcd_rst_gpio { + qcom,cdc-rst-n-gpio = <&tlmm 64 0>; + pinctrl-0 = <&cdc_reset_active>; + pinctrl-1 = <&cdc_reset_sleep>; +}; + +&wcd9xxx_intc { + interrupt-parent = <&tlmm>; + qcom,gpio-connect = <&tlmm 54 0>; + pinctrl-names = "default"; + pinctrl-0 = <&wcd_intr_default>; + /delete-property/interrupts; + /delete-property/interrupt-names; +}; diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-cdp.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-cdp.dtsi new file mode 100644 index 000000000000..4bf3dc08ab3e --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-cdp.dtsi @@ -0,0 +1,512 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msm8998-pinctrl.dtsi" +#include "msm8998-camera-sensor-cdp.dtsi" + +&blsp1_uart3_hs { + status = "ok"; +}; + +&ufsphy1 { + vdda-phy-supply = <&pm660l_l1>; + vdda-pll-supply = <&pm660_l1>; + vddp-ref-clk-supply = <&pm660_l1>; + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14600>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; + status = "ok"; +}; + +&ufs1 { + vdd-hba-supply = <&gdsc_ufs>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm660l_l4>; + vccq2-supply = <&pm660_l8>; + vcc-max-microamp = <500000>; + vccq2-max-microamp = <600000>; + status = "ok"; +}; + +&ufs_ice { + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm660l_l5>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm660l_l2>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + qcom,clk-rates = <400000 20000000 25000000 + 50000000 100000000 200000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + + cd-gpios = <&tlmm 95 0x1>; + + status = "ok"; +}; + +&uartblsp2dm1 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&pm8998_gpios { + /* GPIO 5 for Home Key */ + gpio@c400 { + status = "okay"; + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <0>; + qcom,src-sel = <0>; + qcom,out-strength = <1>; + }; + + /* GPIO 6 for Vol+ Key */ + gpio@c500 { + status = "okay"; + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <0>; + qcom,src-sel = <0>; + qcom,out-strength = <1>; + }; + + /* GPIO 7 for Snapshot Key */ + gpio@c600 { + status = "okay"; + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <0>; + qcom,src-sel = <0>; + qcom,out-strength = <1>; + }; + + /* GPIO 8 for Focus Key */ + gpio@c700 { + status = "okay"; + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <0>; + qcom,src-sel = <0>; + qcom,out-strength = <1>; + }; + + gpio@cc00 { /* GPIO 13 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <0>; + qcom,out-strength = <1>; + qcom,src-sel = <3>; + qcom,master-en = <1>; + status = "okay"; + }; + + /* GPIO 21 (NFC_CLK_REQ) */ + gpio@d400 { + qcom,mode = <0>; + qcom,vin-sel = <1>; + qcom,src-sel = <0>; + qcom,master-en = <1>; + status = "okay"; + }; +}; + +&i2c_5 { + status = "okay"; + synaptics@20 { + compatible = "synaptics,dsx"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <125 0x2008>; + vdd-supply = <&pm8998_l6>; + avdd-supply = <&pm8998_l28>; + synaptics,vdd-voltage = <1808000 1808000>; + synaptics,avdd-voltage = <3008000 3008000>; + synaptics,vdd-current = <40000>; + synaptics,avdd-current = <20000>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + synaptics,display-coords = <0 0 1439 2559>; + synaptics,panel-coords = <0 0 1439 2559>; + synaptics,reset-gpio = <&tlmm 89 0x00>; + synaptics,irq-gpio = <&tlmm 125 0x2008>; + synaptics,disable-gpios; + synaptics,fw-name = "PR1702898-s3528t_60QHD_00400001.img"; + }; +}; + +&i2c_6 { /* BLSP1 QUP6 (NFC) */ + status = "okay"; + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 92 0x00>; + qcom,nq-ven = <&tlmm 12 0x00>; + qcom,nq-firm = <&tlmm 93 0x00>; + qcom,nq-clkreq = <&pm8998_gpios 21 0x00>; + qcom,nq-esepwr = <&tlmm 116 0x00>; + interrupt-parent = <&tlmm>; + qcom,clk-src = "BBCLK3"; + interrupts = <92 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + clocks = <&clock_gcc clk_ln_bb_clk3_pin>; + clock-names = "ref_clk"; + }; +}; + +&mdss_mdp { + qcom,mdss-pref-prim-intf = "dsi"; +}; + +&mdss_dsi { + hw-config = "split_dsi"; + vdda-1p2-supply = <&pm660_l1>; + vdda-0p9-supply = <&pm660l_l1>; +}; + +&mdss_dsi0 { + qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; + wqhd-vddio-supply = <&pm660_l11>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + pinctrl-names = "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; + pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; + qcom,platform-reset-gpio = <&tlmm 94 0>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,panel-mode-gpio = <&tlmm 91 0>; +}; + +&mdss_dsi1 { + qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; + wqhd-vddio-supply = <&pm660_l11>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + pinctrl-names = "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; + pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; + qcom,platform-reset-gpio = <&tlmm 94 0>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,panel-mode-gpio = <&tlmm 91 0>; +}; + +&labibb { + status = "ok"; + qpnp,qpnp-labibb-mode = "lcd"; +}; + +&pmi8998_wled { + qcom,led-strings-list = [00 01]; +}; + +&dsi_dual_nt35597_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_dual_nt35597_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_dual_nt35597_truly_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_nt35597_dsc_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_nt35597_dsc_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_dual_jdi_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,5v-boost-gpio = <&tlmm 51 0>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_dual_jdi_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,5v-boost-gpio = <&tlmm 51 0>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,partial-update-enabled; + qcom,panel-roi-alignment = <4 2 4 2 20 20>; +}; + +&dsi_sharp_1080_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_jdi_1080_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,5v-boost-gpio = <&tlmm 51 0>; +}; + +&dsi_dual_sharp_1080_120hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&mdss_hdmi_tx { + pinctrl-names = "hdmi_hpd_active", "hdmi_ddc_active", "hdmi_cec_active", + "hdmi_active", "hdmi_sleep"; + pinctrl-0 = <&mdss_hdmi_5v_active &mdss_hdmi_hpd_active + &mdss_hdmi_ddc_suspend &mdss_hdmi_cec_suspend>; + pinctrl-1 = <&mdss_hdmi_5v_active &mdss_hdmi_hpd_active + &mdss_hdmi_ddc_active &mdss_hdmi_cec_suspend>; + pinctrl-2 = <&mdss_hdmi_5v_active &mdss_hdmi_hpd_active + &mdss_hdmi_cec_active &mdss_hdmi_ddc_suspend>; + pinctrl-3 = <&mdss_hdmi_5v_active &mdss_hdmi_hpd_active + &mdss_hdmi_ddc_active &mdss_hdmi_cec_active>; + pinctrl-4 = <&mdss_hdmi_5v_suspend &mdss_hdmi_hpd_suspend + &mdss_hdmi_ddc_suspend &mdss_hdmi_cec_suspend>; +}; + +&mdss_dp_ctrl { + vdda-1p2-supply = <&pm660_l1>; + vdda-0p9-supply = <&pm660l_l1>; + pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; + pinctrl-0 = <&mdss_dp_aux_active &mdss_dp_usbplug_cc_active>; + pinctrl-1 = <&mdss_dp_aux_suspend &mdss_dp_usbplug_cc_suspend>; + qcom,aux-en-gpio = <&tlmm 77 0>; + qcom,aux-sel-gpio = <&tlmm 78 0>; + qcom,usbplug-cc-gpio = <&tlmm 38 0>; +}; + +&pmi8998_charger { + qcom,batteryless-platform; +}; + +&pmi8998_haptics { + status = "okay"; +}; + +&pm8998_vadc { + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@85 { + label = "vcoin"; + reg = <0x85>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@4d { + label = "msm_therm"; + reg = <0x4d>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; +}; + +&pm8998_adc_tm { + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,btm-channel-number = <0x60>; + }; + + chan@4d { + label = "msm_therm"; + reg = <0x4d>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x68>; + qcom,thermal-node; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x70>; + qcom,thermal-node; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x78>; + qcom,thermal-node; + }; +}; + +&wil6210 { + status = "ok"; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + status = "okay"; + + home { + label = "home"; + gpios = <&pm8998_gpios 5 0x1>; + linux,input-type = <1>; + linux,code = <102>; + gpio-key,wakeup; + debounce-interval = <15>; + + }; + + vol_up { + label = "volume_up"; + gpios = <&pm8998_gpios 6 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + cam_snapshot { + label = "cam_snapshot"; + gpios = <&pm8998_gpios 7 0x1>; + linux,input-type = <1>; + linux,code = <766>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + cam_focus { + label = "cam_focus"; + gpios = <&pm8998_gpios 8 0x1>; + linux,input-type = <1>; + linux,code = <528>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-mtp.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-mtp.dtsi new file mode 100644 index 000000000000..a9306475e24e --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-mtp.dtsi @@ -0,0 +1,505 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "msm8998-pinctrl.dtsi" +#include "msm8998-camera-sensor-mtp.dtsi" + +&blsp1_uart3_hs { + status = "ok"; +}; + +&ufsphy1 { + vdda-phy-supply = <&pm660l_l1>; + vdda-pll-supply = <&pm660_l1>; + vddp-ref-clk-supply = <&pm660_l1>; + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14600>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; + status = "ok"; +}; + +&ufs1 { + vdd-hba-supply = <&gdsc_ufs>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm660l_l4>; + vccq2-supply = <&pm660_l8>; + vcc-max-microamp = <500000>; + vccq2-max-microamp = <600000>; + status = "ok"; +}; + +&ufs_ice { + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm660l_l5>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm660l_l2>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + qcom,clk-rates = <400000 20000000 25000000 + 50000000 100000000 200000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + + cd-gpios = <&tlmm 95 0x1>; + + status = "ok"; +}; + +&uartblsp2dm1 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&pm8998_gpios { + /* GPIO 6 for Vol+ Key */ + gpio@c500 { + status = "okay"; + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <0>; + qcom,src-sel = <0>; + qcom,out-strength = <1>; + }; + + /* GPIO 7 for Snapshot Key */ + gpio@c600 { + status = "okay"; + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <0>; + qcom,src-sel = <0>; + qcom,out-strength = <1>; + }; + + /* GPIO 8 for Focus Key */ + gpio@c700 { + status = "okay"; + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <0>; + qcom,src-sel = <0>; + qcom,out-strength = <1>; + }; + + gpio@cc00 { /* GPIO 13 */ + qcom,mode = <1>; + qcom,output-type = <0>; + qcom,pull = <5>; + qcom,vin-sel = <0>; + qcom,out-strength = <1>; + qcom,src-sel = <3>; + qcom,master-en = <1>; + status = "okay"; + }; + + /* GPIO 21 (NFC_CLK_REQ) */ + gpio@d400 { + qcom,mode = <0>; + qcom,vin-sel = <1>; + qcom,src-sel = <0>; + qcom,master-en = <1>; + status = "okay"; + }; + + /* GPIO 18 SMB138X */ + gpio@d100 { + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <0>; + qcom,src-sel = <0>; + qcom,master-en = <1>; + status = "okay"; + }; +}; + +&i2c_5 { + status = "okay"; + synaptics@20 { + compatible = "synaptics,dsx"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <125 0x2008>; + vdd-supply = <&pm8998_l6>; + avdd-supply = <&pm8998_l28>; + synaptics,vdd-voltage = <1808000 1808000>; + synaptics,avdd-voltage = <3008000 3008000>; + synaptics,vdd-current = <40000>; + synaptics,avdd-current = <20000>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + synaptics,display-coords = <0 0 1439 2559>; + synaptics,panel-coords = <0 0 1439 2559>; + synaptics,reset-gpio = <&tlmm 89 0x00>; + synaptics,irq-gpio = <&tlmm 125 0x2008>; + synaptics,disable-gpios; + synaptics,fw-name = "PR1702898-s3528t_60QHD_00400001.img"; + }; +}; + +&i2c_6 { /* BLSP1 QUP6 (NFC) */ + status = "okay"; + nq@28 { + compatible = "qcom,nq-nci"; + reg = <0x28>; + qcom,nq-irq = <&tlmm 92 0x00>; + qcom,nq-ven = <&tlmm 12 0x00>; + qcom,nq-firm = <&tlmm 93 0x00>; + qcom,nq-clkreq = <&pm8998_gpios 21 0x00>; + qcom,nq-esepwr = <&tlmm 116 0x00>; + interrupt-parent = <&tlmm>; + qcom,clk-src = "BBCLK3"; + interrupts = <92 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + clocks = <&clock_gcc clk_ln_bb_clk3_pin>; + clock-names = "ref_clk"; + }; +}; + +&mdss_hdmi_tx { + pinctrl-names = "hdmi_hpd_active", "hdmi_ddc_active", "hdmi_cec_active", + "hdmi_active", "hdmi_sleep"; + pinctrl-0 = <&mdss_hdmi_5v_active &mdss_hdmi_hpd_active + &mdss_hdmi_ddc_suspend &mdss_hdmi_cec_suspend>; + pinctrl-1 = <&mdss_hdmi_5v_active &mdss_hdmi_hpd_active + &mdss_hdmi_ddc_active &mdss_hdmi_cec_suspend>; + pinctrl-2 = <&mdss_hdmi_5v_active &mdss_hdmi_hpd_active + &mdss_hdmi_cec_active &mdss_hdmi_ddc_suspend>; + pinctrl-3 = <&mdss_hdmi_5v_active &mdss_hdmi_hpd_active + &mdss_hdmi_ddc_active &mdss_hdmi_cec_active>; + pinctrl-4 = <&mdss_hdmi_5v_suspend &mdss_hdmi_hpd_suspend + &mdss_hdmi_ddc_suspend &mdss_hdmi_cec_suspend>; +}; + +&mdss_dp_ctrl { + vdda-1p2-supply = <&pm660_l1>; + vdda-0p9-supply = <&pm660l_l1>; + pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; + pinctrl-0 = <&mdss_dp_aux_active &mdss_dp_usbplug_cc_active>; + pinctrl-1 = <&mdss_dp_aux_suspend &mdss_dp_usbplug_cc_suspend>; + qcom,aux-en-gpio = <&tlmm 77 0>; + qcom,aux-sel-gpio = <&tlmm 78 0>; + qcom,usbplug-cc-gpio = <&tlmm 38 0>; +}; + +&mdss_mdp { + qcom,mdss-pref-prim-intf = "dsi"; +}; + +&mdss_dsi { + hw-config = "split_dsi"; + vdda-1p2-supply = <&pm660_l1>; + vdda-0p9-supply = <&pm660l_l1>; +}; + +&mdss_dsi0 { + qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; + wqhd-vddio-supply = <&pm660_l11>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + pinctrl-names = "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; + pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; + qcom,platform-reset-gpio = <&tlmm 94 0>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,panel-mode-gpio = <&tlmm 91 0>; +}; + +&mdss_dsi1 { + qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; + wqhd-vddio-supply = <&pm660_l11>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + pinctrl-names = "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; + pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; + qcom,platform-reset-gpio = <&tlmm 94 0>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,panel-mode-gpio = <&tlmm 91 0>; +}; + +&labibb { + status = "ok"; + qpnp,qpnp-labibb-mode = "lcd"; +}; + +&pmi8998_wled { + qcom,led-strings-list = [00 01]; +}; + +&dsi_dual_nt35597_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_dual_nt35597_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_dual_nt35597_truly_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_nt35597_dsc_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_nt35597_dsc_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "single_port"; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_dual_jdi_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,5v-boost-gpio = <&tlmm 51 0>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_dual_jdi_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,5v-boost-gpio = <&tlmm 51 0>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_sharp_1080_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_jdi_1080_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>; + qcom,5v-boost-gpio = <&tlmm 51 0>; +}; + +&dsi_dual_sharp_1080_120hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&pmi8998_haptics { + status = "okay"; +}; + +&pm8998_vadc { + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@85 { + label = "vcoin"; + reg = <0x85>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,fast-avg-setup = <0>; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@4d { + label = "msm_therm"; + reg = <0x4d>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,decimation = <2>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,fast-avg-setup = <0>; + }; +}; + +&pm8998_adc_tm { + chan@83 { + label = "vph_pwr"; + reg = <0x83>; + qcom,pre-div-channel-scaling = <1>; + qcom,calibration-type = "absolute"; + qcom,scale-function = <0>; + qcom,hw-settle-time = <0>; + qcom,btm-channel-number = <0x60>; + }; + + chan@4d { + label = "msm_therm"; + reg = <0x4d>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x68>; + qcom,thermal-node; + }; + + chan@51 { + label = "quiet_therm"; + reg = <0x51>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <2>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x70>; + qcom,thermal-node; + }; + + chan@4c { + label = "xo_therm"; + reg = <0x4c>; + qcom,pre-div-channel-scaling = <0>; + qcom,calibration-type = "ratiometric"; + qcom,scale-function = <4>; + qcom,hw-settle-time = <2>; + qcom,btm-channel-number = <0x78>; + qcom,thermal-node; + }; +}; + +&wil6210 { + status = "ok"; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + status = "okay"; + + vol_up { + label = "volume_up"; + gpios = <&pm8998_gpios 6 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + cam_snapshot { + label = "cam_snapshot"; + gpios = <&pm8998_gpios 7 0x1>; + linux,input-type = <1>; + linux,code = <766>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + cam_focus { + label = "cam_focus"; + gpios = <&pm8998_gpios 8 0x1>; + linux,input-type = <1>; + linux,code = <528>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; +}; + +/{ + mtp_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "fg-gen3-batterydata-itech-3000mah.dtsi" + #include "fg-gen3-batterydata-ascent-3450mah.dtsi" + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660.dtsi new file mode 100644 index 000000000000..d6b278e2a789 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660.dtsi @@ -0,0 +1,3154 @@ +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "skeleton64.dtsi" +#include +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. MSM 8998"; + compatible = "qcom,msm8998"; + qcom,msm-id = <292 0x0>; + interrupt-parent = <&intc>; + + aliases { + serial0 = &uartblsp2dm1; + pci-domain0 = &pcie0; + sdhc2 = &sdhc_2; /* SDC2 SD card slot */ + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + chosen { + stdout-path = "serial0"; + bootargs = "rcupdate.rcu_expedited=1"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + qcom,limits-info = <&mitigation_profile0>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + enable-method = "psci"; + efficiency = <1024>; + next-level-cache = <&L2_0>; + qcom,ea = <&ea0>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + /* A53 L2 dump not supported */ + qcom,dump-size = <0x0>; + }; + L1_I_0: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + L1_D_0: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + qcom,limits-info = <&mitigation_profile1>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + enable-method = "psci"; + efficiency = <1024>; + next-level-cache = <&L2_0>; + qcom,ea = <&ea1>; + L1_I_1: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + L1_D_1: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + qcom,limits-info = <&mitigation_profile2>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + enable-method = "psci"; + efficiency = <1024>; + next-level-cache = <&L2_0>; + qcom,ea = <&ea2>; + L1_I_2: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + L1_D_2: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + qcom,limits-info = <&mitigation_profile3>; + qcom,lmh-dcvs = <&lmh_dcvs0>; + enable-method = "psci"; + efficiency = <1024>; + next-level-cache = <&L2_0>; + qcom,ea = <&ea3>; + L1_I_3: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + L1_D_3: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + }; + + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + qcom,limits-info = <&mitigation_profile4>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + enable-method = "psci"; + efficiency = <1536>; + next-level-cache = <&L2_1>; + qcom,ea = <&ea4>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + }; + L1_I_100: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + L1_D_100: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + }; + + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x101>; + qcom,limits-info = <&mitigation_profile5>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + enable-method = "psci"; + efficiency = <1536>; + next-level-cache = <&L2_1>; + qcom,ea = <&ea5>; + L1_I_101: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + L1_D_101: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + }; + + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x102>; + qcom,limits-info = <&mitigation_profile6>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + enable-method = "psci"; + efficiency = <1536>; + next-level-cache = <&L2_1>; + qcom,ea = <&ea6>; + L1_I_102: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + L1_D_102: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + }; + + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x103>; + qcom,limits-info = <&mitigation_profile7>; + qcom,lmh-dcvs = <&lmh_dcvs1>; + enable-method = "psci"; + efficiency = <1536>; + next-level-cache = <&L2_1>; + qcom,ea = <&ea7>; + L1_I_103: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + L1_D_103: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; + + soc: soc { }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + removed_regions: removed_regions@85800000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x85800000 0 0x3700000>; + }; + + pil_slpi_mem: pil_slpi_region@93800000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x93800000 0 0xf00000>; + }; + + pil_video_mem: pil_video_region@93300000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x93300000 0 0x500000>; + }; + + pil_adsp_mem: pil_adsp_region@91900000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x91900000 0 0x1a00000>; + }; + + modem_mem: modem_region@8ac00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x8ac00000 0 0x6d00000>; + }; + + spss_mem: spss_region@8ab00000 { /* for SPSS-PIL */ + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x8ab00000 0 0x100000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x1400000>; + }; + + sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */ + reusable; + alignment = <0 0x100000>; + size = <0 0x800000>; + }; + + secure_display_memory: secure_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x200000>; + size = <0 0x5c00000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x2000000>; + linux,cma-default; + }; + + cont_splash_mem: splash_region@9d600000 { + reg = <0x0 0x9d600000 0x0 0x02400000>; + label = "cont_splash_mem"; + }; + }; + + bluetooth: bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-vdd-core-supply = <&pm660_l9_pin_ctrl>; + qca,bt-vdd-pa-supply = <&pm660_l6_pin_ctrl>; + qca,bt-vdd-ldo-supply = <&pm660_l19_pin_ctrl>; + qca,bt-chip-pwd-supply = <&pm660l_bob_pin1>; + clocks = <&clock_gcc clk_rf_clk1>; + clock-names = "rf_clk1"; + + qca,bt-vdd-core-voltage-level = <1800000 1900000>; + qca,bt-vdd-pa-voltage-level = <1304000 1370000>; + qca,bt-vdd-ldo-voltage-level = <3312000 3400000>; + qca,bt-chip-pwd-voltage-level = <3600000 3600000>; + + qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */ + }; +}; + +#include "msm8998-smp2p.dtsi" +#include "msm-gdsc-8998.dtsi" + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17b00000 0x100000>; /* GICR * 8 */ + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + interrupts = <1 9 4>; + + gic-its@0x17a20000{ + compatible = "arm,gic-v3-its"; + msi-contoller; + reg = <0x17a20000 0x20000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 1 0xf08>, + <1 2 0xf08>, + <1 3 0xf08>, + <1 0 0xf08>; + clock-frequency = <19200000>; + }; + + restart@10ac000 { + compatible = "qcom,pshold"; + reg = <0x10ac000 0x4>, + <0x1fd3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + spmi_bus: qcom,spmi@800f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x800f000 0x1000>, + <0x8400000 0x1000000>, + <0x9400000 0x1000000>, + <0xa400000 0x220000>, + <0x800a000 0x3000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + qcom,sps { + compatible = "qcom,msm_sps_4k"; + qcom,device-type = <3>; + qcom,pipe-attr-ee; + }; + + uartblsp1dm1: serial@0c170000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xc170000 0x1000>; + interrupts = <0 108 0>; + status = "disabled"; + clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>, + <&clock_gcc clk_gcc_blsp1_ahb_clk>; + clock-names = "core", "iface"; + }; + + uartblsp2dm1: serial@0c1b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xc1b0000 0x1000>; + interrupts = <0 114 0>; + status = "disabled"; + clocks = <&clock_gcc clk_gcc_blsp2_uart2_apps_clk>, + <&clock_gcc clk_gcc_blsp2_ahb_clk>; + clock-names = "core", "iface"; + }; + + slim_aud: slim@171c0000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0x171c0000 0x2C000>, + <0x17184000 0x32000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 163 0>, <0 164 0>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + qcom,apps-ch-pipes = <0x00001f80>; + qcom,ea-pc = <0x210>; + }; + + slim_qca: slim@17240000 { + status = "ok"; + cell-index = <3>; + compatible = "qcom,slim-ngd"; + reg = <0x17240000 0x2C000>, + <0x17204000 0x26000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 291 0>, <0 292 0>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + + /* Slimbus Slave DT for WCN3990 */ + btfmslim_codec: wcn3990 { + compatible = "qcom,btfmslim_slave"; + elemental-addr = [00 01 20 02 17 02]; + qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; + qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; + }; + }; + + timer@17920000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17920000 0x1000>; + clock-frequency = <19200000>; + + frame@17921000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0x17921000 0x1000>, + <0x17922000 0x1000>; + }; + + frame@17923000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0x17923000 0x1000>; + status = "disabled"; + }; + + frame@17924000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0x17924000 0x1000>; + status = "disabled"; + }; + + frame@17925000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0x17925000 0x1000>; + status = "disabled"; + }; + + frame@17926000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0x17926000 0x1000>; + status = "disabled"; + }; + + frame@17927000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0x17927000 0x1000>; + status = "disabled"; + }; + + frame@17928000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0x17928000 0x1000>; + status = "disabled"; + }; + }; + + cpubw: qcom,cpubw { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = <1 512>; + qcom,active-only; + qcom,bw-tbl = + < 762 /* 100 MHz */ >, + < 1144 /* 150 MHz */ >, + < 1525 /* 200 MHz */ >, + < 2288 /* 300 MHz */ >, + < 3143 /* 412 MHz */ >, + < 4173 /* 547 MHz */ >, + < 5195 /* 681 MHz */ >, + < 5859 /* 768 MHz */ >, + < 7759 /* 1017 MHz */ >, + < 9887 /* 1296 MHz */ >, + < 11863 /* 1555 MHz */ >, + < 13763 /* 1804 MHz */ >; + }; + + bwmon: qcom,cpu-bwmon { + compatible = "qcom,bimc-bwmon3"; + reg = <0x01008000 0x300>, <0x01001000 0x200>; + reg-names = "base", "global_base"; + interrupts = <0 183 4>; + qcom,mport = <0>; + qcom,target-dev = <&cpubw>; + }; + + mincpubw: qcom,mincpubw { + compatible = "qcom,devbw"; + governor = "powersave"; + qcom,src-dst-ports = <1 512>; + qcom,active-only; + qcom,bw-tbl = + < 762 /* 100 MHz */ >, + < 1144 /* 150 MHz */ >, + < 1525 /* 200 MHz */ >, + < 2288 /* 300 MHz */ >, + < 3143 /* 412 MHz */ >, + < 4173 /* 547 MHz */ >, + < 5195 /* 681 MHz */ >, + < 5859 /* 768 MHz */ >, + < 7759 /* 1017 MHz */ >, + < 9887 /* 1296 MHz */ >, + < 11863 /* 1555 MHz */ >, + < 13763 /* 1804 MHz */ >; + }; + + memlat_cpu0: qcom,memlat-cpu0 { + compatible = "qcom,devbw"; + governor = "powersave"; + qcom,src-dst-ports = <1 512>; + qcom,active-only; + qcom,bw-tbl = + < 762 /* 100 MHz */ >, + < 1144 /* 150 MHz */ >, + < 1525 /* 200 MHz */ >, + < 2288 /* 300 MHz */ >, + < 3143 /* 412 MHz */ >, + < 4173 /* 547 MHz */ >, + < 5195 /* 681 MHz */ >, + < 5859 /* 768 MHz */ >, + < 7759 /* 1017 MHz */ >, + < 9887 /* 1296 MHz */ >, + < 11863 /* 1555 MHz */ >, + < 13763 /* 1804 MHz */ >; + }; + + memlat_cpu4: qcom,memlat-cpu4 { + compatible = "qcom,devbw"; + governor = "powersave"; + qcom,src-dst-ports = <1 512>; + qcom,active-only; + status = "ok"; + qcom,bw-tbl = + < 762 /* 100 MHz */ >, + < 1144 /* 150 MHz */ >, + < 1525 /* 200 MHz */ >, + < 2288 /* 300 MHz */ >, + < 3143 /* 412 MHz */ >, + < 4173 /* 547 MHz */ >, + < 5195 /* 681 MHz */ >, + < 5859 /* 768 MHz */ >, + < 7759 /* 1017 MHz */ >, + < 9887 /* 1296 MHz */ >, + < 11863 /* 1555 MHz */ >, + < 13763 /* 1804 MHz */ >; + }; + + qcom,arm-memlat-mon-0 { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&memlat_cpu0>; + qcom,core-dev-table = + < 300000 1525 >, + < 499200 3143 >, + < 1113600 4173 >, + < 1881600 5859 >; + }; + + qcom,arm-memlat-mon-4 { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,target-dev = <&memlat_cpu4>; + qcom,core-dev-table = + < 300000 1525 >, + < 480000 3143 >, + < 900000 4173 >, + < 1017000 7759 >, + < 1296000 9887 >, + < 1555000 11863 >, + < 1804000 13763 >; + }; + + devfreq_cpufreq: devfreq-cpufreq { + mincpubw-cpufreq { + target-dev = <&mincpubw>; + cpu-to-dev-map-0 = + < 1881600 1525 >; + cpu-to-dev-map-4 = + < 2016000 1525 >, + < 2092800 5195 >; + }; + }; + + msm_cpufreq: qcom,msm-cpufreq { + compatible = "qcom,msm-cpufreq"; + clock-names = "cpu0_clk", "cpu1_clk", "cpu2_clk", + "cpu3_clk", "cpu4_clk", "cpu5_clk", + "cpu6_clk", "cpu7_clk"; + clocks = <&clock_cpu clk_pwrcl_clk>, + <&clock_cpu clk_pwrcl_clk>, + <&clock_cpu clk_pwrcl_clk>, + <&clock_cpu clk_pwrcl_clk>, + <&clock_cpu clk_perfcl_clk>, + <&clock_cpu clk_perfcl_clk>, + <&clock_cpu clk_perfcl_clk>, + <&clock_cpu clk_perfcl_clk>; + + qcom,governor-per-policy; + + qcom,cpufreq-table-0 = + < 300000 >, + < 345600 >, + < 422400 >, + < 499200 >, + < 576000 >, + < 633600 >, + < 710400 >, + < 806400 >, + < 883200 >, + < 960000 >, + < 1036800 >, + < 1113600 >, + < 1190400 >, + < 1248000 >, + < 1324800 >, + < 1401600 >, + < 1478400 >, + < 1574400 >, + < 1651200 >, + < 1728000 >, + < 1804800 >, + < 1881600 >; + + qcom,cpufreq-table-4 = + < 300000 >, + < 345600 >, + < 422400 >, + < 480000 >, + < 556800 >, + < 633600 >, + < 710400 >, + < 787200 >, + < 844800 >, + < 902400 >, + < 979200 >, + < 1056000 >, + < 1171200 >, + < 1248000 >, + < 1324800 >, + < 1401600 >, + < 1478400 >, + < 1536000 >, + < 1632000 >, + < 1708800 >, + < 1785600 >, + < 1862400 >, + < 1939200 >, + < 2016000 >, + < 2092800 >; + }; + + arm64-cpu-erp { + compatible = "arm,arm64-cpu-erp"; + interrupts = <0 43 4>, + <0 44 4>, + <0 41 4>, + <0 42 4>; + + interrupt-names = "pri-dbe-irq", + "sec-dbe-irq", + "pri-ext-irq", + "sec-ext-irq"; + + poll-delay-ms = <5000>; + }; + + clock_gcc: qcom,gcc@100000 { + compatible = "qcom,gcc-8998"; + reg = <0x100000 0xb0000>; + reg-names = "cc_base"; + vdd_dig-supply = <&pm8998_s1_level>; + vdd_dig_ao-supply = <&pm8998_s1_level_ao>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_mmss: qcom,mmsscc@c8c0000 { + compatible = "qcom,mmsscc-8998"; + reg = <0xc8c0000 0x40000>; + reg-names = "cc_base"; + vdd_dig-supply = <&pm8998_s1_level>; + vdd_mmsscc_mx-supply = <&pm8998_s9_level>; + clock-names = "xo", "gpll0", "gpll0_div", + "pclk0_src", "pclk1_src", + "byte0_src", "byte1_src", + "dp_link_src", "dp_vco_div", + "extpclk_src"; + clocks = <&clock_gcc clk_cxo_clk_src>, + <&clock_gcc clk_gcc_mmss_gpll0_clk>, + <&clock_gcc clk_gcc_mmss_gpll0_div_clk>, + <&mdss_dsi0_pll clk_dsi0pll_pclk_mux>, + <&mdss_dsi1_pll clk_dsi1pll_pclk_mux>, + <&mdss_dsi0_pll clk_dsi0pll_byteclk_mux>, + <&mdss_dsi1_pll clk_dsi1pll_byteclk_mux>, + <&mdss_dp_pll clk_dp_link_2x_clk_divsel_five>, + <&mdss_dp_pll clk_vco_divided_clk_src_mux>, + <&mdss_hdmi_pll clk_hdmi_vco_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_gpu: qcom,gpucc@5065000 { + compatible = "qcom,gpucc-8998"; + reg = <0x5065000 0x9000>; + reg-names = "cc_base"; + vdd_dig-supply = <&pm8998_s1_level>; + clock-names = "xo_ao", "gpll0"; + clocks = <&clock_gcc clk_cxo_clk_src_ao>, + <&clock_gcc clk_gcc_gpu_gpll0_clk>; + #clock-cells = <1>; + }; + + clock_gfx: qcom,gfxcc@5065000 { + compatible = "qcom,gfxcc-8998"; + reg = <0x5065000 0x9000>; + reg-names = "cc_base"; + vdd_gpucc-supply = <&gfx_vreg>; + vdd_mx-supply = <&pm8998_s9_level>; + vdd_gpu_mx-supply = <&pm8998_s9_level>; + qcom,gfx3d_clk_src-opp-handle = <&msm_gpu>; + qcom,gfxfreq-speedbin0 = + < 0 0 0 >, + < 171000000 1 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 251000000 2 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 332000000 3 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 403000000 4 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 504000000 5 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 650000000 6 RPM_SMD_REGULATOR_LEVEL_TURBO >; + qcom,gfxfreq-mx-speedbin0 = + < 0 0 >, + < 171000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 251000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 332000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 403000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 504000000 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 650000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; + #clock-cells = <1>; + }; + + clock_cpu: qcom,cpu-clock-8998@179c0000 { + compatible = "qcom,cpu-clock-osm-msm8998-v1"; + reg = <0x179c0000 0x4000>, + <0x17916000 0x1000>, + <0x17816000 0x1000>, + <0x179d1000 0x1000>, + <0x00784130 0x8>, + <0x1791101c 0x8>; + reg-names = "osm", "pwrcl_pll", "perfcl_pll", + "apcs_common", "perfcl_efuse", "debug"; + + vdd-pwrcl-supply = <&apc0_pwrcl_vreg>; + vdd-perfcl-supply = <&apc1_perfcl_vreg>; + + interrupts = , + ; + interrupt-names = "pwrcl-irq", "perfcl-irq"; + + qcom,pwrcl-speedbin0-v0 = + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 345600000 0x05040012 0x02200020 0x1 2 >, + < 422400000 0x05040016 0x02200020 0x1 3 >, + < 499200000 0x0504001a 0x02200020 0x1 4 >, + < 576000000 0x0504001e 0x03200020 0x1 5 >, + < 633600000 0x05040021 0x03200020 0x1 6 >, + < 710400000 0x05040025 0x03200020 0x1 7 >, + < 806400000 0x0504002a 0x04200020 0x1 8 >, + < 883200000 0x0404002e 0x04250025 0x1 9 >, + < 960000000 0x04040032 0x05280028 0x1 10 >, + < 1036800000 0x04040036 0x052b002b 0x2 11 >, + < 1113600000 0x0404003a 0x052e002e 0x2 12 >, + < 1190400000 0x0404003e 0x06320032 0x2 13 >, + < 1248000000 0x04040041 0x06340034 0x2 14 >, + < 1324800000 0x04040045 0x06370037 0x2 15 >, + < 1401600000 0x04040049 0x073a003a 0x2 16 >, + < 1478400000 0x0404004d 0x073e003e 0x2 17 >, + < 1574400000 0x04040052 0x08420042 0x2 18 >, + < 1651200000 0x04040056 0x08450045 0x2 19 >, + < 1728000000 0x0404005a 0x08480048 0x2 20 >, + < 1804800000 0x0404005e 0x094b004b 0x3 21 >, + < 1881600000 0x04040062 0x094e004e 0x3 22 >; + + qcom,perfcl-speedbin0-v0 = + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 345600000 0x05040012 0x02200020 0x1 2 >, + < 422400000 0x05040016 0x02200020 0x1 3 >, + < 480000000 0x05040019 0x02200020 0x1 4 >, + < 556800000 0x0504001d 0x03200020 0x1 5 >, + < 633600000 0x05040021 0x03200020 0x1 6 >, + < 710400000 0x05040025 0x03200020 0x1 7 >, + < 787200000 0x05040029 0x04200020 0x1 8 >, + < 844800000 0x0404002c 0x04230023 0x1 9 >, + < 902400000 0x0404002f 0x04260026 0x1 10 >, + < 979200000 0x04040033 0x05290029 0x1 11 >, + < 1056000000 0x04040037 0x052c002c 0x1 12 >, + < 1171200000 0x0404003d 0x06310031 0x2 13 >, + < 1248000000 0x04040041 0x06340034 0x2 14 >, + < 1324800000 0x04040045 0x06370037 0x2 15 >, + < 1401600000 0x04040049 0x073a003a 0x2 16 >, + < 1478400000 0x0404004d 0x073e003e 0x2 17 >, + < 1536000000 0x04040050 0x07400040 0x2 18 >, + < 1632000000 0x04040055 0x08440044 0x2 19 >, + < 1708800000 0x04040059 0x08470047 0x2 20 >, + < 1785600000 0x0404005d 0x094a004a 0x2 21 >, + < 1862400000 0x04040061 0x094e004e 0x2 22 >, + < 1939200000 0x04040065 0x09510051 0x3 23 >, + < 2016000000 0x04040069 0x0a540054 0x3 24 >, + < 2092800000 0x0404006d 0x0a570057 0x3 25 >; + + qcom,up-timer = + <1000 1000>; + qcom,down-timer = + <1000 1000>; + qcom,pc-override-index = + <0 0>; + qcom,set-ret-inactive; + qcom,enable-llm-freq-vote; + qcom,llm-freq-up-timer = + <327675 327675>; + qcom,llm-freq-down-timer = + <327675 327675>; + qcom,enable-llm-volt-vote; + qcom,llm-volt-up-timer = + <327675 327675>; + qcom,llm-volt-down-timer = + <327675 327675>; + qcom,cc-reads = <10>; + qcom,cc-delay = <5>; + qcom,cc-factor = <100>; + qcom,osm-clk-rate = <200000000>; + qcom,xo-clk-rate = <19200000>; + + qcom,l-val-base = + <0x17916004 0x17816004>; + qcom,apcs-itm-present = + <0x179d143c 0x179d143c>; + qcom,apcs-pll-user-ctl = + <0x1791600c 0x1781600c>; + qcom,apcs-cfg-rcgr = + <0x17911054 0x17811054>; + qcom,apcs-cmd-rcgr = + <0x17911050 0x17811050>; + qcom,apm-mode-ctl = + <0x179d0004 0x179d0010>; + qcom,apm-ctrl-status = + <0x179d000c 0x179d0018>; + qcom,llm-sw-overr= + <0x8fff0036 0x8fff003a 0x0fff0036>, + <0x8fff003d 0x8fff0041 0x0fff003d>; + + qcom,apm-threshold-voltage = <832000>; + qcom,boost-fsm-en; + qcom,safe-fsm-en; + qcom,ps-fsm-en; + qcom,droop-fsm-en; + qcom,wfx-fsm-en; + qcom,pc-fsm-en; + + qcom,pwrcl-apcs-mem-acc-cfg = + <0x179d1360 0x179d1364 0x179d1364>; + qcom,perfcl-apcs-mem-acc-cfg = + <0x179d1368 0x179d136C 0x179d1370>; + qcom,pwrcl-apcs-mem-acc-val = + <0x00000000 0x80000000 0x80000000>, + <0x00000000 0x00000000 0x00000000>, + <0x00000000 0x00000001 0x00000001>; + qcom,perfcl-apcs-mem-acc-val = + <0x00000000 0x00000000 0x80000000>, + <0x00000000 0x00000000 0x00000000>, + <0x00000000 0x00000000 0x00000001>; + + clock-names = "aux_clk", "xo_ao"; + clocks = <&clock_gcc clk_hmss_gpll0_clk_src>, + <&clock_gcc clk_cxo_clk_src_ao>; + #clock-cells = <1>; + }; + + clock_debug: qcom,debugcc@162000 { + compatible = "qcom,cc-debug-8998"; + reg = <0x162000 0x4>; + reg-names = "cc_base"; + clock-names = "debug_gpu_clk", "debug_gfx_clk", + "debug_mmss_clk", "debug_cpu_clk"; + clocks = <&clock_gpu clk_gpucc_gcc_dbg_clk>, + <&clock_gfx clk_gfxcc_dbg_clk>, + <&clock_mmss clk_mmss_debug_mux>, + <&clock_cpu clk_cpu_debug_mux>; + #clock-cells = <1>; + }; + + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x00200000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + }; + + qcom,msm_gsi { + compatible = "qcom,msm_gsi"; + }; + + qcom,rmnet-ipa { + compatible = "qcom,rmnet-ipa3"; + qcom,rmnet-ipa-ssr; + qcom,ipa-loaduC; + qcom,ipa-advertise-sg-support; + }; + + ipa_hw: qcom,ipa@01e00000 { + compatible = "qcom,ipa"; + reg = <0x01e00000 0x34000>, + <0x01e84000 0x31fff>, + <0x01e04000 0x2c000>; + reg-names = "ipa-base", "bam-base", "gsi-base"; + interrupts = + <0 333 0>, + <0 432 0>, + <0 432 0>; + interrupt-names = "ipa-irq", "bam-irq", "gsi-irq"; + qcom,ipa-hw-ver = <11>; /* IPA core version = IPAv3.1 */ + qcom,ipa-hw-mode = <0>; /* IPA hw type = Normal */ + qcom,ee = <0>; + qcom,use-gsi; + qcom,use-ipa-tethering-bridge; + qcom,modem-cfg-emb-pipe-flt; + qcom,do-not-use-ch-gsi-20; + qcom,ipa-wdi2; + qcom,use-64-bit-dma-mask; + clocks = <&clock_gcc clk_ipa_clk>; + clock-names = "core_clk"; + qcom,arm-smmu; + qcom,smmu-disable-htw; + qcom,smmu-s1-bypass; + qcom,msm-bus,name = "ipa"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <4>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <90 512 0 0>, + <90 585 0 0>, + <1 676 0 0>, + /* SMMU smmu_aggre2_noc_clk */ + <81 10065 0 0>, + /* SVS */ + <90 512 80000 640000>, + <90 585 80000 640000>, + <1 676 80000 80000>, + /* SMMU smmu_aggre2_noc_clk */ + <81 10065 0 16000>, + /* NOMINAL */ + <90 512 206000 960000>, + <90 585 206000 960000>, + <1 676 206000 160000>, + /* SMMU smmu_aggre2_noc_clk */ + <81 10065 0 16000>, + /* TURBO */ + <90 512 206000 3600000>, + <90 585 206000 3600000>, + <1 676 206000 300000>, + /* SMMU smmu_aggre2_noc_clk */ + <81 10065 0 16000>; + qcom,bus-vector-names = "MIN", "SVS", "NOMINAL", "TURBO"; + + /* IPA RAM mmap */ + qcom,ipa-ram-mmap = < + 0x280 /* ofst_start; */ + 0x0 /* nat_ofst; */ + 0x0 /* nat_size; */ + 0x288 /* v4_flt_hash_ofst; */ + 0x78 /* v4_flt_hash_size; */ + 0x4000 /* v4_flt_hash_size_ddr; */ + 0x308 /* v4_flt_nhash_ofst; */ + 0x78 /* v4_flt_nhash_size; */ + 0x4000 /* v4_flt_nhash_size_ddr; */ + 0x388 /* v6_flt_hash_ofst; */ + 0x78 /* v6_flt_hash_size; */ + 0x4000 /* v6_flt_hash_size_ddr; */ + 0x408 /* v6_flt_nhash_ofst; */ + 0x78 /* v6_flt_nhash_size; */ + 0x4000 /* v6_flt_nhash_size_ddr; */ + 0xf /* v4_rt_num_index; */ + 0x0 /* v4_modem_rt_index_lo; */ + 0x7 /* v4_modem_rt_index_hi; */ + 0x8 /* v4_apps_rt_index_lo; */ + 0xe /* v4_apps_rt_index_hi; */ + 0x488 /* v4_rt_hash_ofst; */ + 0x78 /* v4_rt_hash_size; */ + 0x4000 /* v4_rt_hash_size_ddr; */ + 0x508 /* v4_rt_nhash_ofst; */ + 0x78 /* v4_rt_nhash_size; */ + 0x4000 /* v4_rt_nhash_size_ddr; */ + 0xf /* v6_rt_num_index; */ + 0x0 /* v6_modem_rt_index_lo; */ + 0x7 /* v6_modem_rt_index_hi; */ + 0x8 /* v6_apps_rt_index_lo; */ + 0xe /* v6_apps_rt_index_hi; */ + 0x588 /* v6_rt_hash_ofst; */ + 0x78 /* v6_rt_hash_size; */ + 0x4000 /* v6_rt_hash_size_ddr; */ + 0x608 /* v6_rt_nhash_ofst; */ + 0x78 /* v6_rt_nhash_size; */ + 0x4000 /* v6_rt_nhash_size_ddr; */ + 0x688 /* modem_hdr_ofst; */ + 0x140 /* modem_hdr_size; */ + 0x7c8 /* apps_hdr_ofst; */ + 0x0 /* apps_hdr_size; */ + 0x800 /* apps_hdr_size_ddr; */ + 0x7d0 /* modem_hdr_proc_ctx_ofst; */ + 0x200 /* modem_hdr_proc_ctx_size; */ + 0x9d0 /* apps_hdr_proc_ctx_ofst; */ + 0x200 /* apps_hdr_proc_ctx_size; */ + 0x0 /* apps_hdr_proc_ctx_size_ddr; */ + 0x0 /* modem_comp_decomp_ofst; diff */ + 0x0 /* modem_comp_decomp_size; diff */ + 0xbd8 /* modem_ofst; */ + 0x1424 /* modem_size; */ + 0x1ffc /* apps_v4_flt_hash_ofst; */ + 0x0 /* apps_v4_flt_hash_size; */ + 0x1ffc /* apps_v4_flt_nhash_ofst; */ + 0x0 /* apps_v4_flt_nhash_size; */ + 0x1ffc /* apps_v6_flt_hash_ofst; */ + 0x0 /* apps_v6_flt_hash_size; */ + 0x1ffc /* apps_v6_flt_nhash_ofst; */ + 0x0 /* apps_v6_flt_nhash_size; */ + 0x80 /* uc_info_ofst; */ + 0x200 /* uc_info_size; */ + 0x2000 /* end_ofst; */ + 0x1ffc /* apps_v4_rt_hash_ofst; */ + 0x0 /* apps_v4_rt_hash_size; */ + 0x1ffc /* apps_v4_rt_nhash_ofst; */ + 0x0 /* apps_v4_rt_nhash_size; */ + 0x1ffc /* apps_v6_rt_hash_ofst; */ + 0x0 /* apps_v6_rt_hash_size; */ + 0x1ffc /* apps_v6_rt_nhash_ofst; */ + 0x0 /* apps_v6_rt_nhash_size; */ + >; + + /* smp2p gpio information */ + qcom,smp2pgpio_map_ipa_1_out { + compatible = "qcom,smp2pgpio-map-ipa-1-out"; + gpios = <&smp2pgpio_ipa_1_out 0 0>; + }; + + qcom,smp2pgpio_map_ipa_1_in { + compatible = "qcom,smp2pgpio-map-ipa-1-in"; + gpios = <&smp2pgpio_ipa_1_in 0 0>; + }; + + ipa_smmu_ap: ipa_smmu_ap { + compatible = "qcom,ipa-smmu-ap-cb"; + iommus = <&anoc2_smmu 0x18e0>; + qcom,iova-mapping = <0x10000000 0x40000000>; + }; + + ipa_smmu_wlan: ipa_smmu_wlan { + compatible = "qcom,ipa-smmu-wlan-cb"; + iommus = <&anoc2_smmu 0x18e1>; + }; + + ipa_smmu_uc: ipa_smmu_uc { + compatible = "qcom,ipa-smmu-uc-cb"; + iommus = <&anoc2_smmu 0x18e2>; + qcom,iova-mapping = <0x40000000 0x20000000>; + }; + }; + + qcom,ipa_fws@1e08000 { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <0xF>; + qcom,firmware-name = "ipa_fws"; + }; + + qcom,chd_silver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0x179880b0 0x179980b0 + 0x179a80b0 0x179b80b0>; + qcom,config-arr = <0x179880b8 0x179980b8 + 0x179a80b8 0x179b80b8>; + }; + + qcom,chd_gold { + compatible = "qcom,core-hang-detect"; + label = "gold"; + qcom,threshold-arr = <0x178880b0 0x178980b0 + 0x178a80b0 0x178b80b0>; + qcom,config-arr = <0x178880b8 0x178980b8 + 0x178a80b8 0x178b80b8>; + }; + + qcom,ipc-spinlock@1f40000 { + compatible = "qcom,ipc-spinlock-sfpb"; + reg = <0x1f40000 0x8000>; + qcom,num-locks = <8>; + }; + + qcom,ghd { + compatible = "qcom,gladiator-hang-detect"; + qcom,threshold-arr = <0x179d141c 0x179d1420 + 0x179d1424 0x179d1428 0x179d142c 0x179d1430>; + qcom,config-reg = <0x179d1434>; + }; + + qcom,msm-gladiator-v2@17900000 { + compatible = "qcom,msm-gladiator-v2"; + reg = <0x17900000 0xe000>; + reg-names = "gladiator_base"; + interrupts = <0 22 0>; + clock-names = "atb_clk"; + clocks = <&clock_gcc clk_qdss_clk>; + }; + + qcom,smem@86000000 { + compatible = "qcom,smem"; + reg = <0x86000000 0x200000>, + <0x17911008 0x4>, + <0x778000 0x7000>, + <0x1fd4000 0x8>; + reg-names = "smem", "irq-reg-base", "aux-mem1", + "smem_targ_info_reg"; + qcom,mpu-enabled; + }; + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + }; + + qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-adsp"; + qcom,fastrpc-glink; + + qcom,msm_fastrpc_cpz_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 2>; + qcom,secure-context-bank; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 8>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 9>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 10>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 11>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb6 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 5>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb7 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 6>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb8 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 7>; + dma-coherent; + }; + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-glink"; + qcom,glink-edge = "rpm"; + rpm-channel-name = "rpm_requests"; + }; + + glink_mpss: qcom,glink-ssr-modem { + compatible = "qcom,glink_ssr"; + label = "modem"; + qcom,edge = "mpss"; + qcom,notify-edges = <&glink_lpass>, <&glink_dsps>, <&glink_rpm>, + <&glink_spss>; + qcom,xprt = "smem"; + }; + + glink_lpass: qcom,glink-ssr-adsp { + compatible = "qcom,glink_ssr"; + label = "adsp"; + qcom,edge = "lpass"; + qcom,notify-edges = <&glink_mpss>, <&glink_dsps>, <&glink_rpm>, + <&glink_spss>; + qcom,xprt = "smem"; + }; + + glink_dsps: qcom,glink-ssr-dsps { + compatible = "qcom,glink_ssr"; + label = "slpi"; + qcom,edge = "dsps"; + qcom,notify-edges = <&glink_mpss>, <&glink_lpass>, <&glink_rpm>, + <&glink_spss>; + qcom,xprt = "smem"; + }; + + glink_rpm: qcom,glink-ssr-rpm { + compatible = "qcom,glink_ssr"; + label = "rpm"; + qcom,edge = "rpm"; + qcom,notify-edges = <&glink_lpass>, <&glink_mpss>, + <&glink_dsps>, <&glink_spss>; + qcom,xprt = "smem"; + }; + + glink_spss: qcom,glink-ssr-spss { + compatible = "qcom,glink_ssr"; + label = "spss"; + qcom,edge = "spss"; + qcom,notify-edges = <&glink_mpss>, <&glink_lpass>, + <&glink_dsps>, <&glink_rpm>; + qcom,xprt = "mailbox"; + }; + + qcom,glink-smem-native-xprt-modem@86000000 { + compatible = "qcom,glink-smem-native-xprt"; + reg = <0x86000000 0x200000>, + <0x17911008 0x4>; + reg-names = "smem", "irq-reg-base"; + qcom,irq-mask = <0x8000>; + interrupts = <0 452 1>; + label = "mpss"; + }; + + qcom,glink-smem-native-xprt-adsp@86000000 { + compatible = "qcom,glink-smem-native-xprt"; + reg = <0x86000000 0x200000>, + <0x17911008 0x4>; + reg-names = "smem", "irq-reg-base"; + qcom,irq-mask = <0x200>; + interrupts = <0 157 1>; + label = "lpass"; + }; + + qcom,glink-smem-native-xprt-dsps@86000000 { + compatible = "qcom,glink-smem-native-xprt"; + reg = <0x86000000 0x200000>, + <0x17911008 0x4>; + reg-names = "smem", "irq-reg-base"; + qcom,irq-mask = <0x8000000>; + interrupts = <0 179 1>; + label = "dsps"; + }; + + qcom,glink-smem-native-xprt-rpm@778000 { + compatible = "qcom,glink-rpm-native-xprt"; + reg = <0x778000 0x7000>, + <0x17911008 0x4>; + reg-names = "msgram", "irq-reg-base"; + qcom,irq-mask = <0x1>; + interrupts = <0 168 1>; + label = "rpm"; + }; + + qcom,glink-mailbox-xprt-spss@1d05008 { + compatible = "qcom,glink-mailbox-xprt"; + reg = <0x1d05008 0x8>, + <0x1d05010 0x4>, + <0x1d0501c 0x4>, + <0x1d06008 0x4>; + reg-names = "mbox-loc-addr", "mbox-loc-size", "irq-reg-base", + "irq-rx-reset"; + qcom,irq-mask = <0x1>; + interrupts = <0 348 4>; + label = "spss"; + qcom,tx-ring-size = <0x800>; + qcom,rx-ring-size = <0x800>; + }; + + glink_spi_xprt_wdsp: qcom,glink-spi-xprt-wdsp { + compatible = "qcom,glink-spi-xprt"; + label = "wdsp"; + qcom,remote-fifo-config = <&glink_fifo_wdsp>; + qcom,qos-config = <&glink_qos_wdsp>; + qcom,ramp-time = <0x10>, + <0x20>, + <0x30>, + <0x40>; + }; + + glink_fifo_wdsp: qcom,glink-fifo-config-wdsp { + compatible = "qcom,glink-fifo-config"; + qcom,out-read-idx-reg = <0x12000>; + qcom,out-write-idx-reg = <0x12004>; + qcom,in-read-idx-reg = <0x1200C>; + qcom,in-write-idx-reg = <0x12010>; + }; + + glink_qos_wdsp: qcom,glink-qos-config-wdsp { + compatible = "qcom,glink-qos-config"; + qcom,flow-info = <0x80 0x0>, + <0x70 0x1>, + <0x60 0x2>, + <0x50 0x3>; + qcom,mtu-size = <0x800>; + qcom,tput-stats-cycle = <0xa>; + }; + + qcom,glink_pkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-loopback_cntl { + qcom,glinkpkt-transport = "lloop"; + qcom,glinkpkt-edge = "local"; + qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT"; + qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl"; + }; + + qcom,glinkpkt-loopback_data { + qcom,glinkpkt-transport = "lloop"; + qcom,glinkpkt-edge = "local"; + qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT"; + qcom,glinkpkt-dev-name = "glink_pkt_loopback"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + pcie0: qcom,pcie@01c00000 { + compatible = "qcom,pci-msm"; + cell-index = <0>; + + reg = <0x1c00000 0x2000>, + <0x1c06000 0x1000>, + <0x1b000000 0xf1d>, + <0x1b000f20 0xa8>, + <0x1b100000 0x100000>, + <0x1b200000 0x100000>, + <0x1b300000 0xd00000>; + + reg-names = "parf", "phy", "dm_core", "elbi", + "conf", "io", "bars"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>, + <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; + interrupt-parent = <&pcie0>; + interrupts = <0 1 2 3 4 5>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0xffffffff>; + interrupt-map = <0 0 0 0 &intc 0 0 405 0 + 0 0 0 1 &intc 0 0 135 0 + 0 0 0 2 &intc 0 0 136 0 + 0 0 0 3 &intc 0 0 138 0 + 0 0 0 4 &intc 0 0 139 0 + 0 0 0 5 &intc 0 0 278 0>; + + interrupt-names = "int_msi", "int_a", "int_b", "int_c", + "int_d", "int_global_int"; + + qcom,phy-sequence = <0x804 0x01 0x00 + 0x034 0x14 0x00 + 0x138 0x30 0x00 + 0x048 0x0f 0x00 + 0x15c 0x06 0x00 + 0x090 0x01 0x00 + 0x088 0x20 0x00 + 0x0f0 0x00 0x00 + 0x0f8 0x01 0x00 + 0x0f4 0xc9 0x00 + 0x11c 0xff 0x00 + 0x120 0x3f 0x00 + 0x164 0x01 0x00 + 0x154 0x00 0x00 + 0x148 0x0a 0x00 + 0x05C 0x19 0x00 + 0x038 0x90 0x00 + 0x0b0 0x82 0x00 + 0x0c0 0x03 0x00 + 0x0bc 0x55 0x00 + 0x0b8 0x55 0x00 + 0x0a0 0x00 0x00 + 0x09c 0x0d 0x00 + 0x098 0x04 0x00 + 0x13c 0x00 0x00 + 0x060 0x08 0x00 + 0x068 0x16 0x00 + 0x070 0x34 0x00 + 0x15c 0x06 0x00 + 0x138 0x33 0x00 + 0x03c 0x02 0x00 + 0x040 0x0e 0x00 + 0x080 0x04 0x00 + 0x0dc 0x00 0x00 + 0x0d8 0x3f 0x00 + 0x00c 0x09 0x00 + 0x010 0x01 0x00 + 0x01c 0x40 0x00 + 0x020 0x01 0x00 + 0x014 0x02 0x00 + 0x018 0x00 0x00 + 0x024 0x7e 0x00 + 0x028 0x15 0x00 + 0x244 0x02 0x00 + 0x2a4 0x12 0x00 + 0x260 0x10 0x00 + 0x28c 0x06 0x00 + 0x504 0x03 0x00 + 0x500 0x1c 0x00 + 0x50c 0x14 0x00 + 0x4d4 0x0a 0x00 + 0x4d8 0x04 0x00 + 0x4dc 0x1a 0x00 + 0x434 0x4b 0x00 + 0x414 0x04 0x00 + 0x40c 0x04 0x00 + 0x4f8 0x00 0x00 + 0x4fc 0x80 0x00 + 0x51c 0x40 0x00 + 0x444 0x71 0x00 + 0x43c 0x40 0x00 + 0x854 0x04 0x00 + 0x62c 0x52 0x00 + 0x9ac 0x00 0x00 + 0x8a0 0x01 0x00 + 0x9e0 0x00 0x00 + 0x9dc 0x01 0x00 + 0x9a8 0x00 0x00 + 0x8a4 0x01 0x00 + 0x8a8 0x73 0x00 + 0x9d8 0x99 0x00 + 0x9b0 0x03 0x00 + 0x804 0x03 0x00 + 0x800 0x00 0x00 + 0x808 0x03 0x00>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq_default + &pcie0_perst_default + &pcie0_wake_default>; + + perst-gpio = <&tlmm 35 0>; + wake-gpio = <&tlmm 37 0>; + + gdsc-vdd-supply = <&gdsc_pcie_0>; + vreg-1.8-supply = <&pm8998_l2>; + vreg-0.9-supply = <&pm8998_l1>; + vreg-cx-supply = <&pm8998_s1_level>; + + qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>; + qcom,vreg-0.9-voltage-level = <880000 880000 24000>; + qcom,vreg-cx-voltage-level = ; + + qcom,ep-latency = <10>; + + qcom,ep-wakeirq; + + linux,pci-domain = <0>; + + qcom,pcie-phy-ver = <0x20>; + qcom,use-19p2mhz-aux-clk; + + iommus = <&anoc1_smmu>; + qcom,smmu-exist; + qcom,smmu-sid-base = <0x1480>; + + qcom,msm-bus,name = "pcie0"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, + <45 512 500 800>; + + clocks = <&clock_gcc clk_gcc_pcie_0_pipe_clk>, + <&clock_gcc clk_ln_bb_clk1>, + <&clock_gcc clk_gcc_pcie_0_aux_clk>, + <&clock_gcc clk_gcc_pcie_0_cfg_ahb_clk>, + <&clock_gcc clk_gcc_pcie_0_mstr_axi_clk>, + <&clock_gcc clk_gcc_pcie_0_slv_axi_clk>, + <&clock_gcc clk_gcc_pcie_clkref_clk>; + + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", + "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", + "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", + "pcie_0_ldo"; + + max-clock-frequency-hz = <0>, <0>, <19200000>, + <0>, <0>, <0>, <0>, <0>, <0>, + <0>, <0>, <0>, <0>, <0>, <0>, + <0>, <0>; + + resets = <&clock_gcc PCIE_PHY_BCR>, + <&clock_gcc PCIE_0_PHY_BCR>, + <&clock_gcc PCIE_0_PHY_BCR>; + + reset-names = "pcie_phy_reset", + "pcie_0_phy_reset", + "pcie_0_phy_pipe_reset"; + }; + + qcom,ipc_router { + compatible = "qcom,ipc_router"; + qcom,node-id = <1>; + }; + + qcom,ipc_router_modem_xprt { + compatible = "qcom,ipc_router_glink_xprt"; + qcom,ch-name = "IPCRTR"; + qcom,xprt-remote = "mpss"; + qcom,glink-xprt = "smem"; + qcom,xprt-linkid = <1>; + qcom,xprt-version = <1>; + qcom,fragmented-data; + }; + + qcom,ipc_router_q6_xprt { + compatible = "qcom,ipc_router_glink_xprt"; + qcom,ch-name = "IPCRTR"; + qcom,xprt-remote = "lpass"; + qcom,glink-xprt = "smem"; + qcom,xprt-linkid = <1>; + qcom,xprt-version = <1>; + qcom,fragmented-data; + }; + + qcom,ipc_router_dsps_xprt { + compatible = "qcom,ipc_router_glink_xprt"; + qcom,ch-name = "IPCRTR"; + qcom,xprt-remote = "dsps"; + qcom,glink-xprt = "smem"; + qcom,xprt-linkid = <1>; + qcom,xprt-version = <1>; + qcom,fragmented-data; + }; + + qcom,spcom { + compatible = "qcom,spcom"; + + /* predefined channels, remote side is server */ + qcom,spcom-ch-names = "sp_kernel" , "sp_ssr"; + status = "ok"; + }; + + spss_utils: qcom,spss_utils { + compatible = "qcom,spss-utils"; + /* spss test fuse physical address */ + qcom,spss-fuse-addr = <0x007841c4 0x4>; + qcom,spss-fuse-bit = <27>; + qcom,spss-test-firmware-name = "spss"; /* default name */ + qcom,spss-prod-firmware-name = "spss1p"; /* 8 chars max */ + status = "ok"; + }; + + sdhc_2: sdhci@c0a4900 { + compatible = "qcom,sdhci-msm"; + reg = <0xc0a4900 0x314>, <0xc0a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = <0 125 0>, <0 221 0>; + interrupt-names = "hc_irq", "pwr_irq"; + + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc clk_gcc_sdcc2_ahb_clk>, + <&clock_gcc clk_gcc_sdcc2_apps_clk>; + + qcom,large-address-bus; + qcom,bus-width = <4>; + qcom,cpu-dma-latency-us = <701>; + + qcom,devfreq,freq-table = <52000000 200000000>; + + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */ + <81 512 1600 3200>, /* 400 KB/s*/ + <81 512 80000 160000>, /* 20 MB/s */ + <81 512 100000 200000>, /* 25 MB/s */ + <81 512 200000 400000>, /* 50 MB/s */ + <81 512 400000 800000>, /* 100 MB/s */ + <81 512 800000 800000>, /* 200 MB/s */ + <81 512 2048000 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100000000 200000000 4294967295>; + + status = "disabled"; + }; + + ufsphy1: ufsphy@1da7000 { + compatible = "qcom,ufs-phy-qmp-v3"; + reg = <0x1da7000 0xda8>; + reg-names = "phy_mem"; + #phy-cells = <0>; + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&clock_gcc clk_ln_bb_clk1>, + <&clock_gcc clk_gcc_ufs_clkref_clk>, + <&clock_gcc clk_gcc_ufs_phy_aux_hw_ctl_clk>; + status = "disabled"; + }; + + ufs_ice: ufsice@1db0000 { + compatible = "qcom,ice"; + reg = <0x1db0000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ufs_core_clk", + "bus_clk", + "iface_clk", + "ice_core_clk"; + clocks = <&clock_gcc clk_gcc_ufs_axi_clk>, + <&clock_gcc clk_gcc_aggre1_ufs_axi_clk>, + <&clock_gcc clk_gcc_ufs_ahb_clk>, + <&clock_gcc clk_gcc_ufs_ice_core_clk>; + qcom,op-freq-hz = <0>, + <0>, + <0>, + <300000000>; + vdd-hba-supply = <&gdsc_ufs>; + qcom,msm-bus,name = "ufs_ice_noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 650 0 0>, /* No vote */ + <1 650 1000 0>; /* Max. bandwidth */ + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "ufs"; + status = "disabled"; + }; + + ufs1: ufshc@1da4000 { + compatible = "qcom,ufshc"; + reg = <0x1da4000 0x2500>; + interrupts = <0 265 0>; + phys = <&ufsphy1>; + phy-names = "ufsphy"; + ufs-qcom-crypto = <&ufs_ice>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + clocks = + <&clock_gcc clk_gcc_ufs_axi_hw_ctl_clk>, + <&clock_gcc clk_gcc_aggre1_ufs_axi_hw_ctl_clk>, + <&clock_gcc clk_gcc_ufs_ahb_clk>, + <&clock_gcc clk_gcc_ufs_unipro_core_hw_ctl_clk>, + <&clock_gcc clk_gcc_ufs_ice_core_hw_ctl_clk>, + <&clock_gcc clk_ln_bb_clk1>, + <&clock_gcc clk_gcc_ufs_tx_symbol_0_clk>, + <&clock_gcc clk_gcc_ufs_rx_symbol_0_clk>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + + lanes-per-direction = <1>; + + qcom,msm-bus,name = "ufs1"; + qcom,msm-bus,num-cases = <22>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <95 512 0 0>, <1 650 0 0>, /* No vote */ + <95 512 922 0>, <1 650 1000 0>, /* PWM G1 */ + <95 512 1844 0>, <1 650 1000 0>, /* PWM G2 */ + <95 512 3688 0>, <1 650 1000 0>, /* PWM G3 */ + <95 512 7376 0>, <1 650 1000 0>, /* PWM G4 */ + <95 512 1844 0>, <1 650 1000 0>, /* PWM G1 L2 */ + <95 512 3688 0>, <1 650 1000 0>, /* PWM G2 L2 */ + <95 512 7376 0>, <1 650 1000 0>, /* PWM G3 L2 */ + <95 512 14752 0>, <1 650 1000 0>, /* PWM G4 L2 */ + <95 512 127796 0>, <1 650 1000 0>, /* HS G1 RA */ + <95 512 255591 0>, <1 650 1000 0>, /* HS G2 RA */ + <95 512 511181 0>, <1 650 1000 0>, /* HS G3 RA */ + <95 512 255591 0>, <1 650 1000 0>, /* HS G1 RA L2 */ + <95 512 511181 0>, <1 650 1000 0>, /* HS G2 RA L2 */ + <95 512 1022362 0>, <1 650 1000 0>, /* HS G3 RA L2 */ + <95 512 149422 0>, <1 650 1000 0>, /* HS G1 RB */ + <95 512 298189 0>, <1 650 1000 0>, /* HS G2 RB */ + <95 512 596378 0>, <1 650 1000 0>, /* HS G3 RB */ + <95 512 298189 0>, <1 650 1000 0>, /* HS G1 RB L2 */ + <95 512 596378 0>, <1 650 1000 0>, /* HS G2 RB L2 */ + <95 512 1192756 0>, <1 650 1000 0>, /* HS G3 RB L2 */ + <95 512 4096000 0>, <1 650 1000 0>; /* Max. bandwidth */ + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", + "MAX"; + + /* PM QoS */ + qcom,pm-qos-cpu-groups = <0x0F 0xF0>; + qcom,pm-qos-cpu-group-latency-us = <70 70>; + qcom,pm-qos-default-cpu = <0>; + + resets = <&clock_gcc UFS_BCR>; + reset-names = "core_reset"; + + status = "disabled"; + }; + + usb3: ssusb@a800000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a800000 0xf8c00>, + <0x0c016000 0x400>; + reg-names = "core_base", "ahb2phy_base"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = <0 347 0>, <0 243 0>, <0 180 0>; + interrupt-names = "hs_phy_irq", "ss_phy_irq", "pwr_event_irq"; + + USB3_GDSC-supply = <&gdsc_usb30>; + qcom,usb-dbm = <&dbm_1p5>; + qcom,msm-bus,name = "usb3"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <61 512 0 0>, + <61 512 240000 800000>; + + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + extcon = <&pm660_pdphy>; + + clocks = <&clock_gcc clk_gcc_usb30_master_clk>, + <&clock_gcc clk_gcc_cfg_noc_usb3_axi_clk>, + <&clock_gcc clk_gcc_aggre1_usb3_axi_clk>, + <&clock_gcc clk_gcc_usb30_mock_utmi_clk>, + <&clock_gcc clk_gcc_usb30_sleep_clk>, + <&clock_gcc clk_cxo_dwc3_clk>; + + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk", "xo"; + + qcom,core-clk-rate = <120000000>; + + resets = <&clock_gcc USB_30_BCR>; + reset-names = "core_reset"; + + dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0x0a800000 0xcd00>; + interrupt-parent = <&intc>; + interrupts = <0 131 0>; + usb-phy = <&qusb_phy0>, <&ssphy>; + tx-fifo-resize; + snps,nominal-elastic-buffer; + snps,hird_thresh = <0x10>; + snps,num-gsi-evt-buffs = <0x3>; + }; + + qcom,usbbam@a904000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xa904000 0x17000>; + interrupt-parent = <&intc>; + interrupts = <0 132 0>; + + qcom,bam-type = <0>; + qcom,usb-bam-fifo-baseaddr = <0x146bb000>; + qcom,usb-bam-num-pipes = <8>; + qcom,ignore-core-reset-ack; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x6064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; + }; + + qusb_phy0: qusb@c012000 { + compatible = "qcom,qusb2phy-v2"; + reg = <0x0c012000 0x2a8>, + <0x01fcb24c 0x4>; + reg-names = "qusb_phy_base", + "tcsr_clamp_dig_n_1p8"; + vdd-supply = <&pm660l_l1>; + vdda18-supply = <&pm660l_l10>; + vdda33-supply = <&pm660l_l7>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,qusb-phy-init-seq = + /* */ + <0x80 0x0 + 0x13 0x04 + 0x7c 0x18c + 0x80 0x2c + 0x0a 0x184 + 0x00 0x240>; + phy_type= "utmi"; + + clocks = <&clock_gcc clk_ln_bb_clk1>, + <&clock_gcc clk_gcc_rx1_usb2_clkref_clk>; + clock-names = "ref_clk_src", "ref_clk"; + + resets = <&clock_gcc QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + ssphy: ssphy@c010000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x0c010000 0xe0c>, + <0x01fcb244 0x4>, + <0x01fcb248 0x4>; + reg-names = "qmp_phy_base", + "vls_clamp_reg", + "tcsr_usb3_dp_phymode"; + vdd-supply = <&pm660l_l1>; + core-supply = <&pm660_l1>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vbus-valid-override; + qcom,qmp-phy-init-seq = + /* */ + <0x138 0x30 0x00 + 0x034 0x04 0x01 + 0x080 0x14 0x00 + 0x03c 0x06 0x00 + 0x08c 0x08 0x00 + 0x15c 0x06 0x00 + 0x164 0x01 0x00 + 0x13c 0x80 0x00 + 0x0b0 0x82 0x00 + 0x0b8 0xab 0x00 + 0x0bc 0xea 0x00 + 0x0c0 0x02 0x00 + 0x060 0x06 0x00 + 0x068 0x16 0x00 + 0x070 0x36 0x00 + 0x0dc 0x00 0x00 + 0x0d8 0x3f 0x00 + 0x0f8 0x01 0x00 + 0x0f4 0xc9 0x00 + 0x148 0x0a 0x00 + 0x0a0 0x00 0x00 + 0x09c 0x34 0x00 + 0x098 0x15 0x00 + 0x090 0x04 0x00 + 0x154 0x00 0x00 + 0x094 0x00 0x00 + 0x0f0 0x00 0x00 + 0x00c 0x0a 0x00 + 0x048 0x07 0x00 + 0x0d0 0x80 0x00 + 0x184 0x01 0x00 + 0x010 0x01 0x00 + 0x01c 0x31 0x00 + 0x020 0x01 0x00 + 0x014 0x00 0x00 + 0x018 0x00 0x00 + 0x024 0x85 0x00 + 0x028 0x07 0x00 + 0x430 0x0b 0x00 + 0x4d4 0x0f 0x00 + 0x4d8 0x4e 0x00 + 0x4dc 0x18 0x00 + 0x4f8 0x07 0x00 + 0x4fc 0x80 0x00 + 0x504 0x43 0x00 + 0x50c 0x1c 0x00 + 0x434 0x75 0x00 + 0x43c 0x00 0x00 + 0x440 0x00 0x00 + 0x444 0x80 0x00 + 0x408 0x0a 0x00 + 0x414 0x06 0x00 + 0x500 0x00 0x00 + 0x4c0 0x03 0x00 + 0x564 0x05 0x00 + 0x830 0x0b 0x00 + 0x8d4 0x0f 0x00 + 0x8d8 0x4e 0x00 + 0x8dc 0x18 0x00 + 0x8f8 0x07 0x00 + 0x8fc 0x80 0x00 + 0x904 0x43 0x00 + 0x90c 0x1c 0x00 + 0x834 0x75 0x00 + 0x83c 0x00 0x00 + 0x840 0x00 0x00 + 0x844 0x80 0x00 + 0x808 0x0a 0x00 + 0x814 0x06 0x00 + 0x900 0x00 0x00 + 0x8c0 0x03 0x00 + 0x964 0x05 0x00 + 0x260 0x10 0x00 + 0x2a4 0x12 0x00 + 0x28c 0x16 0x00 + 0x244 0x00 0x00 + 0x660 0x10 0x00 + 0x6a4 0x12 0x00 + 0x68c 0x16 0x00 + 0x644 0x00 0x00 + 0xcc8 0x83 0x00 + 0xccc 0x09 0x00 + 0xcd0 0xa2 0x00 + 0xcd4 0x40 0x00 + 0xcc4 0x02 0x00 + 0xc80 0xd1 0x00 + 0xc84 0x1f 0x00 + 0xc88 0x47 0x00 + 0xc64 0x1b 0x00 + 0xc0c 0x9f 0x00 + 0xc10 0x9f 0x00 + 0xc14 0xb7 0x00 + 0xc18 0x4e 0x00 + 0xc1c 0x65 0x00 + 0xc20 0x6b 0x00 + 0xc24 0x15 0x00 + 0xc28 0x0d 0x00 + 0xc2c 0x15 0x00 + 0xc30 0x0d 0x00 + 0xc34 0x15 0x00 + 0xc38 0x0d 0x00 + 0xc3c 0x15 0x00 + 0xc40 0x0d 0x00 + 0xc44 0x15 0x00 + 0xc48 0x0d 0x00 + 0xc4c 0x15 0x00 + 0xc50 0x0d 0x00 + 0xc5c 0x02 0x00 + 0xca0 0x04 0x00 + 0xc8c 0x44 0x00 + 0xc70 0xe7 0x00 + 0xc74 0x03 0x00 + 0xc78 0x40 0x00 + 0xc7c 0x00 0x00 + 0xdd8 0x8a 0x00 + 0xcb8 0x75 0x00 + 0xcb0 0x86 0x00 + 0xcbc 0x13 0x00 + 0xffffffff 0xffffffff 0x00>; + + qcom,qmp-phy-reg-offset = + <0xd74 /* USB3_PHY_PCS_STATUS */ + 0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */ + 0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */ + 0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */ + 0xc00 /* USB3_PHY_SW_RESET */ + 0xc08 /* USB3_PHY_START */ + 0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */ + + clocks = <&clock_gcc clk_gcc_usb3_phy_aux_clk>, + <&clock_gcc clk_gcc_usb3_phy_pipe_clk>, + <&clock_gcc clk_ln_bb_clk1>, + <&clock_gcc clk_gcc_usb3_clkref_clk>; + + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "ref_clk"; + + resets = <&clock_gcc USB3_PHY_BCR>, + <&clock_gcc USB3PHY_PHY_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&lpass_q6_smmu 12>; + qcom,usb-audio-stream-id = <12>; + qcom,usb-audio-intr-num = <2>; + }; + + dbm_1p5: dbm@a8f8000 { + compatible = "qcom,usb-dbm-1p5"; + reg = <0xa8f8000 0x300>; + qcom,reset-ep-after-lpm-resume; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + qcom,lpass@17300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x17300000 0x00100>; + interrupts = <0 162 1>; + + vdd_cx-supply = <&pm660l_s3_level>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + + clocks = <&clock_gcc clk_cxo_pil_lpass_clk>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <1>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <423>; + qcom,sysmon-id = <1>; + status = "ok"; + qcom,ssctl-instance-id = <0x14>; + qcom,firmware-name = "adsp"; + memory-region = <&pil_adsp_mem>; + + /* GPIO inputs from lpass */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>; + qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>; + + /* GPIO output to lpass */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>; + }; + + pil_modem: qcom,mss@4080000 { + compatible = "qcom,pil-q6v55-mss"; + reg = <0x4080000 0x100>, + <0x1f63000 0x008>, + <0x1f65000 0x008>, + <0x1f64000 0x008>, + <0x4180000 0x020>, + <0x00179000 0x004>; + reg-names = "qdsp6_base", "halt_q6", "halt_modem", + "halt_nc", "rmb_base", "restart_reg"; + + clocks = <&clock_gcc clk_cxo_clk_src>, + <&clock_gcc clk_gcc_mss_cfg_ahb_clk>, + <&clock_gcc clk_gcc_bimc_mss_q6_axi_clk>, + <&clock_gcc clk_gcc_boot_rom_ahb_clk>, + <&clock_gcc clk_gpll0_out_msscc>, + <&clock_gcc clk_gcc_mss_snoc_axi_clk>, + <&clock_gcc clk_gcc_mss_mnoc_bimc_axi_clk>, + <&clock_gcc clk_qdss_clk>; + clock-names = "xo", "iface_clk", "bus_clk", + "mem_clk", "gpll0_mss_clk", "snoc_axi_clk", + "mnoc_axi_clk", "qdss_clk"; + qcom,proxy-clock-names = "xo", "qdss_clk"; + qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk", + "gpll0_mss_clk", "snoc_axi_clk", + "mnoc_axi_clk"; + + interrupts = <0 448 1>; + vdd_cx-supply = <&pm660l_s3_level>; + vdd_cx-voltage = ; + vdd_mx-supply = <&pm660l_s5_level>; + vdd_mx-uV = ; + qcom,firmware-name = "modem"; + qcom,pil-self-auth; + qcom,sysmon-id = <0>; + qcom,ssctl-instance-id = <0x12>; + qcom,override-acc; + qcom,qdsp6v62-1-2; + status = "ok"; + memory-region = <&modem_mem>; + qcom,mem-protect-id = <0xF>; + + /* GPIO inputs from mss */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; + qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>; + qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>; + + /* GPIO output to mss */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; + }; + + tsens0: tsens@10aa000 { + compatible = "qcom,msm8998-tsens"; + reg = <0x10aa000 0x2000>; + reg-names = "tsens_physical"; + interrupts = <0 458 0>, <0 445 0>; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + qcom,client-id = <0 1 2 3 4 7 8 9 10 11 12 13>; + qcom,sensor-id = <0 1 2 3 4 7 8 9 10 11 12 13>; + qcom,sensors = <12>; + }; + + tsens1: tsens@10ad000 { + compatible = "qcom,msm8998-tsens"; + reg = <0x10ad000 0x2000>; + reg-names = "tsens_physical"; + interrupts = <0 184 0>, <0 430 0>; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + qcom,client-id = <14 15 16 17 18 19 20 21>; + qcom,sensor-id = <0 1 3 4 5 6 7 2>; + qcom,sensors = <8>; + }; + + qcom,sensor-information { + compatible = "qcom,sensor-information"; + sensor_information0: qcom,sensor-information-0 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor0"; + qcom,scaling-factor = <10>; + }; + sensor_information1: qcom,sensor-information-1 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor1"; + qcom,scaling-factor = <10>; + }; + sensor_information2: qcom,sensor-information-2 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor2"; + qcom,scaling-factor = <10>; + }; + sensor_information3: qcom,sensor-information-3 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor3"; + qcom,scaling-factor = <10>; + }; + sensor_information4: qcom,sensor-information-4 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor4"; + qcom,scaling-factor = <10>; + }; + sensor_information7: qcom,sensor-information-7 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor7"; + qcom,scaling-factor = <10>; + }; + sensor_information8: qcom,sensor-information-8 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor8"; + qcom,scaling-factor = <10>; + }; + sensor_information9: qcom,sensor-information-9 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor9"; + qcom,scaling-factor = <10>; + }; + sensor_information10: qcom,sensor-information-10 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor10"; + qcom,scaling-factor = <10>; + }; + sensor_information11: qcom,sensor-information-11 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor11"; + qcom,scaling-factor = <10>; + }; + sensor_information12: qcom,sensor-information-12 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor12"; + qcom,scaling-factor = <10>; + }; + sensor_information13: qcom,sensor-information-13 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor13"; + qcom,scaling-factor = <10>; + qcom,alias-name = "gpu"; + }; + sensor_information14: qcom,sensor-information-14 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor14"; + qcom,scaling-factor = <10>; + }; + sensor_information15: qcom,sensor-information-15 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor15"; + qcom,scaling-factor = <10>; + }; + sensor_information16: qcom,sensor-information-16 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor16"; + qcom,alias-name = "pop_mem"; + qcom,scaling-factor = <10>; + }; + sensor_information17: qcom,sensor-information-17 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor17"; + qcom,scaling-factor = <10>; + }; + sensor_information18: qcom,sensor-information-18 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor18"; + qcom,scaling-factor = <10>; + }; + sensor_information19: qcom,sensor-information-19 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor19"; + qcom,scaling-factor = <10>; + }; + sensor_information20: qcom,sensor-information-20 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor20"; + qcom,scaling-factor = <10>; + }; + sensor_information21: qcom,sensor-information-21 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor21"; + qcom,scaling-factor = <10>; + }; + sensor_information22: qcom,sensor-information-22 { + qcom,sensor-type = "alarm"; + qcom,sensor-name = "pm8994_tz"; + qcom,scaling-factor = <1000>; + }; + sensor_information23: qcom,sensor-information-23 { + qcom,sensor-type = "adc"; + qcom,sensor-name = "msm_therm"; + }; + sensor_information24: qcom,sensor-information-24 { + qcom,sensor-type = "adc"; + qcom,sensor-name = "emmc_therm"; + }; + sensor_information25: qcom,sensor-information-25 { + qcom,sensor-type = "adc"; + qcom,sensor-name = "pa_therm0"; + }; + sensor_information26: qcom,sensor-information-26 { + qcom,sensor-type = "adc"; + qcom,sensor-name = "pa_therm1"; + }; + sensor_information27: qcom,sensor-information-27 { + qcom,sensor-type = "adc"; + qcom,sensor-name = "quiet_therm"; + }; + sensor_information28: qcom,sensor-information-28 { + qcom,sensor-type = "llm"; + qcom,sensor-name = "limits_sensor-01"; + }; + sensor_information29: qcom,sensor-information-29 { + qcom,sensor-type = "llm"; + qcom,sensor-name = "limits_sensor-02"; + }; + }; + + qcom_seecom: qseecom@86600000 { + compatible = "qcom,qseecom"; + reg = <0x86600000 0x2200000>; + reg-names = "secapp-region"; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,support-fde; + qcom,no-clock-support; + qcom,appsbl-qseecom-support; + qcom,commonlib64-loaded-by-uefi; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 0 0>, + <55 512 120000 1200000>, + <55 512 393600 3936000>; + clock-names = "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = <&clock_gcc clk_ce1_clk>, + <&clock_gcc clk_qseecom_ce1_clk>, + <&clock_gcc clk_gcc_ce1_ahb_m_clk>, + <&clock_gcc clk_gcc_ce1_axi_m_clk>; + qcom,ce-opp-freq = <171430000>; + qcom,qsee-reentrancy-support = <2>; + }; + + qcom_tzlog: tz-log@146BF720 { + compatible = "qcom,tz-log"; + reg = <0x146BF720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; /* 0x066BFB30 */ + hyplog-size-offset = <0x414>; /* 0x066BFB34 */ + }; + + qcom_crypto: qcrypto@1DE0000 { + compatible = "qcom,qcrypto"; + reg = <0x1DE0000 0x20000>, + <0x1DC4000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 206 0>; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,bam-ee = <0>; + qcom,ce-hw-shared; + qcom,clk-mgmt-sus-res; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 3936000 393600>; + clock-names = "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = <&clock_gcc clk_qcrypto_ce1_clk>, + <&clock_gcc clk_qcrypto_ce1_clk>, + <&clock_gcc clk_gcc_ce1_ahb_m_clk>, + <&clock_gcc clk_gcc_ce1_axi_m_clk>; + qcom,ce-opp-freq = <171430000>; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-aead-algo; + qcom,use-sw-hmac-algo; + }; + + qcom_cedev: qcedev@1DE0000{ + compatible = "qcom,qcedev"; + reg = <0x1DE0000 0x20000>, + <0x1DC4000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 206 0>; + qcom,bam-pipe-pair = <1>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,bam-ee = <0>; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 3936000 393600>; + clock-names = "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = <&clock_gcc clk_qcedev_ce1_clk>, + <&clock_gcc clk_qcedev_ce1_clk>, + <&clock_gcc clk_gcc_ce1_ahb_m_clk>, + <&clock_gcc clk_gcc_ce1_axi_m_clk>; + qcom,ce-opp-freq = <171430000>; + }; + + qcom_rng: qrng@793000 { + compatible = "qcom,msm-rng"; + reg = <0x793000 0x1000>; + qcom,msm-rng-iface-clk; + qcom,no-qrng-config; + qcom,msm-bus,name = "msm-rng-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 618 0 0>, /* No vote */ + <1 618 0 800>; /* 100 MB/s */ + clocks = <&clock_gcc clk_gcc_prng_ahb_clk>; + clock-names = "iface_clk"; + }; + + mitigation_profile0: qcom,limit_info-0 { + qcom,temperature-sensor = <&sensor_information1>; + qcom,hotplug-mitigation-enable; + }; + + mitigation_profile1: qcom,limit_info-1 { + qcom,temperature-sensor = <&sensor_information2>; + qcom,hotplug-mitigation-enable; + }; + + mitigation_profile2: qcom,limit_info-2 { + qcom,temperature-sensor = <&sensor_information3>; + qcom,hotplug-mitigation-enable; + }; + + mitigation_profile3: qcom,limit_info-3 { + qcom,temperature-sensor = <&sensor_information4>; + qcom,hotplug-mitigation-enable; + }; + + mitigation_profile4: qcom,limit_info-4 { + qcom,temperature-sensor = <&sensor_information7>; + qcom,hotplug-mitigation-enable; + }; + + mitigation_profile5: qcom,limit_info-5 { + qcom,temperature-sensor = <&sensor_information8>; + qcom,hotplug-mitigation-enable; + }; + + mitigation_profile6: qcom,limit_info-6 { + qcom,temperature-sensor = <&sensor_information9>; + qcom,hotplug-mitigation-enable; + }; + + mitigation_profile7: qcom,limit_info-7 { + qcom,temperature-sensor = <&sensor_information10>; + qcom,hotplug-mitigation-enable; + }; + + qcom,lmh { + compatible = "qcom,lmh_v1"; + interrupts = ; + }; + + qcom,msm-thermal { + compatible = "qcom,msm-thermal"; + qcom,sensor-id = <1>; + qcom,poll-ms = <100>; + qcom,therm-reset-temp = <115>; + qcom,core-limit-temp = <70>; + qcom,core-temp-hysteresis = <10>; + qcom,hotplug-temp = <105>; + qcom,hotplug-temp-hysteresis = <20>; + qcom,online-hotplug-core; + qcom,synchronous-cluster-id = <0 1>; + qcom,synchronous-cluster-map = <0 4 &CPU0 &CPU1 &CPU2 &CPU3>, + <1 4 &CPU4 &CPU5 &CPU6 &CPU7>; + clock-names = "osm"; + clocks = <&clock_cpu clk_pwrcl_clk>; + + qcom,vdd-restriction-temp = <5>; + qcom,vdd-restriction-temp-hysteresis = <10>; + + vdd-dig-supply = <&pm8998_s1_floor_level>; + vdd-gfx-supply = <&gfx_vreg>; + + qcom,vdd-dig-rstr{ + qcom,vdd-rstr-reg = "vdd-dig"; + qcom,levels = ; + /* Nominal, Super Turbo, Super Turbo */ + qcom,min-level = ; + /* No Request */ + }; + + qcom,vdd-gfx-rstr{ + qcom,vdd-rstr-reg = "vdd-gfx"; + qcom,levels = <5 6 6>; /* Nominal, Turbo, Turbo */ + qcom,min-level = <1>; /* No Request */ + }; + + msm_thermal_freq: qcom,vdd-apps-rstr{ + qcom,vdd-rstr-reg = "vdd-apps"; + qcom,levels = <1248000>; + qcom,freq-req; + }; + }; + + qcom,bcl { + compatible = "qcom,bcl"; + qcom,bcl-enable; + qcom,bcl-framework-interface; + qcom,bcl-freq-control-list = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,bcl-hotplug-list = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,bcl-soc-hotplug-list = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,ibat-monitor { + qcom,low-threshold-uamp = <3400000>; + qcom,high-threshold-uamp = <4200000>; + qcom,mitigation-freq-khz = <576000>; + qcom,vph-high-threshold-uv = <3500000>; + qcom,vph-low-threshold-uv = <3300000>; + qcom,soc-low-threshold = <10>; + qcom,thermal-handle = <&msm_thermal_freq>; + }; + }; + + qcom,ssc@5c00000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x5c00000 0x4000>; + interrupts = <0 390 1>; + + vdd_cx-supply = <&pm660l_l9_level>; + qcom,vdd_cx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx"; + qcom,keep-proxy-regs-on; + + clocks = <&clock_gcc clk_cxo_pil_ssc_clk>, + <&clock_gcc clk_aggre2_noc_clk>; + clock-names = "xo", "aggre2"; + qcom,proxy-clock-names = "xo", "aggre2"; + + qcom,pas-id = <12>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <424>; + qcom,sysmon-id = <3>; + qcom,ssctl-instance-id = <0x16>; + qcom,firmware-name = "slpi"; + status = "ok"; + memory-region = <&pil_slpi_mem>; + + /* GPIO inputs from ssc */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_3_in 0 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_3_in 2 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_3_in 1 0>; + qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_3_in 3 0>; + + /* GPIO output to ssc */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_3_out 0 0>; + }; + + qcom,venus@cce0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xcce0000 0x4000>; + + vdd-supply = <&gdsc_venus>; + qcom,proxy-reg-names = "vdd"; + + clocks = <&clock_mmss clk_mmss_video_core_clk>, + <&clock_mmss clk_mmss_mnoc_ahb_clk>, + <&clock_mmss clk_mmss_video_ahb_clk>, + <&clock_gcc clk_mmssnoc_axi_clk>, + <&clock_mmss clk_mmss_video_axi_clk>, + <&clock_mmss clk_mmss_video_maxi_clk>; + clock-names = "core_clk", "mnoc_ahb_clk", "iface_clk", + "noc_axi_clk", "bus_clk", "maxi_clk"; + qcom,proxy-clock-names = "core_clk","mnoc_ahb_clk", + "iface_clk", "noc_axi_clk", "bus_clk", "maxi_clk"; + + qcom,pas-id = <9>; + qcom,msm-bus,name = "pil-venus"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <63 512 0 0>, + <63 512 0 304000>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&pil_video_mem>; + status = "ok"; + }; + + wdog: qcom,wdt@17817000 { + compatible = "qcom,msm-watchdog"; + reg = <0x17817000 0x1000>; + reg-names = "wdt-base"; + interrupts = <0 3 0>, <0 4 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <10000>; + qcom,ipi-ping; + qcom,wakeup-enable; + qcom,scandump-size = <0x40000>; + }; + + qcom,spss@1d00000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x1d0101c 0x4>, + <0x1d01024 0x4>, + <0x1d01028 0x4>, + <0x1d0103c 0x4>, + <0x1d02030 0x4>; + reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", + "sp2soc_irq_mask", "rmb_err", "rmb_err_spare2"; + interrupts = <0 352 1>; + + vdd_cx-supply = <&pm8998_s1_level>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + + clocks = <&clock_gcc clk_cxo_pil_spss_clk>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + qcom,pil-generic-irq-handler; + status = "ok"; + + qcom,pas-id = <14>; + qcom,proxy-timeout-ms = <10000>; + qcom,firmware-name = "spss"; + memory-region = <&spss_mem>; + qcom,spss-scsr-bits = <24 25>; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + qcom,mpm2-sleep-counter@10a3000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0x010a3000 0x1000>; + clock-frequency = <32768>; + }; + + qcom,msm-imem@146bf000 { + compatible = "qcom,msm-imem"; + reg = <0x146bf000 0x1000>; + ranges = <0x0 0x146bf000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 8>; + }; + + dload_type@18 { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x18 4>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 32>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 200>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 200>; + }; + }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = <1 6 4>; + }; + + cpuss_dump { + compatible = "qcom,cpuss-dump"; + qcom,l1_i_cache0 { + qcom,dump-node = <&L1_I_0>; + qcom,dump-id = <0x60>; + }; + qcom,l1_i_cache1 { + qcom,dump-node = <&L1_I_1>; + qcom,dump-id = <0x61>; + }; + qcom,l1_i_cache2 { + qcom,dump-node = <&L1_I_2>; + qcom,dump-id = <0x62>; + }; + qcom,l1_i_cache3 { + qcom,dump-node = <&L1_I_3>; + qcom,dump-id = <0x63>; + }; + qcom,l1_i_cache100 { + qcom,dump-node = <&L1_I_100>; + qcom,dump-id = <0x64>; + }; + qcom,l1_i_cache101 { + qcom,dump-node = <&L1_I_101>; + qcom,dump-id = <0x65>; + }; + qcom,l1_i_cache102 { + qcom,dump-node = <&L1_I_102>; + qcom,dump-id = <0x66>; + }; + qcom,l1_i_cache103 { + qcom,dump-node = <&L1_I_103>; + qcom,dump-id = <0x67>; + }; + qcom,l1_d_cache0 { + qcom,dump-node = <&L1_D_0>; + qcom,dump-id = <0x80>; + }; + qcom,l1_d_cache1 { + qcom,dump-node = <&L1_D_1>; + qcom,dump-id = <0x81>; + }; + qcom,l1_d_cache2 { + qcom,dump-node = <&L1_D_2>; + qcom,dump-id = <0x82>; + }; + qcom,l1_d_cache3 { + qcom,dump-node = <&L1_D_3>; + qcom,dump-id = <0x83>; + }; + qcom,l1_d_cache100 { + qcom,dump-node = <&L1_D_100>; + qcom,dump-id = <0x84>; + }; + qcom,l1_d_cache101 { + qcom,dump-node = <&L1_D_101>; + qcom,dump-id = <0x85>; + }; + qcom,l1_d_cache102 { + qcom,dump-node = <&L1_D_102>; + qcom,dump-id = <0x86>; + }; + qcom,l1_d_cache103 { + qcom,dump-node = <&L1_D_103>; + qcom,dump-id = <0x87>; + }; + }; + + qcom,msm-ssc-sensors { + compatible = "qcom,msm-ssc-sensors"; + status = "ok"; + }; + + dcc: dcc@10b3000 { + compatible = "qcom,dcc"; + reg = <0x10b3000 0x1000>, + <0x10b4000 0x2000>; + reg-names = "dcc-base", "dcc-ram-base"; + + clocks = <&clock_gcc clk_gcc_dcc_ahb_clk>; + clock-names = "dcc_clk"; + }; + + qcom,msm-core@780000 { + compatible = "qcom,apss-core-ea"; + reg = <0x780000 0x1000>; + qcom,low-hyst-temp = <10>; + qcom,high-hyst-temp = <5>; + qcom,polling-interval = <50>; + + ea0: ea0 { + sensor = <&sensor_information1>; + }; + + ea1: ea1 { + sensor = <&sensor_information2>; + }; + + ea2: ea2 { + sensor = <&sensor_information3>; + }; + + ea3: ea3 { + sensor = <&sensor_information4>; + }; + + ea4: ea4 { + sensor = <&sensor_information7>; + }; + + ea5: ea5 { + sensor = <&sensor_information8>; + }; + + ea6: ea6 { + sensor = <&sensor_information9>; + }; + + ea7: ea7 { + sensor = <&sensor_information10>; + }; + + }; + + qcom,icnss@18800000 { + compatible = "qcom,icnss"; + reg = <0x18800000 0x800000>, + <0x10AC000 0x20>, + <0xa0000000 0x10000000>, + <0xb0000000 0x10000>; + reg-names = "membase", "mpm_config", + "smmu_iova_base", "smmu_iova_ipa"; + iommus = <&anoc2_smmu 0x1900>, + <&anoc2_smmu 0x1901>; + interrupts = <0 413 0 /* CE0 */ >, + <0 414 0 /* CE1 */ >, + <0 415 0 /* CE2 */ >, + <0 416 0 /* CE3 */ >, + <0 417 0 /* CE4 */ >, + <0 418 0 /* CE5 */ >, + <0 420 0 /* CE6 */ >, + <0 421 0 /* CE7 */ >, + <0 422 0 /* CE8 */ >, + <0 423 0 /* CE9 */ >, + <0 424 0 /* CE10 */ >, + <0 425 0 /* CE11 */ >; + qcom,wlan-msa-memory = <0x100000>; + qcom,icnss-vadc = <&pm660_vadc>; + qcom,icnss-adc_tm = <&pm660_adc_tm>; + }; + + tspp: msm_tspp@0c1e7000 { + compatible = "qcom,msm_tspp"; + reg = <0x0c1e7000 0x200>, /* MSM_TSIF0_PHYS */ + <0x0c1e8000 0x200>, /* MSM_TSIF1_PHYS */ + <0x0c1e9000 0x1000>, /* MSM_TSPP_PHYS */ + <0x0c1c4000 0x23000>; /* MSM_TSPP_BAM_PHYS */ + reg-names = "MSM_TSIF0_PHYS", + "MSM_TSIF1_PHYS", + "MSM_TSPP_PHYS", + "MSM_TSPP_BAM_PHYS"; + interrupts = <0 121 0>, /* TSIF_TSPP_IRQ */ + <0 119 0>, /* TSIF0_IRQ */ + <0 120 0>, /* TSIF1_IRQ */ + <0 122 0>; /* TSIF_BAM_IRQ */ + interrupt-names = "TSIF_TSPP_IRQ", + "TSIF0_IRQ", + "TSIF1_IRQ", + "TSIF_BAM_IRQ"; + + clock-names = "iface_clk", "ref_clk"; + clocks = <&clock_gcc clk_gcc_tsif_ahb_clk>, + <&clock_gcc clk_gcc_tsif_ref_clk>; + + qcom,msm-bus,name = "tsif"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <82 512 0 0>, /* No vote */ + <82 512 12288 24576>; + /* Max. bandwidth, 2xTSIF, each max of 96Mbps */ + + pinctrl-names = "disabled", + "tsif0-mode1", "tsif0-mode2", + "tsif1-mode1", "tsif1-mode2", + "dual-tsif-mode1", "dual-tsif-mode2"; + + pinctrl-0 = <>; /* disabled */ + pinctrl-1 = <&tsif0_signals_active>; /* tsif0-mode1 */ + pinctrl-2 = <&tsif0_signals_active + &tsif0_sync_active>; /* tsif0-mode2 */ + pinctrl-3 = <&tsif1_signals_active>; /* tsif1-mode1 */ + pinctrl-4 = <&tsif1_signals_active + &tsif1_sync_active>; /* tsif1-mode2 */ + pinctrl-5 = <&tsif0_signals_active + &tsif1_signals_active>; /* dual-tsif-mode1 */ + pinctrl-6 = <&tsif0_signals_active + &tsif0_sync_active + &tsif1_signals_active + &tsif1_sync_active>; /* dual-tsif-mode2 */ + }; + + wil6210: qcom,wil6210 { + compatible = "qcom,wil6210"; + qcom,pcie-parent = <&pcie0>; + qcom,wigig-en = <&tlmm 80 0>; + qcom,msm-bus,name = "wil6210"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <45 512 0 0>, + <45 512 600000 800000>; /* ~4.6Gbps (MCS12) */ + qcom,use-ext-supply; + vdd-supply= <&pm8998_s7>; + vddio-supply= <&pm8998_s5>; + qcom,use-ext-clocks; + clocks = <&clock_gcc clk_rf_clk3>, + <&clock_gcc clk_rf_clk3_pin>; + clock-names = "rf_clk3_clk", "rf_clk3_pin_clk"; + qcom,smmu-support; + status = "disabled"; + }; + + qcom,qsee_ipc_irq_bridge { + compatible = "qcom,qsee-ipc-irq-bridge"; + + qcom,qsee-ipc-irq-spss { + qcom,rx-irq-clr = <0x1d08008 0x4>; + qcom,rx-irq-clr-mask = <0x1>; + qcom,dev-name = "qsee_ipc_irq_spss"; + interrupts = <0 349 4>; + label = "spss"; + }; + }; +}; + +&clock_cpu { + lmh_dcvs0: qcom,limits-dcvs@0 { + compatible = "qcom,msm-hw-limits"; + interrupts = ; + }; + + lmh_dcvs1: qcom,limits-dcvs@1 { + compatible = "qcom,msm-hw-limits"; + interrupts = ; + }; +}; + +&gdsc_usb30 { + status = "ok"; +}; + +&gdsc_pcie_0 { + status = "ok"; +}; + +&gdsc_ufs { + status = "ok"; +}; + +&gdsc_bimc_smmu { + clock-names = "bus_clk"; + clocks = <&clock_mmss clk_mmss_bimc_smmu_axi_clk>; + proxy-supply = <&gdsc_bimc_smmu>; + qcom,proxy-consumer-enable; + status = "ok"; +}; + +&gdsc_hlos1_vote_lpass_adsp { + status = "ok"; +}; + +&gdsc_hlos1_vote_lpass_core { + status = "ok"; +}; + +&gdsc_venus { + status = "ok"; +}; + +&gdsc_venus_core0 { + status = "ok"; + qcom,support-hw-trigger; +}; + +&gdsc_venus_core1 { + status = "ok"; + qcom,support-hw-trigger; +}; + +&gdsc_camss_top { + status = "ok"; +}; + +&gdsc_vfe0 { + parent-supply = <&gdsc_camss_top>; + status = "ok"; +}; + +&gdsc_vfe1 { + parent-supply = <&gdsc_camss_top>; + status = "ok"; +}; + +&gdsc_cpp { + parent-supply = <&gdsc_camss_top>; + status = "ok"; +}; + +&gdsc_mdss { + proxy-supply = <&gdsc_mdss>; + qcom,proxy-consumer-enable; + status = "ok"; +}; + +&gdsc_gpu_gx { + clock-names = "core_root_clk"; + clocks = <&clock_gfx clk_gfx3d_clk_src>; + qcom,force-enable-root-clk; + parent-supply = <&gfx_vreg>; + status = "ok"; +}; + +&gdsc_gpu_cx { + status = "ok"; +}; + +#include "msm-pm8998.dtsi" +#include "msm-pmi8998.dtsi" +#include "msm-pm8005.dtsi" +#include "msm-pm8998-rpm-regulator.dtsi" +#include "msm8998-regulator.dtsi" + +#include "msm8998-pm.dtsi" +#include "msm-arm-smmu-8998.dtsi" +#include "msm-arm-smmu-impl-defs-8998.dtsi" +#include "msm8998-ion.dtsi" +#include "msm8998-camera.dtsi" +#include "msm8998-vidc.dtsi" +#include "msm8998-coresight.dtsi" +#include "msm8998-bus.dtsi" +#include "msm8998-gpu.dtsi" +#include "msm8998-pinctrl.dtsi" +#include "msm8998-mdss.dtsi" +#include "msm8998-mdss-pll.dtsi" +#include "msm8998-blsp.dtsi" +#include "msm-smb138x.dtsi" + +/* GPU overrides */ +&msm_gpu { + qcom,initial-pwrlevel = <0>; + + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <332000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <8>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <251000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <171000000>; + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <4>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <27000000>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + +}; diff --git a/arch/arm/boot/dts/qcom/msm8998-v2-interposer-msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msm8998-v2-interposer-msmfalcon.dtsi deleted file mode 100644 index dc548f8f499b..000000000000 --- a/arch/arm/boot/dts/qcom/msm8998-v2-interposer-msmfalcon.dtsi +++ /dev/null @@ -1,851 +0,0 @@ -/* Copyright (c) 2016 The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * As a general rule, only version-specific property overrides should be placed - * inside this file. Common device definitions should be placed inside the - * msm8998.dtsi file. - */ - -#include "msm8998-interposer-msmfalcon.dtsi" -#include "msm8998-v2-camera.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM8998 v2"; - qcom,msm-id = <292 0x20000>; -}; - -&clock_cpu { - compatible = "qcom,cpu-clock-osm-msm8998-v2"; - reg = <0x179c0000 0x4000>, - <0x17916000 0x1000>, - <0x17816000 0x1000>, - <0x179d1000 0x1000>, - <0x17914800 0x800>, - <0x17814800 0x800>, - <0x00784130 0x8>, - <0x1791101c 0x8>; - reg-names = "osm", "pwrcl_pll", "perfcl_pll", - "apcs_common", "pwrcl_acd", "perfcl_acd", - "perfcl_efuse", "debug"; - - qcom,acdtd-val = <0x00009611 0x00009611>; - qcom,acdcr-val = <0x002b5ffd 0x002b5ffd>; - qcom,acdsscr-val = <0x00000501 0x00000501>; - qcom,acdextint0-val = <0x2cf9ae8 0x2cf9ae8>; - qcom,acdextint1-val = <0x2cf9afc 0x2cf9afc>; - qcom,acdautoxfer-val = <0x00000015 0x00000015>; - - /delete-property/ qcom,llm-sw-overr; - qcom,pwrcl-speedbin0-v0 = - < 300000000 0x0004000f 0x01200020 0x1 1 >, - < 364800000 0x05040013 0x01200020 0x1 2 >, - < 441600000 0x05040017 0x02200020 0x1 3 >, - < 518400000 0x0504001b 0x02200020 0x1 4 >, - < 595200000 0x0504001f 0x02200020 0x1 5 >, - < 672000000 0x05040023 0x03200020 0x1 6 >, - < 748800000 0x05040027 0x03200020 0x1 7 >, - < 825600000 0x0404002b 0x03220022 0x1 8 >, - < 883200000 0x0404002e 0x04250025 0x1 9 >, - < 960000000 0x04040032 0x04280028 0x1 10 >, - < 1036800000 0x04040036 0x042b002b 0x1 11 >, - < 1094400000 0x04040039 0x052e002e 0x2 12 >, - < 1171200000 0x0404003d 0x05310031 0x2 13 >, - < 1248000000 0x04040041 0x05340034 0x2 14 >, - < 1324800000 0x04040045 0x06370037 0x2 15 >, - < 1401600000 0x04040049 0x063a003a 0x2 16 >, - < 1478400000 0x0404004d 0x073e003e 0x2 17 >, - < 1555200000 0x04040051 0x07410041 0x2 18 >, - < 1670400000 0x04040057 0x08460046 0x2 19 >, - < 1747200000 0x0404005b 0x08490049 0x2 20 >, - < 1824000000 0x0404005f 0x084c004c 0x3 21 >, - < 1900800000 0x04040063 0x094f004f 0x3 22 >; - - qcom,perfcl-speedbin0-v0 = - < 300000000 0x0004000f 0x01200020 0x1 1 >, - < 345600000 0x05040012 0x01200020 0x1 2 >, - < 422400000 0x05040016 0x02200020 0x1 3 >, - < 499200000 0x0504001a 0x02200020 0x1 4 >, - < 576000000 0x0504001e 0x02200020 0x1 5 >, - < 652800000 0x05040022 0x03200020 0x1 6 >, - < 729600000 0x05040026 0x03200020 0x1 7 >, - < 806400000 0x0504002a 0x03220022 0x1 8 >, - < 902400000 0x0404002f 0x04260026 0x1 9 >, - < 979200000 0x04040033 0x04290029 0x1 10 >, - < 1056000000 0x04040037 0x052c002c 0x1 11 >, - < 1132800000 0x0404003b 0x052f002f 0x1 12 >, - < 1190400000 0x0404003e 0x05320032 0x2 13 >, - < 1267200000 0x04040042 0x06350035 0x2 14 >, - < 1344000000 0x04040046 0x06380038 0x2 15 >, - < 1420800000 0x0404004a 0x063b003b 0x2 16 >, - < 1497600000 0x0404004e 0x073e003e 0x2 17 >, - < 1574400000 0x04040052 0x07420042 0x2 18 >, - < 1651200000 0x04040056 0x07450045 0x2 19 >, - < 1728000000 0x0404005a 0x08480048 0x2 20 >, - < 1804800000 0x0404005e 0x084b004b 0x2 21 >, - < 1881600000 0x04040062 0x094e004e 0x2 22 >, - < 1958400000 0x04040066 0x09520052 0x2 23 >, - < 2035200000 0x0404006a 0x09550055 0x3 24 >, - < 2112000000 0x0404006e 0x0a580058 0x3 25 >, - < 2188800000 0x04040072 0x0a5b005b 0x3 26 >, - < 2265600000 0x04040076 0x0a5e005e 0x3 27 >, - < 2342400000 0x0404007a 0x0a620062 0x3 28 >, - < 2419200000 0x0404007e 0x0a650065 0x3 29 >, - < 2496000000 0x04040082 0x0a680068 0x3 30 >; - - qcom,perfcl-speedbin1-v0 = - < 300000000 0x0004000f 0x01200020 0x1 1 >, - < 345600000 0x05040012 0x01200020 0x1 2 >, - < 422400000 0x05040016 0x02200020 0x1 3 >, - < 499200000 0x0504001a 0x02200020 0x1 4 >, - < 576000000 0x0504001e 0x02200020 0x1 5 >, - < 652800000 0x05040022 0x03200020 0x1 6 >, - < 729600000 0x05040026 0x03200020 0x1 7 >, - < 806400000 0x0504002a 0x03220022 0x1 8 >, - < 902400000 0x0404002f 0x04260026 0x1 9 >, - < 979200000 0x04040033 0x04290029 0x1 10 >, - < 1056000000 0x04040037 0x052c002c 0x1 11 >, - < 1132800000 0x0404003b 0x052f002f 0x1 12 >, - < 1190400000 0x0404003e 0x05320032 0x2 13 >, - < 1267200000 0x04040042 0x06350035 0x2 14 >, - < 1344000000 0x04040046 0x06380038 0x2 15 >, - < 1420800000 0x0404004a 0x063b003b 0x2 16 >, - < 1497600000 0x0404004e 0x073e003e 0x2 17 >, - < 1574400000 0x04040052 0x07420042 0x2 18 >, - < 1651200000 0x04040056 0x07450045 0x2 19 >, - < 1728000000 0x0404005a 0x08480048 0x2 20 >, - < 1804800000 0x0404005e 0x084b004b 0x2 21 >, - < 1881600000 0x04040062 0x094e004e 0x2 22 >, - < 1958400000 0x04040066 0x09520052 0x2 23 >, - < 2035200000 0x0404006a 0x09550055 0x3 24 >, - < 2112000000 0x0404006e 0x0a580058 0x3 25 >, - < 2208000000 0x04040073 0x0a5c005c 0x3 26 >, - < 2304000000 0x04010078 0x0a5c005c 0x3 26 >; -}; - -&msm_cpufreq { - qcom,cpufreq-table-0 = - < 300000 >, - < 364800 >, - < 441600 >, - < 518400 >, - < 595200 >, - < 672000 >, - < 748800 >, - < 825600 >, - < 883200 >, - < 960000 >, - < 1036800 >, - < 1094400 >, - < 1171200 >, - < 1248000 >, - < 1324800 >, - < 1401600 >, - < 1478400 >, - < 1555200 >, - < 1670400 >, - < 1747200 >, - < 1824000 >, - < 1900800 >; - - qcom,cpufreq-table-4 = - < 300000 >, - < 345600 >, - < 422400 >, - < 499200 >, - < 576000 >, - < 652800 >, - < 729600 >, - < 806400 >, - < 902400 >, - < 979200 >, - < 1056000 >, - < 1132800 >, - < 1190400 >, - < 1267200 >, - < 1344000 >, - < 1420800 >, - < 1497600 >, - < 1574400 >, - < 1651200 >, - < 1728000 >, - < 1804800 >, - < 1881600 >, - < 1958400 >, - < 2035200 >, - < 2112000 >, - < 2188800 >, - < 2265600 >, - < 2342400 >, - < 2419200 >, - < 2496000 >; -}; - -&bwmon { - compatible = "qcom,bimc-bwmon4"; - qcom,hw-timer-hz = <19200000>; -}; - -&devfreq_cpufreq { - mincpubw-cpufreq { - cpu-to-dev-map-0 = - < 1900800 1525 >; - cpu-to-dev-map-4 = - < 2112000 1525 >, - < 2496000 5195 >; - }; -}; - -&clock_gcc { - compatible = "qcom,gcc-8998-v2"; -}; - -&clock_mmss { - compatible = "qcom,mmsscc-8998-v2"; -}; - -&clock_gpu { - compatible = "qcom,gpucc-8998-v2"; -}; - -&clock_gfx { - compatible = "qcom,gfxcc-8998-v2"; - qcom,gfxfreq-speedbin0 = - < 0 0 0 >, - < 180000000 1 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 257000000 2 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 342000000 3 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 414000000 4 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 515000000 5 RPM_SMD_REGULATOR_LEVEL_NOM >, - < 596000000 6 RPM_SMD_REGULATOR_LEVEL_NOM >, - < 670000000 7 RPM_SMD_REGULATOR_LEVEL_TURBO >; - qcom,gfxfreq-mx-speedbin0 = - < 0 0 >, - < 180000000 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 257000000 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 342000000 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 414000000 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 515000000 RPM_SMD_REGULATOR_LEVEL_NOM >, - < 596000000 RPM_SMD_REGULATOR_LEVEL_NOM >, - < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; -}; - -&mdss_mdp { - qcom,vbif-settings = <0x00d0 0x00002020>; - qcom,max-bandwidth-low-kbps = <9400000>; - qcom,max-bandwidth-high-kbps = <9400000>; - qcom,max-bandwidth-per-pipe-kbps = <4700000>; -}; - -&pm8998_s10 { - regulator-min-microvolt = <568000>; - regulator-max-microvolt = <1056000>; -}; - -&pm8998_s13 { - regulator-min-microvolt = <568000>; - regulator-max-microvolt = <1056000>; -}; - -&apc0_cpr { - compatible = "qcom,cprh-msm8998-v2-kbss-regulator"; - qcom,cpr-corner-switch-delay-time = <1042>; - qcom,cpr-aging-ref-voltage = <1056000>; -}; - -&apc0_pwrcl_vreg { - regulator-max-microvolt = <23>; - - qcom,cpr-fuse-combos = <16>; - qcom,cpr-speed-bins = <2>; - qcom,cpr-speed-bin-corners = <22 22>; - qcom,cpr-corners = - /* Speed bin 0 */ - <22 22 22 22 22 22 22 22>, - /* Speed bin 1 */ - <22 22 22 22 22 22 22 22>; - - qcom,cpr-corner-fmax-map = - /* Speed bin 0 */ - <8 11 18 22>, - /* Speed bin 1 */ - <8 11 18 22>; - - qcom,cpr-voltage-ceiling = - /* Speed bin 0 */ - <828000 828000 828000 828000 828000 - 828000 828000 828000 828000 828000 - 828000 900000 900000 900000 900000 - 900000 900000 900000 952000 952000 - 1056000 1056000>, - /* Speed bin 1 */ - <828000 828000 828000 828000 828000 - 828000 828000 828000 828000 828000 - 828000 900000 900000 900000 900000 - 900000 900000 900000 952000 952000 - 1056000 1056000>; - - qcom,cpr-voltage-floor = - /* Speed bin 0 */ - <568000 568000 568000 568000 568000 - 568000 568000 568000 568000 568000 - 568000 632000 632000 632000 632000 - 632000 632000 632000 712000 712000 - 772000 772000>, - /* Speed bin 1 */ - <568000 568000 568000 568000 568000 - 568000 568000 568000 568000 568000 - 568000 632000 632000 632000 632000 - 632000 632000 632000 712000 712000 - 772000 772000>; - - qcom,cpr-floor-to-ceiling-max-range = - /* Speed bin 0 */ - <55000 55000 55000 55000 - 55000 55000 55000 55000 - 55000 55000 55000 65000 - 65000 65000 65000 65000 - 65000 65000 65000 65000 - 65000 65000>, - /* Speed bin 1 */ - <55000 55000 55000 55000 - 55000 55000 55000 55000 - 55000 55000 55000 65000 - 65000 65000 65000 65000 - 65000 65000 65000 65000 - 65000 65000>; - - qcom,corner-frequencies = - /* Speed bin 0 */ - <300000000 364800000 441600000 - 518400000 595200000 672000000 - 748800000 825600000 883200000 - 960000000 1036800000 1094400000 - 1171200000 1248000000 1324800000 - 1401600000 1478400000 1555200000 - 1670400000 1747200000 1824000000 - 1900800000>, - /* Speed bin 1 */ - <300000000 364800000 441600000 - 518400000 595200000 672000000 - 748800000 825600000 883200000 - 960000000 1036800000 1094400000 - 1171200000 1248000000 1324800000 - 1401600000 1478400000 1555200000 - 1670400000 1747200000 1824000000 - 1900800000>; - - qcom,cpr-ro-scaling-factor = - <2595 2794 2577 2762 2471 2674 2199 - 2553 3189 3255 3192 2962 3054 2982 - 2042 2945>, - <2595 2794 2577 2762 2471 2674 2199 - 2553 3189 3255 3192 2962 3054 2982 - 2042 2945>, - <2391 2550 2483 2638 2382 2564 2259 - 2555 2766 3041 2988 2935 2873 2688 - 2013 2784>, - <2066 2153 2300 2434 2220 2386 2288 - 2465 2028 2511 2487 2734 2554 2117 - 1892 2377>; - - qcom,cpr-open-loop-voltage-fuse-adjustment = - /* Speed bin 0 */ - <40000 24000 0 30000>, - <40000 24000 0 30000>, - <40000 24000 0 30000>, - <40000 24000 0 30000>, - <40000 24000 0 30000>, - <40000 24000 0 30000>, - <40000 24000 0 30000>, - <40000 24000 0 30000>, - /* Speed bin 1 */ - <40000 24000 0 30000>, - <40000 24000 0 30000>, - <40000 24000 0 30000>, - <40000 24000 0 30000>, - <40000 24000 0 30000>, - <40000 24000 0 30000>, - <40000 24000 0 30000>, - <40000 24000 0 30000>; - - qcom,cpr-closed-loop-voltage-fuse-adjustment = - /* Speed bin 0 */ - <20000 26000 0 30000>, - <20000 26000 0 30000>, - <20000 26000 0 30000>, - <20000 26000 0 30000>, - <20000 26000 0 30000>, - <20000 26000 0 30000>, - <20000 26000 0 30000>, - <20000 26000 0 30000>, - /* Speed bin 1 */ - <20000 26000 0 30000>, - <20000 26000 0 30000>, - <20000 26000 0 30000>, - <20000 26000 0 30000>, - <20000 26000 0 30000>, - <20000 26000 0 30000>, - <20000 26000 0 30000>, - <20000 26000 0 30000>; - - qcom,allow-voltage-interpolation; - qcom,allow-quotient-interpolation; - qcom,cpr-scaled-open-loop-voltage-as-ceiling; - - qcom,cpr-aging-ref-corner = <22 22>; - qcom,cpr-aging-ro-scaling-factor = <2950>; - qcom,allow-aging-voltage-adjustment = <0>; -}; - -&apc1_cpr { - compatible = "qcom,cprh-msm8998-v2-kbss-regulator"; - qcom,cpr-corner-switch-delay-time = <1042>; - qcom,cpr-aging-ref-voltage = <1056000>; -}; - -&apc1_perfcl_vreg { - regulator-max-microvolt = <31>; - - qcom,cpr-fuse-combos = <16>; - qcom,cpr-speed-bins = <2>; - qcom,cpr-speed-bin-corners = <30 26>; - qcom,cpr-corners = - /* Speed bin 0 */ - <30 30 30 30 30 30 30 30>, - /* Speed bin 1 */ - <26 26 26 26 26 26 26 26>; - - qcom,cpr-corner-fmax-map = - /* Speed bin 0 */ - <8 12 20 30>, - /* Speed bin 1 */ - <8 12 20 26>; - - qcom,cpr-voltage-ceiling = - /* Speed bin 0 */ - <828000 828000 828000 828000 828000 - 828000 828000 828000 828000 828000 - 828000 828000 900000 900000 900000 - 900000 900000 900000 900000 900000 - 952000 952000 952000 1056000 1056000 - 1056000 1056000 1056000 1056000 1056000>, - /* Speed bin 1 */ - <828000 828000 828000 828000 828000 - 828000 828000 828000 828000 828000 - 828000 828000 900000 900000 900000 - 900000 900000 900000 900000 900000 - 952000 952000 952000 1056000 1056000 - 1056000>; - - qcom,cpr-voltage-floor = - /* Speed bin 0 */ - <568000 568000 568000 568000 568000 - 568000 568000 568000 568000 568000 - 568000 568000 632000 632000 632000 - 632000 632000 632000 632000 632000 - 712000 712000 712000 772000 772000 - 772000 772000 772000 772000 772000>, - /* Speed bin 1 */ - <568000 568000 568000 568000 568000 - 568000 568000 568000 568000 568000 - 568000 568000 632000 632000 632000 - 632000 632000 632000 632000 632000 - 712000 712000 712000 772000 772000 - 772000>; - - qcom,cpr-floor-to-ceiling-max-range = - /* Speed bin 0 */ - <55000 55000 55000 55000 - 55000 55000 55000 55000 - 55000 55000 55000 55000 - 65000 65000 65000 65000 - 65000 65000 65000 65000 - 65000 65000 65000 65000 - 65000 65000 65000 65000 - 65000 65000>, - /* Speed bin 1 */ - <55000 55000 55000 55000 - 55000 55000 55000 55000 - 55000 55000 55000 55000 - 65000 65000 65000 65000 - 65000 65000 65000 65000 - 65000 65000 65000 65000 - 65000 65000>; - - qcom,corner-frequencies = - /* Speed bin 0 */ - <300000000 345600000 422400000 - 499200000 576000000 652800000 - 729600000 806400000 902400000 - 979200000 1056000000 1132800000 - 1190400000 1267200000 1344000000 - 1420800000 1497600000 1574400000 - 1651200000 1728000000 1804800000 - 1881600000 1958400000 2035200000 - 2112000000 2188800000 2265600000 - 2342400000 2419200000 2496000000>, - /* Speed bin 1 */ - <300000000 345600000 422400000 - 499200000 576000000 652800000 - 729600000 806400000 902400000 - 979200000 1056000000 1132800000 - 1190400000 1267200000 1344000000 - 1420800000 1497600000 1574400000 - 1651200000 1728000000 1804800000 - 1881600000 1958400000 2035200000 - 2112000000 2208000000>; - - qcom,cpr-ro-scaling-factor = - <2857 3057 2828 2952 2699 2798 2446 - 2631 2629 2578 2244 3344 3289 3137 - 3164 2655>, - <2857 3057 2828 2952 2699 2798 2446 - 2631 2629 2578 2244 3344 3289 3137 - 3164 2655>, - <2603 2755 2676 2777 2573 2685 2465 - 2610 2312 2423 2243 3104 3022 3036 - 2740 2303>, - <1901 2016 2096 2228 2034 2161 2077 - 2188 1565 1870 1925 2235 2205 2413 - 1762 1478>; - - qcom,cpr-open-loop-voltage-fuse-adjustment = - /* Speed bin 0 */ - <8000 0 0 52000>, - <8000 0 0 52000>, - <8000 0 0 52000>, - <8000 0 0 52000>, - <8000 0 0 52000>, - <8000 0 0 52000>, - <8000 0 0 52000>, - <8000 0 0 52000>, - /* Speed bin 1 */ - <8000 0 0 52000>, - <8000 0 0 52000>, - <8000 0 0 52000>, - <8000 0 0 52000>, - <8000 0 0 52000>, - <8000 0 0 52000>, - <8000 0 0 52000>, - <8000 0 0 52000>; - - qcom,cpr-closed-loop-voltage-fuse-adjustment = - /* Speed bin 0 */ - <0 0 0 50000>, - <0 0 0 50000>, - <0 0 0 50000>, - <0 0 0 50000>, - <0 0 0 50000>, - <0 0 0 50000>, - <0 0 0 50000>, - <0 0 0 50000>, - /* Speed bin 1 */ - <0 0 0 50000>, - <0 0 0 50000>, - <0 0 0 50000>, - <0 0 0 50000>, - <0 0 0 50000>, - <0 0 0 50000>, - <0 0 0 50000>, - <0 0 0 50000>; - - qcom,allow-voltage-interpolation; - qcom,allow-quotient-interpolation; - qcom,cpr-scaled-open-loop-voltage-as-ceiling; - - qcom,cpr-aging-ref-corner = <30 26>; - qcom,cpr-aging-ro-scaling-factor = <2950>; - qcom,allow-aging-voltage-adjustment = <0>; -}; - -&pm8005_s1 { - regulator-min-microvolt = <516000>; - regulator-max-microvolt = <1088000>; -}; - -&gfx_cpr { - compatible = "qcom,cpr4-msm8998-v2-mmss-regulator"; - qcom,cpr-aging-ref-voltage = <1024000>; -}; - -&gfx_vreg { - regulator-min-microvolt = <1>; - regulator-max-microvolt = <8>; - - qcom,cpr-fuse-corners = <4>; - qcom,cpr-fuse-combos = <8>; - qcom,cpr-corners = <8>; - - qcom,cpr-corner-fmax-map = <1 3 5 8>; - - qcom,cpr-voltage-ceiling = - <656000 716000 772000 880000 908000 948000 1016000 1088000>, - <660000 724000 772000 832000 916000 968000 1024000 1024000>, - <660000 724000 772000 832000 916000 968000 1024000 1024000>, - <660000 724000 772000 832000 916000 968000 1024000 1024000>, - <660000 724000 772000 832000 916000 968000 1024000 1024000>, - <660000 724000 772000 832000 916000 968000 1024000 1024000>, - <660000 724000 772000 832000 916000 968000 1024000 1024000>, - <660000 724000 772000 832000 916000 968000 1024000 1024000>; - - qcom,cpr-voltage-floor = - <516000 516000 532000 584000 632000 672000 712000 756000>; - - qcom,mem-acc-voltage = <1 1 1 2 2 2 2 2>; - - qcom,corner-frequencies = - <180000000 257000000 342000000 414000000 - 515000000 596000000 670000000 710000000>; - - qcom,cpr-target-quotients = - < 0 0 0 0 331 357 0 0 - 0 0 0 0 0 0 115 0>, - < 0 0 0 0 467 500 0 0 - 0 0 0 0 0 0 199 0>, - < 0 0 0 0 628 665 0 0 - 0 0 0 0 0 0 290 0>, - < 0 0 0 0 762 805 0 0 - 0 0 0 0 0 0 397 0>, - < 0 0 0 0 964 1013 0 0 - 0 0 1143 0 1138 1055 0 0>, - < 0 0 0 0 0 0 0 0 - 0 0 1306 0 1289 1168 0 0>, - < 0 0 0 0 0 0 0 0 - 0 0 1468 0 1429 1256 0 0>, - < 0 0 0 0 0 0 0 0 - 0 0 1627 0 1578 1353 0 0>; - - qcom,cpr-ro-scaling-factor = - < 0 0 0 0 2377 2571 0 0 - 0 0 2168 0 2209 1849 1997 0>, - < 0 0 0 0 2377 2571 0 0 - 0 0 2168 0 2209 1849 1997 0>, - < 0 0 0 0 2377 2571 0 0 - 0 0 2168 0 2209 1849 1997 0>, - < 0 0 0 0 2377 2571 0 0 - 0 0 2168 0 2209 1849 1997 0>, - < 0 0 0 0 2377 2571 0 0 - 0 0 2168 0 2209 1849 1997 0>, - < 0 0 0 0 2377 2571 0 0 - 0 0 2168 0 2209 1849 1997 0>, - < 0 0 0 0 2377 2571 0 0 - 0 0 2168 0 2209 1849 1997 0>, - < 0 0 0 0 2377 2571 0 0 - 0 0 2168 0 2209 1849 1997 0>; - - qcom,cpr-open-loop-voltage-fuse-adjustment = - < 100000 0 0 0>, - < 100000 0 0 0>, - < 85000 (-15000) (-15000) (-15000)>, - < 85000 (-15000) (-15000) (-15000)>, - < 85000 (-15000) (-15000) (-15000)>, - < 85000 (-15000) (-15000) (-15000)>, - < 85000 (-15000) (-15000) (-15000)>, - < 85000 (-15000) (-15000) (-15000)>; - - qcom,cpr-closed-loop-voltage-adjustment = - < 96000 18000 4000 0 - 0 13000 9000 0>, - < 96000 18000 4000 0 - 0 13000 9000 0>, - < 81000 3000 (-11000) (-15000) - (-15000) (-2000) (-6000) (-15000)>, - < 81000 3000 (-11000) (-15000) - (-15000) (-2000) (-6000) (-15000)>, - < 81000 3000 (-11000) (-15000) - (-15000) (-2000) (-6000) (-15000)>, - < 81000 3000 (-11000) (-15000) - (-15000) (-2000) (-6000) (-15000)>, - < 81000 3000 (-11000) (-15000) - (-15000) (-2000) (-6000) (-15000)>, - < 81000 3000 (-11000) (-15000) - (-15000) (-2000) (-6000) (-15000)>; - - qcom,cpr-floor-to-ceiling-max-range = - <50000 50000 50000 50000 50000 50000 70000 70000>; - - qcom,cpr-fused-closed-loop-voltage-adjustment-map = - <0 0 1 2 3 0 0 4>; - - qcom,allow-voltage-interpolation; - qcom,cpr-scaled-open-loop-voltage-as-ceiling; - - qcom,cpr-aging-max-voltage-adjustment = <15000>; - qcom,cpr-aging-ref-corner = <8>; - qcom,cpr-aging-ro-scaling-factor = <2950>; - qcom,allow-aging-voltage-adjustment = <0 0 1 1 1 1 1 1>; -}; - -&qusb_phy0 { - reg = <0x0c012000 0x2a8>, - <0x01fcb24c 0x4>, - <0x00784238 0x4>; - reg-names = "qusb_phy_base", - "tcsr_clamp_dig_n_1p8", - "efuse_addr"; - qcom,efuse-bit-pos = <16>; - qcom,efuse-num-bits = <4>; - qcom,qusb-phy-init-seq = - /* */ - <0x13 0x04 /* analog_controls_two */ - 0x7c 0x18c /* pll_clock_inverter */ - 0x80 0x2c /* pll_cmode */ - 0x0a 0x184 /* pll_lock_delay */ - 0xa5 0x23c /* tune1 */ - 0x09 0x240 /* tune2 */ - 0x19 0xb4>; /* digital_timers_two */ -}; - -&msm_vidc { - qcom,load-freq-tbl = - /* Encoders */ - <1105920 533000000 0x55555555>, /* 4kx2304@30 */ /*TURBO*/ - <1036800 444000000 0x55555555>, /* 720p@240, 1080p@120,1440p@60, - * UHD@30 */ /*NOMINAL*/ - < 829440 355200000 0x55555555>, /* UHD/4096x2160@30 SVSL1 */ - < 489600 269330000 0x55555555>, /* 1080p@60, 720p@120 SVS */ - < 345600 200000000 0x55555555>, /* 2560x1440@24, 1080p@30 */ - /* SVS2 */ - - /* Decoders */ - <2211840 533000000 0xffffffff>, /* 4kx2304@60, 1080p@240 */ - /* TURBO */ - <1728000 444000000 0xffffffff>, /* 2560x1440@120 */ - /* NOMINAL */ - <1675472 355200000 0xffffffff>, /* 4kx2304@44 */ /*SVSL1*/ - <1105920 269330000 0xffffffff>, /* UHD/4k2304@30, 1080p@120 */ - /* SVS */ - < 829440 200000000 0xffffffff>; /* 720p@120, 1080p@60 */ - /* SVS2 */ - - qcom,imem-ab-tbl = - <200000000 1560000>,/* imem @ svs2 freq 75 Mhz */ - <269330000 3570000>,/* imem @ svs freq 171 Mhz */ - <355200000 3570000>,/* imem @ svs freq 171 Mhz */ - <444000000 6750000>,/* imem @ nom freq 323 Mhz */ - <533000000 8490000>;/* imem @ turbo freq 406 Mhz */ - - qcom,dcvs-tbl = /* minLoad LoadLow LoadHigh CodecCheck */ - /* Decode */ - /* Load > Nominal, Nominal <-> Turbo Eg.3840x2160@60 */ - <1728000 1728000 2211840 0x3f00000c>, - /* Encoder */ - /* Load > Nominal, Nominal <-> Turbo Eg. 4kx2304@30 */ - <1036800 1036800 1105920 0x04000004>, - /* Load > SVSL1, SVSL1<-> Nominal Eg. 3840x2160@30 */ - < 829440 829440 1036800 0x04000004>, - /* Load > SVS , SVS <-> SVSL1 Eg. 4kx2304@24 */ - < 489600 489600 829440 0x04000004>; - - qcom,dcvs-limit = /* Min Frame size, Min MBs/sec */ - <32400 30>, /* Encoder 3840x2160@30 */ - <32400 60>; /* Decoder 3840x2160@60 */ - -}; - -&soc { - /* Gold L2 SAW */ - qcom,spm@178120000 { - qcom,saw2-avs-limit = <0x4200420>; - }; - - /* Silver L2 SAW */ - qcom,spm@179120000 { - qcom,saw2-avs-limit = <0x4200420>; - }; -}; - -/* GPU overrides */ -&msm_gpu { - /* Updated chip ID */ - qcom,chipid = <0x05040001>; - qcom,initial-pwrlevel = <0>; - - qcom,gpu-pwrlevels { - #address-cells = <1>; - #size-cells = <0>; - - compatible = "qcom,gpu-pwrlevels"; - - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <342000000>; - qcom,bus-freq = <8>; - qcom,bus-min = <5>; - qcom,bus-max = <9>; - }; - - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <257000000>; - qcom,bus-freq = <5>; - qcom,bus-min = <3>; - qcom,bus-max = <8>; - }; - - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <180000000>; - qcom,bus-freq = <3>; - qcom,bus-min = <1>; - qcom,bus-max = <5>; - }; - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <27000000>; - qcom,bus-freq = <0>; - qcom,bus-min = <0>; - qcom,bus-max = <0>; - }; - }; -}; - -&spss_utils { - qcom,spss-test-firmware-name = "spss2t"; /* 8 chars max */ - qcom,spss-prod-firmware-name = "spss2p"; /* 8 chars max */ -}; - -&ufs1 { - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "core_clk_ice", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; - clocks = - <&clock_gcc clk_gcc_ufs_axi_hw_ctl_clk>, - <&clock_gcc clk_gcc_aggre1_ufs_axi_clk>, - <&clock_gcc clk_gcc_ufs_ahb_clk>, - <&clock_gcc clk_gcc_ufs_unipro_core_hw_ctl_clk>, - <&clock_gcc clk_gcc_ufs_ice_core_hw_ctl_clk>, - <&clock_gcc clk_ln_bb_clk1>, - <&clock_gcc clk_gcc_ufs_tx_symbol_0_clk>, - <&clock_gcc clk_gcc_ufs_rx_symbol_0_clk>, - <&clock_gcc clk_gcc_ufs_rx_symbol_1_clk>; - freq-table-hz = - <50000000 200000000>, - <0 0>, - <0 0>, - <37500000 150000000>, - <75000000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>; - - lanes-per-direction = <2>; -}; diff --git a/arch/arm/boot/dts/qcom/msm8998-v2-interposer-sdm660.dtsi b/arch/arm/boot/dts/qcom/msm8998-v2-interposer-sdm660.dtsi new file mode 100644 index 000000000000..4edcd964f0b3 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8998-v2-interposer-sdm660.dtsi @@ -0,0 +1,851 @@ +/* Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * As a general rule, only version-specific property overrides should be placed + * inside this file. Common device definitions should be placed inside the + * msm8998.dtsi file. + */ + +#include "msm8998-interposer-sdm660.dtsi" +#include "msm8998-v2-camera.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM8998 v2"; + qcom,msm-id = <292 0x20000>; +}; + +&clock_cpu { + compatible = "qcom,cpu-clock-osm-msm8998-v2"; + reg = <0x179c0000 0x4000>, + <0x17916000 0x1000>, + <0x17816000 0x1000>, + <0x179d1000 0x1000>, + <0x17914800 0x800>, + <0x17814800 0x800>, + <0x00784130 0x8>, + <0x1791101c 0x8>; + reg-names = "osm", "pwrcl_pll", "perfcl_pll", + "apcs_common", "pwrcl_acd", "perfcl_acd", + "perfcl_efuse", "debug"; + + qcom,acdtd-val = <0x00009611 0x00009611>; + qcom,acdcr-val = <0x002b5ffd 0x002b5ffd>; + qcom,acdsscr-val = <0x00000501 0x00000501>; + qcom,acdextint0-val = <0x2cf9ae8 0x2cf9ae8>; + qcom,acdextint1-val = <0x2cf9afc 0x2cf9afc>; + qcom,acdautoxfer-val = <0x00000015 0x00000015>; + + /delete-property/ qcom,llm-sw-overr; + qcom,pwrcl-speedbin0-v0 = + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 364800000 0x05040013 0x01200020 0x1 2 >, + < 441600000 0x05040017 0x02200020 0x1 3 >, + < 518400000 0x0504001b 0x02200020 0x1 4 >, + < 595200000 0x0504001f 0x02200020 0x1 5 >, + < 672000000 0x05040023 0x03200020 0x1 6 >, + < 748800000 0x05040027 0x03200020 0x1 7 >, + < 825600000 0x0404002b 0x03220022 0x1 8 >, + < 883200000 0x0404002e 0x04250025 0x1 9 >, + < 960000000 0x04040032 0x04280028 0x1 10 >, + < 1036800000 0x04040036 0x042b002b 0x1 11 >, + < 1094400000 0x04040039 0x052e002e 0x2 12 >, + < 1171200000 0x0404003d 0x05310031 0x2 13 >, + < 1248000000 0x04040041 0x05340034 0x2 14 >, + < 1324800000 0x04040045 0x06370037 0x2 15 >, + < 1401600000 0x04040049 0x063a003a 0x2 16 >, + < 1478400000 0x0404004d 0x073e003e 0x2 17 >, + < 1555200000 0x04040051 0x07410041 0x2 18 >, + < 1670400000 0x04040057 0x08460046 0x2 19 >, + < 1747200000 0x0404005b 0x08490049 0x2 20 >, + < 1824000000 0x0404005f 0x084c004c 0x3 21 >, + < 1900800000 0x04040063 0x094f004f 0x3 22 >; + + qcom,perfcl-speedbin0-v0 = + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 345600000 0x05040012 0x01200020 0x1 2 >, + < 422400000 0x05040016 0x02200020 0x1 3 >, + < 499200000 0x0504001a 0x02200020 0x1 4 >, + < 576000000 0x0504001e 0x02200020 0x1 5 >, + < 652800000 0x05040022 0x03200020 0x1 6 >, + < 729600000 0x05040026 0x03200020 0x1 7 >, + < 806400000 0x0504002a 0x03220022 0x1 8 >, + < 902400000 0x0404002f 0x04260026 0x1 9 >, + < 979200000 0x04040033 0x04290029 0x1 10 >, + < 1056000000 0x04040037 0x052c002c 0x1 11 >, + < 1132800000 0x0404003b 0x052f002f 0x1 12 >, + < 1190400000 0x0404003e 0x05320032 0x2 13 >, + < 1267200000 0x04040042 0x06350035 0x2 14 >, + < 1344000000 0x04040046 0x06380038 0x2 15 >, + < 1420800000 0x0404004a 0x063b003b 0x2 16 >, + < 1497600000 0x0404004e 0x073e003e 0x2 17 >, + < 1574400000 0x04040052 0x07420042 0x2 18 >, + < 1651200000 0x04040056 0x07450045 0x2 19 >, + < 1728000000 0x0404005a 0x08480048 0x2 20 >, + < 1804800000 0x0404005e 0x084b004b 0x2 21 >, + < 1881600000 0x04040062 0x094e004e 0x2 22 >, + < 1958400000 0x04040066 0x09520052 0x2 23 >, + < 2035200000 0x0404006a 0x09550055 0x3 24 >, + < 2112000000 0x0404006e 0x0a580058 0x3 25 >, + < 2188800000 0x04040072 0x0a5b005b 0x3 26 >, + < 2265600000 0x04040076 0x0a5e005e 0x3 27 >, + < 2342400000 0x0404007a 0x0a620062 0x3 28 >, + < 2419200000 0x0404007e 0x0a650065 0x3 29 >, + < 2496000000 0x04040082 0x0a680068 0x3 30 >; + + qcom,perfcl-speedbin1-v0 = + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 345600000 0x05040012 0x01200020 0x1 2 >, + < 422400000 0x05040016 0x02200020 0x1 3 >, + < 499200000 0x0504001a 0x02200020 0x1 4 >, + < 576000000 0x0504001e 0x02200020 0x1 5 >, + < 652800000 0x05040022 0x03200020 0x1 6 >, + < 729600000 0x05040026 0x03200020 0x1 7 >, + < 806400000 0x0504002a 0x03220022 0x1 8 >, + < 902400000 0x0404002f 0x04260026 0x1 9 >, + < 979200000 0x04040033 0x04290029 0x1 10 >, + < 1056000000 0x04040037 0x052c002c 0x1 11 >, + < 1132800000 0x0404003b 0x052f002f 0x1 12 >, + < 1190400000 0x0404003e 0x05320032 0x2 13 >, + < 1267200000 0x04040042 0x06350035 0x2 14 >, + < 1344000000 0x04040046 0x06380038 0x2 15 >, + < 1420800000 0x0404004a 0x063b003b 0x2 16 >, + < 1497600000 0x0404004e 0x073e003e 0x2 17 >, + < 1574400000 0x04040052 0x07420042 0x2 18 >, + < 1651200000 0x04040056 0x07450045 0x2 19 >, + < 1728000000 0x0404005a 0x08480048 0x2 20 >, + < 1804800000 0x0404005e 0x084b004b 0x2 21 >, + < 1881600000 0x04040062 0x094e004e 0x2 22 >, + < 1958400000 0x04040066 0x09520052 0x2 23 >, + < 2035200000 0x0404006a 0x09550055 0x3 24 >, + < 2112000000 0x0404006e 0x0a580058 0x3 25 >, + < 2208000000 0x04040073 0x0a5c005c 0x3 26 >, + < 2304000000 0x04010078 0x0a5c005c 0x3 26 >; +}; + +&msm_cpufreq { + qcom,cpufreq-table-0 = + < 300000 >, + < 364800 >, + < 441600 >, + < 518400 >, + < 595200 >, + < 672000 >, + < 748800 >, + < 825600 >, + < 883200 >, + < 960000 >, + < 1036800 >, + < 1094400 >, + < 1171200 >, + < 1248000 >, + < 1324800 >, + < 1401600 >, + < 1478400 >, + < 1555200 >, + < 1670400 >, + < 1747200 >, + < 1824000 >, + < 1900800 >; + + qcom,cpufreq-table-4 = + < 300000 >, + < 345600 >, + < 422400 >, + < 499200 >, + < 576000 >, + < 652800 >, + < 729600 >, + < 806400 >, + < 902400 >, + < 979200 >, + < 1056000 >, + < 1132800 >, + < 1190400 >, + < 1267200 >, + < 1344000 >, + < 1420800 >, + < 1497600 >, + < 1574400 >, + < 1651200 >, + < 1728000 >, + < 1804800 >, + < 1881600 >, + < 1958400 >, + < 2035200 >, + < 2112000 >, + < 2188800 >, + < 2265600 >, + < 2342400 >, + < 2419200 >, + < 2496000 >; +}; + +&bwmon { + compatible = "qcom,bimc-bwmon4"; + qcom,hw-timer-hz = <19200000>; +}; + +&devfreq_cpufreq { + mincpubw-cpufreq { + cpu-to-dev-map-0 = + < 1900800 1525 >; + cpu-to-dev-map-4 = + < 2112000 1525 >, + < 2496000 5195 >; + }; +}; + +&clock_gcc { + compatible = "qcom,gcc-8998-v2"; +}; + +&clock_mmss { + compatible = "qcom,mmsscc-8998-v2"; +}; + +&clock_gpu { + compatible = "qcom,gpucc-8998-v2"; +}; + +&clock_gfx { + compatible = "qcom,gfxcc-8998-v2"; + qcom,gfxfreq-speedbin0 = + < 0 0 0 >, + < 180000000 1 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 257000000 2 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 342000000 3 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 414000000 4 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 515000000 5 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 596000000 6 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 670000000 7 RPM_SMD_REGULATOR_LEVEL_TURBO >; + qcom,gfxfreq-mx-speedbin0 = + < 0 0 >, + < 180000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 257000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 342000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 414000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 515000000 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 596000000 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; +}; + +&mdss_mdp { + qcom,vbif-settings = <0x00d0 0x00002020>; + qcom,max-bandwidth-low-kbps = <9400000>; + qcom,max-bandwidth-high-kbps = <9400000>; + qcom,max-bandwidth-per-pipe-kbps = <4700000>; +}; + +&pm8998_s10 { + regulator-min-microvolt = <568000>; + regulator-max-microvolt = <1056000>; +}; + +&pm8998_s13 { + regulator-min-microvolt = <568000>; + regulator-max-microvolt = <1056000>; +}; + +&apc0_cpr { + compatible = "qcom,cprh-msm8998-v2-kbss-regulator"; + qcom,cpr-corner-switch-delay-time = <1042>; + qcom,cpr-aging-ref-voltage = <1056000>; +}; + +&apc0_pwrcl_vreg { + regulator-max-microvolt = <23>; + + qcom,cpr-fuse-combos = <16>; + qcom,cpr-speed-bins = <2>; + qcom,cpr-speed-bin-corners = <22 22>; + qcom,cpr-corners = + /* Speed bin 0 */ + <22 22 22 22 22 22 22 22>, + /* Speed bin 1 */ + <22 22 22 22 22 22 22 22>; + + qcom,cpr-corner-fmax-map = + /* Speed bin 0 */ + <8 11 18 22>, + /* Speed bin 1 */ + <8 11 18 22>; + + qcom,cpr-voltage-ceiling = + /* Speed bin 0 */ + <828000 828000 828000 828000 828000 + 828000 828000 828000 828000 828000 + 828000 900000 900000 900000 900000 + 900000 900000 900000 952000 952000 + 1056000 1056000>, + /* Speed bin 1 */ + <828000 828000 828000 828000 828000 + 828000 828000 828000 828000 828000 + 828000 900000 900000 900000 900000 + 900000 900000 900000 952000 952000 + 1056000 1056000>; + + qcom,cpr-voltage-floor = + /* Speed bin 0 */ + <568000 568000 568000 568000 568000 + 568000 568000 568000 568000 568000 + 568000 632000 632000 632000 632000 + 632000 632000 632000 712000 712000 + 772000 772000>, + /* Speed bin 1 */ + <568000 568000 568000 568000 568000 + 568000 568000 568000 568000 568000 + 568000 632000 632000 632000 632000 + 632000 632000 632000 712000 712000 + 772000 772000>; + + qcom,cpr-floor-to-ceiling-max-range = + /* Speed bin 0 */ + <55000 55000 55000 55000 + 55000 55000 55000 55000 + 55000 55000 55000 65000 + 65000 65000 65000 65000 + 65000 65000 65000 65000 + 65000 65000>, + /* Speed bin 1 */ + <55000 55000 55000 55000 + 55000 55000 55000 55000 + 55000 55000 55000 65000 + 65000 65000 65000 65000 + 65000 65000 65000 65000 + 65000 65000>; + + qcom,corner-frequencies = + /* Speed bin 0 */ + <300000000 364800000 441600000 + 518400000 595200000 672000000 + 748800000 825600000 883200000 + 960000000 1036800000 1094400000 + 1171200000 1248000000 1324800000 + 1401600000 1478400000 1555200000 + 1670400000 1747200000 1824000000 + 1900800000>, + /* Speed bin 1 */ + <300000000 364800000 441600000 + 518400000 595200000 672000000 + 748800000 825600000 883200000 + 960000000 1036800000 1094400000 + 1171200000 1248000000 1324800000 + 1401600000 1478400000 1555200000 + 1670400000 1747200000 1824000000 + 1900800000>; + + qcom,cpr-ro-scaling-factor = + <2595 2794 2577 2762 2471 2674 2199 + 2553 3189 3255 3192 2962 3054 2982 + 2042 2945>, + <2595 2794 2577 2762 2471 2674 2199 + 2553 3189 3255 3192 2962 3054 2982 + 2042 2945>, + <2391 2550 2483 2638 2382 2564 2259 + 2555 2766 3041 2988 2935 2873 2688 + 2013 2784>, + <2066 2153 2300 2434 2220 2386 2288 + 2465 2028 2511 2487 2734 2554 2117 + 1892 2377>; + + qcom,cpr-open-loop-voltage-fuse-adjustment = + /* Speed bin 0 */ + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + /* Speed bin 1 */ + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>; + + qcom,cpr-closed-loop-voltage-fuse-adjustment = + /* Speed bin 0 */ + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + /* Speed bin 1 */ + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>; + + qcom,allow-voltage-interpolation; + qcom,allow-quotient-interpolation; + qcom,cpr-scaled-open-loop-voltage-as-ceiling; + + qcom,cpr-aging-ref-corner = <22 22>; + qcom,cpr-aging-ro-scaling-factor = <2950>; + qcom,allow-aging-voltage-adjustment = <0>; +}; + +&apc1_cpr { + compatible = "qcom,cprh-msm8998-v2-kbss-regulator"; + qcom,cpr-corner-switch-delay-time = <1042>; + qcom,cpr-aging-ref-voltage = <1056000>; +}; + +&apc1_perfcl_vreg { + regulator-max-microvolt = <31>; + + qcom,cpr-fuse-combos = <16>; + qcom,cpr-speed-bins = <2>; + qcom,cpr-speed-bin-corners = <30 26>; + qcom,cpr-corners = + /* Speed bin 0 */ + <30 30 30 30 30 30 30 30>, + /* Speed bin 1 */ + <26 26 26 26 26 26 26 26>; + + qcom,cpr-corner-fmax-map = + /* Speed bin 0 */ + <8 12 20 30>, + /* Speed bin 1 */ + <8 12 20 26>; + + qcom,cpr-voltage-ceiling = + /* Speed bin 0 */ + <828000 828000 828000 828000 828000 + 828000 828000 828000 828000 828000 + 828000 828000 900000 900000 900000 + 900000 900000 900000 900000 900000 + 952000 952000 952000 1056000 1056000 + 1056000 1056000 1056000 1056000 1056000>, + /* Speed bin 1 */ + <828000 828000 828000 828000 828000 + 828000 828000 828000 828000 828000 + 828000 828000 900000 900000 900000 + 900000 900000 900000 900000 900000 + 952000 952000 952000 1056000 1056000 + 1056000>; + + qcom,cpr-voltage-floor = + /* Speed bin 0 */ + <568000 568000 568000 568000 568000 + 568000 568000 568000 568000 568000 + 568000 568000 632000 632000 632000 + 632000 632000 632000 632000 632000 + 712000 712000 712000 772000 772000 + 772000 772000 772000 772000 772000>, + /* Speed bin 1 */ + <568000 568000 568000 568000 568000 + 568000 568000 568000 568000 568000 + 568000 568000 632000 632000 632000 + 632000 632000 632000 632000 632000 + 712000 712000 712000 772000 772000 + 772000>; + + qcom,cpr-floor-to-ceiling-max-range = + /* Speed bin 0 */ + <55000 55000 55000 55000 + 55000 55000 55000 55000 + 55000 55000 55000 55000 + 65000 65000 65000 65000 + 65000 65000 65000 65000 + 65000 65000 65000 65000 + 65000 65000 65000 65000 + 65000 65000>, + /* Speed bin 1 */ + <55000 55000 55000 55000 + 55000 55000 55000 55000 + 55000 55000 55000 55000 + 65000 65000 65000 65000 + 65000 65000 65000 65000 + 65000 65000 65000 65000 + 65000 65000>; + + qcom,corner-frequencies = + /* Speed bin 0 */ + <300000000 345600000 422400000 + 499200000 576000000 652800000 + 729600000 806400000 902400000 + 979200000 1056000000 1132800000 + 1190400000 1267200000 1344000000 + 1420800000 1497600000 1574400000 + 1651200000 1728000000 1804800000 + 1881600000 1958400000 2035200000 + 2112000000 2188800000 2265600000 + 2342400000 2419200000 2496000000>, + /* Speed bin 1 */ + <300000000 345600000 422400000 + 499200000 576000000 652800000 + 729600000 806400000 902400000 + 979200000 1056000000 1132800000 + 1190400000 1267200000 1344000000 + 1420800000 1497600000 1574400000 + 1651200000 1728000000 1804800000 + 1881600000 1958400000 2035200000 + 2112000000 2208000000>; + + qcom,cpr-ro-scaling-factor = + <2857 3057 2828 2952 2699 2798 2446 + 2631 2629 2578 2244 3344 3289 3137 + 3164 2655>, + <2857 3057 2828 2952 2699 2798 2446 + 2631 2629 2578 2244 3344 3289 3137 + 3164 2655>, + <2603 2755 2676 2777 2573 2685 2465 + 2610 2312 2423 2243 3104 3022 3036 + 2740 2303>, + <1901 2016 2096 2228 2034 2161 2077 + 2188 1565 1870 1925 2235 2205 2413 + 1762 1478>; + + qcom,cpr-open-loop-voltage-fuse-adjustment = + /* Speed bin 0 */ + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>, + /* Speed bin 1 */ + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>; + + qcom,cpr-closed-loop-voltage-fuse-adjustment = + /* Speed bin 0 */ + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>, + /* Speed bin 1 */ + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>; + + qcom,allow-voltage-interpolation; + qcom,allow-quotient-interpolation; + qcom,cpr-scaled-open-loop-voltage-as-ceiling; + + qcom,cpr-aging-ref-corner = <30 26>; + qcom,cpr-aging-ro-scaling-factor = <2950>; + qcom,allow-aging-voltage-adjustment = <0>; +}; + +&pm8005_s1 { + regulator-min-microvolt = <516000>; + regulator-max-microvolt = <1088000>; +}; + +&gfx_cpr { + compatible = "qcom,cpr4-msm8998-v2-mmss-regulator"; + qcom,cpr-aging-ref-voltage = <1024000>; +}; + +&gfx_vreg { + regulator-min-microvolt = <1>; + regulator-max-microvolt = <8>; + + qcom,cpr-fuse-corners = <4>; + qcom,cpr-fuse-combos = <8>; + qcom,cpr-corners = <8>; + + qcom,cpr-corner-fmax-map = <1 3 5 8>; + + qcom,cpr-voltage-ceiling = + <656000 716000 772000 880000 908000 948000 1016000 1088000>, + <660000 724000 772000 832000 916000 968000 1024000 1024000>, + <660000 724000 772000 832000 916000 968000 1024000 1024000>, + <660000 724000 772000 832000 916000 968000 1024000 1024000>, + <660000 724000 772000 832000 916000 968000 1024000 1024000>, + <660000 724000 772000 832000 916000 968000 1024000 1024000>, + <660000 724000 772000 832000 916000 968000 1024000 1024000>, + <660000 724000 772000 832000 916000 968000 1024000 1024000>; + + qcom,cpr-voltage-floor = + <516000 516000 532000 584000 632000 672000 712000 756000>; + + qcom,mem-acc-voltage = <1 1 1 2 2 2 2 2>; + + qcom,corner-frequencies = + <180000000 257000000 342000000 414000000 + 515000000 596000000 670000000 710000000>; + + qcom,cpr-target-quotients = + < 0 0 0 0 331 357 0 0 + 0 0 0 0 0 0 115 0>, + < 0 0 0 0 467 500 0 0 + 0 0 0 0 0 0 199 0>, + < 0 0 0 0 628 665 0 0 + 0 0 0 0 0 0 290 0>, + < 0 0 0 0 762 805 0 0 + 0 0 0 0 0 0 397 0>, + < 0 0 0 0 964 1013 0 0 + 0 0 1143 0 1138 1055 0 0>, + < 0 0 0 0 0 0 0 0 + 0 0 1306 0 1289 1168 0 0>, + < 0 0 0 0 0 0 0 0 + 0 0 1468 0 1429 1256 0 0>, + < 0 0 0 0 0 0 0 0 + 0 0 1627 0 1578 1353 0 0>; + + qcom,cpr-ro-scaling-factor = + < 0 0 0 0 2377 2571 0 0 + 0 0 2168 0 2209 1849 1997 0>, + < 0 0 0 0 2377 2571 0 0 + 0 0 2168 0 2209 1849 1997 0>, + < 0 0 0 0 2377 2571 0 0 + 0 0 2168 0 2209 1849 1997 0>, + < 0 0 0 0 2377 2571 0 0 + 0 0 2168 0 2209 1849 1997 0>, + < 0 0 0 0 2377 2571 0 0 + 0 0 2168 0 2209 1849 1997 0>, + < 0 0 0 0 2377 2571 0 0 + 0 0 2168 0 2209 1849 1997 0>, + < 0 0 0 0 2377 2571 0 0 + 0 0 2168 0 2209 1849 1997 0>, + < 0 0 0 0 2377 2571 0 0 + 0 0 2168 0 2209 1849 1997 0>; + + qcom,cpr-open-loop-voltage-fuse-adjustment = + < 100000 0 0 0>, + < 100000 0 0 0>, + < 85000 (-15000) (-15000) (-15000)>, + < 85000 (-15000) (-15000) (-15000)>, + < 85000 (-15000) (-15000) (-15000)>, + < 85000 (-15000) (-15000) (-15000)>, + < 85000 (-15000) (-15000) (-15000)>, + < 85000 (-15000) (-15000) (-15000)>; + + qcom,cpr-closed-loop-voltage-adjustment = + < 96000 18000 4000 0 + 0 13000 9000 0>, + < 96000 18000 4000 0 + 0 13000 9000 0>, + < 81000 3000 (-11000) (-15000) + (-15000) (-2000) (-6000) (-15000)>, + < 81000 3000 (-11000) (-15000) + (-15000) (-2000) (-6000) (-15000)>, + < 81000 3000 (-11000) (-15000) + (-15000) (-2000) (-6000) (-15000)>, + < 81000 3000 (-11000) (-15000) + (-15000) (-2000) (-6000) (-15000)>, + < 81000 3000 (-11000) (-15000) + (-15000) (-2000) (-6000) (-15000)>, + < 81000 3000 (-11000) (-15000) + (-15000) (-2000) (-6000) (-15000)>; + + qcom,cpr-floor-to-ceiling-max-range = + <50000 50000 50000 50000 50000 50000 70000 70000>; + + qcom,cpr-fused-closed-loop-voltage-adjustment-map = + <0 0 1 2 3 0 0 4>; + + qcom,allow-voltage-interpolation; + qcom,cpr-scaled-open-loop-voltage-as-ceiling; + + qcom,cpr-aging-max-voltage-adjustment = <15000>; + qcom,cpr-aging-ref-corner = <8>; + qcom,cpr-aging-ro-scaling-factor = <2950>; + qcom,allow-aging-voltage-adjustment = <0 0 1 1 1 1 1 1>; +}; + +&qusb_phy0 { + reg = <0x0c012000 0x2a8>, + <0x01fcb24c 0x4>, + <0x00784238 0x4>; + reg-names = "qusb_phy_base", + "tcsr_clamp_dig_n_1p8", + "efuse_addr"; + qcom,efuse-bit-pos = <16>; + qcom,efuse-num-bits = <4>; + qcom,qusb-phy-init-seq = + /* */ + <0x13 0x04 /* analog_controls_two */ + 0x7c 0x18c /* pll_clock_inverter */ + 0x80 0x2c /* pll_cmode */ + 0x0a 0x184 /* pll_lock_delay */ + 0xa5 0x23c /* tune1 */ + 0x09 0x240 /* tune2 */ + 0x19 0xb4>; /* digital_timers_two */ +}; + +&msm_vidc { + qcom,load-freq-tbl = + /* Encoders */ + <1105920 533000000 0x55555555>, /* 4kx2304@30 */ /*TURBO*/ + <1036800 444000000 0x55555555>, /* 720p@240, 1080p@120,1440p@60, + * UHD@30 */ /*NOMINAL*/ + < 829440 355200000 0x55555555>, /* UHD/4096x2160@30 SVSL1 */ + < 489600 269330000 0x55555555>, /* 1080p@60, 720p@120 SVS */ + < 345600 200000000 0x55555555>, /* 2560x1440@24, 1080p@30 */ + /* SVS2 */ + + /* Decoders */ + <2211840 533000000 0xffffffff>, /* 4kx2304@60, 1080p@240 */ + /* TURBO */ + <1728000 444000000 0xffffffff>, /* 2560x1440@120 */ + /* NOMINAL */ + <1675472 355200000 0xffffffff>, /* 4kx2304@44 */ /*SVSL1*/ + <1105920 269330000 0xffffffff>, /* UHD/4k2304@30, 1080p@120 */ + /* SVS */ + < 829440 200000000 0xffffffff>; /* 720p@120, 1080p@60 */ + /* SVS2 */ + + qcom,imem-ab-tbl = + <200000000 1560000>,/* imem @ svs2 freq 75 Mhz */ + <269330000 3570000>,/* imem @ svs freq 171 Mhz */ + <355200000 3570000>,/* imem @ svs freq 171 Mhz */ + <444000000 6750000>,/* imem @ nom freq 323 Mhz */ + <533000000 8490000>;/* imem @ turbo freq 406 Mhz */ + + qcom,dcvs-tbl = /* minLoad LoadLow LoadHigh CodecCheck */ + /* Decode */ + /* Load > Nominal, Nominal <-> Turbo Eg.3840x2160@60 */ + <1728000 1728000 2211840 0x3f00000c>, + /* Encoder */ + /* Load > Nominal, Nominal <-> Turbo Eg. 4kx2304@30 */ + <1036800 1036800 1105920 0x04000004>, + /* Load > SVSL1, SVSL1<-> Nominal Eg. 3840x2160@30 */ + < 829440 829440 1036800 0x04000004>, + /* Load > SVS , SVS <-> SVSL1 Eg. 4kx2304@24 */ + < 489600 489600 829440 0x04000004>; + + qcom,dcvs-limit = /* Min Frame size, Min MBs/sec */ + <32400 30>, /* Encoder 3840x2160@30 */ + <32400 60>; /* Decoder 3840x2160@60 */ + +}; + +&soc { + /* Gold L2 SAW */ + qcom,spm@178120000 { + qcom,saw2-avs-limit = <0x4200420>; + }; + + /* Silver L2 SAW */ + qcom,spm@179120000 { + qcom,saw2-avs-limit = <0x4200420>; + }; +}; + +/* GPU overrides */ +&msm_gpu { + /* Updated chip ID */ + qcom,chipid = <0x05040001>; + qcom,initial-pwrlevel = <0>; + + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <342000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <5>; + qcom,bus-max = <9>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <257000000>; + qcom,bus-freq = <5>; + qcom,bus-min = <3>; + qcom,bus-max = <8>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <180000000>; + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <5>; + }; + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <27000000>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; +}; + +&spss_utils { + qcom,spss-test-firmware-name = "spss2t"; /* 8 chars max */ + qcom,spss-prod-firmware-name = "spss2p"; /* 8 chars max */ +}; + +&ufs1 { + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&clock_gcc clk_gcc_ufs_axi_hw_ctl_clk>, + <&clock_gcc clk_gcc_aggre1_ufs_axi_clk>, + <&clock_gcc clk_gcc_ufs_ahb_clk>, + <&clock_gcc clk_gcc_ufs_unipro_core_hw_ctl_clk>, + <&clock_gcc clk_gcc_ufs_ice_core_hw_ctl_clk>, + <&clock_gcc clk_ln_bb_clk1>, + <&clock_gcc clk_gcc_ufs_tx_symbol_0_clk>, + <&clock_gcc clk_gcc_ufs_rx_symbol_0_clk>, + <&clock_gcc clk_gcc_ufs_rx_symbol_1_clk>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + lanes-per-direction = <2>; +}; diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-cdp.dts b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-cdp.dts deleted file mode 100644 index 5ea248f6f2dc..000000000000 --- a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-cdp.dts +++ /dev/null @@ -1,155 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "msm8998-v2.1-interposer-msmfalcon.dtsi" -#include "msm8998-interposer-msmfalcon-cdp.dtsi" -#include "msm8998-interposer-pmfalcon.dtsi" -#include "msm8998-interposer-msmfalcon-audio.dtsi" -#include "msm8998-interposer-camera-sensor-cdp.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM 8998 v2.1 MSM FALCON Interposer CDP"; - compatible = "qcom,msm8998-cdp", "qcom,msm8998", "qcom,cdp"; - qcom,board-id = <1 1>; -}; - -&pmfalcon_charger { - qcom,batteryless-platform; -}; - -&clock_gcc { - vdd_dig-supply = <&pm2falcon_s3_level>; - vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>; -}; - -&clock_mmss { - vdd_dig-supply = <&pm2falcon_s3_level>; - vdd_mmsscc_mx-supply = <&pm2falcon_s5_level>; -}; - -&clock_gpu { - vdd_dig-supply = <&pm2falcon_s3_level>; -}; - -&clock_gfx { - /* GFX Rail = CX */ - vdd_gpucc-supply = <&pm2falcon_s3_level>; - vdd_mx-supply = <&pm2falcon_s5_level>; - vdd_gpu_mx-supply = <&pm2falcon_s5_level>; - qcom,gfxfreq-speedbin0 = - < 0 0 0 >, - < 180000000 RPM_SMD_REGULATOR_LEVEL_MIN_SVS - RPM_SMD_REGULATOR_LEVEL_SVS >, - < 257000000 RPM_SMD_REGULATOR_LEVEL_LOW_SVS - RPM_SMD_REGULATOR_LEVEL_SVS >, - < 342000000 RPM_SMD_REGULATOR_LEVEL_SVS - RPM_SMD_REGULATOR_LEVEL_SVS >, - < 414000000 RPM_SMD_REGULATOR_LEVEL_SVS_PLUS - RPM_SMD_REGULATOR_LEVEL_SVS >, - < 515000000 RPM_SMD_REGULATOR_LEVEL_NOM - RPM_SMD_REGULATOR_LEVEL_NOM >, - < 596000000 RPM_SMD_REGULATOR_LEVEL_NOM_PLUS - RPM_SMD_REGULATOR_LEVEL_NOM >, - < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO - RPM_SMD_REGULATOR_LEVEL_TURBO >, - < 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO - RPM_SMD_REGULATOR_LEVEL_TURBO >; - qcom,gfxfreq-mx-speedbin0 = - < 0 0 >, - < 180000000 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 257000000 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 342000000 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 414000000 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 515000000 RPM_SMD_REGULATOR_LEVEL_NOM >, - < 596000000 RPM_SMD_REGULATOR_LEVEL_NOM >, - < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >, - < 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; -}; - -&gdsc_gpu_gx { - clock-names = "core_root_clk"; - clocks = <&clock_gfx clk_gfx3d_clk_src>; - qcom,force-enable-root-clk; - /* GFX Rail = CX */ - parent-supply = <&pm2falcon_s3_level>; - status = "ok"; -}; - -&usb3 { - extcon = <&pmfalcon_pdphy>; -}; - -&qusb_phy0 { - vdd-supply = <&pm2falcon_l1>; - vdda18-supply = <&pmfalcon_l10>; - qcom,vdd-voltage-level = <0 925000 925000>; - vdda33-supply = <&pm2falcon_l7>; -}; - -&ssphy { - vdd-supply = <&pm2falcon_l1>; - qcom,vdd-voltage-level = <0 925000 925000>; - core-supply = <&pmfalcon_l1>; -}; - -&mdss_dsi { - hw-config = "split_dsi"; - vdda-1p2-supply = <&pmfalcon_l1>; - vdda-0p9-supply = <&pm2falcon_l1>; - - qcom,ctrl-supply-entries { - qcom,ctrl-supply-entry@0 { - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1250000>; - }; - }; - - qcom,phy-supply-entries { - qcom,phy-supply-entry@0 { - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <925000>; - }; - }; -}; - -&mdss_dsi0 { - qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; - wqhd-vddio-supply = <&pmfalcon_l11>; - lab-supply = <&lcdb_ldo_vreg>; - ibb-supply = <&lcdb_ncp_vreg>; - pinctrl-names = "mdss_default", "mdss_sleep"; - pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; - pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; - qcom,platform-reset-gpio = <&tlmm 94 0>; - qcom,platform-te-gpio = <&tlmm 10 0>; - qcom,panel-mode-gpio = <&tlmm 91 0>; -}; - -&mdss_dsi1 { - qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; - wqhd-vddio-supply = <&pmfalcon_l11>; - lab-supply = <&lcdb_ldo_vreg>; - ibb-supply = <&lcdb_ncp_vreg>; - pinctrl-names = "mdss_default", "mdss_sleep"; - pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; - pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; - qcom,platform-reset-gpio = <&tlmm 94 0>; - qcom,platform-te-gpio = <&tlmm 10 0>; - qcom,panel-mode-gpio = <&tlmm 91 0>; -}; - -&pm2falcon_wled { - qcom,led-strings-list = [01 02]; -}; diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-mtp.dts b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-mtp.dts deleted file mode 100644 index 7c0c53033a44..000000000000 --- a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-mtp.dts +++ /dev/null @@ -1,184 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "msm8998-v2.1-interposer-msmfalcon.dtsi" -#include "msm8998-interposer-msmfalcon-mtp.dtsi" -#include "msm8998-interposer-pmfalcon.dtsi" -#include "msm8998-interposer-msmfalcon-audio.dtsi" -#include "msm8998-interposer-camera-sensor-mtp.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM 8998 v2.1 MSM FALCON Interposer MTP"; - compatible = "qcom,msm8998-mtp", "qcom,msm8998", "qcom,mtp"; - qcom,board-id = <8 2>; -}; - -&pmfalcon_fg { - qcom,battery-data = <&mtp_batterydata>; -}; - -&clock_gcc { - vdd_dig-supply = <&pm2falcon_s3_level>; - vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>; -}; - -&clock_mmss { - vdd_dig-supply = <&pm2falcon_s3_level>; - vdd_mmsscc_mx-supply = <&pm2falcon_s5_level>; -}; - -&clock_gpu { - vdd_dig-supply = <&pm2falcon_s3_level>; -}; - -&clock_gfx { - /* GFX Rail = CX */ - vdd_gpucc-supply = <&pm2falcon_s3_level>; - vdd_mx-supply = <&pm2falcon_s5_level>; - vdd_gpu_mx-supply = <&pm2falcon_s5_level>; - qcom,gfxfreq-speedbin0 = - < 0 0 0 >, - < 180000000 RPM_SMD_REGULATOR_LEVEL_MIN_SVS - RPM_SMD_REGULATOR_LEVEL_SVS >, - < 257000000 RPM_SMD_REGULATOR_LEVEL_LOW_SVS - RPM_SMD_REGULATOR_LEVEL_SVS >, - < 342000000 RPM_SMD_REGULATOR_LEVEL_SVS - RPM_SMD_REGULATOR_LEVEL_SVS >, - < 414000000 RPM_SMD_REGULATOR_LEVEL_SVS_PLUS - RPM_SMD_REGULATOR_LEVEL_SVS >, - < 515000000 RPM_SMD_REGULATOR_LEVEL_NOM - RPM_SMD_REGULATOR_LEVEL_NOM >, - < 596000000 RPM_SMD_REGULATOR_LEVEL_NOM_PLUS - RPM_SMD_REGULATOR_LEVEL_NOM >, - < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO - RPM_SMD_REGULATOR_LEVEL_TURBO >, - < 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO - RPM_SMD_REGULATOR_LEVEL_TURBO >; - qcom,gfxfreq-mx-speedbin0 = - < 0 0 >, - < 180000000 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 257000000 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 342000000 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 414000000 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 515000000 RPM_SMD_REGULATOR_LEVEL_NOM >, - < 596000000 RPM_SMD_REGULATOR_LEVEL_NOM >, - < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >, - < 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; -}; - -&gdsc_gpu_gx { - clock-names = "core_root_clk"; - clocks = <&clock_gfx clk_gfx3d_clk_src>; - qcom,force-enable-root-clk; - /* GFX Rail = CX */ - parent-supply = <&pm2falcon_s3_level>; - status = "ok"; -}; - -&mdss_dsi { - hw-config = "split_dsi"; - vdda-1p2-supply = <&pmfalcon_l1>; - vdda-0p9-supply = <&pm2falcon_l1>; - - qcom,ctrl-supply-entries { - qcom,ctrl-supply-entry@0 { - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1250000>; - }; - }; - - qcom,phy-supply-entries { - qcom,phy-supply-entry@0 { - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <925000>; - }; - }; -}; - -&mdss_dsi0 { - qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; - wqhd-vddio-supply = <&pmfalcon_l11>; - lab-supply = <&lcdb_ldo_vreg>; - ibb-supply = <&lcdb_ncp_vreg>; - pinctrl-names = "mdss_default", "mdss_sleep"; - pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; - pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; - qcom,platform-reset-gpio = <&tlmm 94 0>; - qcom,platform-te-gpio = <&tlmm 10 0>; - qcom,panel-mode-gpio = <&tlmm 91 0>; -}; - -&mdss_dsi1 { - qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; - wqhd-vddio-supply = <&pmfalcon_l11>; - lab-supply = <&lcdb_ldo_vreg>; - ibb-supply = <&lcdb_ncp_vreg>; - pinctrl-names = "mdss_default", "mdss_sleep"; - pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; - pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; - qcom,platform-reset-gpio = <&tlmm 94 0>; - qcom,platform-te-gpio = <&tlmm 10 0>; - qcom,panel-mode-gpio = <&tlmm 91 0>; -}; - -&usb3 { - extcon = <&pmfalcon_pdphy>; -}; - -&qusb_phy0 { - vdd-supply = <&pm2falcon_l1>; - vdda18-supply = <&pmfalcon_l10>; - qcom,vdd-voltage-level = <0 925000 925000>; - vdda33-supply = <&pm2falcon_l7>; -}; - -&ssphy { - vdd-supply = <&pm2falcon_l1>; - qcom,vdd-voltage-level = <0 925000 925000>; - core-supply = <&pmfalcon_l1>; -}; - -&pm2falcon_gpios { - /* GPIO 7 for VOL_UP */ - gpio@c600 { - status = "okay"; - qcom,mode = <0>; - qcom,pull = <0>; - qcom,vin-sel = <0>; - qcom,src-sel = <0>; - qcom,out-strength = <1>; - }; -}; - -&soc { - gpio_keys { - compatible = "gpio-keys"; - input-name = "gpio-keys"; - status = "okay"; - - vol_up { - label = "volume_up"; - gpios = <&pm2falcon_gpios 7 0x1>; - linux,input-type = <1>; - linux,code = <115>; - gpio-key,wakeup; - debounce-interval = <15>; - }; - }; -}; - -&pm2falcon_wled { - qcom,led-strings-list = [01 02]; -}; diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dts b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dts deleted file mode 100644 index 3de548ed1446..000000000000 --- a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dts +++ /dev/null @@ -1,169 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "msm8998-v2.1-interposer-msmfalcon-qrd.dtsi" -#include "msm8998-interposer-pmfalcon.dtsi" -#include "msm8998-interposer-msmfalcon-audio.dtsi" -#include "msm8998-interposer-camera-sensor-qrd.dtsi" - -/ { - model = - "Qualcomm Technologies, Inc. MSM 8998 v2.1 MSM FALCON Interposer QRD"; - compatible = "qcom,msm8998-qrd", "qcom,msm8998", "qcom,qrd"; - qcom,board-id = <0x03000b 0x80>; -}; - -&slim_aud { - tasha_codec { - /delete-property/cdc-vdd-buck-supply; - /delete-property/cdc-buck-sido-supply; - /delete-property/cdc-vdd-tx-h-supply; - /delete-property/cdc-vdd-rx-h-supply; - /delete-property/cdc-vddpx-1-supply; - }; - - tavil_codec { - /delete-property/cdc-vdd-buck-supply; - /delete-property/cdc-buck-sido-supply; - /delete-property/cdc-vdd-tx-h-supply; - /delete-property/cdc-vdd-rx-h-supply; - /delete-property/cdc-vddpx-1-supply; - }; -}; - -&clock_gcc { - vdd_dig-supply = <&pm2falcon_s3_level>; - vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>; -}; - -&clock_mmss { - vdd_dig-supply = <&pm2falcon_s3_level>; - vdd_mmsscc_mx-supply = <&pm2falcon_s5_level>; -}; - -&clock_gpu { - vdd_dig-supply = <&pm2falcon_s3_level>; -}; - -&clock_gfx { - /* GFX Rail = CX */ - vdd_gpucc-supply = <&pm2falcon_s3_level>; - vdd_mx-supply = <&pm2falcon_s5_level>; - vdd_gpu_mx-supply = <&pm2falcon_s5_level>; - qcom,gfxfreq-speedbin0 = - < 0 0 0 >, - < 180000000 RPM_SMD_REGULATOR_LEVEL_MIN_SVS - RPM_SMD_REGULATOR_LEVEL_SVS >, - < 257000000 RPM_SMD_REGULATOR_LEVEL_LOW_SVS - RPM_SMD_REGULATOR_LEVEL_SVS >, - < 342000000 RPM_SMD_REGULATOR_LEVEL_SVS - RPM_SMD_REGULATOR_LEVEL_SVS >, - < 414000000 RPM_SMD_REGULATOR_LEVEL_SVS_PLUS - RPM_SMD_REGULATOR_LEVEL_SVS >, - < 515000000 RPM_SMD_REGULATOR_LEVEL_NOM - RPM_SMD_REGULATOR_LEVEL_NOM >, - < 596000000 RPM_SMD_REGULATOR_LEVEL_NOM_PLUS - RPM_SMD_REGULATOR_LEVEL_NOM >, - < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO - RPM_SMD_REGULATOR_LEVEL_TURBO >, - < 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO - RPM_SMD_REGULATOR_LEVEL_TURBO >; - qcom,gfxfreq-mx-speedbin0 = - < 0 0 >, - < 180000000 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 257000000 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 342000000 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 414000000 RPM_SMD_REGULATOR_LEVEL_SVS >, - < 515000000 RPM_SMD_REGULATOR_LEVEL_NOM >, - < 596000000 RPM_SMD_REGULATOR_LEVEL_NOM >, - < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >, - < 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; -}; - -&gdsc_gpu_gx { - clock-names = "core_root_clk"; - clocks = <&clock_gfx clk_gfx3d_clk_src>; - qcom,force-enable-root-clk; - /* GFX Rail = CX */ - parent-supply = <&pm2falcon_s3_level>; - status = "ok"; -}; - -&usb3 { - extcon = <&pmfalcon_pdphy>; -}; - -&qusb_phy0 { - vdd-supply = <&pm2falcon_l1>; - vdda18-supply = <&pmfalcon_l10>; - qcom,vdd-voltage-level = <0 925000 925000>; - vdda33-supply = <&pm2falcon_l7>; -}; - -&ssphy { - vdd-supply = <&pm2falcon_l1>; - qcom,vdd-voltage-level = <0 925000 925000>; - core-supply = <&pmfalcon_l1>; -}; - -&sdhc_2 { - vdd-supply = <&pm2falcon_l5>; - vdd-io-supply = <&pm2falcon_l2>; -}; - -&pm2falcon_gpios { - /* GPIO 7 for VOL_UP */ - gpio@c600 { - status = "ok"; - qcom,mode = <0>; - qcom,pull = <0>; - qcom,vin-sel = <0>; - qcom,src-sel = <0>; - qcom,out-strength = <1>; - }; -}; - -&soc { - gpio_keys { - compatible = "gpio-keys"; - input-name = "gpio-keys"; - status = "ok"; - - vol_up { - label = "volume_up"; - gpios = <&pm2falcon_gpios 7 0x1>; - linux,input-type = <1>; - linux,code = <115>; - gpio-key,wakeup; - debounce-interval = <15>; - }; - }; -}; - -/ { - qrd_batterydata: qcom,battery-data { - qcom,batt-id-range-pct = <15>; - - #include "fg-gen3-batterydata-qrd-skuk-4v4-3000mah.dtsi" - }; -}; - -&pmfalcon_fg { - qcom,battery-data = <&qrd_batterydata>; -}; - -&pm2falcon_wled { - qcom,led-strings-list = [00 01]; -}; diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dtsi b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dtsi deleted file mode 100644 index 9740e9c1b168..000000000000 --- a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dtsi +++ /dev/null @@ -1,125 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include "msm8998-v2.1-interposer-msmfalcon.dtsi" -#include "msm8998-camera-sensor-mtp.dtsi" - -/ { - bluetooth: bt_wcn3990 { - compatible = "qca,wcn3990"; - qca,bt-vdd-core-supply = <&pmfalcon_l9_pin_ctrl>; - qca,bt-vdd-pa-supply = <&pmfalcon_l6_pin_ctrl>; - qca,bt-vdd-ldo-supply = <&pmfalcon_l19_pin_ctrl>; - qca,bt-chip-pwd-supply = <&pm2falcon_bob_pin1>; - clocks = <&clock_gcc clk_rf_clk1>; - clock-names = "rf_clk1"; - - qca,bt-vdd-core-voltage-level = <1800000 1900000>; - qca,bt-vdd-pa-voltage-level = <1304000 1370000>; - qca,bt-vdd-ldo-voltage-level = <3312000 3400000>; - qca,bt-chip-pwd-voltage-level = <3600000 3600000>; - - qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ - qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ - qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */ - }; -}; - -&blsp1_uart3_hs { - status = "ok"; -}; - -&uartblsp2dm1 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&uart_console_active>; -}; - -&ufsphy1 { - vdda-phy-supply = <&pm2falcon_l1>; - vdda-pll-supply = <&pmfalcon_l1>; - vddp-ref-clk-supply = <&pmfalcon_l1>; - vdda-phy-max-uv = <925000>; - vdda-phy-min-uv = <800000>; - vdda-phy-max-microamp = <51400>; - vdda-pll-max-microamp = <14600>; - vddp-ref-clk-max-microamp = <100>; - vddp-ref-clk-always-on; - status = "ok"; -}; - -&ufs1 { - vdd-hba-supply = <&gdsc_ufs>; - vdd-hba-fixed-regulator; - vcc-supply = <&pm2falcon_l4>; - vccq2-supply = <&pmfalcon_l8>; - vcc-max-microamp = <500000>; - vccq2-max-microamp = <600000>; - status = "ok"; -}; - -&ufs_ice { - status = "ok"; -}; - -&sdhc_2 { - vdd-supply = <&pm2falcon_l5>; - qcom,vdd-voltage-level = <2950000 2950000>; - qcom,vdd-current-level = <200 800000>; - - vdd-io-supply = <&pm2falcon_l2>; - qcom,vdd-io-voltage-level = <1800000 2950000>; - qcom,vdd-io-current-level = <200 22000>; - - pinctrl-names = "active", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - - qcom,clk-rates = <400000 20000000 25000000 - 50000000 100000000 200000000>; - qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; - - cd-gpios = <&tlmm 95 0x0>; - - status = "ok"; -}; - - -&i2c_5 { - status = "okay"; - synaptics@20 { - compatible = "synaptics,dsx"; - reg = <0x20>; - interrupt-parent = <&tlmm>; - interrupts = <125 0x2008>; - avdd-supply = <&pm2falcon_l3>; - vdd-supply = <&pmfalcon_l11>; - synaptics,vdd-voltage = <1880000 1880000>; - synaptics,avdd-voltage = <3000000 3008000>; - synaptics,vdd-current = <40000>; - synaptics,avdd-current = <20000>; - /* pins used by touchscreen */ - pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", - "pmx_ts_release"; - pinctrl-0 = <&ts_int_active &ts_reset_active>; - pinctrl-1 = <&ts_int_suspend1 &ts_reset_suspend1>; - pinctrl-2 = <&ts_release>; - synaptics,display-coords = <0 0 1439 2559>; - synaptics,panel-coords = <0 0 1439 2779>; - synaptics,irq-gpio = <&tlmm 125 0x2008>; - synaptics,reset-gpio = <&tlmm 89 0x0>; - synaptics,i2c-pull-up; - synaptics,disable-gpios; - synaptics,button-map = <139 172 158>; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon.dtsi deleted file mode 100644 index c2a393bd019d..000000000000 --- a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -/* Copyright (c) 2016 The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "msm8998-v2-interposer-msmfalcon.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM8998 v2.1"; - qcom,msm-id = <292 0x20001>; -}; diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-cdp.dts b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-cdp.dts new file mode 100644 index 000000000000..6884397bf0ba --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-cdp.dts @@ -0,0 +1,155 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "msm8998-v2.1-interposer-sdm660.dtsi" +#include "msm8998-interposer-sdm660-cdp.dtsi" +#include "msm8998-interposer-pm660.dtsi" +#include "msm8998-interposer-sdm660-audio.dtsi" +#include "msm8998-interposer-camera-sensor-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM 8998 v2.1 SDM 660 Interposer CDP"; + compatible = "qcom,msm8998-cdp", "qcom,msm8998", "qcom,cdp"; + qcom,board-id = <1 1>; +}; + +&pm660_charger { + qcom,batteryless-platform; +}; + +&clock_gcc { + vdd_dig-supply = <&pm660l_s3_level>; + vdd_dig_ao-supply = <&pm660l_s3_level_ao>; +}; + +&clock_mmss { + vdd_dig-supply = <&pm660l_s3_level>; + vdd_mmsscc_mx-supply = <&pm660l_s5_level>; +}; + +&clock_gpu { + vdd_dig-supply = <&pm660l_s3_level>; +}; + +&clock_gfx { + /* GFX Rail = CX */ + vdd_gpucc-supply = <&pm660l_s3_level>; + vdd_mx-supply = <&pm660l_s5_level>; + vdd_gpu_mx-supply = <&pm660l_s5_level>; + qcom,gfxfreq-speedbin0 = + < 0 0 0 >, + < 180000000 RPM_SMD_REGULATOR_LEVEL_MIN_SVS + RPM_SMD_REGULATOR_LEVEL_SVS >, + < 257000000 RPM_SMD_REGULATOR_LEVEL_LOW_SVS + RPM_SMD_REGULATOR_LEVEL_SVS >, + < 342000000 RPM_SMD_REGULATOR_LEVEL_SVS + RPM_SMD_REGULATOR_LEVEL_SVS >, + < 414000000 RPM_SMD_REGULATOR_LEVEL_SVS_PLUS + RPM_SMD_REGULATOR_LEVEL_SVS >, + < 515000000 RPM_SMD_REGULATOR_LEVEL_NOM + RPM_SMD_REGULATOR_LEVEL_NOM >, + < 596000000 RPM_SMD_REGULATOR_LEVEL_NOM_PLUS + RPM_SMD_REGULATOR_LEVEL_NOM >, + < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO + RPM_SMD_REGULATOR_LEVEL_TURBO >, + < 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO + RPM_SMD_REGULATOR_LEVEL_TURBO >; + qcom,gfxfreq-mx-speedbin0 = + < 0 0 >, + < 180000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 257000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 342000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 414000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 515000000 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 596000000 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >, + < 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; +}; + +&gdsc_gpu_gx { + clock-names = "core_root_clk"; + clocks = <&clock_gfx clk_gfx3d_clk_src>; + qcom,force-enable-root-clk; + /* GFX Rail = CX */ + parent-supply = <&pm660l_s3_level>; + status = "ok"; +}; + +&usb3 { + extcon = <&pm660_pdphy>; +}; + +&qusb_phy0 { + vdd-supply = <&pm660l_l1>; + vdda18-supply = <&pm660_l10>; + qcom,vdd-voltage-level = <0 925000 925000>; + vdda33-supply = <&pm660l_l7>; +}; + +&ssphy { + vdd-supply = <&pm660l_l1>; + qcom,vdd-voltage-level = <0 925000 925000>; + core-supply = <&pm660_l1>; +}; + +&mdss_dsi { + hw-config = "split_dsi"; + vdda-1p2-supply = <&pm660_l1>; + vdda-0p9-supply = <&pm660l_l1>; + + qcom,ctrl-supply-entries { + qcom,ctrl-supply-entry@0 { + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1250000>; + }; + }; + + qcom,phy-supply-entries { + qcom,phy-supply-entry@0 { + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <925000>; + }; + }; +}; + +&mdss_dsi0 { + qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; + wqhd-vddio-supply = <&pm660_l11>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + pinctrl-names = "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; + pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; + qcom,platform-reset-gpio = <&tlmm 94 0>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,panel-mode-gpio = <&tlmm 91 0>; +}; + +&mdss_dsi1 { + qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; + wqhd-vddio-supply = <&pm660_l11>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + pinctrl-names = "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; + pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; + qcom,platform-reset-gpio = <&tlmm 94 0>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,panel-mode-gpio = <&tlmm 91 0>; +}; + +&pm660l_wled { + qcom,led-strings-list = [01 02]; +}; diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-mtp.dts b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-mtp.dts new file mode 100644 index 000000000000..2e5de95de0c5 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-mtp.dts @@ -0,0 +1,184 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "msm8998-v2.1-interposer-sdm660.dtsi" +#include "msm8998-interposer-sdm660-mtp.dtsi" +#include "msm8998-interposer-pm660.dtsi" +#include "msm8998-interposer-sdm660-audio.dtsi" +#include "msm8998-interposer-camera-sensor-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM 8998 v2.1 SDM 660 Interposer MTP"; + compatible = "qcom,msm8998-mtp", "qcom,msm8998", "qcom,mtp"; + qcom,board-id = <8 2>; +}; + +&pm660_fg { + qcom,battery-data = <&mtp_batterydata>; +}; + +&clock_gcc { + vdd_dig-supply = <&pm660l_s3_level>; + vdd_dig_ao-supply = <&pm660l_s3_level_ao>; +}; + +&clock_mmss { + vdd_dig-supply = <&pm660l_s3_level>; + vdd_mmsscc_mx-supply = <&pm660l_s5_level>; +}; + +&clock_gpu { + vdd_dig-supply = <&pm660l_s3_level>; +}; + +&clock_gfx { + /* GFX Rail = CX */ + vdd_gpucc-supply = <&pm660l_s3_level>; + vdd_mx-supply = <&pm660l_s5_level>; + vdd_gpu_mx-supply = <&pm660l_s5_level>; + qcom,gfxfreq-speedbin0 = + < 0 0 0 >, + < 180000000 RPM_SMD_REGULATOR_LEVEL_MIN_SVS + RPM_SMD_REGULATOR_LEVEL_SVS >, + < 257000000 RPM_SMD_REGULATOR_LEVEL_LOW_SVS + RPM_SMD_REGULATOR_LEVEL_SVS >, + < 342000000 RPM_SMD_REGULATOR_LEVEL_SVS + RPM_SMD_REGULATOR_LEVEL_SVS >, + < 414000000 RPM_SMD_REGULATOR_LEVEL_SVS_PLUS + RPM_SMD_REGULATOR_LEVEL_SVS >, + < 515000000 RPM_SMD_REGULATOR_LEVEL_NOM + RPM_SMD_REGULATOR_LEVEL_NOM >, + < 596000000 RPM_SMD_REGULATOR_LEVEL_NOM_PLUS + RPM_SMD_REGULATOR_LEVEL_NOM >, + < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO + RPM_SMD_REGULATOR_LEVEL_TURBO >, + < 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO + RPM_SMD_REGULATOR_LEVEL_TURBO >; + qcom,gfxfreq-mx-speedbin0 = + < 0 0 >, + < 180000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 257000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 342000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 414000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 515000000 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 596000000 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >, + < 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; +}; + +&gdsc_gpu_gx { + clock-names = "core_root_clk"; + clocks = <&clock_gfx clk_gfx3d_clk_src>; + qcom,force-enable-root-clk; + /* GFX Rail = CX */ + parent-supply = <&pm660l_s3_level>; + status = "ok"; +}; + +&mdss_dsi { + hw-config = "split_dsi"; + vdda-1p2-supply = <&pm660_l1>; + vdda-0p9-supply = <&pm660l_l1>; + + qcom,ctrl-supply-entries { + qcom,ctrl-supply-entry@0 { + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1250000>; + }; + }; + + qcom,phy-supply-entries { + qcom,phy-supply-entry@0 { + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <925000>; + }; + }; +}; + +&mdss_dsi0 { + qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; + wqhd-vddio-supply = <&pm660_l11>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + pinctrl-names = "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; + pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; + qcom,platform-reset-gpio = <&tlmm 94 0>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,panel-mode-gpio = <&tlmm 91 0>; +}; + +&mdss_dsi1 { + qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; + wqhd-vddio-supply = <&pm660_l11>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + pinctrl-names = "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; + pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; + qcom,platform-reset-gpio = <&tlmm 94 0>; + qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,panel-mode-gpio = <&tlmm 91 0>; +}; + +&usb3 { + extcon = <&pm660_pdphy>; +}; + +&qusb_phy0 { + vdd-supply = <&pm660l_l1>; + vdda18-supply = <&pm660_l10>; + qcom,vdd-voltage-level = <0 925000 925000>; + vdda33-supply = <&pm660l_l7>; +}; + +&ssphy { + vdd-supply = <&pm660l_l1>; + qcom,vdd-voltage-level = <0 925000 925000>; + core-supply = <&pm660_l1>; +}; + +&pm660l_gpios { + /* GPIO 7 for VOL_UP */ + gpio@c600 { + status = "okay"; + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <0>; + qcom,src-sel = <0>; + qcom,out-strength = <1>; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + status = "okay"; + + vol_up { + label = "volume_up"; + gpios = <&pm660l_gpios 7 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; +}; + +&pm660l_wled { + qcom,led-strings-list = [01 02]; +}; diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-qrd.dts b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-qrd.dts new file mode 100644 index 000000000000..9957adcc2336 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-qrd.dts @@ -0,0 +1,169 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "msm8998-v2.1-interposer-sdm660-qrd.dtsi" +#include "msm8998-interposer-pm660.dtsi" +#include "msm8998-interposer-sdm660-audio.dtsi" +#include "msm8998-interposer-camera-sensor-qrd.dtsi" + +/ { + model = + "Qualcomm Technologies, Inc. MSM 8998 v2.1 SDM 660 Interposer QRD"; + compatible = "qcom,msm8998-qrd", "qcom,msm8998", "qcom,qrd"; + qcom,board-id = <0x03000b 0x80>; +}; + +&slim_aud { + tasha_codec { + /delete-property/cdc-vdd-buck-supply; + /delete-property/cdc-buck-sido-supply; + /delete-property/cdc-vdd-tx-h-supply; + /delete-property/cdc-vdd-rx-h-supply; + /delete-property/cdc-vddpx-1-supply; + }; + + tavil_codec { + /delete-property/cdc-vdd-buck-supply; + /delete-property/cdc-buck-sido-supply; + /delete-property/cdc-vdd-tx-h-supply; + /delete-property/cdc-vdd-rx-h-supply; + /delete-property/cdc-vddpx-1-supply; + }; +}; + +&clock_gcc { + vdd_dig-supply = <&pm660l_s3_level>; + vdd_dig_ao-supply = <&pm660l_s3_level_ao>; +}; + +&clock_mmss { + vdd_dig-supply = <&pm660l_s3_level>; + vdd_mmsscc_mx-supply = <&pm660l_s5_level>; +}; + +&clock_gpu { + vdd_dig-supply = <&pm660l_s3_level>; +}; + +&clock_gfx { + /* GFX Rail = CX */ + vdd_gpucc-supply = <&pm660l_s3_level>; + vdd_mx-supply = <&pm660l_s5_level>; + vdd_gpu_mx-supply = <&pm660l_s5_level>; + qcom,gfxfreq-speedbin0 = + < 0 0 0 >, + < 180000000 RPM_SMD_REGULATOR_LEVEL_MIN_SVS + RPM_SMD_REGULATOR_LEVEL_SVS >, + < 257000000 RPM_SMD_REGULATOR_LEVEL_LOW_SVS + RPM_SMD_REGULATOR_LEVEL_SVS >, + < 342000000 RPM_SMD_REGULATOR_LEVEL_SVS + RPM_SMD_REGULATOR_LEVEL_SVS >, + < 414000000 RPM_SMD_REGULATOR_LEVEL_SVS_PLUS + RPM_SMD_REGULATOR_LEVEL_SVS >, + < 515000000 RPM_SMD_REGULATOR_LEVEL_NOM + RPM_SMD_REGULATOR_LEVEL_NOM >, + < 596000000 RPM_SMD_REGULATOR_LEVEL_NOM_PLUS + RPM_SMD_REGULATOR_LEVEL_NOM >, + < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO + RPM_SMD_REGULATOR_LEVEL_TURBO >, + < 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO + RPM_SMD_REGULATOR_LEVEL_TURBO >; + qcom,gfxfreq-mx-speedbin0 = + < 0 0 >, + < 180000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 257000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 342000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 414000000 RPM_SMD_REGULATOR_LEVEL_SVS >, + < 515000000 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 596000000 RPM_SMD_REGULATOR_LEVEL_NOM >, + < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >, + < 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; +}; + +&gdsc_gpu_gx { + clock-names = "core_root_clk"; + clocks = <&clock_gfx clk_gfx3d_clk_src>; + qcom,force-enable-root-clk; + /* GFX Rail = CX */ + parent-supply = <&pm660l_s3_level>; + status = "ok"; +}; + +&usb3 { + extcon = <&pm660_pdphy>; +}; + +&qusb_phy0 { + vdd-supply = <&pm660l_l1>; + vdda18-supply = <&pm660_l10>; + qcom,vdd-voltage-level = <0 925000 925000>; + vdda33-supply = <&pm660l_l7>; +}; + +&ssphy { + vdd-supply = <&pm660l_l1>; + qcom,vdd-voltage-level = <0 925000 925000>; + core-supply = <&pm660_l1>; +}; + +&sdhc_2 { + vdd-supply = <&pm660l_l5>; + vdd-io-supply = <&pm660l_l2>; +}; + +&pm660l_gpios { + /* GPIO 7 for VOL_UP */ + gpio@c600 { + status = "ok"; + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <0>; + qcom,src-sel = <0>; + qcom,out-strength = <1>; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + status = "ok"; + + vol_up { + label = "volume_up"; + gpios = <&pm660l_gpios 7 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; +}; + +/ { + qrd_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + + #include "fg-gen3-batterydata-qrd-skuk-4v4-3000mah.dtsi" + }; +}; + +&pm660_fg { + qcom,battery-data = <&qrd_batterydata>; +}; + +&pm660l_wled { + qcom,led-strings-list = [00 01]; +}; diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-qrd.dtsi b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-qrd.dtsi new file mode 100644 index 000000000000..5a882c7eb27f --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-qrd.dtsi @@ -0,0 +1,125 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "msm8998-v2.1-interposer-sdm660.dtsi" +#include "msm8998-camera-sensor-mtp.dtsi" + +/ { + bluetooth: bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-vdd-core-supply = <&pm660_l9_pin_ctrl>; + qca,bt-vdd-pa-supply = <&pm660_l6_pin_ctrl>; + qca,bt-vdd-ldo-supply = <&pm660_l19_pin_ctrl>; + qca,bt-chip-pwd-supply = <&pm660l_bob_pin1>; + clocks = <&clock_gcc clk_rf_clk1>; + clock-names = "rf_clk1"; + + qca,bt-vdd-core-voltage-level = <1800000 1900000>; + qca,bt-vdd-pa-voltage-level = <1304000 1370000>; + qca,bt-vdd-ldo-voltage-level = <3312000 3400000>; + qca,bt-chip-pwd-voltage-level = <3600000 3600000>; + + qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */ + }; +}; + +&blsp1_uart3_hs { + status = "ok"; +}; + +&uartblsp2dm1 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&ufsphy1 { + vdda-phy-supply = <&pm660l_l1>; + vdda-pll-supply = <&pm660_l1>; + vddp-ref-clk-supply = <&pm660_l1>; + vdda-phy-max-uv = <925000>; + vdda-phy-min-uv = <800000>; + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14600>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; + status = "ok"; +}; + +&ufs1 { + vdd-hba-supply = <&gdsc_ufs>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm660l_l4>; + vccq2-supply = <&pm660_l8>; + vcc-max-microamp = <500000>; + vccq2-max-microamp = <600000>; + status = "ok"; +}; + +&ufs_ice { + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&pm660l_l5>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm660l_l2>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + qcom,clk-rates = <400000 20000000 25000000 + 50000000 100000000 200000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + + cd-gpios = <&tlmm 95 0x0>; + + status = "ok"; +}; + + +&i2c_5 { + status = "okay"; + synaptics@20 { + compatible = "synaptics,dsx"; + reg = <0x20>; + interrupt-parent = <&tlmm>; + interrupts = <125 0x2008>; + avdd-supply = <&pm660l_l3>; + vdd-supply = <&pm660_l11>; + synaptics,vdd-voltage = <1880000 1880000>; + synaptics,avdd-voltage = <3000000 3008000>; + synaptics,vdd-current = <40000>; + synaptics,avdd-current = <20000>; + /* pins used by touchscreen */ + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend1 &ts_reset_suspend1>; + pinctrl-2 = <&ts_release>; + synaptics,display-coords = <0 0 1439 2559>; + synaptics,panel-coords = <0 0 1439 2779>; + synaptics,irq-gpio = <&tlmm 125 0x2008>; + synaptics,reset-gpio = <&tlmm 89 0x0>; + synaptics,i2c-pull-up; + synaptics,disable-gpios; + synaptics,button-map = <139 172 158>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660.dtsi b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660.dtsi new file mode 100644 index 000000000000..8adbff55fead --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660.dtsi @@ -0,0 +1,18 @@ +/* Copyright (c) 2016 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msm8998-v2-interposer-sdm660.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM8998 v2.1"; + qcom,msm-id = <292 0x20001>; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-audio.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-audio.dtsi deleted file mode 100644 index df42ba124641..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-audio.dtsi +++ /dev/null @@ -1,248 +0,0 @@ -/* - * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "msmfalcon-wsa881x.dtsi" -#include "msmfalcon-lpi.dtsi" - -&slim_aud { - status = "okay"; - dai_slim: msm_dai_slim { - compatible = "qcom,msm-dai-slim"; - elemental-addr = [ff ff ff fe 17 02]; - }; - - wcd9335: tasha_codec { - compatible = "qcom,tasha-slim-pgd"; - elemental-addr = [00 01 a0 01 17 02]; - - interrupt-parent = <&wcd9xxx_intc>; - interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 - 17 18 19 20 21 22 23 24 25 26 27 28 29 - 30>; - - qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; - - clock-names = "wcd_clk", "wcd_native_clk"; - clocks = <&clock_audio AUDIO_PMI_CLK>, - <&clock_audio AUDIO_AP_CLK2>; - - cdc-vdd-mic-bias-supply = <&pm2falcon_bob>; - qcom,cdc-vdd-mic-bias-voltage = <3300000 3300000>; - qcom,cdc-vdd-mic-bias-current = <30400>; - - qcom,cdc-static-supplies = "cdc-vdd-mic-bias"; - - qcom,cdc-micbias1-mv = <1800>; - qcom,cdc-micbias2-mv = <1800>; - qcom,cdc-micbias3-mv = <1800>; - qcom,cdc-micbias4-mv = <1800>; - - qcom,cdc-mclk-clk-rate = <9600000>; - qcom,cdc-slim-ifd = "tasha-slim-ifd"; - qcom,cdc-slim-ifd-elemental-addr = [00 00 a0 01 17 02]; - qcom,cdc-dmic-sample-rate = <4800000>; - qcom,cdc-mad-dmic-rate = <600000>; - }; - - wcd934x_cdc: tavil_codec { - compatible = "qcom,tavil-slim-pgd"; - elemental-addr = [00 01 50 02 17 02]; - - interrupt-parent = <&wcd9xxx_intc>; - interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 - 17 18 19 20 21 22 23 24 25 26 27 28 29 - 30 31>; - - qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; - - clock-names = "wcd_clk"; - clocks = <&clock_audio_lnbb AUDIO_PMIC_LNBB_CLK>; - - cdc-vdd-mic-bias-supply = <&pm2falcon_bob>; - qcom,cdc-vdd-mic-bias-voltage = <3300000 3300000>; - qcom,cdc-vdd-mic-bias-current = <30400>; - - qcom,cdc-static-supplies = "cdc-vdd-mic-bias"; - - qcom,cdc-micbias1-mv = <1800>; - qcom,cdc-micbias2-mv = <1800>; - qcom,cdc-micbias3-mv = <1800>; - qcom,cdc-micbias4-mv = <1800>; - - qcom,cdc-mclk-clk-rate = <9600000>; - qcom,cdc-slim-ifd = "tavil-slim-ifd"; - qcom,cdc-slim-ifd-elemental-addr = [00 00 50 02 17 02]; - qcom,cdc-dmic-sample-rate = <4800000>; - qcom,cdc-mad-dmic-rate = <600000>; - - qcom,wdsp-cmpnt-dev-name = "tavil_codec"; - - wcd_spi_0: wcd_spi { - compatible = "qcom,wcd-spi-v2"; - qcom,master-bus-num = <10>; - qcom,chip-select = <0>; - qcom,max-frequency = <24000000>; - qcom,mem-base-addr = <0x100000>; - }; - }; -}; - -&pm2falcon_3 { - pmic_analog_codec: analog-codec@f000 { - status = "disabled"; - compatible = "qcom,pmic-analog-codec"; - reg = <0xf000 0x200>; - interrupt-parent = <&spmi_bus>; - interrupts = <0x1 0xf0 0x0>, - <0x1 0xf0 0x1>, - <0x1 0xf0 0x2>, - <0x1 0xf0 0x3>, - <0x1 0xf0 0x4>, - <0x1 0xf0 0x5>, - <0x1 0xf0 0x6>, - <0x1 0xf0 0x7>; - interrupt-names = "spk_cnp_int", - "spk_clip_int", - "spk_ocp_int", - "ins_rem_det1", - "but_rel_det", - "but_press_det", - "ins_rem_det", - "mbhc_int"; - - cdc-vdda-cp-supply = <&pmfalcon_s4>; - qcom,cdc-vdda-cp-voltage = <1900000 2050000>; - qcom,cdc-vdda-cp-current = <50000>; - - cdc-vdd-pa-supply = <&pmfalcon_s4>; - qcom,cdc-vdd-pa-voltage = <2040000 2040000>; - qcom,cdc-vdd-pa-current = <260000>; - - cdc-vdd-mic-bias-supply = <&pm2falcon_l7>; - qcom,cdc-vdd-mic-bias-voltage = <3125000 3125000>; - qcom,cdc-vdd-mic-bias-current = <5000>; - - qcom,cdc-mclk-clk-rate = <9600000>; - - qcom,cdc-static-supplies = "cdc-vdda-cp", - "cdc-vdd-pa"; - - qcom,cdc-on-demand-supplies = "cdc-vdd-mic-bias"; - - cdc_pdm_gpios: cdc_pdm_pinctrl { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&cdc_pdm_gpios_active>; - pinctrl-1 = <&cdc_pdm_gpios_sleep>; - qcom,lpi-gpios; - }; - - cdc_comp_gpios: cdc_comp_pinctrl { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&cdc_comp_gpios_active>; - pinctrl-1 = <&cdc_comp_gpios_sleep>; - qcom,lpi-gpios; - }; - /* - * Not marking address @ as driver searches this child - * with name msm-dig-codec - */ - msm_digital_codec: msm-dig-codec { - compatible = "qcom,msm-digital-codec"; - reg = <0x152c0000 0x0>; - cdc_dmic_gpios: cdc_dmic_pinctrl { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&cdc_dmic12_gpios_active - &cdc_dmic34_gpios_active>; - pinctrl-1 = <&cdc_dmic12_gpios_sleep - &cdc_dmic34_gpios_sleep>; - qcom,lpi-gpios; - }; - }; - }; -}; - -&soc { - msm_sdw_codec: msm-sdw-codec@152c1000 { - status = "disabled"; - compatible = "qcom,msm-sdw-codec"; - reg = <0x152c1000 0x0>; - interrupts = <0 161 0>; - interrupt-names = "swr_master_irq"; - - cdc_sdw_gpios: sdw_clk_data_pinctrl { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&sdw_clk_active &sdw_data_active>; - pinctrl-1 = <&sdw_clk_sleep &sdw_data_sleep>; - }; - - wsa_spkr_en1: wsa_spkr_en1_pinctrl { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&spkr_1_sd_n_active>; - pinctrl-1 = <&spkr_1_sd_n_sleep>; - }; - - wsa_spkr_en2: wsa_spkr_en2_pinctrl { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&spkr_2_sd_n_active>; - pinctrl-1 = <&spkr_2_sd_n_sleep>; - }; - - swr_master { - compatible = "qcom,swr-wcd"; - #address-cells = <2>; - #size-cells = <0>; - - wsa881x_211_en: wsa881x_en@20170211 { - compatible = "qcom,wsa881x"; - reg = <0x0 0x20170211>; - qcom,spkr-sd-n-node = <&wsa_spkr_en1>; - }; - - wsa881x_212_en: wsa881x_en@20170212 { - compatible = "qcom,wsa881x"; - reg = <0x0 0x20170212>; - qcom,spkr-sd-n-node = <&wsa_spkr_en2>; - }; - - wsa881x_213_en: wsa881x_en@21170213 { - compatible = "qcom,wsa881x"; - reg = <0x0 0x21170213>; - qcom,spkr-sd-n-node = <&wsa_spkr_en1>; - }; - - wsa881x_214_en: wsa881x_en@21170214 { - compatible = "qcom,wsa881x"; - reg = <0x0 0x21170214>; - qcom,spkr-sd-n-node = <&wsa_spkr_en2>; - }; - }; - }; -}; - -&pmfalcon_gpios { - gpio@c200 { - status = "ok"; - qcom,mode = <1>; - qcom,pull = <5>; - qcom,vin-sel = <0>; - qcom,src-sel = <2>; - qcom,master-en = <1>; - qcom,out-strength = <2>; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-blsp.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-blsp.dtsi deleted file mode 100644 index c401d364409b..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-blsp.dtsi +++ /dev/null @@ -1,569 +0,0 @@ -/* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include "msmfalcon-pinctrl.dtsi" - -/ { - aliases { - spi1 = &spi_1; - spi2 = &spi_2; - spi3 = &spi_3; - spi4 = &spi_4; - spi5 = &spi_5; - spi6 = &spi_6; - spi7 = &spi_7; - spi8 = &spi_8; - i2c1 = &i2c_1; - i2c2 = &i2c_2; - i2c3 = &i2c_3; - i2c4 = &i2c_4; - i2c5 = &i2c_5; - i2c6 = &i2c_6; - i2c7 = &i2c_7; - i2c8 = &i2c_8; - }; -}; - - -&soc { - i2c_1: i2c@c175000 { /* BLSP1 QUP1 */ - compatible = "qcom,i2c-msm-v2"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xc175000 0x600>; - reg-names = "qup_phys_addr"; - interrupt-names = "qup_irq"; - interrupts = <0 95 0>; - dmas = <&dma_blsp1 4 64 0x20000020 0x20>, - <&dma_blsp1 5 32 0x20000020 0x20>; - dma-names = "tx", "rx"; - qcom,master-id = <86>; - qcom,clk-freq-out = <400000>; - qcom,clk-freq-in = <19200000>; - clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, - <&clock_gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; - pinctrl-names = "i2c_active", "i2c_sleep"; - pinctrl-0 = <&i2c_1_active>; - pinctrl-1 = <&i2c_1_sleep>; - status = "disabled"; - }; - - i2c_2: i2c@c176000 { /* BLSP1 QUP2 */ - compatible = "qcom,i2c-msm-v2"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xc176000 0x600>; - reg-names = "qup_phys_addr"; - interrupt-names = "qup_irq"; - interrupts = <0 96 0>; - dmas = <&dma_blsp1 6 64 0x20000020 0x20>, - <&dma_blsp1 7 32 0x20000020 0x20>; - dma-names = "tx", "rx"; - qcom,master-id = <86>; - qcom,clk-freq-out = <400000>; - qcom,clk-freq-in = <19200000>; - clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, - <&clock_gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - pinctrl-names = "i2c_active", "i2c_sleep"; - pinctrl-0 = <&i2c_2_active>; - pinctrl-1 = <&i2c_2_sleep>; - status = "disabled"; - }; - - i2c_3: i2c@c177000 { /* BLSP1 QUP3 */ - compatible = "qcom,i2c-msm-v2"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xc177000 0x600>; - reg-names = "qup_phys_addr"; - interrupt-names = "qup_irq"; - interrupts = <0 97 0>; - dmas = <&dma_blsp1 8 64 0x20000020 0x20>, - <&dma_blsp1 9 32 0x20000020 0x20>; - dma-names = "tx", "rx"; - qcom,master-id = <86>; - qcom,clk-freq-out = <400000>; - qcom,clk-freq-in = <19200000>; - clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, - <&clock_gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; - pinctrl-names = "i2c_active", "i2c_sleep"; - pinctrl-0 = <&i2c_3_active>; - pinctrl-1 = <&i2c_3_sleep>; - status = "disabled"; - }; - - i2c_4: i2c@c178000 { /* BLSP1 QUP4 */ - compatible = "qcom,i2c-msm-v2"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xc178000 0x600>; - reg-names = "qup_phys_addr"; - interrupt-names = "qup_irq"; - interrupts = <0 98 0>; - dmas = <&dma_blsp1 10 64 0x20000020 0x20>, - <&dma_blsp1 11 32 0x20000020 0x20>; - dma-names = "tx", "rx"; - qcom,master-id = <86>; - qcom,clk-freq-out = <400000>; - qcom,clk-freq-in = <19200000>; - clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, - <&clock_gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; - pinctrl-names = "i2c_active", "i2c_sleep"; - pinctrl-0 = <&i2c_4_active>; - pinctrl-1 = <&i2c_4_sleep>; - status = "disabled"; - }; - - i2c_5: i2c@c1b5000 { /* BLSP2 QUP1 */ - compatible = "qcom,i2c-msm-v2"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xc1b5000 0x600>; - reg-names = "qup_phys_addr"; - interrupt-names = "qup_irq"; - interrupts = <0 101 0>; - dmas = <&dma_blsp2 4 64 0x20000020 0x20>, - <&dma_blsp2 5 32 0x20000020 0x20>; - dma-names = "tx", "rx"; - qcom,master-id = <84>; - qcom,clk-freq-out = <400000>; - qcom,clk-freq-in = <19200000>; - clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, - <&clock_gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; - pinctrl-names = "i2c_active", "i2c_sleep"; - pinctrl-0 = <&i2c_5_active>; - pinctrl-1 = <&i2c_5_sleep>; - status = "disabled"; - }; - - i2c_6: i2c@c1b6000 { /* BLSP2 QUP2 */ - compatible = "qcom,i2c-msm-v2"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xc1b6000 0x600>; - reg-names = "qup_phys_addr"; - interrupt-names = "qup_irq"; - interrupts = <0 102 0>; - dmas = <&dma_blsp2 6 64 0x20000020 0x20>, - <&dma_blsp2 7 32 0x20000020 0x20>; - dma-names = "tx", "rx"; - qcom,master-id = <84>; - qcom,clk-freq-out = <400000>; - qcom,clk-freq-in = <19200000>; - clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, - <&clock_gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; - pinctrl-names = "i2c_active", "i2c_sleep"; - pinctrl-0 = <&i2c_6_active>; - pinctrl-1 = <&i2c_6_sleep>; - status = "disabled"; - }; - - i2c_7: i2c@c1b7000 { /* BLSP2 QUP3 */ - compatible = "qcom,i2c-msm-v2"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xc1b7000 0x600>; - reg-names = "qup_phys_addr"; - interrupt-names = "qup_irq"; - interrupts = <0 103 0>; - dmas = <&dma_blsp2 8 64 0x20000020 0x20>, - <&dma_blsp2 9 32 0x20000020 0x20>; - dma-names = "tx", "rx"; - qcom,master-id = <84>; - qcom,clk-freq-out = <400000>; - qcom,clk-freq-in = <19200000>; - clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, - <&clock_gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>; - pinctrl-names = "i2c_active", "i2c_sleep"; - pinctrl-0 = <&i2c_7_active>; - pinctrl-1 = <&i2c_7_sleep>; - status = "disabled"; - }; - - i2c_8: i2c@c1b8000 { /* BLSP2 QUP4 */ - compatible = "qcom,i2c-msm-v2"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xc1b8000 0x600>; - reg-names = "qup_phys_addr"; - interrupt-names = "qup_irq"; - interrupts = <0 104 0>; - dmas = <&dma_blsp2 10 64 0x20000020 0x20>, - <&dma_blsp2 11 32 0x20000020 0x20>; - dma-names = "tx", "rx"; - qcom,master-id = <84>; - qcom,clk-freq-out = <400000>; - qcom,clk-freq-in = <19200000>; - clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, - <&clock_gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>; - pinctrl-names = "i2c_active", "i2c_sleep"; - pinctrl-0 = <&i2c_8_active>; - pinctrl-1 = <&i2c_8_sleep>; - status = "disabled"; - }; - - spi_1: spi@c175000 { /* BLSP1 QUP1 */ - compatible = "qcom,spi-qup-v2"; - #address-cells = <1>; - #size-cells = <0>; - reg-names = "spi_physical", "spi_bam_physical"; - reg = <0xc175000 0x600>, - <0xc144000 0x1f000>; - interrupt-names = "spi_irq", "spi_bam_irq"; - interrupts = <0 95 0>, <0 238 0>; - spi-max-frequency = <50000000>; - qcom,use-bam; - qcom,ver-reg-exists; - qcom,bam-consumer-pipe-index = <4>; - qcom,bam-producer-pipe-index = <5>; - qcom,master-id = <86>; - qcom,use-pinctrl; - pinctrl-names = "spi_default", "spi_sleep"; - pinctrl-0 = <&spi_1_active>; - pinctrl-1 = <&spi_1_sleep>; - clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, - <&clock_gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>; - status = "disabled"; - }; - - spi_2: spi@c176000 { /* BLSP1 QUP2 */ - compatible = "qcom,spi-qup-v2"; - #address-cells = <1>; - #size-cells = <0>; - reg-names = "spi_physical", "spi_bam_physical"; - reg = <0xc176000 0x600>, - <0xc144000 0x1f000>; - interrupt-names = "spi_irq", "spi_bam_irq"; - interrupts = <0 96 0>, <0 238 0>; - spi-max-frequency = <50000000>; - qcom,use-bam; - qcom,ver-reg-exists; - qcom,bam-consumer-pipe-index = <6>; - qcom,bam-producer-pipe-index = <7>; - qcom,master-id = <86>; - qcom,use-pinctrl; - pinctrl-names = "spi_default", "spi_sleep"; - pinctrl-0 = <&spi_2_active>; - pinctrl-1 = <&spi_2_sleep>; - clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, - <&clock_gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>; - status = "disabled"; - }; - - spi_3: spi@c177000 { /* BLSP1 QUP3 */ - compatible = "qcom,spi-qup-v2"; - #address-cells = <1>; - #size-cells = <0>; - reg-names = "spi_physical", "spi_bam_physical"; - reg = <0xc177000 0x600>, - <0xc144000 0x1f000>; - interrupt-names = "spi_irq", "spi_bam_irq"; - interrupts = <0 97 0>, <0 238 0>; - spi-max-frequency = <50000000>; - qcom,use-bam; - qcom,ver-reg-exists; - qcom,bam-consumer-pipe-index = <8>; - qcom,bam-producer-pipe-index = <9>; - qcom,master-id = <86>; - qcom,use-pinctrl; - pinctrl-names = "spi_default", "spi_sleep"; - pinctrl-0 = <&spi_3_active>; - pinctrl-1 = <&spi_3_sleep>; - clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, - <&clock_gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; - status = "disabled"; - }; - - spi_4: spi@c178000 { /* BLSP1 QUP4 */ - compatible = "qcom,spi-qup-v2"; - #address-cells = <1>; - #size-cells = <0>; - reg-names = "spi_physical", "spi_bam_physical"; - reg = <0xc178000 0x600>, - <0xc144000 0x1f000>; - interrupt-names = "spi_irq", "spi_bam_irq"; - interrupts = <0 98 0>, <0 238 0>; - spi-max-frequency = <50000000>; - qcom,use-bam; - qcom,ver-reg-exists; - qcom,bam-consumer-pipe-index = <10>; - qcom,bam-producer-pipe-index = <11>; - qcom,master-id = <86>; - qcom,use-pinctrl; - pinctrl-names = "spi_default", "spi_sleep"; - pinctrl-0 = <&spi_4_active>; - pinctrl-1 = <&spi_4_sleep>; - clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, - <&clock_gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>; - status = "disabled"; - }; - - spi_5: spi@c1b5000 { /* BLSP2 QUP1 */ - compatible = "qcom,spi-qup-v2"; - #address-cells = <1>; - #size-cells = <0>; - reg-names = "spi_physical", "spi_bam_physical"; - reg = <0xc1b5000 0x600>, - <0xc184000 0x1f000>; - interrupt-names = "spi_irq", "spi_bam_irq"; - interrupts = <0 101 0>, <0 239 0>; - spi-max-frequency = <50000000>; - qcom,use-bam; - qcom,ver-reg-exists; - qcom,bam-consumer-pipe-index = <4>; - qcom,bam-producer-pipe-index = <5>; - qcom,master-id = <84>; - qcom,use-pinctrl; - pinctrl-names = "spi_default", "spi_sleep"; - pinctrl-0 = <&spi_5_active>; - pinctrl-1 = <&spi_5_sleep>; - clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, - <&clock_gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>; - status = "disabled"; - }; - - spi_6: spi@c1b6000 { /* BLSP2 QUP2 */ - compatible = "qcom,spi-qup-v2"; - #address-cells = <1>; - #size-cells = <0>; - reg-names = "spi_physical", "spi_bam_physical"; - reg = <0xc1b6000 0x600>, - <0xc184000 0x1f000>; - interrupt-names = "spi_irq", "spi_bam_irq"; - interrupts = <0 102 0>, <0 239 0>; - spi-max-frequency = <50000000>; - qcom,use-bam; - qcom,ver-reg-exists; - qcom,bam-consumer-pipe-index = <6>; - qcom,bam-producer-pipe-index = <7>; - qcom,master-id = <84>; - qcom,use-pinctrl; - pinctrl-names = "spi_default", "spi_sleep"; - pinctrl-0 = <&spi_6_active>; - pinctrl-1 = <&spi_6_sleep>; - clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, - <&clock_gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>; - status = "disabled"; - }; - - spi_7: spi@c1b7000 { /* BLSP2 QUP3 */ - compatible = "qcom,spi-qup-v2"; - #address-cells = <1>; - #size-cells = <0>; - reg-names = "spi_physical", "spi_bam_physical"; - reg = <0xc1b7000 0x600>, - <0xc184000 0x1f000>; - interrupt-names = "spi_irq", "spi_bam_irq"; - interrupts = <0 103 0>, <0 239 0>; - spi-max-frequency = <50000000>; - qcom,use-bam; - qcom,ver-reg-exists; - qcom,bam-consumer-pipe-index = <8>; - qcom,bam-producer-pipe-index = <9>; - qcom,master-id = <84>; - qcom,use-pinctrl; - pinctrl-names = "spi_default", "spi_sleep"; - pinctrl-0 = <&spi_7_active>; - pinctrl-1 = <&spi_7_sleep>; - clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, - <&clock_gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>; - status = "disabled"; - }; - - spi_8: spi@c1b8000 { /* BLSP2 QUP4 */ - compatible = "qcom,spi-qup-v2"; - #address-cells = <1>; - #size-cells = <0>; - reg-names = "spi_physical", "spi_bam_physical"; - reg = <0xc1b8000 0x600>, - <0xc184000 0x1f000>; - interrupt-names = "spi_irq", "spi_bam_irq"; - interrupts = <0 104 0>, <0 239 0>; - spi-max-frequency = <50000000>; - qcom,use-bam; - qcom,ver-reg-exists; - qcom,bam-consumer-pipe-index = <10>; - qcom,bam-producer-pipe-index = <11>; - qcom,master-id = <84>; - qcom,use-pinctrl; - pinctrl-names = "spi_default", "spi_sleep"; - pinctrl-0 = <&spi_8_active>; - pinctrl-1 = <&spi_8_sleep>; - clock-names = "iface_clk", "core_clk"; - clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, - <&clock_gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>; - status = "disabled"; - }; - - blsp1_uart1_hs: uart@c16f000 { /* BLSP1 UART1 */ - compatible = "qcom,msm-hsuart-v14"; - reg = <0xc16f000 0x200>, - <0xc144000 0x1f000>; - reg-names = "core_mem", "bam_mem"; - interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; - #address-cells = <0>; - interrupt-parent = <&blsp1_uart1_hs>; - interrupts = <0 1 2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xffffffff>; - interrupt-map = <0 &intc 0 0 107 0 - 1 &intc 0 0 238 0 - 2 &tlmm 1 0>; - - qcom,inject-rx-on-wakeup; - qcom,rx-char-to-inject = <0xfd>; - - qcom,bam-tx-ep-pipe-index = <0>; - qcom,bam-rx-ep-pipe-index = <1>; - qcom,master-id = <86>; - clock-names = "core_clk", "iface_clk"; - clocks = <&clock_gcc GCC_BLSP1_UART1_APPS_CLK>, - <&clock_gcc GCC_BLSP1_AHB_CLK>; - pinctrl-names = "sleep", "default"; - pinctrl-0 = <&blsp1_uart1_sleep>; - pinctrl-1 = <&blsp1_uart1_active>; - - qcom,msm-bus,name = "buart1"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <86 512 0 0>, - <86 512 500 800>; - status = "disabled"; - }; - - blsp1_uart2_hs: uart@c170000 { /* BLSP1 UART2 */ - compatible = "qcom,msm-hsuart-v14"; - reg = <0xc170000 0x200>, - <0xc144000 0x1f000>; - reg-names = "core_mem", "bam_mem"; - interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; - #address-cells = <0>; - interrupt-parent = <&blsp1_uart2_hs>; - interrupts = <0 1 2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xffffffff>; - interrupt-map = <0 &intc 0 0 108 0 - 1 &intc 0 0 238 0 - 2 &tlmm 5 0>; - - qcom,inject-rx-on-wakeup; - qcom,rx-char-to-inject = <0xfd>; - - qcom,bam-tx-ep-pipe-index = <2>; - qcom,bam-rx-ep-pipe-index = <3>; - qcom,master-id = <86>; - clock-names = "core_clk", "iface_clk"; - clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>, - <&clock_gcc GCC_BLSP1_AHB_CLK>; - pinctrl-names = "sleep", "default"; - pinctrl-0 = <&blsp1_uart2_sleep>; - pinctrl-1 = <&blsp1_uart2_active>; - - qcom,msm-bus,name = "buart2"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <86 512 0 0>, - <86 512 500 800>; - status = "disabled"; - }; - - blsp2_uart1_hs: uart@c1af000 { /* BLSP2 UART1 */ - compatible = "qcom,msm-hsuart-v14"; - reg = <0xc1af000 0x200>, - <0xc184000 0x1f000>; - reg-names = "core_mem", "bam_mem"; - interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; - #address-cells = <0>; - interrupt-parent = <&blsp2_uart1_hs>; - interrupts = <0 1 2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xffffffff>; - interrupt-map = <0 &intc 0 0 113 0 - 1 &intc 0 0 239 0 - 2 &tlmm 17 0>; - - qcom,inject-rx-on-wakeup; - qcom,rx-char-to-inject = <0xfd>; - - qcom,bam-tx-ep-pipe-index = <0>; - qcom,bam-rx-ep-pipe-index = <1>; - qcom,master-id = <84>; - clock-names = "core_clk", "iface_clk"; - clocks = <&clock_gcc GCC_BLSP2_UART1_APPS_CLK>, - <&clock_gcc GCC_BLSP2_AHB_CLK>; - pinctrl-names = "sleep", "default"; - pinctrl-0 = <&blsp2_uart1_sleep>; - pinctrl-1 = <&blsp2_uart1_active>; - - qcom,msm-bus,name = "buart3"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <84 512 0 0>, - <84 512 500 800>; - status = "disabled"; - }; - - blsp2_uart2_hs: uart@c1b0000 { /* BLSP2 UART2 */ - compatible = "qcom,msm-hsuart-v14"; - reg = <0xc1b0000 0x200>, - <0xc184000 0x1f000>; - reg-names = "core_mem", "bam_mem"; - interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; - #address-cells = <0>; - interrupt-parent = <&blsp2_uart2_hs>; - interrupts = <0 1 2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xffffffff>; - interrupt-map = <0 &intc 0 0 114 0 - 1 &intc 0 0 239 0 - 2 &tlmm 25 0>; - - qcom,inject-rx-on-wakeup; - qcom,rx-char-to-inject = <0xfd>; - - qcom,bam-tx-ep-pipe-index = <2>; - qcom,bam-rx-ep-pipe-index = <3>; - qcom,master-id = <84>; - clock-names = "core_clk", "iface_clk"; - clocks = <&clock_gcc GCC_BLSP2_UART2_APPS_CLK>, - <&clock_gcc GCC_BLSP2_AHB_CLK>; - pinctrl-names = "sleep", "default"; - pinctrl-0 = <&blsp2_uart2_sleep>; - pinctrl-1 = <&blsp2_uart2_active>; - - qcom,msm-bus,name = "buart4"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <84 512 0 0>, - <84 512 500 800>; - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-bus.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-bus.dtsi deleted file mode 100644 index 93c615639be9..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-bus.dtsi +++ /dev/null @@ -1,1284 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -&soc { - ad_hoc_bus: ad-hoc-bus { - /*Version = 14 */ - compatible = "qcom,msm-bus-device"; - reg = <0x1620000 0x20000>, - <0x1000000 0x80000>, - <0x1500000 0x10000>, - <0x1700000 0x20000>, - <0x17900000 0xE000>, - <0x1740000 0x10000>, - <0x1740000 0x10000>; - - reg-names = "snoc-base", "bimc-base", "cnoc-base", - "a2noc-base", "gnoc-base", "mmnoc-ahb-base", "mnoc-base"; - - /*Buses*/ - - fab_a2noc: fab-a2noc { - cell-id = ; - label = "fab-a2noc"; - qcom,fab-dev; - qcom,base-name = "a2noc-base"; - qcom,bypass-qos-prg; - qcom,bus-type = <1>; - qcom,qos-off = <4096>; - qcom,base-offset = <16384>; - clock-names = "bus_clk", "bus_a_clk"; - clocks = <&clock_rpmcc RPM_AGGR2_NOC_CLK>, - <&clock_rpmcc RPM_AGGR2_NOC_A_CLK>; - qcom,node-qos-clks { - clock-names = - "clk-ipa-clk", - "clk-sdcc1-ahb-no-rate", - "clk-sdcc2-ahb-no-rate", - "clk-blsp1-ahb-no-rate", - "clk-blsp2-ahb-no-rate"; - clocks = - <&clock_rpmcc RPM_IPA_CLK>, - <&clock_gcc GCC_SDCC1_AHB_CLK>, - <&clock_gcc GCC_SDCC2_AHB_CLK>, - <&clock_gcc GCC_BLSP1_AHB_CLK>, - <&clock_gcc GCC_BLSP2_AHB_CLK>; - }; - }; - - fab_bimc: fab-bimc { - cell-id = ; - label = "fab-bimc"; - qcom,fab-dev; - qcom,base-name = "bimc-base"; - qcom,bus-type = <2>; - qcom,bypass-qos-prg; - qcom,util-fact = <153>; - clock-names = "bus_clk", "bus_a_clk"; - clocks = <&clock_rpmcc BIMC_MSMBUS_CLK>, - <&clock_rpmcc BIMC_MSMBUS_A_CLK>; - }; - - fab_cnoc: fab-cnoc { - cell-id = ; - label = "fab-cnoc"; - qcom,fab-dev; - qcom,base-name = "cnoc-base"; - qcom,bypass-qos-prg; - qcom,bus-type = <1>; - clock-names = "bus_clk", "bus_a_clk"; - clocks = <&clock_rpmcc CNOC_MSMBUS_CLK>, - <&clock_rpmcc CNOC_MSMBUS_A_CLK>; - }; - - fab_gnoc: fab-gnoc { - cell-id = ; - label = "fab-gnoc"; - qcom,virt-dev; - qcom,base-name = "gnoc-base"; - qcom,bypass-qos-prg; - }; - - fab_mnoc: fab-mnoc { - cell-id = ; - label = "fab-mnoc"; - qcom,fab-dev; - qcom,base-name = "mnoc-base"; - qcom,bypass-qos-prg; - qcom,bus-type = <1>; - qcom,qos-off = <4096>; - qcom,base-offset = <20480>; - qcom,util-fact = <153>; - clock-names = "bus_clk", "bus_a_clk"; - clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, - <&clock_rpmcc MMSSNOC_AXI_A_CLK>; - clk-camss-ahb-no-rate-supply = - <&gdsc_camss_top>; - clk-video-ahb-no-rate-supply = - <&gdsc_venus>; - clk-video-axi-no-rate-supply = - <&gdsc_venus>; - qcom,node-qos-clks { - clock-names = - "clk-mmssnoc-axi-no-rate", - "clk-noc-cfg-ahb-no-rate", - "clk-mnoc-ahb-no-rate", - "clk-camss-ahb-no-rate", - "clk-video-ahb-no-rate", - "clk-video-axi-no-rate"; - clocks = - <&clock_rpmcc MMSSNOC_AXI_CLK>, - <&clock_gcc GCC_MMSS_NOC_CFG_AHB_CLK>, - <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_AHB_CLK>, - <&clock_mmss MMSS_VIDEO_AHB_CLK>, - <&clock_mmss MMSS_VIDEO_AXI_CLK>; - }; - }; - - fab_snoc: fab-snoc { - cell-id = ; - label = "fab-snoc"; - qcom,fab-dev; - qcom,base-name = "snoc-base"; - qcom,bypass-qos-prg; - qcom,bus-type = <1>; - qcom,qos-off = <4096>; - qcom,base-offset = <24576>; - clock-names = "bus_clk", "bus_a_clk"; - clocks = <&clock_rpmcc SNOC_MSMBUS_CLK>, - <&clock_rpmcc SNOC_MSMBUS_A_CLK>; - }; - - fab_mnoc_ahb: fab-mnoc-ahb { - cell-id = ; - label = "fab-mnoc-ahb"; - qcom,fab-dev; - qcom,base-name = "mmnoc-ahb-base"; - qcom,bypass-qos-prg; - qcom,setrate-only-clk; - qcom,bus-type = <1>; - clock-names = "bus_clk", "bus_a_clk"; - clocks = <&clock_mmss AHB_CLK_SRC >, - <&clock_mmss AHB_CLK_SRC>; - }; - - /*Masters*/ - - mas_ipa: mas-ipa { - cell-id = ; - label = "mas-ipa"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,qport = <3>; - qcom,qos-mode = "fixed"; - qcom,connections = <&slv_a2noc_snoc>; - qcom,prio1 = <1>; - qcom,prio0 = <1>; - qcom,bus-dev = <&fab_a2noc>; - qcom,mas-rpm-id = ; - }; - - mas_cnoc_a2noc: mas-cnoc-a2noc { - cell-id = ; - label = "mas-cnoc-a2noc"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,connections = <&slv_a2noc_snoc>; - qcom,bus-dev = <&fab_a2noc>; - qcom,mas-rpm-id = ; - qcom,blacklist = <&slv_snoc_cnoc>; - }; - - mas_sdcc_1: mas-sdcc-1 { - cell-id = ; - label = "mas-sdcc-1"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,connections = <&slv_a2noc_snoc>; - qcom,bus-dev = <&fab_a2noc>; - qcom,mas-rpm-id = ; - }; - - mas_sdcc_2: mas-sdcc-2 { - cell-id = ; - label = "mas-sdcc-2"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,connections = <&slv_a2noc_snoc>; - qcom,bus-dev = <&fab_a2noc>; - qcom,mas-rpm-id = ; - }; - - mas_blsp_1: mas-blsp-1 { - cell-id = ; - label = "mas-blsp-1"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,connections = <&slv_a2noc_snoc>; - qcom,bus-dev = <&fab_a2noc>; - qcom,mas-rpm-id = ; - }; - - mas_blsp_2: mas-blsp-2 { - cell-id = ; - label = "mas-blsp-2"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,connections = <&slv_a2noc_snoc>; - qcom,bus-dev = <&fab_a2noc>; - qcom,mas-rpm-id = ; - }; - - mas_ufs: mas-ufs { - cell-id = ; - label = "mas-ufs"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,qport = <4>; - qcom,qos-mode = "fixed"; - qcom,connections = <&slv_a2noc_snoc>; - qcom,prio1 = <1>; - qcom,prio0 = <1>; - qcom,bus-dev = <&fab_a2noc>; - qcom,mas-rpm-id = ; - }; - - mas_usb_hs: mas-usb-hs { - cell-id = ; - label = "mas-usb-hs"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,qport = <1>; - qcom,qos-mode = "fixed"; - qcom,connections = <&slv_a2noc_snoc>; - qcom,prio1 = <1>; - qcom,prio0 = <1>; - qcom,bus-dev = <&fab_a2noc>; - qcom,mas-rpm-id = ; - }; - - mas_usb3: mas-usb3 { - cell-id = ; - label = "mas-usb3"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,qport = <2>; - qcom,qos-mode = "fixed"; - qcom,connections = <&slv_a2noc_snoc>; - qcom,prio1 = <1>; - qcom,prio0 = <1>; - qcom,bus-dev = <&fab_a2noc>; - qcom,mas-rpm-id = ; - }; - - mas_crypto_c0: mas-crypto-c0 { - cell-id = ; - label = "mas-crypto-c0"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,qport = <11>; - qcom,qos-mode = "fixed"; - qcom,connections = <&slv_a2noc_snoc>; - qcom,prio1 = <1>; - qcom,prio0 = <1>; - qcom,bus-dev = <&fab_a2noc>; - qcom,mas-rpm-id = ; - }; - - mas_gnoc_bimc: mas-gnoc-bimc { - cell-id = ; - label = "mas-gnoc-bimc"; - qcom,buswidth = <4>; - qcom,agg-ports = <2>; - qcom,ap-owned; - qcom,qport = <0>; - qcom,qos-mode = "fixed"; - qcom,connections = <&slv_ebi>; - qcom,prio-lvl = <0>; - qcom,prio-rd = <0>; - qcom,prio-wr = <0>; - qcom,bus-dev = <&fab_bimc>; - qcom,mas-rpm-id = ; - }; - - mas_oxili: mas-oxili { - cell-id = ; - label = "mas-oxili"; - qcom,buswidth = <4>; - qcom,agg-ports = <2>; - qcom,ap-owned; - qcom,qport = <1>; - qcom,qos-mode = "bypass"; - qcom,connections = <&slv_hmss_l3 - &slv_ebi &slv_bimc_snoc>; - qcom,bus-dev = <&fab_bimc>; - qcom,mas-rpm-id = ; - }; - - mas_mnoc_bimc: mas-mnoc-bimc { - cell-id = ; - label = "mas-mnoc-bimc"; - qcom,buswidth = <4>; - qcom,agg-ports = <2>; - qcom,ap-owned; - qcom,qport = <2>; - qcom,qos-mode = "bypass"; - qcom,connections = <&slv_hmss_l3 - &slv_ebi &slv_bimc_snoc>; - qcom,bus-dev = <&fab_bimc>; - qcom,mas-rpm-id = ; - }; - - mas_snoc_bimc: mas-snoc-bimc { - cell-id = ; - label = "mas-snoc-bimc"; - qcom,buswidth = <4>; - qcom,agg-ports = <2>; - qcom,connections = <&slv_hmss_l3 &slv_ebi>; - qcom,bus-dev = <&fab_bimc>; - qcom,mas-rpm-id = ; - }; - - mas_pimem: mas-pimem { - cell-id = ; - label = "mas-pimem"; - qcom,buswidth = <4>; - qcom,agg-ports = <2>; - qcom,ap-owned; - qcom,qport = <4>; - qcom,qos-mode = "fixed"; - qcom,connections = <&slv_hmss_l3 &slv_ebi>; - qcom,prio-lvl = <0>; - qcom,prio-rd = <0>; - qcom,prio-wr = <0>; - qcom,bus-dev = <&fab_bimc>; - qcom,mas-rpm-id = ; - }; - - mas_snoc_cnoc: mas-snoc-cnoc { - cell-id = ; - label = "mas-snoc-cnoc"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,connections = <&slv_clk_ctl - &slv_qdss_cfg &slv_qm_cfg - &slv_srvc_cnoc &slv_ufs_cfg - &slv_tcsr &slv_a2noc_smmu_cfg - &slv_snoc_cfg &slv_tlmm_south - &slv_mpm &slv_cnoc_mnoc_mmss_cfg - &slv_sdcc_2 &slv_sdcc_1 - &slv_spdm &slv_pmic_arb - &slv_prng &slv_mss_cfg - &slv_gpuss_cfg &slv_imem_cfg - &slv_usb3_0 &slv_a2noc_cfg - &slv_tlmm_north &slv_usb_hs - &slv_pdm &slv_tlmm_center - &slv_ahb2phy &slv_blsp_2 - &slv_blsp_1 &slv_pimem_cfg - &slv_glm &slv_message_ram - &slv_bimc_cfg &slv_cnoc_mnoc_cfg>; - qcom,bus-dev = <&fab_cnoc>; - qcom,mas-rpm-id = ; - }; - - mas_qdss_dap: mas-qdss-dap { - cell-id = ; - label = "mas-qdss-dap"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,connections = <&slv_clk_ctl - &slv_qdss_cfg &slv_qm_cfg - &slv_srvc_cnoc &slv_ufs_cfg - &slv_tcsr &slv_a2noc_smmu_cfg - &slv_snoc_cfg &slv_tlmm_south - &slv_mpm &slv_cnoc_mnoc_mmss_cfg - &slv_sdcc_2 &slv_sdcc_1 - &slv_spdm &slv_pmic_arb - &slv_prng &slv_mss_cfg - &slv_gpuss_cfg &slv_imem_cfg - &slv_usb3_0 &slv_a2noc_cfg - &slv_tlmm_north &slv_usb_hs - &slv_pdm &slv_tlmm_center - &slv_ahb2phy &slv_blsp_2 - &slv_blsp_1 &slv_pimem_cfg - &slv_glm &slv_message_ram - &slv_cnoc_a2noc &slv_bimc_cfg - &slv_cnoc_mnoc_cfg>; - qcom,bus-dev = <&fab_cnoc>; - qcom,mas-rpm-id = ; - }; - - mas_apps_proc: mas-apps-proc { - cell-id = ; - label = "mas-apps-proc"; - qcom,buswidth = <16>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,connections = <&slv_gnoc_snoc &slv_gnoc_bimc>; - qcom,bus-dev = <&fab_gnoc>; - qcom,mas-rpm-id = ; - }; - - mas_cnoc_mnoc_mmss_cfg: mas-cnoc-mnoc-mmss-cfg { - cell-id = ; - label = "mas-cnoc-mnoc-mmss-cfg"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,connections = <&slv_venus_throttle_cfg - &slv_venus_cfg &slv_camera_throttle_cfg - &slv_smmu_cfg &slv_camera_cfg &slv_csi_phy_cfg - &slv_display_throttle_cfg &slv_display_cfg - &slv_mmss_clk_cfg &slv_mnoc_mpu_cfg - &slv_misc_cfg &slv_mmss_clk_xpu_cfg>; - qcom,bus-dev = <&fab_mnoc_ahb>; - qcom,mas-rpm-id = ; - }; - - mas_cnoc_mnoc_cfg: mas-cnoc-mnoc-cfg { - cell-id = ; - label = "mas-cnoc-mnoc-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,connections = <&slv_srvc_mnoc>; - qcom,bus-dev = <&fab_mnoc_ahb>; - qcom,mas-rpm-id = ; - }; - - mas_cpp: mas-cpp { - cell-id = ; - label = "mas-cpp"; - qcom,buswidth = <16>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,qport = <4>; - qcom,qos-mode = "bypass"; - qcom,connections = <&slv_mnoc_bimc>; - qcom,bus-dev = <&fab_mnoc>; - qcom,mas-rpm-id = ; - }; - - mas_jpeg: mas-jpeg { - cell-id = ; - label = "mas-jpeg"; - qcom,buswidth = <16>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,qport = <6>; - qcom,qos-mode = "bypass"; - qcom,connections = <&slv_mnoc_bimc>; - qcom,bus-dev = <&fab_mnoc>; - qcom,mas-rpm-id = ; - }; - - mas_mdp_p0: mas-mdp-p0 { - cell-id = ; - label = "mas-mdp-p0"; - qcom,buswidth = <16>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,qport = <0>; - qcom,qos-mode = "bypass"; - qcom,connections = <&slv_mnoc_bimc>; - qcom,bus-dev = <&fab_mnoc>; - qcom,vrail-comp = <50>; - qcom,mas-rpm-id = ; - clk-mdss-axi-no-rate-supply = - <&gdsc_mdss>; - clk-mdss-ahb-no-rate-supply = - <&gdsc_mdss>; - qcom,node-qos-clks { - clock-names = - "clk-mdss-ahb-no-rate", - "clk-mdss-axi-no-rate"; - clocks = - <&clock_mmss MMSS_MDSS_AHB_CLK>, - <&clock_mmss MMSS_MDSS_AXI_CLK>; - }; - }; - - mas_mdp_p1: mas-mdp-p1 { - cell-id = ; - label = "mas-mdp-p1"; - qcom,buswidth = <16>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,qport = <1>; - qcom,qos-mode = "bypass"; - qcom,connections = <&slv_mnoc_bimc>; - qcom,bus-dev = <&fab_mnoc>; - qcom,vrail-comp = <50>; - qcom,mas-rpm-id = ; - }; - - mas_venus: mas-venus { - cell-id = ; - label = "mas-venus"; - qcom,buswidth = <16>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,qport = <2>; - qcom,qos-mode = "bypass"; - qcom,connections = <&slv_mnoc_bimc>; - qcom,bus-dev = <&fab_mnoc>; - qcom,mas-rpm-id = ; - }; - - mas_vfe: mas-vfe { - cell-id = ; - label = "mas-vfe"; - qcom,buswidth = <16>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,qport = <5>; - qcom,qos-mode = "bypass"; - qcom,connections = <&slv_mnoc_bimc>; - qcom,bus-dev = <&fab_mnoc>; - qcom,mas-rpm-id = ; - }; - - mas_qdss_etr: mas-qdss-etr { - cell-id = ; - label = "mas-qdss-etr"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,qport = <1>; - qcom,qos-mode = "fixed"; - qcom,connections = <&slv_pimem - &slv_imem &slv_snoc_cnoc - &slv_snoc_bimc>; - qcom,prio1 = <1>; - qcom,prio0 = <1>; - qcom,bus-dev = <&fab_snoc>; - qcom,mas-rpm-id = ; - }; - - mas_qdss_bam: mas-qdss-bam { - cell-id = ; - label = "mas-qdss-bam"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,qport = <0>; - qcom,qos-mode = "fixed"; - qcom,connections = <&slv_pimem - &slv_imem &slv_snoc_cnoc - &slv_snoc_bimc>; - qcom,prio1 = <1>; - qcom,prio0 = <1>; - qcom,bus-dev = <&fab_snoc>; - qcom,mas-rpm-id = ; - }; - - mas_snoc_cfg: mas-snoc-cfg { - cell-id = ; - label = "mas-snoc-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,connections = <&slv_srvc_snoc>; - qcom,bus-dev = <&fab_snoc>; - qcom,mas-rpm-id = ; - }; - - mas_bimc_snoc: mas-bimc-snoc { - cell-id = ; - label = "mas-bimc-snoc"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,connections = <&slv_pimem - &slv_ipa &slv_qdss_stm - &slv_lpass &slv_hmss - &slv_cdsp &slv_snoc_cnoc - &slv_wlan &slv_imem>; - qcom,bus-dev = <&fab_snoc>; - qcom,mas-rpm-id = ; - }; - - mas_a2noc_snoc: mas-a2noc-snoc { - cell-id = ; - label = "mas-a2noc-snoc"; - qcom,buswidth = <16>; - qcom,agg-ports = <1>; - qcom,connections = <&slv_pimem - &slv_ipa &slv_qdss_stm - &slv_lpass &slv_hmss - &slv_snoc_bimc &slv_cdsp - &slv_snoc_cnoc &slv_wlan - &slv_imem>; - qcom,bus-dev = <&fab_snoc>; - qcom,mas-rpm-id = ; - }; - - /*Internal nodes*/ - - /*Slaves*/ - - slv_a2noc_snoc:slv-a2noc-snoc { - cell-id = ; - label = "slv-a2noc-snoc"; - qcom,buswidth = <16>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_a2noc>; - qcom,connections = <&mas_a2noc_snoc>; - qcom,slv-rpm-id = ; - }; - - slv_ebi:slv-ebi { - cell-id = ; - label = "slv-ebi"; - qcom,buswidth = <4>; - qcom,agg-ports = <2>; - qcom,bus-dev = <&fab_bimc>; - qcom,slv-rpm-id = ; - }; - - slv_hmss_l3:slv-hmss-l3 { - cell-id = ; - label = "slv-hmss-l3"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_bimc>; - qcom,slv-rpm-id = ; - }; - - slv_bimc_snoc:slv-bimc-snoc { - cell-id = ; - label = "slv-bimc-snoc"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_bimc>; - qcom,connections = <&mas_bimc_snoc>; - qcom,slv-rpm-id = ; - }; - - slv_cnoc_a2noc:slv-cnoc-a2noc { - cell-id = ; - label = "slv-cnoc-a2noc"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,connections = <&mas_cnoc_a2noc>; - qcom,slv-rpm-id = ; - }; - - slv_mpm:slv-mpm { - cell-id = ; - label = "slv-mpm"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_pmic_arb:slv-pmic-arb { - cell-id = ; - label = "slv-pmic-arb"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_tlmm_north:slv-tlmm-north { - cell-id = ; - label = "slv-tlmm-north"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_tcsr:slv-tcsr { - cell-id = ; - label = "slv-tcsr"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_pimem_cfg:slv-pimem-cfg { - cell-id = ; - label = "slv-pimem-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_imem_cfg:slv-imem-cfg { - cell-id = ; - label = "slv-imem-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_message_ram:slv-message-ram { - cell-id = ; - label = "slv-message-ram"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_glm:slv-glm { - cell-id = ; - label = "slv-glm"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_bimc_cfg:slv-bimc-cfg { - cell-id = ; - label = "slv-bimc-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_prng:slv-prng { - cell-id = ; - label = "slv-prng"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_spdm:slv-spdm { - cell-id = ; - label = "slv-spdm"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_qdss_cfg:slv-qdss-cfg { - cell-id = ; - label = "slv-qdss-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_cnoc_mnoc_cfg:slv-cnoc-mnoc-cfg { - cell-id = ; - label = "slv-cnoc-mnoc-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,connections = <&mas_cnoc_mnoc_cfg>; - qcom,slv-rpm-id = ; - }; - - slv_snoc_cfg:slv-snoc-cfg { - cell-id = ; - label = "slv-snoc-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_qm_cfg:slv-qm-cfg { - cell-id = ; - label = "slv-qm-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_clk_ctl:slv-clk-ctl { - cell-id = ; - label = "slv-clk-ctl"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_mss_cfg:slv-mss-cfg { - cell-id = ; - label = "slv-mss-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_tlmm_south:slv-tlmm-south { - cell-id = ; - label = "slv-tlmm-south"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_ufs_cfg:slv-ufs-cfg { - cell-id = ; - label = "slv-ufs-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_a2noc_cfg:slv-a2noc-cfg { - cell-id = ; - label = "slv-a2noc-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_a2noc_smmu_cfg:slv-a2noc-smmu-cfg { - cell-id = ; - label = "slv-a2noc-smmu-cfg"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_gpuss_cfg:slv-gpuss-cfg { - cell-id = ; - label = "slv-gpuss-cfg"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_ahb2phy:slv-ahb2phy { - cell-id = ; - label = "slv-ahb2phy"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_blsp_1:slv-blsp-1 { - cell-id = ; - label = "slv-blsp-1"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_sdcc_1:slv-sdcc-1 { - cell-id = ; - label = "slv-sdcc-1"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_sdcc_2:slv-sdcc-2 { - cell-id = ; - label = "slv-sdcc-2"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_tlmm_center:slv-tlmm-center { - cell-id = ; - label = "slv-tlmm-center"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_blsp_2:slv-blsp-2 { - cell-id = ; - label = "slv-blsp-2"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_pdm:slv-pdm { - cell-id = ; - label = "slv-pdm"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_cnoc_mnoc_mmss_cfg:slv-cnoc-mnoc-mmss-cfg { - cell-id = ; - label = "slv-cnoc-mnoc-mmss-cfg"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,connections = <&mas_cnoc_mnoc_mmss_cfg>; - qcom,slv-rpm-id = ; - }; - - slv_usb_hs:slv-usb-hs { - cell-id = ; - label = "slv-usb-hs"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_usb3_0:slv-usb3-0 { - cell-id = ; - label = "slv-usb3-0"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_srvc_cnoc:slv-srvc-cnoc { - cell-id = ; - label = "slv-srvc-cnoc"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_cnoc>; - qcom,slv-rpm-id = ; - }; - - - slv_gnoc_bimc:slv-gnoc-bimc { - cell-id = ; - label = "slv-gnoc-bimc"; - qcom,buswidth = <16>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_gnoc>; - qcom,connections = <&mas_gnoc_bimc>; - qcom,slv-rpm-id = ; - }; - - slv_gnoc_snoc:slv-gnoc-snoc { - cell-id = ; - label = "slv-gnoc-snoc"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_gnoc>; - qcom,connections = <&mas_gnoc_snoc>; - qcom,slv-rpm-id = ; - }; - - mas_gnoc_snoc: mas-gnoc-snoc { - cell-id = ; - label = "mas-gnoc-snoc"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,connections = <&slv_pimem - &slv_ipa &slv_qdss_stm - &slv_lpass &slv_hmss - &slv_cdsp &slv_snoc_cnoc - &slv_wlan &slv_imem>; - qcom,bus-dev = <&fab_snoc>; - qcom,mas-rpm-id = ; - }; - - slv_camera_cfg:slv-camera-cfg { - cell-id = ; - label = "slv-camera-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_mnoc_ahb>; - qcom,slv-rpm-id = ; - }; - - slv_camera_throttle_cfg:slv-camera-throttle-cfg { - cell-id = ; - label = "slv-camera-throttle-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_mnoc_ahb>; - qcom,slv-rpm-id = ; - }; - - slv_misc_cfg:slv-misc-cfg { - cell-id = ; - label = "slv-misc-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_mnoc_ahb>; - qcom,slv-rpm-id = ; - }; - - slv_venus_throttle_cfg:slv-venus-throttle-cfg { - cell-id = ; - label = "slv-venus-throttle-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_mnoc_ahb>; - qcom,slv-rpm-id = ; - }; - - slv_venus_cfg:slv-venus-cfg { - cell-id = ; - label = "slv-venus-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_mnoc_ahb>; - qcom,slv-rpm-id = ; - }; - - slv_mmss_clk_xpu_cfg:slv-mmss-clk-xpu-cfg { - cell-id = ; - label = "slv-mmss-clk-xpu-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_mnoc_ahb>; - qcom,slv-rpm-id = ; - }; - - slv_mmss_clk_cfg:slv-mmss-clk-cfg { - cell-id = ; - label = "slv-mmss-clk-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_mnoc_ahb>; - qcom,slv-rpm-id = ; - }; - - slv_mnoc_mpu_cfg:slv-mnoc-mpu-cfg { - cell-id = ; - label = "slv-mnoc-mpu-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_mnoc_ahb>; - qcom,slv-rpm-id = ; - }; - - slv_display_cfg:slv-display-cfg { - cell-id = ; - label = "slv-display-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_mnoc_ahb>; - qcom,slv-rpm-id = ; - }; - - slv_csi_phy_cfg:slv-csi-phy-cfg { - cell-id = ; - label = "slv-csi-phy-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_mnoc_ahb>; - qcom,slv-rpm-id = ; - }; - - slv_display_throttle_cfg:slv-display-throttle-cfg { - cell-id = ; - label = "slv-display-throttle-cfg"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_mnoc_ahb>; - qcom,slv-rpm-id = ; - }; - - slv_smmu_cfg:slv-smmu-cfg { - cell-id = ; - label = "slv-smmu-cfg"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_mnoc_ahb>; - qcom,slv-rpm-id = ; - }; - - slv_mnoc_bimc:slv-mnoc-bimc { - cell-id = ; - label = "slv-mnoc-bimc"; - qcom,buswidth = <16>; - qcom,agg-ports = <2>; - qcom,ap-owned; - qcom,bus-dev = <&fab_mnoc>; - qcom,connections = <&mas_mnoc_bimc>; - qcom,slv-rpm-id = ; - qcom,enable-only-clk; - clock-names = "node_clk"; - clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>; - }; - - slv_srvc_mnoc:slv-srvc-mnoc { - cell-id = ; - label = "slv-srvc-mnoc"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_mnoc_ahb>; - qcom,slv-rpm-id = ; - }; - - slv_hmss:slv-hmss { - cell-id = ; - label = "slv-hmss"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_snoc>; - qcom,slv-rpm-id = ; - }; - - slv_lpass:slv-lpass { - cell-id = ; - label = "slv-lpass"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_snoc>; - qcom,slv-rpm-id = ; - }; - - slv_wlan:slv-wlan { - cell-id = ; - label = "slv-wlan"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_snoc>; - qcom,slv-rpm-id = ; - }; - - slv_cdsp:slv-cdsp { - cell-id = ; - label = "slv-cdsp"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_snoc>; - qcom,slv-rpm-id = ; - }; - - slv_ipa:slv-ipa { - cell-id = ; - label = "slv-ipa"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,ap-owned; - qcom,bus-dev = <&fab_snoc>; - qcom,slv-rpm-id = ; - }; - - slv_snoc_bimc:slv-snoc-bimc { - cell-id = ; - label = "slv-snoc-bimc"; - qcom,buswidth = <16>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_snoc>; - qcom,connections = <&mas_snoc_bimc>; - qcom,slv-rpm-id = ; - }; - - slv_snoc_cnoc:slv-snoc-cnoc { - cell-id = ; - label = "slv-snoc-cnoc"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_snoc>; - qcom,connections = <&mas_snoc_cnoc>; - qcom,slv-rpm-id = ; - }; - - slv_imem:slv-imem { - cell-id = ; - label = "slv-imem"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_snoc>; - qcom,slv-rpm-id = ; - }; - - slv_pimem:slv-pimem { - cell-id = ; - label = "slv-pimem"; - qcom,buswidth = <8>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_snoc>; - qcom,slv-rpm-id = ; - }; - - slv_qdss_stm:slv-qdss-stm { - cell-id = ; - label = "slv-qdss-stm"; - qcom,buswidth = <4>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_snoc>; - qcom,slv-rpm-id = ; - }; - - slv_srvc_snoc:slv-srvc-snoc { - cell-id = ; - label = "slv-srvc-snoc"; - qcom,buswidth = <16>; - qcom,agg-ports = <1>; - qcom,bus-dev = <&fab_snoc>; - qcom,slv-rpm-id = ; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-camera-sensor-cdp.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-camera-sensor-cdp.dtsi deleted file mode 100644 index 63528e23160a..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-camera-sensor-cdp.dtsi +++ /dev/null @@ -1,384 +0,0 @@ -/* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -&soc { - led_flash0: qcom,camera-flash@0 { - cell-index = <0>; - compatible = "qcom,camera-flash"; - qcom,flash-source = <&pm2falcon_flash0 &pm2falcon_flash1>; - qcom,torch-source = <&pm2falcon_torch0 &pm2falcon_torch1>; - qcom,switch-source = <&pm2falcon_switch0>; - status = "ok"; - }; - - led_flash1: qcom,camera-flash@1 { - cell-index = <1>; - compatible = "qcom,camera-flash"; - qcom,flash-source = <&pm2falcon_flash2>; - qcom,torch-source = <&pm2falcon_torch2>; - qcom,switch-source = <&pm2falcon_switch1>; - status = "ok"; - }; -}; - -&cci { - actuator0: qcom,actuator@0 { - cell-index = <0>; - reg = <0x0>; - compatible = "qcom,actuator"; - qcom,cci-master = <0>; - gpios = <&tlmm 50 0>; - qcom,gpio-vaf = <0>; - qcom,gpio-req-tbl-num = <0>; - qcom,gpio-req-tbl-flags = <0>; - qcom,gpio-req-tbl-label = "CAM_VAF"; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_actuator_vaf_active>; - pinctrl-1 = <&cam_actuator_vaf_suspend>; - }; - - actuator1: qcom,actuator@1 { - cell-index = <1>; - reg = <0x1>; - compatible = "qcom,actuator"; - qcom,cci-master = <1>; - gpios = <&tlmm 50 0>; - qcom,gpio-vaf = <0>; - qcom,gpio-req-tbl-num = <0>; - qcom,gpio-req-tbl-flags = <0>; - qcom,gpio-req-tbl-label = "CAM_VAF"; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_actuator_vaf_active>; - pinctrl-1 = <&cam_actuator_vaf_suspend>; - }; - - actuator2: qcom,actuator@2 { - cell-index = <2>; - reg = <0x2>; - compatible = "qcom,actuator"; - qcom,cci-master = <1>; - gpios = <&tlmm 50 0>; - qcom,gpio-vaf = <0>; - qcom,gpio-req-tbl-num = <0>; - qcom,gpio-req-tbl-flags = <0>; - qcom,gpio-req-tbl-label = "CAM_VAF"; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_actuator_vaf_active>; - pinctrl-1 = <&cam_actuator_vaf_suspend>; - }; - - ois0: qcom,ois@0 { - cell-index = <0>; - reg = <0x0>; - compatible = "qcom,ois"; - qcom,cci-master = <0>; - gpios = <&tlmm 50 0>; - qcom,gpio-vaf = <0>; - qcom,gpio-req-tbl-num = <0>; - qcom,gpio-req-tbl-flags = <0>; - qcom,gpio-req-tbl-label = "CAM_VAF"; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_actuator_vaf_active>; - pinctrl-1 = <&cam_actuator_vaf_suspend>; - status = "disabled"; - }; - - eeprom0: qcom,eeprom@0 { - cell-index = <0>; - reg = <0>; - compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; - qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; - qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; - qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; - qcom,cam-vreg-op-mode = <105000 80000 105000>; - qcom,gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk0_active - &cam_sensor_rear_active - &cam_actuator_vaf_active>; - pinctrl-1 = <&cam_sensor_mclk0_suspend - &cam_sensor_rear_suspend - &cam_actuator_vaf_suspend>; - gpios = <&tlmm 32 0>, - <&tlmm 46 0>, - <&pm2falcon_gpios 4 0>, - <&tlmm 51 0>, - <&tlmm 50 0>; - qcom,gpio-reset = <1>; - qcom,gpio-vdig = <2>; - qcom,gpio-vana = <3>; - qcom,gpio-vaf = <4>; - qcom,gpio-req-tbl-num = <0 1 2 3 4>; - qcom,gpio-req-tbl-flags = <1 0 0 0 0>; - qcom,gpio-req-tbl-label = "CAMIF_MCLK0", - "CAM_RESET0", - "CAM_VDIG", - "CAM_VANA", - "CAM_VAF"; - qcom,sensor-position = <0>; - qcom,sensor-mode = <0>; - qcom,cci-master = <0>; - status = "ok"; - clocks = <&clock_mmss MCLK0_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_MCLK0_CLK>; - clock-names = "cam_src_clk", "cam_clk"; - qcom,clock-rates = <24000000 0>; - }; - - eeprom1: qcom,eeprom@1 { - cell-index = <1>; - reg = <0x1>; - compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; - qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; - qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; - qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; - qcom,cam-vreg-op-mode = <105000 80000 105000>; - qcom,gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk2_active - &cam_sensor_rear2_active>; - pinctrl-1 = <&cam_sensor_mclk2_suspend - &cam_sensor_rear2_suspend>; - gpios = <&tlmm 34 0>, - <&tlmm 48 0>, - <&pm2falcon_gpios 3 0>, - <&tlmm 51 0>; - qcom,gpio-reset = <1>; - qcom,gpio-vdig = <2>; - qcom,gpio-vana = <3>; - qcom,gpio-req-tbl-num = <0 1 2 3>; - qcom,gpio-req-tbl-flags = <1 0 0 0>; - qcom,gpio-req-tbl-label = "CAMIF_MCLK", - "CAM_RESET", - "CAM_VDIG", - "CAM_VANA"; - qcom,sensor-position = <0>; - qcom,sensor-mode = <0>; - qcom,cci-master = <1>; - status = "ok"; - clocks = <&clock_mmss MCLK2_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_MCLK2_CLK>; - clock-names = "cam_src_clk", "cam_clk"; - qcom,clock-rates = <24000000 0>; - }; - - eeprom2: qcom,eeprom@2 { - cell-index = <2>; - reg = <0x2>; - compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; - qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; - qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; - qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; - qcom,cam-vreg-op-mode = <105000 80000 105000>; - qcom,gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk1_active - &cam_sensor_front_active - &cam_actuator_vaf_active>; - pinctrl-1 = <&cam_sensor_mclk1_suspend - &cam_sensor_front_suspend - &cam_actuator_vaf_suspend>; - gpios = <&tlmm 33 0>, - <&tlmm 47 0>, - <&pmfalcon_gpios 3 0>, - <&tlmm 44 0>, - <&tlmm 50 0>; - qcom,gpio-reset = <1>; - qcom,gpio-vdig = <2>; - qcom,gpio-vana = <3>; - qcom,gpio-vaf = <4>; - qcom,gpio-req-tbl-num = <0 1 2 3 4>; - qcom,gpio-req-tbl-flags = <1 0 0 0 0>; - qcom,gpio-req-tbl-label = "CAMIF_MCLK2", - "CAM_RESET2", - "CAM_VDIG", - "CAM_VANA", - "CAM_VAF"; - qcom,sensor-position = <1>; - qcom,sensor-mode = <0>; - qcom,cci-master = <1>; - status = "ok"; - clocks = <&clock_mmss MCLK1_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_MCLK1_CLK>; - clock-names = "cam_src_clk", "cam_clk"; - qcom,clock-rates = <24000000 0>; - }; - - qcom,camera@0 { - cell-index = <0>; - compatible = "qcom,camera"; - reg = <0x0>; - qcom,csiphy-sd-index = <0>; - qcom,csid-sd-index = <0>; - qcom,mount-angle = <270>; - qcom,led-flash-src = <&led_flash0>; - qcom,actuator-src = <&actuator0>; - qcom,ois-src = <&ois0>; - qcom,eeprom-src = <&eeprom0>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; - qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; - qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; - qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; - qcom,cam-vreg-op-mode = <105000 80000 105000>; - qcom,gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk0_active - &cam_sensor_rear_active>; - pinctrl-1 = <&cam_sensor_mclk0_suspend - &cam_sensor_rear_suspend>; - gpios = <&tlmm 32 0>, - <&tlmm 46 0>, - <&pm2falcon_gpios 4 0>, - <&tlmm 51 0>; - qcom,gpio-reset = <1>; - qcom,gpio-vdig = <2>; - qcom,gpio-vana = <3>; - qcom,gpio-req-tbl-num = <0 1 2 3>; - qcom,gpio-req-tbl-flags = <1 0 0 0>; - qcom,gpio-req-tbl-label = "CAMIF_MCLK0", - "CAM_RESET0", - "CAM_VDIG", - "CAM_VANA"; - qcom,sensor-position = <0>; - qcom,sensor-mode = <0>; - qcom,cci-master = <0>; - status = "ok"; - clocks = <&clock_mmss MCLK0_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_MCLK0_CLK>; - clock-names = "cam_src_clk", "cam_clk"; - qcom,clock-rates = <24000000 0>; - }; - - qcom,camera@1 { - cell-index = <1>; - compatible = "qcom,camera"; - reg = <0x1>; - qcom,csiphy-sd-index = <1>; - qcom,csid-sd-index = <2>; - qcom,mount-angle = <90>; - qcom,actuator-src = <&actuator1>; - qcom,eeprom-src = <&eeprom1>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; - qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; - qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; - qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; - qcom,cam-vreg-op-mode = <105000 80000 105000>; - qcom,gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk2_active - &cam_sensor_rear2_active>; - pinctrl-1 = <&cam_sensor_mclk2_suspend - &cam_sensor_rear2_suspend>; - gpios = <&tlmm 34 0>, - <&tlmm 48 0>, - <&pm2falcon_gpios 3 0>, - <&tlmm 51 0>; - qcom,gpio-reset = <1>; - qcom,gpio-vdig = <2>; - qcom,gpio-vana = <3>; - qcom,gpio-req-tbl-num = <0 1 2 3>; - qcom,gpio-req-tbl-flags = <1 0 0 0>; - qcom,gpio-req-tbl-label = "CAMIF_MCLK", - "CAM_RESET", - "CAM_VDIG", - "CAM_VANA"; - qcom,sensor-position = <0>; - qcom,sensor-mode = <0>; - qcom,cci-master = <1>; - status = "ok"; - clocks = <&clock_mmss MCLK2_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_MCLK2_CLK>; - clock-names = "cam_src_clk", "cam_clk"; - qcom,clock-rates = <24000000 0>; - }; - - qcom,camera@2 { - cell-index = <2>; - compatible = "qcom,camera"; - reg = <0x02>; - qcom,csiphy-sd-index = <2>; - qcom,csid-sd-index = <2>; - qcom,mount-angle = <90>; - qcom,actuator-src = <&actuator2>; - qcom,eeprom-src = <&eeprom2>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; - qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; - qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; - qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; - qcom,cam-vreg-op-mode = <105000 80000 105000>; - qcom,gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk1_active - &cam_sensor_front_active>; - pinctrl-1 = <&cam_sensor_mclk1_suspend - &cam_sensor_front_suspend>; - gpios = <&tlmm 33 0>, - <&tlmm 47 0>, - <&pm2falcon_gpios 3 0>, - <&tlmm 51 0>; - qcom,gpio-reset = <1>; - qcom,gpio-vdig = <2>; - qcom,gpio-vana = <3>; - qcom,gpio-req-tbl-num = <0 1 2 3>; - qcom,gpio-req-tbl-flags = <1 0 0 0>; - qcom,gpio-req-tbl-label = "CAMIF_MCLK2", - "CAM_RESET2", - "CAM_VDIG", - "CAM_VANA"; - qcom,sensor-position = <1>; - qcom,sensor-mode = <0>; - qcom,cci-master = <1>; - status = "ok"; - clocks = <&clock_mmss MCLK1_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_MCLK1_CLK>; - clock-names = "cam_src_clk", "cam_clk"; - qcom,clock-rates = <24000000 0>; - }; -}; - -&pm2falcon_gpios { - gpio@c300 { /* GPIO4 -CAMERA SENSOR 0 VDIG*/ - qcom,mode = <1>; /* Output */ - qcom,pull = <5>; /* No Pull */ - qcom,vin-sel = <0>; /* VIN1 GPIO_LV */ - qcom,src-sel = <0>; /* GPIO */ - qcom,invert = <0>; /* Invert */ - qcom,master-en = <1>; /* Enable GPIO */ - status = "ok"; - }; - - gpio@c200 { /* GPIO3 -CAMERA SENSOR 2 VDIG*/ - qcom,mode = <1>; /* Output */ - qcom,pull = <5>; /* No Pull */ - qcom,vin-sel = <0>; /* VIN1 GPIO_LV */ - qcom,src-sel = <0>; /* GPIO */ - qcom,invert = <0>; /* Invert */ - qcom,master-en = <1>; /* Enable GPIO */ - status = "ok"; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-camera-sensor-mtp.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-camera-sensor-mtp.dtsi deleted file mode 100644 index 384807c4ef60..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-camera-sensor-mtp.dtsi +++ /dev/null @@ -1,384 +0,0 @@ -/* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -&soc { - led_flash0: qcom,camera-flash@0 { - cell-index = <0>; - compatible = "qcom,camera-flash"; - qcom,flash-source = <&pm2falcon_flash0 &pm2falcon_flash1>; - qcom,torch-source = <&pm2falcon_torch0 &pm2falcon_torch1>; - qcom,switch-source = <&pm2falcon_switch0>; - status = "ok"; - }; - - led_flash1: qcom,camera-flash@1 { - cell-index = <1>; - compatible = "qcom,camera-flash"; - qcom,flash-source = <&pm2falcon_flash2>; - qcom,torch-source = <&pm2falcon_torch2>; - qcom,switch-source = <&pm2falcon_switch1>; - status = "ok"; - }; -}; - -&cci { - actuator0: qcom,actuator@0 { - cell-index = <0>; - reg = <0x0>; - compatible = "qcom,actuator"; - qcom,cci-master = <0>; - gpios = <&tlmm 50 0>; - qcom,gpio-vaf = <0>; - qcom,gpio-req-tbl-num = <0>; - qcom,gpio-req-tbl-flags = <0>; - qcom,gpio-req-tbl-label = "CAM_VAF"; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_actuator_vaf_active>; - pinctrl-1 = <&cam_actuator_vaf_suspend>; - }; - - actuator1: qcom,actuator@1 { - cell-index = <1>; - reg = <0x1>; - compatible = "qcom,actuator"; - qcom,cci-master = <1>; - gpios = <&tlmm 50 0>; - qcom,gpio-vaf = <0>; - qcom,gpio-req-tbl-num = <0>; - qcom,gpio-req-tbl-flags = <0>; - qcom,gpio-req-tbl-label = "CAM_VAF"; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_actuator_vaf_active>; - pinctrl-1 = <&cam_actuator_vaf_suspend>; - }; - - actuator2: qcom,actuator@2 { - cell-index = <2>; - reg = <0x2>; - compatible = "qcom,actuator"; - qcom,cci-master = <1>; - gpios = <&tlmm 50 0>; - qcom,gpio-vaf = <0>; - qcom,gpio-req-tbl-num = <0>; - qcom,gpio-req-tbl-flags = <0>; - qcom,gpio-req-tbl-label = "CAM_VAF"; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_actuator_vaf_active>; - pinctrl-1 = <&cam_actuator_vaf_suspend>; - }; - - ois0: qcom,ois@0 { - cell-index = <0>; - reg = <0x0>; - compatible = "qcom,ois"; - qcom,cci-master = <0>; - gpios = <&tlmm 50 0>; - qcom,gpio-vaf = <0>; - qcom,gpio-req-tbl-num = <0>; - qcom,gpio-req-tbl-flags = <0>; - qcom,gpio-req-tbl-label = "CAM_VAF"; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_actuator_vaf_active>; - pinctrl-1 = <&cam_actuator_vaf_suspend>; - status = "disabled"; - }; - - eeprom0: qcom,eeprom@0 { - cell-index = <0>; - reg = <0>; - compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; - qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; - qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; - qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; - qcom,cam-vreg-op-mode = <105000 80000 105000>; - qcom,gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk0_active - &cam_sensor_rear_active - &cam_actuator_vaf_active>; - pinctrl-1 = <&cam_sensor_mclk0_suspend - &cam_sensor_rear_suspend - &cam_actuator_vaf_suspend>; - gpios = <&tlmm 32 0>, - <&tlmm 46 0>, - <&pm2falcon_gpios 4 0>, - <&tlmm 51 0>, - <&tlmm 50 0>; - qcom,gpio-reset = <1>; - qcom,gpio-vdig = <2>; - qcom,gpio-vana = <3>; - qcom,gpio-vaf = <4>; - qcom,gpio-req-tbl-num = <0 1 2 3 4>; - qcom,gpio-req-tbl-flags = <1 0 0 0 0>; - qcom,gpio-req-tbl-label = "CAMIF_MCLK0", - "CAM_RESET0", - "CAM_VDIG", - "CAM_VANA", - "CAM_VAF"; - qcom,sensor-position = <0>; - qcom,sensor-mode = <0>; - qcom,cci-master = <0>; - status = "ok"; - clocks = <&clock_mmss MCLK0_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_MCLK0_CLK>; - clock-names = "cam_src_clk", "cam_clk"; - qcom,clock-rates = <24000000 0>; - }; - - eeprom1: qcom,eeprom@1 { - cell-index = <1>; - reg = <0x1>; - compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; - qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; - qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; - qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; - qcom,cam-vreg-op-mode = <105000 80000 105000>; - qcom,gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk2_active - &cam_sensor_rear2_active>; - pinctrl-1 = <&cam_sensor_mclk2_suspend - &cam_sensor_rear2_suspend>; - gpios = <&tlmm 34 0>, - <&tlmm 48 0>, - <&pm2falcon_gpios 3 0>, - <&tlmm 51 0>; - qcom,gpio-reset = <1>; - qcom,gpio-vdig = <2>; - qcom,gpio-vana = <3>; - qcom,gpio-req-tbl-num = <0 1 2 3>; - qcom,gpio-req-tbl-flags = <1 0 0 0>; - qcom,gpio-req-tbl-label = "CAMIF_MCLK", - "CAM_RESET", - "CAM_VDIG", - "CAM_VANA"; - qcom,sensor-position = <0>; - qcom,sensor-mode = <0>; - qcom,cci-master = <1>; - status = "ok"; - clocks = <&clock_mmss MCLK2_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_MCLK2_CLK>; - clock-names = "cam_src_clk", "cam_clk"; - qcom,clock-rates = <24000000 0>; - }; - - eeprom2: qcom,eeprom@2 { - cell-index = <2>; - reg = <0x2>; - compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; - qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; - qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; - qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; - qcom,cam-vreg-op-mode = <105000 80000 105000>; - qcom,gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk1_active - &cam_sensor_front_active - &cam_actuator_vaf_active>; - pinctrl-1 = <&cam_sensor_mclk1_suspend - &cam_sensor_front_suspend - &cam_actuator_vaf_suspend>; - gpios = <&tlmm 33 0>, - <&tlmm 47 0>, - <&pmfalcon_gpios 3 0>, - <&tlmm 44 0>, - <&tlmm 50 0>; - qcom,gpio-reset = <1>; - qcom,gpio-vdig = <2>; - qcom,gpio-vana = <3>; - qcom,gpio-vaf = <4>; - qcom,gpio-req-tbl-num = <0 1 2 3 4>; - qcom,gpio-req-tbl-flags = <1 0 0 0 0>; - qcom,gpio-req-tbl-label = "CAMIF_MCLK2", - "CAM_RESET2", - "CAM_VDIG", - "CAM_VANA", - "CAM_VAF"; - qcom,sensor-position = <1>; - qcom,sensor-mode = <0>; - qcom,cci-master = <1>; - status = "ok"; - clocks = <&clock_mmss MCLK1_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_MCLK1_CLK>; - clock-names = "cam_src_clk", "cam_clk"; - qcom,clock-rates = <24000000 0>; - }; - - qcom,camera@0 { - cell-index = <0>; - compatible = "qcom,camera"; - reg = <0x0>; - qcom,csiphy-sd-index = <0>; - qcom,csid-sd-index = <0>; - qcom,mount-angle = <270>; - qcom,led-flash-src = <&led_flash0>; - qcom,actuator-src = <&actuator0>; - qcom,ois-src = <&ois0>; - qcom,eeprom-src = <&eeprom0>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; - qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; - qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; - qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; - qcom,cam-vreg-op-mode = <105000 80000 105000>; - qcom,gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk0_active - &cam_sensor_rear_active>; - pinctrl-1 = <&cam_sensor_mclk0_suspend - &cam_sensor_rear_suspend>; - gpios = <&tlmm 32 0>, - <&tlmm 46 0>, - <&pm2falcon_gpios 4 0>, - <&tlmm 51 0>; - qcom,gpio-reset = <1>; - qcom,gpio-vdig = <2>; - qcom,gpio-vana = <3>; - qcom,gpio-req-tbl-num = <0 1 2 3>; - qcom,gpio-req-tbl-flags = <1 0 0 0>; - qcom,gpio-req-tbl-label = "CAMIF_MCLK0", - "CAM_RESET0", - "CAM_VDIG", - "CAM_VANA"; - qcom,sensor-position = <0>; - qcom,sensor-mode = <0>; - qcom,cci-master = <0>; - status = "ok"; - clocks = <&clock_mmss MCLK0_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_MCLK0_CLK>; - clock-names = "cam_src_clk", "cam_clk"; - qcom,clock-rates = <24000000 0>; - }; - - qcom,camera@1 { - cell-index = <1>; - compatible = "qcom,camera"; - reg = <0x1>; - qcom,csiphy-sd-index = <1>; - qcom,csid-sd-index = <2>; - qcom,mount-angle = <90>; - qcom,actuator-src = <&actuator1>; - qcom,eeprom-src = <&eeprom1>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; - qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; - qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; - qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; - qcom,cam-vreg-op-mode = <105000 80000 105000>; - qcom,gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk2_active - &cam_sensor_rear2_active>; - pinctrl-1 = <&cam_sensor_mclk2_suspend - &cam_sensor_rear2_suspend>; - gpios = <&tlmm 34 0>, - <&tlmm 48 0>, - <&pm2falcon_gpios 3 0>, - <&tlmm 51 0>; - qcom,gpio-reset = <1>; - qcom,gpio-vdig = <2>; - qcom,gpio-vana = <3>; - qcom,gpio-req-tbl-num = <0 1 2 3>; - qcom,gpio-req-tbl-flags = <1 0 0 0>; - qcom,gpio-req-tbl-label = "CAMIF_MCLK", - "CAM_RESET", - "CAM_VDIG", - "CAM_VANA"; - qcom,sensor-position = <0>; - qcom,sensor-mode = <0>; - qcom,cci-master = <1>; - status = "ok"; - clocks = <&clock_mmss MCLK2_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_MCLK2_CLK>; - clock-names = "cam_src_clk", "cam_clk"; - qcom,clock-rates = <24000000 0>; - }; - - qcom,camera@2 { - cell-index = <2>; - compatible = "qcom,camera"; - reg = <0x02>; - qcom,csiphy-sd-index = <2>; - qcom,csid-sd-index = <2>; - qcom,mount-angle = <90>; - qcom,actuator-src = <&actuator2>; - qcom,eeprom-src = <&eeprom2>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; - qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; - qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; - qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; - qcom,cam-vreg-op-mode = <105000 80000 105000>; - qcom,gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_sensor_mclk1_active - &cam_sensor_front_active>; - pinctrl-1 = <&cam_sensor_mclk1_suspend - &cam_sensor_front_suspend>; - gpios = <&tlmm 33 0>, - <&tlmm 47 0>, - <&pm2falcon_gpios 3 0>, - <&tlmm 51 0>; - qcom,gpio-reset = <1>; - qcom,gpio-vdig = <2>; - qcom,gpio-vana = <3>; - qcom,gpio-req-tbl-num = <0 1 2 3>; - qcom,gpio-req-tbl-flags = <1 0 0 0>; - qcom,gpio-req-tbl-label = "CAMIF_MCLK2", - "CAM_RESET2", - "CAM_VDIG", - "CAM_VANA"; - qcom,sensor-position = <1>; - qcom,sensor-mode = <0>; - qcom,cci-master = <1>; - status = "ok"; - clocks = <&clock_mmss MCLK1_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_MCLK1_CLK>; - clock-names = "cam_src_clk", "cam_clk"; - qcom,clock-rates = <24000000 0>; - }; -}; - -&pm2falcon_gpios { - gpio@c300 { /* GPIO4 -CAMERA SENSOR 0 VDIG*/ - qcom,mode = <1>; /* Output */ - qcom,pull = <5>; /* No Pull */ - qcom,vin-sel = <0>; /* VIN1 GPIO_LV */ - qcom,src-sel = <0>; /* GPIO */ - qcom,invert = <0>; /* Invert */ - qcom,master-en = <1>; /* Enable GPIO */ - status = "ok"; - }; - - gpio@c200 { /* GPIO3 -CAMERA SENSOR 2 VDIG*/ - qcom,mode = <1>; /* Output */ - qcom,pull = <5>; /* No Pull */ - qcom,vin-sel = <0>; /* VIN1 GPIO_LV */ - qcom,src-sel = <0>; /* GPIO */ - qcom,invert = <0>; /* Invert */ - qcom,master-en = <1>; /* Enable GPIO */ - status = "ok"; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-camera.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-camera.dtsi deleted file mode 100644 index c16794550d88..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-camera.dtsi +++ /dev/null @@ -1,850 +0,0 @@ -/* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -&soc { - qcom,msm-cam@8c0000 { - compatible = "qcom,msm-cam"; - reg = <0x8c0000 0x40000>; - reg-names = "msm-cam"; - status = "ok"; - bus-vectors = "suspend", "svs", "nominal", "turbo"; - qcom,bus-votes = <0 300000000 640000000 640000000>; - }; - - qcom,csiphy@c824000 { - cell-index = <0>; - compatible = "qcom,csiphy-v3.5", "qcom,csiphy"; - reg = <0xc824000 0x1000>; - reg-names = "csiphy"; - interrupts = <0 78 0>; - interrupt-names = "csiphy"; - gdscr-supply = <&gdsc_camss_top>; - bimc_smmu-supply = <&gdsc_bimc_smmu>; - qcom,cam-vreg-name = "gdscr", "bimc_smmu"; - clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, - <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, - <&clock_mmss MMSS_CAMSS_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, - <&clock_mmss CSI0_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_CSI0_CLK>, - <&clock_mmss MMSS_CAMSS_CPHY_CSID0_CLK>, - <&clock_mmss CSI0PHYTIMER_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_CSI0PHYTIMER_CLK>, - <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, - <&clock_mmss CSIPHY_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_CSIPHY0_CLK>; - clock-names = "mmssnoc_axi", "mnoc_ahb", - "bmic_smmu_ahb", "bmic_smmu_axi", - "camss_ahb_clk", "camss_top_ahb_clk", - "csi_src_clk", "csi_clk", "cphy_csid_clk", - "csiphy_timer_src_clk", "csiphy_timer_clk", - "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; - qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0 - 0 384000000 0>; - status = "ok"; - }; - - qcom,csiphy@c825000 { - cell-index = <1>; - compatible = "qcom,csiphy-v3.5", "qcom,csiphy"; - reg = <0xc825000 0x1000>; - reg-names = "csiphy"; - interrupts = <0 79 0>; - interrupt-names = "csiphy"; - gdscr-supply = <&gdsc_camss_top>; - bimc_smmu-supply = <&gdsc_bimc_smmu>; - qcom,cam-vreg-name = "gdscr", "bimc_smmu"; - clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, - <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, - <&clock_mmss MMSS_CAMSS_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, - <&clock_mmss CSI1_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_CSI1_CLK>, - <&clock_mmss MMSS_CAMSS_CPHY_CSID1_CLK>, - <&clock_mmss CSI1PHYTIMER_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_CSI1PHYTIMER_CLK>, - <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, - <&clock_mmss CSIPHY_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_CSIPHY1_CLK>; - clock-names = "mmssnoc_axi", "mnoc_ahb", - "bmic_smmu_ahb", "bmic_smmu_axi", - "camss_ahb_clk", "camss_top_ahb_clk", - "csi_src_clk", "csi_clk", "cphy_csid_clk", - "csiphy_timer_src_clk", "csiphy_timer_clk", - "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; - qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0 - 0 384000000 0>; - status = "ok"; - }; - - qcom,csiphy@c826000 { - cell-index = <2>; - compatible = "qcom,csiphy-v3.5", "qcom,csiphy"; - reg = <0xc826000 0x1000>; - reg-names = "csiphy"; - interrupts = <0 80 0>; - interrupt-names = "csiphy"; - gdscr-supply = <&gdsc_camss_top>; - bimc_smmu-supply = <&gdsc_bimc_smmu>; - qcom,cam-vreg-name = "gdscr", "bimc_smmu"; - clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, - <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, - <&clock_mmss MMSS_CAMSS_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, - <&clock_mmss CSI0_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_CSI2_CLK>, - <&clock_mmss MMSS_CAMSS_CPHY_CSID2_CLK>, - <&clock_mmss CSI2PHYTIMER_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_CSI2PHYTIMER_CLK>, - <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, - <&clock_mmss CSIPHY_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_CSIPHY2_CLK>; - clock-names = "mmssnoc_axi", "mnoc_ahb", - "bmic_smmu_ahb", "bmic_smmu_axi", - "camss_ahb_clk", "camss_top_ahb_clk", - "csi_src_clk", "csi_clk", "cphy_csid_clk", - "csiphy_timer_src_clk", "csiphy_timer_clk", - "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; - qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0 - 0 384000000 0>; - status = "ok"; - }; - - qcom,csid@ca30000 { - cell-index = <0>; - compatible = "qcom,csid-v5.0", "qcom,csid"; - reg = <0xca30000 0x400>; - reg-names = "csid"; - interrupts = <0 296 0>; - interrupt-names = "csid"; - qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; - gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; - bimc_smmu-supply = <&gdsc_bimc_smmu>; - qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; - qcom,cam-vreg-min-voltage = <925000 0 0>; - qcom,cam-vreg-max-voltage = <925000 0 0>; - qcom,cam-vreg-op-mode = <0 0 0>; - clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, - <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, - <&clock_mmss MMSS_CAMSS_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, - <&clock_mmss CSI0_CLK_SRC>, - <&clock_mmss CSIPHY_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_CSI0_CLK>, - <&clock_mmss MMSS_CAMSS_CSI0_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_CSI0RDI_CLK>, - <&clock_mmss MMSS_CAMSS_CSI0PIX_CLK>, - <&clock_mmss MMSS_CAMSS_CPHY_CSID0_CLK>; - clock-names = "mmssnoc_axi", "mnoc_ahb", - "bmic_smmu_ahb", "bmic_smmu_axi", - "camss_ahb_clk", "camss_top_ahb_clk", - "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", - "csi_clk", "csi_ahb_clk", "csi_rdi_clk", - "csi_pix_clk", "cphy_csid_clk"; - qcom,clock-rates = <0 0 0 0 0 0 0 384000000 384000000 - 0 0 0 0 0>; - status = "ok"; - }; - - qcom,csid@ca30400 { - cell-index = <1>; - compatible = "qcom,csid-v5.0", "qcom,csid"; - reg = <0xca30400 0x400>; - reg-names = "csid"; - interrupts = <0 297 0>; - interrupt-names = "csid"; - qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; - gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; - bimc_smmu-supply = <&gdsc_bimc_smmu>; - qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; - qcom,cam-vreg-min-voltage = <925000 0 0>; - qcom,cam-vreg-max-voltage = <925000 0 0>; - qcom,cam-vreg-op-mode = <0 0 0>; - clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, - <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, - <&clock_mmss MMSS_CAMSS_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, - <&clock_mmss CSI1_CLK_SRC>, - <&clock_mmss CSIPHY_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_CSI1_CLK>, - <&clock_mmss MMSS_CAMSS_CSI1_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_CSI1RDI_CLK>, - <&clock_mmss MMSS_CAMSS_CSI1PIX_CLK>, - <&clock_mmss MMSS_CAMSS_CPHY_CSID1_CLK>; - clock-names = "mmssnoc_axi", "mnoc_ahb", - "bmic_smmu_ahb", "bmic_smmu_axi", - "camss_ahb_clk", "camss_top_ahb_clk", - "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", - "csi_clk", "csi_ahb_clk", "csi_rdi_clk", - "csi_pix_clk", "cphy_csid_clk"; - qcom,clock-rates = <0 0 0 0 0 0 0 256000000 256000000 - 0 0 0 0 0>; - status = "ok"; - }; - - qcom,csid@ca30800 { - cell-index = <2>; - compatible = "qcom,csid-v5.0", "qcom,csid"; - reg = <0xca30800 0x400>; - reg-names = "csid"; - interrupts = <0 298 0>; - interrupt-names = "csid"; - qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; - gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; - bimc_smmu-supply = <&gdsc_bimc_smmu>; - qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; - qcom,cam-vreg-min-voltage = <925000 0 0>; - qcom,cam-vreg-max-voltage = <925000 0 0>; - qcom,cam-vreg-op-mode = <0 0 0>; - clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, - <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, - <&clock_mmss MMSS_CAMSS_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, - <&clock_mmss CSI2_CLK_SRC>, - <&clock_mmss CSIPHY_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_CSI2_CLK>, - <&clock_mmss MMSS_CAMSS_CSI2_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_CSI2RDI_CLK>, - <&clock_mmss MMSS_CAMSS_CSI2PIX_CLK>, - <&clock_mmss MMSS_CAMSS_CPHY_CSID2_CLK>; - clock-names = "mmssnoc_axi", "mnoc_ahb", - "bmic_smmu_ahb", "bmic_smmu_axi", - "camss_ahb_clk", "camss_top_ahb_clk", - "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", - "csi_clk", "csi_ahb_clk", "csi_rdi_clk", - "csi_pix_clk", "cphy_csid_clk"; - qcom,clock-rates = <0 0 0 0 0 0 0 256000000 256000000 - 0 0 0 0 0>; - status = "ok"; - }; - - qcom,csid@ca30c00 { - cell-index = <3>; - compatible = "qcom,csid-v5.0", "qcom,csid"; - reg = <0xca30c00 0x400>; - reg-names = "csid"; - interrupts = <0 299 0>; - interrupt-names = "csid"; - qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; - gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; - bimc_smmu-supply = <&gdsc_bimc_smmu>; - qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; - qcom,cam-vreg-min-voltage = <925000 0 0>; - qcom,cam-vreg-max-voltage = <925000 0 0>; - qcom,cam-vreg-op-mode = <0 0 0>; - clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, - <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, - <&clock_mmss MMSS_CAMSS_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, - <&clock_mmss CSI3_CLK_SRC>, - <&clock_mmss CSIPHY_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_CSI3_CLK>, - <&clock_mmss MMSS_CAMSS_CSI3_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_CSI3RDI_CLK>, - <&clock_mmss MMSS_CAMSS_CSI3PIX_CLK>, - <&clock_mmss MMSS_CAMSS_CPHY_CSID3_CLK>; - clock-names = "mmssnoc_axi", "mnoc_ahb", - "bmic_smmu_ahb", "bmic_smmu_axi", - "camss_ahb_clk", "camss_top_ahb_clk", - "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", - "csi_clk", "csi_ahb_clk", "csi_rdi_clk", - "csi_pix_clk", "cphy_csid_clk"; - qcom,clock-rates = <0 0 0 0 0 0 0 256000000 256000000 - 0 0 0 0 0>; - status = "ok"; - }; - - qcom,cam_smmu { - compatible = "qcom,msm-cam-smmu"; - status = "ok"; - - msm_cam_smmu_cb1 { - compatible = "qcom,msm-cam-smmu-cb"; - iommus = <&mmss_bimc_smmu 0xc00>, - <&mmss_bimc_smmu 0xc01>, - <&mmss_bimc_smmu 0xc02>, - <&mmss_bimc_smmu 0xc03>; - label = "vfe"; - qcom,scratch-buf-support; - }; - - msm_cam_smmu_cb2 { - compatible = "qcom,msm-cam-smmu-cb"; - iommus = <&mmss_bimc_smmu 0xa00>; - label = "cpp"; - }; - - msm_cam_smmu_cb3 { - compatible = "qcom,msm-cam-smmu-cb"; - iommus = <&mmss_bimc_smmu 0xa01>; - label = "camera_fd"; - }; - - msm_cam_smmu_cb4 { - compatible = "qcom,msm-cam-smmu-cb"; - iommus = <&mmss_bimc_smmu 0x800>; - label = "jpeg_enc0"; - }; - - msm_cam_smmu_cb5 { - compatible = "qcom,msm-cam-smmu-cb"; - iommus = <&mmss_bimc_smmu 0x801>; - label = "jpeg_dma"; - }; - }; - - qcom,cpp@ca04000 { - cell-index = <0>; - compatible = "qcom,cpp"; - reg = <0xca04000 0x100>, - <0xca80000 0x3000>, - <0xca18000 0x3000>, - <0xc8c36D4 0x4>; - reg-names = "cpp", "cpp_vbif", "cpp_hw", "camss_cpp"; - interrupts = <0 294 0>; - interrupt-names = "cpp"; - smmu-vdd-supply = <&gdsc_bimc_smmu>; - camss-vdd-supply = <&gdsc_camss_top>; - vdd-supply = <&gdsc_cpp>; - qcom,vdd-names = "smmu-vdd", "camss-vdd", "vdd"; - clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, - <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, - <&clock_mmss CPP_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_CPP_CLK>, - <&clock_mmss MMSS_CAMSS_CPP_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_CPP_AXI_CLK>, - <&clock_mmss MMSS_CAMSS_MICRO_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, - <&clock_mmss MMSS_CAMSS_CPP_VBIF_AHB_CLK>; - clock-names = "mmssnoc_axi_clk", - "mnoc_ahb_clk", - "camss_ahb_clk", "camss_top_ahb_clk", - "cpp_src_clk", - "cpp_core_clk", "camss_cpp_ahb_clk", - "camss_cpp_axi_clk", "micro_iface_clk", - "mmss_smmu_axi_clk", "cpp_vbif_ahb_clk"; - qcom,clock-rates = <0 0 0 0 200000000 200000000 0 0 0 0 0>; - qcom,min-clock-rate = <200000000>; - qcom,bus-master = <1>; - qcom,vbif-qos-setting = <0x20 0x10000000>, - <0x24 0x10000000>, - <0x28 0x10000000>, - <0x2C 0x10000000>; - status = "ok"; - qcom,msm-bus,name = "msm_camera_cpp"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <106 512 0 0>, - <106 512 0 0>; - qcom,msm-bus-vector-dyn-vote; - resets = <&clock_mmss CAMSS_MICRO_BCR>; - reset-names = "micro_iface_reset"; - qcom,src-clock-rates = <100000000 200000000 576000000 - 600000000>; - qcom,cpp-fw-payload-info { - qcom,stripe-base = <790>; - qcom,plane-base = <715>; - qcom,stripe-size = <63>; - qcom,plane-size = <25>; - qcom,fe-ptr-off = <11>; - qcom,we-ptr-off = <23>; - qcom,ref-fe-ptr-off = <17>; - qcom,ref-we-ptr-off = <36>; - qcom,we-meta-ptr-off = <42>; - qcom,fe-mmu-pf-ptr-off = <7>; - qcom,ref-fe-mmu-pf-ptr-off = <10>; - qcom,we-mmu-pf-ptr-off = <13>; - qcom,dup-we-mmu-pf-ptr-off = <18>; - qcom,ref-we-mmu-pf-ptr-off = <23>; - qcom,set-group-buffer-len = <135>; - qcom,dup-frame-indicator-off = <70>; - }; - }; - - qcom,ispif@ca31000 { - cell-index = <0>; - compatible = "qcom,ispif-v3.0", "qcom,ispif"; - reg = <0xca31000 0xc00>, - <0xca00020 0x4>; - reg-names = "ispif", "csi_clk_mux"; - interrupts = <0 309 0>; - interrupt-names = "ispif"; - qcom,num-isps = <0x2>; - camss-vdd-supply = <&gdsc_camss_top>; - vfe0-vdd-supply = <&gdsc_vfe0>; - vfe1-vdd-supply = <&gdsc_vfe1>; - qcom,vdd-names = "camss-vdd", "vfe0-vdd", - "vfe1-vdd"; - qcom,clock-cntl-support; - clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, - <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, - <&clock_mmss CSI0_CLK_SRC>, - <&clock_mmss CSI1_CLK_SRC>, - <&clock_mmss CSI2_CLK_SRC>, - <&clock_mmss CSI3_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_CSI0RDI_CLK>, - <&clock_mmss MMSS_CAMSS_CSI1RDI_CLK>, - <&clock_mmss MMSS_CAMSS_CSI2RDI_CLK>, - <&clock_mmss MMSS_CAMSS_CSI3RDI_CLK>, - <&clock_mmss MMSS_CAMSS_CSI0PIX_CLK>, - <&clock_mmss MMSS_CAMSS_CSI1PIX_CLK>, - <&clock_mmss MMSS_CAMSS_CSI2PIX_CLK>, - <&clock_mmss MMSS_CAMSS_CSI3PIX_CLK>, - <&clock_mmss MMSS_CAMSS_CSI0_CLK>, - <&clock_mmss MMSS_CAMSS_CSI1_CLK>, - <&clock_mmss MMSS_CAMSS_CSI2_CLK>, - <&clock_mmss MMSS_CAMSS_CSI3_CLK>, - <&clock_mmss MMSS_CAMSS_VFE0_CLK>, - <&clock_mmss VFE0_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_CSI_VFE0_CLK>, - <&clock_mmss MMSS_CAMSS_VFE1_CLK>, - <&clock_mmss VFE1_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_CSI_VFE1_CLK>; - clock-names = "mmssnoc_axi", "mnoc_ahb_clk", - "camss_ahb_clk", - "camss_top_ahb_clk", "ispif_ahb_clk", - "csi0_src_clk", "csi1_src_clk", - "csi2_src_clk", "csi3_src_clk", - "csi0_rdi_clk", "csi1_rdi_clk", - "csi2_rdi_clk", "csi3_rdi_clk", - "csi0_pix_clk", "csi1_pix_clk", - "csi2_pix_clk", "csi3_pix_clk", - "camss_csi0_clk", "camss_csi1_clk", - "camss_csi2_clk", "camss_csi3_clk", - "camss_vfe_vfe0_clk", - "vfe0_clk_src", "camss_csi_vfe0_clk", - "camss_vfe_vfe1_clk", - "vfe1_clk_src", "camss_csi_vfe1_clk"; - qcom,clock-rates = <0 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 - 0 0 0>; - qcom,clock-control = "INIT_RATE", "NO_SET_RATE", - "NO_SET_RATE", "NO_SET_RATE", - "NO_SET_RATE", - "INIT_RATE", "INIT_RATE", - "INIT_RATE", "INIT_RATE", - "NO_SET_RATE", "NO_SET_RATE", - "NO_SET_RATE", "NO_SET_RATE", - "NO_SET_RATE", "NO_SET_RATE", - "NO_SET_RATE", "NO_SET_RATE", - "NO_SET_RATE", "NO_SET_RATE", - "NO_SET_RATE", "NO_SET_RATE", - "NO_SET_RATE", - "INIT_RATE", "NO_SET_RATE", - "NO_SET_RATE", - "INIT_RATE", "NO_SET_RATE"; - status = "ok"; - }; - - vfe0: qcom,vfe0@ca10000 { - cell-index = <0>; - compatible = "qcom,vfe48"; - reg = <0xca10000 0x4000>, - <0xca40000 0x3000>; - reg-names = "vfe", "vfe_vbif"; - interrupts = <0 314 0>; - interrupt-names = "vfe"; - vdd-supply = <&gdsc_vfe0>; - camss-vdd-supply = <&gdsc_camss_top>; - smmu-vdd-supply = <&gdsc_bimc_smmu>; - qcom,vdd-names = "vdd", "camss-vdd", "smmu-vdd"; - clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, - <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, - <&clock_mmss MMSS_CAMSS_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_VFE0_CLK>, - <&clock_mmss MMSS_CAMSS_VFE0_STREAM_CLK>, - <&clock_mmss MMSS_CAMSS_VFE0_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_VFE_VBIF_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_VFE_VBIF_AXI_CLK>, - <&clock_mmss VFE0_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_CSI_VFE0_CLK>; - clock-names = "mmssnoc_axi", "mnoc_ahb_clk", - "bimc_smmu_ahb_clk", "bimc_smmu_axi_clk", - "camss_ahb_clk", "camss_top_ahb_clk", - "camss_vfe_clk", "camss_vfe_stream_clk", - "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk", - "camss_vfe_vbif_axi_clk", "vfe_clk_src", - "camss_csi_vfe_clk"; - qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 384000000 0 - 0 0 0 0 0 0 0 0 0 0 0 576000000 0 - 0 0 0 0 0 0 0 0 0 0 0 600000000 0>; - status = "ok"; - qos-entries = <8>; - qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 - 0x41c 0x420>; - qos-settings = <0xaaa5aaa5 - 0xaaa5aaa5 - 0xaaa5aaa5 - 0xaa55aaa5 - 0xaa55aa55 - 0xaa55aa55 - 0xaa55aa55 - 0x0005aa55>; - vbif-entries = <3>; - vbif-regs = <0x124 0xac 0xd0>; - vbif-settings = <0x3 0x40 0x1010>; - ds-entries = <17>; - ds-regs = <0x424 0x428 0x42c 0x430 0x434 - 0x438 0x43c 0x440 0x444 0x448 0x44c - 0x450 0x454 0x458 0x45c 0x460 0x464>; - ds-settings = <0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0x110>; - qcom,msm-bus,name = "msm_camera_vfe"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <29 512 0 0>, - <29 512 100000000 100000000>; - qcom,msm-bus-vector-dyn-vote; - }; - - vfe1: qcom,vfe1@ca14000 { - cell-index = <1>; - compatible = "qcom,vfe48"; - reg = <0xca14000 0x4000>, - <0xca40000 0x3000>; - reg-names = "vfe", "vfe_vbif"; - interrupts = <0 315 0>; - interrupt-names = "vfe"; - vdd-supply = <&gdsc_vfe1>; - camss-vdd-supply = <&gdsc_camss_top>; - smmu-vdd-supply = <&gdsc_bimc_smmu>; - qcom,vdd-names = "vdd", "camss-vdd", "smmu-vdd"; - clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, - <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, - <&clock_mmss MMSS_CAMSS_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_VFE1_CLK>, - <&clock_mmss MMSS_CAMSS_VFE1_STREAM_CLK>, - <&clock_mmss MMSS_CAMSS_VFE1_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_VFE_VBIF_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_VFE_VBIF_AXI_CLK>, - <&clock_mmss VFE1_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_CSI_VFE1_CLK>; - clock-names = "mmssnoc_axi", "mnoc_ahb_clk", - "bimc_smmu_ahb_clk", "bimc_smmu_axi_clk", - "camss_ahb_clk", "camss_top_ahb_clk", - "camss_vfe_clk", "camss_vfe_stream_clk", - "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk", - "camss_vfe_vbif_axi_clk", "vfe_clk_src", - "camss_csi_vfe_clk"; - qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 384000000 0 - 0 0 0 0 0 0 0 0 0 0 0 576000000 0 - 0 0 0 0 0 0 0 0 0 0 0 600000000 0>; - status = "ok"; - qos-entries = <8>; - qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 - 0x41c 0x420>; - qos-settings = <0xaaa5aaa5 - 0xaaa5aaa5 - 0xaaa5aaa5 - 0xaa55aaa5 - 0xaa55aa55 - 0xaa55aa55 - 0xaa55aa55 - 0x0005aa55>; - vbif-entries = <3>; - vbif-regs = <0x124 0xac 0xd0>; - vbif-settings = <0x3 0x40 0x1010>; - ds-entries = <17>; - ds-regs = <0x424 0x428 0x42c 0x430 0x434 - 0x438 0x43c 0x440 0x444 0x448 0x44c - 0x450 0x454 0x458 0x45c 0x460 0x464>; - ds-settings = <0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0xcccc1111 - 0x110>; - qcom,msm-bus,name = "msm_camera_vfe"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <29 512 0 0>, - <29 512 100000000 100000000>; - qcom,msm-bus-vector-dyn-vote; - }; - - qcom,vfe { - compatible = "qcom,vfe"; - num_child = <2>; - }; - - cci: qcom,cci@ca0c000 { - cell-index = <0>; - compatible = "qcom,cci"; - reg = <0xca0c000 0x4000>; - #address-cells = <1>; - #size-cells = <0>; - reg-names = "cci"; - interrupts = <0 295 0>; - interrupt-names = "cci"; - status = "ok"; - mmagic-supply = <&gdsc_bimc_smmu>; - gdscr-supply = <&gdsc_camss_top>; - qcom,cam-vreg-name = "mmagic", "gdscr"; - clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, - <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, - <&clock_mmss MMSS_CAMSS_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, - <&clock_mmss CCI_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_CCI_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_CCI_CLK>; - clock-names = "mmssnoc_axi", "mnoc_ahb", "smmu_ahb", "smmu_axi", - "camss_ahb_clk", "camss_top_ahb_clk", - "cci_src_clk", "cci_ahb_clk", "camss_cci_clk"; - qcom,clock-rates = <0 0 0 0 0 0 19200000 0 0>, - <0 0 0 0 0 0 37500000 0 0>; - pinctrl-names = "cci_default", "cci_suspend"; - pinctrl-0 = <&cci0_active &cci1_active>; - pinctrl-1 = <&cci0_suspend &cci1_suspend>; - gpios = <&tlmm 36 0>, - <&tlmm 37 0>, - <&tlmm 38 0>, - <&tlmm 39 0>; - qcom,gpio-tbl-num = <0 1 2 3>; - qcom,gpio-tbl-flags = <1 1 1 1>; - qcom,gpio-tbl-label = "CCI_I2C_DATA0", - "CCI_I2C_CLK0", - "CCI_I2C_DATA1", - "CCI_I2C_CLK1"; - i2c_freq_100Khz: qcom,i2c_standard_mode { - status = "disabled"; - }; - i2c_freq_400Khz: qcom,i2c_fast_mode { - status = "disabled"; - }; - i2c_freq_custom: qcom,i2c_custom_mode { - status = "disabled"; - }; - i2c_freq_1Mhz: qcom,i2c_fast_plus_mode { - status = "disabled"; - }; - }; - - qcom,jpeg@ca1c000 { - cell-index = <0>; - compatible = "qcom,jpeg"; - reg = <0xca1c000 0x4000>, - <0xca60000 0x3000>; - reg-names = "jpeg_hw", "jpeg_vbif"; - interrupts = <0 316 0>; - interrupt-names = "jpeg"; - smmu-vdd-supply = <&gdsc_bimc_smmu>; - camss-vdd-supply = <&gdsc_camss_top>; - qcom,vdd-names = "smmu-vdd", "camss-vdd"; - clock-names = "mmssnoc_axi", - "mmss_mnoc_ahb_clk", - "mmss_bimc_smmu_ahb_clk", - "mmss_bimc_smmu_axi_clk", - "mmss_camss_ahb_clk", - "mmss_camss_top_ahb_clk", - "core_clk", - "mmss_camss_jpeg_ahb_clk", - "mmss_camss_jpeg_axi_clk"; - clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, - <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, - <&clock_mmss MMSS_CAMSS_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_JPEG0_CLK>, - <&clock_mmss MMSS_CAMSS_JPEG_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_JPEG_AXI_CLK >; - qcom,clock-rates = <0 0 0 0 0 0 480000000 0 0>; - qcom,vbif-reg-settings = <0x4 0x1>; - qcom,prefetch-reg-settings = <0x30c 0x1111>, - <0x318 0x31>, - <0x324 0x31>, - <0x330 0x31>, - <0x33c 0x0>; - qcom,msm-bus,name = "msm_camera_jpeg0"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = <62 512 0 0>, - <62 512 1920000 2880000>; - status = "ok"; - }; - - qcom,jpeg@caa0000 { - cell-index = <3>; - compatible = "qcom,jpegdma"; - reg = <0xcaa0000 0x4000>, - <0xca60000 0x3000>; - reg-names = "jpeg_hw", "jpeg_vbif"; - interrupts = <0 304 0>; - interrupt-names = "jpeg"; - smmu-vdd-supply = <&gdsc_bimc_smmu>; - camss-vdd-supply = <&gdsc_camss_top>; - qcom,vdd-names = "smmu-vdd", "camss-vdd"; - clock-names = "mmssnoc_axi", - "mmss_mnoc_ahb_clk", - "mmss_bimc_smmu_ahb_clk", - "mmss_bimc_smmu_axi_clk", - "mmss_camss_ahb_clk", - "mmss_camss_top_ahb_clk", - "core_clk", - "mmss_camss_jpeg_ahb_clk", - "mmss_camss_jpeg_axi_clk"; - clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, - <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, - <&clock_mmss MMSS_CAMSS_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_JPEG0_CLK>, - <&clock_mmss MMSS_CAMSS_JPEG_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_JPEG_AXI_CLK>; - qcom,clock-rates = <0 0 0 0 0 0 480000000 0 0>; - qcom,vbif-reg-settings = <0x4 0x1>; - qcom,prefetch-reg-settings = <0x18c 0x11>, - <0x1a0 0x31>, - <0x1b0 0x31>; - qcom,msm-bus,name = "msm_camera_jpeg_dma"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = <62 512 0 0>, - <62 512 1920000 2880000>; - qcom,max-ds-factor = <128>; - status = "ok"; - }; -}; - -&i2c_freq_100Khz { - qcom,hw-thigh = <201>; - qcom,hw-tlow = <174>; - qcom,hw-tsu-sto = <204>; - qcom,hw-tsu-sta = <231>; - qcom,hw-thd-dat = <22>; - qcom,hw-thd-sta = <162>; - qcom,hw-tbuf = <227>; - qcom,hw-scl-stretch-en = <0>; - qcom,hw-trdhld = <6>; - qcom,hw-tsp = <3>; - qcom,cci-clk-src = <37500000>; - status = "ok"; -}; - -&i2c_freq_400Khz { - qcom,hw-thigh = <38>; - qcom,hw-tlow = <56>; - qcom,hw-tsu-sto = <40>; - qcom,hw-tsu-sta = <40>; - qcom,hw-thd-dat = <22>; - qcom,hw-thd-sta = <35>; - qcom,hw-tbuf = <62>; - qcom,hw-scl-stretch-en = <0>; - qcom,hw-trdhld = <6>; - qcom,hw-tsp = <3>; - qcom,cci-clk-src = <37500000>; - status = "ok"; -}; - -&i2c_freq_custom { - qcom,hw-thigh = <38>; - qcom,hw-tlow = <56>; - qcom,hw-tsu-sto = <40>; - qcom,hw-tsu-sta = <40>; - qcom,hw-thd-dat = <22>; - qcom,hw-thd-sta = <35>; - qcom,hw-tbuf = <62>; - qcom,hw-scl-stretch-en = <1>; - qcom,hw-trdhld = <6>; - qcom,hw-tsp = <3>; - qcom,cci-clk-src = <37500000>; - status = "ok"; -}; - -&i2c_freq_1Mhz { - qcom,hw-thigh = <16>; - qcom,hw-tlow = <22>; - qcom,hw-tsu-sto = <17>; - qcom,hw-tsu-sta = <18>; - qcom,hw-thd-dat = <16>; - qcom,hw-thd-sta = <15>; - qcom,hw-tbuf = <24>; - qcom,hw-scl-stretch-en = <0>; - qcom,hw-trdhld = <3>; - qcom,hw-tsp = <3>; - qcom,cci-clk-src = <37500000>; - status = "ok"; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-cdp.dts b/arch/arm/boot/dts/qcom/msmfalcon-cdp.dts deleted file mode 100644 index ddcea8653983..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-cdp.dts +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "msmfalcon.dtsi" -#include "msmfalcon-cdp.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON CDP"; - compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp"; - qcom,board-id = <1 0>; - qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, - <0x0001001b 0x0201011a 0x0 0x0>; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-cdp.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-cdp.dtsi deleted file mode 100644 index e1306bd78837..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-cdp.dtsi +++ /dev/null @@ -1,95 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "msmfalcon-pinctrl.dtsi" -#include "msmfalcon-camera-sensor-cdp.dtsi" -/ { -}; - -&uartblsp1dm1 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&uart_console_active>; -}; - -&ufsphy1 { - vdda-phy-supply = <&pm2falcon_l1>; - vdda-pll-supply = <&pmfalcon_l10>; - vddp-ref-clk-supply = <&pmfalcon_l1>; - vdda-phy-max-microamp = <51400>; - vdda-pll-max-microamp = <14200>; - vddp-ref-clk-max-microamp = <100>; - vddp-ref-clk-always-on; - status = "ok"; -}; - -&ufs1 { - vdd-hba-supply = <&gdsc_ufs>; - vdd-hba-fixed-regulator; - vcc-supply = <&pm2falcon_l4>; - vccq2-supply = <&pmfalcon_l8>; - vcc-max-microamp = <500000>; - vccq2-max-microamp = <600000>; - status = "ok"; -}; - -&mdss_mdp { - qcom,mdss-pref-prim-intf = "dsi"; -}; - -&mdss_dsi { - hw-config = "split_dsi"; -}; - -&mdss_dsi0 { - qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; - pinctrl-names = "mdss_default", "mdss_sleep"; - pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; - pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; - qcom,platform-reset-gpio = <&tlmm 53 0>; - qcom,platform-te-gpio = <&tlmm 59 0>; -}; - -&mdss_dsi1 { - qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; - pinctrl-names = "mdss_default", "mdss_sleep"; - pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; - pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; - qcom,platform-reset-gpio = <&tlmm 53 0>; - qcom,platform-te-gpio = <&tlmm 59 0>; -}; - -&pm2falcon_wled { - qcom,led-strings-list = [01 02]; -}; - -&dsi_dual_nt35597_truly_video { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&dsi_dual_nt35597_truly_cmd { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&soc { - qcom,msm-ssc-sensors { - compatible = "qcom,msm-ssc-sensors"; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-common.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-common.dtsi deleted file mode 100644 index 1a7ec9fea452..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-common.dtsi +++ /dev/null @@ -1,324 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -&soc { - usb3: ssusb@a800000 { - compatible = "qcom,dwc-usb3-msm"; - reg = <0x0a800000 0xfc100>, - <0x0c016000 0x400>; - reg-names = "core_base", - "ahb2phy_base"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - interrupts = <0 347 0>, <0 243 0>, <0 180 0>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", "pwr_event_irq"; - - USB3_GDSC-supply = <&gdsc_usb30>; - - qcom,usb-dbm = <&dbm_1p5>; - qcom,msm-bus,name = "usb3"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <61 512 0 0>, - <61 512 240000 800000>; - - qcom,dwc-usb3-msm-tx-fifo-size = <21288>; - extcon = <&pmfalcon_pdphy>; - qcom,pm-qos-latency = <41>; /* CPU-CLUSTER-WFI-LVL latency +1 */ - - clocks = <&clock_gcc GCC_USB30_MASTER_CLK>, - <&clock_gcc GCC_CFG_NOC_USB3_AXI_CLK>, - <&clock_gcc GCC_AGGRE2_USB3_AXI_CLK>, - <&clock_rpmcc RPM_AGGR2_NOC_CLK>, - <&clock_gcc GCC_USB30_MOCK_UTMI_CLK>, - <&clock_gcc GCC_USB30_SLEEP_CLK>, - <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&clock_rpmcc CXO_DWC3_CLK>; - - clock-names = "core_clk", "iface_clk", "bus_aggr_clk", - "noc_aggr_clk", "utmi_clk", "sleep_clk", - "cfg_ahb_clk", "xo"; - - qcom,core-clk-rate = <133330000>; - - resets = <&clock_gcc GCC_USB_30_BCR>; - reset-names = "core_reset"; - - dwc3@a800000 { - compatible = "snps,dwc3"; - reg = <0x0a800000 0xc8d0>; - interrupt-parent = <&intc>; - interrupts = <0 131 0>; - usb-phy = <&qusb_phy0>, <&ssphy>; - tx-fifo-resize; - snps,nominal-elastic-buffer; - snps,disable-clk-gating; - snps,is-utmi-l1-suspend; - snps,hird-threshold = /bits/ 8 <0x0>; - }; - - qcom,usbbam@a904000 { - compatible = "qcom,usb-bam-msm"; - reg = <0x0a904000 0x17000>; - interrupt-parent = <&intc>; - interrupts = <0 132 0>; - - qcom,bam-type = <0>; - qcom,usb-bam-fifo-baseaddr = <0x146bb000>; - qcom,usb-bam-num-pipes = <8>; - qcom,ignore-core-reset-ack; - qcom,disable-clk-gating; - qcom,usb-bam-override-threshold = <0x4001>; - qcom,usb-bam-max-mbps-highspeed = <400>; - qcom,usb-bam-max-mbps-superspeed = <3600>; - qcom,reset-bam-on-connect; - - qcom,pipe0 { - label = "ssusb-ipa-out-0"; - qcom,usb-bam-mem-type = <1>; - qcom,dir = <0>; - qcom,pipe-num = <0>; - qcom,peer-bam = <1>; - qcom,src-bam-pipe-index = <1>; - qcom,data-fifo-size = <0x8000>; - qcom,descriptor-fifo-size = <0x2000>; - }; - qcom,pipe1 { - label = "ssusb-ipa-in-0"; - qcom,usb-bam-mem-type = <1>; - qcom,dir = <1>; - qcom,pipe-num = <0>; - qcom,peer-bam = <1>; - qcom,dst-bam-pipe-index = <0>; - qcom,data-fifo-size = <0x8000>; - qcom,descriptor-fifo-size = <0x2000>; - }; - qcom,pipe2 { - label = "ssusb-qdss-in-0"; - qcom,usb-bam-mem-type = <2>; - qcom,dir = <1>; - qcom,pipe-num = <0>; - qcom,peer-bam = <0>; - qcom,peer-bam-physical-address = <0x06064000>; - qcom,src-bam-pipe-index = <0>; - qcom,dst-bam-pipe-index = <2>; - qcom,data-fifo-offset = <0x0>; - qcom,data-fifo-size = <0x1800>; - qcom,descriptor-fifo-offset = <0x1800>; - qcom,descriptor-fifo-size = <0x800>; - }; - qcom,pipe3 { - label = "ssusb-dpl-ipa-in-1"; - qcom,usb-bam-mem-type = <1>; - qcom,dir = <1>; - qcom,pipe-num = <1>; - qcom,peer-bam = <1>; - qcom,dst-bam-pipe-index = <2>; - qcom,data-fifo-size = <0x8000>; - qcom,descriptor-fifo-size = <0x2000>; - }; - }; - }; - - qusb_phy0: qusb@c012000 { - compatible = "qcom,qusb2phy"; - reg = <0x0c012000 0x180>, - <0x01fcb24c 0x4>, - <0x00188018 0x4>; - reg-names = "qusb_phy_base", - "tcsr_clamp_dig_n_1p8", - "ref_clk_addr"; - vdd-supply = <&pm2falcon_l1>; - vdda18-supply = <&pmfalcon_l10>; - vdda33-supply = <&pm2falcon_l7>; - qcom,vdd-voltage-level = <0 925000 925000>; - qcom,qusb-phy-init-seq = <0xf8 0x80 - 0xb3 0x84 - 0x83 0x88 - 0xc0 0x8c - 0x30 0x08 - 0x79 0x0c - 0x21 0x10 - 0x14 0x9c - 0x9f 0x1c - 0x00 0x18>; - phy_type= "utmi"; - qcom,phy-clk-scheme = "cml"; - qcom,major-rev = <1>; - - clocks = <&clock_rpmcc RPM_LN_BB_CLK1>, - <&clock_gcc GCC_RX0_USB2_CLKREF_CLK>, - <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; - - clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk"; - - resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>; - reset-names = "phy_reset"; - }; - - ssphy: ssphy@c010000 { - compatible = "qcom,usb-ssphy-qmp-v2"; - reg = <0xc010000 0xe18>, - <0x01fcb244 0x4>, - <0x01fcb248 0x4>; - reg-names = "qmp_phy_base", - "vls_clamp_reg", - "tcsr_usb3_dp_phymode"; - vdd-supply = <&pm2falcon_l1>; - core-supply = <&pmfalcon_l10>; - qcom,vdd-voltage-level = <0 925000 925000>; - vdd-core-voltage-level = <0 1800000 1800000>; - qcom,vbus-valid-override; - qcom,qmp-phy-init-seq = - /* */ - <0xac 0x14 0x00 - 0x34 0x08 0x00 - 0x174 0x30 0x00 - 0x3c 0x06 0x00 - 0xbc 0x00 0x00 - 0xc0 0x08 0x00 - 0x194 0x06 0x00 - 0x19c 0x01 0x00 - 0x178 0x00 0x00 - 0xd0 0x82 0x00 - 0xdc 0x55 0x00 - 0xe0 0x55 0x00 - 0xe4 0x03 0x00 - 0x78 0x0b 0x00 - 0x84 0x16 0x00 - 0x90 0x28 0x00 - 0x108 0x80 0x00 - 0x10c 0x00 0x00 - 0x184 0x0a 0x00 - 0x4c 0x15 0x00 - 0x50 0x34 0x00 - 0x54 0x00 0x00 - 0xc8 0x00 0x00 - 0x18c 0x00 0x00 - 0xcc 0x00 0x00 - 0x128 0x00 0x00 - 0x0c 0x0a 0x00 - 0x10 0x01 0x00 - 0x1c 0x31 0x00 - 0x20 0x01 0x00 - 0x14 0x00 0x00 - 0x18 0x00 0x00 - 0x24 0xde 0x00 - 0x28 0x07 0x00 - 0x48 0x0f 0x00 - 0x70 0x0f 0x00 - 0x100 0x80 0x00 - 0xa8 0x01 0x00 - 0x430 0x0b 0x00 - 0x830 0x0b 0x00 - 0x444 0x00 0x00 - 0x844 0x00 0x00 - 0x43c 0x00 0x00 - 0x83c 0x00 0x00 - 0x440 0x00 0x00 - 0x840 0x00 0x00 - 0x408 0x0a 0x00 - 0x808 0x0a 0x00 - 0x414 0x06 0x00 - 0x814 0x06 0x00 - 0x434 0x75 0x00 - 0x834 0x75 0x00 - 0x4d4 0x02 0x00 - 0x8d4 0x02 0x00 - 0x4d8 0x4e 0x00 - 0x8d8 0x4e 0x00 - 0x4dc 0x18 0x00 - 0x8dc 0x18 0x00 - 0x4f8 0x77 0x00 - 0x8f8 0x77 0x00 - 0x4fc 0x80 0x00 - 0x8fc 0x80 0x00 - 0x4c0 0x0a 0x00 - 0x8c0 0x0a 0x00 - 0x504 0x03 0x00 - 0x904 0x03 0x00 - 0x50c 0x16 0x00 - 0x90c 0x16 0x00 - 0x500 0x00 0x00 - 0x900 0x00 0x00 - 0x260 0x10 0x00 - 0x660 0x10 0x00 - 0x2a4 0x12 0x00 - 0x6a4 0x12 0x00 - 0x28c 0xc6 0x00 - 0x68c 0xc6 0x00 - 0x244 0x00 0x00 - 0x644 0x00 0x00 - 0x248 0x00 0x00 - 0x648 0x00 0x00 - 0xc0c 0x9f 0x00 - 0xc24 0x17 0x00 - 0xc28 0x0f 0x00 - 0xcc8 0x83 0x00 - 0xcc4 0x02 0x00 - 0xccc 0x09 0x00 - 0xcd0 0xa2 0x00 - 0xcd4 0x85 0x00 - 0xc80 0xd1 0x00 - 0xc84 0x1f 0x00 - 0xc88 0x47 0x00 - 0xcb8 0x75 0x00 - 0xcbc 0x13 0x00 - 0xcb0 0x86 0x00 - 0xca0 0x04 0x00 - 0xc8c 0x44 0x00 - 0xc70 0xe7 0x00 - 0xc74 0x03 0x00 - 0xc78 0x40 0x00 - 0xc7c 0x00 0x00 - 0xdd8 0x88 0x00 - 0xffffffff 0xffffffff 0x00>; - - qcom,qmp-phy-reg-offset = - <0xd74 /* USB3_PHY_PCS_STATUS */ - 0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */ - 0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */ - 0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */ - 0xc00 /* USB3_PHY_SW_RESET */ - 0xc08 /* USB3_PHY_START */ - 0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */ - - clocks = <&clock_gcc GCC_USB3_PHY_AUX_CLK>, - <&clock_gcc GCC_USB3_PHY_PIPE_CLK>, - <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&clock_rpmcc RPM_LN_BB_CLK1>, - <&clock_gcc GCC_USB3_CLKREF_CLK>; - - clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", - "ref_clk_src", "ref_clk"; - - resets = <&clock_gcc GCC_USB3_PHY_BCR>, - <&clock_gcc GCC_USB3PHY_PHY_BCR>; - reset-names = "phy_reset", "phy_phy_reset"; - }; - - usb_audio_qmi_dev { - compatible = "qcom,usb-audio-qmi-dev"; - iommus = <&lpass_q6_smmu 6>; - qcom,usb-audio-stream-id = <6>; - qcom,usb-audio-intr-num = <2>; - }; - - dbm_1p5: dbm@a8f8000 { - compatible = "qcom,usb-dbm-1p5"; - reg = <0xa8f8000 0x300>; - qcom,reset-ep-after-lpm-resume; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-coresight.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-coresight.dtsi deleted file mode 100644 index 07f3743e8d1c..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-coresight.dtsi +++ /dev/null @@ -1,1849 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -&soc { - tmc_etr: tmc@6048000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x0003b961>; - - reg = <0x6048000 0x1000>, - <0x6064000 0x15000>; - reg-names = "tmc-base", "bam-base"; - - arm,buffer-size = <0x400000>; - arm,sg-enable; - - coresight-ctis = <&cti0 &cti8>; - - coresight-name = "coresight-tmc-etr"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "core_a_clk"; - - port{ - tmc_etr_in_replicator: endpoint { - slave-mode; - remote-endpoint = <&replicator_out_tmc_etr>; - }; - }; - }; - - replicator: replicator@6046000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x0003b909>; - - reg = <0x6046000 0x1000>; - reg-names = "replicator-base"; - - coresight-name = "coresight-replicator"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "core_a_clk"; - - ports{ - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - replicator_out_tmc_etr:endpoint { - remote-endpoint = - <&tmc_etr_in_replicator>; - }; - }; - port@1 { - reg = <0>; - replicator_in_tmc_etf:endpoint { - slave-mode; - remote-endpoint = - <&tmc_etf_out_replicator>; - }; - }; - }; - }; - - tmc_etf: tmc@6047000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x0003b961>; - - reg = <0x6047000 0x1000>; - reg-names = "tmc-base"; - - coresight-name = "coresight-tmc-etf"; - - coresight-ctis = <&cti0 &cti8>; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "core_a_clk"; - - ports{ - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - tmc_etf_out_replicator:endpoint { - remote-endpoint = - <&replicator_in_tmc_etf>; - }; - }; - port@1 { - reg = <0>; - tmc_etf_in_funnel_merg:endpoint { - slave-mode; - remote-endpoint = - <&funnel_merg_out_tmc_etf>; - }; - }; - }; - }; - - funnel_merg: funnel@6045000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x0003b908>; - - reg = <0x6045000 0x1000>; - reg-names = "funnel-base"; - - coresight-name = "coresight-funnel-merg"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "core_a_clk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_merg_out_tmc_etf:endpoint { - remote-endpoint = - <&tmc_etf_in_funnel_merg>; - }; - }; - port@1 { - reg = <0>; - funnel_merg_in_funnel_in0:endpoint { - slave-mode; - remote-endpoint = - <&funnel_in0_out_funnel_merg>; - }; - }; - port@2 { - reg = <1>; - funnel_merg_in_funnel_in1:endpoint { - slave-mode; - remote-endpoint = - <&funnel_in1_out_funnel_merg>; - }; - }; - }; - }; - - funnel_in0: funnel@6041000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x0003b908>; - - reg = <0x6041000 0x1000>; - reg-names = "funnel-base"; - - coresight-name = "coresight-funnel-in0"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "core_a_clk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_in0_out_funnel_merg: endpoint { - remote-endpoint = - <&funnel_merg_in_funnel_in0>; - }; - }; - port@2 { - reg = <6>; - funnel_in0_in_funnel_qatb: endpoint { - slave-mode; - remote-endpoint = - <&funnel_qatb_out_funnel_in0>; - }; - }; - port@3 { - reg = <7>; - funnel_in0_in_stm: endpoint { - slave-mode; - remote-endpoint = <&stm_out_funnel_in0>; - }; - }; - port@4 { - reg = <0>; - funnel_in0_in_rpm_etm0: endpoint { - slave-mode; - remote-endpoint = - <&rpm_etm0_out_funnel_in0>; - }; - }; - }; - }; - - funnel_in1: funnel@6042000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x0003b908>; - - reg = <0x6042000 0x1000>; - reg-names = "funnel-base"; - - coresight-name = "coresight-funnel-in1"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "core_a_clk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_in1_out_funnel_merg: endpoint { - remote-endpoint = - <&funnel_merg_in_funnel_in1>; - }; - }; - port@1 { - reg = <2>; - funnel_in1_in_tpda_nav: endpoint { - slave-mode; - remote-endpoint = - <&tpda_nav_out_funnel_in1>; - }; - }; - port@2 { - reg = <5>; - funnel_in1_in_tpda_mss: endpoint { - slave-mode; - remote-endpoint = - <&tpda_mss_out_funnel_in1>; - }; - }; - port@3 { - reg = <6>; - funnel_in1_in_funnel_apss_merg: endpoint { - slave-mode; - remote-endpoint = - <&funnel_apss_merg_out_funnel_in1>; - }; - }; - port@4 { - reg = <4>; - funnel_in1_in_turing_etm0: endpoint { - slave-mode; - remote-endpoint = - <&turing_etm0_out_funnel_in1>; - }; - }; - }; - }; - - funnel_apss_merg: funnel@7b70000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x0003b908>; - - reg = <0x7b70000 0x1000>; - reg-names = "funnel-base"; - - coresight-name = "coresight-funnel-apss-merg"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "core_a_clk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_apss_merg_out_funnel_in1: endpoint { - remote-endpoint = - <&funnel_in1_in_funnel_apss_merg>; - }; - }; - port@1 { - reg = <0>; - funnel_apss_merg_in_funnel_apss: endpoint { - slave-mode; - remote-endpoint = - <&funnel_apss_out_funnel_apss_merg>; - }; - }; - port@2 { - reg = <1>; - funnel_apss_merg_in_tpda_olc: endpoint { - slave-mode; - remote-endpoint = - <&tpda_olc_out_funnel_apss_merg>; - }; - }; - port@3 { - reg = <3>; - funnel_apss_merg_in_tpda_apss: endpoint { - slave-mode; - remote-endpoint = - <&tpda_apss_out_funnel_apss_merg>; - }; - }; - }; - }; - - funnel_apss: funnel@7b60000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x0003b908>; - - reg = <0x7b60000 0x1000>; - reg-names = "funnel-base"; - - coresight-name = "coresight-funnel-apss"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "core_a_clk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_apss_out_funnel_apss_merg: endpoint { - remote-endpoint = - <&funnel_apss_merg_in_funnel_apss>; - }; - }; - port@1 { - reg = <0>; - funnel_apss_in_etm0: endpoint { - slave-mode; - remote-endpoint = - <&etm0_out_funnel_apss>; - }; - }; - port@2 { - reg = <1>; - funnel_apss_in_etm1: endpoint { - slave-mode; - remote-endpoint = - <&etm1_out_funnel_apss>; - }; - }; - port@3 { - reg = <2>; - funnel_apss_in_etm2: endpoint { - slave-mode; - remote-endpoint = - <&etm2_out_funnel_apss>; - }; - }; - port@4 { - reg = <3>; - funnel_apss_in_etm3: endpoint { - slave-mode; - remote-endpoint = - <&etm3_out_funnel_apss>; - }; - }; - port@5 { - reg = <4>; - funnel_apss_in_etm4: endpoint { - slave-mode; - remote-endpoint = - <&etm4_out_funnel_apss>; - }; - }; - port@6 { - reg = <5>; - funnel_apss_in_etm5: endpoint { - slave-mode; - remote-endpoint = - <&etm5_out_funnel_apss>; - }; - }; - port@7 { - reg = <6>; - funnel_apss_in_etm6: endpoint { - slave-mode; - remote-endpoint = - <&etm6_out_funnel_apss>; - }; - }; - port@8 { - reg = <7>; - funnel_apss_in_etm7: endpoint { - slave-mode; - remote-endpoint = - <&etm7_out_funnel_apss>; - }; - }; - }; - }; - - stm: stm@6002000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x0003b962>; - - reg = <0x6002000 0x1000>, - <0x16280000 0x180000>; - reg-names = "stm-base", "stm-data-base"; - - coresight-name = "coresight-stm"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "core_a_clk"; - - port{ - stm_out_funnel_in0: endpoint { - remote-endpoint = <&funnel_in0_in_stm>; - }; - }; - }; - - etm0: etm@7840000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x0003b95d>; - - reg = <0x7840000 0x1000>; - cpu = <&CPU0>; - - coresight-name = "coresight-etm0"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "core_a_clk"; - - port{ - etm0_out_funnel_apss: endpoint { - remote-endpoint = <&funnel_apss_in_etm0>; - }; - }; - }; - - etm1: etm@7940000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x0003b95d>; - - reg = <0x7940000 0x1000>; - cpu = <&CPU1>; - - coresight-name = "coresight-etm1"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "core_a_clk"; - - port{ - etm1_out_funnel_apss: endpoint { - remote-endpoint = <&funnel_apss_in_etm1>; - }; - }; - }; - - etm2: etm@7a40000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x0003b95d>; - - reg = <0x7a40000 0x1000>; - cpu = <&CPU2>; - - coresight-name = "coresight-etm2"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "core_a_clk"; - - port{ - etm2_out_funnel_apss: endpoint { - remote-endpoint = <&funnel_apss_in_etm2>; - }; - }; - }; - - etm3: etm@7b40000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x0003b95d>; - - reg = <0x7b40000 0x1000>; - cpu = <&CPU3>; - - coresight-name = "coresight-etm3"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "core_a_clk"; - - port{ - etm3_out_funnel_apss: endpoint { - remote-endpoint = <&funnel_apss_in_etm3>; - }; - }; - }; - - etm4: etm@7c40000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x0003b95d>; - - reg = <0x7c40000 0x1000>; - cpu = <&CPU4>; - - coresight-name = "coresight-etm4"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "core_a_clk"; - - port{ - etm4_out_funnel_apss: endpoint { - remote-endpoint = <&funnel_apss_in_etm4>; - }; - }; - }; - - etm5: etm@7d40000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x0003b95d>; - - reg = <0x7d40000 0x1000>; - cpu = <&CPU5>; - - coresight-name = "coresight-etm5"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "core_a_clk"; - - port{ - etm5_out_funnel_apss: endpoint { - remote-endpoint = <&funnel_apss_in_etm5>; - }; - }; - }; - - etm6: etm@7e40000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x0003b95d>; - - reg = <0x7e40000 0x1000>; - cpu = <&CPU6>; - - coresight-name = "coresight-etm6"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "core_a_clk"; - - port{ - etm6_out_funnel_apss: endpoint { - remote-endpoint = <&funnel_apss_in_etm6>; - }; - }; - }; - - etm7: etm@7f40000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x0003b95d>; - - reg = <0x7f40000 0x1000>; - cpu = <&CPU7>; - - coresight-name = "coresight-etm7"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "core_a_clk"; - - port{ - etm7_out_funnel_apss: endpoint { - remote-endpoint = <&funnel_apss_in_etm7>; - }; - }; - }; - - cti0: cti@6010000 { - compatible = "arm,coresight-cti"; - reg = <0x6010000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti0"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti1: cti@6011000 { - compatible = "arm,coresight-cti"; - reg = <0x6011000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti1"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti2: cti@6012000 { - compatible = "arm,coresight-cti"; - reg = <0x6012000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti2"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - qcom,cti-gpio-trigout = <4>; - pinctrl-names = "cti-trigout-pctrl"; - pinctrl-0 = <&trigout_b>; - }; - - cti3: cti@6013000 { - compatible = "arm,coresight-cti"; - reg = <0x6013000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti3"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti4: cti@6014000 { - compatible = "arm,coresight-cti"; - reg = <0x6014000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti4"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti5: cti@6015000 { - compatible = "arm,coresight-cti"; - reg = <0x6015000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti5"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti6: cti@6016000 { - compatible = "arm,coresight-cti"; - reg = <0x6016000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti6"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti7: cti@6017000 { - compatible = "arm,coresight-cti"; - reg = <0x6017000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti7"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti8: cti@6018000 { - compatible = "arm,coresight-cti"; - reg = <0x6018000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti8"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti9: cti@6019000 { - compatible = "arm,coresight-cti"; - reg = <0x6019000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti9"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti10: cti@601a000 { - compatible = "arm,coresight-cti"; - reg = <0x601a000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti10"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti11: cti@601b000 { - compatible = "arm,coresight-cti"; - reg = <0x601b000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti11"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti12: cti@601c000 { - compatible = "arm,coresight-cti"; - reg = <0x601c000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti12"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti13: cti@601d000 { - compatible = "arm,coresight-cti"; - reg = <0x601d000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti13"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti14: cti@601e000 { - compatible = "arm,coresight-cti"; - reg = <0x601e000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti14"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti15: cti@601f000 { - compatible = "arm,coresight-cti"; - reg = <0x601f000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti15"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti_cpu0: cti@7820000 { - compatible = "arm,coresight-cti"; - reg = <0x7820000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti-cpu0"; - cpu = <&CPU0>; - - qcom,cti-save; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti_cpu1: cti@7920000 { - compatible = "arm,coresight-cti"; - reg = <0x7920000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti-cpu1"; - cpu = <&CPU1>; - - qcom,cti-save; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti_cpu2: cti@7a20000 { - compatible = "arm,coresight-cti"; - reg = <0x7a20000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti-cpu2"; - cpu = <&CPU2>; - - qcom,cti-save; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti_cpu3: cti@7b20000 { - compatible = "arm,coresight-cti"; - reg = <0x7b20000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti-cpu3"; - cpu = <&CPU3>; - - qcom,cti-save; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti_cpu4: cti@7c20000 { - compatible = "arm,coresight-cti"; - reg = <0x7c20000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti-cpu4"; - cpu = <&CPU4>; - - qcom,cti-save; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti_cpu5: cti@7d20000 { - compatible = "arm,coresight-cti"; - reg = <0x7d20000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti-cpu5"; - cpu = <&CPU5>; - - qcom,cti-save; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti_cpu6: cti@7e20000 { - compatible = "arm,coresight-cti"; - reg = <0x7e20000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti-cpu6"; - cpu = <&CPU6>; - - qcom,cti-save; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti_cpu7: cti@7f20000 { - compatible = "arm,coresight-cti"; - reg = <0x7f20000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti-cpu7"; - cpu = <&CPU7>; - - qcom,cti-save; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti_apss: cti@7b80000 { - compatible = "arm,coresight-cti"; - reg = <0x7b80000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti-apss"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti_apss_dl: cti@7bc1000 { - compatible = "arm,coresight-cti"; - reg = <0x7bc1000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti-apss-dl"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti_olc: cti@7b91000 { - compatible = "arm,coresight-cti"; - reg = <0x7b91000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti-olc"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti_lpass0: cti@7060000 { - compatible = "arm,coresight-cti"; - reg = <0x7060000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti-lpass0"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti_lpass1: cti@7061000 { - compatible = "arm,coresight-cti"; - reg = <0x7061000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti-lpass1"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti_turing: cti@7068000 { - compatible = "arm,coresight-cti"; - reg = <0x7068000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti-turing"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti_wcss0: cti@71a4000 { - compatible = "arm,coresight-cti"; - reg = <0x71a4000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti-wcss0"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti_wcss1: cti@71a5000 { - compatible = "arm,coresight-cti"; - reg = <0x71a5000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti-wcss1"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti_wcss2: cti@71a6000 { - compatible = "arm,coresight-cti"; - reg = <0x71a6000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti-wcss2"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti_mmss: cti@7188000 { - compatible = "arm,coresight-cti"; - reg = <0x7188000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti-mmss"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti_isdb: cti@7121000 { - compatible = "arm,coresight-cti"; - reg = <0x7121000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti-isdb"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti_rpm: cti@7048000 { - compatible = "arm,coresight-cti"; - reg = <0x7048000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti-rpm"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - cti_mss: cti@7041000 { - compatible = "arm,coresight-cti"; - reg = <0x7041000 0x1000>; - reg-names = "cti-base"; - - coresight-name = "coresight-cti-mss"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - }; - - funnel_qatb: funnel@6005000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x0003b908>; - - reg = <0x6005000 0x1000>; - reg-names = "funnel-base"; - - coresight-name = "coresight-funnel-qatb"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "core_a_clk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_qatb_out_funnel_in0: endpoint { - remote-endpoint = - <&funnel_in0_in_funnel_qatb>; - }; - }; - port@1 { - reg = <0>; - funnel_qatb_in_tpda: endpoint { - slave-mode; - remote-endpoint = - <&tpda_out_funnel_qatb>; - }; - }; - port@2 { - reg = <3>; - funnel_qatb_in_funnel_dlct: endpoint { - slave-mode; - remote-endpoint = - <&funnel_dlct_out_funnel_qatb>; - }; - }; - }; - }; - - tpda: tpda@6004000 { - compatible = "qcom,coresight-tpda"; - reg = <0x6004000 0x1000>; - reg-names = "tpda-base"; - - coresight-name = "coresight-tpda"; - - qcom,tpda-atid = <65>; - qcom,bc-elem-size = <7 32>, - <9 32>; - qcom,tc-elem-size = <3 32>, - <6 32>, - <9 32>; - qcom,dsb-elem-size = <7 32>, - <9 32>; - qcom,cmb-elem-size = <3 32>, - <4 32>, - <5 32>, - <9 64>; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - tpda_out_funnel_qatb: endpoint { - remote-endpoint = - <&funnel_qatb_in_tpda>; - }; - }; - port@1 { - reg = <1>; - tpda_in_funnel_gpu_dl: endpoint { - slave-mode; - remote-endpoint = - <&funnel_gpu_dl_out_tpda>; - }; - }; - port@2 { - reg = <2>; - tpda_in_funnel_dlct: endpoint { - slave-mode; - remote-endpoint = - <&funnel_dlct_out_tpda>; - }; - }; - port@3 { - reg = <4>; - tpda_in_tpdm_vsense: endpoint { - slave-mode; - remote-endpoint = - <&tpdm_vsense_out_tpda>; - }; - }; - port@4 { - reg = <5>; - tpda_in_tpdm_dcc: endpoint { - slave-mode; - remote-endpoint = - <&tpdm_dcc_out_tpda>; - }; - }; - port@5 { - reg = <6>; - tpda_in_tpdm_prng: endpoint { - slave-mode; - remote-endpoint = - <&tpdm_prng_out_tpda>; - }; - }; - port@6 { - reg = <8>; - tpda_in_tpdm_qm: endpoint { - slave-mode; - remote-endpoint = - <&tpdm_qm_out_tpda>; - }; - }; - port@7 { - reg = <10>; - tpda_in_tpdm_pimem: endpoint { - slave-mode; - remote-endpoint = - <&tpdm_pimem_out_tpda>; - }; - }; - port@8 { - reg = <11>; - tpda_in_tpdm: endpoint { - slave-mode; - remote-endpoint = - <&tpdm_out_tpda>; - }; - }; - }; - }; - - funnel_gpu_dl: funnel@7140000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x0003b908>; - - reg = <0x71c40000 0x1000>; - reg-names = "funnel-base"; - - coresight-name = "coresight-funnel-gpu-dl"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "core_a_clk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_gpu_dl_out_tpda: endpoint { - remote-endpoint = - <&tpda_in_funnel_gpu_dl>; - }; - }; - port@2 { - reg = <0>; - funnel_gpu_dl_in_tpdm_gpu: endpoint { - slave-mode; - remote-endpoint = - <&tpdm_gpu_out_funnel_gpu_dl>; - }; - }; - }; - }; - - tpdm_gpu: tpdm@7111000 { - status = "disabled"; - compatible = "qcom,coresight-tpdm"; - reg = <0x7111000 0x1000>; - reg-names = "tpdm-base"; - - coresight-name = "coresight-tpdm-gpu"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - port{ - tpdm_gpu_out_funnel_gpu_dl: endpoint { - remote-endpoint = <&funnel_gpu_dl_in_tpdm_gpu>; - }; - }; - }; - - tpdm_vsense: tpdm@7038000 { - compatible = "qcom,coresight-tpdm"; - reg = <0x7038000 0x1000>; - reg-names = "tpdm-base"; - - coresight-name = "coresight-tpdm-vsense"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - port{ - tpdm_vsense_out_tpda: endpoint { - remote-endpoint = <&tpda_in_tpdm_vsense>; - }; - }; - }; - - tpdm_dcc: tpdm@7054000 { - compatible = "qcom,coresight-tpdm"; - reg = <0x7054000 0x1000>; - reg-names = "tpdm-base"; - - coresight-name = "coresight-tpdm-dcc"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - port{ - tpdm_dcc_out_tpda: endpoint { - remote-endpoint = <&tpda_in_tpdm_dcc>; - }; - }; - }; - - tpdm_prng: tpdm@704c000 { - compatible = "qcom,coresight-tpdm"; - reg = <0x704c000 0x1000>; - reg-names = "tpdm-base"; - - coresight-name = "coresight-tpdm-prng"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - port{ - tpdm_prng_out_tpda: endpoint { - remote-endpoint = <&tpda_in_tpdm_prng>; - }; - }; - }; - - tpdm_qm: tpdm@71d0000 { - compatible = "qcom,coresight-tpdm"; - reg = <0x71d0000 0x1000>; - reg-names = "tpdm-base"; - - coresight-name = "coresight-tpdm-qm"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - port{ - tpdm_qm_out_tpda: endpoint { - remote-endpoint = <&tpda_in_tpdm_qm>; - }; - }; - }; - - tpdm_pimem: tpdm@7050000 { - compatible = "qcom,coresight-tpdm"; - reg = <0x7050000 0x1000>; - reg-names = "tpdm-base"; - - coresight-name = "coresight-tpdm-pimem"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - port{ - tpdm_pimem_out_tpda: endpoint { - remote-endpoint = <&tpda_in_tpdm_pimem>; - }; - }; - }; - - tpdm: tpdm@6006000 { - compatible = "qcom,coresight-tpdm"; - reg = <0x6006000 0x1000>; - reg-names = "tpdm-base"; - - coresight-name = "coresight-tpdm"; - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - port{ - tpdm_out_tpda: endpoint { - remote-endpoint = <&tpda_in_tpdm>; - }; - }; - }; - - tpda_nav: tpda@7191000 { - compatible = "qcom,coresight-tpda"; - reg = <0x7191000 0x1000>; - reg-names = "tpda-base"; - - coresight-name = "coresight-tpda-nav"; - - qcom,tpda-atid = <68>; - qcom,cmb-elem-size = <0 32>; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - tpda_nav_out_funnel_in1: endpoint { - remote-endpoint = - <&funnel_in1_in_tpda_nav>; - }; - }; - port@1 { - reg = <0>; - tpda_nav_in_tpdm_nav: endpoint { - slave-mode; - remote-endpoint = - <&tpdm_nav_out_tpda_nav>; - }; - }; - }; - }; - - tpda_apss: tpda@7bc2000 { - compatible = "qcom,coresight-tpda"; - reg = <0x7bc2000 0x1000>; - reg-names = "tpda-base"; - - coresight-name = "coresight-tpda-apss"; - - qcom,tpda-atid = <66>; - qcom,dsb-elem-size = <0 128>; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - tpda_apss_out_funnel_apss_merg: endpoint { - remote-endpoint = - <&funnel_apss_merg_in_tpda_apss>; - }; - }; - port@1 { - reg = <0>; - tpda_apss_in_tpdm_apss: endpoint { - slave-mode; - remote-endpoint = - <&tpdm_apss_out_tpda_apss>; - }; - }; - }; - }; - - tpdm_apss: tpdm@7bc0000 { - compatible = "qcom,coresight-tpdm"; - reg = <0x7bc0000 0x1000>; - reg-names = "tpdm-base"; - - coresight-name = "coresight-tpdm-apss"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - port{ - tpdm_apss_out_tpda_apss: endpoint { - remote-endpoint = <&tpda_apss_in_tpdm_apss>; - }; - }; - }; - - tpda_mss: tpda@7043000 { - compatible = "qcom,coresight-tpda"; - reg = <0x7043000 0x1000>; - reg-names = "tpda-base"; - - coresight-name = "coresight-tpda-mss"; - - qcom,tpda-atid = <67>; - qcom,dsb-elem-size = <0 32>; - qcom,cmb-elem-size = <0 32>; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - tpda_mss_out_funnel_in1: endpoint { - remote-endpoint = - <&funnel_in1_in_tpda_mss>; - }; - }; - port@1 { - reg = <0>; - tpda_mss_in_tpdm_mss: endpoint { - slave-mode; - remote-endpoint = - <&tpdm_mss_out_tpda_mss>; - }; - }; - }; - }; - - tpdm_mss: tpdm@7042000 { - compatible = "qcom,coresight-tpdm"; - reg = <0x7042000 0x1000>; - reg-names = "tpdm-base"; - - coresight-name = "coresight-tpdm-mss"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - port{ - tpdm_mss_out_tpda_mss: endpoint { - remote-endpoint = <&tpda_mss_in_tpdm_mss>; - }; - }; - }; - - tpdm_nav: tpdm@7190000 { - compatible = "qcom,coresight-tpdm"; - reg = <0x7190000 0x1000>; - reg-names = "tpdm-base"; - - coresight-name = "coresight-tpdm-nav"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - port{ - tpdm_nav_out_tpda_nav: endpoint { - remote-endpoint = <&tpda_nav_in_tpdm_nav>; - }; - }; - }; - - tpda_olc: tpda@7b92000 { - compatible = "qcom,coresight-tpda"; - reg = <0x7b92000 0x1000>; - reg-names = "tpda-base"; - - coresight-name = "coresight-tpda-olc"; - - qcom,tpda-atid = <69>; - qcom,cmb-elem-size = <0 64>; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - tpda_olc_out_funnel_apss_merg: endpoint { - remote-endpoint = - <&funnel_apss_merg_in_tpda_olc>; - }; - }; - port@1 { - reg = <0>; - tpda_olc_in_tpdm_olc: endpoint { - slave-mode; - remote-endpoint = - <&tpdm_olc_out_tpda_olc>; - }; - }; - }; - }; - - tpdm_olc: tpdm@7b90000 { - compatible = "qcom,coresight-tpdm"; - reg = <0x7b90000 0x1000>; - reg-names = "tpdm-base"; - - coresight-name = "coresight-tpdm-olc"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - port{ - tpdm_olc_out_tpda_olc: endpoint { - remote-endpoint = <&tpda_olc_in_tpdm_olc>; - }; - }; - }; - - funnel_dlct: funnel@71c3000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x0003b908>; - - reg = <0x71c3000 0x1000>; - reg-names = "funnel-base"; - - coresight-name = "coresight-funnel-dlct"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "core_a_clk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_dlct_out_tpda: endpoint { - remote-endpoint = - <&tpda_in_funnel_dlct>; - }; - }; - port@1 { - reg = <1>; - funnel_dlct_out_funnel_qatb: endpoint { - remote-endpoint = - <&funnel_qatb_in_funnel_dlct>; - }; - }; - port@2 { - reg = <0>; - funnel_dlct_in_tpdm_dlct: endpoint { - slave-mode; - remote-endpoint = - <&tpdm_dlct_out_funnel_dlct>; - }; - }; - port@3 { - reg = <3>; - funnel_dlct_in_funnel_wcss: endpoint { - slave-mode; - remote-endpoint = - <&funnel_wcss_out_funnel_dlct>; - }; - }; - port@4 { - reg = <1>; - funnel_dlct_in_audio_etm0: endpoint { - slave-mode; - remote-endpoint = - <&audio_etm0_out_funnel_dlct>; - }; - }; - port@5 { - reg = <2>; - funnel_dlct_in_modem_etm0: endpoint { - slave-mode; - remote-endpoint = - <&modem_etm0_out_funnel_dlct>; - }; - }; - }; - }; - - tpdm_dlct: tpdm@71c2000 { - compatible = "qcom,coresight-tpdm"; - reg = <0x71c2000 0x1000>; - reg-names = "tpdm-base"; - - coresight-name = "coresight-tpdm-dlct"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - port{ - tpdm_dlct_out_funnel_dlct: endpoint { - remote-endpoint = <&funnel_dlct_in_tpdm_dlct>; - }; - }; - }; - - hwevent: hwevent@158000 { - compatible = "qcom,coresight-hwevent"; - reg = <0x158000 0x80>, - <0x17091000 0x80>, - <0x1730200c 0x4>, - <0xc90137c 0x4>, - <0xc828018 0x80>, - <0x1c00058 0x80>, - <0x5e02038 0x4>, - <0x5e02028 0x10>, - <0x1fcb360 0x80>, - <0x1fcb760 0x80>, - <0x1fcbf60 0x80>, - <0xa8f8860 0x4>, - <0x500c260 0x4>, - <0x500d040 0x4>, - <0x1da6400 0x80>; - reg-names = "gcc-ctrl", "lpass-stm", "lpass-qdsp", "mdss-mdp", - "mdss-misc", "pcie0-hwev", "ssc-en", "ssc-hwev", - "tcsr-qdss", "tcsr-mss0", "tcsr-mss1", "usb-ctrl", - "vbif-stm", "vbif-stm-en", "ufs-mux"; - - coresight-name = "coresight-hwevent"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>, - <&clock_mmss MMSS_MISC_AHB_CLK>; - clock-names = "core_clk", "core_a_clk", "core_mmss_clk"; - - qcom,hwevent-clks = "core_mmss_clk"; - }; - - csr: csr@6001000 { - compatible = "qcom,coresight-csr"; - reg = <0x6001000 0x1000>; - reg-names = "csr-base"; - - coresight-name = "coresight-csr"; - - qcom,blk-size = <1>; - }; - - modem_etm0 { - compatible = "qcom,coresight-remote-etm"; - - coresight-name = "coresight-modem-etm0"; - qcom,inst-id = <2>; - - port{ - modem_etm0_out_funnel_dlct: endpoint { - remote-endpoint = <&funnel_dlct_in_modem_etm0>; - }; - }; - }; - - audio_etm0 { - compatible = "qcom,coresight-remote-etm"; - - coresight-name = "coresight-audio-etm0"; - qcom,inst-id = <5>; - - port{ - audio_etm0_out_funnel_dlct: endpoint { - remote-endpoint = <&funnel_dlct_in_audio_etm0>; - }; - }; - }; - - rpm_etm0 { - compatible = "qcom,coresight-remote-etm"; - - coresight-name = "coresight-rpm-etm0"; - qcom,inst-id = <4>; - - port{ - rpm_etm0_out_funnel_in0: endpoint { - remote-endpoint = <&funnel_in0_in_rpm_etm0>; - }; - }; - }; - - turing_etm0 { - compatible = "qcom,coresight-remote-etm"; - - coresight-name = "coresight-turing-etm0"; - qcom,inst-id = <13>; - - port{ - turing_etm0_out_funnel_in1: endpoint { - remote-endpoint = <&funnel_in1_in_turing_etm0>; - }; - }; - }; - - funnel_wcss: funnel@719e000 { - compatible = "arm,primecell"; - arm,primecell-periphid = <0x0003b908>; - - reg = <0x719e000 0x1000>; - reg-names = "funnel-base"; - - coresight-name = "coresight-funnel-wcss"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "apb_pclk", "core_a_clk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - funnel_wcss_out_funnel_dlct: endpoint { - remote-endpoint = - <&funnel_dlct_in_funnel_wcss>; - }; - }; - port@1 { - reg = <1>; - funnel_wcss_in_tpda_wcss: endpoint { - slave-mode; - remote-endpoint = - <&tpda_wcss_out_funnel_wcss>; - }; - }; - }; - }; - - tpda_wcss: tpda@719d000 { - status = "disabled"; - compatible = "qcom,coresight-tpda"; - reg = <0x719d000 0x1000>; - reg-names = "tpda-base"; - - coresight-name = "coresight-tpda-wcss"; - - qcom,tpda-atid = <70>; - qcom,dsb-elem-size = <0 32>; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - tpda_wcss_out_funnel_wcss: endpoint { - remote-endpoint = - <&funnel_wcss_in_tpda_wcss>; - }; - }; - port@1 { - reg = <0>; - tpda_wcss_in_tpdm_wcss: endpoint { - slave-mode; - remote-endpoint = - <&tpdm_wcss_out_tpda_wcss>; - }; - }; - }; - }; - - tpdm_wcss: tpdm@719c000 { - status = "disabled"; - compatible = "qcom,coresight-tpdm"; - reg = <0x719c000 0x1000>; - reg-names = "tpdm-base"; - - coresight-name = "coresight-tpdm-wcss"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - port{ - tpdm_wcss_out_tpda_wcss: endpoint { - remote-endpoint = <&tpda_wcss_in_tpdm_wcss>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-gpu.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-gpu.dtsi deleted file mode 100644 index 5c11131b9ddf..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-gpu.dtsi +++ /dev/null @@ -1,271 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -&soc { - pil_gpu: qcom,kgsl-hyp { - compatible = "qcom,pil-tz-generic"; - qcom,pas-id = <13>; - qcom,firmware-name = "a512_zap"; - }; - - msm_bus: qcom,kgsl-busmon{ - label = "kgsl-busmon"; - compatible = "qcom,kgsl-busmon"; - }; - - gpubw: qcom,gpubw { - compatible = "qcom,devbw"; - governor = "bw_vbif"; - qcom,src-dst-ports = <26 512>; - /* - * active-only flag is used while registering the bus - * governor. It helps release the bus vote when the CPU - * subsystem is inactive - */ - qcom,active-only; - qcom,bw-tbl = - < 0 /* off */ >, - < 762 /* 100 MHz */ >, - < 1144 /* 150 MHz */ >, - < 1525 /* 200 MHz */ >, - < 2288 /* 300 MHz */ >, - < 3143 /* 412 MHz */ >, - < 4173 /* 547 MHz */ >, - < 5195 /* 681 MHz */ >, - < 5859 /* 768 MHz */ >, - < 7759 /* 1017 MHz */ >, - < 9887 /* 1296 MHz */ >, - < 10327 /* 1353 MHz */ >, - < 11863 /* 1555 MHz */ >, - < 13763 /* 1804 MHz */ >; - }; - - msm_gpu: qcom,kgsl-3d0@5000000 { - label = "kgsl-3d0"; - compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; - status = "ok"; - reg = <0x5000000 0x40000>; - reg-names = "kgsl_3d0_reg_memory"; - interrupts = <0 300 0>; - interrupt-names = "kgsl_3d0_irq"; - qcom,id = <0>; - - qcom,chipid = <0x05010200>; - - qcom,initial-pwrlevel = <6>; - - /* */ - qcom,idle-timeout = <80>; - - qcom,highest-bank-bit = <14>; - - /* size in bytes */ - qcom,snapshot-size = <1048576>; - - clocks = <&clock_gfx GPUCC_GFX3D_CLK>, - <&clock_gcc GCC_GPU_CFG_AHB_CLK>, - <&clock_gfx GPUCC_RBBMTIMER_CLK>, - <&clock_gcc GCC_GPU_BIMC_GFX_CLK>, - <&clock_gcc GCC_GPU_BIMC_GFX_SRC_CLK>, - <&clock_gfx GPUCC_RBCPR_CLK>; - - clock-names = "core_clk", "iface_clk", "rbbmtimer_clk", - "mem_clk", "mem_iface_clk", "rbcpr_clk"; - - /* Bus Scale Settings */ - qcom,gpubw-dev = <&gpubw>; - qcom,bus-control; - qcom,bus-width = <16>; - qcom,msm-bus,name = "grp3d"; - qcom,msm-bus,num-cases = <14>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <26 512 0 0>, - - <26 512 0 800000>, /* 1 bus=100 */ - <26 512 0 1200000>, /* 2 bus=150 */ - <26 512 0 1600000>, /* 3 bus=200 */ - <26 512 0 2400000>, /* 4 bus=300 */ - <26 512 0 3296000>, /* 5 bus=412 */ - <26 512 0 4376000>, /* 6 bus=547 */ - <26 512 0 5448000>, /* 7 bus=681 */ - <26 512 0 6144000>, /* 8 bus=768 */ - <26 512 0 8136000>, /* 9 bus=1017 */ - <26 512 0 10368000>, /* 10 bus=1296 */ - <26 512 0 10824000>, /* 11 bus=1353 */ - <26 512 0 12440000>, /* 12 bus=1555 */ - <26 512 0 14432000>; /* 13 bus=1804 */ - - /* GDSC regulator names */ - regulator-names = "vddcx", "vdd"; - /* GDSC oxili regulators */ - vddcx-supply = <&gdsc_gpu_cx>; - vdd-supply = <&gdsc_gpu_gx>; - - /* CPU latency parameter */ - qcom,pm-qos-active-latency = <349>; - qcom,pm-qos-wakeup-latency = <349>; - - /* Quirks */ - qcom,gpu-quirk-two-pass-use-wfi; - qcom,gpu-quirk-dp2clockgating-disable; - qcom,gpu-quirk-lmloadkill-disable; - - /* Enable context aware freq. scaling */ - qcom,enable-ca-jump; - - /* Context aware jump busy penalty in us */ - qcom,ca-busy-penalty = <12000>; - - /* Context aware jump target power level */ - qcom,ca-target-pwrlevel = <4>; - - /* GPU Mempools */ - qcom,gpu-mempools { - #address-cells= <1>; - #size-cells = <0>; - compatible = "qcom,gpu-mempools"; - - qcom,mempool-max-pages = <32768>; - - /* 4K Page Pool configuration */ - qcom,gpu-mempool@0 { - reg = <0>; - qcom,mempool-page-size = <4096>; - }; - /* 64K Page Pool configuration */ - qcom,gpu-mempool@1 { - reg = <1>; - qcom,mempool-page-size = <65536>; - }; - }; - - /* Power levels */ - qcom,gpu-pwrlevels { - #address-cells = <1>; - #size-cells = <0>; - - compatible = "qcom,gpu-pwrlevels"; - - /* TURBO */ - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <750000000>; - qcom,bus-freq = <12>; - qcom,bus-min = <11>; - qcom,bus-max = <13>; - }; - - /* TURBO */ - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <700000000>; - qcom,bus-freq = <11>; - qcom,bus-min = <10>; - qcom,bus-max = <13>; - }; - - /* NOM_L1 */ - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <647000000>; - qcom,bus-freq = <10>; - qcom,bus-min = <10>; - qcom,bus-max = <12>; - }; - - /* NOM */ - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <588000000>; - qcom,bus-freq = <9>; - qcom,bus-min = <9>; - qcom,bus-max = <11>; - }; - - /* SVS_L1 */ - qcom,gpu-pwrlevel@4 { - reg = <4>; - qcom,gpu-freq = <465000000>; - qcom,bus-freq = <9>; - qcom,bus-min = <7>; - qcom,bus-max = <11>; - }; - - /* SVS */ - qcom,gpu-pwrlevel@5 { - reg = <5>; - qcom,gpu-freq = <370000000>; - qcom,bus-freq = <7>; - qcom,bus-min = <5>; - qcom,bus-max = <9>; - }; - - /* Low SVS */ - qcom,gpu-pwrlevel@6 { - reg = <6>; - qcom,gpu-freq = <266000000>; - qcom,bus-freq = <3>; - qcom,bus-min = <3>; - qcom,bus-max = <6>; - }; - - /* Min SVS */ - qcom,gpu-pwrlevel@7 { - reg = <7>; - qcom,gpu-freq = <160000000>; - qcom,bus-freq = <3>; - qcom,bus-min = <2>; - qcom,bus-max = <5>; - }; - - /* XO */ - qcom,gpu-pwrlevel@8 { - reg = <8>; - qcom,gpu-freq = <19200000>; - qcom,bus-freq = <0>; - qcom,bus-min = <0>; - qcom,bus-max = <0>; - }; - }; - }; - - kgsl_msm_iommu: qcom,kgsl-iommu { - compatible = "qcom,kgsl-smmu-v2"; - - reg = <0x05040000 0x10000>; - qcom,protect = <0x40000 0x10000>; - qcom,micro-mmu-control = <0x6000>; - - clocks =<&clock_gcc GCC_GPU_CFG_AHB_CLK>, - <&clock_gcc GCC_GPU_BIMC_GFX_CLK>, - <&clock_gcc GCC_GPU_BIMC_GFX_SRC_CLK>; - - clock-names = "iface_clk", "mem_clk", "mem_iface_clk"; - - qcom,secure_align_mask = <0xfff>; - qcom,retention; - qcom,hyp_secure_alloc; - - gfx3d_user: gfx3d_user { - compatible = "qcom,smmu-kgsl-cb"; - label = "gfx3d_user"; - iommus = <&kgsl_smmu 0>; - qcom,gpu-offset = <0x48000>; - }; - - gfx3d_secure: gfx3d_secure { - compatible = "qcom,smmu-kgsl-cb"; - iommus = <&kgsl_smmu 2>; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-cdp.dts b/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-cdp.dts deleted file mode 100644 index ee3255ebe9f8..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-cdp.dts +++ /dev/null @@ -1,73 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "msmfalcon.dtsi" -#include "msmfalcon-cdp.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON Int. Audio Codec CDP"; - compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp"; - qcom,board-id = <1 1>; - qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, - <0x0001001b 0x0201011a 0x0 0x0>; -}; - -&slim_aud { - status = "disabled"; -}; - -&dai_slim { - status = "disabled"; -}; - -&wcd9335 { - status = "disabled"; -}; - -&wcd934x_cdc { - status = "disabled"; -}; - -&clock_audio { - status = "disabled"; -}; - -&wcd_rst_gpio { - status = "disabled"; -}; - -&wcd9xxx_intc { - status = "disabled"; -}; - -&tasha_snd { - status = "disabled"; -}; - -&tavil_snd { - status = "disabled"; -}; - -&int_codec { - status = "okay"; -}; - -&pmic_analog_codec { - status = "okay"; -}; - -&msm_sdw_codec { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-mtp.dts b/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-mtp.dts deleted file mode 100644 index 59611ab3e5ff..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-mtp.dts +++ /dev/null @@ -1,74 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "msmfalcon.dtsi" -#include "msmfalcon-mtp.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON Int. Audio Codec MTP"; - compatible = "qcom,msmfalcon-mtp", "qcom,msmfalcon", "qcom,mtp"; - qcom,board-id = <8 1>; - qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, - <0x0001001b 0x0201011a 0x0 0x0>; -}; - -&slim_aud { - status = "disabled"; -}; - -&dai_slim { - status = "disabled"; -}; - -&wcd9335 { - status = "disabled"; -}; - -&wcd934x_cdc { - status = "disabled"; -}; - -&clock_audio { - status = "disabled"; -}; - -&wcd_rst_gpio { - status = "disabled"; -}; - -&wcd9xxx_intc { - status = "disabled"; -}; - -&tasha_snd { - status = "disabled"; -}; - -&tavil_snd { - status = "disabled"; -}; - -&int_codec { - qcom,model = "msmfalcon-snd-card-mtp"; - status = "okay"; -}; - -&pmic_analog_codec { - status = "okay"; -}; - -&msm_sdw_codec { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-pm3falcon-cdp.dts b/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-pm3falcon-cdp.dts deleted file mode 100644 index fe91109a4a07..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-pm3falcon-cdp.dts +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "msmfalcon.dtsi" -#include "msmfalcon-cdp.dtsi" -#include "msm-pm3falcon.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON Int. Audio Codec CDP"; - compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp"; - qcom,board-id = <1 1>; - qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-pm3falcon-mtp.dts b/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-pm3falcon-mtp.dts deleted file mode 100644 index 0653e898ec7d..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-pm3falcon-mtp.dts +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "msmfalcon.dtsi" -#include "msmfalcon-mtp.dtsi" -#include "msm-pm3falcon.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON Int. Audio Codec MTP"; - compatible = "qcom,msmfalcon-mtp", "qcom,msmfalcon", "qcom,mtp"; - qcom,board-id = <8 1>; - qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-pm3falcon-rcm.dts b/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-pm3falcon-rcm.dts deleted file mode 100644 index cb2b2239588d..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-pm3falcon-rcm.dts +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "msmfalcon.dtsi" -#include "msmfalcon-cdp.dtsi" -#include "msm-pm3falcon.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON Int. Audio Codec RCM"; - compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp"; - qcom,board-id = <21 1>; - qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-rcm.dts b/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-rcm.dts deleted file mode 100644 index 1d67fe1129c7..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-rcm.dts +++ /dev/null @@ -1,73 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "msmfalcon.dtsi" -#include "msmfalcon-cdp.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON Int. Audio Codec RCM"; - compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp"; - qcom,board-id = <21 1>; - qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, - <0x0001001b 0x0201011a 0x0 0x0>; -}; - -&slim_aud { - status = "disabled"; -}; - -&dai_slim { - status = "disabled"; -}; - -&wcd9335 { - status = "disabled"; -}; - -&wcd934x_cdc { - status = "disabled"; -}; - -&clock_audio { - status = "disabled"; -}; - -&wcd_rst_gpio { - status = "disabled"; -}; - -&wcd9xxx_intc { - status = "disabled"; -}; - -&tasha_snd { - status = "disabled"; -}; - -&tavil_snd { - status = "disabled"; -}; - -&int_codec { - status = "okay"; -}; - -&pmic_analog_codec { - status = "okay"; -}; - -&msm_sdw_codec { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-ion.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-ion.dtsi deleted file mode 100644 index 00b9e61d01b8..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-ion.dtsi +++ /dev/null @@ -1,47 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -&soc { - qcom,ion { - compatible = "qcom,msm-ion"; - #address-cells = <1>; - #size-cells = <0>; - - system_heap: qcom,ion-heap@25 { - reg = <25>; - qcom,ion-heap-type = "SYSTEM"; - }; - - qcom,ion-heap@22 { /* ADSP HEAP */ - reg = <22>; - memory-region = <&adsp_mem>; - qcom,ion-heap-type = "DMA"; - }; - - qcom,ion-heap@27 { /* QSEECOM HEAP */ - reg = <27>; - memory-region = <&qseecom_mem>; - qcom,ion-heap-type = "DMA"; - }; - - qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */ - reg = <10>; - memory-region = <&secure_display_memory>; - qcom,ion-heap-type = "HYP_CMA"; - }; - - qcom,ion-heap@9 { - reg = <9>; - qcom,ion-heap-type = "SYSTEM_SECURE"; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-lpi.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-lpi.dtsi deleted file mode 100644 index 34946c07074b..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-lpi.dtsi +++ /dev/null @@ -1,182 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -&soc { - lpi_tlmm: lpi_pinctrl@15070000 { - compatible = "qcom,lpi-pinctrl"; - reg = <0x15070000 0x0>; - qcom,num-gpios = <32>; - gpio-controller; - #gpio-cells = <2>; - - lpi_mclk0_active: lpi_mclk0_active { - mux { - pins = "gpio18"; - function = "func2"; - }; - - config { - pins = "gpio18"; - drive-strength = <8>; - bias-disable; - }; - }; - - lpi_mclk0_sleep: lpi_mclk0_sleep { - mux { - pins = "gpio18"; - function = "func2"; - }; - - config { - pins = "gpio18"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - cdc_pdm_gpios_active: cdc_pdm_gpios_active { - mux { - pins = "gpio18", "gpio19", - "gpio20", "gpio21", - "gpio23", "gpio25"; - function = "func1"; - }; - - config { - pins = "gpio18", "gpio19", - "gpio20", "gpio21", - "gpio23", "gpio25"; - drive-strength = <8>; - }; - }; - - cdc_pdm_gpios_sleep: cdc_pdm_gpios_sleep { - mux { - pins = "gpio18", "gpio19", - "gpio20", "gpio21", - "gpio23", "gpio25"; - function = "func1"; - }; - - config { - pins = "gpio18", "gpio19", - "gpio20", "gpio21", - "gpio23", "gpio25"; - drive-strength = <2>; - bias-disable; - }; - }; - - cdc_comp_gpios_active: cdc_pdm_comp_gpios_active { - mux { - pins = "gpio22", "gpio24"; - function = "func1"; - }; - - config { - pins = "gpio22", "gpio24"; - drive-strength = <8>; - }; - }; - - cdc_comp_gpios_sleep: cdc_pdm_comp_gpios_sleep { - mux { - pins = "gpio22", "gpio24"; - function = "func1"; - }; - - config { - pins = "gpio22", "gpio24"; - drive-strength = <2>; - bias-disable; - }; - }; - - lpi_cdc_reset_active: lpi_cdc_reset_active { - mux { - pins = "gpio24"; - function = "func2"; - }; - config { - pins = "gpio24"; - drive-strength = <16>; - bias-pull-down; - output-high; - }; - }; - - lpi_cdc_reset_sleep: lpi_cdc_reset_sleep { - mux { - pins = "gpio24"; - function = "func2"; - }; - - config { - pins = "gpio24"; - drive-strength = <16>; - bias-disable; - output-low; - }; - }; - - cdc_dmic12_gpios_active: dmic12_gpios_active { - mux { - pins = "gpio26", "gpio27"; - function = "func1"; - }; - - config { - pins = "gpio26", "gpio27"; - drive-strength = <8>; - }; - }; - - cdc_dmic12_gpios_sleep: dmic12_gpios_sleep { - mux { - pins = "gpio26", "gpio27"; - function = "func1"; - }; - - config { - pins = "gpio26", "gpio27"; - drive-strength = <2>; - bias-disable; - }; - }; - - cdc_dmic34_gpios_active: dmic34_gpios_active { - mux { - pins = "gpio28", "gpio29"; - function = "func1"; - }; - - config { - pins = "gpio28", "gpio29"; - drive-strength = <8>; - }; - }; - - cdc_dmic34_gpios_sleep: dmic34_gpios_sleep { - mux { - pins = "gpio28", "gpio29"; - function = "func1"; - }; - - config { - pins = "gpio28", "gpio29"; - drive-strength = <2>; - bias-disable; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-mdss-panels.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-mdss-panels.dtsi deleted file mode 100644 index 28e5f6ba8b45..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-mdss-panels.dtsi +++ /dev/null @@ -1,83 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "dsi-panel-sim-video.dtsi" -#include "dsi-panel-sim-dualmipi-video.dtsi" -#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi" -#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi" - -&soc { - dsi_panel_pwr_supply: dsi_panel_pwr_supply { - #address-cells = <1>; - #size-cells = <0>; - - qcom,panel-supply-entry@0 { - reg = <0>; - qcom,supply-name = "wqhd-vddio"; - qcom,supply-min-voltage = <1880000>; - qcom,supply-max-voltage = <1950000>; - qcom,supply-enable-load = <32000>; - qcom,supply-disable-load = <80>; - }; - - qcom,panel-supply-entry@1 { - reg = <1>; - qcom,supply-name = "lab"; - qcom,supply-min-voltage = <4600000>; - qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <100000>; - qcom,supply-disable-load = <100>; - }; - - qcom,panel-supply-entry@2 { - reg = <2>; - qcom,supply-name = "ibb"; - qcom,supply-min-voltage = <4600000>; - qcom,supply-max-voltage = <6000000>; - qcom,supply-enable-load = <100000>; - qcom,supply-disable-load = <100>; - qcom,supply-post-on-sleep = <10>; - }; - }; -}; - -&soc { - dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { - #address-cells = <1>; - #size-cells = <0>; - - qcom,panel-supply-entry@0 { - reg = <0>; - qcom,supply-name = "wqhd-vddio"; - qcom,supply-min-voltage = <1880000>; - qcom,supply-max-voltage = <1950000>; - qcom,supply-enable-load = <32000>; - qcom,supply-disable-load = <80>; - }; - }; -}; - -&dsi_dual_nt35597_truly_video { - qcom,mdss-dsi-panel-timings-8996 = [23 1e 07 08 05 03 04 a0 - 23 1e 07 08 05 03 04 a0 - 23 1e 07 08 05 03 04 a0 - 23 1e 07 08 05 03 04 a0 - 23 18 07 08 04 03 04 a0]; -}; - -&dsi_dual_nt35597_truly_cmd { - qcom,mdss-dsi-panel-timings-8996 = [23 1e 07 08 05 03 04 a0 - 23 1e 07 08 05 03 04 a0 - 23 1e 07 08 05 03 04 a0 - 23 1e 07 08 05 03 04 a0 - 23 18 07 08 04 03 04 a0]; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-mdss-pll.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-mdss-pll.dtsi deleted file mode 100644 index 61baf6aff4b1..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-mdss-pll.dtsi +++ /dev/null @@ -1,82 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -&soc { - mdss_dsi0_pll: qcom,mdss_dsi_pll@c994400 { - compatible = "qcom,mdss_dsi_pll_msmfalcon"; - status = "ok"; - label = "MDSS DSI 0 PLL"; - cell-index = <0>; - #clock-cells = <1>; - - reg = <0xc994400 0x588>, - <0xc8c2300 0x8>; - reg-names = "pll_base", "gdsc_base"; - - gdsc-supply = <&gdsc_mdss>; - - clocks = <&clock_mmss MMSS_MDSS_AHB_CLK>; - clock-names = "iface_clk"; - clock-rate = <0>; - qcom,dsi-pll-ssc-en; - qcom,dsi-pll-ssc-mode = "down-spread"; - - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "gdsc"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - - }; - }; - - mdss_dsi1_pll: qcom,mdss_dsi_pll@c996400 { - compatible = "qcom,mdss_dsi_pll_msmfalcon"; - status = "ok"; - label = "MDSS DSI 1 PLL"; - cell-index = <1>; - #clock-cells = <1>; - - reg = <0xc996400 0x588>, - <0xc8c2300 0x8>; - reg-names = "pll_base", "gdsc_base"; - - gdsc-supply = <&gdsc_mdss>; - - clocks = <&clock_mmss MMSS_MDSS_AHB_CLK>; - clock-names = "iface_clk"; - clock-rate = <0>; - qcom,dsi-pll-ssc-en; - qcom,dsi-pll-ssc-mode = "down-spread"; - - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "gdsc"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-mdss.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-mdss.dtsi deleted file mode 100644 index f7e1b053dbb2..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-mdss.dtsi +++ /dev/null @@ -1,579 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -&soc { - mdss_mdp: qcom,mdss_mdp@c900000 { - compatible = "qcom,mdss_mdp"; - status = "ok"; - reg = <0x0c900000 0x90000>, - <0x0c9b0000 0x1040>; - reg-names = "mdp_phys", "vbif_phys"; - interrupts = <0 83 0>; - interrupt-controller; - #interrupt-cells = <1>; - vdd-supply = <&gdsc_mdss>; - - /* Bus Scale Settings */ - qcom,msm-bus,name = "mdss_mdp"; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-KBps = - <22 512 0 0>, <23 512 0 0>, - <22 512 0 6400000>, <23 512 0 6400000>, - <22 512 0 6400000>, <23 512 0 6400000>; - - /* Fudge factors */ - qcom,mdss-ab-factor = <1 1>; /* 1 time */ - qcom,mdss-ib-factor = <1 1>; /* 1 time */ - qcom,mdss-clk-factor = <105 100>; /* 1.05 times */ - - qcom,max-mixer-width = <2560>; - qcom,max-pipe-width = <2560>; - - qcom,max-dest-scaler-input-width = <2048>; - qcom,max-dest-scaler-output-width = <2560>; - - /* VBIF QoS remapper settings*/ - qcom,mdss-vbif-qos-rt-setting = <1 2 2 2>; - qcom,vbif-settings = <0x00ac 0x00000040>, - <0x00d0 0x00001010>; /* v1 only */ - - qcom,mdss-has-panic-ctrl; - qcom,mdss-per-pipe-panic-luts = <0x000f>, - <0xffff>, - <0xfffc>, - <0xff00>; - - qcom,mdss-mdp-reg-offset = <0x00001000>; - qcom,max-bandwidth-low-kbps = <6600000>; - qcom,max-bandwidth-high-kbps = <6600000>; - qcom,max-bandwidth-per-pipe-kbps = <3100000>; - qcom,max-clk-rate = <412500000>; - qcom,mdss-default-ot-rd-limit = <32>; - qcom,mdss-default-ot-wr-limit = <40>; - qcom,mdss-dram-channels = <2>; - - /* Bandwidth limit settings */ - qcom,max-bw-settings = <1 6600000>, /* Default */ - <2 4500000>; /* Camera */ - - qcom,mdss-pipe-vig-off = <0x00005000 0x00007000>; - qcom,mdss-pipe-dma-off = <0x00025000 0x00027000 - 0x00029000>; - qcom,mdss-pipe-cursor-off = <0x00035000>; - - qcom,mdss-pipe-vig-xin-id = <0 4>; - qcom,mdss-pipe-dma-xin-id = <1 5 9>; - qcom,mdss-pipe-cursor-xin-id = <2>; - - /* These Offsets are relative to - * "mdp_phys + mdp-reg-offset" address - */ - qcom,mdss-pipe-vig-clk-ctrl-offsets = <0x2ac 0 0>, - <0x2b4 0 0>; - qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x2ac 8 12>, - <0x2b4 8 12>, - <0x2c4 8 12>; - qcom,mdss-pipe-cursor-clk-ctrl-offsets = <0x3a8 16 15>; - - qcom,mdss-ctl-off = <0x00002000 0x00002200 0x00002400 - 0x00002600 0x00002800>; - qcom,mdss-mixer-intf-off = <0x00045000 0x00046000 - 0x00047000 0x0004a000>; - qcom,mdss-dspp-off = <0x00055000 0x00057000>; - qcom,mdss-wb-off = <0x00066000>; - qcom,mdss-intf-off = <0x0006b000 0x0006b800 - 0x0006c000 0x0006c800>; - qcom,mdss-pingpong-off = <0x00071000 0x00071800 - 0x00072000 0x00072800>; - qcom,mdss-slave-pingpong-off = <0x00073000>; - qcom,mdss-ppb-ctl-off = <0x00000330 0x00000338 0x00000370 - 0x00000374> ; - qcom,mdss-ppb-cfg-off = <0x00000334 0x0000033C>; - qcom,mdss-has-pingpong-split; - qcom,mdss-has-separate-rotator; - - qcom,mdss-ad-off = <0x0079000 0x00079800>; - qcom,mdss-cdm-off = <0x0007a200>; - qcom,mdss-dsc-off = <0x00081000 0x00081400>; - qcom,mdss-wfd-mode = "intf"; - qcom,mdss-has-source-split; - qcom,mdss-highest-bank-bit = <0x1>; - qcom,mdss-has-decimation; - qcom,mdss-idle-power-collapse-enabled; - clocks = <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_mmss MMSS_MDSS_AHB_CLK>, - <&clock_mmss MMSS_MDSS_AXI_CLK>, - <&clock_mmss MDP_CLK_SRC>, - <&clock_mmss MMSS_MDSS_MDP_CLK>, - <&clock_mmss MMSS_MDSS_VSYNC_CLK>, - <&clock_mmss MDP_CLK_SRC>; - clock-names = "mnoc_clk", "iface_clk", "bus_clk", - "core_clk_src", "core_clk", "vsync_clk", - "lut_clk"; - - qcom,mdp-settings = <0x01190 0x00000000>, - <0x012ac 0xc0000ccc>, - <0x012b4 0xc0000ccc>, - <0x012bc 0x00cccccc>, - <0x012c4 0x000000cc>, - <0x013a8 0x0cccc0c0>, - <0x013b0 0xccccc0c0>, - <0x013b8 0xcccc0000>, - <0x013d0 0x00cc0000>, - <0x0506c 0x00000000>, - <0x0706c 0x00000000>, - <0x0906c 0x00000000>, - <0x0b06c 0x00000000>, - <0x1506c 0x00000000>, - <0x1706c 0x00000000>, - <0x1906c 0x00000000>, - <0x1b06c 0x00000000>, - <0x2506c 0x00000000>, - <0x2706c 0x00000000>; - - qcom,regs-dump-mdp = <0x01000 0x01458>, - <0x02000 0x02094>, - <0x02200 0x02294>, - <0x02400 0x02494>, - <0x02600 0x02694>, - <0x02800 0x02894>, - <0x05000 0x05154>, - <0x05a00 0x05b00>, - <0x07000 0x07154>, - <0x07a00 0x07b00>, - <0x25000 0x25184>, - <0x27000 0x27184>, - <0x29000 0x29184>, - <0x35000 0x35150>, - <0x45000 0x452bc>, - <0x46000 0x462bc>, - <0x47000 0x472bc>, - <0x4a000 0x4a2bc>, - <0x55000 0x5522c>, - <0x57000 0x5722c>, - <0x66000 0x662c0>, - <0x6b000 0x6b268>, - <0x6b800 0x6ba68>, - <0x6c000 0x6c268>, - <0x71000 0x710d4>, - <0x71800 0x718d4>, - <0x73000 0x730d4>, - <0x81000 0x81140>, - <0x81400 0x81540>; - - qcom,regs-dump-names-mdp = "MDP", - "CTL_0", "CTL_1", "CTL_2", "CTL_3", "CTL_4", - "VIG0_SSPP", "VIG0", "VIG1_SSPP", "VIG1", - "DMA0_SSPP", "DMA1_SSPP","DMA2_SSPP", - "CURSOR0_SSPP", - "LAYER_0", "LAYER_1", "LAYER_2", - "LAYER_5", - "DSPP_0", "DSPP_1", - "WB_2", - "INTF_0", "INTF_1", "INTF_2", - "PP_0", "PP_1", "PP_4", - "DSC_0", "DSC_1"; - - /* buffer parameters to calculate prefill bandwidth */ - qcom,mdss-prefill-outstanding-buffer-bytes = <0>; - qcom,mdss-prefill-y-buffer-bytes = <0>; - qcom,mdss-prefill-scaler-buffer-lines-bilinear = <2>; - qcom,mdss-prefill-scaler-buffer-lines-caf = <4>; - qcom,mdss-prefill-post-scaler-buffer-pixels = <2560>; - qcom,mdss-prefill-pingpong-buffer-pixels = <5120>; - - qcom,mdss-pp-offsets { - qcom,mdss-sspp-mdss-igc-lut-off = <0x2000>; - qcom,mdss-sspp-vig-pcc-off = <0x1b00>; - qcom,mdss-sspp-rgb-pcc-off = <0x380>; - qcom,mdss-sspp-dma-pcc-off = <0x380>; - qcom,mdss-lm-pgc-off = <0x3c0>; - qcom,mdss-dspp-gamut-off = <0x1600>; - qcom,mdss-dspp-pcc-off = <0x1700>; - qcom,mdss-dspp-pgc-off = <0x17c0>; - }; - - qcom,mdss-scaler-offsets { - qcom,mdss-vig-scaler-off = <0xa00>; - qcom,mdss-vig-scaler-lut-off = <0xb00>; - qcom,mdss-has-dest-scaler; - qcom,mdss-dest-block-off = <0x00061000>; - qcom,mdss-dest-scaler-off = <0x800 0x1000>; - qcom,mdss-dest-scaler-lut-off = <0x900 0x1100>; - }; - - smmu_mdp_unsec: qcom,smmu_mdp_unsec_cb { - compatible = "qcom,smmu_mdp_unsec"; - iommus = <&mmss_bimc_smmu 0>; - gdsc-mmagic-mdss-supply = <&gdsc_bimc_smmu>; - clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, - <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>; - clock-names = "mmss_noc_axi_clk", - "mmss_noc_ahb_clk", - "mmss_smmu_ahb_clk", - "mmss_smmu_axi_clk"; - }; - - smmu_mdp_sec: qcom,smmu_mdp_sec_cb { - compatible = "qcom,smmu_mdp_sec"; - iommus = <&mmss_bimc_smmu 1>; - gdsc-mmagic-mdss-supply = <&gdsc_bimc_smmu>; - clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, - <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>; - clock-names = "mmss_noc_axi_clk", - "mmss_noc_ahb_clk", - "mmss_smmu_ahb_clk", - "mmss_smmu_axi_clk"; - }; - - mdss_fb0: qcom,mdss_fb_primary { - cell-index = <0>; - compatible = "qcom,mdss-fb"; - }; - - mdss_fb1: qcom,mdss_fb_wfd { - cell-index = <1>; - compatible = "qcom,mdss-fb"; - }; - - mdss_fb2: qcom,mdss_fb_dp { - cell-index = <2>; - compatible = "qcom,mdss-fb"; - qcom,mdss-intf = <&mdss_dp_ctrl>; - }; - - }; - - mdss_dsi: qcom,mdss_dsi@0 { - compatible = "qcom,mdss-dsi"; - #address-cells = <1>; - #size-cells = <1>; - gdsc-supply = <&gdsc_mdss>; - vdda-1p2-supply = <&pmfalcon_l1>; - vdda-0p9-supply = <&pm2falcon_l1>; - ranges = <0xc994000 0xc994000 0x400 - 0xc994400 0xc994400 0x588 - 0xc828000 0xc828000 0xac - 0xc996000 0xc996000 0x400 - 0xc996400 0xc996400 0x588 - 0xc828000 0xc828000 0xac>; - - /* Bus Scale Settings */ - qcom,msm-bus,name = "mdss_dsi"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <22 512 0 0>, - <22 512 0 1000>; - - qcom,mmss-ulp-clamp-ctrl-offset = <0x14>; - - clocks = <&clock_mmss MMSS_MDSS_MDP_CLK>, - <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_mmss MMSS_MDSS_AHB_CLK>, - <&clock_mmss MMSS_MDSS_AXI_CLK>, - <&clock_mmss MMSS_MISC_AHB_CLK>, - <&mdss_dsi0_pll BYTE0_MUX_CLK>, - <&mdss_dsi1_pll BYTE1_MUX_CLK>, - <&mdss_dsi0_pll PIX0_MUX_CLK>, - <&mdss_dsi1_pll PIX1_MUX_CLK>; - clock-names = "mdp_core_clk", - "mnoc_clk", "iface_clk", - "bus_clk", "core_mmss_clk", - "ext_byte0_clk", "ext_byte1_clk", - "ext_pixel0_clk", "ext_pixel1_clk"; - - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "gdsc"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1250000>; - qcom,supply-enable-load = <12560>; - qcom,supply-disable-load = <4>; - }; - }; - - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <925000>; - qcom,supply-enable-load = <73400>; - qcom,supply-disable-load = <32>; - }; - }; - - mdss_dsi0: qcom,mdss_dsi_ctrl0@c994000 { - compatible = "qcom,mdss-dsi-ctrl"; - label = "MDSS DSI CTRL->0"; - cell-index = <0>; - reg = <0xc994000 0x400>, - <0xc994400 0x588>, - <0xc828000 0xac>; - reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys"; - - qcom,timing-db-mode; - wqhd-vddio-supply = <&pmfalcon_l11>; - lab-supply = <&lcdb_ldo_vreg>; - ibb-supply = <&lcdb_ncp_vreg>; - qcom,mdss-mdp = <&mdss_mdp>; - qcom,mdss-fb-map = <&mdss_fb0>; - - clocks = <&clock_mmss MMSS_MDSS_BYTE0_CLK>, - <&clock_mmss MMSS_MDSS_PCLK0_CLK>, - <&clock_mmss MMSS_MDSS_ESC0_CLK>, - <&clock_mmss BYTE0_CLK_SRC>, - <&clock_mmss PCLK0_CLK_SRC>, - <&clock_mmss MMSS_MDSS_BYTE0_INTF_CLK>; - clock-names = "byte_clk", "pixel_clk", "core_clk", - "byte_clk_rcg", "pixel_clk_rcg", - "byte_intf_clk"; - - qcom,platform-strength-ctrl = [ff 06 - ff 06 - ff 06 - ff 06 - ff 00]; - qcom,platform-regulator-settings = [1d - 1d 1d 1d 1d]; - qcom,platform-lane-config = [00 00 10 0f - 00 00 10 0f - 00 00 10 0f - 00 00 10 0f - 00 00 10 8f]; - }; - - mdss_dsi1: qcom,mdss_dsi_ctrl1@c996000 { - compatible = "qcom,mdss-dsi-ctrl"; - label = "MDSS DSI CTRL->1"; - cell-index = <1>; - reg = <0xc996000 0x400>, - <0xc996400 0x588>, - <0xc828000 0xac>; - reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys"; - - qcom,timing-db-mode; - wqhd-vddio-supply = <&pmfalcon_l11>; - lab-supply = <&lcdb_ldo_vreg>; - ibb-supply = <&lcdb_ncp_vreg>; - qcom,mdss-mdp = <&mdss_mdp>; - qcom,mdss-fb-map = <&mdss_fb0>; - - clocks = <&clock_mmss MMSS_MDSS_BYTE1_CLK>, - <&clock_mmss MMSS_MDSS_PCLK1_CLK>, - <&clock_mmss MMSS_MDSS_ESC1_CLK>, - <&clock_mmss BYTE1_CLK_SRC>, - <&clock_mmss PCLK1_CLK_SRC>, - <&clock_mmss MMSS_MDSS_BYTE1_INTF_CLK>; - clock-names = "byte_clk", "pixel_clk", "core_clk", - "byte_clk_rcg", "pixel_clk_rcg", - "byte_intf_clk"; - - qcom,platform-strength-ctrl = [ff 06 - ff 06 - ff 06 - ff 06 - ff 00]; - qcom,platform-regulator-settings = [1d - 1d 1d 1d 1d]; - qcom,platform-lane-config = [00 00 10 0f - 00 00 10 0f - 00 00 10 0f - 00 00 10 0f - 00 00 10 8f]; - }; - }; - - qcom,mdss_wb_panel { - compatible = "qcom,mdss_wb"; - qcom,mdss_pan_res = <640 480>; - qcom,mdss_pan_bpp = <24>; - qcom,mdss-fb-map = <&mdss_fb1>; - }; - - msm_ext_disp: qcom,msm_ext_disp { - status = "disabled"; - compatible = "qcom,msm-ext-disp"; - - ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { - compatible = "qcom,msm-ext-disp-audio-codec-rx"; - qcom,msm_ext_disp = <&msm_ext_disp>; - }; - }; - - mdss_dp_ctrl: qcom,dp_ctrl@c990000 { - status = "disabled"; - cell-index = <0>; - compatible = "qcom,mdss-dp"; - qcom,mdss-fb-map = <&mdss_fb2>; - - gdsc-supply = <&gdsc_mdss>; - vdda-1p2-supply = <&pmfalcon_l1>; - vdda-0p9-supply = <&pm2falcon_l1>; - - reg = <0xc990000 0xa84>, - <0xc011000 0x910>, - <0x1fcb200 0x050>, - <0xc8c2200 0x1a0>, - <0x780000 0x621c>, - <0xc9e1000 0x02c>; - reg-names = "dp_ctrl", "dp_phy", "tcsr_regs", "dp_mmss_cc", - "qfprom_physical","hdcp_physical"; - - qcom,msm_ext_disp = <&msm_ext_disp>; - - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "gdsc"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1250000>; - qcom,supply-enable-load = <12560>; - qcom,supply-disable-load = <4>; - }; - }; - - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <925000>; - qcom,supply-enable-load = <73400>; - qcom,supply-disable-load = <32>; - }; - }; - }; - - mdss_rotator: qcom,mdss_rotator { - compatible = "qcom,sde_rotator"; - reg = <0x0c900000 0xab100>, - <0x0c9b0000 0x1040>; - reg-names = "mdp_phys", - "rot_vbif_phys"; - - qcom,mdss-rot-mode = <1>; - qcom,mdss-highest-bank-bit = <0x2>; - - /* Bus Scale Settings */ - qcom,msm-bus,name = "mdss_rotator"; - qcom,msm-bus,num-cases = <3>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <22 512 0 0>, - <22 512 0 6400000>, - <22 512 0 6400000>; - - rot-vdd-supply = <&gdsc_mdss>; - qcom,supply-names = "rot-vdd"; - - clocks = <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_mmss MMSS_MDSS_AHB_CLK>, - <&clock_mmss ROT_CLK_SRC>, - <&clock_mmss MMSS_MDSS_ROT_CLK>, - <&clock_mmss MMSS_MDSS_AXI_CLK>; - clock-names = "mnoc_clk", - "iface_clk", "rot_core_clk", - "rot_clk", "axi_clk"; - - interrupt-parent = <&mdss_mdp>; - interrupts = <2 0>; - - /* VBIF QoS remapper settings*/ - qcom,mdss-rot-vbif-qos-setting = <1 1 1 1>; - - qcom,mdss-default-ot-rd-limit = <32>; - qcom,mdss-default-ot-wr-limit = <40>; - - smmu_rot_unsec: qcom,smmu_rot_unsec_cb { - compatible = "qcom,smmu_sde_rot_unsec"; - iommus = <&mmss_bimc_smmu 0xe00>; - gdsc-mdss-supply = <&gdsc_bimc_smmu>; - - clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, - <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>; - clock-names = "mmss_noc_axi_clk", - "mmss_noc_ahb_clk", - "mmss_smmu_ahb_clk", - "mmss_smmu_axi_clk"; - }; - - smmu_rot_sec: qcom,smmu_rot_sec_cb { - compatible = "qcom,smmu_sde_rot_sec"; - iommus = <&mmss_bimc_smmu 0xe01>; - gdsc-mdss-supply = <&gdsc_bimc_smmu>; - - clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, - <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>; - clock-names = "mmss_noc_axi_clk", - "mmss_noc_ahb_clk", - "mmss_smmu_ahb_clk", - "mmss_smmu_axi_clk"; - }; - }; - -}; - -#include "msmfalcon-mdss-panels.dtsi" diff --git a/arch/arm/boot/dts/qcom/msmfalcon-mtp.dts b/arch/arm/boot/dts/qcom/msmfalcon-mtp.dts deleted file mode 100644 index cefe0d7c275b..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-mtp.dts +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "msmfalcon.dtsi" -#include "msmfalcon-mtp.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON MTP"; - compatible = "qcom,msmfalcon-mtp", "qcom,msmfalcon", "qcom,mtp"; - qcom,board-id = <8 0>; - qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, - <0x0001001b 0x0201011a 0x0 0x0>; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-mtp.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-mtp.dtsi deleted file mode 100644 index a9d77583b590..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-mtp.dtsi +++ /dev/null @@ -1,99 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "msmfalcon-pinctrl.dtsi" -#include "msmfalcon-camera-sensor-mtp.dtsi" -/ { -}; - -&uartblsp1dm1 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&uart_console_active>; -}; - -&ufsphy1 { - vdda-phy-supply = <&pm2falcon_l1>; - vdda-pll-supply = <&pmfalcon_l10>; - vddp-ref-clk-supply = <&pmfalcon_l1>; - vdda-phy-max-microamp = <51400>; - vdda-pll-max-microamp = <14200>; - vddp-ref-clk-max-microamp = <100>; - vddp-ref-clk-always-on; - status = "ok"; -}; - -&ufs1 { - vdd-hba-supply = <&gdsc_ufs>; - vdd-hba-fixed-regulator; - vcc-supply = <&pm2falcon_l4>; - vccq2-supply = <&pmfalcon_l8>; - vcc-max-microamp = <500000>; - vccq2-max-microamp = <600000>; - status = "ok"; -}; - -&mdss_mdp { - qcom,mdss-pref-prim-intf = "dsi"; -}; - -&mdss_dsi { - hw-config = "split_dsi"; -}; - -&mdss_dsi0 { - qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; - pinctrl-names = "mdss_default", "mdss_sleep"; - pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; - pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; - qcom,platform-reset-gpio = <&tlmm 53 0>; - qcom,platform-te-gpio = <&tlmm 59 0>; -}; - -&mdss_dsi1 { - qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; - pinctrl-names = "mdss_default", "mdss_sleep"; - pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; - pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; - qcom,platform-reset-gpio = <&tlmm 53 0>; - qcom,platform-te-gpio = <&tlmm 59 0>; -}; - -&pm2falcon_wled { - qcom,led-strings-list = [01 02]; -}; - -&dsi_dual_nt35597_truly_video { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&dsi_dual_nt35597_truly_cmd { - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; -}; - -&soc { - qcom,msm-ssc-sensors { - compatible = "qcom,msm-ssc-sensors"; - }; -}; - -&mem_client_3_size { - qcom,peripheral-size = <0x500000>; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi deleted file mode 100644 index a54079413e7c..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi +++ /dev/null @@ -1,1293 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -&soc { - tlmm: pinctrl@03000000 { - compatible = "qcom,msmfalcon-pinctrl"; - reg = <0x03000000 0xc00000>; - interrupts = <0 208 0>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - - uart_console_active: uart_console_active { - mux { - pins = "gpio4", "gpio5"; - function = "blsp_uart2"; - }; - - config { - pins = "gpio4", "gpio5"; - drive-strength = <2>; - bias-disable; - }; - }; - - led_enable: led_enable { - mux { - pins = "gpio40"; - drive_strength = <16>; - output-high; - }; - }; - - led_disable: led_disable { - mux { - pins = "gpio40"; - drive_strength = <2>; - output-low; - }; - }; - - trigout_b: trigout_b { - mux { - pins = "gpio12"; - function = "qdss_cti1_b"; - }; - - config { - pins = "gpio12"; - drive-strength = <16>; - bias-disable; - }; - }; - - /* SDC pin type */ - sdc1_clk_on: sdc1_clk_on { - config { - pins = "sdc1_clk"; - bias-disable; /* NO pull */ - drive-strength = <16>; /* 16 MA */ - }; - }; - - sdc1_clk_off: sdc1_clk_off { - config { - pins = "sdc1_clk"; - bias-disable; /* NO pull */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc1_cmd_on: sdc1_cmd_on { - config { - pins = "sdc1_cmd"; - bias-pull-up; /* pull up */ - drive-strength = <10>; /* 10 MA */ - }; - }; - - sdc1_cmd_off: sdc1_cmd_off { - config { - pins = "sdc1_cmd"; - num-grp-pins = <1>; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc1_data_on: sdc1_data_on { - config { - pins = "sdc1_data"; - bias-pull-up; /* pull up */ - drive-strength = <10>; /* 10 MA */ - }; - }; - - sdc1_data_off: sdc1_data_off { - config { - pins = "sdc1_data"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - sdc1_rclk_on: sdc1_rclk_on { - config { - pins = "sdc1_rclk"; - bias-pull-down; /* pull down */ - }; - }; - - sdc1_rclk_off: sdc1_rclk_off { - config { - pins = "sdc1_rclk"; - bias-pull-down; /* pull down */ - }; - }; - - /* I2C CONFIGURATION */ - i2c_1 { - i2c_1_active: i2c_1_active { - mux { - pins = "gpio2", "gpio3"; - function = "blsp_i2c1"; - }; - - config { - pins = "gpio2", "gpio3"; - drive-strength = <2>; - bias-disable; - }; - }; - - i2c_1_sleep: i2c_1_sleep { - mux { - pins = "gpio2", "gpio3"; - function = "blsp_i2c1"; - }; - - config { - pins = "gpio2", "gpio3"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - i2c_2 { - i2c_2_active: i2c_2_active { - mux { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - }; - - config { - pins = "gpio6", "gpio7"; - drive-strength = <2>; - bias-disable; - }; - }; - - i2c_2_sleep: i2c_2_sleep { - mux { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - }; - - config { - pins = "gpio6", "gpio7"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - i2c_3 { - i2c_3_active: i2c_3_active { - mux { - pins = "gpio10", "gpio11"; - function = "blsp_i2c3"; - }; - - config { - pins = "gpio10", "gpio11"; - drive-strength = <2>; - bias-disable; - }; - }; - - i2c_3_sleep: i2c_3_sleep { - mux { - pins = "gpio10", "gpio11"; - function = "blsp_i2c3"; - }; - - config { - pins = "gpio10", "gpio11"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - i2c_4 { - i2c_4_active: i2c_4_active { - mux { - pins = "gpio14", "gpio15"; - function = "blsp_i2c4"; - }; - - config { - pins = "gpio14", "gpio15"; - drive-strength = <2>; - bias-disable; - }; - }; - - i2c_4_sleep: i2c_4_sleep { - mux { - pins = "gpio14", "gpio15"; - function = "blsp_i2c4"; - }; - - config { - pins = "gpio14", "gpio15"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - i2c_5 { - i2c_5_active: i2c_5_active { - mux { - pins = "gpio18", "gpio19"; - function = "blsp_i2c5"; - }; - - config { - pins = "gpio18", "gpio19"; - drive-strength = <2>; - bias-disable; - }; - }; - - i2c_5_sleep: i2c_5_sleep { - mux { - pins = "gpio18", "gpio19"; - function = "blsp_i2c5"; - }; - - config { - pins = "gpio18", "gpio19"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - i2c_6 { - i2c_6_active: i2c_6_active { - mux { - pins = "gpio22", "gpio23"; - function = "blsp_i2c6"; - }; - - config { - pins = "gpio22", "gpio23"; - drive-strength = <2>; - bias-disable; - }; - }; - - i2c_6_sleep: i2c_6_sleep { - mux { - pins = "gpio22", "gpio23"; - function = "blsp_i2c6"; - }; - - config { - pins = "gpio22", "gpio23"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - i2c_7 { - i2c_7_active: i2c_7_active { - mux { - pins = "gpio26", "gpio27"; - function = "blsp_i2c7"; - }; - - config { - pins = "gpio26", "gpio27"; - drive-strength = <2>; - bias-disable; - }; - }; - - i2c_7_sleep: i2c_7_sleep { - mux { - pins = "gpio26", "gpio27"; - function = "blsp_i2c7"; - }; - - config { - pins = "gpio26", "gpio27"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - i2c_8 { - i2c_8_active: i2c_8_active { - mux { - pins = "gpio30", "gpio31"; - function = "blsp_i2c8_a"; - }; - - config { - pins = "gpio30", "gpio31"; - drive-strength = <2>; - bias-disable; - }; - }; - - i2c_8_sleep: i2c_8_sleep { - mux { - pins = "gpio30", "gpio31"; - function = "blsp_i2c8_a"; - }; - - config { - pins = "gpio30", "gpio31"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - /* SPI CONFIGURATION */ - spi_1 { - spi_1_active: spi_1_active { - mux { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - function = "blsp_spi1"; - }; - - config { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - drive-strength = <6>; - bias-disable; - }; - }; - - spi_1_sleep: spi_1_sleep { - mux { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - function = "blsp_spi1"; - }; - - config { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - spi_2 { - spi_2_active: spi_2_active { - mux { - pins = "gpio4", "gpio5", - "gpio6", "gpio7"; - function = "blsp_spi2"; - }; - - config { - pins = "gpio4", "gpio5", - "gpio6", "gpio7"; - drive-strength = <6>; - bias-disable; - }; - }; - - spi_2_sleep: spi_2_sleep { - mux { - pins = "gpio4", "gpio5", - "gpio6", "gpio7"; - function = "blsp_spi2"; - }; - - config { - pins = "gpio4", "gpio5", - "gpio6", "gpio7"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - spi_3 { - spi_3_active: spi_3_active { - mux { - pins = "gpio8", "gpio9", - "gpio10", "gpio11"; - function = "blsp_spi3"; - }; - - config { - pins = "gpio8", "gpio9", - "gpio10", "gpio11"; - drive-strength = <6>; - bias-disable; - }; - }; - - spi_3_sleep: spi_3_sleep { - mux { - pins = "gpio8", "gpio9", - "gpio10", "gpio11"; - function = "blsp_spi3"; - }; - - config { - pins = "gpio8", "gpio9", - "gpio10", "gpio11"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - spi_4 { - spi_4_active: spi_4_active { - mux { - pins = "gpio12", "gpio13", - "gpio14", "gpio15"; - function = "blsp_spi4"; - }; - - config { - pins = "gpio12", "gpio13", - "gpio14", "gpio15"; - drive-strength = <6>; - bias-disable; - }; - }; - - spi_4_sleep: spi_4_sleep { - mux { - pins = "gpio12", "gpio13", - "gpio14", "gpio15"; - function = "blsp_spi4"; - }; - - config { - pins = "gpio12", "gpio13", - "gpio14", "gpio15"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - spi_5 { - spi_5_active: spi_5_active { - mux { - pins = "gpio16", "gpio17", - "gpio18", "gpio19"; - function = "blsp_spi5"; - }; - - config { - pins = "gpio16", "gpio17", - "gpio18", "gpio19"; - drive-strength = <6>; - bias-disable; - }; - }; - - spi_5_sleep: spi_5_sleep { - mux { - pins = "gpio16", "gpio17", - "gpio18", "gpio19"; - function = "blsp_spi5"; - }; - - config { - pins = "gpio16", "gpio17", - "gpio18", "gpio19"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - spi_6 { - spi_6_active: spi_6_active { - mux { - pins = "gpio49", "gpio52", - "gpio22", "gpio23"; - function = "blsp_spi6"; - }; - - config { - pins = "gpio49", "gpio52", - "gpio22", "gpio23"; - drive-strength = <6>; - bias-disable; - }; - }; - - spi_6_sleep: spi_6_sleep { - mux { - pins = "gpio49", "gpio52", - "gpio22", "gpio23"; - function = "blsp_spi6"; - }; - - config { - pins = "gpio49", "gpio52", - "gpio22", "gpio23"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - spi_7 { - spi_7_active: spi_7_active { - mux { - pins = "gpio24", "gpio25", - "gpio26", "gpio27"; - function = "blsp_spi7"; - }; - - config { - pins = "gpio24", "gpio25", - "gpio26", "gpio27"; - drive-strength = <6>; - bias-disable; - }; - }; - - spi_7_sleep: spi_7_sleep { - mux { - pins = "gpio24", "gpio25", - "gpio26", "gpio27"; - function = "blsp_spi7"; - }; - - config { - pins = "gpio24", "gpio25", - "gpio26", "gpio27"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - spi_8 { - spi_8_active: spi_8_active { - mux { - pins = "gpio28", "gpio29", - "gpio30", "gpio31"; - function = "blsp_spi8_a"; - }; - - config { - pins = "gpio28", "gpio29", - "gpio30", "gpio31"; - drive-strength = <6>; - bias-disable; - }; - }; - - spi_8_sleep: spi_8_sleep { - mux { - pins = "gpio28", "gpio29", - "gpio30", "gpio31"; - function = "blsp_spi8_a"; - }; - - config { - pins = "gpio28", "gpio29", - "gpio30", "gpio31"; - drive-strength = <6>; - bias-disable; - }; - }; - }; - - sdw_clk_pin { - sdw_clk_sleep: sdw_clk_sleep { - mux { - pins = "gpio24"; - function = "sndwire_clk"; - }; - - config { - pins = "gpio24"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - sdw_clk_active: sdw_clk_active { - mux { - pins = "gpio24"; - function = "sndwire_clk"; - }; - - config { - pins = "gpio24"; - drive-strength = <16>; - bias-disable; - }; - }; - }; - - sdw_clk_data { - sdw_data_sleep: sdw_data_sleep { - mux { - pins = "gpio25"; - function = "sndwire_data"; - }; - - config { - pins = "gpio25"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - sdw_data_active: sdw_data_active { - mux { - pins = "gpio25"; - function = "sndwire_data"; - }; - - config { - pins = "gpio25"; - drive-strength = <16>; - bias-disable; - }; - }; - }; - - /* WSA speaker reset pins */ - spkr_1_sd_n { - spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { - mux { - pins = "gpio26"; - function = "gpio"; - }; - - config { - pins = "gpio26"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; - input-enable; - }; - }; - - spkr_1_sd_n_active: spkr_1_sd_n_active { - mux { - pins = "gpio26"; - function = "gpio"; - }; - - config { - pins = "gpio26"; - drive-strength = <16>; /* 16 mA */ - bias-disable; - output-high; - }; - }; - }; - - spkr_2_sd_n { - spkr_2_sd_n_sleep: spkr_2_sd_n_sleep { - mux { - pins = "gpio27"; - function = "gpio"; - }; - - config { - pins = "gpio27"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; - input-enable; - }; - }; - - spkr_2_sd_n_active: spkr_2_sd_n_active { - mux { - pins = "gpio27"; - function = "gpio"; - }; - - config { - pins = "gpio27"; - drive-strength = <16>; /* 16 mA */ - bias-disable; - output-high; - }; - }; - }; - - wcd_gnd_mic_swap { - wcd_gnd_mic_swap_idle: wcd_gnd_mic_swap_idle { - mux { - pins = "gpio63"; - function = "gpio"; - }; - config { - pins = "gpio63"; - drive-strength = <2>; - bias-pull-down; - output-low; - }; - }; - - wcd_gnd_mic_swap_active: wcd_gnd_mic_swap_active { - mux { - pins = "gpio63"; - function = "gpio"; - }; - config { - pins = "gpio63"; - drive-strength = <2>; - bias-disable; - output-high; - }; - }; - }; - - msm_hph_en0 { - hph_en0_sleep: hph_en0_sleep { - mux { - pins = "gpio24"; - function = "gpio"; - }; - - config { - pins = "gpio24"; - output-low; - }; - }; - - hph_en0_active: hph_en0_active { - mux { - pins = "gpio24"; - function = "gpio"; - }; - - config { - pins = "gpio24"; - output-high; - }; - }; - }; - - msm_hph_en1 { - hph_en1_sleep: hph_en1_sleep { - mux { - pins = "gpio25"; - function = "gpio"; - }; - - config { - pins = "gpio25"; - output-low; - }; - }; - - hph_en1_active: hph_en1_active { - mux { - pins = "gpio25"; - function = "gpio"; - }; - - config { - pins = "gpio25"; - output-high; - }; - }; - }; - - cci0_active: cci0_active { - mux { - /* CLK, DATA */ - pins = "gpio36","gpio37"; // Only 2 - function = "cci_i2c"; - }; - - config { - pins = "gpio36","gpio37"; - bias-pull-up; /* PULL UP*/ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cci0_suspend: cci0_suspend { - mux { - /* CLK, DATA */ - pins = "gpio36","gpio37"; - function = "cci_i2c"; - }; - - config { - pins = "gpio36","gpio37"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cci1_active: cci1_active { - mux { - /* CLK, DATA */ - pins = "gpio38","gpio39"; - function = "cci_i2c"; - }; - - config { - pins = "gpio38","gpio39"; - bias-pull-up; /* PULL UP*/ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cci1_suspend: cci1_suspend { - mux { - /* CLK, DATA */ - pins = "gpio38","gpio39"; - function = "cci_i2c"; - }; - - - config { - pins = "gpio38","gpio39"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_actuator_vaf_active: cam_actuator_vaf_active { - /* ACTUATOR POWER */ - mux { - pins = "gpio50"; - function = "gpio"; - }; - - config { - pins = "gpio50"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_actuator_vaf_suspend: cam_actuator_vaf_suspend { - /* ACTUATOR POWER */ - mux { - pins = "gpio50"; - function = "gpio"; - }; - - config { - pins = "gpio50"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_mclk0_active: cam_sensor_mclk0_active { - /* MCLK0 */ - mux { - /* CLK, DATA */ - pins = "gpio32"; - function = "cam_mclk"; - }; - - config { - pins = "gpio32"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { - /* MCLK0 */ - mux { - /* CLK, DATA */ - pins = "gpio32"; - function = "cam_mclk"; - }; - - config { - pins = "gpio32"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_rear_active: cam_sensor_rear_active { - /* RESET, STANDBY */ - mux { - pins = "gpio46","gpio44"; - function = "gpio"; - }; - - config { - pins = "gpio46","gpio44"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_rear_suspend: cam_sensor_rear_suspend { - /* RESET, STANDBY */ - mux { - pins = "gpio46","gpio44"; - function = "gpio"; - }; - - config { - pins = "gpio46","gpio44"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_mclk1_active: cam_sensor_mclk1_active { - /* MCLK1 */ - mux { - /* CLK, DATA */ - pins = "gpio33"; - function = "cam_mclk"; - }; - - config { - pins = "gpio33"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { - /* MCLK1 */ - mux { - /* CLK, DATA */ - pins = "gpio33"; - function = "cam_mclk"; - }; - - config { - pins = "gpio33"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_rear2_active: cam_sensor_rear2_active { - /* RESET, STANDBY */ - mux { - pins = "gpio48","gpio51"; - function = "gpio"; - }; - - config { - pins = "gpio48","gpio51"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_rear2_suspend: cam_sensor_rear2_suspend { - /* RESET, STANDBY */ - mux { - pins = "gpio48","gpio51"; - function = "gpio"; - }; - config { - pins = "gpio48","gpio51"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_mclk2_active: cam_sensor_mclk2_active { - /* MCLK1 */ - mux { - /* CLK, DATA */ - pins = "gpio34"; - function = "cam_mclk"; - }; - - config { - pins = "gpio34"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { - /* MCLK1 */ - mux { - /* CLK, DATA */ - pins = "gpio34"; - function = "cam_mclk"; - }; - - config { - pins = "gpio34"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_front_active: cam_sensor_front_active { - /* RESET VANA*/ - mux { - pins = "gpio47", "gpio44"; - function = "gpio"; - }; - - config { - pins = "gpio47", "gpio44"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - cam_sensor_front_suspend: cam_sensor_front_suspend { - /* RESET */ - mux { - pins = "gpio47"; - function = "gpio"; - }; - - config { - pins = "gpio47"; - bias-disable; /* No PULL */ - drive-strength = <2>; /* 2 MA */ - }; - }; - - /* HS UART CONFIGURATION */ - blsp1_uart1_active: blsp1_uart1_active { - mux { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "blsp_uart1"; - }; - - config { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp1_uart1_sleep: blsp1_uart1_sleep { - mux { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - function = "gpio"; - }; - - config { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp1_uart2_active: blsp1_uart2_active { - mux { - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - function = "blsp_uart2 "; - }; - - config { - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp1_uart2_sleep: blsp1_uart2_sleep { - mux { - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - function = "gpio"; - }; - - config { - pins = "gpio4", "gpio5", "gpio6", "gpio7"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_uart1_active: blsp2_uart1_active { - mux { - pins = "gpio16", "gpio17", "gpio18", "gpio19"; - function = "blsp_uart5"; - }; - - config { - pins = "gpio16", "gpio17", "gpio18", "gpio19"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_uart1_sleep: blsp2_uart1_sleep { - mux { - pins = "gpio16", "gpio17", "gpio18", "gpio19"; - function = "gpio"; - }; - - config { - pins = "gpio16", "gpio17", "gpio18", "gpio19"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_uart2_active: blsp2_uart2_active { - mux { - pins = "gpio24", "gpio25", "gpio26", "gpio27"; - function = "blsp_uart6_a"; - }; - - config { - pins = "gpio24", "gpio25", "gpio26", "gpio27"; - drive-strength = <2>; - bias-disable; - }; - }; - - blsp2_uart2_sleep: blsp2_uart2_sleep { - mux { - pins = "gpio24", "gpio25", "gpio26", "gpio27"; - function = "gpio"; - }; - - config { - pins = "gpio24", "gpio25", "gpio26", "gpio27"; - drive-strength = <2>; - bias-disable; - }; - }; - - tlmm_gpio_key { - gpio_key_active: gpio_key_active { - mux { - pins = "gpio64", "gpio113"; - function = "gpio"; - }; - - config { - pins = "gpio64", "gpio113"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - gpio_key_suspend: gpio_key_suspend { - mux { - pins = "gpio64", "gpio113"; - function = "gpio"; - }; - - config { - pins = "gpio64", "gpio113"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; - - pmx_mdss: pmx_mdss { - mdss_dsi_active: mdss_dsi_active { - mux { - pins = "gpio53"; - function = "gpio"; - }; - - config { - pins = "gpio53"; - drive-strength = <8>; /* 8 mA */ - bias-disable = <0>; /* no pull */ - }; - }; - mdss_dsi_suspend: mdss_dsi_suspend { - mux { - pins = "gpio53"; - function = "gpio"; - }; - - config { - pins = "gpio53"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* pull down */ - }; - }; - }; - - pmx_mdss_te { - mdss_te_active: mdss_te_active { - mux { - pins = "gpio59"; - function = "mdp_vsync_p"; - }; - config { - pins = "gpio59"; - drive-strength = <2>; /* 8 mA */ - bias-pull-down; /* pull down*/ - }; - }; - - mdss_te_suspend: mdss_te_suspend { - mux { - pins = "gpio59"; - function = "mdp_vsync_p"; - }; - config { - pins = "gpio59"; - drive-strength = <2>; /* 2 mA */ - bias-pull-down; /* pull down */ - }; - }; - }; - - ts_mux { - ts_active: ts_active { - mux { - pins = "gpio66", "gpio67"; - function = "gpio"; - }; - - config { - pins = "gpio66", "gpio67"; - drive-strength = <16>; - bias-pull-up; - }; - }; - - ts_reset_suspend: ts_reset_suspend { - mux { - pins = "gpio66"; - function = "gpio"; - }; - - config { - pins = "gpio66"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - ts_int_suspend: ts_int_suspend { - mux { - pins = "gpio67"; - function = "gpio"; - }; - - config { - pins = "gpio67"; - drive-strength = <2>; - bias-disable; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pm.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-pm.dtsi deleted file mode 100644 index 6a9fc5bde361..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-pm.dtsi +++ /dev/null @@ -1,821 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include - -&soc { - qcom,spm@178120000 { - compatible = "qcom,spm-v2"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x17812000 0x1000>; - qcom,name = "gold-l2"; /* Gold L2 SAW */ - qcom,saw2-ver-reg = <0xfd0>; - qcom,cpu-vctl-list = <&CPU4 &CPU5 &CPU6 &CPU7>; - qcom,vctl-timeout-us = <500>; - qcom,vctl-port = <0x0>; - qcom,phase-port = <0x1>; - qcom,saw2-avs-ctl = <0x1010031>; - qcom,saw2-avs-limit = <0x4580458>; - qcom,pfm-port = <0x2>; - }; - - qcom,spm@179120000 { - compatible = "qcom,spm-v2"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x17912000 0x1000>; - qcom,name = "silver-l2"; /* Silver L2 SAW */ - qcom,saw2-ver-reg = <0xfd0>; - qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>; - qcom,vctl-timeout-us = <500>; - qcom,vctl-port = <0x0>; - qcom,phase-port = <0x1>; - qcom,saw2-avs-ctl = <0x1010031>; - qcom,saw2-avs-limit = <0x4580458>; - qcom,pfm-port = <0x2>; - }; - - qcom,lpm-levels { - compatible = "qcom,lpm-levels"; - qcom,use-psci; - #address-cells = <1>; - #size-cells = <0>; - qcom,pm-cluster@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - label = "system"; - qcom,spm-device-names = "cci"; - qcom,psci-mode-shift = <8>; - qcom,psci-mode-mask = <0xf>; - - qcom,pm-cluster-level@0{ - reg = <0>; - label = "system-wfi"; - qcom,psci-mode = <0x0>; - qcom,latency-us = <100>; - qcom,ss-power = <725>; - qcom,energy-overhead = <85000>; - qcom,time-overhead = <120>; - }; - - qcom,pm-cluster-level@1{ /* E3 */ - reg = <1>; - label = "system-pc"; - qcom,psci-mode = <0x3>; - qcom,latency-us = <350>; - qcom,ss-power = <530>; - qcom,energy-overhead = <160000>; - qcom,time-overhead = <550>; - qcom,min-child-idx = <3>; - qcom,is-reset; - qcom,notify-rpm; - }; - - qcom,pm-cluster@0{ - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - label = "pwr"; - qcom,spm-device-names = "l2"; - qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>; - qcom,psci-mode-shift = <4>; - qcom,psci-mode-mask = <0xf>; - - qcom,pm-cluster-level@0{ /* D1 */ - reg = <0>; - label = "pwr-l2-wfi"; - qcom,psci-mode = <0x1>; - qcom,latency-us = <40>; - qcom,ss-power = <740>; - qcom,energy-overhead = <65000>; - qcom,time-overhead = <85>; - }; - qcom,pm-cluster-level@1{ /* D2D */ - reg = <1>; - label = "pwr-l2-dynret"; - qcom,psci-mode = <0x2>; - qcom,latency-us = <60>; - qcom,ss-power = <700>; - qcom,energy-overhead = <85000>; - qcom,time-overhead = <85>; - qcom,min-child-idx = <1>; - }; - - qcom,pm-cluster-level@2{ /* D2E */ - reg = <2>; - label = "pwr-l2-ret"; - qcom,psci-mode = <0x3>; - qcom,latency-us = <100>; - qcom,ss-power = <640>; - qcom,energy-overhead = <135000>; - qcom,time-overhead = <85>; - qcom,min-child-idx = <2>; - }; - - qcom,pm-cluster-level@3{ /* D4 */ - reg = <3>; - label = "pwr-l2-pc"; - qcom,psci-mode = <0x4>; - qcom,latency-us = <700>; - qcom,ss-power = <450>; - qcom,energy-overhead = <210000>; - qcom,time-overhead = <11500>; - qcom,min-child-idx = <2>; - qcom,is-reset; - }; - - qcom,pm-cpu { - #address-cells = <1>; - #size-cells = <0>; - qcom,psci-mode-shift = <0>; - qcom,psci-mode-mask = <0xf>; - - qcom,pm-cpu-level@0 { /* C1 */ - reg = <0>; - qcom,spm-cpu-mode = "wfi"; - qcom,psci-cpu-mode = <0x1>; - qcom,latency-us = <20>; - qcom,ss-power = <750>; - qcom,energy-overhead = <32000>; - qcom,time-overhead = <60>; - }; - - qcom,pm-cpu-level@1 { /* C2D */ - reg = <1>; - qcom,psci-cpu-mode = <2>; - qcom,spm-cpu-mode = "ret"; - qcom,latency-us = <40>; - qcom,ss-power = <730>; - qcom,energy-overhead = <85500>; - qcom,time-overhead = <110>; - }; - - qcom,pm-cpu-level@2 { /* C3 */ - reg = <2>; - qcom,spm-cpu-mode = "pc"; - qcom,psci-cpu-mode = <0x3>; - qcom,latency-us = <80>; - qcom,ss-power = <700>; - qcom,energy-overhead = <126480>; - qcom,time-overhead = <160>; - qcom,is-reset; - }; - }; - }; - - qcom,pm-cluster@1{ - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - label = "perf"; - qcom,spm-device-names = "l2"; - qcom,cpu = <&CPU4 &CPU5 &CPU6 &CPU7>; - qcom,psci-mode-shift = <4>; - qcom,psci-mode-mask = <0xf>; - - qcom,pm-cluster-level@0{ /* D1 */ - reg = <0>; - label = "perf-l2-wfi"; - qcom,psci-mode = <0x1>; - qcom,latency-us = <40>; - qcom,ss-power = <740>; - qcom,energy-overhead = <70000>; - qcom,time-overhead = <80>; - }; - - qcom,pm-cluster-level@1{ /* D2D */ - reg = <1>; - label = "perf-l2-dynret"; - qcom,psci-mode = <2>; - qcom,latency-us = <60>; - qcom,ss-power = <700>; - qcom,energy-overhead = <85000>; - qcom,time-overhead = <85>; - qcom,min-child-idx = <1>; - }; - - qcom,pm-cluster-level@2{ /* D2E */ - reg = <2>; - label = "perf-l2-ret"; - qcom,psci-mode = <3>; - qcom,latency-us = <100>; - qcom,ss-power = <640>; - qcom,energy-overhead = <135000>; - qcom,time-overhead = <85>; - qcom,min-child-idx = <2>; - }; - - qcom,pm-cluster-level@3{ /* D4 */ - reg = <3>; - label = "perf-l2-pc"; - qcom,psci-mode = <0x4>; - qcom,latency-us = <800>; - qcom,ss-power = <450>; - qcom,energy-overhead = <240000>; - qcom,time-overhead = <11500>; - qcom,min-child-idx = <2>; - qcom,is-reset; - }; - - qcom,pm-cpu { - #address-cells = <1>; - #size-cells = <0>; - qcom,psci-mode-shift = <0>; - qcom,psci-mode-mask = <0xf>; - - qcom,pm-cpu-level@0 { /* C1 */ - reg = <0>; - qcom,spm-cpu-mode = "wfi"; - qcom,psci-cpu-mode = <0x1>; - qcom,latency-us = <25>; - qcom,ss-power = <750>; - qcom,energy-overhead = <37000>; - qcom,time-overhead = <50>; - }; - - qcom,pm-cpu-level@1 { /* C2D */ - reg = <1>; - qcom,psci-cpu-mode = <2>; - qcom,spm-cpu-mode = "ret"; - qcom,latency-us = <40>; - qcom,ss-power = <730>; - qcom,energy-overhead = <85500>; - qcom,time-overhead = <110>; - }; - - qcom,pm-cpu-level@2 { /* C3 */ - reg = <2>; - qcom,spm-cpu-mode = "pc"; - qcom,psci-cpu-mode = <0x3>; - qcom,latency-us = <80>; - qcom,ss-power = <700>; - qcom,energy-overhead = <136480>; - qcom,time-overhead = <160>; - qcom,is-reset; - }; - }; - }; - }; - }; - - qcom,rpm-stats@200000 { - compatible = "qcom,rpm-stats"; - reg = <0x200000 0x1000>, - <0x290014 0x4>, - <0x29001c 0x4>; - reg-names = "phys_addr_base", - "offset_addr", - "heap_phys_addrbase"; - qcom,sleep-stats-version = <2>; - }; - - qcom,rpm-rail-stats@200000 { - compatible = "qcom,rpm-rail-stats"; - reg = <0x200000 0x100>, - <0x29000c 0x4>; - reg-names = "phys_addr_base", - "offset_addr"; - }; - - qcom,rpm-log@200000 { - compatible = "qcom,rpm-log"; - reg = <0x200000 0x4000>, - <0x290018 0x4>; - qcom,rpm-addr-phys = <0x200000>; - qcom,offset-version = <4>; - qcom,offset-page-buffer-addr = <36>; - qcom,offset-log-len = <40>; - qcom,offset-log-len-mask = <44>; - qcom,offset-page-indices = <56>; - }; - - qcom,rpm-master-stats@778150 { - compatible = "qcom,rpm-master-stats"; - reg = <0x778150 0x5000>; - qcom,masters = "APSS", "MPSS", "ADSP", "CDSP", "TZ"; - qcom,master-stats-version = <2>; - qcom,master-offset = <4096>; - }; - - rpm_msg_ram: memory@0x200000 { - compatible = "qcom,rpm-msg-ram"; - reg = <0x200000 0x1000>, - <0x290000 0x1000>; - }; - - rpm_code_ram: rpm-memory@0x778000 { - compatible = "qcom,rpm-code-ram"; - reg = <0x778000 0x5000>; - }; - - qcom,system-stats { - compatible = "qcom,system-stats"; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - qcom,rpm-code-ram = <&rpm_code_ram>; - qcom,masters = "APSS", "MPSS", "ADSP", "CDSP", "TZ"; - }; - - qcom,mpm@7781b8 { - compatible = "qcom,mpm-v2"; - reg = <0x7781b8 0x1000>, /* MSM_RPM_MPM_BASE 4K */ - <0x17911008 0x4>; /* MSM_APCS_GCC_BASE 4K */ - reg-names = "vmpm", "ipc"; - interrupts = ; - clocks = <&clock_rpmcc CXO_LPM_CLK>; - clock-names = "xo"; - qcom,num-mpm-irqs = <96>; - - qcom,ipc-bit-offset = <1>; - - qcom,gic-parent = <&intc>; - qcom,gic-map = - <0x02 216>, /* tsens1_tsens_upper_lower_int */ - <0x34 275>, /* qmp_usb3_lfps_rxterm_irq_cx */ - <0x4f 379>, /* qusb2phy_intr */ - <0x51 379>, /* qusb2phy_intr */ - <0x57 358>, /* ee0_apps_hlos_spmi_periph_irq */ - <0x5b 519>, /* lpass_pmu_tmr_timeout_irq_cx */ - <0xff 16>, /* APC[0-7]_qgicQTmrHypPhysIrptReq */ - <0xff 17>, /* APC[0-7]_qgicQTmrSecPhysIrptReq */ - <0xff 18>, /* APC[0-7]_qgicQTmrNonSecPhysIrptReq */ - <0xff 19>, /* APC[0-7]_qgicQTmrVirtIrptReq */ - <0xff 20>, /* APC[0-7]_dbgCommRxFull */ - <0xff 21>, /* APC[0-7]_dbgCommTxEmpty */ - <0xff 22>, /* APC[0-7]_qgicPerfMonIrptReq */ - <0xff 23>, /* corespm_vote_int[0-7] */ - <0xff 24>, /* APC[0-3]_qgicExtFaultIrptReq */ - <0xff 28>, /* qgicWakeupSync[0-7] */ - <0xff 29>, /* APCC_cti_SPI_intx[0-7] */ - <0xff 30>, /* APCC_cti_SPI_inty[0-7] */ - <0xff 32>, /* l2spm_vote_int[0] */ - <0xff 33>, /* l2spm_vote_int[1] */ - <0xff 34>, /* APCC_qgicL2ErrorIrptReq */ - <0xff 35>, /* WDT_barkInt */ - <0xff 36>, /* WDT_biteExpired */ - <0xff 39>, /* QTMR_qgicFrm0VirtIrq */ - <0xff 40>, /* QTMR_qgicFrm0PhyIrq */ - <0xff 41>, /* QTMR_qgicFrm1PhyIrq */ - <0xff 42>, /* QTMR_qgicFrm2PhyIrq */ - <0xff 43>, /* QTMR_qgicFrm3PhyIrq */ - <0xff 44>, /* QTMR_qgicFrm4PhyIrq */ - <0xff 45>, /* QTMR_qgicFrm5PhyIrq */ - <0xff 46>, /* QTMR_qgicFrm6PhyIrq */ - <0xff 47>, /* rbif_Irq[0] */ - <0xff 48>, /* rbif_Irq[1] */ - <0xff 49>, /* rbif_Irq[2] */ - <0xff 50>, /* rbif_Irq[3] */ - <0xff 51>, /* rbif_Irq[4] */ - <0xff 52>, /* cci_spm_vote_summary_int */ - <0xff 54>, /* nERRORIRQ */ - <0xff 55>, /* nEVNTCNTOVERFLOW_cci */ - <0xff 56>, /* QTMR_qgicFrm0VirtIrq */ - <0xff 57>, /* QTMR_qgicFrm0PhyIrq */ - <0xff 58>, /* QTMR_qgicFrm1PhyIrq */ - <0xff 59>, /* QTMR_qgicFrm2PhyIrq */ - <0xff 60>, /* QTMR_qgicFrm3PhyIrq */ - <0xff 61>, /* QTMR_qgicFrm4PhyIrq */ - <0xff 62>, /* QTMR_qgicFrm5PhyIrq */ - <0xff 63>, /* QTMR_qgicFrm6PhyIrq */ - <0xff 64>, /* wakeup_counter_irq_OR */ - <0xff 65>, /* APC[0-3]_vs_alarm */ - <0xff 66>, /* apc1_vs_alarm */ - <0xff 67>, /* o_pwr_osm_irq */ - <0xff 68>, /* o_perf_osm_irq */ - <0xff 69>, /* o_pwr_dcvsh_interrupt */ - <0xff 70>, /* o_perf_dcvsh_interrupt */ - <0xff 73>, /* L2_EXTERRIRQ_C0 */ - <0xff 74>, /* L2_EXTERRIRQ_C1 */ - <0xff 75>, /* L2_INTERRIRQ_C0 */ - <0xff 76>, /* L2_INTERRIRQ_C1 */ - <0xff 77>, /* L2SPM_svicInt[0] */ - <0xff 78>, /* L2SPM_svicInt[1] */ - <0xff 79>, /* L2SPM_svicIntSwDone[0] */ - <0xff 80>, /* L2SPM_svicIntSwDone[1] */ - <0xff 81>, /* l2_avs_err[0] */ - <0xff 82>, /* l2_avs_err[1] */ - <0xff 83>, /* l2_avs_ack[0] */ - <0xff 84>, /* l2_avs_ack[1] */ - <0xff 98>, /* o_qm_interrupt */ - <0xff 100>, /* camss_vbif_1_irpt */ - <0xff 101>, /* processor_1_user_int */ - <0xff 102>, /* processor_1_kernel_int */ - <0xff 106>, /* dir_conn_irq_lpa_dsp[2] */ - <0xff 107>, /* dir_conn_irq_lpa_dsp[1] */ - <0xff 109>, /* camss_vbif_0_irpt */ - <0xff 110>, /* csiphy_0_irq */ - <0xff 111>, /* csiphy_1_irq */ - <0xff 112>, /* csiphy_2_irq */ - <0xff 115>, /* mdss_irq */ - <0xff 116>, /* mdss_vbif_irpt */ - <0xff 117>, /* dir_conn_irq_lpa_dsp[0] */ - <0xff 119>, /* lpass_irq_out_apcs[11] */ - <0xff 122>, /* o_pimem_tpdm_bc_irq_ofsat */ - <0xff 123>, /* o_pimem_tpdm_tc_irq_ofsat */ - <0xff 124>, /* dir_conn_irq_sensors[1] */ - <0xff 125>, /* dir_conn_irq_sensors[0] */ - <0xff 127>, /* peripheral_irq[2] */ - <0xff 128>, /* peripheral_irq[3] */ - <0xff 129>, /* peripheral_irq[4] */ - <0xff 130>, /* peripheral_irq[5] */ - <0xff 133>, /* peripheral_irq[2] */ - <0xff 134>, /* peripheral_irq[3] */ - <0xff 135>, /* peripheral_irq[4] */ - <0xff 136>, /* peripheral_irq[5] */ - <0xff 139>, /* peripheral_irq[0] */ - <0xff 140>, /* peripheral_irq[1] */ - <0xff 142>, /* sdcc_irq[0] */ - <0xff 143>, /* sdcc_irq[1] */ - <0xff 144>, /* sdcc_pwr_cmd_irq */ - <0xff 145>, /* peripheral_irq[0] */ - <0xff 146>, /* peripheral_irq[1] */ - <0xff 148>, /* osmmu_CIrpt[4] */ - <0xff 149>, /* osmmu_CIrpt[5] */ - <0xff 150>, /* sdio_wakeup_irq */ - <0xff 151>, /* acvremoval_int */ - <0xff 152>, /* trs_int */ - <0xff 155>, /* dir_conn_irq_lpa_dsp[5] */ - <0xff 156>, /* dir_conn_irq_lpa_dsp[4] */ - <0xff 157>, /* sdcc_irq[0] */ - <0xff 158>, /* sdcc_irq[1] */ - <0xff 159>, /* lpass_irq_out_apcs[39] */ - <0xff 160>, /* lpass_irq_out_apcs[38] */ - <0xff 163>, /* usb30_ctrl_irq[0] */ - <0xff 164>, /* usb30_bam_irq[0] */ - <0xff 165>, /* usb30_hs_phy_irq */ - <0xff 166>, /* o_lm_int_2qgic */ - <0xff 169>, /* lpass_irq_out_apcs[33] */ - <0xff 171>, /* usb20s_hs_phy_irq */ - <0xff 172>, /* dcvs_int[6] */ - <0xff 173>, /* dcvs_int[7] */ - <0xff 175>, /* usb20s_ee1_irq */ - <0xff 176>, /* usb20s_power_event_irq */ - <0xff 184>, /* dir_conn_irq_lpa_dsp[3] */ - <0xff 185>, /* camss_vbif_2_irpt */ - <0xff 186>, /* mnoc_obs_mainfault */ - <0xff 188>, /* lpass_irq_out_apcs[00] */ - <0xff 189>, /* lpass_irq_out_apcs[01] */ - <0xff 190>, /* lpass_irq_out_apcs[02] */ - <0xff 191>, /* lpass_irq_out_apcs[03] */ - <0xff 192>, /* lpass_irq_out_apcs[04] */ - <0xff 193>, /* lpass_irq_out_apcs[05] */ - <0xff 194>, /* lpass_irq_out_apcs[06] */ - <0xff 195>, /* lpass_irq_out_apcs[07] */ - <0xff 196>, /* lpass_irq_out_apcs[08] */ - <0xff 197>, /* lpass_irq_out_apcs[09] */ - <0xff 199>, /* qdss_usb_trace_bam_irq[0] */ - <0xff 200>, /* rpm_ipc[4] */ - <0xff 201>, /* rpm_ipc[5] */ - <0xff 202>, /* rpm_ipc[6] */ - <0xff 203>, /* rpm_ipc[7] */ - <0xff 204>, /* rpm_ipc[20] */ - <0xff 205>, /* rpm_ipc[21] */ - <0xff 206>, /* rpm_ipc[22] */ - <0xff 207>, /* rpm_ipc[23] */ - <0xff 208>, /* lpi_dir_conn_irq_apps[0] */ - <0xff 209>, /* lpi_dir_conn_irq_apps[1] */ - <0xff 210>, /* lpi_dir_conn_irq_apps[2] */ - <0xff 213>, /* secure_wdog_bark_irq */ - <0xff 214>, /* tsens1_tsens_max_min_int */ - <0xff 215>, /* o_bimc_intr[0] */ - <0xff 217>, /* o_ocimem_nonsec_irq */ - <0xff 218>, /* cpr_irq[1] */ - <0xff 219>, /* lpass_irq_out_vmm[00] */ - <0xff 220>, /* spmi_protocol_irq */ - <0xff 221>, /* lpass_irq_out_vmm[01] */ - <0xff 222>, /* lpass_irq_out_vmm[02] */ - <0xff 223>, /* spdm_offline_irq */ - <0xff 224>, /* spdm_realtime_irq[1] */ - <0xff 225>, /* snoc_obs_mainFault */ - <0xff 226>, /* cnoc_obs_mainFault */ - <0xff 227>, /* o_tcsr_xpu3_sec_summary_intr */ - <0xff 228>, /* o_tcsr_xpu3_non_sec_summary_intr */ - <0xff 229>, /* o_timeout_slave_hmss_summary_intr */ - <0xff 230>, /* o_tcsr_vmidmt_client_sec_summary_intr */ - <0xff 231>, /* o_tcsr_vmidmt_client_nsec_summary_intr */ - <0xff 232>, /* o_tcsr_vmidmt_cfg_sec_summary_intr */ - <0xff 233>, /* o_tcsr_vmidmt_cfg_non_sec_summary_intr */ - <0xff 234>, /* lpass_irq_out_vmm[03] */ - <0xff 235>, /* cpr_irq[0] */ - <0xff 236>, /* crypto_core_irq[0] */ - <0xff 237>, /* crypto_core_irq[1] */ - <0xff 238>, /* crypto_bam_irq[0] */ - <0xff 239>, /* crypto_bam_irq[1] */ - <0xff 240>, /* summary_irq_hmss */ - <0xff 241>, /* dir_conn_irq_hmss[7] */ - <0xff 242>, /* dir_conn_irq_hmss[6] */ - <0xff 243>, /* dir_conn_irq_hmss[5] */ - <0xff 244>, /* dir_conn_irq_hmss[4] */ - <0xff 245>, /* dir_conn_irq_hmss[3] */ - <0xff 246>, /* dir_conn_irq_hmss[2] */ - <0xff 247>, /* dir_conn_irq_hmss[1] */ - <0xff 248>, /* dir_conn_irq_hmss[0] */ - <0xff 249>, /* summary_irq_hmss_tz */ - <0xff 250>, /* cpr_irq[3] */ - <0xff 251>, /* cpr_irq[2] */ - <0xff 252>, /* cpr_irq[1] */ - <0xff 253>, /* sdcc_pwr_cmd_irq */ - <0xff 254>, /* sdio_wakeup_irq */ - <0xff 255>, /* cpr_irq[0] */ - <0xff 256>, /* lpass_irq_out_apcs[34] */ - <0xff 257>, /* lpass_irq_out_apcs[35] */ - <0xff 258>, /* lpass_irq_out_apcs[21] */ - <0xff 261>, /* o_tcsr_mmu_nsgcfglrpt_summary_intr */ - <0xff 262>, /* o_tcsr_mmu_gcfglrpt_summary_intr */ - <0xff 263>, /* o_tcsr_mmu_nsglrpt_summary_intr */ - <0xff 264>, /* o_tcsr_mmu_glrpt_summary_intr */ - <0xff 265>, /* vbif_irpt */ - <0xff 266>, /* lpass_irq_out_apcs[20] */ - <0xff 267>, /* lpass_irq_out_apcs[19] */ - <0xff 269>, /* rpm_wdog_expired_irq */ - <0xff 270>, /* bam_irq[0] */ - <0xff 271>, /* bam_irq[0] */ - <0xff 276>, /* mmss_bimc_smmu_cirpt[4] */ - <0xff 277>, /* mmss_bimc_smmu_cirpt[5] */ - <0xff 278>, /* usb30_ctrl_irq[1] */ - <0xff 279>, /* mmss_bimc_smmu_cirpt[6] */ - <0xff 280>, /* mmss_bimc_smmu_cirpt[7] */ - <0xff 281>, /* mmss_bimc_smmu_cirpt[8] */ - <0xff 282>, /* mmss_bimc_smmu_cirpt[9] */ - <0xff 283>, /* mmss_bimc_smmu_cirpt[10] */ - <0xff 284>, /* mmss_bimc_smmu_cirpt[11] */ - <0xff 285>, /* mmss_bimc_smmu_cirpt[12] */ - <0xff 286>, /* mmss_bimc_smmu_cirpt[13] */ - <0xff 287>, /* mmss_bimc_smmu_cirpt[14] */ - <0xff 288>, /* mmss_bimc_smmu_cirpt[15] */ - <0xff 289>, /* ufs_ice_sec_level_irq */ - <0xff 291>, /* lpass_irq_out_apcs[18] */ - <0xff 292>, /* mmss_bimc_smmu_cirpt[16] */ - <0xff 293>, /* mmss_bimc_smmu_cirpt[17] */ - <0xff 294>, /* mmss_bimc_smmu_cirpt[18] */ - <0xff 295>, /* mmss_bimc_smmu_cirpt[0] */ - <0xff 296>, /* mmss_bimc_smmu_pmirpt */ - <0xff 297>, /* ufs_intrq */ - <0xff 298>, /* mmss_bimc_smmu_cirpt[1] */ - <0xff 299>, /* mmss_bimc_smmu_cirpt[2] */ - <0xff 300>, /* mmss_bimc_smmu_cirpt[3] */ - <0xff 301>, /* lpass_irq_out_apcs[17] */ - <0xff 302>, /* qdss_etrbytecnt_irq */ - <0xff 303>, /* lpass_irq_out_apcs[16] */ - <0xff 304>, /* mmss_bimc_smmu_cirpt[19] */ - <0xff 305>, /* mmss_bimc_smmu_cirpt[20] */ - <0xff 306>, /* mmss_bimc_smmu_cirpt[21] */ - <0xff 307>, /* mmss_bimc_smmu_cirpt[22] */ - <0xff 308>, /* mmss_bimc_smmu_cirpt[23] */ - <0xff 316>, /* lpass_irq_out_apcs[13] */ - <0xff 317>, /* rbif_irq */ - <0xff 318>, /* gpu_cc_gpu_cx_gds_hw_ctrl_irq_out */ - <0xff 319>, /* venus0_irq */ - <0xff 323>, /* lpass_irq_out_apcs[14] */ - <0xff 324>, /* lpass_irq_out_apcs[15] */ - <0xff 325>, /* camss_irq18 */ - <0xff 326>, /* camss_irq0 */ - <0xff 327>, /* camss_irq1 */ - <0xff 328>, /* camss_irq2 */ - <0xff 329>, /* camss_irq3 */ - <0xff 330>, /* camss_irq4 */ - <0xff 331>, /* camss_irq5 */ - <0xff 332>, /* GC_SYS_irq[0] */ - <0xff 333>, /* GC_SYS_irq[1] */ - <0xff 334>, /* GC_SYS_irq[2] */ - <0xff 335>, /* GC_SYS_irq[3] */ - <0xff 336>, /* camss_irq13 */ - <0xff 337>, /* camss_irq14 */ - <0xff 338>, /* camss_irq15 */ - <0xff 339>, /* camss_irq16 */ - <0xff 340>, /* camss_irq17 */ - <0xff 341>, /* camss_irq6 */ - <0xff 342>, /* lpass_irq_out_apcs[36] */ - <0xff 345>, /* camss_irq7 */ - <0xff 346>, /* camss_irq8 */ - <0xff 347>, /* camss_irq9 */ - <0xff 348>, /* camss_irq10 */ - <0xff 350>, /* camss_irq12 */ - <0xff 351>, /* lpass_irq_out_apcs[12] */ - <0xff 357>, /* o_pimem_nonfatal_irq */ - <0xff 359>, /* ee1_apps_trustzone_spmi_periph_irq */ - <0xff 360>, /* o_pimem_fatal_irq */ - <0xff 361>, /* osmmu_CIrpt[0] */ - <0xff 362>, /* osmmu_CIrpt[1] */ - <0xff 363>, /* osmmu_CIrpt[2] */ - <0xff 364>, /* osmmu_CIrpt[3] */ - <0xff 365>, /* ipa_irq[0] */ - <0xff 366>, /* osmmu_PMIrpt */ - <0xff 380>, /* qusb2phy_intr */ - <0xff 381>, /* osmmu_CIrpt[6] */ - <0xff 382>, /* osmmu_CIrpt[7] */ - <0xff 385>, /* osmmu_CIrpt[12] */ - <0xff 386>, /* osmmu_CIrpt[13] */ - <0xff 387>, /* osmmu_CIrpt[14] */ - <0xff 388>, /* osmmu_CIrpt[15] */ - <0xff 389>, /* osmmu_CIrpt[16] */ - <0xff 390>, /* osmmu_CIrpt[17] */ - <0xff 391>, /* osmmu_CIrpt[18] */ - <0xff 392>, /* osmmu_CIrpt[19] */ - <0xff 393>, /* o_dcc_crc_fail_int */ - <0xff 404>, /* aggre2noc_obs_mainFault */ - <0xff 405>, /* osmmu_CIrpt[0] */ - <0xff 406>, /* osmmu_CIrpt[1] */ - <0xff 407>, /* osmmu_CIrpt[2] */ - <0xff 408>, /* osmmu_CIrpt[3] */ - <0xff 409>, /* osmmu_CIrpt[4] */ - <0xff 410>, /* osmmu_CIrpt[5] */ - <0xff 411>, /* o_dcc_task_done_int */ - <0xff 412>, /* vsense_apps_alarm_irq */ - <0xff 413>, /* osmmu_PMIrpt */ - <0xff 414>, /* channel0_apps_hlos_trans_done_irq */ - <0xff 415>, /* channel1_apps_trustzone_trans_done_irq */ - <0xff 416>, /* rpm_ipc[28] */ - <0xff 417>, /* rpm_ipc[29] */ - <0xff 418>, /* rpm_ipc[30] */ - <0xff 419>, /* rpm_ipc[31] */ - <0xff 423>, /* lpass_irq_out_apcs[40] */ - <0xff 424>, /* ipa_irq[2] */ - <0xff 425>, /* lpass_irq_out_apcs[22] */ - <0xff 426>, /* lpass_irq_out_apcs[23] */ - <0xff 427>, /* lpass_irq_out_apcs[24] */ - <0xff 428>, /* lpass_irq_out_apcs[25] */ - <0xff 429>, /* lpass_irq_out_apcs[26] */ - <0xff 430>, /* lpass_irq_out_apcs[27] */ - <0xff 431>, /* lpass_irq_out_apcs[28] */ - <0xff 432>, /* lpass_irq_out_apcs[29] */ - <0xff 433>, /* lpass_irq_out_apcs[30] */ - <0xff 434>, /* lpass_irq_out_apcs[31] */ - <0xff 435>, /* lpass_irq_out_apcs[32] */ - <0xff 436>, /* lpass_irq_out_apcs[37] */ - <0xff 445>, /* wcss_apss_ce_intr[0] */ - <0xff 446>, /* wcss_apss_ce_intr[1] */ - <0xff 447>, /* wcss_apss_ce_intr[2] */ - <0xff 448>, /* wcss_apss_ce_intr[3] */ - <0xff 449>, /* wcss_apss_ce_intr[4] */ - <0xff 450>, /* wcss_apss_ce_intr[5] */ - <0xff 452>, /* wcss_apss_ce_intr[6] */ - <0xff 453>, /* wcss_apss_ce_intr[7] */ - <0xff 454>, /* wcss_apss_ce_intr[8] */ - <0xff 455>, /* wcss_apss_ce_intr[9] */ - <0xff 456>, /* wcss_apss_ce_intr[10] */ - <0xff 457>, /* wcss_apss_ce_intr[11] */ - <0xff 458>, /* wcss_apss_status_intr */ - <0xff 462>, /* tsens1_tsens_critical_int */ - <0xff 464>, /* ipa_bam_irq[0] */ - <0xff 465>, /* ipa_bam_irq[2] */ - <0xff 466>, /* ssc_uart_int */ - <0xff 468>, /* cri_cm_irq_tz */ - <0xff 469>, /* cri_cm_irq_hyp */ - <0xff 471>, /* mmss_bimc_smmu_gds_hw_ctrl_irq_out */ - <0xff 472>, /* gcc_gds_hw_ctrl_irq_out */ - <0xff 474>, /* osmmu_CIrpt[20] */ - <0xff 475>, /* osmmu_CIrpt[21] */ - <0xff 476>, /* osmmu_CIrpt[22] */ - <0xff 477>, /* tsens0_tsens_critical_int */ - <0xff 478>, /* tsens0_tsens_max_min_int */ - <0xff 479>, /* osmmu_CIrpt[23] */ - <0xff 480>, /* q6_wdog_expired_irq */ - <0xff 481>, /* mss_ipc_out_irq[4] */ - <0xff 482>, /* mss_ipc_out_irq[5] */ - <0xff 483>, /* mss_ipc_out_irq[6] */ - <0xff 484>, /* mss_ipc_out_irq[7] */ - <0xff 485>, /* mss_ipc_out_irq[28] */ - <0xff 486>, /* mss_ipc_out_irq[29] */ - <0xff 487>, /* mss_ipc_out_irq[30] */ - <0xff 488>, /* mss_ipc_out_irq[31] */ - <0xff 490>, /* tsens0_tsens_upper_lower_int */ - <0xff 491>, /* qspi_irq0 */ - <0xff 492>, /* sdcc_ice_sec_level_irq */ - <0xff 494>, /* osmmu_CIrpt[6] */ - <0xff 495>, /* osmmu_CIrpt[7] */ - <0xff 496>, /* osmmu_CIrpt[8] */ - <0xff 497>, /* osmmu_CIrpt[9] */ - <0xff 498>, /* osmmu_CIrpt[10] */ - <0xff 499>, /* osmmu_CIrpt[11] */ - <0xff 500>, /* osmmu_CIrpt[24] */ - <0xff 501>, /* osmmu_CIrpt[25] */ - <0xff 503>, /* o_bimc_intr[1] */ - <0xff 504>, /* osmmu_CIrpt[26] */ - <0xff 505>, /* osmmu_CIrpt[27] */ - <0xff 506>, /* osmmu_CIrpt[28] */ - <0xff 512>, /* turing_irq_out_vmm[0] */ - <0xff 513>, /* turing_irq_out_vmm[1] */ - <0xff 514>, /* turing_irq_out_vmm[2] */ - <0xff 515>, /* turing_irq_out_vmm[3] */ - <0xff 516>, /* lpass_irq_out_apcs[41] */ - <0xff 517>, /* lpass_irq_out_apcs[42] */ - <0xff 520>, /* lpass_irq_out_apcs[45] */ - <0xff 544>, /* turing_irq_out_apcs[00] */ - <0xff 545>, /* turing_irq_out_apcs[01] */ - <0xff 546>, /* turing_irq_out_apcs[02] */ - <0xff 547>, /* turing_irq_out_apcs[03] */ - <0xff 548>, /* turing_irq_out_apcs[04] */ - <0xff 549>, /* turing_irq_out_apcs[05] */ - <0xff 550>, /* turing_irq_out_apcs[06] */ - <0xff 551>, /* turing_irq_out_apcs[07] */ - <0xff 552>, /* turing_irq_out_apcs[08] */ - <0xff 553>, /* turing_irq_out_apcs[09] */ - <0xff 554>, /* turing_irq_out_apcs[10] */ - <0xff 556>, /* turing_irq_out_apcs[12] */ - <0xff 557>, /* turing_irq_out_apcs[13] */ - <0xff 558>, /* turing_irq_out_apcs[14] */ - <0xff 559>, /* turing_irq_out_apcs[15] */ - <0xff 560>, /* turing_irq_out_apcs[16] */ - <0xff 561>, /* turing_irq_out_apcs[17] */ - <0xff 562>, /* turing_irq_out_apcs[18] */ - <0xff 563>, /* turing_irq_out_apcs[19] */ - <0xff 564>, /* turing_irq_out_apcs[20] */ - <0xff 565>, /* turing_irq_out_apcs[21] */ - <0xff 566>, /* turing_irq_out_apcs[22] */ - <0xff 567>, /* turing_irq_out_apcs[23] */ - <0xff 568>, /* turing_irq_out_apcs[24] */ - <0xff 569>, /* turing_irq_out_apcs[25] */ - <0xff 570>, /* turing_irq_out_apcs[26] */ - <0xff 571>, /* turing_irq_out_apcs[27] */ - <0xff 572>, /* turing_irq_out_apcs[28] */ - <0xff 573>, /* turing_irq_out_apcs[29] */ - <0xff 574>, /* turing_irq_out_apcs[30] */ - <0xff 575>, /* turing_irq_out_apcs[31] */ - <0xff 576>, /* turing_irq_out_apcs[32] */ - <0xff 577>, /* turing_irq_out_apcs[33] */ - <0xff 578>, /* turing_irq_out_apcs[34] */ - <0xff 579>, /* turing_irq_out_apcs[35] */ - <0xff 580>, /* turing_irq_out_apcs[36] */ - <0xff 581>, /* turing_irq_out_apcs[37] */ - <0xff 582>, /* turing_irq_out_apcs[38] */ - <0xff 583>, /* turing_irq_out_apcs[39] */ - <0xff 584>; /* turing_irq_out_apcs[40] */ - - qcom,gpio-parent = <&tlmm>; - qcom,gpio-map = - <3 1>, - <4 5>, - <5 9>, - <6 10>, - <7 66>, - <8 22>, - <9 25>, - <10 28>, - <11 58>, - <13 41>, - <14 43>, - <15 40>, - <16 42>, - <17 46>, - <18 50>, - <19 44>, - <21 56>, - <22 45>, - <23 68>, - <24 69>, - <25 70>, - <26 71>, - <27 72>, - <28 73>, - <29 64>, - <30 2>, - <31 13>, - <32 111>, - <33 74>, - <34 75>, - <35 76>, - <36 82>, - <37 17>, - <38 77>, - <39 47>, - <40 54>, - <41 48>, - <42 101>, - <43 49>, - <44 51>, - <45 86>, - <46 90>, - <47 91>, - <48 52>, - <50 55>, - <51 6>, - <53 65>, - <55 67>, - <56 83>, - <57 84>, - <58 85>, - <59 87>, - <63 21>, - <64 78>, - <65 113>, - <66 60>, - <67 98>, - <68 30>, - <70 31>, - <71 29>, - <76 107>, - <83 109>, - <84 103>, - <85 105>; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-cdp.dts b/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-cdp.dts deleted file mode 100644 index 3d3f8682941f..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-cdp.dts +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "msmfalcon.dtsi" -#include "msmfalcon-cdp.dtsi" -#include "msm-pm3falcon.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON CDP"; - compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp"; - qcom,board-id = <1 0>; - qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-mtp.dts b/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-mtp.dts deleted file mode 100644 index 4e6bb7336f2b..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-mtp.dts +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "msmfalcon.dtsi" -#include "msmfalcon-mtp.dtsi" -#include "msm-pm3falcon.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON MTP"; - compatible = "qcom,msmfalcon-mtp", "qcom,msmfalcon", "qcom,mtp"; - qcom,board-id = <8 0>; - qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-qrd.dts b/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-qrd.dts deleted file mode 100644 index e2d45f0d151e..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-qrd.dts +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "msmfalcon.dtsi" -#include "msmfalcon-qrd.dtsi" -#include "msm-pm3falcon.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON QRD"; - compatible = "qcom,msmfalcon-qrd", "qcom,msmfalcon", "qcom,qrd"; - qcom,board-id = <0x1000b 0>; - qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-rcm.dts b/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-rcm.dts deleted file mode 100644 index c48124120d61..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-rcm.dts +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "msmfalcon.dtsi" -#include "msmfalcon-cdp.dtsi" -#include "msm-pm3falcon.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON RCM"; - compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp"; - qcom,board-id = <21 0>; - qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-rumi.dts b/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-rumi.dts deleted file mode 100644 index b81a92a4aa7c..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-rumi.dts +++ /dev/null @@ -1,146 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "msmfalcon.dtsi" -#include "msmfalcon-pinctrl.dtsi" -#include "msm-pm3falcon.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON RUMI"; - compatible = "qcom,msmfalcon-rumi", "qcom,msmfalcon", "qcom,rumi"; - qcom,board-id = <15 0>; - qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; - - chosen { - bootargs = "lpm_levels.sleep_disabled=1"; - }; -}; - -&usb3 { - /delete-property/ USB3_GDSC-supply; - /delete-property/ extcon; - dwc3@a800000 { - maximum-speed = "high-speed"; - }; -}; - -&ssphy { - compatible = "usb-nop-xceiv"; -}; - -&qusb_phy0 { - reg = <0x0a928000 0x8000>, - <0x0a8f8800 0x400>, - <0x0a920000 0x100>; - reg-names = "qusb_phy_base", - "qscratch_base", - "emu_phy_base"; - qcom,emulation; - qcom,qusb-phy-init-seq = <0x19 0x1404 - 0x20 0x1414 - 0x79 0x1410 - 0x00 0x1418 - 0x99 0x1404 - 0x04 0x1408 - 0xd9 0x1404>; - qcom,emu-dcm-reset-seq = <0x100000 0x20 - 0x0 0x20 - 0x1a0 0x20 - 0x5 0x14>; -}; - -&uartblsp1dm1 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&uart_console_active>; -}; - -&sdhc_1 { - /* device core power supply */ - vdd-supply = <&pm2falcon_l4>; - qcom,vdd-voltage-level = <2950000 2950000>; - qcom,vdd-current-level = <200 570000>; - - /* device communication power supply */ - vdd-io-supply = <&pmfalcon_l8>; - qcom,vdd-io-always-on; - qcom,vdd-io-lpm-sup; - qcom,vdd-io-voltage-level = <1800000 1800000>; - qcom,vdd-io-current-level = <200 325000>; - - pinctrl-names = "active", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; - - qcom,clk-rates = <400000 20000000 25000000 50000000 192000000 - 384000000>; - - qcom,nonremovable; - qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; - - status = "ok"; -}; - -&clock_gcc { - compatible = "qcom,dummycc"; - clock-output-names = "gcc_clocks"; -}; - -&pmfalcon_charger { - status = "disabled"; -}; - -&pmfalcon_fg { - status = "disabled"; -}; - -&clock_gfx { - compatible = "qcom,dummycc"; - clock-output-names = "gfx_clocks"; -}; - -&pmfalcon_pdphy { - status = "disabled"; -}; - -&clock_mmss { - compatible = "qcom,dummycc"; - clock-output-names = "mmss_clocks"; -}; - -&ufsphy1 { - vdda-phy-supply = <&pm2falcon_l1>; - vdda-pll-supply = <&pmfalcon_l10>; - vddp-ref-clk-supply = <&pmfalcon_l1>; - vdda-phy-max-microamp = <51400>; - vdda-pll-max-microamp = <14200>; - vddp-ref-clk-max-microamp = <100>; - vddp-ref-clk-always-on; -}; - -&ufs1 { - vdd-hba-supply = <&gdsc_ufs>; - vdd-hba-fixed-regulator; - vcc-supply = <&pm2falcon_l4>; - vccq2-supply = <&pmfalcon_l8>; - vcc-max-microamp = <500000>; - vccq2-max-microamp = <600000>; - qcom,disable-lpm; -}; - -&clock_debug { - compatible = "qcom,dummycc"; - clock-output-names = "debug_clocks"; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-sim.dts b/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-sim.dts deleted file mode 100644 index b47c1d328201..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-sim.dts +++ /dev/null @@ -1,111 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "msmfalcon.dtsi" -#include "msmfalcon-pinctrl.dtsi" -#include "msm-pm3falcon.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON SIM"; - compatible = "qcom,msmfalcon-sim", "qcom,msmfalcon", "qcom,sim"; - qcom,board-id = <16 0>; - qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; - - chosen { - bootargs = "lpm_levels.sleep_disabled=1"; - }; -}; - -&usb3 { - reg = <0xa800000 0xfc000>; - reg-names = "core_base"; - /delete-property/ extcon; - dwc3@a800000 { - maximum-speed = "high-speed"; - }; -}; - -&ssphy { - compatible = "usb-nop-xceiv"; -}; - -&qusb_phy0 { - compatible = "usb-nop-xceiv"; -}; - -&uartblsp1dm1 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&uart_console_active>; -}; - -&sdhc_1 { - /* device core power supply */ - vdd-supply = <&pm2falcon_l4>; - qcom,vdd-voltage-level = <2950000 2950000>; - qcom,vdd-current-level = <200 570000>; - - /* device communication power supply */ - vdd-io-supply = <&pmfalcon_l8>; - qcom,vdd-io-always-on; - qcom,vdd-io-lpm-sup; - qcom,vdd-io-voltage-level = <1800000 1800000>; - qcom,vdd-io-current-level = <200 325000>; - - pinctrl-names = "active", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; - - qcom,clk-rates = <400000 20000000 25000000 50000000 192000000 - 384000000>; - - qcom,nonremovable; - qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; - - status = "ok"; -}; - -&pmfalcon_charger { - status = "disabled"; -}; - -&pmfalcon_fg { - status = "disabled"; -}; - -&pmfalcon_pdphy { - status = "disabled"; -}; - -&ufsphy1 { - vdda-phy-supply = <&pm2falcon_l1>; - vdda-pll-supply = <&pmfalcon_l10>; - vddp-ref-clk-supply = <&pmfalcon_l1>; - vdda-phy-max-microamp = <51400>; - vdda-pll-max-microamp = <14200>; - vddp-ref-clk-max-microamp = <100>; - vddp-ref-clk-always-on; - status = "ok"; -}; - -&ufs1 { - vdd-hba-supply = <&gdsc_ufs>; - vdd-hba-fixed-regulator; - vcc-supply = <&pm2falcon_l4>; - vccq2-supply = <&pmfalcon_l8>; - vcc-max-microamp = <500000>; - vccq2-max-microamp = <600000>; - status = "ok"; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-qrd.dts b/arch/arm/boot/dts/qcom/msmfalcon-qrd.dts deleted file mode 100644 index b97fdd18e229..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-qrd.dts +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "msmfalcon.dtsi" -#include "msmfalcon-qrd.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON QRD"; - compatible = "qcom,msmfalcon-qrd", "qcom,msmfalcon", "qcom,qrd"; - qcom,board-id = <0x1000b 0>; - qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, - <0x0001001b 0x0201011a 0x0 0x0>; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-qrd.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-qrd.dtsi deleted file mode 100644 index 3ec991b82bba..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-qrd.dtsi +++ /dev/null @@ -1,24 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "msmfalcon-pinctrl.dtsi" -/ { -}; - -&uartblsp1dm1 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&uart_console_active>; -}; - -&soc { -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-rcm.dts b/arch/arm/boot/dts/qcom/msmfalcon-rcm.dts deleted file mode 100644 index e4f59c735e70..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-rcm.dts +++ /dev/null @@ -1,25 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "msmfalcon.dtsi" -#include "msmfalcon-cdp.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON RCM"; - compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp"; - qcom,board-id = <21 0>; - qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, - <0x0001001b 0x0201011a 0x0 0x0>; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-regulator.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-regulator.dtsi deleted file mode 100644 index 02e61bcdd95c..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-regulator.dtsi +++ /dev/null @@ -1,498 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -&rpm_bus { - rpm-regulator-smpa4 { - status = "okay"; - pmfalcon_s4: regulator-s4 { - regulator-min-microvolt = <1805000>; - regulator-max-microvolt = <2040000>; - status = "okay"; - }; - }; - - rpm-regulator-smpa5 { - status = "okay"; - pmfalcon_s5: regulator-s5 { - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - status = "okay"; - }; - }; - - rpm-regulator-smpa6 { - status = "okay"; - pmfalcon_s6: regulator-s6 { - regulator-min-microvolt = <504000>; - regulator-max-microvolt = <992000>; - status = "okay"; - }; - }; - - rpm-regulator-smpb1 { - status = "okay"; - pm2falcon_s1: regulator-s1 { - regulator-min-microvolt = <1125000>; - regulator-max-microvolt = <1125000>; - status = "okay"; - }; - }; - - rpm-regulator-smpb2 { - status = "okay"; - pm2falcon_s2: regulator-s2 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - status = "okay"; - }; - }; - - /* PM2FALCON S3 + S4 - VDD_CX supply */ - rpm-regulator-smpb3 { - status = "okay"; - pm2falcon_s3_level: regulator-s3-level { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s3_level"; - qcom,set = <3>; - regulator-min-microvolt = - ; - regulator-max-microvolt = - ; - qcom,use-voltage-level; - }; - - pm2falcon_s3_floor_level: regulator-s3-floor-level { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s3_floor_level"; - qcom,set = <3>; - regulator-min-microvolt = - ; - regulator-max-microvolt = - ; - qcom,use-voltage-floor-level; - qcom,always-send-voltage; - }; - - pm2falcon_s3_level_ao: regulator-s3-level-ao { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s3_level_ao"; - qcom,set = <1>; - regulator-min-microvolt = - ; - regulator-max-microvolt = - ; - qcom,use-voltage-level; - }; - }; - - /* PM2FALCON S5 - VDD_MX supply */ - rpm-regulator-smpb5 { - status = "okay"; - pm2falcon_s5_level: regulator-s5-level { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s5_level"; - qcom,set = <3>; - regulator-min-microvolt = - ; - regulator-max-microvolt = - ; - qcom,use-voltage-level; - }; - - pm2falcon_s5_floor_level: regulator-s5-floor-level { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s5_floor_level"; - qcom,set = <3>; - regulator-min-microvolt = - ; - regulator-max-microvolt = - ; - qcom,use-voltage-floor-level; - qcom,always-send-voltage; - }; - - pm2falcon_s5_level_ao: regulator-s5-level-ao { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s5_level_ao"; - qcom,set = <1>; - regulator-min-microvolt = - ; - regulator-max-microvolt = - ; - qcom,use-voltage-level; - }; - }; - - rpm-regulator-ldoa1 { - status = "okay"; - pmfalcon_l1: regulator-l1 { - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1250000>; - status = "okay"; - }; - }; - - rpm-regulator-ldoa2 { - status = "okay"; - pmfalcon_l2: regulator-l2 { - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1010000>; - status = "okay"; - }; - }; - - rpm-regulator-ldoa3 { - status = "okay"; - pmfalcon_l3: regulator-l3 { - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1010000>; - status = "okay"; - }; - }; - - /* TODO: remove if ADRASTEA CX/MX not voted from APPS */ - rpm-regulator-ldoa5 { - status = "okay"; - pmfalcon_l5: regulator-l5 { - regulator-min-microvolt = <525000>; - regulator-max-microvolt = <950000>; - status = "okay"; - }; - }; - - rpm-regulator-ldoa6 { - status = "okay"; - pmfalcon_l6: regulator-l6 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1370000>; - status = "okay"; - }; - - pmfalcon_l6_pin_ctrl: regulator-l6-pin-ctrl { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l6_pin_ctrl"; - qcom,set = <3>; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1370000>; - /* Force NPM follows HW_EN1 */ - qcom,init-pin-ctrl-mode = <2>; - /* Enable follows HW_EN1 */ - qcom,enable-with-pin-ctrl = <0 2>; - }; - }; - - rpm-regulator-ldoa7 { - status = "okay"; - pmfalcon_l7: regulator-l7 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - status = "okay"; - }; - }; - - rpm-regulator-ldoa8 { - status = "okay"; - pmfalcon_l8: regulator-l8 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <1900000>; - status = "okay"; - }; - }; - - rpm-regulator-ldoa9 { - status = "okay"; - pmfalcon_l9: regulator-l9 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <1900000>; - status = "okay"; - }; - - pmfalcon_l9_pin_ctrl: regulator-l9-pin-ctrl { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l9_pin_ctrl"; - qcom,set = <3>; - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <1900000>; - /* Force NPM follows HW_EN1 */ - qcom,init-pin-ctrl-mode = <2>; - /* Enable follows HW_EN1 */ - qcom,enable-with-pin-ctrl = <0 2>; - }; - }; - - rpm-regulator-ldoa10 { - status = "okay"; - pmfalcon_l10: regulator-l10 { - regulator-min-microvolt = <1780000>; - regulator-max-microvolt = <1950000>; - status = "okay"; - }; - }; - - rpm-regulator-ldoa11 { - status = "okay"; - pmfalcon_l11: regulator-l11 { - regulator-min-microvolt = <1780000>; - regulator-max-microvolt = <1950000>; - status = "okay"; - }; - }; - - rpm-regulator-ldoa12 { - status = "okay"; - pmfalcon_l12: regulator-l12 { - regulator-min-microvolt = <1780000>; - regulator-max-microvolt = <1950000>; - status = "okay"; - }; - }; - - rpm-regulator-ldoa13 { - status = "okay"; - pmfalcon_l13: regulator-l13 { - regulator-min-microvolt = <1780000>; - regulator-max-microvolt = <1950000>; - status = "okay"; - }; - }; - - rpm-regulator-ldoa14 { - status = "okay"; - pmfalcon_l14: regulator-l14 { - regulator-min-microvolt = <1710000>; - regulator-max-microvolt = <1900000>; - status = "okay"; - }; - }; - - rpm-regulator-ldoa15 { - status = "okay"; - pmfalcon_l15: regulator-l15 { - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <2950000>; - status = "okay"; - }; - }; - - rpm-regulator-ldoa17 { - status = "okay"; - pmfalcon_l17: regulator-l17 { - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <2950000>; - status = "okay"; - }; - }; - - rpm-regulator-ldoa19 { - status = "okay"; - pmfalcon_l19: regulator-l19 { - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3400000>; - status = "okay"; - }; - - pmfalcon_l19_pin_ctrl: regulator-l19-pin-ctrl { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l19_pin_ctrl"; - qcom,set = <3>; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3400000>; - /* Force NPM follows HW_EN1 */ - qcom,init-pin-ctrl-mode = <2>; - /* Enable follows HW_EN1 */ - qcom,enable-with-pin-ctrl = <0 2>; - }; - }; - - rpm-regulator-ldob1 { - status = "okay"; - pm2falcon_l1: regulator-l1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <925000>; - status = "okay"; - }; - }; - - rpm-regulator-ldob2 { - status = "okay"; - pm2falcon_l2: regulator-l2 { - regulator-min-microvolt = <350000>; - regulator-max-microvolt = <3100000>; - status = "okay"; - }; - }; - - rpm-regulator-ldob3 { - status = "okay"; - pm2falcon_l3: regulator-l3 { - regulator-min-microvolt = <1710000>; - regulator-max-microvolt = <3600000>; - status = "okay"; - }; - }; - - rpm-regulator-ldob4 { - status = "okay"; - pm2falcon_l4: regulator-l4 { - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <2950000>; - status = "okay"; - }; - }; - - rpm-regulator-ldob5 { - status = "okay"; - pm2falcon_l5: regulator-l5 { - regulator-min-microvolt = <1721000>; - regulator-max-microvolt = <3600000>; - status = "okay"; - }; - }; - - rpm-regulator-ldob6 { - status = "okay"; - pm2falcon_l6: regulator-l6 { - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <3300000>; - status = "okay"; - }; - }; - - rpm-regulator-ldob7 { - status = "okay"; - pm2falcon_l7: regulator-l7 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3125000>; - status = "okay"; - }; - }; - - rpm-regulator-ldob8 { - status = "okay"; - pm2falcon_l8: regulator-l8 { - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3400000>; - status = "okay"; - }; - }; - - /* PM2FALCON L9 = VDD_SSC_CX supply */ - rpm-regulator-ldob9 { - status = "okay"; - pm2falcon_l9_level: regulator-l9-level { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l9_level"; - qcom,set = <3>; - regulator-min-microvolt = - ; - regulator-max-microvolt = - ; - qcom,use-voltage-level; - }; - - pm2falcon_l9_floor_level: regulator-l9-floor-level { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l9_floor_level"; - qcom,set = <3>; - regulator-min-microvolt = - ; - regulator-max-microvolt = - ; - qcom,use-voltage-floor-level; - qcom,always-send-voltage; - }; - }; - - /* PM2FALCON L10 = VDD_SSC_MX supply */ - rpm-regulator-ldob10 { - status = "okay"; - pm2falcon_l10_level: regulator-l10-level { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l10_level"; - qcom,set = <3>; - regulator-min-microvolt = - ; - regulator-max-microvolt = - ; - qcom,use-voltage-level; - }; - - pm2falcon_l10_floor_level: regulator-l10-floor-level { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l10_floor_level"; - qcom,set = <3>; - regulator-min-microvolt = - ; - regulator-max-microvolt = - ; - qcom,use-voltage-floor-level; - qcom,always-send-voltage; - }; - }; - - rpm-regulator-bobb { - status = "okay"; - pm2falcon_bob: regulator-bob { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3600000>; - status = "okay"; - }; - - pm2falcon_bob_pin1: regulator-bob-pin1 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_bob_pin1"; - qcom,set = <3>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3600000>; - qcom,use-pin-ctrl-voltage1; - }; - - pm2falcon_bob_pin2: regulator-bob-pin2 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_bob_pin2"; - qcom,set = <3>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3600000>; - qcom,use-pin-ctrl-voltage2; - }; - - pm2falcon_bob_pin3: regulator-bob-pin3 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_bob_pin3"; - qcom,set = <3>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3600000>; - qcom,use-pin-ctrl-voltage3; - }; - }; -}; - -&pmfalcon_charger { - smb2_vbus: qcom,smb2-vbus { - regulator-name = "smb2-vbus"; - }; - - smb2_vconn: qcom,smb2-vconn { - regulator-name = "smb2-vconn"; - }; -}; - -/* Stub regulators */ -/ { - /* GFX Supply */ - gfx_vreg_corner: regulator-gfx-corner { - compatible = "qcom,stub-regulator"; - regulator-name = "gfx_corner"; - regulator-min-microvolt = <1>; - regulator-max-microvolt = <7>; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts b/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts deleted file mode 100644 index c371ddeda563..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts +++ /dev/null @@ -1,146 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "msmfalcon.dtsi" -#include "msmfalcon-pinctrl.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON RUMI"; - compatible = "qcom,msmfalcon-rumi", "qcom,msmfalcon", "qcom,rumi"; - qcom,board-id = <15 0>; - qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, - <0x0001001b 0x0201011a 0x0 0x0>; - - chosen { - bootargs = "lpm_levels.sleep_disabled=1"; - }; -}; - -&usb3 { - /delete-property/ USB3_GDSC-supply; - /delete-property/ extcon; - dwc3@a800000 { - maximum-speed = "high-speed"; - }; -}; - -&ssphy { - compatible = "usb-nop-xceiv"; -}; - -&qusb_phy0 { - reg = <0x0a928000 0x8000>, - <0x0a8f8800 0x400>, - <0x0a920000 0x100>; - reg-names = "qusb_phy_base", - "qscratch_base", - "emu_phy_base"; - qcom,emulation; - qcom,qusb-phy-init-seq = <0x19 0x1404 - 0x20 0x1414 - 0x79 0x1410 - 0x00 0x1418 - 0x99 0x1404 - 0x04 0x1408 - 0xd9 0x1404>; - qcom,emu-dcm-reset-seq = <0x100000 0x20 - 0x0 0x20 - 0x1a0 0x20 - 0x5 0x14>; -}; - -&uartblsp1dm1 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&uart_console_active>; -}; - -&sdhc_1 { - /* device core power supply */ - vdd-supply = <&pm2falcon_l4>; - qcom,vdd-voltage-level = <2950000 2950000>; - qcom,vdd-current-level = <200 570000>; - - /* device communication power supply */ - vdd-io-supply = <&pmfalcon_l8>; - qcom,vdd-io-always-on; - qcom,vdd-io-lpm-sup; - qcom,vdd-io-voltage-level = <1800000 1800000>; - qcom,vdd-io-current-level = <200 325000>; - - pinctrl-names = "active", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; - - qcom,clk-rates = <400000 20000000 25000000 50000000 192000000 - 384000000>; - - qcom,nonremovable; - qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; - - status = "ok"; -}; - -&clock_gcc { - compatible = "qcom,dummycc"; - clock-output-names = "gcc_clocks"; -}; - -&pmfalcon_charger { - status = "disabled"; -}; - -&pmfalcon_fg { - status = "disabled"; -}; - -&clock_gfx { - compatible = "qcom,dummycc"; - clock-output-names = "gfx_clocks"; -}; - -&pmfalcon_pdphy { - status = "disabled"; -}; - -&clock_mmss { - compatible = "qcom,dummycc"; - clock-output-names = "mmss_clocks"; -}; - -&ufsphy1 { - vdda-phy-supply = <&pm2falcon_l1>; - vdda-pll-supply = <&pmfalcon_l10>; - vddp-ref-clk-supply = <&pmfalcon_l1>; - vdda-phy-max-microamp = <51400>; - vdda-pll-max-microamp = <14200>; - vddp-ref-clk-max-microamp = <100>; - vddp-ref-clk-always-on; -}; - -&ufs1 { - vdd-hba-supply = <&gdsc_ufs>; - vdd-hba-fixed-regulator; - vcc-supply = <&pm2falcon_l4>; - vccq2-supply = <&pmfalcon_l8>; - vcc-max-microamp = <500000>; - vccq2-max-microamp = <600000>; - qcom,disable-lpm; -}; - -&clock_debug { - compatible = "qcom,dummycc"; - clock-output-names = "debug_clocks"; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-sim.dts b/arch/arm/boot/dts/qcom/msmfalcon-sim.dts deleted file mode 100644 index 596aae818fab..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-sim.dts +++ /dev/null @@ -1,111 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -/dts-v1/; - -#include "msmfalcon.dtsi" -#include "msmfalcon-pinctrl.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON SIM"; - compatible = "qcom,msmfalcon-sim", "qcom,msmfalcon", "qcom,sim"; - qcom,board-id = <16 0>; - qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, - <0x0001001b 0x0201011a 0x0 0x0>; - - chosen { - bootargs = "lpm_levels.sleep_disabled=1"; - }; -}; - -&usb3 { - reg = <0xa800000 0xfc000>; - reg-names = "core_base"; - /delete-property/ extcon; - dwc3@a800000 { - maximum-speed = "high-speed"; - }; -}; - -&ssphy { - compatible = "usb-nop-xceiv"; -}; - -&qusb_phy0 { - compatible = "usb-nop-xceiv"; -}; - -&uartblsp1dm1 { - status = "ok"; - pinctrl-names = "default"; - pinctrl-0 = <&uart_console_active>; -}; - -&sdhc_1 { - /* device core power supply */ - vdd-supply = <&pm2falcon_l4>; - qcom,vdd-voltage-level = <2950000 2950000>; - qcom,vdd-current-level = <200 570000>; - - /* device communication power supply */ - vdd-io-supply = <&pmfalcon_l8>; - qcom,vdd-io-always-on; - qcom,vdd-io-lpm-sup; - qcom,vdd-io-voltage-level = <1800000 1800000>; - qcom,vdd-io-current-level = <200 325000>; - - pinctrl-names = "active", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; - - qcom,clk-rates = <400000 20000000 25000000 50000000 192000000 - 384000000>; - - qcom,nonremovable; - qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; - - status = "ok"; -}; - -&pmfalcon_charger { - status = "disabled"; -}; - -&pmfalcon_fg { - status = "disabled"; -}; - -&pmfalcon_pdphy { - status = "disabled"; -}; - -&ufsphy1 { - vdda-phy-supply = <&pm2falcon_l1>; - vdda-pll-supply = <&pmfalcon_l10>; - vddp-ref-clk-supply = <&pmfalcon_l1>; - vdda-phy-max-microamp = <51400>; - vdda-pll-max-microamp = <14200>; - vddp-ref-clk-max-microamp = <100>; - vddp-ref-clk-always-on; - status = "ok"; -}; - -&ufs1 { - vdd-hba-supply = <&gdsc_ufs>; - vdd-hba-fixed-regulator; - vcc-supply = <&pm2falcon_l4>; - vccq2-supply = <&pmfalcon_l8>; - vcc-max-microamp = <500000>; - vccq2-max-microamp = <600000>; - status = "ok"; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-smp2p.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-smp2p.dtsi deleted file mode 100644 index b43fae954ec2..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-smp2p.dtsi +++ /dev/null @@ -1,244 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -&soc { - qcom,smp2p-modem@17911008 { - compatible = "qcom,smp2p"; - reg = <0x17911008 0x4>; - qcom,remote-pid = <1>; - qcom,irq-bitmask = <0x4000>; - interrupts = <0 451 1>; - }; - - qcom,smp2p-adsp@17911008 { - compatible = "qcom,smp2p"; - reg = <0x17911008 0x4>; - qcom,remote-pid = <2>; - qcom,irq-bitmask = <0x400>; - interrupts = <0 158 1>; - }; - - qcom,smp2p-cdsp@17911008 { - compatible = "qcom,smp2p"; - reg = <0x17911008 0x4>; - qcom,remote-pid = <5>; - qcom,irq-bitmask = <0x40000000>; - interrupts = <0 514 1>; - }; - - smp2pgpio_smp2p_15_in: qcom,smp2pgpio-smp2p-15-in { - compatible = "qcom,smp2pgpio"; - qcom,entry-name = "smp2p"; - qcom,remote-pid = <15>; - qcom,is-inbound; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - qcom,smp2pgpio_test_smp2p_15_in { - compatible = "qcom,smp2pgpio_test_smp2p_15_in"; - gpios = <&smp2pgpio_smp2p_15_in 0 0>; - }; - - smp2pgpio_smp2p_15_out: qcom,smp2pgpio-smp2p-15-out { - compatible = "qcom,smp2pgpio"; - qcom,entry-name = "smp2p"; - qcom,remote-pid = <15>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - qcom,smp2pgpio_test_smp2p_15_out { - compatible = "qcom,smp2pgpio_test_smp2p_15_out"; - gpios = <&smp2pgpio_smp2p_15_out 0 0>; - }; - - smp2pgpio_smp2p_1_in: qcom,smp2pgpio-smp2p-1-in { - compatible = "qcom,smp2pgpio"; - qcom,entry-name = "smp2p"; - qcom,remote-pid = <1>; - qcom,is-inbound; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - qcom,smp2pgpio_test_smp2p_1_in { - compatible = "qcom,smp2pgpio_test_smp2p_1_in"; - gpios = <&smp2pgpio_smp2p_1_in 0 0>; - }; - - smp2pgpio_smp2p_1_out: qcom,smp2pgpio-smp2p-1-out { - compatible = "qcom,smp2pgpio"; - qcom,entry-name = "smp2p"; - qcom,remote-pid = <1>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - qcom,smp2pgpio_test_smp2p_1_out { - compatible = "qcom,smp2pgpio_test_smp2p_1_out"; - gpios = <&smp2pgpio_smp2p_1_out 0 0>; - }; - - smp2pgpio_smp2p_2_in: qcom,smp2pgpio-smp2p-2-in { - compatible = "qcom,smp2pgpio"; - qcom,entry-name = "smp2p"; - qcom,remote-pid = <2>; - qcom,is-inbound; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - qcom,smp2pgpio_test_smp2p_2_in { - compatible = "qcom,smp2pgpio_test_smp2p_2_in"; - gpios = <&smp2pgpio_smp2p_2_in 0 0>; - }; - - smp2pgpio_smp2p_2_out: qcom,smp2pgpio-smp2p-2-out { - compatible = "qcom,smp2pgpio"; - qcom,entry-name = "smp2p"; - qcom,remote-pid = <2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - qcom,smp2pgpio_test_smp2p_2_out { - compatible = "qcom,smp2pgpio_test_smp2p_2_out"; - gpios = <&smp2pgpio_smp2p_2_out 0 0>; - }; - - smp2pgpio_sleepstate_2_out: qcom,smp2pgpio-sleepstate-gpio-2-out { - compatible = "qcom,smp2pgpio"; - qcom,entry-name = "sleepstate"; - qcom,remote-pid = <2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - qcom,smp2pgpio-sleepstate-2-out { - compatible = "qcom,smp2pgpio-sleepstate-out"; - gpios = <&smp2pgpio_sleepstate_2_out 0 0>; - }; - - smp2pgpio_smp2p_5_in: qcom,smp2pgpio-smp2p-5-in { - compatible = "qcom,smp2pgpio"; - qcom,entry-name = "smp2p"; - qcom,remote-pid = <5>; - qcom,is-inbound; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - qcom,smp2pgpio_test_smp2p_5_in { - compatible = "qcom,smp2pgpio_test_smp2p_5_in"; - gpios = <&smp2pgpio_smp2p_5_in 0 0>; - }; - - smp2pgpio_smp2p_5_out: qcom,smp2pgpio-smp2p-5-out { - compatible = "qcom,smp2pgpio"; - qcom,entry-name = "smp2p"; - qcom,remote-pid = <5>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - qcom,smp2pgpio_test_smp2p_5_out { - compatible = "qcom,smp2pgpio_test_smp2p_5_out"; - gpios = <&smp2pgpio_smp2p_5_out 0 0>; - }; - - /* ssr - inbound entry from mss */ - smp2pgpio_ssr_smp2p_1_in: qcom,smp2pgpio-ssr-smp2p-1-in { - compatible = "qcom,smp2pgpio"; - qcom,entry-name = "slave-kernel"; - qcom,remote-pid = <1>; - qcom,is-inbound; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - /* ssr - outbound entry to mss */ - smp2pgpio_ssr_smp2p_1_out: qcom,smp2pgpio-ssr-smp2p-1-out { - compatible = "qcom,smp2pgpio"; - qcom,entry-name = "master-kernel"; - qcom,remote-pid = <1>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - /* ssr - inbound entry from lpass */ - smp2pgpio_ssr_smp2p_2_in: qcom,smp2pgpio-ssr-smp2p-2-in { - compatible = "qcom,smp2pgpio"; - qcom,entry-name = "slave-kernel"; - qcom,remote-pid = <2>; - qcom,is-inbound; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - /* ssr - outbound entry to lpass */ - smp2pgpio_ssr_smp2p_2_out: qcom,smp2pgpio-ssr-smp2p-2-out { - compatible = "qcom,smp2pgpio"; - qcom,entry-name = "master-kernel"; - qcom,remote-pid = <2>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - /* ssr - inbound entry from turing */ - smp2pgpio_ssr_smp2p_5_in: qcom,smp2pgpio-ssr-smp2p-5-in { - compatible = "qcom,smp2pgpio"; - qcom,entry-name = "slave-kernel"; - qcom,remote-pid = <5>; - qcom,is-inbound; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - /* ssr - outbound entry to turing */ - smp2pgpio_ssr_smp2p_5_out: qcom,smp2pgpio-ssr-smp2p-5-out { - compatible = "qcom,smp2pgpio"; - qcom,entry-name = "master-kernel"; - qcom,remote-pid = <5>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-vidc.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-vidc.dtsi deleted file mode 100644 index 9a9c96f5181d..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-vidc.dtsi +++ /dev/null @@ -1,264 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - - -&soc { - msm_vidc: qcom,vidc@cc00000 { - compatible = "qcom,msm-vidc"; - status = "ok"; - reg = <0xcc00000 0x100000>; - interrupts = ; - qcom,hfi = "venus"; - qcom,hfi-version = "3xx"; - qcom,firmware-name = "venus"; - qcom,sw-power-collapse; - qcom,reg-presets = - <0x80010 0x00000003>, - <0x80018 0x05555556>, - <0x8001c 0x05555556>; - - qcom,max-hw-load = <1036800>; /* Full 4k @ 30 */ - qcom,allowed-clock-rates = - /* TURBO NOM+ NOM - * SVS+ SVS SVS- - */ - <518400000 441600000 404000000 - 320000000 269330000 133330000>; - - qcom,dcvs-tbl = - /* Dec UHD@30 All decoder - NOM to SVS+ */ - <897600 734400 979200 0x3f00000c>, - - /* Dec DCI@24 HEVC - NOM to SVS+ */ - <816000 734400 829440 0x0c000000>, - - /* Enc UHD@30 H264/HEVC - TURBO to NOM+ */ - <897600 897600 979200 0x4000004>; - qcom,dcvs-limit = - <32400 30>, /* Encoder UHD */ - <32400 24>; /* Decoder UHD */ - - /* Regulators */ - smmu-vdd-supply = <&gdsc_bimc_smmu>; - venus-supply = <&gdsc_venus>; - venus-core0-supply = <&gdsc_venus_core0>; - - /* Clocks */ - clock-names = "gcc_mmss_sys_noc_axi_clk", - "mmssnoc_axi_clk", "mmss_mnoc_ahb_clk", - "mmss_bimc_smmu_ahb_clk", "mmss_bimc_smmu_axi_clk", - "mmss_video_core_clk", "mmss_video_ahb_clk", - "mmss_video_axi_clk", - "mmss_video_core0_clk"; - clocks = <&clock_gcc GCC_MMSS_SYS_NOC_AXI_CLK>, - <&clock_rpmcc MMSSNOC_AXI_CLK>, - <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, - <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, - <&clock_mmss MMSS_VIDEO_CORE_CLK>, - <&clock_mmss MMSS_VIDEO_AHB_CLK>, - <&clock_mmss MMSS_VIDEO_AXI_CLK>, - <&clock_mmss MMSS_VIDEO_SUBCORE0_CLK>; - qcom,clock-configs = <0x0 0x0 0x0 0x0 0x0 - 0x3 0x0 0x2 0x3>; - - /* Buses */ - bus_cnoc { - compatible = "qcom,msm-vidc,bus"; - label = "cnoc"; - qcom,bus-master = ; - qcom,bus-slave = ; - qcom,bus-governor = "performance"; - qcom,bus-range-kbps = <1 1>; - }; - - venus_bus_ddr { - compatible = "qcom,msm-vidc,bus"; - label = "venus-ddr"; - qcom,bus-master = ; - qcom,bus-slave = ; - qcom,bus-governor = "venus-ddr-gov"; - qcom,bus-range-kbps = <1000 2365000>; - }; - - arm9_bus_ddr { - compatible = "qcom,msm-vidc,bus"; - label = "venus-arm9-ddr"; - qcom,bus-master = ; - qcom,bus-slave = ; - qcom,bus-governor = "performance"; - qcom,bus-range-kbps = <1 1>; - }; - - qcom,clock-freq-tbl { - qcom,profile-enc { - qcom,codec-mask = <0x55555555>; - qcom,cycles-per-mb = <863>; - qcom,low-power-mode-factor = <35616>; - }; - qcom,profile-dec { - qcom,codec-mask = <0xf3ffffff>; - qcom,cycles-per-mb = <355>; - }; - qcom,profile-hevcdec { - qcom,codec-mask = <0x0c000000>; - qcom,cycles-per-mb = <400>; - }; - }; - - venus-ddr-gov { - compatible = "qcom,msm-vidc,governor,table"; - name = "venus-ddr-gov"; - status = "ok"; - qcom,bus-freq-table { - qcom,profile-enc { - qcom,codec-mask = <0x55555555>; - qcom,load-busfreq-tbl = - <979200 1044000>, /* UHD30E */ - <864000 887000>, /* 720p240LPE */ - <489600 666000>, /* 1080p60E */ - <432000 578000>, /* 720p120E */ - <244800 346000>, /* 1080p30E */ - <216000 293000>, /* 720p60E */ - <108000 151000>, /* 720p30E */ - <0 0>; - }; - qcom,profile-dec { - qcom,codec-mask = <0xffffffff>; - qcom,load-busfreq-tbl = - <979200 2365000>, /* UHD30D */ - <864000 1978000>, /* 720p240D */ - <489600 1133000>, /* 1080p60D */ - <432000 994000>, /* 720p120D */ - <244800 580000>, /* 1080p30D */ - <216000 501000>, /* 720p60E */ - <108000 255000>, /* 720p30D */ - <0 0>; - }; - qcom,profile-dec-ubwc { - qcom,codec-mask = <0xffffffff>; - qcom,ubwc-mode; - qcom,load-busfreq-tbl = - <979200 1892000>, /* UHD30D */ - <864000 1554000>, /* 720p240D */ - <489600 895000>, /* 1080p60D */ - <432000 781000>, /* 720p120D */ - <244800 460000>, /* 1080p30D */ - <216000 301000>, /* 720p60E */ - <108000 202000>, /* 720p30D */ - <0 0>; - }; - qcom,profile-dec-ubwc-10bit { - qcom,codec-mask = <0xffffffff>; - qcom,ubwc-10bit; - qcom,load-busfreq-tbl = - <979200 2446336>, /* UHD30D */ - <864000 2108416>, /* 720p240D */ - <489600 1207296>, /* 1080p60D */ - <432000 1058816>, /* 720p120D */ - <244800 616448>, /* 1080p30D */ - <216000 534528>, /* 720p60D */ - <108000 271360>, /* 720p30D */ - <0 0>; - }; - }; - }; - - - /* MMUs */ - non_secure_cb { - compatible = "qcom,msm-vidc,context-bank"; - label = "venus_ns"; - iommus = - <&mmss_bimc_smmu 0x400>, - <&mmss_bimc_smmu 0x401>, - <&mmss_bimc_smmu 0x40a>, - <&mmss_bimc_smmu 0x407>, - <&mmss_bimc_smmu 0x40e>, - <&mmss_bimc_smmu 0x40f>, - <&mmss_bimc_smmu 0x408>, - <&mmss_bimc_smmu 0x409>, - <&mmss_bimc_smmu 0x40b>, - <&mmss_bimc_smmu 0x40c>, - <&mmss_bimc_smmu 0x40d>, - <&mmss_bimc_smmu 0x410>, - <&mmss_bimc_smmu 0x421>, - <&mmss_bimc_smmu 0x428>, - <&mmss_bimc_smmu 0x429>, - <&mmss_bimc_smmu 0x42b>, - <&mmss_bimc_smmu 0x42c>, - <&mmss_bimc_smmu 0x42d>, - <&mmss_bimc_smmu 0x411>, - <&mmss_bimc_smmu 0x431>; - buffer-types = <0xfff>; - virtual-addr-pool = <0x70800000 0x6f800000>; - }; - - firmware_cb { - compatible = "qcom,msm-vidc,context-bank"; - qcom,fw-context-bank; - iommus = <&mmss_bimc_smmu 0x580>, - <&mmss_bimc_smmu 0x586>; - }; - secure_bitstream_cb { - compatible = "qcom,msm-vidc,context-bank"; - label = "venus_sec_bitstream"; - iommus = <&mmss_bimc_smmu 0x500>, - <&mmss_bimc_smmu 0x502>, - <&mmss_bimc_smmu 0x509>, - <&mmss_bimc_smmu 0x50a>, - <&mmss_bimc_smmu 0x50b>, - <&mmss_bimc_smmu 0x50e>, - <&mmss_bimc_smmu 0x526>, - <&mmss_bimc_smmu 0x529>, - <&mmss_bimc_smmu 0x52b>; - buffer-types = <0x241>; - virtual-addr-pool = <0x4b000000 0x25800000>; - qcom,secure-context-bank; - }; - - venus_secure_pixel_cb: secure_pixel_cb { - compatible = "qcom,msm-vidc,context-bank"; - label = "venus_sec_pixel"; - iommus = <&mmss_bimc_smmu 0x504>, - <&mmss_bimc_smmu 0x50c>, - <&mmss_bimc_smmu 0x510>, - <&mmss_bimc_smmu 0x52c>; - buffer-types = <0x106>; - virtual-addr-pool = <0x25800000 0x25800000>; - qcom,secure-context-bank; - }; - - venus_secure_non_pixel_cb: secure_non_pixel_cb { - compatible = "qcom,msm-vidc,context-bank"; - label = "venus_sec_non_pixel"; - iommus = <&mmss_bimc_smmu 0x505>, - <&mmss_bimc_smmu 0x507>, - <&mmss_bimc_smmu 0x508>, - <&mmss_bimc_smmu 0x50d>, - <&mmss_bimc_smmu 0x50f>, - <&mmss_bimc_smmu 0x525>, - <&mmss_bimc_smmu 0x528>, - <&mmss_bimc_smmu 0x52d>, - <&mmss_bimc_smmu 0x540>; - buffer-types = <0x480>; - virtual-addr-pool = <0x1000000 0x24800000>; - qcom,secure-context-bank; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-wcd.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-wcd.dtsi deleted file mode 100644 index 006bf0175874..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-wcd.dtsi +++ /dev/null @@ -1,197 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -&slim_aud { - tasha_codec { - wsa_spkr_sd1: msm_cdc_pinctrll { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&spkr_1_sd_n_active>; - pinctrl-1 = <&spkr_1_sd_n_sleep>; - }; - - wsa_spkr_sd2: msm_cdc_pinctrlr { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&spkr_2_sd_n_active>; - pinctrl-1 = <&spkr_2_sd_n_sleep>; - }; - - tasha_hph_en0: msm_cdc_pinctrl_hph_en0 { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&hph_en0_active>; - pinctrl-1 = <&hph_en0_sleep>; - }; - - tasha_hph_en1: msm_cdc_pinctrl_hph_en1 { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&hph_en1_active>; - pinctrl-1 = <&hph_en1_sleep>; - }; - }; - - tavil_codec { - wcd: wcd_pinctrl@5 { - compatible = "qcom,wcd-pinctrl"; - qcom,num-gpios = <5>; - gpio-controller; - #gpio-cells = <2>; - - us_euro_sw_wcd_active: us_euro_sw_wcd_active { - mux { - pins = "gpio1"; - }; - - config { - pins = "gpio1"; - output-high; - }; - }; - - us_euro_sw_wcd_sleep: us_euro_sw_wcd_sleep { - mux { - pins = "gpio1"; - }; - - config { - pins = "gpio1"; - output-low; - }; - }; - - spkr_1_wcd_en_active: spkr_1_wcd_en_active { - mux { - pins = "gpio2"; - }; - - config { - pins = "gpio2"; - output-high; - }; - }; - - spkr_1_wcd_en_sleep: spkr_1_wcd_en_sleep { - mux { - pins = "gpio2"; - }; - - config { - pins = "gpio2"; - input-enable; - }; - }; - - spkr_2_wcd_en_active: spkr_2_sd_n_active { - mux { - pins = "gpio3"; - }; - - config { - pins = "gpio3"; - output-high; - }; - }; - - spkr_2_wcd_en_sleep: spkr_2_sd_n_sleep { - mux { - pins = "gpio3"; - }; - - config { - pins = "gpio3"; - input-enable; - }; - }; - - hph_en0_wcd_active: hph_en0_wcd_active { - mux { - pins = "gpio4"; - }; - - config { - pins = "gpio4"; - output-high; - }; - }; - - hph_en0_wcd_sleep: hph_en0_wcd_sleep { - mux { - pins = "gpio4"; - }; - - config { - pins = "gpio4"; - output-low; - }; - }; - - hph_en1_wcd_active: hph_en1_wcd_active { - mux { - pins = "gpio5"; - }; - - config { - pins = "gpio5"; - output-high; - }; - }; - - hph_en1_wcd_sleep: hph_en1_wcd_sleep { - mux { - pins = "gpio5"; - }; - - config { - pins = "gpio5"; - output-low; - }; - }; - }; - - wsa_spkr_wcd_sd1: msm_cdc_pinctrll { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&spkr_1_wcd_en_active>; - pinctrl-1 = <&spkr_1_wcd_en_sleep>; - }; - - wsa_spkr_wcd_sd2: msm_cdc_pinctrlr { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&spkr_2_wcd_en_active>; - pinctrl-1 = <&spkr_2_wcd_en_sleep>; - }; - - tavil_us_euro_sw: msm_cdc_pinctrl_us_euro_sw { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&us_euro_sw_wcd_active>; - pinctrl-1 = <&us_euro_sw_wcd_sleep>; - }; - - tavil_hph_en0: msm_cdc_pinctrl_hph_en0 { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&hph_en0_wcd_active>; - pinctrl-1 = <&hph_en0_wcd_sleep>; - }; - - tavil_hph_en1: msm_cdc_pinctrl_hph_en1 { - compatible = "qcom,msm-cdc-pinctrl"; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&hph_en1_wcd_active>; - pinctrl-1 = <&hph_en1_wcd_sleep>; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-wsa881x.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-wsa881x.dtsi deleted file mode 100644 index 123f922facdd..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-wsa881x.dtsi +++ /dev/null @@ -1,79 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "msmfalcon-wcd.dtsi" - -&slim_aud { - tasha_codec { - swr_master { - compatible = "qcom,swr-wcd"; - #address-cells = <2>; - #size-cells = <0>; - - wsa881x_211: wsa881x@20170211 { - compatible = "qcom,wsa881x"; - reg = <0x0 0x20170211>; - qcom,spkr-sd-n-node = <&wsa_spkr_sd1>; - }; - - wsa881x_212: wsa881x@20170212 { - compatible = "qcom,wsa881x"; - reg = <0x0 0x20170212>; - qcom,spkr-sd-n-node = <&wsa_spkr_sd2>; - }; - - wsa881x_213: wsa881x@21170213 { - compatible = "qcom,wsa881x"; - reg = <0x0 0x21170213>; - qcom,spkr-sd-n-node = <&wsa_spkr_sd1>; - }; - - wsa881x_214: wsa881x@21170214 { - compatible = "qcom,wsa881x"; - reg = <0x0 0x21170214>; - qcom,spkr-sd-n-node = <&wsa_spkr_sd2>; - }; - }; - }; - - tavil_codec { - swr_master { - compatible = "qcom,swr-wcd"; - #address-cells = <2>; - #size-cells = <0>; - - wsa881x_0211: wsa881x@20170211 { - compatible = "qcom,wsa881x"; - reg = <0x0 0x20170211>; - qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>; - }; - - wsa881x_0212: wsa881x@20170212 { - compatible = "qcom,wsa881x"; - reg = <0x0 0x20170212>; - qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd2>; - }; - - wsa881x_0213: wsa881x@21170213 { - compatible = "qcom,wsa881x"; - reg = <0x0 0x21170213>; - qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>; - }; - - wsa881x_0214: wsa881x@21170214 { - compatible = "qcom,wsa881x"; - reg = <0x0 0x21170214>; - qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd2>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msmfalcon.dtsi deleted file mode 100644 index b57e7d033c70..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon.dtsi +++ /dev/null @@ -1,2278 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "skeleton64.dtsi" -#include -#include -#include -#include -#include -#include -#include - -/ { - model = "Qualcomm Technologies, Inc. MSM FALCON"; - compatible = "qcom,msmfalcon"; - qcom,msm-id = <317 0x0>; - interrupt-parent = <&intc>; - - aliases { - serial0 = &uartblsp1dm1; - sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ - }; - - chosen { - stdout-path = "serial0"; - bootargs = "rcupdate.rcu_expedited=1"; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x0>; - enable-method = "psci"; - qcom,limits-info = <&mitigation_profile0>; - qcom,ea = <&ea0>; - efficiency = <1024>; - next-level-cache = <&L2_0>; - L2_0: l2-cache { - compatible = "arm,arch-cache"; - cache-level = <2>; - /* A53 L2 dump not supported */ - qcom,dump-size = <0x0>; - }; - L1_I_0: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9040>; - }; - L1_D_0: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9040>; - }; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x1>; - enable-method = "psci"; - qcom,limits-info = <&mitigation_profile0>; - qcom,ea = <&ea1>; - efficiency = <1024>; - next-level-cache = <&L2_0>; - L1_I_1: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9040>; - }; - L1_D_1: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9040>; - }; - }; - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x2>; - enable-method = "psci"; - qcom,limits-info = <&mitigation_profile0>; - qcom,ea = <&ea2>; - efficiency = <1024>; - next-level-cache = <&L2_0>; - L1_I_2: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9040>; - }; - L1_D_2: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9040>; - }; - }; - - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x3>; - enable-method = "psci"; - qcom,limits-info = <&mitigation_profile0>; - qcom,ea = <&ea3>; - efficiency = <1024>; - next-level-cache = <&L2_0>; - L1_I_3: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9040>; - }; - L1_D_3: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x9040>; - }; - }; - - CPU4: cpu@100 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x100>; - enable-method = "psci"; - qcom,limits-info = <&mitigation_profile1>; - qcom,ea = <&ea4>; - efficiency = <1536>; - next-level-cache = <&L2_1>; - L2_1: l2-cache { - compatible = "arm,arch-cache"; - cache-level = <2>; - }; - L1_I_100: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x12000>; - }; - L1_D_100: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x12000>; - }; - }; - - CPU5: cpu@101 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x101>; - enable-method = "psci"; - qcom,limits-info = <&mitigation_profile2>; - qcom,ea = <&ea5>; - efficiency = <1536>; - next-level-cache = <&L2_1>; - L1_I_101: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x12000>; - }; - L1_D_101: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x12000>; - }; - }; - - CPU6: cpu@102 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x102>; - enable-method = "psci"; - qcom,limits-info = <&mitigation_profile3>; - qcom,ea = <&ea6>; - efficiency = <1536>; - next-level-cache = <&L2_1>; - L1_I_102: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x12000>; - }; - L1_D_102: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x12000>; - }; - }; - - CPU7: cpu@103 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x103>; - enable-method = "psci"; - qcom,limits-info = <&mitigation_profile4>; - qcom,ea = <&ea7>; - efficiency = <1536>; - next-level-cache = <&L2_1>; - L1_I_103: l1-icache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x12000>; - }; - L1_D_103: l1-dcache { - compatible = "arm,arch-cache"; - qcom,dump-size = <0x12000>; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - }; - - cluster1 { - core0 { - cpu = <&CPU4>; - }; - - core1 { - cpu = <&CPU5>; - }; - - core2 { - cpu = <&CPU6>; - }; - - core3 { - cpu = <&CPU7>; - }; - }; - }; - }; - - clocks { - xo_board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - clock-output-names = "xo_board"; - }; - - sleep_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32764>; - clock-output-names = "sleep_clk"; - }; - }; - - soc: soc { }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - removed_regions: removed_regions@85800000 { - compatible = "removed-dma-pool"; - no-map; - reg = <0x0 0x85800000 0x0 0x3700000>; - }; - - modem_fw_mem: modem_fw_region@8ac00000 { - compatible = "removed-dma-pool"; - no-map; - reg = <0x0 0x8ac00000 0x0 0x7e00000>; - }; - - adsp_fw_mem: adsp_fw_region@92a00000 { - compatible = "removed-dma-pool"; - no-map; - reg = <0x0 0x92a00000 0x0 0x1e00000>; - }; - - cdsp_fw_mem: cdsp_fw_region@94800000 { - compatible = "removed-dma-pool"; - no-map; - reg = <0x0 0x94800000 0x0 0x600000>; - }; - - venus_fw_mem: venus_fw_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x80000000 0x0 0x20000000>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x800000>; - }; - - adsp_mem: adsp_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x400000>; - }; - - qseecom_mem: qseecom_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1400000>; - }; - - secure_display_memory: secure_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x5c00000>; - }; - }; - - bluetooth: bt_wcn3990 { - compatible = "qca,wcn3990"; - qca,bt-vdd-core-supply = <&pmfalcon_l9_pin_ctrl>; - qca,bt-vdd-pa-supply = <&pmfalcon_l6_pin_ctrl>; - qca,bt-vdd-ldo-supply = <&pmfalcon_l19_pin_ctrl>; - qca,bt-chip-pwd-supply = <&pm2falcon_bob_pin1>; - clocks = <&clock_rpmcc RPM_RF_CLK1>; - clock-names = "rf_clk1"; - - qca,bt-vdd-core-voltage-level = <1800000 1900000>; - qca,bt-vdd-pa-voltage-level = <1304000 1370000>; - qca,bt-vdd-ldo-voltage-level = <3312000 3400000>; - qca,bt-chip-pwd-voltage-level = <3600000 3600000>; - - qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ - qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ - qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */ - }; -}; - -#include "msmfalcon-smp2p.dtsi" -#include "msmfalcon-coresight.dtsi" -&soc { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; - compatible = "simple-bus"; - - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - reg = <0x17a00000 0x10000>, /* GICD */ - <0x17b00000 0x100000>; /* GICR * 8 */ - #interrupt-cells = <3>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-controller; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x20000>; - interrupts = <1 9 4>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 1 0xf08>, - <1 2 0xf08>, - <1 3 0xf08>, - <1 0 0xf08>; - clock-frequency = <19200000>; - }; - - dma_blsp1: qcom,sps-dma@0xc144000{ /* BLSP1 */ - #dma-cells = <4>; - compatible = "qcom,sps-dma"; - reg = <0xc144000 0x1F000>; - interrupts = <0 238 0>; - qcom,summing-threshold = <0x10>; - }; - - dma_blsp2: qcom,sps-dma@0xc184000{ /* BLSP2 */ - #dma-cells = <4>; - compatible = "qcom,sps-dma"; - reg = <0xc184000 0x1F000>; - interrupts = <0 239 0>; - qcom,summing-threshold = <0x10>; - }; - - restart@10ac000 { - compatible = "qcom,pshold"; - reg = <0x10ac000 0x4>, - <0x1fd3000 0x4>; - reg-names = "pshold-base", "tcsr-boot-misc-detect"; - }; - - spmi_bus: qcom,spmi@800f000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x800f000 0x1000>, - <0x8400000 0x1000000>, - <0x9400000 0x1000000>, - <0xa400000 0x220000>, - <0x800a000 0x3000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - cell-index = <0>; - qcom,not-wakeup; /* Needed until Full-boot-chain enabled */ - status = "ok"; - }; - - cpuss_dump { - compatible = "qcom,cpuss-dump"; - qcom,l1_i_cache0 { - qcom,dump-node = <&L1_I_0>; - qcom,dump-id = <0x60>; - }; - qcom,l1_i_cache1 { - qcom,dump-node = <&L1_I_1>; - qcom,dump-id = <0x61>; - }; - qcom,l1_i_cache2 { - qcom,dump-node = <&L1_I_2>; - qcom,dump-id = <0x62>; - }; - qcom,l1_i_cache3 { - qcom,dump-node = <&L1_I_3>; - qcom,dump-id = <0x63>; - }; - qcom,l1_i_cache100 { - qcom,dump-node = <&L1_I_100>; - qcom,dump-id = <0x64>; - }; - qcom,l1_i_cache101 { - qcom,dump-node = <&L1_I_101>; - qcom,dump-id = <0x65>; - }; - qcom,l1_i_cache102 { - qcom,dump-node = <&L1_I_102>; - qcom,dump-id = <0x66>; - }; - qcom,l1_i_cache103 { - qcom,dump-node = <&L1_I_103>; - qcom,dump-id = <0x67>; - }; - qcom,l1_d_cache0 { - qcom,dump-node = <&L1_D_0>; - qcom,dump-id = <0x80>; - }; - qcom,l1_d_cache1 { - qcom,dump-node = <&L1_D_1>; - qcom,dump-id = <0x81>; - }; - qcom,l1_d_cache2 { - qcom,dump-node = <&L1_D_2>; - qcom,dump-id = <0x82>; - }; - qcom,l1_d_cache3 { - qcom,dump-node = <&L1_D_3>; - qcom,dump-id = <0x83>; - }; - qcom,l1_d_cache100 { - qcom,dump-node = <&L1_D_100>; - qcom,dump-id = <0x84>; - }; - qcom,l1_d_cache101 { - qcom,dump-node = <&L1_D_101>; - qcom,dump-id = <0x85>; - }; - qcom,l1_d_cache102 { - qcom,dump-node = <&L1_D_102>; - qcom,dump-id = <0x86>; - }; - qcom,l1_d_cache103 { - qcom,dump-node = <&L1_D_103>; - qcom,dump-id = <0x87>; - }; - }; - - wdog: qcom,wdt@17817000 { - status = "disabled"; - compatible = "qcom,msm-watchdog"; - reg = <0x17817000 0x1000>; - reg-names = "wdt-base"; - interrupts = <0 3 0>, <0 4 0>; - qcom,bark-time = <11000>; - qcom,pet-time = <10000>; - qcom,ipi-ping; - qcom,wakeup-enable; - }; - - qcom,sps { - compatible = "qcom,msm_sps_4k"; - qcom,pipe-attr-ee; - }; - - qcom,memshare { - compatible = "qcom,memshare"; - - qcom,client_1 { - compatible = "qcom,memshare-peripheral"; - qcom,peripheral-size = <0x200000>; - qcom,client-id = <0>; - qcom,allocate-boot-time; - label = "modem"; - }; - - qcom,client_2 { - compatible = "qcom,memshare-peripheral"; - qcom,peripheral-size = <0x300000>; - qcom,client-id = <2>; - label = "modem"; - }; - - mem_client_3_size: qcom,client_3 { - compatible = "qcom,memshare-peripheral"; - qcom,peripheral-size = <0x0>; - qcom,client-id = <1>; - label = "modem"; - }; - }; - - tsens: tsens@10ad000 { - compatible = "qcom,msmfalcon-tsens"; - reg = <0x10ad000 0x2000>, - <0x784240 0x1000>; - reg-names = "tsens_physical", "tsens_eeprom_physical"; - interrupts = <0 184 0>, <0 430 0>; - interrupt-names = "tsens-upper-lower", "tsens-critical"; - qcom,sensors = <14>; - qcom,slope = <3200 3200 3200 3200 3200 3200 3200 3200 - 3200 3200 3200 3200 3200 3200>; - }; - - uartblsp1dm1: serial@0c170000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xc170000 0x1000>; - interrupts = <0 108 0>; - status = "disabled"; - clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>, - <&clock_gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - }; - - qcom,sensor-information { - compatible = "qcom,sensor-information"; - sensor_information0: qcom,sensor-information-0 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor0"; - qcom,scaling-factor = <10>; - }; - sensor_information1: qcom,sensor-information-1 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor1"; - qcom,scaling-factor = <10>; - }; - sensor_information2: qcom,sensor-information-2 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor2"; - qcom,scaling-factor = <10>; - }; - sensor_information3: qcom,sensor-information-3 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor3"; - qcom,scaling-factor = <10>; - }; - sensor_information4: qcom,sensor-information-4 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor4"; - qcom,scaling-factor = <10>; - }; - sensor_information5: qcom,sensor-information-5 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor5"; - qcom,scaling-factor = <10>; - }; - sensor_information6: qcom,sensor-information-6 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor6"; - qcom,scaling-factor = <10>; - }; - sensor_information7: qcom,sensor-information-7 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor7"; - qcom,scaling-factor = <10>; - }; - sensor_information8: qcom,sensor-information-8 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor8"; - qcom,scaling-factor = <10>; - qcom,alias-name = "gpu"; - }; - sensor_information9: qcom,sensor-information-9 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor9"; - qcom,scaling-factor = <10>; - }; - sensor_information10: qcom,sensor-information-10 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor10"; - qcom,scaling-factor = <10>; - }; - sensor_information11: qcom,sensor-information-11 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor11"; - qcom,scaling-factor = <10>; - }; - sensor_information12: qcom,sensor-information-12 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor12"; - qcom,scaling-factor = <10>; - }; - sensor_information13: qcom,sensor-information-13 { - qcom,sensor-type = "tsens"; - qcom,sensor-name = "tsens_tz_sensor13"; - qcom,scaling-factor = <10>; - }; - sensor_information14: qcom,sensor-information-14 { - qcom,sensor-type = "alarm"; - qcom,sensor-name = "pmfalcon_tz"; - qcom,scaling-factor = <1000>; - }; - sensor_information15: qcom,sensor-information-15 { - qcom,sensor-type = "adc"; - qcom,sensor-name = "msm_therm"; - }; - sensor_information16: qcom,sensor-information-16 { - qcom,sensor-type = "adc"; - qcom,sensor-name = "xo_therm"; - }; - sensor_information17: qcom,sensor-information-17 { - qcom,sensor-type = "adc"; - qcom,sensor-name = "pa_therm0"; - }; - sensor_information18: qcom,sensor-information-18 { - qcom,sensor-type = "adc"; - qcom,sensor-name = "pa_therm1"; - }; - sensor_information19: qcom,sensor-information-19 { - qcom,sensor-type = "adc"; - qcom,sensor-name = "quiet_therm"; - }; - sensor_information20: qcom,sensor-information-20 { - qcom,sensor-type = "llm"; - qcom,sensor-name = "limits_sensor-00"; - }; - sensor_information21: qcom,sensor-information-21 { - qcom,sensor-type = "llm"; - qcom,sensor-name = "limits_sensor-01"; - }; - }; - - mitigation_profile0: qcom,limit_info-0 { - qcom,temperature-sensor = <&sensor_information1>; - qcom,hotplug-mitigation-enable; - }; - - mitigation_profile1: qcom,limit_info-1 { - qcom,temperature-sensor = <&sensor_information3>; - qcom,hotplug-mitigation-enable; - }; - - mitigation_profile2: qcom,limit_info-2 { - qcom,temperature-sensor = <&sensor_information4>; - qcom,hotplug-mitigation-enable; - }; - - mitigation_profile3: qcom,limit_info-3 { - qcom,temperature-sensor = <&sensor_information5>; - qcom,hotplug-mitigation-enable; - }; - - mitigation_profile4: qcom,limit_info-4 { - qcom,temperature-sensor = <&sensor_information6>; - qcom,hotplug-mitigation-enable; - }; - - qcom,msm-thermal { - compatible = "qcom,msm-thermal"; - qcom,sensor-id = <1>; - qcom,poll-ms = <100>; - qcom,therm-reset-temp = <115>; - qcom,core-limit-temp = <70>; - qcom,core-temp-hysteresis = <10>; - qcom,hotplug-temp = <105>; - qcom,hotplug-temp-hysteresis = <20>; - qcom,online-hotplug-core; - qcom,synchronous-cluster-id = <0 1>; - qcom,synchronous-cluster-map = <0 4 &CPU0 &CPU1 &CPU2 &CPU3>, - <1 4 &CPU4 &CPU5 &CPU6 &CPU7>; - - qcom,vdd-restriction-temp = <5>; - qcom,vdd-restriction-temp-hysteresis = <10>; - - vdd-dig-supply = <&pm2falcon_s3_floor_level>; - vdd-gfx-supply = <&gfx_vreg_corner>; - - qcom,vdd-dig-rstr{ - qcom,vdd-rstr-reg = "vdd-dig"; - qcom,levels = ; - qcom,min-level = ; - }; - - qcom,vdd-gfx-rstr{ - qcom,vdd-rstr-reg = "vdd-gfx"; - qcom,levels = <5 6 6>; /* Nominal, Turbo, Turbo */ - qcom,min-level = <1>; /* No Request */ - }; - - msm_thermal_freq: qcom,vdd-apps-rstr{ - qcom,vdd-rstr-reg = "vdd-apps"; - qcom,levels = <1248000>; - qcom,freq-req; - }; - }; - - qcom,lmh { - compatible = "qcom,lmh_v1"; - interrupts = ; - }; - - qcom,msm-core@780000 { - compatible = "qcom,apss-core-ea"; - reg = <0x780000 0x1000>; - qcom,low-hyst-temp = <10>; - qcom,high-hyst-temp = <5>; - - ea0: ea0 { - sensor = <&sensor_information1>; - }; - - ea1: ea1 { - sensor = <&sensor_information1>; - }; - - ea2: ea2 { - sensor = <&sensor_information1>; - }; - - ea3: ea3 { - sensor = <&sensor_information1>; - }; - - ea4: ea4 { - sensor = <&sensor_information3>; - }; - - ea5: ea5 { - sensor = <&sensor_information4>; - }; - - ea6: ea6 { - sensor = <&sensor_information5>; - }; - - ea7: ea7 { - sensor = <&sensor_information6>; - }; - }; - - uartblsp2dm1: serial@0c1b0000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0xc1b0000 0x1000>; - interrupts = <0 114 0>; - status = "disabled"; - clocks = <&clock_gcc GCC_BLSP2_UART2_APPS_CLK>, - <&clock_gcc GCC_BLSP2_AHB_CLK>; - clock-names = "core", "iface"; - }; - - slim_aud: slim@151c0000 { - cell-index = <1>; - compatible = "qcom,slim-ngd"; - reg = <0x151c0000 0x2c000>, - <0x15180000 0x2e000>; - reg-names = "slimbus_physical", "slimbus_bam_physical"; - interrupts = <0 163 0>, <0 164 0>; - interrupt-names = "slimbus_irq", "slimbus_bam_irq"; - qcom,apps-ch-pipes = <0x7e0000>; - qcom,ea-pc = <0x260>; - status = "disabled"; - }; - - slim_qca: slim@15240000 { - cell-index = <3>; - compatible = "qcom,slim-ngd"; - reg = <0x15240000 0x2c000>, - <0x15200000 0x24000>; - reg-names = "slimbus_physical", "slimbus_bam_physical"; - interrupts = <0 291 0>, <0 292 0>; - interrupt-names = "slimbus_irq", "slimbus_bam_irq"; - qcom,apps-ch-pipes = <0x1800>; - status = "disabled"; - }; - - timer@17920000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0x17920000 0x1000>; - clock-frequency = <19200000>; - - frame@17921000 { - frame-number = <0>; - interrupts = <0 8 0x4>, - <0 7 0x4>; - reg = <0x17921000 0x1000>, - <0x17922000 0x1000>; - }; - - frame@17923000 { - frame-number = <1>; - interrupts = <0 9 0x4>; - reg = <0x17923000 0x1000>; - status = "disabled"; - }; - - frame@17924000 { - frame-number = <2>; - interrupts = <0 10 0x4>; - reg = <0x17924000 0x1000>; - status = "disabled"; - }; - - frame@17925000 { - frame-number = <3>; - interrupts = <0 11 0x4>; - reg = <0x17925000 0x1000>; - status = "disabled"; - }; - - frame@17926000 { - frame-number = <4>; - interrupts = <0 12 0x4>; - reg = <0x17926000 0x1000>; - status = "disabled"; - }; - - frame@17927000 { - frame-number = <5>; - interrupts = <0 13 0x4>; - reg = <0x17927000 0x1000>; - status = "disabled"; - }; - - frame@17928000 { - frame-number = <6>; - interrupts = <0 14 0x4>; - reg = <0x17928000 0x1000>; - status = "disabled"; - }; - }; - - arm64-cpu-erp { - compatible = "arm,arm64-cpu-erp"; - interrupts = <0 43 4>, - <0 44 4>, - <0 41 4>, - <0 42 4>; - - interrupt-names = "pri-dbe-irq", - "sec-dbe-irq", - "pri-ext-irq", - "sec-ext-irq"; - - poll-delay-ms = <5000>; - }; - - clock_rpmcc: qcom,rpmcc { - compatible = "qcom,rpmcc-msmfalcon", "qcom,rpmcc"; - #clock-cells = <1>; - }; - - clock_gcc: clock-controller@100000 { - compatible = "qcom,gcc-msmfalcon", "syscon"; - reg = <0x100000 0x94000>; - vdd_dig-supply = <&pm2falcon_s3_level>; - vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - clock_mmss: clock-controller@c8c0000 { - compatible = "qcom,mmcc-msmfalcon"; - reg = <0xc8c0000 0x40000>; - vdd_mx_mmss-supply = <&pm2falcon_s5_level>; - vdd_dig_mmss-supply = <&pm2falcon_s3_level>; - vdda-supply = <&pmfalcon_l10>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - clock_gfx: clock-controller@5065000 { - compatible = "qcom,gpucc-msmfalcon"; - reg = <0x5065000 0x10000>; - vdd_dig_gfx-supply = <&pm2falcon_s3_level>; - vdd_mx_gfx-supply = <&pm2falcon_s5_level>; - vdd_gfx-supply = <&gfx_vreg_corner>; - qcom,gfxfreq-corner = - < 0 0>, - < 160000000 1>, /* MinSVS */ - < 266000000 2>, /* LowSVS */ - < 370000000 3>, /* SVS */ - < 465000000 4>, /* SVS_L1 */ - < 588000000 5>, /* NOM */ - < 647000000 6>, /* NOM_L1 */ - < 700000000 7>, /* TURBO */ - < 750000000 7>; /* TURBO */ - #clock-cells = <1>; - #reset-cells = <1>; - }; - - cpu_debug: syscon@1791101c { - compatible = "syscon"; - reg = <0x1791101c 0x4>; - }; - - gpu_debug: syscon@05065120 { - compatible = "syscon"; - reg = <0x05065120 0x4>; - }; - - mmss_debug: syscon@c8c0900 { - compatible = "syscon"; - reg = <0xc8c0900 0x4>; - }; - - clock_debug: qcom,cc-debug@62000 { - compatible = "qcom,gcc-debug-msmfalcon"; - reg = <0x62000 0x4>; - reg-names = "dbg_offset"; - clocks = <&clock_rpmcc RPM_XO_CLK_SRC>; - clock-names = "xo_clk_src"; - qcom,cc-count = <4>; - qcom,gcc = <&clock_gcc>; - qcom,cpu = <&cpu_debug>; - qcom,mmss = <&mmss_debug>; - qcom,gpu = <&gpu_debug>; - #clock-cells = <1>; - }; - - cpubw: qcom,cpubw { - compatible = "qcom,devbw"; - governor = "performance"; - qcom,src-dst-ports = <1 512>; - qcom,active-only; - qcom,bw-tbl = - < 762 /* 100 MHz */ >, - < 1144 /* 150 MHz */ >, - < 1525 /* 200 MHz */ >, - < 2288 /* 300 MHz */ >, - < 3143 /* 412 MHz */ >, - < 4173 /* 547 MHz */ >, - < 5195 /* 681 MHz */ >, - < 5859 /* 768 MHz */ >, - < 7759 /* 1017 MHz */ >, - < 9887 /* 1296 MHz */ >, - < 10327 /* 1353 MHz */ >, - < 11863 /* 1555 MHz */ >, - < 13763 /* 1804 MHz */ >; - }; - - bwmon: qcom,cpu-bwmon { - compatible = "qcom,bimc-bwmon3"; - reg = <0x01008000 0x300>, <0x01001000 0x200>; - reg-names = "base", "global_base"; - interrupts = <0 183 4>; - qcom,mport = <0>; - qcom,target-dev = <&cpubw>; - }; - - mincpubw: qcom,mincpubw { - compatible = "qcom,devbw"; - governor = "powersave"; - qcom,src-dst-ports = <1 512>; - qcom,active-only; - qcom,bw-tbl = - < 762 /* 100 MHz */ >, - < 1144 /* 150 MHz */ >, - < 1525 /* 200 MHz */ >, - < 2288 /* 300 MHz */ >, - < 3143 /* 412 MHz */ >, - < 4173 /* 547 MHz */ >, - < 5195 /* 681 MHz */ >, - < 5859 /* 768 MHz */ >, - < 7759 /* 1017 MHz */ >, - < 9887 /* 1296 MHz */ >, - < 10327 /* 1353 MHz */ >, - < 11863 /* 1555 MHz */ >, - < 13763 /* 1804 MHz */ >; - }; - - memlat_cpu0: qcom,memlat-cpu0 { - compatible = "qcom,devbw"; - governor = "powersave"; - qcom,src-dst-ports = <1 512>; - qcom,active-only; - qcom,bw-tbl = - < 762 /* 100 MHz */ >, - < 1144 /* 150 MHz */ >, - < 1525 /* 200 MHz */ >, - < 2288 /* 300 MHz */ >, - < 3143 /* 412 MHz */ >, - < 4173 /* 547 MHz */ >, - < 5195 /* 681 MHz */ >, - < 5859 /* 768 MHz */ >, - < 7759 /* 1017 MHz */ >, - < 9887 /* 1296 MHz */ >, - < 10327 /* 1353 MHz */ >, - < 11863 /* 1555 MHz */ >, - < 13763 /* 1804 MHz */ >; - }; - - memlat_cpu4: qcom,memlat-cpu4 { - compatible = "qcom,devbw"; - governor = "powersave"; - qcom,src-dst-ports = <1 512>; - qcom,active-only; - qcom,bw-tbl = - < 762 /* 100 MHz */ >, - < 1144 /* 150 MHz */ >, - < 1525 /* 200 MHz */ >, - < 2288 /* 300 MHz */ >, - < 3143 /* 412 MHz */ >, - < 4173 /* 547 MHz */ >, - < 5195 /* 681 MHz */ >, - < 5859 /* 768 MHz */ >, - < 7759 /* 1017 MHz */ >, - < 9887 /* 1296 MHz */ >, - < 10327 /* 1353 MHz */ >, - < 11863 /* 1555 MHz */ >, - < 13763 /* 1804 MHz */ >; - }; - - devfreq_memlat_0: qcom,arm-memlat-mon-0 { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; - qcom,target-dev = <&memlat_cpu0>; - qcom,core-dev-table = - < 633600 1525 >, - < 1401600 4173 >, - < 1881600 7759 >; - }; - - devfreq_memlat_4: qcom,arm-memlat-mon-4 { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; - qcom,target-dev = <&memlat_cpu4>; - qcom,core-dev-table = - < 1113600 1525 >, - < 1401600 7759 >, - < 2150400 11863 >, - < 2457600 13763 >; - }; - - devfreq_cpufreq: devfreq-cpufreq { - mincpubw-cpufreq { - target-dev = <&mincpubw>; - cpu-to-dev-map-0 = - < 633600 1525 >, - < 1401600 3143 >, - < 1881600 5859 >; - cpu-to-dev-map-4 = - < 1113600 1525 >, - < 1401600 4173 >, - < 1747200 5859 >, - < 2150400 7759 >, - < 2457600 13763 >; - }; - }; - - clock_cpu: qcom,clk-cpu-falcon@179c0000 { - compatible = "qcom,clk-cpu-osm"; - status = "disabled"; - reg = <0x179c0000 0x4000>, <0x17916000 0x1000>, - <0x17816000 0x1000>, <0x179d1000 0x1000>, - <0x00784130 0x8>; - reg-names = "osm", "pwrcl_pll", "perfcl_pll", - "apcs_common", "perfcl_efuse"; - - /* ToDo: Add power and perf supply rails */ - - interrupts = , - ; - interrupt-names = "pwrcl-irq", "perfcl-irq"; - - qcom,pwrcl-speedbin0-v0 = - < 300000000 0x0004000f 0x01200020 0x1 1 >, - < 633600000 0x05040021 0x03200020 0x1 1 >, - < 902400000 0x0404002f 0x04260026 0x1 2 >, - < 1113600000 0x0404003a 0x052e002e 0x2 3 >, - < 1401600000 0x04040049 0x073a003a 0x2 4 >, - < 1536000000 0x04040050 0x08400040 0x3 5 >, - < 1747200000 0x0404005b 0x09480048 0x3 6 >, - < 1843200000 0x04040060 0x094c004c 0x3 7 >; - - qcom,perfcl-speedbin0-v0 = - < 300000000 0x0004000f 0x01200020 0x1 1 >, - < 1113600000 0x0404003a 0x052e002e 0x1 1 >, - < 1401600000 0x04040049 0x073a003a 0x2 2 >, - < 1747200000 0x0404005b 0x09480048 0x2 3 >, - < 1958400000 0x04040066 0x0a510051 0x3 4 >, - < 2150400000 0x04040070 0x0b590059 0x3 5 >, - < 2457600000 0x04040080 0x0c660066 0x3 6 >; - - qcom,perfcl-speedbin1-v0 = - < 300000000 0x0004000f 0x01200020 0x1 1 >, - < 1113600000 0x0404003a 0x052e002e 0x1 1 >, - < 1401600000 0x04040049 0x073a003a 0x2 2 >, - < 1747200000 0x0404005b 0x09480048 0x2 3 >, - < 1958400000 0x04040066 0x0a510051 0x3 4 >, - < 2150400000 0x04040070 0x0b590059 0x3 5 >, - < 2208000000 0x04040073 0x0b5c005c 0x3 6 >; - - qcom,up-timer = <1000 1000>; - qcom,down-timer = <1000 1000>; - qcom,pc-override-index = <0 0>; - qcom,set-ret-inactive; - qcom,enable-llm-freq-vote; - qcom,llm-freq-up-timer = <327675 327675>; - qcom,llm-freq-down-timer = <327675 327675>; - qcom,enable-llm-volt-vote; - qcom,llm-volt-up-timer = <327675 327675>; - qcom,llm-volt-down-timer = <327675 327675>; - qcom,cc-reads = <10>; - qcom,cc-delay = <5>; - qcom,cc-factor = <100>; - qcom,osm-clk-rate = <200000000>; - qcom,xo-clk-rate = <19200000>; - - qcom,l-val-base = <0x17916004 0x17816004>; - qcom,apcs-itm-present = <0x179d143c 0x179d143c>; - qcom,apcs-pll-user-ctl = <0x1791600c 0x1781600c>; - qcom,apcs-cfg-rcgr = <0x17911054 0x17811054>; - qcom,apcs-cmd-rcgr = <0x17911050 0x17811050>; - qcom,apm-mode-ctl = <0x179d0004 0x179d0010>; - qcom,apm-ctrl-status = <0x179d000c 0x179d0018>; - - qcom,apm-threshold-voltage = <832000>; - qcom,boost-fsm-en; - qcom,safe-fsm-en; - qcom,ps-fsm-en; - qcom,droop-fsm-en; - qcom,wfx-fsm-en; - qcom,pc-fsm-en; - - qcom,pwrcl-apcs-mem-acc-cfg = - <0x179d1360 0x179d1364 0x179d1364>; - qcom,perfcl-apcs-mem-acc-cfg = - <0x179d1368 0x179d136C 0x179d1370>; - qcom,pwrcl-apcs-mem-acc-val = - <0x00000000 0x80000000 0x80000000>, - <0x00000000 0x00000000 0x00000000>, - <0x00000000 0x00000001 0x00000001>; - qcom,perfcl-apcs-mem-acc-val = - <0x00000000 0x00000000 0x80000000>, - <0x00000000 0x00000000 0x00000000>, - <0x00000000 0x00000000 0x00000001>; - - clock-names = "aux_clk", "xo_a"; - clocks = <&clock_gcc HMSS_GPLL0_CLK_SRC>, - <&clock_rpmcc RPM_XO_A_CLK_SRC>; - - #clock-cells = <1>; - }; - - sdhc_1: sdhci@c0c4000 { - compatible = "qcom,sdhci-msm-v5"; - reg = <0xc0c4000 0x1000>, <0xc0c5000 0x1000>; - reg-names = "hc_mem", "cmdq_mem"; - - interrupts = <0 129 0>, <0 227 0>; - interrupt-names = "hc_irq", "pwr_irq"; - - qcom,bus-width = <8>; - qcom,large-address-bus; - - qcom,devfreq,freq-table = <50000000 200000000>; - - clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>, - <&clock_gcc GCC_SDCC1_APPS_CLK>; - clock-names = "iface_clk", "core_clk"; - - status = "disabled"; - }; - - ipa_hw: qcom,ipa@14780000 { - compatible = "qcom,ipa"; - reg = <0x14780000 0x4effc>, <0x14784000 0x26934>; - reg-names = "ipa-base", "bam-base"; - interrupts = <0 333 0>, - <0 432 0>; - interrupt-names = "ipa-irq", "bam-irq"; - qcom,ipa-hw-ver = <6>; /* IPA core version = IPAv2.6L */ - qcom,ipa-hw-mode = <0>; /* IPA hw type = Normal */ - qcom,wan-rx-ring-size = <192>; /* IPA WAN-rx-ring-size*/ - qcom,lan-rx-ring-size = <192>; /* IPA LAN-rx-ring-size*/ - clocks = <&clock_rpmcc RPM_IPA_CLK>, - <&clock_rpmcc RPM_AGGR2_NOC_CLK>; - clock-names = "core_clk", "smmu_clk"; - qcom,arm-smmu; - qcom,smmu-disable-htw; - qcom,smmu-s1-bypass; - qcom,ee = <0>; - qcom,use-ipa-tethering-bridge; - qcom,modem-cfg-emb-pipe-flt; - qcom,msm-bus,name = "ipa"; - qcom,msm-bus,num-cases = <4>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-KBps = - /* No vote */ - <90 512 0 0>, - <1 676 0 0>, - /* SVS */ - <90 512 80000 640000>, - <1 676 80000 80000>, - /* NOMINAL */ - <90 512 206000 960000>, - <1 676 206000 160000>, - /* TURBO */ - <90 512 206000 960000>, - <1 676 206000 160000>; - qcom,bus-vector-names = "MIN", "SVS", "PERF", "TURBO"; - qcom,rx-polling-sleep-ms = <2>; /* Polling sleep interval */ - qcom,ipa-polling-iteration = <5>; /* Polling Iteration */ - - ipa_smmu_ap: ipa_smmu_ap { - compatible = "qcom,ipa-smmu-ap-cb"; - iommus = <&anoc2_smmu 0x19C0>; - qcom,iova-mapping = <0x10000000 0x40000000>; - }; - - ipa_smmu_wlan: ipa_smmu_wlan { - status = "disabled"; - compatible = "qcom,ipa-smmu-wlan-cb"; - iommus = <&anoc2_smmu 0x19C1>; - }; - - ipa_smmu_uc: ipa_smmu_uc { - compatible = "qcom,ipa-smmu-uc-cb"; - iommus = <&anoc2_smmu 0x19C2>; - qcom,iova-mapping = <0x40000000 0x20000000>; - }; - }; - - qcom,rmtfs_sharedmem@0 { - compatible = "qcom,sharedmem-uio"; - reg = <0x0 0x200000>; - reg-names = "rmtfs"; - qcom,client-id = <0x00000001>; - }; - - qcom,rmnet-ipa { - compatible = "qcom,rmnet-ipa"; - qcom,rmnet-ipa-ssr; - qcom,ipa-loaduC; - qcom,ipa-advertise-sg-support; - }; - - qcom,ipc-spinlock@1f40000 { - compatible = "qcom,ipc-spinlock-sfpb"; - reg = <0x1f40000 0x8000>; - qcom,num-locks = <8>; - }; - - qcom,smem@86000000 { - compatible = "qcom,smem"; - reg = <0x86000000 0x200000>, - <0x17911008 0x4>, - <0x778000 0x7000>, - <0x1fd4000 0x8>; - reg-names = "smem", "irq-reg-base", "aux-mem1", - "smem_targ_info_reg"; - qcom,mpu-enabled; - }; - - - qcom,msm-adsprpc-mem { - compatible = "qcom,msm-adsprpc-mem-region"; - memory-region = <&adsp_mem>; - }; - - qcom,msm_fastrpc { - compatible = "qcom,msm-fastrpc-adsp"; - qcom,fastrpc-glink; - - qcom,msm_fastrpc_compute_cb1 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "adsprpc-smd"; - iommus = <&lpass_q6_smmu 3>; - dma-coherent; - }; - qcom,msm_fastrpc_compute_cb2 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "adsprpc-smd"; - iommus = <&lpass_q6_smmu 7>; - dma-coherent; - }; - qcom,msm_fastrpc_compute_cb3 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "adsprpc-smd"; - iommus = <&lpass_q6_smmu 8>; - dma-coherent; - }; - qcom,msm_fastrpc_compute_cb4 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "adsprpc-smd"; - iommus = <&lpass_q6_smmu 9>; - dma-coherent; - }; - qcom,msm_fastrpc_compute_cb5 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "cdsprpc-smd"; - iommus = <&turing_q6_smmu 3>; - dma-coherent; - }; - qcom,msm_fastrpc_compute_cb6 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "cdsprpc-smd"; - iommus = <&turing_q6_smmu 4>; - dma-coherent; - }; - qcom,msm_fastrpc_compute_cb7 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "cdsprpc-smd"; - iommus = <&turing_q6_smmu 5>; - dma-coherent; - }; - - qcom,msm_fastrpc_compute_cb8 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "cdsprpc-smd"; - iommus = <&turing_q6_smmu 6>; - dma-coherent; - }; - qcom,msm_fastrpc_compute_cb9 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "cdsprpc-smd"; - iommus = <&turing_q6_smmu 7>; - dma-coherent; - }; - qcom,msm_fastrpc_compute_cb10 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "cdsprpc-smd"; - iommus = <&turing_q6_smmu 8>; - dma-coherent; - }; - qcom,msm_fastrpc_compute_cb11 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "cdsprpc-smd"; - iommus = <&turing_q6_smmu 9>; - dma-coherent; - }; - qcom,msm_fastrpc_compute_cb12 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "cdsprpc-smd"; - iommus = <&turing_q6_smmu 10>; - dma-coherent; - }; - qcom,msm_fastrpc_compute_cb13 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "cdsprpc-smd"; - iommus = <&turing_q6_smmu 11>; - dma-coherent; - }; - }; - - - dcc: dcc@10b3000 { - compatible = "qcom,dcc"; - reg = <0x10b3000 0x1000>, - <0x10b4000 0x800>; - reg-names = "dcc-base", "dcc-ram-base"; - - clocks = <&clock_gcc GCC_DCC_AHB_CLK>; - clock-names = "dcc_clk"; - }; - - qcom,glink-smem-native-xprt-modem@86000000 { - compatible = "qcom,glink-smem-native-xprt"; - reg = <0x86000000 0x200000>, - <0x17911008 0x4>; - reg-names = "smem", "irq-reg-base"; - qcom,irq-mask = <0x8000>; - interrupts = <0 452 1>; - label = "mpss"; - }; - - qcom,glink-smem-native-xprt-adsp@86000000 { - compatible = "qcom,glink-smem-native-xprt"; - reg = <0x86000000 0x200000>, - <0x17911008 0x4>; - reg-names = "smem", "irq-reg-base"; - qcom,irq-mask = <0x200>; - interrupts = <0 157 1>; - label = "lpass"; - qcom,qos-config = <&glink_qos_adsp>; - qcom,ramp-time = <0xaf>; - }; - - glink_qos_adsp: qcom,glink-qos-config-adsp { - compatible = "qcom,glink-qos-config"; - qcom,flow-info = <0x3c 0x0>, - <0x3c 0x0>, - <0x3c 0x0>, - <0x3c 0x0>; - qcom,mtu-size = <0x800>; - qcom,tput-stats-cycle = <0xa>; - }; - - qcom,glink-smem-native-xprt-cdsp@86000000 { - compatible = "qcom,glink-smem-native-xprt"; - reg = <0x86000000 0x200000>, - <0x17911008 0x4>; - reg-names = "smem", "irq-reg-base"; - qcom,irq-mask = <0x20000000>; - interrupts = <0 513 1>; - label = "cdsp"; - }; - - qcom,glink-smem-native-xprt-rpm@778000 { - compatible = "qcom,glink-rpm-native-xprt"; - reg = <0x778000 0x7000>, - <0x17911008 0x4>; - reg-names = "msgram", "irq-reg-base"; - qcom,irq-mask = <0x1>; - interrupts = <0 168 1>; - label = "rpm"; - }; - - glink_mpss: qcom,glink-ssr-modem { - compatible = "qcom,glink_ssr"; - label = "modem"; - qcom,edge = "mpss"; - qcom,notify-edges = <&glink_lpass>, <&glink_rpm>, - <&glink_cdsp>; - qcom,xprt = "smem"; - }; - - glink_lpass: qcom,glink-ssr-adsp { - compatible = "qcom,glink_ssr"; - label = "adsp"; - qcom,edge = "lpass"; - qcom,notify-edges = <&glink_mpss>, <&glink_rpm>, - <&glink_cdsp>; - qcom,xprt = "smem"; - }; - - glink_rpm: qcom,glink-ssr-rpm { - compatible = "qcom,glink_ssr"; - label = "rpm"; - qcom,edge = "rpm"; - qcom,notify-edges = <&glink_lpass>, <&glink_mpss>, - <&glink_cdsp>; - qcom,xprt = "smem"; - }; - - glink_cdsp: qcom,glink-ssr-cdsp { - compatible = "qcom,glink_ssr"; - label = "cdsp"; - qcom,edge = "cdsp"; - qcom,notify-edges = <&glink_lpass>, <&glink_mpss>, - <&glink_rpm>; - qcom,xprt = "smem"; - }; - - qcom,glink_pkt { - compatible = "qcom,glinkpkt"; - - qcom,glinkpkt-at-mdm0 { - qcom,glinkpkt-transport = "smem"; - qcom,glinkpkt-edge = "mpss"; - qcom,glinkpkt-ch-name = "DS"; - qcom,glinkpkt-dev-name = "at_mdm0"; - }; - - qcom,glinkpkt-loopback_cntl { - qcom,glinkpkt-transport = "lloop"; - qcom,glinkpkt-edge = "local"; - qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT"; - qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl"; - }; - - qcom,glinkpkt-loopback_data { - qcom,glinkpkt-transport = "lloop"; - qcom,glinkpkt-edge = "local"; - qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT"; - qcom,glinkpkt-dev-name = "glink_pkt_loopback"; - }; - - qcom,glinkpkt-apr-apps2 { - qcom,glinkpkt-transport = "smem"; - qcom,glinkpkt-edge = "adsp"; - qcom,glinkpkt-ch-name = "apr_apps2"; - qcom,glinkpkt-dev-name = "apr_apps2"; - }; - - qcom,glinkpkt-data40-cntl { - qcom,glinkpkt-transport = "smem"; - qcom,glinkpkt-edge = "mpss"; - qcom,glinkpkt-ch-name = "DATA40_CNTL"; - qcom,glinkpkt-dev-name = "smdcntl8"; - }; - - qcom,glinkpkt-data1 { - qcom,glinkpkt-transport = "smem"; - qcom,glinkpkt-edge = "mpss"; - qcom,glinkpkt-ch-name = "DATA1"; - qcom,glinkpkt-dev-name = "smd7"; - }; - - qcom,glinkpkt-data4 { - qcom,glinkpkt-transport = "smem"; - qcom,glinkpkt-edge = "mpss"; - qcom,glinkpkt-ch-name = "DATA4"; - qcom,glinkpkt-dev-name = "smd8"; - }; - - qcom,glinkpkt-data11 { - qcom,glinkpkt-transport = "smem"; - qcom,glinkpkt-edge = "mpss"; - qcom,glinkpkt-ch-name = "DATA11"; - qcom,glinkpkt-dev-name = "smd11"; - }; - }; - - rpm_bus: qcom,rpm-smd { - compatible = "qcom,rpm-glink"; - qcom,glink-edge = "rpm"; - rpm-channel-name = "rpm_requests"; - }; - - qcom,ipc_router { - compatible = "qcom,ipc_router"; - qcom,node-id = <1>; - }; - - qcom,ipc_router_modem_xprt { - compatible = "qcom,ipc_router_glink_xprt"; - qcom,ch-name = "IPCRTR"; - qcom,xprt-remote = "mpss"; - qcom,glink-xprt = "smem"; - qcom,xprt-linkid = <1>; - qcom,xprt-version = <1>; - qcom,fragmented-data; - }; - - qcom,ipc_router_q6_xprt { - compatible = "qcom,ipc_router_glink_xprt"; - qcom,ch-name = "IPCRTR"; - qcom,xprt-remote = "lpass"; - qcom,glink-xprt = "smem"; - qcom,xprt-linkid = <1>; - qcom,xprt-version = <1>; - qcom,fragmented-data; - }; - - qcom,ipc_router_cdsp_xprt { - compatible = "qcom,ipc_router_glink_xprt"; - qcom,ch-name = "IPCRTR"; - qcom,xprt-remote = "cdsp"; - qcom,glink-xprt = "smem"; - qcom,xprt-linkid = <1>; - qcom,xprt-version = <1>; - qcom,fragmented-data; - }; - - qcom,venus@cce0000 { - compatible = "qcom,pil-tz-generic"; - reg = <0xcce0000 0x4000>; - - vdd-supply = <&gdsc_venus>; - qcom,proxy-reg-names = "vdd"; - - clocks = <&clock_mmss MMSS_VIDEO_CORE_CLK>, - <&clock_mmss MMSS_MNOC_AHB_CLK>, - <&clock_mmss MMSS_VIDEO_AHB_CLK>, - <&clock_rpmcc MMSSNOC_AXI_CLK>, - <&clock_mmss MMSS_VIDEO_AXI_CLK>; - clock-names = "core_clk", "mnoc_ahb_clk", "iface_clk", - "noc_axi_clk", "bus_clk"; - qcom,proxy-clock-names = "core_clk", "mnoc_ahb_clk", - "iface_clk", "noc_axi_clk", "bus_clk"; - - qcom,msm-bus,name = "pil-venus"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <63 512 0 0>, - <63 512 0 304000>; - - qcom,pas-id = <9>; - qcom,proxy-timeout-ms = <100>; - qcom,firmware-name = "venus"; - memory-region = <&venus_fw_mem>; - status = "ok"; - }; - - qcom,icnss@18800000 { - status = "disabled"; - compatible = "qcom,icnss"; - reg = <0x18800000 0x800000>, - <0x10ac000 0x20>; - reg-names = "membase", "mpm_config"; - interrupts = <0 413 0>, /* CE0 */ - <0 414 0>, /* CE1 */ - <0 415 0>, /* CE2 */ - <0 416 0>, /* CE3 */ - <0 417 0>, /* CE4 */ - <0 418 0>, /* CE5 */ - <0 420 0>, /* CE6 */ - <0 421 0>, /* CE7 */ - <0 422 0>, /* CE8 */ - <0 423 0>, /* CE9 */ - <0 424 0>, /* CE10 */ - <0 425 0>; /* CE11 */ - qcom,wlan-msa-memory = <0x100000>; - }; - - qcom,lpass@15700000 { - compatible = "qcom,pil-tz-generic"; - reg = <0x15700000 0x00100>; - interrupts = <0 162 1>; - - vdd_cx-supply = <&pm2falcon_l9_level>; - qcom,proxy-reg-names = "vdd_cx"; - qcom,vdd_cx-uV-uA = ; - - clocks = <&clock_rpmcc CXO_PIL_LPASS_CLK>; - clock-names = "xo"; - qcom,proxy-clock-names = "xo"; - - qcom,pas-id = <1>; - qcom,proxy-timeout-ms = <10000>; - qcom,smem-id = <423>; - qcom,sysmon-id = <1>; - qcom,ssctl-instance-id = <0x14>; - qcom,firmware-name = "adsp"; - memory-region = <&adsp_fw_mem>; - - /* GPIO inputs from lpass */ - qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>; - qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>; - qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>; - qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>; - - /* GPIO output to lpass */ - qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>; - status = "ok"; - }; - - qcom,turing@1a300000 { - compatible = "qcom,pil-tz-generic"; - reg = <0x1a300000 0x00100>; - interrupts = <0 518 1>; - - vdd_cx-supply = <&pm2falcon_s3_level>; - qcom,proxy-reg-names = "vdd_cx"; - qcom,vdd_cx-uV-uA = ; - - clocks = <&clock_rpmcc CXO_PIL_CDSP_CLK>; - clock-names = "xo"; - qcom,proxy-clock-names = "xo"; - - qcom,pas-id = <18>; - qcom,proxy-timeout-ms = <10000>; - qcom,smem-id = <601>; - qcom,sysmon-id = <7>; - qcom,ssctl-instance-id = <0x17>; - qcom,firmware-name = "cdsp"; - memory-region = <&cdsp_fw_mem>; - - /* GPIO inputs from turing */ - qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_5_in 0 0>; - qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_5_in 2 0>; - qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_5_in 1 0>; - qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_5_in 3 0>; - - /* GPIO output to turing*/ - qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_5_out 0 0>; - status = "ok"; - }; - - pil_modem: qcom,mss@4080000 { - compatible = "qcom,pil-q6v55-mss"; - reg = <0x4080000 0x100>, - <0x1f63000 0x008>, - <0x1f65000 0x008>, - <0x1f64000 0x008>, - <0x4180000 0x040>, - <0x00179000 0x004>, - <0x01fe5048 0x004>; - reg-names = "qdsp6_base", "halt_q6", "halt_modem", - "halt_nc", "rmb_base", "restart_reg", - "cxip_lm_vote_clear"; - - clocks = <&clock_rpmcc RPM_XO_CLK_SRC>, - <&clock_gcc GCC_MSS_CFG_AHB_CLK>, - <&clock_gcc GCC_BIMC_MSS_Q6_AXI_CLK>, - <&clock_gcc GCC_BOOT_ROM_AHB_CLK>, - <&clock_gcc GPLL0_OUT_MSSCC>, - <&clock_gcc GCC_MSS_SNOC_AXI_CLK>, - <&clock_gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, - <&clock_rpmcc RPM_QDSS_CLK>; - clock-names = "xo", "iface_clk", "bus_clk", - "mem_clk", "gpll0_mss_clk", "snoc_axi_clk", - "mnoc_axi_clk", "qdss_clk"; - qcom,proxy-clock-names = "xo", "qdss_clk"; - qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk", - "gpll0_mss_clk", "snoc_axi_clk", - "mnoc_axi_clk"; - - interrupts = <0 448 1>; - vdd_cx-supply = <&pm2falcon_s3_level>; - vdd_cx-voltage = ; - vdd_mx-supply = <&pm2falcon_s5_level>; - vdd_mx-uV = ; - qcom,firmware-name = "modem"; - qcom,pil-self-auth; - qcom,sysmon-id = <0>; - qcom,ssctl-instance-id = <0x12>; - qcom,qdsp6v62-1-5; - memory-region = <&modem_fw_mem>; - qcom,mem-protect-id = <0xF>; - qcom,cx-ipeak-vote; - - /* GPIO inputs from mss */ - qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; - qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; - qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; - qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>; - qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>; - - /* GPIO output to mss */ - qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; - status = "ok"; - }; - - qcom,msm-rtb { - compatible = "qcom,msm-rtb"; - qcom,rtb-size = <0x100000>; - }; - - qcom,mpm2-sleep-counter@10a3000 { - compatible = "qcom,mpm2-sleep-counter"; - reg = <0x10a3000 0x1000>; - clock-frequency = <32768>; - }; - - qcom,msm-imem@146bf000 { - compatible = "qcom,msm-imem"; - reg = <0x146bf000 0x1000>; - ranges = <0x0 0x146bf000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - mem_dump_table@10 { - compatible = "qcom,msm-imem-mem_dump_table"; - reg = <0x10 8>; - }; - - dload_type@18 { - compatible = "qcom,msm-imem-dload-type"; - reg = <0x18 4>; - }; - - restart_reason@65c { - compatible = "qcom,msm-imem-restart_reason"; - reg = <0x65c 4>; - }; - - boot_stats@6b0 { - compatible = "qcom,msm-imem-boot_stats"; - reg = <0x6b0 32>; - }; - - pil@94c { - compatible = "qcom,msm-imem-pil"; - reg = <0x94c 200>; - }; - - diag_dload@c8 { - compatible = "qcom,msm-imem-diag-dload"; - reg = <0xc8 200>; - }; - }; - - qcom,ghd { - compatible = "qcom,gladiator-hang-detect"; - qcom,threshold-arr = <0x179d141c 0x179d1420 - 0x179d1424 0x179d1428 - 0x179d142c 0x179d1430>; - qcom,config-reg = <0x179d1434>; - }; - - qcom,msm-gladiator-v2@17900000 { - compatible = "qcom,msm-gladiator-v2"; - reg = <0x17900000 0xe000>; - reg-names = "gladiator_base"; - interrupts = <0 22 0>; - clock-names = "atb_clk"; - clocks = <&clock_rpmcc RPM_QDSS_CLK>; - }; - - cpu_pmu: cpu-pmu { - compatible = "arm,armv8-pmuv3"; - qcom,irq-is-percpu; - interrupts = <1 6 4>; - }; - - qcom_seecom: qseecom@86d00000 { - compatible = "qcom,qseecom"; - reg = <0x86d00000 0x2200000>; - reg-names = "secapp-region"; - qcom,hlos-num-ce-hw-instances = <1>; - qcom,hlos-ce-hw-instance = <0>; - qcom,qsee-ce-hw-instance = <0>; - qcom,disk-encrypt-pipe-pair = <2>; - qcom,support-fde; - qcom,no-clock-support; - qcom,msm-bus,name = "qseecom-noc"; - qcom,msm-bus,num-cases = <4>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <55 512 0 0>, - <55 512 200000 400000>, - <55 512 300000 800000>, - <55 512 400000 1000000>; - clock-names = "core_clk_src", "core_clk", - "iface_clk", "bus_clk"; - clocks = <&clock_rpmcc QSEECOM_CE1_CLK>, - <&clock_rpmcc QSEECOM_CE1_CLK>, - <&clock_rpmcc QSEECOM_CE1_CLK>, - <&clock_rpmcc QSEECOM_CE1_CLK>; - qcom,ce-opp-freq = <171430000>; - qcom,qsee-reentrancy-support = <2>; - }; - - qcom_cedev: qcedev@1de0000{ - compatible = "qcom,qcedev"; - reg = <0x1de0000 0x20000>, - <0x1dc4000 0x24000>; - reg-names = "crypto-base","crypto-bam-base"; - interrupts = <0 207 0>; - qcom,bam-pipe-pair = <1>; - qcom,ce-hw-instance = <0>; - qcom,ce-device = <0>; - qcom,ce-hw-shared; - qcom,bam-ee = <0>; - qcom,msm-bus,name = "qcedev-noc"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <55 512 0 0>, - <55 512 393600 393600>; - clock-names = "core_clk_src", "core_clk", - "iface_clk", "bus_clk"; - clocks = <&clock_rpmcc QCEDEV_CE1_CLK>, - <&clock_rpmcc QCEDEV_CE1_CLK>, - <&clock_rpmcc QCEDEV_CE1_CLK>, - <&clock_rpmcc QCEDEV_CE1_CLK>; - qcom,ce-opp-freq = <171430000>; - }; - - qcom_crypto: qcrypto@1de0000 { - compatible = "qcom,qcrypto"; - reg = <0x1de0000 0x20000>, - <0x1dc4000 0x24000>; - reg-names = "crypto-base","crypto-bam-base"; - interrupts = <0 207 0>; - qcom,bam-pipe-pair = <2>; - qcom,ce-hw-instance = <0>; - qcom,ce-device = <0>; - qcom,bam-ee = <0>; - qcom,ce-hw-shared; - qcom,clk-mgmt-sus-res; - qcom,msm-bus,name = "qcrypto-noc"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <55 512 0 0>, - <55 512 393600 393600>; - clock-names = "core_clk_src", "core_clk", - "iface_clk", "bus_clk"; - clocks = <&clock_rpmcc QCRYPTO_CE1_CLK>, - <&clock_rpmcc QCRYPTO_CE1_CLK>, - <&clock_rpmcc QCRYPTO_CE1_CLK>, - <&clock_rpmcc QCRYPTO_CE1_CLK>; - qcom,ce-opp-freq = <171430000>; - qcom,use-sw-aes-cbc-ecb-ctr-algo; - qcom,use-sw-aes-xts-algo; - qcom,use-sw-aes-ccm-algo; - qcom,use-sw-ahash-algo; - qcom,use-sw-aead-algo; - qcom,use-sw-hmac-algo; - }; - - qcom_tzlog: tz-log@146bf720 { - compatible = "qcom,tz-log"; - reg = <0x146bf720 0x3000>; - qcom,hyplog-enabled; - hyplog-address-offset = <0x410>; - hyplog-size-offset = <0x414>; - }; - - qcom_rng: qrng@794000 { - compatible = "qcom,msm-rng"; - reg = <0x794000 0x1000>; - qcom,msm-rng-iface-clk; - qcom,no-qrng-config; - qcom,msm-bus,name = "msm-rng-noc"; - qcom,msm-bus,num-cases = <2>; - qcom,msm-bus,num-paths = <1>; - qcom,msm-bus,vectors-KBps = - <1 618 0 0>, /* No vote */ - <1 618 0 800>; /* 100 KHz */ - clocks = <&clock_gcc GCC_PRNG_AHB_CLK>; - clock-names = "iface_clk"; - }; - - qcom,chd_silver { - compatible = "qcom,core-hang-detect"; - label = "silver"; - qcom,threshold-arr = <0x179880b0 0x179980b0 - 0x179a80b0 0x179b80b0>; - qcom,config-arr = <0x179880b8 0x179980b8 - 0x179a80b8 0x179b80b8>; - }; - - qcom,chd_gold { - compatible = "qcom,core-hang-detect"; - label = "gold"; - qcom,threshold-arr = <0x178880b0 0x178980b0 - 0x178a80b0 0x178b80b0>; - qcom,config-arr = <0x178880b8 0x178980b8 - 0x178a80b8 0x178b80b8>; - }; - - ufsphy1: ufsphy@1da7000 { - compatible = "qcom,ufs-phy-qmp-v3-falcon"; - reg = <0x1da7000 0xdb8>; - reg-names = "phy_mem"; - #phy-cells = <0>; - clock-names = "ref_clk_src", - "ref_clk", - "ref_aux_clk"; - clocks = <&clock_rpmcc RPM_LN_BB_CLK1>, - <&clock_gcc GCC_UFS_CLKREF_CLK>, - <&clock_gcc GCC_UFS_PHY_AUX_CLK>; - status = "disabled"; - }; - - ufs1: ufshc@1da4000 { - compatible = "qcom,ufshc"; - reg = <0x1da4000 0x3000>; - interrupts = <0 265 0>; - phys = <&ufsphy1>; - phy-names = "ufsphy"; - - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "core_clk_ice", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk"; - clocks = - <&clock_gcc GCC_UFS_AXI_CLK>, - <&clock_gcc GCC_AGGRE2_UFS_AXI_CLK>, - <&clock_gcc GCC_UFS_AHB_CLK>, - <&clock_gcc GCC_UFS_UNIPRO_CORE_CLK>, - <&clock_gcc GCC_UFS_ICE_CORE_CLK>, - <&clock_rpmcc RPM_LN_BB_CLK1>, - <&clock_gcc GCC_UFS_TX_SYMBOL_0_CLK>, - <&clock_gcc GCC_UFS_RX_SYMBOL_0_CLK>; - freq-table-hz = - <50000000 200000000>, - <0 0>, - <0 0>, - <37500000 150000000>, - <75000000 300000000>, - <0 0>, - <0 0>, - <0 0>; - - lanes-per-direction = <1>; - - qcom,msm-bus,name = "ufs1"; - qcom,msm-bus,num-cases = <12>; - qcom,msm-bus,num-paths = <2>; - qcom,msm-bus,vectors-KBps = - <95 512 0 0>, <1 650 0 0>, /* No vote */ - <95 512 922 0>, <1 650 1000 0>, /* PWM G1 */ - <95 512 1844 0>, <1 650 1000 0>, /* PWM G2 */ - <95 512 3688 0>, <1 650 1000 0>, /* PWM G3 */ - <95 512 7376 0>, <1 650 1000 0>, /* PWM G4 */ - <95 512 127796 0>, <1 650 1000 0>, /* HS G1 RA */ - <95 512 255591 0>, <1 650 1000 0>, /* HS G2 RA */ - <95 512 2097152 0>, <1 650 102400 0>, /* HS G3 RA */ - <95 512 149422 0>, <1 650 1000 0>, /* HS G1 RB */ - <95 512 298189 0>, <1 650 1000 0>, /* HS G2 RB */ - <95 512 2097152 0>, <1 650 102400 0>, /* HS G3 RB */ - <95 512 7643136 0>, <1 650 307200 0>; /* Max. bandwidth */ - qcom,bus-vector-names = "MIN", - "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", - "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", - "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", - "MAX"; - - resets = <&clock_gcc GCC_UFS_BCR>; - reset-names = "core_reset"; - - status = "disabled"; - }; - - jtag_fuse: jtagfuse@786040 { - compatible = "qcom,jtag-fuse-v4"; - reg = <0x786040 0x8>; - reg-names = "fuse-base"; - }; - - jtag_mm0: jtagmm@7840000 { - compatible = "qcom,jtagv8-mm"; - reg = <0x7840000 0x1000>; - reg-names = "etm-base"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - qcom,coresight-jtagmm-cpu = <&CPU0>; - }; - - jtag_mm1: jtagmm@7940000 { - compatible = "qcom,jtagv8-mm"; - reg = <0x7940000 0x1000>; - reg-names = "etm-base"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - qcom,coresight-jtagmm-cpu = <&CPU1>; - }; - - jtag_mm2: jtagmm@7a40000 { - compatible = "qcom,jtagv8-mm"; - reg = <0x7a40000 0x1000>; - reg-names = "etm-base"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - qcom,coresight-jtagmm-cpu = <&CPU2>; - }; - - jtag_mm3: jtagmm@7b40000 { - compatible = "qcom,jtagv8-mm"; - reg = <0x7b40000 0x1000>; - reg-names = "etm-base"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - qcom,coresight-jtagmm-cpu = <&CPU3>; - }; - - jtag_mm4: jtagmm@7c40000 { - compatible = "qcom,jtagv8-mm"; - reg = <0x7c40000 0x1000>; - reg-names = "etm-base"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - qcom,coresight-jtagmm-cpu = <&CPU0>; - }; - - jtag_mm5: jtagmm@7d40000 { - compatible = "qcom,jtagv8-mm"; - reg = <0x7d40000 0x1000>; - reg-names = "etm-base"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - qcom,coresight-jtagmm-cpu = <&CPU1>; - }; - - jtag_mm6: jtagmm@7e40000 { - compatible = "qcom,jtagv8-mm"; - reg = <0x7e40000 0x1000>; - reg-names = "etm-base"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - qcom,coresight-jtagmm-cpu = <&CPU2>; - }; - - jtag_mm7: jtagmm@7f40000 { - compatible = "qcom,jtagv8-mm"; - reg = <0x7f40000 0x1000>; - reg-names = "etm-base"; - - clocks = <&clock_rpmcc RPM_QDSS_CLK>, - <&clock_rpmcc RPM_QDSS_A_CLK>; - clock-names = "core_clk", "core_a_clk"; - - qcom,coresight-jtagmm-cpu = <&CPU3>; - }; -}; - -#include "msmfalcon-ion.dtsi" -#include "msmfalcon-bus.dtsi" -#include "msm-pmfalcon.dtsi" -#include "msm-pm2falcon.dtsi" -#include "msm-pmfalcon-rpm-regulator.dtsi" -#include "msm-pm2falcon-rpm-regulator.dtsi" -#include "msmfalcon-regulator.dtsi" -#include "msm-gdsc-falcon.dtsi" -#include "msmfalcon-gpu.dtsi" -#include "msmfalcon-pm.dtsi" -#include "msm-audio.dtsi" -#include "msmfalcon-audio.dtsi" - -&gdsc_usb30 { - status = "ok"; -}; - -&gdsc_ufs { - status = "ok"; -}; - -&gdsc_bimc_smmu { - clock-names = "bus_clk"; - clocks = <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>; - proxy-supply = <&gdsc_bimc_smmu>; - qcom,proxy-consumer-enable; - status = "ok"; -}; - -&gdsc_hlos1_vote_lpass_adsp { - status = "ok"; -}; - -&gdsc_hlos1_vote_turing_adsp { - status = "ok"; -}; - -&gdsc_hlos2_vote_turing_adsp { - status = "ok"; -}; - -&gdsc_venus { - status = "ok"; -}; - -&gdsc_venus_core0 { - qcom,support-hw-trigger; - status = "ok"; -}; - -&gdsc_camss_top { - status = "ok"; -}; - -&gdsc_vfe0 { - parent-supply = <&gdsc_camss_top>; - status = "ok"; -}; - -&gdsc_vfe1 { - parent-supply = <&gdsc_camss_top>; - status = "ok"; -}; - -&gdsc_cpp { - parent-supply = <&gdsc_camss_top>; - status = "ok"; -}; - -&gdsc_mdss { - proxy-supply = <&gdsc_mdss>; - qcom,proxy-consumer-enable; - status = "ok"; -}; - -&gdsc_gpu_gx { - clock-names = "core_root_clk"; - clocks = <&clock_gfx GFX3D_CLK_SRC>; - qcom,force-enable-root-clk; - parent-supply = <&gfx_vreg_corner>; - status = "ok"; -}; - -&gdsc_gpu_cx { - status = "ok"; -}; - -#include "msm-arm-smmu-falcon.dtsi" -#include "msm-arm-smmu-impl-defs-falcon.dtsi" -#include "msmfalcon-common.dtsi" -#include "msmfalcon-blsp.dtsi" -#include "msmfalcon-camera.dtsi" -#include "msmfalcon-vidc.dtsi" - -&pm2falcon_gpios { - /* GPIO 7 for VOL_UP */ - gpio@c600 { - status = "okay"; - qcom,mode = <0>; - qcom,pull = <0>; - qcom,vin-sel = <0>; - qcom,src-sel = <0>; - qcom,out-strength = <1>; - }; -}; - -&soc { - gpio_keys { - status = "okay"; - compatible = "gpio-keys"; - input-name = "gpio-keys"; - pinctrl-names = "tlmm_gpio_key_active","tlmm_gpio_key_suspend"; - pinctrl-0 = <&gpio_key_active>; - pinctrl-1 = <&gpio_key_suspend>; - - camera_focus { - label = "camera_focus"; - gpios = <&tlmm 64 0x1>; - linux,input-type = <1>; - linux,code = <0x210>; - debounce-interval = <15>; - }; - - camera_snapshot { - label = "camera_snapshot"; - gpios = <&tlmm 113 0x1>; - linux,input-type = <1>; - linux,code = <0x2fe>; - debounce-interval = <15>; - }; - - vol_up { - label = "volume_up"; - gpios = <&pm2falcon_gpios 7 0x1>; - linux,input-type = <1>; - linux,code = <115>; - gpio-key,wakeup; - debounce-interval = <15>; - }; - }; -}; - -#include "msmfalcon-mdss.dtsi" -#include "msmfalcon-mdss-pll.dtsi" diff --git a/arch/arm/boot/dts/qcom/msmtriton-coresight.dtsi b/arch/arm/boot/dts/qcom/msmtriton-coresight.dtsi index 796235ffd1be..e035cf85b9df 100644 --- a/arch/arm/boot/dts/qcom/msmtriton-coresight.dtsi +++ b/arch/arm/boot/dts/qcom/msmtriton-coresight.dtsi @@ -10,7 +10,7 @@ * GNU General Public License for more details. */ -#include "msmfalcon-coresight.dtsi" +#include "sdm660-coresight.dtsi" &etm0 { cpu = <&CPU4>; diff --git a/arch/arm/boot/dts/qcom/msmtriton-regulator.dtsi b/arch/arm/boot/dts/qcom/msmtriton-regulator.dtsi index 2201a04cfbc1..73735159101d 100644 --- a/arch/arm/boot/dts/qcom/msmtriton-regulator.dtsi +++ b/arch/arm/boot/dts/qcom/msmtriton-regulator.dtsi @@ -13,7 +13,7 @@ &rpm_bus { rpm-regulator-smpa4 { status = "okay"; - pmfalcon_s4: regulator-s4 { + pm660_s4: regulator-s4 { regulator-min-microvolt = <1805000>; regulator-max-microvolt = <2040000>; status = "okay"; @@ -22,7 +22,7 @@ rpm-regulator-smpa5 { status = "okay"; - pmfalcon_s5: regulator-s5 { + pm660_s5: regulator-s5 { regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; status = "okay"; @@ -31,7 +31,7 @@ rpm-regulator-smpa6 { status = "okay"; - pmfalcon_s6: regulator-s6 { + pm660_s6: regulator-s6 { regulator-min-microvolt = <504000>; regulator-max-microvolt = <992000>; status = "okay"; @@ -40,7 +40,7 @@ rpm-regulator-smpb1 { status = "okay"; - pm2falcon_s1: regulator-s1 { + pm660l_s1: regulator-s1 { regulator-min-microvolt = <1125000>; regulator-max-microvolt = <1125000>; status = "okay"; @@ -49,19 +49,19 @@ rpm-regulator-smpb2 { status = "okay"; - pm2falcon_s2: regulator-s2 { + pm660l_s2: regulator-s2 { regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; status = "okay"; }; }; - /* PM2FALCON S3 + S4 - VDD_CX supply */ + /* PM660L S3 + S4 - VDD_CX supply */ rpm-regulator-smpb3 { status = "okay"; - pm2falcon_s3_level: regulator-s3-level { + pm660l_s3_level: regulator-s3-level { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s3_level"; + regulator-name = "pm660l_s3_level"; qcom,set = <3>; regulator-min-microvolt = ; @@ -70,9 +70,9 @@ qcom,use-voltage-level; }; - pm2falcon_s3_floor_level: regulator-s3-floor-level { + pm660l_s3_floor_level: regulator-s3-floor-level { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s3_floor_level"; + regulator-name = "pm660l_s3_floor_level"; qcom,set = <3>; regulator-min-microvolt = ; @@ -82,9 +82,9 @@ qcom,always-send-voltage; }; - pm2falcon_s3_level_ao: regulator-s3-level-ao { + pm660l_s3_level_ao: regulator-s3-level-ao { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s3_level_ao"; + regulator-name = "pm660l_s3_level_ao"; qcom,set = <1>; regulator-min-microvolt = ; @@ -94,12 +94,12 @@ }; }; - /* PM2FALCON S5 - VDD_MX supply */ + /* PM660L S5 - VDD_MX supply */ rpm-regulator-smpb5 { status = "okay"; - pm2falcon_s5_level: regulator-s5-level { + pm660l_s5_level: regulator-s5-level { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s5_level"; + regulator-name = "pm660l_s5_level"; qcom,set = <3>; regulator-min-microvolt = ; @@ -108,9 +108,9 @@ qcom,use-voltage-level; }; - pm2falcon_s5_floor_level: regulator-s5-floor-level { + pm660l_s5_floor_level: regulator-s5-floor-level { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s5_floor_level"; + regulator-name = "pm660l_s5_floor_level"; qcom,set = <3>; regulator-min-microvolt = ; @@ -120,9 +120,9 @@ qcom,always-send-voltage; }; - pm2falcon_s5_level_ao: regulator-s5-level-ao { + pm660l_s5_level_ao: regulator-s5-level-ao { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s5_level_ao"; + regulator-name = "pm660l_s5_level_ao"; qcom,set = <1>; regulator-min-microvolt = ; @@ -134,7 +134,7 @@ rpm-regulator-ldoa1 { status = "okay"; - pmfalcon_l1: regulator-l1 { + pm660_l1: regulator-l1 { regulator-min-microvolt = <1150000>; regulator-max-microvolt = <1250000>; status = "okay"; @@ -143,7 +143,7 @@ rpm-regulator-ldoa2 { status = "okay"; - pmfalcon_l2: regulator-l2 { + pm660_l2: regulator-l2 { regulator-min-microvolt = <950000>; regulator-max-microvolt = <1010000>; status = "okay"; @@ -152,7 +152,7 @@ rpm-regulator-ldoa3 { status = "okay"; - pmfalcon_l3: regulator-l3 { + pm660_l3: regulator-l3 { regulator-min-microvolt = <950000>; regulator-max-microvolt = <1010000>; status = "okay"; @@ -161,7 +161,7 @@ rpm-regulator-ldoa5 { status = "okay"; - pmfalcon_l5: regulator-l5 { + pm660_l5: regulator-l5 { regulator-min-microvolt = <525000>; regulator-max-microvolt = <950000>; status = "okay"; @@ -170,15 +170,15 @@ rpm-regulator-ldoa6 { status = "okay"; - pmfalcon_l6: regulator-l6 { + pm660_l6: regulator-l6 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1370000>; status = "okay"; }; - pmfalcon_l6_pin_ctrl: regulator-l6-pin-ctrl { + pm660_l6_pin_ctrl: regulator-l6-pin-ctrl { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l6_pin_ctrl"; + regulator-name = "pm660_l6_pin_ctrl"; qcom,set = <3>; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1370000>; @@ -191,7 +191,7 @@ rpm-regulator-ldoa7 { status = "okay"; - pmfalcon_l7: regulator-l7 { + pm660_l7: regulator-l7 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; status = "okay"; @@ -200,7 +200,7 @@ rpm-regulator-ldoa8 { status = "okay"; - pmfalcon_l8: regulator-l8 { + pm660_l8: regulator-l8 { regulator-min-microvolt = <1750000>; regulator-max-microvolt = <1900000>; status = "okay"; @@ -209,15 +209,15 @@ rpm-regulator-ldoa9 { status = "okay"; - pmfalcon_l9: regulator-l9 { + pm660_l9: regulator-l9 { regulator-min-microvolt = <1750000>; regulator-max-microvolt = <1900000>; status = "okay"; }; - pmfalcon_l9_pin_ctrl: regulator-l9-pin-ctrl { + pm660_l9_pin_ctrl: regulator-l9-pin-ctrl { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l9_pin_ctrl"; + regulator-name = "pm660_l9_pin_ctrl"; qcom,set = <3>; regulator-min-microvolt = <1750000>; regulator-max-microvolt = <1900000>; @@ -230,7 +230,7 @@ rpm-regulator-ldoa10 { status = "okay"; - pmfalcon_l10: regulator-l10 { + pm660_l10: regulator-l10 { regulator-min-microvolt = <1780000>; regulator-max-microvolt = <1950000>; status = "okay"; @@ -239,7 +239,7 @@ rpm-regulator-ldoa11 { status = "okay"; - pmfalcon_l11: regulator-l11 { + pm660_l11: regulator-l11 { regulator-min-microvolt = <1780000>; regulator-max-microvolt = <1950000>; status = "okay"; @@ -248,7 +248,7 @@ rpm-regulator-ldoa12 { status = "okay"; - pmfalcon_l12: regulator-l12 { + pm660_l12: regulator-l12 { regulator-min-microvolt = <1780000>; regulator-max-microvolt = <1950000>; status = "okay"; @@ -257,7 +257,7 @@ rpm-regulator-ldoa13 { status = "okay"; - pmfalcon_l13: regulator-l13 { + pm660_l13: regulator-l13 { regulator-min-microvolt = <1780000>; regulator-max-microvolt = <1950000>; status = "okay"; @@ -266,7 +266,7 @@ rpm-regulator-ldoa14 { status = "okay"; - pmfalcon_l14: regulator-l14 { + pm660_l14: regulator-l14 { regulator-min-microvolt = <1710000>; regulator-max-microvolt = <1900000>; status = "okay"; @@ -275,7 +275,7 @@ rpm-regulator-ldoa15 { status = "okay"; - pmfalcon_l15: regulator-l15 { + pm660_l15: regulator-l15 { regulator-min-microvolt = <1650000>; regulator-max-microvolt = <2950000>; status = "okay"; @@ -284,7 +284,7 @@ rpm-regulator-ldoa17 { status = "okay"; - pmfalcon_l17: regulator-l17 { + pm660_l17: regulator-l17 { regulator-min-microvolt = <1650000>; regulator-max-microvolt = <2950000>; status = "okay"; @@ -293,15 +293,15 @@ rpm-regulator-ldoa19 { status = "okay"; - pmfalcon_l19: regulator-l19 { + pm660_l19: regulator-l19 { regulator-min-microvolt = <3200000>; regulator-max-microvolt = <3400000>; status = "okay"; }; - pmfalcon_l19_pin_ctrl: regulator-l19-pin-ctrl { + pm660_l19_pin_ctrl: regulator-l19-pin-ctrl { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l19_pin_ctrl"; + regulator-name = "pm660_l19_pin_ctrl"; qcom,set = <3>; regulator-min-microvolt = <3200000>; regulator-max-microvolt = <3400000>; @@ -314,7 +314,7 @@ rpm-regulator-ldob1 { status = "okay"; - pm2falcon_l1: regulator-l1 { + pm660l_l1: regulator-l1 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <925000>; status = "okay"; @@ -323,7 +323,7 @@ rpm-regulator-ldob2 { status = "okay"; - pm2falcon_l2: regulator-l2 { + pm660l_l2: regulator-l2 { regulator-min-microvolt = <350000>; regulator-max-microvolt = <3100000>; status = "okay"; @@ -332,7 +332,7 @@ rpm-regulator-ldob3 { status = "okay"; - pm2falcon_l3: regulator-l3 { + pm660l_l3: regulator-l3 { regulator-min-microvolt = <1710000>; regulator-max-microvolt = <3600000>; status = "okay"; @@ -341,7 +341,7 @@ rpm-regulator-ldob4 { status = "okay"; - pm2falcon_l4: regulator-l4 { + pm660l_l4: regulator-l4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2950000>; status = "okay"; @@ -350,7 +350,7 @@ rpm-regulator-ldob5 { status = "okay"; - pm2falcon_l5: regulator-l5 { + pm660l_l5: regulator-l5 { regulator-min-microvolt = <1721000>; regulator-max-microvolt = <3600000>; status = "okay"; @@ -359,7 +359,7 @@ rpm-regulator-ldob6 { status = "okay"; - pm2falcon_l6: regulator-l6 { + pm660l_l6: regulator-l6 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <3300000>; status = "okay"; @@ -368,7 +368,7 @@ rpm-regulator-ldob7 { status = "okay"; - pm2falcon_l7: regulator-l7 { + pm660l_l7: regulator-l7 { regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3125000>; status = "okay"; @@ -377,19 +377,19 @@ rpm-regulator-ldob8 { status = "okay"; - pm2falcon_l8: regulator-l8 { + pm660l_l8: regulator-l8 { regulator-min-microvolt = <3200000>; regulator-max-microvolt = <3400000>; status = "okay"; }; }; - /* PM2FALCON L9 = VDD_SSC_CX supply */ + /* PM660L L9 = VDD_SSC_CX supply */ rpm-regulator-ldob9 { status = "okay"; - pm2falcon_l9_level: regulator-l9-level { + pm660l_l9_level: regulator-l9-level { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l9_level"; + regulator-name = "pm660l_l9_level"; qcom,set = <3>; regulator-min-microvolt = ; @@ -398,9 +398,9 @@ qcom,use-voltage-level; }; - pm2falcon_l9_floor_level: regulator-l9-floor-level { + pm660l_l9_floor_level: regulator-l9-floor-level { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l9_floor_level"; + regulator-name = "pm660l_l9_floor_level"; qcom,set = <3>; regulator-min-microvolt = ; @@ -411,12 +411,12 @@ }; }; - /* PM2FALCON L10 = VDD_SSC_MX supply */ + /* PM660L L10 = VDD_SSC_MX supply */ rpm-regulator-ldob10 { status = "okay"; - pm2falcon_l10_level: regulator-l10-level { + pm660l_l10_level: regulator-l10-level { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l10_level"; + regulator-name = "pm660l_l10_level"; qcom,set = <3>; regulator-min-microvolt = ; @@ -425,9 +425,9 @@ qcom,use-voltage-level; }; - pm2falcon_l10_floor_level: regulator-l10-floor-level { + pm660l_l10_floor_level: regulator-l10-floor-level { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l10_floor_level"; + regulator-name = "pm660l_l10_floor_level"; qcom,set = <3>; regulator-min-microvolt = ; @@ -440,33 +440,33 @@ rpm-regulator-bobb { status = "okay"; - pm2falcon_bob: regulator-bob { + pm660l_bob: regulator-bob { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3600000>; status = "okay"; }; - pm2falcon_bob_pin1: regulator-bob-pin1 { + pm660l_bob_pin1: regulator-bob-pin1 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_bob_pin1"; + regulator-name = "pm660l_bob_pin1"; qcom,set = <3>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3600000>; qcom,use-pin-ctrl-voltage1; }; - pm2falcon_bob_pin2: regulator-bob-pin2 { + pm660l_bob_pin2: regulator-bob-pin2 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_bob_pin2"; + regulator-name = "pm660l_bob_pin2"; qcom,set = <3>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3600000>; qcom,use-pin-ctrl-voltage2; }; - pm2falcon_bob_pin3: regulator-bob-pin3 { + pm660l_bob_pin3: regulator-bob-pin3 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_bob_pin3"; + regulator-name = "pm660l_bob_pin3"; qcom,set = <3>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3600000>; @@ -475,7 +475,7 @@ }; }; -&pmfalcon_charger { +&pm660_charger { smb2_vbus: qcom,smb2-vbus { regulator-name = "smb2-vbus"; }; diff --git a/arch/arm/boot/dts/qcom/msmtriton-rumi.dts b/arch/arm/boot/dts/qcom/msmtriton-rumi.dts index a27ee2ac1ed5..797ba087d76c 100644 --- a/arch/arm/boot/dts/qcom/msmtriton-rumi.dts +++ b/arch/arm/boot/dts/qcom/msmtriton-rumi.dts @@ -14,7 +14,7 @@ /dts-v1/; #include "msmtriton.dtsi" -#include "msmfalcon-pinctrl.dtsi" +#include "sdm660-pinctrl.dtsi" / { model = "Qualcomm Technologies, Inc. MSM TRITON RUMI"; diff --git a/arch/arm/boot/dts/qcom/msmtriton.dtsi b/arch/arm/boot/dts/qcom/msmtriton.dtsi index 4ef236d52911..0cea3cb973da 100644 --- a/arch/arm/boot/dts/qcom/msmtriton.dtsi +++ b/arch/arm/boot/dts/qcom/msmtriton.dtsi @@ -11,9 +11,9 @@ */ #include "skeleton64.dtsi" -#include -#include -#include +#include +#include +#include #include #include #include @@ -523,7 +523,7 @@ }; sensor_information12: qcom,sensor-information-12 { qcom,sensor-type = "alarm"; - qcom,sensor-name = "pmfalcon_tz"; + qcom,sensor-name = "pm660_tz"; qcom,scaling-factor = <1000>; }; sensor_information13: qcom,sensor-information-13 { @@ -598,7 +598,7 @@ qcom,vdd-restriction-temp = <5>; qcom,vdd-restriction-temp-hysteresis = <10>; - vdd-dig-supply = <&pm2falcon_s3_floor_level>; + vdd-dig-supply = <&pm660l_s3_floor_level>; vdd-gfx-supply = <&gfx_vreg_corner>; qcom,vdd-dig-rstr{ @@ -734,25 +734,25 @@ }; clock_rpmcc: qcom,rpmcc { - compatible = "qcom,rpmcc-msmfalcon", "qcom,rpmcc"; + compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; #clock-cells = <1>; }; clock_gcc: clock-controller@100000 { - compatible = "qcom,gcc-msmfalcon", "syscon"; + compatible = "qcom,gcc-sdm660", "syscon"; reg = <0x100000 0x94000>; - vdd_dig-supply = <&pm2falcon_s3_level>; - vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>; + vdd_dig-supply = <&pm660l_s3_level>; + vdd_dig_ao-supply = <&pm660l_s3_level_ao>; #clock-cells = <1>; #reset-cells = <1>; }; clock_mmss: clock-controller@c8c0000 { - compatible = "qcom,mmcc-msmfalcon"; + compatible = "qcom,mmcc-sdm660"; reg = <0xc8c0000 0x40000>; - vdd_mx_mmss-supply = <&pm2falcon_s5_level>; - vdd_dig_mmss-supply = <&pm2falcon_s3_level>; - vdda-supply = <&pmfalcon_l10>; + vdd_mx_mmss-supply = <&pm660l_s5_level>; + vdd_dig_mmss-supply = <&pm660l_s3_level>; + vdda-supply = <&pm660_l10>; #clock-cells = <1>; #reset-cells = <1>; }; @@ -760,8 +760,8 @@ clock_gfx: clock-controller@5065000 { compatible = "qcom,gpucc-msmtriton"; reg = <0x5065000 0x10000>; - vdd_dig_gfx-supply = <&pm2falcon_s3_level>; - vdd_mx_gfx-supply = <&pm2falcon_s5_level>; + vdd_dig_gfx-supply = <&pm660l_s3_level>; + vdd_mx_gfx-supply = <&pm660l_s5_level>; vdd_gfx-supply = <&gfx_vreg_corner>; qcom,gfxfreq-corner = < 0 0>, @@ -793,7 +793,7 @@ }; clock_debug: qcom,cc-debug@62000 { - compatible = "qcom,gcc-debug-msmfalcon"; + compatible = "qcom,gcc-debug-sdm660"; reg = <0x62000 0x4>; reg-names = "dbg_offset"; clocks = <&clock_rpmcc RPM_XO_CLK_SRC>; @@ -1017,7 +1017,7 @@ reg = <0x15700000 0x00100>; interrupts = <0 162 1>; - vdd_cx-supply = <&pm2falcon_l9_level>; + vdd_cx-supply = <&pm660l_l9_level>; qcom,proxy-reg-names = "vdd_cx"; qcom,vdd_cx-uV-uA = ; @@ -1103,9 +1103,9 @@ "mnoc_axi_clk"; interrupts = <0 448 1>; - vdd_cx-supply = <&pm2falcon_s3_level>; + vdd_cx-supply = <&pm660l_s3_level>; vdd_cx-voltage = ; - vdd_mx-supply = <&pm2falcon_s5_level>; + vdd_mx-supply = <&pm660l_s5_level>; vdd_mx-uV = ; qcom,firmware-name = "modem"; qcom,pil-self-auth; @@ -1240,13 +1240,13 @@ }; #include "msmtriton-ion.dtsi" -#include "msm-pmfalcon.dtsi" -#include "msm-pm2falcon.dtsi" -#include "msm-pmfalcon-rpm-regulator.dtsi" -#include "msm-pm2falcon-rpm-regulator.dtsi" +#include "msm-pm660.dtsi" +#include "msm-pm660l.dtsi" +#include "msm-pm660-rpm-regulator.dtsi" +#include "msm-pm660l-rpm-regulator.dtsi" #include "msmtriton-regulator.dtsi" -#include "msm-gdsc-falcon.dtsi" -#include "msmfalcon-common.dtsi" +#include "msm-gdsc-660.dtsi" +#include "sdm660-common.dtsi" #include "msm-arm-smmu-triton.dtsi" &gdsc_usb30 { diff --git a/arch/arm/boot/dts/qcom/sda660-cdp.dts b/arch/arm/boot/dts/qcom/sda660-cdp.dts new file mode 100644 index 000000000000..43e43f7f7125 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sda660-cdp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sda660.dtsi" +#include "sdm660-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDA 660 PM660 + PM660L CDP"; + compatible = "qcom,sda660-cdp", "qcom,sda660", "qcom,cdp"; + qcom,board-id = <1 0>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sda660-mtp.dts b/arch/arm/boot/dts/qcom/sda660-mtp.dts new file mode 100644 index 000000000000..0e14f3df9d8b --- /dev/null +++ b/arch/arm/boot/dts/qcom/sda660-mtp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sda660.dtsi" +#include "sdm660-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDA 660 PM660 + PM660L MTP"; + compatible = "qcom,sda660-mtp", "qcom,sda660", "qcom,mtp"; + qcom,board-id = <8 0>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sda660-pm660a-cdp.dts b/arch/arm/boot/dts/qcom/sda660-pm660a-cdp.dts new file mode 100644 index 000000000000..bfccd541e4b6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sda660-pm660a-cdp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sda660.dtsi" +#include "sdm660-cdp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDA 660 PM660 + PM660A CDP"; + compatible = "qcom,sda660-cdp", "qcom,sda660", "qcom,cdp"; + qcom,board-id = <1 0>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sda660-pm660a-mtp.dts b/arch/arm/boot/dts/qcom/sda660-pm660a-mtp.dts new file mode 100644 index 000000000000..1b7cfe1e1077 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sda660-pm660a-mtp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sda660.dtsi" +#include "sdm660-mtp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDA 660 PM660 + PM660A MTP"; + compatible = "qcom,sda660-mtp", "qcom,sda660", "qcom,mtp"; + qcom,board-id = <8 0>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sda660-pm660a-rcm.dts b/arch/arm/boot/dts/qcom/sda660-pm660a-rcm.dts new file mode 100644 index 000000000000..aa7a890fbe39 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sda660-pm660a-rcm.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sda660.dtsi" +#include "sdm660-cdp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDA 660 PM660 + PM660A RCM"; + compatible = "qcom,sda660-cdp", "qcom,sda660", "qcom,cdp"; + qcom,board-id = <21 0>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sda660-rcm.dts b/arch/arm/boot/dts/qcom/sda660-rcm.dts new file mode 100644 index 000000000000..73ea188c5221 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sda660-rcm.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sda660.dtsi" +#include "sdm660-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDA 660 PM660 + PM660L RCM"; + compatible = "qcom,sda660-cdp", "qcom,sda660", "qcom,cdp"; + qcom,board-id = <21 0>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sda660.dtsi b/arch/arm/boot/dts/qcom/sda660.dtsi new file mode 100644 index 000000000000..d2919a9467dd --- /dev/null +++ b/arch/arm/boot/dts/qcom/sda660.dtsi @@ -0,0 +1,19 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdm660.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDA 660"; + compatible = "qcom,sda660"; + qcom,msm-id = <324 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-audio.dtsi b/arch/arm/boot/dts/qcom/sdm660-audio.dtsi new file mode 100644 index 000000000000..13ee40c71228 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-audio.dtsi @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdm660-wsa881x.dtsi" +#include "sdm660-lpi.dtsi" + +&slim_aud { + status = "okay"; + dai_slim: msm_dai_slim { + compatible = "qcom,msm-dai-slim"; + elemental-addr = [ff ff ff fe 17 02]; + }; + + wcd9335: tasha_codec { + compatible = "qcom,tasha-slim-pgd"; + elemental-addr = [00 01 a0 01 17 02]; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 + 30>; + + qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; + + clock-names = "wcd_clk", "wcd_native_clk"; + clocks = <&clock_audio AUDIO_PMI_CLK>, + <&clock_audio AUDIO_AP_CLK2>; + + cdc-vdd-mic-bias-supply = <&pm660l_bob>; + qcom,cdc-vdd-mic-bias-voltage = <3300000 3300000>; + qcom,cdc-vdd-mic-bias-current = <30400>; + + qcom,cdc-static-supplies = "cdc-vdd-mic-bias"; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + qcom,cdc-micbias4-mv = <1800>; + + qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-slim-ifd = "tasha-slim-ifd"; + qcom,cdc-slim-ifd-elemental-addr = [00 00 a0 01 17 02]; + qcom,cdc-dmic-sample-rate = <4800000>; + qcom,cdc-mad-dmic-rate = <600000>; + }; + + wcd934x_cdc: tavil_codec { + compatible = "qcom,tavil-slim-pgd"; + elemental-addr = [00 01 50 02 17 02]; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 + 30 31>; + + qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; + + clock-names = "wcd_clk"; + clocks = <&clock_audio_lnbb AUDIO_PMIC_LNBB_CLK>; + + cdc-vdd-mic-bias-supply = <&pm660l_bob>; + qcom,cdc-vdd-mic-bias-voltage = <3300000 3300000>; + qcom,cdc-vdd-mic-bias-current = <30400>; + + qcom,cdc-static-supplies = "cdc-vdd-mic-bias"; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + qcom,cdc-micbias4-mv = <1800>; + + qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-slim-ifd = "tavil-slim-ifd"; + qcom,cdc-slim-ifd-elemental-addr = [00 00 50 02 17 02]; + qcom,cdc-dmic-sample-rate = <4800000>; + qcom,cdc-mad-dmic-rate = <600000>; + + qcom,wdsp-cmpnt-dev-name = "tavil_codec"; + + wcd_spi_0: wcd_spi { + compatible = "qcom,wcd-spi-v2"; + qcom,master-bus-num = <10>; + qcom,chip-select = <0>; + qcom,max-frequency = <24000000>; + qcom,mem-base-addr = <0x100000>; + }; + }; +}; + +&pm660l_3 { + pmic_analog_codec: analog-codec@f000 { + status = "disabled"; + compatible = "qcom,pmic-analog-codec"; + reg = <0xf000 0x200>; + interrupt-parent = <&spmi_bus>; + interrupts = <0x1 0xf0 0x0>, + <0x1 0xf0 0x1>, + <0x1 0xf0 0x2>, + <0x1 0xf0 0x3>, + <0x1 0xf0 0x4>, + <0x1 0xf0 0x5>, + <0x1 0xf0 0x6>, + <0x1 0xf0 0x7>; + interrupt-names = "spk_cnp_int", + "spk_clip_int", + "spk_ocp_int", + "ins_rem_det1", + "but_rel_det", + "but_press_det", + "ins_rem_det", + "mbhc_int"; + + cdc-vdda-cp-supply = <&pm660_s4>; + qcom,cdc-vdda-cp-voltage = <1900000 2050000>; + qcom,cdc-vdda-cp-current = <50000>; + + cdc-vdd-pa-supply = <&pm660_s4>; + qcom,cdc-vdd-pa-voltage = <2040000 2040000>; + qcom,cdc-vdd-pa-current = <260000>; + + cdc-vdd-mic-bias-supply = <&pm660l_l7>; + qcom,cdc-vdd-mic-bias-voltage = <3125000 3125000>; + qcom,cdc-vdd-mic-bias-current = <5000>; + + qcom,cdc-mclk-clk-rate = <9600000>; + + qcom,cdc-static-supplies = "cdc-vdda-cp", + "cdc-vdd-pa"; + + qcom,cdc-on-demand-supplies = "cdc-vdd-mic-bias"; + + cdc_pdm_gpios: cdc_pdm_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_pdm_gpios_active>; + pinctrl-1 = <&cdc_pdm_gpios_sleep>; + qcom,lpi-gpios; + }; + + cdc_comp_gpios: cdc_comp_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_comp_gpios_active>; + pinctrl-1 = <&cdc_comp_gpios_sleep>; + qcom,lpi-gpios; + }; + /* + * Not marking address @ as driver searches this child + * with name msm-dig-codec + */ + msm_digital_codec: msm-dig-codec { + compatible = "qcom,msm-digital-codec"; + reg = <0x152c0000 0x0>; + cdc_dmic_gpios: cdc_dmic_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_dmic12_gpios_active + &cdc_dmic34_gpios_active>; + pinctrl-1 = <&cdc_dmic12_gpios_sleep + &cdc_dmic34_gpios_sleep>; + qcom,lpi-gpios; + }; + }; + }; +}; + +&soc { + msm_sdw_codec: msm-sdw-codec@152c1000 { + status = "disabled"; + compatible = "qcom,msm-sdw-codec"; + reg = <0x152c1000 0x0>; + interrupts = <0 161 0>; + interrupt-names = "swr_master_irq"; + + cdc_sdw_gpios: sdw_clk_data_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&sdw_clk_active &sdw_data_active>; + pinctrl-1 = <&sdw_clk_sleep &sdw_data_sleep>; + }; + + wsa_spkr_en1: wsa_spkr_en1_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-1 = <&spkr_1_sd_n_sleep>; + }; + + wsa_spkr_en2: wsa_spkr_en2_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_2_sd_n_active>; + pinctrl-1 = <&spkr_2_sd_n_sleep>; + }; + + swr_master { + compatible = "qcom,swr-wcd"; + #address-cells = <2>; + #size-cells = <0>; + + wsa881x_211_en: wsa881x_en@20170211 { + compatible = "qcom,wsa881x"; + reg = <0x0 0x20170211>; + qcom,spkr-sd-n-node = <&wsa_spkr_en1>; + }; + + wsa881x_212_en: wsa881x_en@20170212 { + compatible = "qcom,wsa881x"; + reg = <0x0 0x20170212>; + qcom,spkr-sd-n-node = <&wsa_spkr_en2>; + }; + + wsa881x_213_en: wsa881x_en@21170213 { + compatible = "qcom,wsa881x"; + reg = <0x0 0x21170213>; + qcom,spkr-sd-n-node = <&wsa_spkr_en1>; + }; + + wsa881x_214_en: wsa881x_en@21170214 { + compatible = "qcom,wsa881x"; + reg = <0x0 0x21170214>; + qcom,spkr-sd-n-node = <&wsa_spkr_en2>; + }; + }; + }; +}; + +&pm660_gpios { + gpio@c200 { + status = "ok"; + qcom,mode = <1>; + qcom,pull = <5>; + qcom,vin-sel = <0>; + qcom,src-sel = <2>; + qcom,master-en = <1>; + qcom,out-strength = <2>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-blsp.dtsi b/arch/arm/boot/dts/qcom/sdm660-blsp.dtsi new file mode 100644 index 000000000000..023c34d65680 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-blsp.dtsi @@ -0,0 +1,569 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "sdm660-pinctrl.dtsi" + +/ { + aliases { + spi1 = &spi_1; + spi2 = &spi_2; + spi3 = &spi_3; + spi4 = &spi_4; + spi5 = &spi_5; + spi6 = &spi_6; + spi7 = &spi_7; + spi8 = &spi_8; + i2c1 = &i2c_1; + i2c2 = &i2c_2; + i2c3 = &i2c_3; + i2c4 = &i2c_4; + i2c5 = &i2c_5; + i2c6 = &i2c_6; + i2c7 = &i2c_7; + i2c8 = &i2c_8; + }; +}; + + +&soc { + i2c_1: i2c@c175000 { /* BLSP1 QUP1 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc175000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 95 0>; + dmas = <&dma_blsp1 4 64 0x20000020 0x20>, + <&dma_blsp1 5 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_1_active>; + pinctrl-1 = <&i2c_1_sleep>; + status = "disabled"; + }; + + i2c_2: i2c@c176000 { /* BLSP1 QUP2 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc176000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 96 0>; + dmas = <&dma_blsp1 6 64 0x20000020 0x20>, + <&dma_blsp1 7 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_2_active>; + pinctrl-1 = <&i2c_2_sleep>; + status = "disabled"; + }; + + i2c_3: i2c@c177000 { /* BLSP1 QUP3 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc177000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 97 0>; + dmas = <&dma_blsp1 8 64 0x20000020 0x20>, + <&dma_blsp1 9 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_3_active>; + pinctrl-1 = <&i2c_3_sleep>; + status = "disabled"; + }; + + i2c_4: i2c@c178000 { /* BLSP1 QUP4 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc178000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 98 0>; + dmas = <&dma_blsp1 10 64 0x20000020 0x20>, + <&dma_blsp1 11 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <86>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_4_active>; + pinctrl-1 = <&i2c_4_sleep>; + status = "disabled"; + }; + + i2c_5: i2c@c1b5000 { /* BLSP2 QUP1 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc1b5000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 101 0>; + dmas = <&dma_blsp2 4 64 0x20000020 0x20>, + <&dma_blsp2 5 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <84>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, + <&clock_gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_5_active>; + pinctrl-1 = <&i2c_5_sleep>; + status = "disabled"; + }; + + i2c_6: i2c@c1b6000 { /* BLSP2 QUP2 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc1b6000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 102 0>; + dmas = <&dma_blsp2 6 64 0x20000020 0x20>, + <&dma_blsp2 7 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <84>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, + <&clock_gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_6_active>; + pinctrl-1 = <&i2c_6_sleep>; + status = "disabled"; + }; + + i2c_7: i2c@c1b7000 { /* BLSP2 QUP3 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc1b7000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 103 0>; + dmas = <&dma_blsp2 8 64 0x20000020 0x20>, + <&dma_blsp2 9 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <84>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, + <&clock_gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_7_active>; + pinctrl-1 = <&i2c_7_sleep>; + status = "disabled"; + }; + + i2c_8: i2c@c1b8000 { /* BLSP2 QUP4 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc1b8000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 104 0>; + dmas = <&dma_blsp2 10 64 0x20000020 0x20>, + <&dma_blsp2 11 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <84>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, + <&clock_gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_8_active>; + pinctrl-1 = <&i2c_8_sleep>; + status = "disabled"; + }; + + spi_1: spi@c175000 { /* BLSP1 QUP1 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xc175000 0x600>, + <0xc144000 0x1f000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 95 0>, <0 238 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <4>; + qcom,bam-producer-pipe-index = <5>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_1_active>; + pinctrl-1 = <&spi_1_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_2: spi@c176000 { /* BLSP1 QUP2 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xc176000 0x600>, + <0xc144000 0x1f000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 96 0>, <0 238 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <6>; + qcom,bam-producer-pipe-index = <7>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_2_active>; + pinctrl-1 = <&spi_2_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_3: spi@c177000 { /* BLSP1 QUP3 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xc177000 0x600>, + <0xc144000 0x1f000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 97 0>, <0 238 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <8>; + qcom,bam-producer-pipe-index = <9>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_3_active>; + pinctrl-1 = <&spi_3_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_4: spi@c178000 { /* BLSP1 QUP4 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xc178000 0x600>, + <0xc144000 0x1f000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 98 0>, <0 238 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <10>; + qcom,bam-producer-pipe-index = <11>; + qcom,master-id = <86>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_4_active>; + pinctrl-1 = <&spi_4_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_5: spi@c1b5000 { /* BLSP2 QUP1 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xc1b5000 0x600>, + <0xc184000 0x1f000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 101 0>, <0 239 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <4>; + qcom,bam-producer-pipe-index = <5>; + qcom,master-id = <84>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_5_active>; + pinctrl-1 = <&spi_5_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, + <&clock_gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_6: spi@c1b6000 { /* BLSP2 QUP2 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xc1b6000 0x600>, + <0xc184000 0x1f000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 102 0>, <0 239 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <6>; + qcom,bam-producer-pipe-index = <7>; + qcom,master-id = <84>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_6_active>; + pinctrl-1 = <&spi_6_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, + <&clock_gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_7: spi@c1b7000 { /* BLSP2 QUP3 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xc1b7000 0x600>, + <0xc184000 0x1f000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 103 0>, <0 239 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <8>; + qcom,bam-producer-pipe-index = <9>; + qcom,master-id = <84>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_7_active>; + pinctrl-1 = <&spi_7_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, + <&clock_gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_8: spi@c1b8000 { /* BLSP2 QUP4 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xc1b8000 0x600>, + <0xc184000 0x1f000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 104 0>, <0 239 0>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <10>; + qcom,bam-producer-pipe-index = <11>; + qcom,master-id = <84>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_8_active>; + pinctrl-1 = <&spi_8_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>, + <&clock_gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>; + status = "disabled"; + }; + + blsp1_uart1_hs: uart@c16f000 { /* BLSP1 UART1 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0xc16f000 0x200>, + <0xc144000 0x1f000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart1_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 0 107 0 + 1 &intc 0 0 238 0 + 2 &tlmm 1 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc GCC_BLSP1_UART1_APPS_CLK>, + <&clock_gcc GCC_BLSP1_AHB_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart1_sleep>; + pinctrl-1 = <&blsp1_uart1_active>; + + qcom,msm-bus,name = "buart1"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; + + blsp1_uart2_hs: uart@c170000 { /* BLSP1 UART2 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0xc170000 0x200>, + <0xc144000 0x1f000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart2_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 0 108 0 + 1 &intc 0 0 238 0 + 2 &tlmm 5 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <2>; + qcom,bam-rx-ep-pipe-index = <3>; + qcom,master-id = <86>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>, + <&clock_gcc GCC_BLSP1_AHB_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart2_sleep>; + pinctrl-1 = <&blsp1_uart2_active>; + + qcom,msm-bus,name = "buart2"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <86 512 0 0>, + <86 512 500 800>; + status = "disabled"; + }; + + blsp2_uart1_hs: uart@c1af000 { /* BLSP2 UART1 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0xc1af000 0x200>, + <0xc184000 0x1f000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp2_uart1_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 0 113 0 + 1 &intc 0 0 239 0 + 2 &tlmm 17 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + qcom,master-id = <84>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc GCC_BLSP2_UART1_APPS_CLK>, + <&clock_gcc GCC_BLSP2_AHB_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp2_uart1_sleep>; + pinctrl-1 = <&blsp2_uart1_active>; + + qcom,msm-bus,name = "buart3"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <84 512 0 0>, + <84 512 500 800>; + status = "disabled"; + }; + + blsp2_uart2_hs: uart@c1b0000 { /* BLSP2 UART2 */ + compatible = "qcom,msm-hsuart-v14"; + reg = <0xc1b0000 0x200>, + <0xc184000 0x1f000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp2_uart2_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 0 114 0 + 1 &intc 0 0 239 0 + 2 &tlmm 25 0>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <2>; + qcom,bam-rx-ep-pipe-index = <3>; + qcom,master-id = <84>; + clock-names = "core_clk", "iface_clk"; + clocks = <&clock_gcc GCC_BLSP2_UART2_APPS_CLK>, + <&clock_gcc GCC_BLSP2_AHB_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp2_uart2_sleep>; + pinctrl-1 = <&blsp2_uart2_active>; + + qcom,msm-bus,name = "buart4"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <84 512 0 0>, + <84 512 500 800>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-bus.dtsi b/arch/arm/boot/dts/qcom/sdm660-bus.dtsi new file mode 100644 index 000000000000..93c615639be9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-bus.dtsi @@ -0,0 +1,1284 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + ad_hoc_bus: ad-hoc-bus { + /*Version = 14 */ + compatible = "qcom,msm-bus-device"; + reg = <0x1620000 0x20000>, + <0x1000000 0x80000>, + <0x1500000 0x10000>, + <0x1700000 0x20000>, + <0x17900000 0xE000>, + <0x1740000 0x10000>, + <0x1740000 0x10000>; + + reg-names = "snoc-base", "bimc-base", "cnoc-base", + "a2noc-base", "gnoc-base", "mmnoc-ahb-base", "mnoc-base"; + + /*Buses*/ + + fab_a2noc: fab-a2noc { + cell-id = ; + label = "fab-a2noc"; + qcom,fab-dev; + qcom,base-name = "a2noc-base"; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + qcom,qos-off = <4096>; + qcom,base-offset = <16384>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_rpmcc RPM_AGGR2_NOC_CLK>, + <&clock_rpmcc RPM_AGGR2_NOC_A_CLK>; + qcom,node-qos-clks { + clock-names = + "clk-ipa-clk", + "clk-sdcc1-ahb-no-rate", + "clk-sdcc2-ahb-no-rate", + "clk-blsp1-ahb-no-rate", + "clk-blsp2-ahb-no-rate"; + clocks = + <&clock_rpmcc RPM_IPA_CLK>, + <&clock_gcc GCC_SDCC1_AHB_CLK>, + <&clock_gcc GCC_SDCC2_AHB_CLK>, + <&clock_gcc GCC_BLSP1_AHB_CLK>, + <&clock_gcc GCC_BLSP2_AHB_CLK>; + }; + }; + + fab_bimc: fab-bimc { + cell-id = ; + label = "fab-bimc"; + qcom,fab-dev; + qcom,base-name = "bimc-base"; + qcom,bus-type = <2>; + qcom,bypass-qos-prg; + qcom,util-fact = <153>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_rpmcc BIMC_MSMBUS_CLK>, + <&clock_rpmcc BIMC_MSMBUS_A_CLK>; + }; + + fab_cnoc: fab-cnoc { + cell-id = ; + label = "fab-cnoc"; + qcom,fab-dev; + qcom,base-name = "cnoc-base"; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_rpmcc CNOC_MSMBUS_CLK>, + <&clock_rpmcc CNOC_MSMBUS_A_CLK>; + }; + + fab_gnoc: fab-gnoc { + cell-id = ; + label = "fab-gnoc"; + qcom,virt-dev; + qcom,base-name = "gnoc-base"; + qcom,bypass-qos-prg; + }; + + fab_mnoc: fab-mnoc { + cell-id = ; + label = "fab-mnoc"; + qcom,fab-dev; + qcom,base-name = "mnoc-base"; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + qcom,qos-off = <4096>; + qcom,base-offset = <20480>; + qcom,util-fact = <153>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_rpmcc MMSSNOC_AXI_A_CLK>; + clk-camss-ahb-no-rate-supply = + <&gdsc_camss_top>; + clk-video-ahb-no-rate-supply = + <&gdsc_venus>; + clk-video-axi-no-rate-supply = + <&gdsc_venus>; + qcom,node-qos-clks { + clock-names = + "clk-mmssnoc-axi-no-rate", + "clk-noc-cfg-ahb-no-rate", + "clk-mnoc-ahb-no-rate", + "clk-camss-ahb-no-rate", + "clk-video-ahb-no-rate", + "clk-video-axi-no-rate"; + clocks = + <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_gcc GCC_MMSS_NOC_CFG_AHB_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_VIDEO_AHB_CLK>, + <&clock_mmss MMSS_VIDEO_AXI_CLK>; + }; + }; + + fab_snoc: fab-snoc { + cell-id = ; + label = "fab-snoc"; + qcom,fab-dev; + qcom,base-name = "snoc-base"; + qcom,bypass-qos-prg; + qcom,bus-type = <1>; + qcom,qos-off = <4096>; + qcom,base-offset = <24576>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_rpmcc SNOC_MSMBUS_CLK>, + <&clock_rpmcc SNOC_MSMBUS_A_CLK>; + }; + + fab_mnoc_ahb: fab-mnoc-ahb { + cell-id = ; + label = "fab-mnoc-ahb"; + qcom,fab-dev; + qcom,base-name = "mmnoc-ahb-base"; + qcom,bypass-qos-prg; + qcom,setrate-only-clk; + qcom,bus-type = <1>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&clock_mmss AHB_CLK_SRC >, + <&clock_mmss AHB_CLK_SRC>; + }; + + /*Masters*/ + + mas_ipa: mas-ipa { + cell-id = ; + label = "mas-ipa"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <3>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_a2noc_snoc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + }; + + mas_cnoc_a2noc: mas-cnoc-a2noc { + cell-id = ; + label = "mas-cnoc-a2noc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_a2noc_snoc>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + qcom,blacklist = <&slv_snoc_cnoc>; + }; + + mas_sdcc_1: mas-sdcc-1 { + cell-id = ; + label = "mas-sdcc-1"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_a2noc_snoc>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + }; + + mas_sdcc_2: mas-sdcc-2 { + cell-id = ; + label = "mas-sdcc-2"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_a2noc_snoc>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + }; + + mas_blsp_1: mas-blsp-1 { + cell-id = ; + label = "mas-blsp-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_a2noc_snoc>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + }; + + mas_blsp_2: mas-blsp-2 { + cell-id = ; + label = "mas-blsp-2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_a2noc_snoc>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + }; + + mas_ufs: mas-ufs { + cell-id = ; + label = "mas-ufs"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <4>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_a2noc_snoc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + }; + + mas_usb_hs: mas-usb-hs { + cell-id = ; + label = "mas-usb-hs"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <1>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_a2noc_snoc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + }; + + mas_usb3: mas-usb3 { + cell-id = ; + label = "mas-usb3"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <2>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_a2noc_snoc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + }; + + mas_crypto_c0: mas-crypto-c0 { + cell-id = ; + label = "mas-crypto-c0"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,qport = <11>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_a2noc_snoc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_a2noc>; + qcom,mas-rpm-id = ; + }; + + mas_gnoc_bimc: mas-gnoc-bimc { + cell-id = ; + label = "mas-gnoc-bimc"; + qcom,buswidth = <4>; + qcom,agg-ports = <2>; + qcom,ap-owned; + qcom,qport = <0>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_ebi>; + qcom,prio-lvl = <0>; + qcom,prio-rd = <0>; + qcom,prio-wr = <0>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_oxili: mas-oxili { + cell-id = ; + label = "mas-oxili"; + qcom,buswidth = <4>; + qcom,agg-ports = <2>; + qcom,ap-owned; + qcom,qport = <1>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_hmss_l3 + &slv_ebi &slv_bimc_snoc>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_mnoc_bimc: mas-mnoc-bimc { + cell-id = ; + label = "mas-mnoc-bimc"; + qcom,buswidth = <4>; + qcom,agg-ports = <2>; + qcom,ap-owned; + qcom,qport = <2>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_hmss_l3 + &slv_ebi &slv_bimc_snoc>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_snoc_bimc: mas-snoc-bimc { + cell-id = ; + label = "mas-snoc-bimc"; + qcom,buswidth = <4>; + qcom,agg-ports = <2>; + qcom,connections = <&slv_hmss_l3 &slv_ebi>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_pimem: mas-pimem { + cell-id = ; + label = "mas-pimem"; + qcom,buswidth = <4>; + qcom,agg-ports = <2>; + qcom,ap-owned; + qcom,qport = <4>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_hmss_l3 &slv_ebi>; + qcom,prio-lvl = <0>; + qcom,prio-rd = <0>; + qcom,prio-wr = <0>; + qcom,bus-dev = <&fab_bimc>; + qcom,mas-rpm-id = ; + }; + + mas_snoc_cnoc: mas-snoc-cnoc { + cell-id = ; + label = "mas-snoc-cnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_clk_ctl + &slv_qdss_cfg &slv_qm_cfg + &slv_srvc_cnoc &slv_ufs_cfg + &slv_tcsr &slv_a2noc_smmu_cfg + &slv_snoc_cfg &slv_tlmm_south + &slv_mpm &slv_cnoc_mnoc_mmss_cfg + &slv_sdcc_2 &slv_sdcc_1 + &slv_spdm &slv_pmic_arb + &slv_prng &slv_mss_cfg + &slv_gpuss_cfg &slv_imem_cfg + &slv_usb3_0 &slv_a2noc_cfg + &slv_tlmm_north &slv_usb_hs + &slv_pdm &slv_tlmm_center + &slv_ahb2phy &slv_blsp_2 + &slv_blsp_1 &slv_pimem_cfg + &slv_glm &slv_message_ram + &slv_bimc_cfg &slv_cnoc_mnoc_cfg>; + qcom,bus-dev = <&fab_cnoc>; + qcom,mas-rpm-id = ; + }; + + mas_qdss_dap: mas-qdss-dap { + cell-id = ; + label = "mas-qdss-dap"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_clk_ctl + &slv_qdss_cfg &slv_qm_cfg + &slv_srvc_cnoc &slv_ufs_cfg + &slv_tcsr &slv_a2noc_smmu_cfg + &slv_snoc_cfg &slv_tlmm_south + &slv_mpm &slv_cnoc_mnoc_mmss_cfg + &slv_sdcc_2 &slv_sdcc_1 + &slv_spdm &slv_pmic_arb + &slv_prng &slv_mss_cfg + &slv_gpuss_cfg &slv_imem_cfg + &slv_usb3_0 &slv_a2noc_cfg + &slv_tlmm_north &slv_usb_hs + &slv_pdm &slv_tlmm_center + &slv_ahb2phy &slv_blsp_2 + &slv_blsp_1 &slv_pimem_cfg + &slv_glm &slv_message_ram + &slv_cnoc_a2noc &slv_bimc_cfg + &slv_cnoc_mnoc_cfg>; + qcom,bus-dev = <&fab_cnoc>; + qcom,mas-rpm-id = ; + }; + + mas_apps_proc: mas-apps-proc { + cell-id = ; + label = "mas-apps-proc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_gnoc_snoc &slv_gnoc_bimc>; + qcom,bus-dev = <&fab_gnoc>; + qcom,mas-rpm-id = ; + }; + + mas_cnoc_mnoc_mmss_cfg: mas-cnoc-mnoc-mmss-cfg { + cell-id = ; + label = "mas-cnoc-mnoc-mmss-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_venus_throttle_cfg + &slv_venus_cfg &slv_camera_throttle_cfg + &slv_smmu_cfg &slv_camera_cfg &slv_csi_phy_cfg + &slv_display_throttle_cfg &slv_display_cfg + &slv_mmss_clk_cfg &slv_mnoc_mpu_cfg + &slv_misc_cfg &slv_mmss_clk_xpu_cfg>; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,mas-rpm-id = ; + }; + + mas_cnoc_mnoc_cfg: mas-cnoc-mnoc-cfg { + cell-id = ; + label = "mas-cnoc-mnoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,connections = <&slv_srvc_mnoc>; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,mas-rpm-id = ; + }; + + mas_cpp: mas-cpp { + cell-id = ; + label = "mas-cpp"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <4>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_mnoc_bimc>; + qcom,bus-dev = <&fab_mnoc>; + qcom,mas-rpm-id = ; + }; + + mas_jpeg: mas-jpeg { + cell-id = ; + label = "mas-jpeg"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <6>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_mnoc_bimc>; + qcom,bus-dev = <&fab_mnoc>; + qcom,mas-rpm-id = ; + }; + + mas_mdp_p0: mas-mdp-p0 { + cell-id = ; + label = "mas-mdp-p0"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <0>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_mnoc_bimc>; + qcom,bus-dev = <&fab_mnoc>; + qcom,vrail-comp = <50>; + qcom,mas-rpm-id = ; + clk-mdss-axi-no-rate-supply = + <&gdsc_mdss>; + clk-mdss-ahb-no-rate-supply = + <&gdsc_mdss>; + qcom,node-qos-clks { + clock-names = + "clk-mdss-ahb-no-rate", + "clk-mdss-axi-no-rate"; + clocks = + <&clock_mmss MMSS_MDSS_AHB_CLK>, + <&clock_mmss MMSS_MDSS_AXI_CLK>; + }; + }; + + mas_mdp_p1: mas-mdp-p1 { + cell-id = ; + label = "mas-mdp-p1"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <1>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_mnoc_bimc>; + qcom,bus-dev = <&fab_mnoc>; + qcom,vrail-comp = <50>; + qcom,mas-rpm-id = ; + }; + + mas_venus: mas-venus { + cell-id = ; + label = "mas-venus"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <2>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_mnoc_bimc>; + qcom,bus-dev = <&fab_mnoc>; + qcom,mas-rpm-id = ; + }; + + mas_vfe: mas-vfe { + cell-id = ; + label = "mas-vfe"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <5>; + qcom,qos-mode = "bypass"; + qcom,connections = <&slv_mnoc_bimc>; + qcom,bus-dev = <&fab_mnoc>; + qcom,mas-rpm-id = ; + }; + + mas_qdss_etr: mas-qdss-etr { + cell-id = ; + label = "mas-qdss-etr"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <1>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_pimem + &slv_imem &slv_snoc_cnoc + &slv_snoc_bimc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + mas_qdss_bam: mas-qdss-bam { + cell-id = ; + label = "mas-qdss-bam"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,qport = <0>; + qcom,qos-mode = "fixed"; + qcom,connections = <&slv_pimem + &slv_imem &slv_snoc_cnoc + &slv_snoc_bimc>; + qcom,prio1 = <1>; + qcom,prio0 = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + mas_snoc_cfg: mas-snoc-cfg { + cell-id = ; + label = "mas-snoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_srvc_snoc>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + mas_bimc_snoc: mas-bimc-snoc { + cell-id = ; + label = "mas-bimc-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_pimem + &slv_ipa &slv_qdss_stm + &slv_lpass &slv_hmss + &slv_cdsp &slv_snoc_cnoc + &slv_wlan &slv_imem>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + mas_a2noc_snoc: mas-a2noc-snoc { + cell-id = ; + label = "mas-a2noc-snoc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_pimem + &slv_ipa &slv_qdss_stm + &slv_lpass &slv_hmss + &slv_snoc_bimc &slv_cdsp + &slv_snoc_cnoc &slv_wlan + &slv_imem>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + /*Internal nodes*/ + + /*Slaves*/ + + slv_a2noc_snoc:slv-a2noc-snoc { + cell-id = ; + label = "slv-a2noc-snoc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_a2noc>; + qcom,connections = <&mas_a2noc_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_ebi:slv-ebi { + cell-id = ; + label = "slv-ebi"; + qcom,buswidth = <4>; + qcom,agg-ports = <2>; + qcom,bus-dev = <&fab_bimc>; + qcom,slv-rpm-id = ; + }; + + slv_hmss_l3:slv-hmss-l3 { + cell-id = ; + label = "slv-hmss-l3"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_bimc>; + qcom,slv-rpm-id = ; + }; + + slv_bimc_snoc:slv-bimc-snoc { + cell-id = ; + label = "slv-bimc-snoc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_bimc>; + qcom,connections = <&mas_bimc_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_cnoc_a2noc:slv-cnoc-a2noc { + cell-id = ; + label = "slv-cnoc-a2noc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,connections = <&mas_cnoc_a2noc>; + qcom,slv-rpm-id = ; + }; + + slv_mpm:slv-mpm { + cell-id = ; + label = "slv-mpm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_pmic_arb:slv-pmic-arb { + cell-id = ; + label = "slv-pmic-arb"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_tlmm_north:slv-tlmm-north { + cell-id = ; + label = "slv-tlmm-north"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_tcsr:slv-tcsr { + cell-id = ; + label = "slv-tcsr"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_pimem_cfg:slv-pimem-cfg { + cell-id = ; + label = "slv-pimem-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_imem_cfg:slv-imem-cfg { + cell-id = ; + label = "slv-imem-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_message_ram:slv-message-ram { + cell-id = ; + label = "slv-message-ram"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_glm:slv-glm { + cell-id = ; + label = "slv-glm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_bimc_cfg:slv-bimc-cfg { + cell-id = ; + label = "slv-bimc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_prng:slv-prng { + cell-id = ; + label = "slv-prng"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_spdm:slv-spdm { + cell-id = ; + label = "slv-spdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_qdss_cfg:slv-qdss-cfg { + cell-id = ; + label = "slv-qdss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_cnoc_mnoc_cfg:slv-cnoc-mnoc-cfg { + cell-id = ; + label = "slv-cnoc-mnoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,connections = <&mas_cnoc_mnoc_cfg>; + qcom,slv-rpm-id = ; + }; + + slv_snoc_cfg:slv-snoc-cfg { + cell-id = ; + label = "slv-snoc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_qm_cfg:slv-qm-cfg { + cell-id = ; + label = "slv-qm-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_clk_ctl:slv-clk-ctl { + cell-id = ; + label = "slv-clk-ctl"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_mss_cfg:slv-mss-cfg { + cell-id = ; + label = "slv-mss-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_tlmm_south:slv-tlmm-south { + cell-id = ; + label = "slv-tlmm-south"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_ufs_cfg:slv-ufs-cfg { + cell-id = ; + label = "slv-ufs-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_a2noc_cfg:slv-a2noc-cfg { + cell-id = ; + label = "slv-a2noc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_a2noc_smmu_cfg:slv-a2noc-smmu-cfg { + cell-id = ; + label = "slv-a2noc-smmu-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_gpuss_cfg:slv-gpuss-cfg { + cell-id = ; + label = "slv-gpuss-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_ahb2phy:slv-ahb2phy { + cell-id = ; + label = "slv-ahb2phy"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_blsp_1:slv-blsp-1 { + cell-id = ; + label = "slv-blsp-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_sdcc_1:slv-sdcc-1 { + cell-id = ; + label = "slv-sdcc-1"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_sdcc_2:slv-sdcc-2 { + cell-id = ; + label = "slv-sdcc-2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_tlmm_center:slv-tlmm-center { + cell-id = ; + label = "slv-tlmm-center"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_blsp_2:slv-blsp-2 { + cell-id = ; + label = "slv-blsp-2"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_pdm:slv-pdm { + cell-id = ; + label = "slv-pdm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_cnoc_mnoc_mmss_cfg:slv-cnoc-mnoc-mmss-cfg { + cell-id = ; + label = "slv-cnoc-mnoc-mmss-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,connections = <&mas_cnoc_mnoc_mmss_cfg>; + qcom,slv-rpm-id = ; + }; + + slv_usb_hs:slv-usb-hs { + cell-id = ; + label = "slv-usb-hs"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_usb3_0:slv-usb3-0 { + cell-id = ; + label = "slv-usb3-0"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_srvc_cnoc:slv-srvc-cnoc { + cell-id = ; + label = "slv-srvc-cnoc"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_cnoc>; + qcom,slv-rpm-id = ; + }; + + + slv_gnoc_bimc:slv-gnoc-bimc { + cell-id = ; + label = "slv-gnoc-bimc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_gnoc>; + qcom,connections = <&mas_gnoc_bimc>; + qcom,slv-rpm-id = ; + }; + + slv_gnoc_snoc:slv-gnoc-snoc { + cell-id = ; + label = "slv-gnoc-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_gnoc>; + qcom,connections = <&mas_gnoc_snoc>; + qcom,slv-rpm-id = ; + }; + + mas_gnoc_snoc: mas-gnoc-snoc { + cell-id = ; + label = "mas-gnoc-snoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,connections = <&slv_pimem + &slv_ipa &slv_qdss_stm + &slv_lpass &slv_hmss + &slv_cdsp &slv_snoc_cnoc + &slv_wlan &slv_imem>; + qcom,bus-dev = <&fab_snoc>; + qcom,mas-rpm-id = ; + }; + + slv_camera_cfg:slv-camera-cfg { + cell-id = ; + label = "slv-camera-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_camera_throttle_cfg:slv-camera-throttle-cfg { + cell-id = ; + label = "slv-camera-throttle-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_misc_cfg:slv-misc-cfg { + cell-id = ; + label = "slv-misc-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_venus_throttle_cfg:slv-venus-throttle-cfg { + cell-id = ; + label = "slv-venus-throttle-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_venus_cfg:slv-venus-cfg { + cell-id = ; + label = "slv-venus-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_mmss_clk_xpu_cfg:slv-mmss-clk-xpu-cfg { + cell-id = ; + label = "slv-mmss-clk-xpu-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_mmss_clk_cfg:slv-mmss-clk-cfg { + cell-id = ; + label = "slv-mmss-clk-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_mnoc_mpu_cfg:slv-mnoc-mpu-cfg { + cell-id = ; + label = "slv-mnoc-mpu-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_display_cfg:slv-display-cfg { + cell-id = ; + label = "slv-display-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_csi_phy_cfg:slv-csi-phy-cfg { + cell-id = ; + label = "slv-csi-phy-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_display_throttle_cfg:slv-display-throttle-cfg { + cell-id = ; + label = "slv-display-throttle-cfg"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_smmu_cfg:slv-smmu-cfg { + cell-id = ; + label = "slv-smmu-cfg"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_mnoc_bimc:slv-mnoc-bimc { + cell-id = ; + label = "slv-mnoc-bimc"; + qcom,buswidth = <16>; + qcom,agg-ports = <2>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc>; + qcom,connections = <&mas_mnoc_bimc>; + qcom,slv-rpm-id = ; + qcom,enable-only-clk; + clock-names = "node_clk"; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>; + }; + + slv_srvc_mnoc:slv-srvc-mnoc { + cell-id = ; + label = "slv-srvc-mnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_mnoc_ahb>; + qcom,slv-rpm-id = ; + }; + + slv_hmss:slv-hmss { + cell-id = ; + label = "slv-hmss"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_lpass:slv-lpass { + cell-id = ; + label = "slv-lpass"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_wlan:slv-wlan { + cell-id = ; + label = "slv-wlan"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_cdsp:slv-cdsp { + cell-id = ; + label = "slv-cdsp"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_ipa:slv-ipa { + cell-id = ; + label = "slv-ipa"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,ap-owned; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_snoc_bimc:slv-snoc-bimc { + cell-id = ; + label = "slv-snoc-bimc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,connections = <&mas_snoc_bimc>; + qcom,slv-rpm-id = ; + }; + + slv_snoc_cnoc:slv-snoc-cnoc { + cell-id = ; + label = "slv-snoc-cnoc"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,connections = <&mas_snoc_cnoc>; + qcom,slv-rpm-id = ; + }; + + slv_imem:slv-imem { + cell-id = ; + label = "slv-imem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_pimem:slv-pimem { + cell-id = ; + label = "slv-pimem"; + qcom,buswidth = <8>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_qdss_stm:slv-qdss-stm { + cell-id = ; + label = "slv-qdss-stm"; + qcom,buswidth = <4>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + + slv_srvc_snoc:slv-srvc-snoc { + cell-id = ; + label = "slv-srvc-snoc"; + qcom,buswidth = <16>; + qcom,agg-ports = <1>; + qcom,bus-dev = <&fab_snoc>; + qcom,slv-rpm-id = ; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-camera-sensor-cdp.dtsi b/arch/arm/boot/dts/qcom/sdm660-camera-sensor-cdp.dtsi new file mode 100644 index 000000000000..e31a863ae22d --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-camera-sensor-cdp.dtsi @@ -0,0 +1,384 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + led_flash0: qcom,camera-flash@0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + qcom,flash-source = <&pm660l_flash0 &pm660l_flash1>; + qcom,torch-source = <&pm660l_torch0 &pm660l_torch1>; + qcom,switch-source = <&pm660l_switch0>; + status = "ok"; + }; + + led_flash1: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + qcom,flash-source = <&pm660l_flash2>; + qcom,torch-source = <&pm660l_torch2>; + qcom,switch-source = <&pm660l_switch1>; + status = "ok"; + }; +}; + +&cci { + actuator0: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + gpios = <&tlmm 50 0>; + qcom,gpio-vaf = <0>; + qcom,gpio-req-tbl-num = <0>; + qcom,gpio-req-tbl-flags = <0>; + qcom,gpio-req-tbl-label = "CAM_VAF"; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_actuator_vaf_active>; + pinctrl-1 = <&cam_actuator_vaf_suspend>; + }; + + actuator1: qcom,actuator@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,actuator"; + qcom,cci-master = <1>; + gpios = <&tlmm 50 0>; + qcom,gpio-vaf = <0>; + qcom,gpio-req-tbl-num = <0>; + qcom,gpio-req-tbl-flags = <0>; + qcom,gpio-req-tbl-label = "CAM_VAF"; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_actuator_vaf_active>; + pinctrl-1 = <&cam_actuator_vaf_suspend>; + }; + + actuator2: qcom,actuator@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,actuator"; + qcom,cci-master = <1>; + gpios = <&tlmm 50 0>; + qcom,gpio-vaf = <0>; + qcom,gpio-req-tbl-num = <0>; + qcom,gpio-req-tbl-flags = <0>; + qcom,gpio-req-tbl-label = "CAM_VAF"; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_actuator_vaf_active>; + pinctrl-1 = <&cam_actuator_vaf_suspend>; + }; + + ois0: qcom,ois@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,ois"; + qcom,cci-master = <0>; + gpios = <&tlmm 50 0>; + qcom,gpio-vaf = <0>; + qcom,gpio-req-tbl-num = <0>; + qcom,gpio-req-tbl-flags = <0>; + qcom,gpio-req-tbl-label = "CAM_VAF"; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_actuator_vaf_active>; + pinctrl-1 = <&cam_actuator_vaf_suspend>; + status = "disabled"; + }; + + eeprom0: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active + &cam_actuator_vaf_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend + &cam_actuator_vaf_suspend>; + gpios = <&tlmm 32 0>, + <&tlmm 46 0>, + <&pm660l_gpios 4 0>, + <&tlmm 51 0>, + <&tlmm 50 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-vaf = <4>; + qcom,gpio-req-tbl-num = <0 1 2 3 4>; + qcom,gpio-req-tbl-flags = <1 0 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VDIG", + "CAM_VANA", + "CAM_VAF"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&clock_mmss MCLK0_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK0_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + eeprom1: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 34 0>, + <&tlmm 48 0>, + <&pm660l_gpios 3 0>, + <&tlmm 51 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-req-tbl-num = <0 1 2 3>; + qcom,gpio-req-tbl-flags = <1 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET", + "CAM_VDIG", + "CAM_VANA"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_mmss MCLK2_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + eeprom2: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_front_active + &cam_actuator_vaf_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_front_suspend + &cam_actuator_vaf_suspend>; + gpios = <&tlmm 33 0>, + <&tlmm 47 0>, + <&pm660_gpios 3 0>, + <&tlmm 44 0>, + <&tlmm 50 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-vaf = <4>; + qcom,gpio-req-tbl-num = <0 1 2 3 4>; + qcom,gpio-req-tbl-flags = <1 0 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VDIG", + "CAM_VANA", + "CAM_VAF"; + qcom,sensor-position = <1>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_mmss MCLK1_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK1_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@0 { + cell-index = <0>; + compatible = "qcom,camera"; + reg = <0x0>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <270>; + qcom,led-flash-src = <&led_flash0>; + qcom,actuator-src = <&actuator0>; + qcom,ois-src = <&ois0>; + qcom,eeprom-src = <&eeprom0>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 32 0>, + <&tlmm 46 0>, + <&pm660l_gpios 4 0>, + <&tlmm 51 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-req-tbl-num = <0 1 2 3>; + qcom,gpio-req-tbl-flags = <1 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VDIG", + "CAM_VANA"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&clock_mmss MCLK0_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK0_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@1 { + cell-index = <1>; + compatible = "qcom,camera"; + reg = <0x1>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <2>; + qcom,mount-angle = <90>; + qcom,actuator-src = <&actuator1>; + qcom,eeprom-src = <&eeprom1>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 34 0>, + <&tlmm 48 0>, + <&pm660l_gpios 3 0>, + <&tlmm 51 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-req-tbl-num = <0 1 2 3>; + qcom,gpio-req-tbl-flags = <1 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET", + "CAM_VDIG", + "CAM_VANA"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_mmss MCLK2_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@2 { + cell-index = <2>; + compatible = "qcom,camera"; + reg = <0x02>; + qcom,csiphy-sd-index = <2>; + qcom,csid-sd-index = <2>; + qcom,mount-angle = <90>; + qcom,actuator-src = <&actuator2>; + qcom,eeprom-src = <&eeprom2>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 33 0>, + <&tlmm 47 0>, + <&pm660l_gpios 3 0>, + <&tlmm 51 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-req-tbl-num = <0 1 2 3>; + qcom,gpio-req-tbl-flags = <1 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VDIG", + "CAM_VANA"; + qcom,sensor-position = <1>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_mmss MCLK1_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK1_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; +}; + +&pm660l_gpios { + gpio@c300 { /* GPIO4 -CAMERA SENSOR 0 VDIG*/ + qcom,mode = <1>; /* Output */ + qcom,pull = <5>; /* No Pull */ + qcom,vin-sel = <0>; /* VIN1 GPIO_LV */ + qcom,src-sel = <0>; /* GPIO */ + qcom,invert = <0>; /* Invert */ + qcom,master-en = <1>; /* Enable GPIO */ + status = "ok"; + }; + + gpio@c200 { /* GPIO3 -CAMERA SENSOR 2 VDIG*/ + qcom,mode = <1>; /* Output */ + qcom,pull = <5>; /* No Pull */ + qcom,vin-sel = <0>; /* VIN1 GPIO_LV */ + qcom,src-sel = <0>; /* GPIO */ + qcom,invert = <0>; /* Invert */ + qcom,master-en = <1>; /* Enable GPIO */ + status = "ok"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-camera-sensor-mtp.dtsi b/arch/arm/boot/dts/qcom/sdm660-camera-sensor-mtp.dtsi new file mode 100644 index 000000000000..416cd99a81cb --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-camera-sensor-mtp.dtsi @@ -0,0 +1,384 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + led_flash0: qcom,camera-flash@0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + qcom,flash-source = <&pm660l_flash0 &pm660l_flash1>; + qcom,torch-source = <&pm660l_torch0 &pm660l_torch1>; + qcom,switch-source = <&pm660l_switch0>; + status = "ok"; + }; + + led_flash1: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + qcom,flash-source = <&pm660l_flash2>; + qcom,torch-source = <&pm660l_torch2>; + qcom,switch-source = <&pm660l_switch1>; + status = "ok"; + }; +}; + +&cci { + actuator0: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + gpios = <&tlmm 50 0>; + qcom,gpio-vaf = <0>; + qcom,gpio-req-tbl-num = <0>; + qcom,gpio-req-tbl-flags = <0>; + qcom,gpio-req-tbl-label = "CAM_VAF"; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_actuator_vaf_active>; + pinctrl-1 = <&cam_actuator_vaf_suspend>; + }; + + actuator1: qcom,actuator@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,actuator"; + qcom,cci-master = <1>; + gpios = <&tlmm 50 0>; + qcom,gpio-vaf = <0>; + qcom,gpio-req-tbl-num = <0>; + qcom,gpio-req-tbl-flags = <0>; + qcom,gpio-req-tbl-label = "CAM_VAF"; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_actuator_vaf_active>; + pinctrl-1 = <&cam_actuator_vaf_suspend>; + }; + + actuator2: qcom,actuator@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,actuator"; + qcom,cci-master = <1>; + gpios = <&tlmm 50 0>; + qcom,gpio-vaf = <0>; + qcom,gpio-req-tbl-num = <0>; + qcom,gpio-req-tbl-flags = <0>; + qcom,gpio-req-tbl-label = "CAM_VAF"; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_actuator_vaf_active>; + pinctrl-1 = <&cam_actuator_vaf_suspend>; + }; + + ois0: qcom,ois@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,ois"; + qcom,cci-master = <0>; + gpios = <&tlmm 50 0>; + qcom,gpio-vaf = <0>; + qcom,gpio-req-tbl-num = <0>; + qcom,gpio-req-tbl-flags = <0>; + qcom,gpio-req-tbl-label = "CAM_VAF"; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_actuator_vaf_active>; + pinctrl-1 = <&cam_actuator_vaf_suspend>; + status = "disabled"; + }; + + eeprom0: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active + &cam_actuator_vaf_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend + &cam_actuator_vaf_suspend>; + gpios = <&tlmm 32 0>, + <&tlmm 46 0>, + <&pm660l_gpios 4 0>, + <&tlmm 51 0>, + <&tlmm 50 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-vaf = <4>; + qcom,gpio-req-tbl-num = <0 1 2 3 4>; + qcom,gpio-req-tbl-flags = <1 0 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VDIG", + "CAM_VANA", + "CAM_VAF"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&clock_mmss MCLK0_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK0_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + eeprom1: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 34 0>, + <&tlmm 48 0>, + <&pm660l_gpios 3 0>, + <&tlmm 51 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-req-tbl-num = <0 1 2 3>; + qcom,gpio-req-tbl-flags = <1 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET", + "CAM_VDIG", + "CAM_VANA"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_mmss MCLK2_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + eeprom2: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_front_active + &cam_actuator_vaf_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_front_suspend + &cam_actuator_vaf_suspend>; + gpios = <&tlmm 33 0>, + <&tlmm 47 0>, + <&pm660_gpios 3 0>, + <&tlmm 44 0>, + <&tlmm 50 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-vaf = <4>; + qcom,gpio-req-tbl-num = <0 1 2 3 4>; + qcom,gpio-req-tbl-flags = <1 0 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VDIG", + "CAM_VANA", + "CAM_VAF"; + qcom,sensor-position = <1>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_mmss MCLK1_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK1_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@0 { + cell-index = <0>; + compatible = "qcom,camera"; + reg = <0x0>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <270>; + qcom,led-flash-src = <&led_flash0>; + qcom,actuator-src = <&actuator0>; + qcom,ois-src = <&ois0>; + qcom,eeprom-src = <&eeprom0>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 32 0>, + <&tlmm 46 0>, + <&pm660l_gpios 4 0>, + <&tlmm 51 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-req-tbl-num = <0 1 2 3>; + qcom,gpio-req-tbl-flags = <1 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VDIG", + "CAM_VANA"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&clock_mmss MCLK0_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK0_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@1 { + cell-index = <1>; + compatible = "qcom,camera"; + reg = <0x1>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <2>; + qcom,mount-angle = <90>; + qcom,actuator-src = <&actuator1>; + qcom,eeprom-src = <&eeprom1>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 34 0>, + <&tlmm 48 0>, + <&pm660l_gpios 3 0>, + <&tlmm 51 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-req-tbl-num = <0 1 2 3>; + qcom,gpio-req-tbl-flags = <1 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET", + "CAM_VDIG", + "CAM_VANA"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_mmss MCLK2_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@2 { + cell-index = <2>; + compatible = "qcom,camera"; + reg = <0x02>; + qcom,csiphy-sd-index = <2>; + qcom,csid-sd-index = <2>; + qcom,mount-angle = <90>; + qcom,actuator-src = <&actuator2>; + qcom,eeprom-src = <&eeprom2>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 33 0>, + <&tlmm 47 0>, + <&pm660l_gpios 3 0>, + <&tlmm 51 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-req-tbl-num = <0 1 2 3>; + qcom,gpio-req-tbl-flags = <1 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VDIG", + "CAM_VANA"; + qcom,sensor-position = <1>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_mmss MCLK1_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK1_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; +}; + +&pm660l_gpios { + gpio@c300 { /* GPIO4 -CAMERA SENSOR 0 VDIG*/ + qcom,mode = <1>; /* Output */ + qcom,pull = <5>; /* No Pull */ + qcom,vin-sel = <0>; /* VIN1 GPIO_LV */ + qcom,src-sel = <0>; /* GPIO */ + qcom,invert = <0>; /* Invert */ + qcom,master-en = <1>; /* Enable GPIO */ + status = "ok"; + }; + + gpio@c200 { /* GPIO3 -CAMERA SENSOR 2 VDIG*/ + qcom,mode = <1>; /* Output */ + qcom,pull = <5>; /* No Pull */ + qcom,vin-sel = <0>; /* VIN1 GPIO_LV */ + qcom,src-sel = <0>; /* GPIO */ + qcom,invert = <0>; /* Invert */ + qcom,master-en = <1>; /* Enable GPIO */ + status = "ok"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-camera.dtsi b/arch/arm/boot/dts/qcom/sdm660-camera.dtsi new file mode 100644 index 000000000000..09f5bec8ca62 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-camera.dtsi @@ -0,0 +1,850 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,msm-cam@8c0000 { + compatible = "qcom,msm-cam"; + reg = <0x8c0000 0x40000>; + reg-names = "msm-cam"; + status = "ok"; + bus-vectors = "suspend", "svs", "nominal", "turbo"; + qcom,bus-votes = <0 300000000 640000000 640000000>; + }; + + qcom,csiphy@c824000 { + cell-index = <0>; + compatible = "qcom,csiphy-v3.5", "qcom,csiphy"; + reg = <0xc824000 0x1000>; + reg-names = "csiphy"; + interrupts = <0 78 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&gdsc_camss_top>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "gdscr", "bimc_smmu"; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss CSI0_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI0_CLK>, + <&clock_mmss MMSS_CAMSS_CPHY_CSID0_CLK>, + <&clock_mmss CSI0PHYTIMER_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI0PHYTIMER_CLK>, + <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, + <&clock_mmss CSIPHY_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSIPHY0_CLK>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "csi_src_clk", "csi_clk", "cphy_csid_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; + qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0 + 0 384000000 0>; + status = "ok"; + }; + + qcom,csiphy@c825000 { + cell-index = <1>; + compatible = "qcom,csiphy-v3.5", "qcom,csiphy"; + reg = <0xc825000 0x1000>; + reg-names = "csiphy"; + interrupts = <0 79 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&gdsc_camss_top>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "gdscr", "bimc_smmu"; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss CSI1_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI1_CLK>, + <&clock_mmss MMSS_CAMSS_CPHY_CSID1_CLK>, + <&clock_mmss CSI1PHYTIMER_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI1PHYTIMER_CLK>, + <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, + <&clock_mmss CSIPHY_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSIPHY1_CLK>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "csi_src_clk", "csi_clk", "cphy_csid_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; + qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0 + 0 384000000 0>; + status = "ok"; + }; + + qcom,csiphy@c826000 { + cell-index = <2>; + compatible = "qcom,csiphy-v3.5", "qcom,csiphy"; + reg = <0xc826000 0x1000>; + reg-names = "csiphy"; + interrupts = <0 80 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&gdsc_camss_top>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "gdscr", "bimc_smmu"; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss CSI0_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI2_CLK>, + <&clock_mmss MMSS_CAMSS_CPHY_CSID2_CLK>, + <&clock_mmss CSI2PHYTIMER_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI2PHYTIMER_CLK>, + <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, + <&clock_mmss CSIPHY_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSIPHY2_CLK>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "csi_src_clk", "csi_clk", "cphy_csid_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; + qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0 + 0 384000000 0>; + status = "ok"; + }; + + qcom,csid@ca30000 { + cell-index = <0>; + compatible = "qcom,csid-v5.0", "qcom,csid"; + reg = <0xca30000 0x400>; + reg-names = "csid"; + interrupts = <0 296 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; + gdscr-supply = <&gdsc_camss_top>; + vdd_sec-supply = <&pm660l_l1>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + qcom,cam-vreg-min-voltage = <925000 0 0>; + qcom,cam-vreg-max-voltage = <925000 0 0>; + qcom,cam-vreg-op-mode = <0 0 0>; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, + <&clock_mmss CSI0_CLK_SRC>, + <&clock_mmss CSIPHY_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI0_CLK>, + <&clock_mmss MMSS_CAMSS_CSI0_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_CSI0RDI_CLK>, + <&clock_mmss MMSS_CAMSS_CSI0PIX_CLK>, + <&clock_mmss MMSS_CAMSS_CPHY_CSID0_CLK>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", + "csi_clk", "csi_ahb_clk", "csi_rdi_clk", + "csi_pix_clk", "cphy_csid_clk"; + qcom,clock-rates = <0 0 0 0 0 0 0 384000000 384000000 + 0 0 0 0 0>; + status = "ok"; + }; + + qcom,csid@ca30400 { + cell-index = <1>; + compatible = "qcom,csid-v5.0", "qcom,csid"; + reg = <0xca30400 0x400>; + reg-names = "csid"; + interrupts = <0 297 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; + gdscr-supply = <&gdsc_camss_top>; + vdd_sec-supply = <&pm660l_l1>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + qcom,cam-vreg-min-voltage = <925000 0 0>; + qcom,cam-vreg-max-voltage = <925000 0 0>; + qcom,cam-vreg-op-mode = <0 0 0>; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, + <&clock_mmss CSI1_CLK_SRC>, + <&clock_mmss CSIPHY_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI1_CLK>, + <&clock_mmss MMSS_CAMSS_CSI1_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_CSI1RDI_CLK>, + <&clock_mmss MMSS_CAMSS_CSI1PIX_CLK>, + <&clock_mmss MMSS_CAMSS_CPHY_CSID1_CLK>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", + "csi_clk", "csi_ahb_clk", "csi_rdi_clk", + "csi_pix_clk", "cphy_csid_clk"; + qcom,clock-rates = <0 0 0 0 0 0 0 256000000 256000000 + 0 0 0 0 0>; + status = "ok"; + }; + + qcom,csid@ca30800 { + cell-index = <2>; + compatible = "qcom,csid-v5.0", "qcom,csid"; + reg = <0xca30800 0x400>; + reg-names = "csid"; + interrupts = <0 298 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; + gdscr-supply = <&gdsc_camss_top>; + vdd_sec-supply = <&pm660l_l1>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + qcom,cam-vreg-min-voltage = <925000 0 0>; + qcom,cam-vreg-max-voltage = <925000 0 0>; + qcom,cam-vreg-op-mode = <0 0 0>; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, + <&clock_mmss CSI2_CLK_SRC>, + <&clock_mmss CSIPHY_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI2_CLK>, + <&clock_mmss MMSS_CAMSS_CSI2_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_CSI2RDI_CLK>, + <&clock_mmss MMSS_CAMSS_CSI2PIX_CLK>, + <&clock_mmss MMSS_CAMSS_CPHY_CSID2_CLK>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", + "csi_clk", "csi_ahb_clk", "csi_rdi_clk", + "csi_pix_clk", "cphy_csid_clk"; + qcom,clock-rates = <0 0 0 0 0 0 0 256000000 256000000 + 0 0 0 0 0>; + status = "ok"; + }; + + qcom,csid@ca30c00 { + cell-index = <3>; + compatible = "qcom,csid-v5.0", "qcom,csid"; + reg = <0xca30c00 0x400>; + reg-names = "csid"; + interrupts = <0 299 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; + gdscr-supply = <&gdsc_camss_top>; + vdd_sec-supply = <&pm660l_l1>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + qcom,cam-vreg-min-voltage = <925000 0 0>; + qcom,cam-vreg-max-voltage = <925000 0 0>; + qcom,cam-vreg-op-mode = <0 0 0>; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, + <&clock_mmss CSI3_CLK_SRC>, + <&clock_mmss CSIPHY_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI3_CLK>, + <&clock_mmss MMSS_CAMSS_CSI3_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_CSI3RDI_CLK>, + <&clock_mmss MMSS_CAMSS_CSI3PIX_CLK>, + <&clock_mmss MMSS_CAMSS_CPHY_CSID3_CLK>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", + "csi_clk", "csi_ahb_clk", "csi_rdi_clk", + "csi_pix_clk", "cphy_csid_clk"; + qcom,clock-rates = <0 0 0 0 0 0 0 256000000 256000000 + 0 0 0 0 0>; + status = "ok"; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu"; + status = "ok"; + + msm_cam_smmu_cb1 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&mmss_bimc_smmu 0xc00>, + <&mmss_bimc_smmu 0xc01>, + <&mmss_bimc_smmu 0xc02>, + <&mmss_bimc_smmu 0xc03>; + label = "vfe"; + qcom,scratch-buf-support; + }; + + msm_cam_smmu_cb2 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&mmss_bimc_smmu 0xa00>; + label = "cpp"; + }; + + msm_cam_smmu_cb3 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&mmss_bimc_smmu 0xa01>; + label = "camera_fd"; + }; + + msm_cam_smmu_cb4 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&mmss_bimc_smmu 0x800>; + label = "jpeg_enc0"; + }; + + msm_cam_smmu_cb5 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&mmss_bimc_smmu 0x801>; + label = "jpeg_dma"; + }; + }; + + qcom,cpp@ca04000 { + cell-index = <0>; + compatible = "qcom,cpp"; + reg = <0xca04000 0x100>, + <0xca80000 0x3000>, + <0xca18000 0x3000>, + <0xc8c36D4 0x4>; + reg-names = "cpp", "cpp_vbif", "cpp_hw", "camss_cpp"; + interrupts = <0 294 0>; + interrupt-names = "cpp"; + smmu-vdd-supply = <&gdsc_bimc_smmu>; + camss-vdd-supply = <&gdsc_camss_top>; + vdd-supply = <&gdsc_cpp>; + qcom,vdd-names = "smmu-vdd", "camss-vdd", "vdd"; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss CPP_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CPP_CLK>, + <&clock_mmss MMSS_CAMSS_CPP_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_CPP_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_MICRO_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_CPP_VBIF_AHB_CLK>; + clock-names = "mmssnoc_axi_clk", + "mnoc_ahb_clk", + "camss_ahb_clk", "camss_top_ahb_clk", + "cpp_src_clk", + "cpp_core_clk", "camss_cpp_ahb_clk", + "camss_cpp_axi_clk", "micro_iface_clk", + "mmss_smmu_axi_clk", "cpp_vbif_ahb_clk"; + qcom,clock-rates = <0 0 0 0 200000000 200000000 0 0 0 0 0>; + qcom,min-clock-rate = <200000000>; + qcom,bus-master = <1>; + qcom,vbif-qos-setting = <0x20 0x10000000>, + <0x24 0x10000000>, + <0x28 0x10000000>, + <0x2C 0x10000000>; + status = "ok"; + qcom,msm-bus,name = "msm_camera_cpp"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <106 512 0 0>, + <106 512 0 0>; + qcom,msm-bus-vector-dyn-vote; + resets = <&clock_mmss CAMSS_MICRO_BCR>; + reset-names = "micro_iface_reset"; + qcom,src-clock-rates = <100000000 200000000 576000000 + 600000000>; + qcom,cpp-fw-payload-info { + qcom,stripe-base = <790>; + qcom,plane-base = <715>; + qcom,stripe-size = <63>; + qcom,plane-size = <25>; + qcom,fe-ptr-off = <11>; + qcom,we-ptr-off = <23>; + qcom,ref-fe-ptr-off = <17>; + qcom,ref-we-ptr-off = <36>; + qcom,we-meta-ptr-off = <42>; + qcom,fe-mmu-pf-ptr-off = <7>; + qcom,ref-fe-mmu-pf-ptr-off = <10>; + qcom,we-mmu-pf-ptr-off = <13>; + qcom,dup-we-mmu-pf-ptr-off = <18>; + qcom,ref-we-mmu-pf-ptr-off = <23>; + qcom,set-group-buffer-len = <135>; + qcom,dup-frame-indicator-off = <70>; + }; + }; + + qcom,ispif@ca31000 { + cell-index = <0>; + compatible = "qcom,ispif-v3.0", "qcom,ispif"; + reg = <0xca31000 0xc00>, + <0xca00020 0x4>; + reg-names = "ispif", "csi_clk_mux"; + interrupts = <0 309 0>; + interrupt-names = "ispif"; + qcom,num-isps = <0x2>; + camss-vdd-supply = <&gdsc_camss_top>; + vfe0-vdd-supply = <&gdsc_vfe0>; + vfe1-vdd-supply = <&gdsc_vfe1>; + qcom,vdd-names = "camss-vdd", "vfe0-vdd", + "vfe1-vdd"; + qcom,clock-cntl-support; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, + <&clock_mmss CSI0_CLK_SRC>, + <&clock_mmss CSI1_CLK_SRC>, + <&clock_mmss CSI2_CLK_SRC>, + <&clock_mmss CSI3_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI0RDI_CLK>, + <&clock_mmss MMSS_CAMSS_CSI1RDI_CLK>, + <&clock_mmss MMSS_CAMSS_CSI2RDI_CLK>, + <&clock_mmss MMSS_CAMSS_CSI3RDI_CLK>, + <&clock_mmss MMSS_CAMSS_CSI0PIX_CLK>, + <&clock_mmss MMSS_CAMSS_CSI1PIX_CLK>, + <&clock_mmss MMSS_CAMSS_CSI2PIX_CLK>, + <&clock_mmss MMSS_CAMSS_CSI3PIX_CLK>, + <&clock_mmss MMSS_CAMSS_CSI0_CLK>, + <&clock_mmss MMSS_CAMSS_CSI1_CLK>, + <&clock_mmss MMSS_CAMSS_CSI2_CLK>, + <&clock_mmss MMSS_CAMSS_CSI3_CLK>, + <&clock_mmss MMSS_CAMSS_VFE0_CLK>, + <&clock_mmss VFE0_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI_VFE0_CLK>, + <&clock_mmss MMSS_CAMSS_VFE1_CLK>, + <&clock_mmss VFE1_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI_VFE1_CLK>; + clock-names = "mmssnoc_axi", "mnoc_ahb_clk", + "camss_ahb_clk", + "camss_top_ahb_clk", "ispif_ahb_clk", + "csi0_src_clk", "csi1_src_clk", + "csi2_src_clk", "csi3_src_clk", + "csi0_rdi_clk", "csi1_rdi_clk", + "csi2_rdi_clk", "csi3_rdi_clk", + "csi0_pix_clk", "csi1_pix_clk", + "csi2_pix_clk", "csi3_pix_clk", + "camss_csi0_clk", "camss_csi1_clk", + "camss_csi2_clk", "camss_csi3_clk", + "camss_vfe_vfe0_clk", + "vfe0_clk_src", "camss_csi_vfe0_clk", + "camss_vfe_vfe1_clk", + "vfe1_clk_src", "camss_csi_vfe1_clk"; + qcom,clock-rates = <0 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 + 0 0 0>; + qcom,clock-control = "INIT_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", + "INIT_RATE", "INIT_RATE", + "INIT_RATE", "INIT_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", + "INIT_RATE", "NO_SET_RATE", + "NO_SET_RATE", + "INIT_RATE", "NO_SET_RATE"; + status = "ok"; + }; + + vfe0: qcom,vfe0@ca10000 { + cell-index = <0>; + compatible = "qcom,vfe48"; + reg = <0xca10000 0x4000>, + <0xca40000 0x3000>; + reg-names = "vfe", "vfe_vbif"; + interrupts = <0 314 0>; + interrupt-names = "vfe"; + vdd-supply = <&gdsc_vfe0>; + camss-vdd-supply = <&gdsc_camss_top>; + smmu-vdd-supply = <&gdsc_bimc_smmu>; + qcom,vdd-names = "vdd", "camss-vdd", "smmu-vdd"; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_VFE0_CLK>, + <&clock_mmss MMSS_CAMSS_VFE0_STREAM_CLK>, + <&clock_mmss MMSS_CAMSS_VFE0_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_VFE_VBIF_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_VFE_VBIF_AXI_CLK>, + <&clock_mmss VFE0_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI_VFE0_CLK>; + clock-names = "mmssnoc_axi", "mnoc_ahb_clk", + "bimc_smmu_ahb_clk", "bimc_smmu_axi_clk", + "camss_ahb_clk", "camss_top_ahb_clk", + "camss_vfe_clk", "camss_vfe_stream_clk", + "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk", + "camss_vfe_vbif_axi_clk", "vfe_clk_src", + "camss_csi_vfe_clk"; + qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 384000000 0 + 0 0 0 0 0 0 0 0 0 0 0 576000000 0 + 0 0 0 0 0 0 0 0 0 0 0 600000000 0>; + status = "ok"; + qos-entries = <8>; + qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 + 0x41c 0x420>; + qos-settings = <0xaaa5aaa5 + 0xaaa5aaa5 + 0xaaa5aaa5 + 0xaa55aaa5 + 0xaa55aa55 + 0xaa55aa55 + 0xaa55aa55 + 0x0005aa55>; + vbif-entries = <3>; + vbif-regs = <0x124 0xac 0xd0>; + vbif-settings = <0x3 0x40 0x1010>; + ds-entries = <17>; + ds-regs = <0x424 0x428 0x42c 0x430 0x434 + 0x438 0x43c 0x440 0x444 0x448 0x44c + 0x450 0x454 0x458 0x45c 0x460 0x464>; + ds-settings = <0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0x110>; + qcom,msm-bus,name = "msm_camera_vfe"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <29 512 0 0>, + <29 512 100000000 100000000>; + qcom,msm-bus-vector-dyn-vote; + }; + + vfe1: qcom,vfe1@ca14000 { + cell-index = <1>; + compatible = "qcom,vfe48"; + reg = <0xca14000 0x4000>, + <0xca40000 0x3000>; + reg-names = "vfe", "vfe_vbif"; + interrupts = <0 315 0>; + interrupt-names = "vfe"; + vdd-supply = <&gdsc_vfe1>; + camss-vdd-supply = <&gdsc_camss_top>; + smmu-vdd-supply = <&gdsc_bimc_smmu>; + qcom,vdd-names = "vdd", "camss-vdd", "smmu-vdd"; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_VFE1_CLK>, + <&clock_mmss MMSS_CAMSS_VFE1_STREAM_CLK>, + <&clock_mmss MMSS_CAMSS_VFE1_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_VFE_VBIF_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_VFE_VBIF_AXI_CLK>, + <&clock_mmss VFE1_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI_VFE1_CLK>; + clock-names = "mmssnoc_axi", "mnoc_ahb_clk", + "bimc_smmu_ahb_clk", "bimc_smmu_axi_clk", + "camss_ahb_clk", "camss_top_ahb_clk", + "camss_vfe_clk", "camss_vfe_stream_clk", + "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk", + "camss_vfe_vbif_axi_clk", "vfe_clk_src", + "camss_csi_vfe_clk"; + qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 384000000 0 + 0 0 0 0 0 0 0 0 0 0 0 576000000 0 + 0 0 0 0 0 0 0 0 0 0 0 600000000 0>; + status = "ok"; + qos-entries = <8>; + qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 + 0x41c 0x420>; + qos-settings = <0xaaa5aaa5 + 0xaaa5aaa5 + 0xaaa5aaa5 + 0xaa55aaa5 + 0xaa55aa55 + 0xaa55aa55 + 0xaa55aa55 + 0x0005aa55>; + vbif-entries = <3>; + vbif-regs = <0x124 0xac 0xd0>; + vbif-settings = <0x3 0x40 0x1010>; + ds-entries = <17>; + ds-regs = <0x424 0x428 0x42c 0x430 0x434 + 0x438 0x43c 0x440 0x444 0x448 0x44c + 0x450 0x454 0x458 0x45c 0x460 0x464>; + ds-settings = <0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0x110>; + qcom,msm-bus,name = "msm_camera_vfe"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <29 512 0 0>, + <29 512 100000000 100000000>; + qcom,msm-bus-vector-dyn-vote; + }; + + qcom,vfe { + compatible = "qcom,vfe"; + num_child = <2>; + }; + + cci: qcom,cci@ca0c000 { + cell-index = <0>; + compatible = "qcom,cci"; + reg = <0xca0c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "cci"; + interrupts = <0 295 0>; + interrupt-names = "cci"; + status = "ok"; + mmagic-supply = <&gdsc_bimc_smmu>; + gdscr-supply = <&gdsc_camss_top>; + qcom,cam-vreg-name = "mmagic", "gdscr"; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss CCI_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CCI_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_CCI_CLK>; + clock-names = "mmssnoc_axi", "mnoc_ahb", "smmu_ahb", "smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "cci_src_clk", "cci_ahb_clk", "camss_cci_clk"; + qcom,clock-rates = <0 0 0 0 0 0 19200000 0 0>, + <0 0 0 0 0 0 37500000 0 0>; + pinctrl-names = "cci_default", "cci_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 36 0>, + <&tlmm 37 0>, + <&tlmm 38 0>, + <&tlmm 39 0>; + qcom,gpio-tbl-num = <0 1 2 3>; + qcom,gpio-tbl-flags = <1 1 1 1>; + qcom,gpio-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + i2c_freq_100Khz: qcom,i2c_standard_mode { + status = "disabled"; + }; + i2c_freq_400Khz: qcom,i2c_fast_mode { + status = "disabled"; + }; + i2c_freq_custom: qcom,i2c_custom_mode { + status = "disabled"; + }; + i2c_freq_1Mhz: qcom,i2c_fast_plus_mode { + status = "disabled"; + }; + }; + + qcom,jpeg@ca1c000 { + cell-index = <0>; + compatible = "qcom,jpeg"; + reg = <0xca1c000 0x4000>, + <0xca60000 0x3000>; + reg-names = "jpeg_hw", "jpeg_vbif"; + interrupts = <0 316 0>; + interrupt-names = "jpeg"; + smmu-vdd-supply = <&gdsc_bimc_smmu>; + camss-vdd-supply = <&gdsc_camss_top>; + qcom,vdd-names = "smmu-vdd", "camss-vdd"; + clock-names = "mmssnoc_axi", + "mmss_mnoc_ahb_clk", + "mmss_bimc_smmu_ahb_clk", + "mmss_bimc_smmu_axi_clk", + "mmss_camss_ahb_clk", + "mmss_camss_top_ahb_clk", + "core_clk", + "mmss_camss_jpeg_ahb_clk", + "mmss_camss_jpeg_axi_clk"; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_JPEG0_CLK>, + <&clock_mmss MMSS_CAMSS_JPEG_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_JPEG_AXI_CLK >; + qcom,clock-rates = <0 0 0 0 0 0 480000000 0 0>; + qcom,vbif-reg-settings = <0x4 0x1>; + qcom,prefetch-reg-settings = <0x30c 0x1111>, + <0x318 0x31>, + <0x324 0x31>, + <0x330 0x31>, + <0x33c 0x0>; + qcom,msm-bus,name = "msm_camera_jpeg0"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <62 512 0 0>, + <62 512 1920000 2880000>; + status = "ok"; + }; + + qcom,jpeg@caa0000 { + cell-index = <3>; + compatible = "qcom,jpegdma"; + reg = <0xcaa0000 0x4000>, + <0xca60000 0x3000>; + reg-names = "jpeg_hw", "jpeg_vbif"; + interrupts = <0 304 0>; + interrupt-names = "jpeg"; + smmu-vdd-supply = <&gdsc_bimc_smmu>; + camss-vdd-supply = <&gdsc_camss_top>; + qcom,vdd-names = "smmu-vdd", "camss-vdd"; + clock-names = "mmssnoc_axi", + "mmss_mnoc_ahb_clk", + "mmss_bimc_smmu_ahb_clk", + "mmss_bimc_smmu_axi_clk", + "mmss_camss_ahb_clk", + "mmss_camss_top_ahb_clk", + "core_clk", + "mmss_camss_jpeg_ahb_clk", + "mmss_camss_jpeg_axi_clk"; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_JPEG0_CLK>, + <&clock_mmss MMSS_CAMSS_JPEG_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_JPEG_AXI_CLK>; + qcom,clock-rates = <0 0 0 0 0 0 480000000 0 0>; + qcom,vbif-reg-settings = <0x4 0x1>; + qcom,prefetch-reg-settings = <0x18c 0x11>, + <0x1a0 0x31>, + <0x1b0 0x31>; + qcom,msm-bus,name = "msm_camera_jpeg_dma"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <62 512 0 0>, + <62 512 1920000 2880000>; + qcom,max-ds-factor = <128>; + status = "ok"; + }; +}; + +&i2c_freq_100Khz { + qcom,hw-thigh = <201>; + qcom,hw-tlow = <174>; + qcom,hw-tsu-sto = <204>; + qcom,hw-tsu-sta = <231>; + qcom,hw-thd-dat = <22>; + qcom,hw-thd-sta = <162>; + qcom,hw-tbuf = <227>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; + +&i2c_freq_400Khz { + qcom,hw-thigh = <38>; + qcom,hw-tlow = <56>; + qcom,hw-tsu-sto = <40>; + qcom,hw-tsu-sta = <40>; + qcom,hw-thd-dat = <22>; + qcom,hw-thd-sta = <35>; + qcom,hw-tbuf = <62>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; + +&i2c_freq_custom { + qcom,hw-thigh = <38>; + qcom,hw-tlow = <56>; + qcom,hw-tsu-sto = <40>; + qcom,hw-tsu-sta = <40>; + qcom,hw-thd-dat = <22>; + qcom,hw-thd-sta = <35>; + qcom,hw-tbuf = <62>; + qcom,hw-scl-stretch-en = <1>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; + +&i2c_freq_1Mhz { + qcom,hw-thigh = <16>; + qcom,hw-tlow = <22>; + qcom,hw-tsu-sto = <17>; + qcom,hw-tsu-sta = <18>; + qcom,hw-thd-dat = <16>; + qcom,hw-thd-sta = <15>; + qcom,hw-tbuf = <24>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <3>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-cdp.dts b/arch/arm/boot/dts/qcom/sdm660-cdp.dts new file mode 100644 index 000000000000..8d338660a14a --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-cdp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L CDP"; + compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp"; + qcom,board-id = <1 0>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-cdp.dtsi b/arch/arm/boot/dts/qcom/sdm660-cdp.dtsi new file mode 100644 index 000000000000..8304f3386c8a --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-cdp.dtsi @@ -0,0 +1,95 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdm660-pinctrl.dtsi" +#include "sdm660-camera-sensor-cdp.dtsi" +/ { +}; + +&uartblsp1dm1 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&ufsphy1 { + vdda-phy-supply = <&pm660l_l1>; + vdda-pll-supply = <&pm660_l10>; + vddp-ref-clk-supply = <&pm660_l1>; + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14200>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; + status = "ok"; +}; + +&ufs1 { + vdd-hba-supply = <&gdsc_ufs>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm660l_l4>; + vccq2-supply = <&pm660_l8>; + vcc-max-microamp = <500000>; + vccq2-max-microamp = <600000>; + status = "ok"; +}; + +&mdss_mdp { + qcom,mdss-pref-prim-intf = "dsi"; +}; + +&mdss_dsi { + hw-config = "split_dsi"; +}; + +&mdss_dsi0 { + qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; + pinctrl-names = "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; + pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; + qcom,platform-reset-gpio = <&tlmm 53 0>; + qcom,platform-te-gpio = <&tlmm 59 0>; +}; + +&mdss_dsi1 { + qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; + pinctrl-names = "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; + pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; + qcom,platform-reset-gpio = <&tlmm 53 0>; + qcom,platform-te-gpio = <&tlmm 59 0>; +}; + +&pm660l_wled { + qcom,led-strings-list = [01 02]; +}; + +&dsi_dual_nt35597_truly_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&soc { + qcom,msm-ssc-sensors { + compatible = "qcom,msm-ssc-sensors"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-common.dtsi b/arch/arm/boot/dts/qcom/sdm660-common.dtsi new file mode 100644 index 000000000000..a6bc326a6508 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-common.dtsi @@ -0,0 +1,324 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + usb3: ssusb@a800000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0a800000 0xfc100>, + <0x0c016000 0x400>; + reg-names = "core_base", + "ahb2phy_base"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = <0 347 0>, <0 243 0>, <0 180 0>; + interrupt-names = "hs_phy_irq", "ss_phy_irq", "pwr_event_irq"; + + USB3_GDSC-supply = <&gdsc_usb30>; + + qcom,usb-dbm = <&dbm_1p5>; + qcom,msm-bus,name = "usb3"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <61 512 0 0>, + <61 512 240000 800000>; + + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + extcon = <&pm660_pdphy>; + qcom,pm-qos-latency = <41>; /* CPU-CLUSTER-WFI-LVL latency +1 */ + + clocks = <&clock_gcc GCC_USB30_MASTER_CLK>, + <&clock_gcc GCC_CFG_NOC_USB3_AXI_CLK>, + <&clock_gcc GCC_AGGRE2_USB3_AXI_CLK>, + <&clock_rpmcc RPM_AGGR2_NOC_CLK>, + <&clock_gcc GCC_USB30_MOCK_UTMI_CLK>, + <&clock_gcc GCC_USB30_SLEEP_CLK>, + <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&clock_rpmcc CXO_DWC3_CLK>; + + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "noc_aggr_clk", "utmi_clk", "sleep_clk", + "cfg_ahb_clk", "xo"; + + qcom,core-clk-rate = <133330000>; + + resets = <&clock_gcc GCC_USB_30_BCR>; + reset-names = "core_reset"; + + dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0x0a800000 0xc8d0>; + interrupt-parent = <&intc>; + interrupts = <0 131 0>; + usb-phy = <&qusb_phy0>, <&ssphy>; + tx-fifo-resize; + snps,nominal-elastic-buffer; + snps,disable-clk-gating; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + }; + + qcom,usbbam@a904000 { + compatible = "qcom,usb-bam-msm"; + reg = <0x0a904000 0x17000>; + interrupt-parent = <&intc>; + interrupts = <0 132 0>; + + qcom,bam-type = <0>; + qcom,usb-bam-fifo-baseaddr = <0x146bb000>; + qcom,usb-bam-num-pipes = <8>; + qcom,ignore-core-reset-ack; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "ssusb-ipa-out-0"; + qcom,usb-bam-mem-type = <1>; + qcom,dir = <0>; + qcom,pipe-num = <0>; + qcom,peer-bam = <1>; + qcom,src-bam-pipe-index = <1>; + qcom,data-fifo-size = <0x8000>; + qcom,descriptor-fifo-size = <0x2000>; + }; + qcom,pipe1 { + label = "ssusb-ipa-in-0"; + qcom,usb-bam-mem-type = <1>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <1>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-size = <0x8000>; + qcom,descriptor-fifo-size = <0x2000>; + }; + qcom,pipe2 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x06064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <2>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + qcom,pipe3 { + label = "ssusb-dpl-ipa-in-1"; + qcom,usb-bam-mem-type = <1>; + qcom,dir = <1>; + qcom,pipe-num = <1>; + qcom,peer-bam = <1>; + qcom,dst-bam-pipe-index = <2>; + qcom,data-fifo-size = <0x8000>; + qcom,descriptor-fifo-size = <0x2000>; + }; + }; + }; + + qusb_phy0: qusb@c012000 { + compatible = "qcom,qusb2phy"; + reg = <0x0c012000 0x180>, + <0x01fcb24c 0x4>, + <0x00188018 0x4>; + reg-names = "qusb_phy_base", + "tcsr_clamp_dig_n_1p8", + "ref_clk_addr"; + vdd-supply = <&pm660l_l1>; + vdda18-supply = <&pm660_l10>; + vdda33-supply = <&pm660l_l7>; + qcom,vdd-voltage-level = <0 925000 925000>; + qcom,qusb-phy-init-seq = <0xf8 0x80 + 0xb3 0x84 + 0x83 0x88 + 0xc0 0x8c + 0x30 0x08 + 0x79 0x0c + 0x21 0x10 + 0x14 0x9c + 0x9f 0x1c + 0x00 0x18>; + phy_type= "utmi"; + qcom,phy-clk-scheme = "cml"; + qcom,major-rev = <1>; + + clocks = <&clock_rpmcc RPM_LN_BB_CLK1>, + <&clock_gcc GCC_RX0_USB2_CLKREF_CLK>, + <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; + + clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk"; + + resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + ssphy: ssphy@c010000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0xc010000 0xe18>, + <0x01fcb244 0x4>, + <0x01fcb248 0x4>; + reg-names = "qmp_phy_base", + "vls_clamp_reg", + "tcsr_usb3_dp_phymode"; + vdd-supply = <&pm660l_l1>; + core-supply = <&pm660_l10>; + qcom,vdd-voltage-level = <0 925000 925000>; + vdd-core-voltage-level = <0 1800000 1800000>; + qcom,vbus-valid-override; + qcom,qmp-phy-init-seq = + /* */ + <0xac 0x14 0x00 + 0x34 0x08 0x00 + 0x174 0x30 0x00 + 0x3c 0x06 0x00 + 0xbc 0x00 0x00 + 0xc0 0x08 0x00 + 0x194 0x06 0x00 + 0x19c 0x01 0x00 + 0x178 0x00 0x00 + 0xd0 0x82 0x00 + 0xdc 0x55 0x00 + 0xe0 0x55 0x00 + 0xe4 0x03 0x00 + 0x78 0x0b 0x00 + 0x84 0x16 0x00 + 0x90 0x28 0x00 + 0x108 0x80 0x00 + 0x10c 0x00 0x00 + 0x184 0x0a 0x00 + 0x4c 0x15 0x00 + 0x50 0x34 0x00 + 0x54 0x00 0x00 + 0xc8 0x00 0x00 + 0x18c 0x00 0x00 + 0xcc 0x00 0x00 + 0x128 0x00 0x00 + 0x0c 0x0a 0x00 + 0x10 0x01 0x00 + 0x1c 0x31 0x00 + 0x20 0x01 0x00 + 0x14 0x00 0x00 + 0x18 0x00 0x00 + 0x24 0xde 0x00 + 0x28 0x07 0x00 + 0x48 0x0f 0x00 + 0x70 0x0f 0x00 + 0x100 0x80 0x00 + 0xa8 0x01 0x00 + 0x430 0x0b 0x00 + 0x830 0x0b 0x00 + 0x444 0x00 0x00 + 0x844 0x00 0x00 + 0x43c 0x00 0x00 + 0x83c 0x00 0x00 + 0x440 0x00 0x00 + 0x840 0x00 0x00 + 0x408 0x0a 0x00 + 0x808 0x0a 0x00 + 0x414 0x06 0x00 + 0x814 0x06 0x00 + 0x434 0x75 0x00 + 0x834 0x75 0x00 + 0x4d4 0x02 0x00 + 0x8d4 0x02 0x00 + 0x4d8 0x4e 0x00 + 0x8d8 0x4e 0x00 + 0x4dc 0x18 0x00 + 0x8dc 0x18 0x00 + 0x4f8 0x77 0x00 + 0x8f8 0x77 0x00 + 0x4fc 0x80 0x00 + 0x8fc 0x80 0x00 + 0x4c0 0x0a 0x00 + 0x8c0 0x0a 0x00 + 0x504 0x03 0x00 + 0x904 0x03 0x00 + 0x50c 0x16 0x00 + 0x90c 0x16 0x00 + 0x500 0x00 0x00 + 0x900 0x00 0x00 + 0x260 0x10 0x00 + 0x660 0x10 0x00 + 0x2a4 0x12 0x00 + 0x6a4 0x12 0x00 + 0x28c 0xc6 0x00 + 0x68c 0xc6 0x00 + 0x244 0x00 0x00 + 0x644 0x00 0x00 + 0x248 0x00 0x00 + 0x648 0x00 0x00 + 0xc0c 0x9f 0x00 + 0xc24 0x17 0x00 + 0xc28 0x0f 0x00 + 0xcc8 0x83 0x00 + 0xcc4 0x02 0x00 + 0xccc 0x09 0x00 + 0xcd0 0xa2 0x00 + 0xcd4 0x85 0x00 + 0xc80 0xd1 0x00 + 0xc84 0x1f 0x00 + 0xc88 0x47 0x00 + 0xcb8 0x75 0x00 + 0xcbc 0x13 0x00 + 0xcb0 0x86 0x00 + 0xca0 0x04 0x00 + 0xc8c 0x44 0x00 + 0xc70 0xe7 0x00 + 0xc74 0x03 0x00 + 0xc78 0x40 0x00 + 0xc7c 0x00 0x00 + 0xdd8 0x88 0x00 + 0xffffffff 0xffffffff 0x00>; + + qcom,qmp-phy-reg-offset = + <0xd74 /* USB3_PHY_PCS_STATUS */ + 0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */ + 0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */ + 0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */ + 0xc00 /* USB3_PHY_SW_RESET */ + 0xc08 /* USB3_PHY_START */ + 0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */ + + clocks = <&clock_gcc GCC_USB3_PHY_AUX_CLK>, + <&clock_gcc GCC_USB3_PHY_PIPE_CLK>, + <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&clock_rpmcc RPM_LN_BB_CLK1>, + <&clock_gcc GCC_USB3_CLKREF_CLK>; + + clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", + "ref_clk_src", "ref_clk"; + + resets = <&clock_gcc GCC_USB3_PHY_BCR>, + <&clock_gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&lpass_q6_smmu 6>; + qcom,usb-audio-stream-id = <6>; + qcom,usb-audio-intr-num = <2>; + }; + + dbm_1p5: dbm@a8f8000 { + compatible = "qcom,usb-dbm-1p5"; + reg = <0xa8f8000 0x300>; + qcom,reset-ep-after-lpm-resume; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-coresight.dtsi b/arch/arm/boot/dts/qcom/sdm660-coresight.dtsi new file mode 100644 index 000000000000..be625a15f4ec --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-coresight.dtsi @@ -0,0 +1,1849 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +&soc { + tmc_etr: tmc@6048000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b961>; + + reg = <0x6048000 0x1000>, + <0x6064000 0x15000>; + reg-names = "tmc-base", "bam-base"; + + arm,buffer-size = <0x400000>; + arm,sg-enable; + + coresight-ctis = <&cti0 &cti8>; + + coresight-name = "coresight-tmc-etr"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + tmc_etr_in_replicator: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_tmc_etr>; + }; + }; + }; + + replicator: replicator@6046000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b909>; + + reg = <0x6046000 0x1000>; + reg-names = "replicator-base"; + + coresight-name = "coresight-replicator"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + ports{ + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out_tmc_etr:endpoint { + remote-endpoint = + <&tmc_etr_in_replicator>; + }; + }; + port@1 { + reg = <0>; + replicator_in_tmc_etf:endpoint { + slave-mode; + remote-endpoint = + <&tmc_etf_out_replicator>; + }; + }; + }; + }; + + tmc_etf: tmc@6047000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b961>; + + reg = <0x6047000 0x1000>; + reg-names = "tmc-base"; + + coresight-name = "coresight-tmc-etf"; + + coresight-ctis = <&cti0 &cti8>; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + ports{ + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tmc_etf_out_replicator:endpoint { + remote-endpoint = + <&replicator_in_tmc_etf>; + }; + }; + port@1 { + reg = <0>; + tmc_etf_in_funnel_merg:endpoint { + slave-mode; + remote-endpoint = + <&funnel_merg_out_tmc_etf>; + }; + }; + }; + }; + + funnel_merg: funnel@6045000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6045000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-merg"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_merg_out_tmc_etf:endpoint { + remote-endpoint = + <&tmc_etf_in_funnel_merg>; + }; + }; + port@1 { + reg = <0>; + funnel_merg_in_funnel_in0:endpoint { + slave-mode; + remote-endpoint = + <&funnel_in0_out_funnel_merg>; + }; + }; + port@2 { + reg = <1>; + funnel_merg_in_funnel_in1:endpoint { + slave-mode; + remote-endpoint = + <&funnel_in1_out_funnel_merg>; + }; + }; + }; + }; + + funnel_in0: funnel@6041000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6041000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in0"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in0_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in0>; + }; + }; + port@2 { + reg = <6>; + funnel_in0_in_funnel_qatb: endpoint { + slave-mode; + remote-endpoint = + <&funnel_qatb_out_funnel_in0>; + }; + }; + port@3 { + reg = <7>; + funnel_in0_in_stm: endpoint { + slave-mode; + remote-endpoint = <&stm_out_funnel_in0>; + }; + }; + port@4 { + reg = <0>; + funnel_in0_in_rpm_etm0: endpoint { + slave-mode; + remote-endpoint = + <&rpm_etm0_out_funnel_in0>; + }; + }; + }; + }; + + funnel_in1: funnel@6042000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6042000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-in1"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_in1_out_funnel_merg: endpoint { + remote-endpoint = + <&funnel_merg_in_funnel_in1>; + }; + }; + port@1 { + reg = <2>; + funnel_in1_in_tpda_nav: endpoint { + slave-mode; + remote-endpoint = + <&tpda_nav_out_funnel_in1>; + }; + }; + port@2 { + reg = <5>; + funnel_in1_in_tpda_mss: endpoint { + slave-mode; + remote-endpoint = + <&tpda_mss_out_funnel_in1>; + }; + }; + port@3 { + reg = <6>; + funnel_in1_in_funnel_apss_merg: endpoint { + slave-mode; + remote-endpoint = + <&funnel_apss_merg_out_funnel_in1>; + }; + }; + port@4 { + reg = <4>; + funnel_in1_in_turing_etm0: endpoint { + slave-mode; + remote-endpoint = + <&turing_etm0_out_funnel_in1>; + }; + }; + }; + }; + + funnel_apss_merg: funnel@7b70000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x7b70000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss-merg"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_apss_merg_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_funnel_apss_merg>; + }; + }; + port@1 { + reg = <0>; + funnel_apss_merg_in_funnel_apss: endpoint { + slave-mode; + remote-endpoint = + <&funnel_apss_out_funnel_apss_merg>; + }; + }; + port@2 { + reg = <1>; + funnel_apss_merg_in_tpda_olc: endpoint { + slave-mode; + remote-endpoint = + <&tpda_olc_out_funnel_apss_merg>; + }; + }; + port@3 { + reg = <3>; + funnel_apss_merg_in_tpda_apss: endpoint { + slave-mode; + remote-endpoint = + <&tpda_apss_out_funnel_apss_merg>; + }; + }; + }; + }; + + funnel_apss: funnel@7b60000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x7b60000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-apss"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_apss_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_funnel_apss>; + }; + }; + port@1 { + reg = <0>; + funnel_apss_in_etm0: endpoint { + slave-mode; + remote-endpoint = + <&etm0_out_funnel_apss>; + }; + }; + port@2 { + reg = <1>; + funnel_apss_in_etm1: endpoint { + slave-mode; + remote-endpoint = + <&etm1_out_funnel_apss>; + }; + }; + port@3 { + reg = <2>; + funnel_apss_in_etm2: endpoint { + slave-mode; + remote-endpoint = + <&etm2_out_funnel_apss>; + }; + }; + port@4 { + reg = <3>; + funnel_apss_in_etm3: endpoint { + slave-mode; + remote-endpoint = + <&etm3_out_funnel_apss>; + }; + }; + port@5 { + reg = <4>; + funnel_apss_in_etm4: endpoint { + slave-mode; + remote-endpoint = + <&etm4_out_funnel_apss>; + }; + }; + port@6 { + reg = <5>; + funnel_apss_in_etm5: endpoint { + slave-mode; + remote-endpoint = + <&etm5_out_funnel_apss>; + }; + }; + port@7 { + reg = <6>; + funnel_apss_in_etm6: endpoint { + slave-mode; + remote-endpoint = + <&etm6_out_funnel_apss>; + }; + }; + port@8 { + reg = <7>; + funnel_apss_in_etm7: endpoint { + slave-mode; + remote-endpoint = + <&etm7_out_funnel_apss>; + }; + }; + }; + }; + + stm: stm@6002000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b962>; + + reg = <0x6002000 0x1000>, + <0x16280000 0x180000>; + reg-names = "stm-base", "stm-data-base"; + + coresight-name = "coresight-stm"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + stm_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_stm>; + }; + }; + }; + + etm0: etm@7840000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b95d>; + + reg = <0x7840000 0x1000>; + cpu = <&CPU0>; + + coresight-name = "coresight-etm0"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + etm0_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm0>; + }; + }; + }; + + etm1: etm@7940000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b95d>; + + reg = <0x7940000 0x1000>; + cpu = <&CPU1>; + + coresight-name = "coresight-etm1"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + etm1_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm1>; + }; + }; + }; + + etm2: etm@7a40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b95d>; + + reg = <0x7a40000 0x1000>; + cpu = <&CPU2>; + + coresight-name = "coresight-etm2"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + etm2_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm2>; + }; + }; + }; + + etm3: etm@7b40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b95d>; + + reg = <0x7b40000 0x1000>; + cpu = <&CPU3>; + + coresight-name = "coresight-etm3"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + etm3_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm3>; + }; + }; + }; + + etm4: etm@7c40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b95d>; + + reg = <0x7c40000 0x1000>; + cpu = <&CPU4>; + + coresight-name = "coresight-etm4"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + etm4_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm4>; + }; + }; + }; + + etm5: etm@7d40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b95d>; + + reg = <0x7d40000 0x1000>; + cpu = <&CPU5>; + + coresight-name = "coresight-etm5"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + etm5_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm5>; + }; + }; + }; + + etm6: etm@7e40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b95d>; + + reg = <0x7e40000 0x1000>; + cpu = <&CPU6>; + + coresight-name = "coresight-etm6"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + etm6_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm6>; + }; + }; + }; + + etm7: etm@7f40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b95d>; + + reg = <0x7f40000 0x1000>; + cpu = <&CPU7>; + + coresight-name = "coresight-etm7"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + etm7_out_funnel_apss: endpoint { + remote-endpoint = <&funnel_apss_in_etm7>; + }; + }; + }; + + cti0: cti@6010000 { + compatible = "arm,coresight-cti"; + reg = <0x6010000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti0"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti1: cti@6011000 { + compatible = "arm,coresight-cti"; + reg = <0x6011000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti1"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti2: cti@6012000 { + compatible = "arm,coresight-cti"; + reg = <0x6012000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti2"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + qcom,cti-gpio-trigout = <4>; + pinctrl-names = "cti-trigout-pctrl"; + pinctrl-0 = <&trigout_b>; + }; + + cti3: cti@6013000 { + compatible = "arm,coresight-cti"; + reg = <0x6013000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti3"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti4: cti@6014000 { + compatible = "arm,coresight-cti"; + reg = <0x6014000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti4"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti5: cti@6015000 { + compatible = "arm,coresight-cti"; + reg = <0x6015000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti5"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti6: cti@6016000 { + compatible = "arm,coresight-cti"; + reg = <0x6016000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti6"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti7: cti@6017000 { + compatible = "arm,coresight-cti"; + reg = <0x6017000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti7"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti8: cti@6018000 { + compatible = "arm,coresight-cti"; + reg = <0x6018000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti8"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti9: cti@6019000 { + compatible = "arm,coresight-cti"; + reg = <0x6019000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti9"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti10: cti@601a000 { + compatible = "arm,coresight-cti"; + reg = <0x601a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti10"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti11: cti@601b000 { + compatible = "arm,coresight-cti"; + reg = <0x601b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti11"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti12: cti@601c000 { + compatible = "arm,coresight-cti"; + reg = <0x601c000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti12"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti13: cti@601d000 { + compatible = "arm,coresight-cti"; + reg = <0x601d000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti13"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti14: cti@601e000 { + compatible = "arm,coresight-cti"; + reg = <0x601e000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti14"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti15: cti@601f000 { + compatible = "arm,coresight-cti"; + reg = <0x601f000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti15"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_cpu0: cti@7820000 { + compatible = "arm,coresight-cti"; + reg = <0x7820000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu0"; + cpu = <&CPU0>; + + qcom,cti-save; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_cpu1: cti@7920000 { + compatible = "arm,coresight-cti"; + reg = <0x7920000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu1"; + cpu = <&CPU1>; + + qcom,cti-save; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_cpu2: cti@7a20000 { + compatible = "arm,coresight-cti"; + reg = <0x7a20000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu2"; + cpu = <&CPU2>; + + qcom,cti-save; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_cpu3: cti@7b20000 { + compatible = "arm,coresight-cti"; + reg = <0x7b20000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu3"; + cpu = <&CPU3>; + + qcom,cti-save; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_cpu4: cti@7c20000 { + compatible = "arm,coresight-cti"; + reg = <0x7c20000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu4"; + cpu = <&CPU4>; + + qcom,cti-save; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_cpu5: cti@7d20000 { + compatible = "arm,coresight-cti"; + reg = <0x7d20000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu5"; + cpu = <&CPU5>; + + qcom,cti-save; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_cpu6: cti@7e20000 { + compatible = "arm,coresight-cti"; + reg = <0x7e20000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu6"; + cpu = <&CPU6>; + + qcom,cti-save; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_cpu7: cti@7f20000 { + compatible = "arm,coresight-cti"; + reg = <0x7f20000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-cpu7"; + cpu = <&CPU7>; + + qcom,cti-save; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_apss: cti@7b80000 { + compatible = "arm,coresight-cti"; + reg = <0x7b80000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_apss_dl: cti@7bc1000 { + compatible = "arm,coresight-cti"; + reg = <0x7bc1000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss-dl"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_olc: cti@7b91000 { + compatible = "arm,coresight-cti"; + reg = <0x7b91000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-olc"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_lpass0: cti@7060000 { + compatible = "arm,coresight-cti"; + reg = <0x7060000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-lpass0"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_lpass1: cti@7061000 { + compatible = "arm,coresight-cti"; + reg = <0x7061000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-lpass1"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_turing: cti@7068000 { + compatible = "arm,coresight-cti"; + reg = <0x7068000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-turing"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_wcss0: cti@71a4000 { + compatible = "arm,coresight-cti"; + reg = <0x71a4000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-wcss0"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_wcss1: cti@71a5000 { + compatible = "arm,coresight-cti"; + reg = <0x71a5000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-wcss1"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_wcss2: cti@71a6000 { + compatible = "arm,coresight-cti"; + reg = <0x71a6000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-wcss2"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_mmss: cti@7188000 { + compatible = "arm,coresight-cti"; + reg = <0x7188000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-mmss"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_isdb: cti@7121000 { + compatible = "arm,coresight-cti"; + reg = <0x7121000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-isdb"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_rpm: cti@7048000 { + compatible = "arm,coresight-cti"; + reg = <0x7048000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-rpm"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_mss: cti@7041000 { + compatible = "arm,coresight-cti"; + reg = <0x7041000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-mss"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + funnel_qatb: funnel@6005000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6005000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-qatb"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_qatb_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_qatb>; + }; + }; + port@1 { + reg = <0>; + funnel_qatb_in_tpda: endpoint { + slave-mode; + remote-endpoint = + <&tpda_out_funnel_qatb>; + }; + }; + port@2 { + reg = <3>; + funnel_qatb_in_funnel_dlct: endpoint { + slave-mode; + remote-endpoint = + <&funnel_dlct_out_funnel_qatb>; + }; + }; + }; + }; + + tpda: tpda@6004000 { + compatible = "qcom,coresight-tpda"; + reg = <0x6004000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda"; + + qcom,tpda-atid = <65>; + qcom,bc-elem-size = <7 32>, + <9 32>; + qcom,tc-elem-size = <3 32>, + <6 32>, + <9 32>; + qcom,dsb-elem-size = <7 32>, + <9 32>; + qcom,cmb-elem-size = <3 32>, + <4 32>, + <5 32>, + <9 64>; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_tpda>; + }; + }; + port@1 { + reg = <1>; + tpda_in_funnel_gpu_dl: endpoint { + slave-mode; + remote-endpoint = + <&funnel_gpu_dl_out_tpda>; + }; + }; + port@2 { + reg = <2>; + tpda_in_funnel_dlct: endpoint { + slave-mode; + remote-endpoint = + <&funnel_dlct_out_tpda>; + }; + }; + port@3 { + reg = <4>; + tpda_in_tpdm_vsense: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_vsense_out_tpda>; + }; + }; + port@4 { + reg = <5>; + tpda_in_tpdm_dcc: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dcc_out_tpda>; + }; + }; + port@5 { + reg = <6>; + tpda_in_tpdm_prng: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_prng_out_tpda>; + }; + }; + port@6 { + reg = <8>; + tpda_in_tpdm_qm: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_qm_out_tpda>; + }; + }; + port@7 { + reg = <10>; + tpda_in_tpdm_pimem: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_pimem_out_tpda>; + }; + }; + port@8 { + reg = <11>; + tpda_in_tpdm: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_out_tpda>; + }; + }; + }; + }; + + funnel_gpu_dl: funnel@7140000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x71c40000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-gpu-dl"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_gpu_dl_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_funnel_gpu_dl>; + }; + }; + port@2 { + reg = <0>; + funnel_gpu_dl_in_tpdm_gpu: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_gpu_out_funnel_gpu_dl>; + }; + }; + }; + }; + + tpdm_gpu: tpdm@7111000 { + status = "disabled"; + compatible = "qcom,coresight-tpdm"; + reg = <0x7111000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-gpu"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_gpu_out_funnel_gpu_dl: endpoint { + remote-endpoint = <&funnel_gpu_dl_in_tpdm_gpu>; + }; + }; + }; + + tpdm_vsense: tpdm@7038000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7038000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-vsense"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_vsense_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_vsense>; + }; + }; + }; + + tpdm_dcc: tpdm@7054000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7054000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dcc"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_dcc_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_dcc>; + }; + }; + }; + + tpdm_prng: tpdm@704c000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x704c000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-prng"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_prng_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_prng>; + }; + }; + }; + + tpdm_qm: tpdm@71d0000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x71d0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-qm"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_qm_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_qm>; + }; + }; + }; + + tpdm_pimem: tpdm@7050000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7050000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-pimem"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_pimem_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_pimem>; + }; + }; + }; + + tpdm: tpdm@6006000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x6006000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm"; + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm>; + }; + }; + }; + + tpda_nav: tpda@7191000 { + compatible = "qcom,coresight-tpda"; + reg = <0x7191000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-nav"; + + qcom,tpda-atid = <68>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_nav_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_tpda_nav>; + }; + }; + port@1 { + reg = <0>; + tpda_nav_in_tpdm_nav: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_nav_out_tpda_nav>; + }; + }; + }; + }; + + tpda_apss: tpda@7bc2000 { + compatible = "qcom,coresight-tpda"; + reg = <0x7bc2000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-apss"; + + qcom,tpda-atid = <66>; + qcom,dsb-elem-size = <0 128>; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_apss_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_tpda_apss>; + }; + }; + port@1 { + reg = <0>; + tpda_apss_in_tpdm_apss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_apss_out_tpda_apss>; + }; + }; + }; + }; + + tpdm_apss: tpdm@7bc0000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7bc0000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-apss"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_apss_out_tpda_apss: endpoint { + remote-endpoint = <&tpda_apss_in_tpdm_apss>; + }; + }; + }; + + tpda_mss: tpda@7043000 { + compatible = "qcom,coresight-tpda"; + reg = <0x7043000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-mss"; + + qcom,tpda-atid = <67>; + qcom,dsb-elem-size = <0 32>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_mss_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_tpda_mss>; + }; + }; + port@1 { + reg = <0>; + tpda_mss_in_tpdm_mss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_mss_out_tpda_mss>; + }; + }; + }; + }; + + tpdm_mss: tpdm@7042000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7042000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-mss"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_mss_out_tpda_mss: endpoint { + remote-endpoint = <&tpda_mss_in_tpdm_mss>; + }; + }; + }; + + tpdm_nav: tpdm@7190000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7190000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-nav"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_nav_out_tpda_nav: endpoint { + remote-endpoint = <&tpda_nav_in_tpdm_nav>; + }; + }; + }; + + tpda_olc: tpda@7b92000 { + compatible = "qcom,coresight-tpda"; + reg = <0x7b92000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-olc"; + + qcom,tpda-atid = <69>; + qcom,cmb-elem-size = <0 64>; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_olc_out_funnel_apss_merg: endpoint { + remote-endpoint = + <&funnel_apss_merg_in_tpda_olc>; + }; + }; + port@1 { + reg = <0>; + tpda_olc_in_tpdm_olc: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_olc_out_tpda_olc>; + }; + }; + }; + }; + + tpdm_olc: tpdm@7b90000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7b90000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-olc"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_olc_out_tpda_olc: endpoint { + remote-endpoint = <&tpda_olc_in_tpdm_olc>; + }; + }; + }; + + funnel_dlct: funnel@71c3000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x71c3000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-dlct"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_dlct_out_tpda: endpoint { + remote-endpoint = + <&tpda_in_funnel_dlct>; + }; + }; + port@1 { + reg = <1>; + funnel_dlct_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_funnel_dlct>; + }; + }; + port@2 { + reg = <0>; + funnel_dlct_in_tpdm_dlct: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dlct_out_funnel_dlct>; + }; + }; + port@3 { + reg = <3>; + funnel_dlct_in_funnel_wcss: endpoint { + slave-mode; + remote-endpoint = + <&funnel_wcss_out_funnel_dlct>; + }; + }; + port@4 { + reg = <1>; + funnel_dlct_in_audio_etm0: endpoint { + slave-mode; + remote-endpoint = + <&audio_etm0_out_funnel_dlct>; + }; + }; + port@5 { + reg = <2>; + funnel_dlct_in_modem_etm0: endpoint { + slave-mode; + remote-endpoint = + <&modem_etm0_out_funnel_dlct>; + }; + }; + }; + }; + + tpdm_dlct: tpdm@71c2000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x71c2000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dlct"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_dlct_out_funnel_dlct: endpoint { + remote-endpoint = <&funnel_dlct_in_tpdm_dlct>; + }; + }; + }; + + hwevent: hwevent@158000 { + compatible = "qcom,coresight-hwevent"; + reg = <0x158000 0x80>, + <0x17091000 0x80>, + <0x1730200c 0x4>, + <0xc90137c 0x4>, + <0xc828018 0x80>, + <0x1c00058 0x80>, + <0x5e02038 0x4>, + <0x5e02028 0x10>, + <0x1fcb360 0x80>, + <0x1fcb760 0x80>, + <0x1fcbf60 0x80>, + <0xa8f8860 0x4>, + <0x500c260 0x4>, + <0x500d040 0x4>, + <0x1da6400 0x80>; + reg-names = "gcc-ctrl", "lpass-stm", "lpass-qdsp", "mdss-mdp", + "mdss-misc", "pcie0-hwev", "ssc-en", "ssc-hwev", + "tcsr-qdss", "tcsr-mss0", "tcsr-mss1", "usb-ctrl", + "vbif-stm", "vbif-stm-en", "ufs-mux"; + + coresight-name = "coresight-hwevent"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>, + <&clock_mmss MMSS_MISC_AHB_CLK>; + clock-names = "core_clk", "core_a_clk", "core_mmss_clk"; + + qcom,hwevent-clks = "core_mmss_clk"; + }; + + csr: csr@6001000 { + compatible = "qcom,coresight-csr"; + reg = <0x6001000 0x1000>; + reg-names = "csr-base"; + + coresight-name = "coresight-csr"; + + qcom,blk-size = <1>; + }; + + modem_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-modem-etm0"; + qcom,inst-id = <2>; + + port{ + modem_etm0_out_funnel_dlct: endpoint { + remote-endpoint = <&funnel_dlct_in_modem_etm0>; + }; + }; + }; + + audio_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-audio-etm0"; + qcom,inst-id = <5>; + + port{ + audio_etm0_out_funnel_dlct: endpoint { + remote-endpoint = <&funnel_dlct_in_audio_etm0>; + }; + }; + }; + + rpm_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-rpm-etm0"; + qcom,inst-id = <4>; + + port{ + rpm_etm0_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_rpm_etm0>; + }; + }; + }; + + turing_etm0 { + compatible = "qcom,coresight-remote-etm"; + + coresight-name = "coresight-turing-etm0"; + qcom,inst-id = <13>; + + port{ + turing_etm0_out_funnel_in1: endpoint { + remote-endpoint = <&funnel_in1_in_turing_etm0>; + }; + }; + }; + + funnel_wcss: funnel@719e000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x719e000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-wcss"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_wcss_out_funnel_dlct: endpoint { + remote-endpoint = + <&funnel_dlct_in_funnel_wcss>; + }; + }; + port@1 { + reg = <1>; + funnel_wcss_in_tpda_wcss: endpoint { + slave-mode; + remote-endpoint = + <&tpda_wcss_out_funnel_wcss>; + }; + }; + }; + }; + + tpda_wcss: tpda@719d000 { + status = "disabled"; + compatible = "qcom,coresight-tpda"; + reg = <0x719d000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-wcss"; + + qcom,tpda-atid = <70>; + qcom,dsb-elem-size = <0 32>; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_wcss_out_funnel_wcss: endpoint { + remote-endpoint = + <&funnel_wcss_in_tpda_wcss>; + }; + }; + port@1 { + reg = <0>; + tpda_wcss_in_tpdm_wcss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_wcss_out_tpda_wcss>; + }; + }; + }; + }; + + tpdm_wcss: tpdm@719c000 { + status = "disabled"; + compatible = "qcom,coresight-tpdm"; + reg = <0x719c000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-wcss"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_wcss_out_tpda_wcss: endpoint { + remote-endpoint = <&tpda_wcss_in_tpdm_wcss>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-gpu.dtsi b/arch/arm/boot/dts/qcom/sdm660-gpu.dtsi new file mode 100644 index 000000000000..5c11131b9ddf --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-gpu.dtsi @@ -0,0 +1,271 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + pil_gpu: qcom,kgsl-hyp { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <13>; + qcom,firmware-name = "a512_zap"; + }; + + msm_bus: qcom,kgsl-busmon{ + label = "kgsl-busmon"; + compatible = "qcom,kgsl-busmon"; + }; + + gpubw: qcom,gpubw { + compatible = "qcom,devbw"; + governor = "bw_vbif"; + qcom,src-dst-ports = <26 512>; + /* + * active-only flag is used while registering the bus + * governor. It helps release the bus vote when the CPU + * subsystem is inactive + */ + qcom,active-only; + qcom,bw-tbl = + < 0 /* off */ >, + < 762 /* 100 MHz */ >, + < 1144 /* 150 MHz */ >, + < 1525 /* 200 MHz */ >, + < 2288 /* 300 MHz */ >, + < 3143 /* 412 MHz */ >, + < 4173 /* 547 MHz */ >, + < 5195 /* 681 MHz */ >, + < 5859 /* 768 MHz */ >, + < 7759 /* 1017 MHz */ >, + < 9887 /* 1296 MHz */ >, + < 10327 /* 1353 MHz */ >, + < 11863 /* 1555 MHz */ >, + < 13763 /* 1804 MHz */ >; + }; + + msm_gpu: qcom,kgsl-3d0@5000000 { + label = "kgsl-3d0"; + compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; + status = "ok"; + reg = <0x5000000 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = <0 300 0>; + interrupt-names = "kgsl_3d0_irq"; + qcom,id = <0>; + + qcom,chipid = <0x05010200>; + + qcom,initial-pwrlevel = <6>; + + /* */ + qcom,idle-timeout = <80>; + + qcom,highest-bank-bit = <14>; + + /* size in bytes */ + qcom,snapshot-size = <1048576>; + + clocks = <&clock_gfx GPUCC_GFX3D_CLK>, + <&clock_gcc GCC_GPU_CFG_AHB_CLK>, + <&clock_gfx GPUCC_RBBMTIMER_CLK>, + <&clock_gcc GCC_GPU_BIMC_GFX_CLK>, + <&clock_gcc GCC_GPU_BIMC_GFX_SRC_CLK>, + <&clock_gfx GPUCC_RBCPR_CLK>; + + clock-names = "core_clk", "iface_clk", "rbbmtimer_clk", + "mem_clk", "mem_iface_clk", "rbcpr_clk"; + + /* Bus Scale Settings */ + qcom,gpubw-dev = <&gpubw>; + qcom,bus-control; + qcom,bus-width = <16>; + qcom,msm-bus,name = "grp3d"; + qcom,msm-bus,num-cases = <14>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <26 512 0 0>, + + <26 512 0 800000>, /* 1 bus=100 */ + <26 512 0 1200000>, /* 2 bus=150 */ + <26 512 0 1600000>, /* 3 bus=200 */ + <26 512 0 2400000>, /* 4 bus=300 */ + <26 512 0 3296000>, /* 5 bus=412 */ + <26 512 0 4376000>, /* 6 bus=547 */ + <26 512 0 5448000>, /* 7 bus=681 */ + <26 512 0 6144000>, /* 8 bus=768 */ + <26 512 0 8136000>, /* 9 bus=1017 */ + <26 512 0 10368000>, /* 10 bus=1296 */ + <26 512 0 10824000>, /* 11 bus=1353 */ + <26 512 0 12440000>, /* 12 bus=1555 */ + <26 512 0 14432000>; /* 13 bus=1804 */ + + /* GDSC regulator names */ + regulator-names = "vddcx", "vdd"; + /* GDSC oxili regulators */ + vddcx-supply = <&gdsc_gpu_cx>; + vdd-supply = <&gdsc_gpu_gx>; + + /* CPU latency parameter */ + qcom,pm-qos-active-latency = <349>; + qcom,pm-qos-wakeup-latency = <349>; + + /* Quirks */ + qcom,gpu-quirk-two-pass-use-wfi; + qcom,gpu-quirk-dp2clockgating-disable; + qcom,gpu-quirk-lmloadkill-disable; + + /* Enable context aware freq. scaling */ + qcom,enable-ca-jump; + + /* Context aware jump busy penalty in us */ + qcom,ca-busy-penalty = <12000>; + + /* Context aware jump target power level */ + qcom,ca-target-pwrlevel = <4>; + + /* GPU Mempools */ + qcom,gpu-mempools { + #address-cells= <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + qcom,mempool-max-pages = <32768>; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <65536>; + }; + }; + + /* Power levels */ + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + /* TURBO */ + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <750000000>; + qcom,bus-freq = <12>; + qcom,bus-min = <11>; + qcom,bus-max = <13>; + }; + + /* TURBO */ + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <700000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <10>; + qcom,bus-max = <13>; + }; + + /* NOM_L1 */ + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <647000000>; + qcom,bus-freq = <10>; + qcom,bus-min = <10>; + qcom,bus-max = <12>; + }; + + /* NOM */ + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <588000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <9>; + qcom,bus-max = <11>; + }; + + /* SVS_L1 */ + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <465000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <7>; + qcom,bus-max = <11>; + }; + + /* SVS */ + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <370000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <5>; + qcom,bus-max = <9>; + }; + + /* Low SVS */ + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <266000000>; + qcom,bus-freq = <3>; + qcom,bus-min = <3>; + qcom,bus-max = <6>; + }; + + /* Min SVS */ + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <160000000>; + qcom,bus-freq = <3>; + qcom,bus-min = <2>; + qcom,bus-max = <5>; + }; + + /* XO */ + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <19200000>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + }; + + kgsl_msm_iommu: qcom,kgsl-iommu { + compatible = "qcom,kgsl-smmu-v2"; + + reg = <0x05040000 0x10000>; + qcom,protect = <0x40000 0x10000>; + qcom,micro-mmu-control = <0x6000>; + + clocks =<&clock_gcc GCC_GPU_CFG_AHB_CLK>, + <&clock_gcc GCC_GPU_BIMC_GFX_CLK>, + <&clock_gcc GCC_GPU_BIMC_GFX_SRC_CLK>; + + clock-names = "iface_clk", "mem_clk", "mem_iface_clk"; + + qcom,secure_align_mask = <0xfff>; + qcom,retention; + qcom,hyp_secure_alloc; + + gfx3d_user: gfx3d_user { + compatible = "qcom,smmu-kgsl-cb"; + label = "gfx3d_user"; + iommus = <&kgsl_smmu 0>; + qcom,gpu-offset = <0x48000>; + }; + + gfx3d_secure: gfx3d_secure { + compatible = "qcom,smmu-kgsl-cb"; + iommus = <&kgsl_smmu 2>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-internal-codec-cdp.dts b/arch/arm/boot/dts/qcom/sdm660-internal-codec-cdp.dts new file mode 100644 index 000000000000..2a338d2ed07b --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-internal-codec-cdp.dts @@ -0,0 +1,73 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L Int. Audio Codec CDP"; + compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp"; + qcom,board-id = <1 1>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; + +&slim_aud { + status = "disabled"; +}; + +&dai_slim { + status = "disabled"; +}; + +&wcd9335 { + status = "disabled"; +}; + +&wcd934x_cdc { + status = "disabled"; +}; + +&clock_audio { + status = "disabled"; +}; + +&wcd_rst_gpio { + status = "disabled"; +}; + +&wcd9xxx_intc { + status = "disabled"; +}; + +&tasha_snd { + status = "disabled"; +}; + +&tavil_snd { + status = "disabled"; +}; + +&int_codec { + status = "okay"; +}; + +&pmic_analog_codec { + status = "okay"; +}; + +&msm_sdw_codec { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-internal-codec-mtp.dts b/arch/arm/boot/dts/qcom/sdm660-internal-codec-mtp.dts new file mode 100644 index 000000000000..3518402bd0dc --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-internal-codec-mtp.dts @@ -0,0 +1,74 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L Int. Audio Codec MTP"; + compatible = "qcom,sdm660-mtp", "qcom,sdm660", "qcom,mtp"; + qcom,board-id = <8 1>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; + +&slim_aud { + status = "disabled"; +}; + +&dai_slim { + status = "disabled"; +}; + +&wcd9335 { + status = "disabled"; +}; + +&wcd934x_cdc { + status = "disabled"; +}; + +&clock_audio { + status = "disabled"; +}; + +&wcd_rst_gpio { + status = "disabled"; +}; + +&wcd9xxx_intc { + status = "disabled"; +}; + +&tasha_snd { + status = "disabled"; +}; + +&tavil_snd { + status = "disabled"; +}; + +&int_codec { + qcom,model = "sdm660-snd-card-mtp"; + status = "okay"; +}; + +&pmic_analog_codec { + status = "okay"; +}; + +&msm_sdw_codec { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-cdp.dts b/arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-cdp.dts new file mode 100644 index 000000000000..af0467cb3278 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-cdp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-cdp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A Int. Audio Codec CDP"; + compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp"; + qcom,board-id = <1 1>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-mtp.dts b/arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-mtp.dts new file mode 100644 index 000000000000..c9e37963146c --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-mtp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-mtp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A Int. Audio Codec MTP"; + compatible = "qcom,sdm660-mtp", "qcom,sdm660", "qcom,mtp"; + qcom,board-id = <8 1>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-rcm.dts b/arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-rcm.dts new file mode 100644 index 000000000000..d38f16d4f628 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-rcm.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-cdp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A Int. Audio Codec RCM"; + compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp"; + qcom,board-id = <21 1>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-internal-codec-rcm.dts b/arch/arm/boot/dts/qcom/sdm660-internal-codec-rcm.dts new file mode 100644 index 000000000000..eb171c66849b --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-internal-codec-rcm.dts @@ -0,0 +1,73 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L Int. Audio Codec RCM"; + compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp"; + qcom,board-id = <21 1>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; + +&slim_aud { + status = "disabled"; +}; + +&dai_slim { + status = "disabled"; +}; + +&wcd9335 { + status = "disabled"; +}; + +&wcd934x_cdc { + status = "disabled"; +}; + +&clock_audio { + status = "disabled"; +}; + +&wcd_rst_gpio { + status = "disabled"; +}; + +&wcd9xxx_intc { + status = "disabled"; +}; + +&tasha_snd { + status = "disabled"; +}; + +&tavil_snd { + status = "disabled"; +}; + +&int_codec { + status = "okay"; +}; + +&pmic_analog_codec { + status = "okay"; +}; + +&msm_sdw_codec { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-ion.dtsi b/arch/arm/boot/dts/qcom/sdm660-ion.dtsi new file mode 100644 index 000000000000..00b9e61d01b8 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-ion.dtsi @@ -0,0 +1,47 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap@25 { + reg = <25>; + qcom,ion-heap-type = "SYSTEM"; + }; + + qcom,ion-heap@22 { /* ADSP HEAP */ + reg = <22>; + memory-region = <&adsp_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = <27>; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */ + reg = <10>; + memory-region = <&secure_display_memory>; + qcom,ion-heap-type = "HYP_CMA"; + }; + + qcom,ion-heap@9 { + reg = <9>; + qcom,ion-heap-type = "SYSTEM_SECURE"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-lpi.dtsi b/arch/arm/boot/dts/qcom/sdm660-lpi.dtsi new file mode 100644 index 000000000000..34946c07074b --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-lpi.dtsi @@ -0,0 +1,182 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + lpi_tlmm: lpi_pinctrl@15070000 { + compatible = "qcom,lpi-pinctrl"; + reg = <0x15070000 0x0>; + qcom,num-gpios = <32>; + gpio-controller; + #gpio-cells = <2>; + + lpi_mclk0_active: lpi_mclk0_active { + mux { + pins = "gpio18"; + function = "func2"; + }; + + config { + pins = "gpio18"; + drive-strength = <8>; + bias-disable; + }; + }; + + lpi_mclk0_sleep: lpi_mclk0_sleep { + mux { + pins = "gpio18"; + function = "func2"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + cdc_pdm_gpios_active: cdc_pdm_gpios_active { + mux { + pins = "gpio18", "gpio19", + "gpio20", "gpio21", + "gpio23", "gpio25"; + function = "func1"; + }; + + config { + pins = "gpio18", "gpio19", + "gpio20", "gpio21", + "gpio23", "gpio25"; + drive-strength = <8>; + }; + }; + + cdc_pdm_gpios_sleep: cdc_pdm_gpios_sleep { + mux { + pins = "gpio18", "gpio19", + "gpio20", "gpio21", + "gpio23", "gpio25"; + function = "func1"; + }; + + config { + pins = "gpio18", "gpio19", + "gpio20", "gpio21", + "gpio23", "gpio25"; + drive-strength = <2>; + bias-disable; + }; + }; + + cdc_comp_gpios_active: cdc_pdm_comp_gpios_active { + mux { + pins = "gpio22", "gpio24"; + function = "func1"; + }; + + config { + pins = "gpio22", "gpio24"; + drive-strength = <8>; + }; + }; + + cdc_comp_gpios_sleep: cdc_pdm_comp_gpios_sleep { + mux { + pins = "gpio22", "gpio24"; + function = "func1"; + }; + + config { + pins = "gpio22", "gpio24"; + drive-strength = <2>; + bias-disable; + }; + }; + + lpi_cdc_reset_active: lpi_cdc_reset_active { + mux { + pins = "gpio24"; + function = "func2"; + }; + config { + pins = "gpio24"; + drive-strength = <16>; + bias-pull-down; + output-high; + }; + }; + + lpi_cdc_reset_sleep: lpi_cdc_reset_sleep { + mux { + pins = "gpio24"; + function = "func2"; + }; + + config { + pins = "gpio24"; + drive-strength = <16>; + bias-disable; + output-low; + }; + }; + + cdc_dmic12_gpios_active: dmic12_gpios_active { + mux { + pins = "gpio26", "gpio27"; + function = "func1"; + }; + + config { + pins = "gpio26", "gpio27"; + drive-strength = <8>; + }; + }; + + cdc_dmic12_gpios_sleep: dmic12_gpios_sleep { + mux { + pins = "gpio26", "gpio27"; + function = "func1"; + }; + + config { + pins = "gpio26", "gpio27"; + drive-strength = <2>; + bias-disable; + }; + }; + + cdc_dmic34_gpios_active: dmic34_gpios_active { + mux { + pins = "gpio28", "gpio29"; + function = "func1"; + }; + + config { + pins = "gpio28", "gpio29"; + drive-strength = <8>; + }; + }; + + cdc_dmic34_gpios_sleep: dmic34_gpios_sleep { + mux { + pins = "gpio28", "gpio29"; + function = "func1"; + }; + + config { + pins = "gpio28", "gpio29"; + drive-strength = <2>; + bias-disable; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-mdss-panels.dtsi b/arch/arm/boot/dts/qcom/sdm660-mdss-panels.dtsi new file mode 100644 index 000000000000..28e5f6ba8b45 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-mdss-panels.dtsi @@ -0,0 +1,83 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-sim-dualmipi-video.dtsi" +#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi" +#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi" + +&soc { + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "wqhd-vddio"; + qcom,supply-min-voltage = <1880000>; + qcom,supply-max-voltage = <1950000>; + qcom,supply-enable-load = <32000>; + qcom,supply-disable-load = <80>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "lab"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "ibb"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-post-on-sleep = <10>; + }; + }; +}; + +&soc { + dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "wqhd-vddio"; + qcom,supply-min-voltage = <1880000>; + qcom,supply-max-voltage = <1950000>; + qcom,supply-enable-load = <32000>; + qcom,supply-disable-load = <80>; + }; + }; +}; + +&dsi_dual_nt35597_truly_video { + qcom,mdss-dsi-panel-timings-8996 = [23 1e 07 08 05 03 04 a0 + 23 1e 07 08 05 03 04 a0 + 23 1e 07 08 05 03 04 a0 + 23 1e 07 08 05 03 04 a0 + 23 18 07 08 04 03 04 a0]; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,mdss-dsi-panel-timings-8996 = [23 1e 07 08 05 03 04 a0 + 23 1e 07 08 05 03 04 a0 + 23 1e 07 08 05 03 04 a0 + 23 1e 07 08 05 03 04 a0 + 23 18 07 08 04 03 04 a0]; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-mdss-pll.dtsi b/arch/arm/boot/dts/qcom/sdm660-mdss-pll.dtsi new file mode 100644 index 000000000000..d2134c56541e --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-mdss-pll.dtsi @@ -0,0 +1,82 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + mdss_dsi0_pll: qcom,mdss_dsi_pll@c994400 { + compatible = "qcom,mdss_dsi_pll_sdm660"; + status = "ok"; + label = "MDSS DSI 0 PLL"; + cell-index = <0>; + #clock-cells = <1>; + + reg = <0xc994400 0x588>, + <0xc8c2300 0x8>; + reg-names = "pll_base", "gdsc_base"; + + gdsc-supply = <&gdsc_mdss>; + + clocks = <&clock_mmss MMSS_MDSS_AHB_CLK>; + clock-names = "iface_clk"; + clock-rate = <0>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + }; + }; + + mdss_dsi1_pll: qcom,mdss_dsi_pll@c996400 { + compatible = "qcom,mdss_dsi_pll_sdm660"; + status = "ok"; + label = "MDSS DSI 1 PLL"; + cell-index = <1>; + #clock-cells = <1>; + + reg = <0xc996400 0x588>, + <0xc8c2300 0x8>; + reg-names = "pll_base", "gdsc_base"; + + gdsc-supply = <&gdsc_mdss>; + + clocks = <&clock_mmss MMSS_MDSS_AHB_CLK>; + clock-names = "iface_clk"; + clock-rate = <0>; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-mdss.dtsi b/arch/arm/boot/dts/qcom/sdm660-mdss.dtsi new file mode 100644 index 000000000000..ec14815a4be6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-mdss.dtsi @@ -0,0 +1,579 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@c900000 { + compatible = "qcom,mdss_mdp"; + status = "ok"; + reg = <0x0c900000 0x90000>, + <0x0c9b0000 0x1040>; + reg-names = "mdp_phys", "vbif_phys"; + interrupts = <0 83 0>; + interrupt-controller; + #interrupt-cells = <1>; + vdd-supply = <&gdsc_mdss>; + + /* Bus Scale Settings */ + qcom,msm-bus,name = "mdss_mdp"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, <23 512 0 0>, + <22 512 0 6400000>, <23 512 0 6400000>, + <22 512 0 6400000>, <23 512 0 6400000>; + + /* Fudge factors */ + qcom,mdss-ab-factor = <1 1>; /* 1 time */ + qcom,mdss-ib-factor = <1 1>; /* 1 time */ + qcom,mdss-clk-factor = <105 100>; /* 1.05 times */ + + qcom,max-mixer-width = <2560>; + qcom,max-pipe-width = <2560>; + + qcom,max-dest-scaler-input-width = <2048>; + qcom,max-dest-scaler-output-width = <2560>; + + /* VBIF QoS remapper settings*/ + qcom,mdss-vbif-qos-rt-setting = <1 2 2 2>; + qcom,vbif-settings = <0x00ac 0x00000040>, + <0x00d0 0x00001010>; /* v1 only */ + + qcom,mdss-has-panic-ctrl; + qcom,mdss-per-pipe-panic-luts = <0x000f>, + <0xffff>, + <0xfffc>, + <0xff00>; + + qcom,mdss-mdp-reg-offset = <0x00001000>; + qcom,max-bandwidth-low-kbps = <6600000>; + qcom,max-bandwidth-high-kbps = <6600000>; + qcom,max-bandwidth-per-pipe-kbps = <3100000>; + qcom,max-clk-rate = <412500000>; + qcom,mdss-default-ot-rd-limit = <32>; + qcom,mdss-default-ot-wr-limit = <40>; + qcom,mdss-dram-channels = <2>; + + /* Bandwidth limit settings */ + qcom,max-bw-settings = <1 6600000>, /* Default */ + <2 4500000>; /* Camera */ + + qcom,mdss-pipe-vig-off = <0x00005000 0x00007000>; + qcom,mdss-pipe-dma-off = <0x00025000 0x00027000 + 0x00029000>; + qcom,mdss-pipe-cursor-off = <0x00035000>; + + qcom,mdss-pipe-vig-xin-id = <0 4>; + qcom,mdss-pipe-dma-xin-id = <1 5 9>; + qcom,mdss-pipe-cursor-xin-id = <2>; + + /* These Offsets are relative to + * "mdp_phys + mdp-reg-offset" address + */ + qcom,mdss-pipe-vig-clk-ctrl-offsets = <0x2ac 0 0>, + <0x2b4 0 0>; + qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x2ac 8 12>, + <0x2b4 8 12>, + <0x2c4 8 12>; + qcom,mdss-pipe-cursor-clk-ctrl-offsets = <0x3a8 16 15>; + + qcom,mdss-ctl-off = <0x00002000 0x00002200 0x00002400 + 0x00002600 0x00002800>; + qcom,mdss-mixer-intf-off = <0x00045000 0x00046000 + 0x00047000 0x0004a000>; + qcom,mdss-dspp-off = <0x00055000 0x00057000>; + qcom,mdss-wb-off = <0x00066000>; + qcom,mdss-intf-off = <0x0006b000 0x0006b800 + 0x0006c000 0x0006c800>; + qcom,mdss-pingpong-off = <0x00071000 0x00071800 + 0x00072000 0x00072800>; + qcom,mdss-slave-pingpong-off = <0x00073000>; + qcom,mdss-ppb-ctl-off = <0x00000330 0x00000338 0x00000370 + 0x00000374> ; + qcom,mdss-ppb-cfg-off = <0x00000334 0x0000033C>; + qcom,mdss-has-pingpong-split; + qcom,mdss-has-separate-rotator; + + qcom,mdss-ad-off = <0x0079000 0x00079800>; + qcom,mdss-cdm-off = <0x0007a200>; + qcom,mdss-dsc-off = <0x00081000 0x00081400>; + qcom,mdss-wfd-mode = "intf"; + qcom,mdss-has-source-split; + qcom,mdss-highest-bank-bit = <0x1>; + qcom,mdss-has-decimation; + qcom,mdss-idle-power-collapse-enabled; + clocks = <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_MDSS_AHB_CLK>, + <&clock_mmss MMSS_MDSS_AXI_CLK>, + <&clock_mmss MDP_CLK_SRC>, + <&clock_mmss MMSS_MDSS_MDP_CLK>, + <&clock_mmss MMSS_MDSS_VSYNC_CLK>, + <&clock_mmss MDP_CLK_SRC>; + clock-names = "mnoc_clk", "iface_clk", "bus_clk", + "core_clk_src", "core_clk", "vsync_clk", + "lut_clk"; + + qcom,mdp-settings = <0x01190 0x00000000>, + <0x012ac 0xc0000ccc>, + <0x012b4 0xc0000ccc>, + <0x012bc 0x00cccccc>, + <0x012c4 0x000000cc>, + <0x013a8 0x0cccc0c0>, + <0x013b0 0xccccc0c0>, + <0x013b8 0xcccc0000>, + <0x013d0 0x00cc0000>, + <0x0506c 0x00000000>, + <0x0706c 0x00000000>, + <0x0906c 0x00000000>, + <0x0b06c 0x00000000>, + <0x1506c 0x00000000>, + <0x1706c 0x00000000>, + <0x1906c 0x00000000>, + <0x1b06c 0x00000000>, + <0x2506c 0x00000000>, + <0x2706c 0x00000000>; + + qcom,regs-dump-mdp = <0x01000 0x01458>, + <0x02000 0x02094>, + <0x02200 0x02294>, + <0x02400 0x02494>, + <0x02600 0x02694>, + <0x02800 0x02894>, + <0x05000 0x05154>, + <0x05a00 0x05b00>, + <0x07000 0x07154>, + <0x07a00 0x07b00>, + <0x25000 0x25184>, + <0x27000 0x27184>, + <0x29000 0x29184>, + <0x35000 0x35150>, + <0x45000 0x452bc>, + <0x46000 0x462bc>, + <0x47000 0x472bc>, + <0x4a000 0x4a2bc>, + <0x55000 0x5522c>, + <0x57000 0x5722c>, + <0x66000 0x662c0>, + <0x6b000 0x6b268>, + <0x6b800 0x6ba68>, + <0x6c000 0x6c268>, + <0x71000 0x710d4>, + <0x71800 0x718d4>, + <0x73000 0x730d4>, + <0x81000 0x81140>, + <0x81400 0x81540>; + + qcom,regs-dump-names-mdp = "MDP", + "CTL_0", "CTL_1", "CTL_2", "CTL_3", "CTL_4", + "VIG0_SSPP", "VIG0", "VIG1_SSPP", "VIG1", + "DMA0_SSPP", "DMA1_SSPP","DMA2_SSPP", + "CURSOR0_SSPP", + "LAYER_0", "LAYER_1", "LAYER_2", + "LAYER_5", + "DSPP_0", "DSPP_1", + "WB_2", + "INTF_0", "INTF_1", "INTF_2", + "PP_0", "PP_1", "PP_4", + "DSC_0", "DSC_1"; + + /* buffer parameters to calculate prefill bandwidth */ + qcom,mdss-prefill-outstanding-buffer-bytes = <0>; + qcom,mdss-prefill-y-buffer-bytes = <0>; + qcom,mdss-prefill-scaler-buffer-lines-bilinear = <2>; + qcom,mdss-prefill-scaler-buffer-lines-caf = <4>; + qcom,mdss-prefill-post-scaler-buffer-pixels = <2560>; + qcom,mdss-prefill-pingpong-buffer-pixels = <5120>; + + qcom,mdss-pp-offsets { + qcom,mdss-sspp-mdss-igc-lut-off = <0x2000>; + qcom,mdss-sspp-vig-pcc-off = <0x1b00>; + qcom,mdss-sspp-rgb-pcc-off = <0x380>; + qcom,mdss-sspp-dma-pcc-off = <0x380>; + qcom,mdss-lm-pgc-off = <0x3c0>; + qcom,mdss-dspp-gamut-off = <0x1600>; + qcom,mdss-dspp-pcc-off = <0x1700>; + qcom,mdss-dspp-pgc-off = <0x17c0>; + }; + + qcom,mdss-scaler-offsets { + qcom,mdss-vig-scaler-off = <0xa00>; + qcom,mdss-vig-scaler-lut-off = <0xb00>; + qcom,mdss-has-dest-scaler; + qcom,mdss-dest-block-off = <0x00061000>; + qcom,mdss-dest-scaler-off = <0x800 0x1000>; + qcom,mdss-dest-scaler-lut-off = <0x900 0x1100>; + }; + + smmu_mdp_unsec: qcom,smmu_mdp_unsec_cb { + compatible = "qcom,smmu_mdp_unsec"; + iommus = <&mmss_bimc_smmu 0>; + gdsc-mmagic-mdss-supply = <&gdsc_bimc_smmu>; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>; + clock-names = "mmss_noc_axi_clk", + "mmss_noc_ahb_clk", + "mmss_smmu_ahb_clk", + "mmss_smmu_axi_clk"; + }; + + smmu_mdp_sec: qcom,smmu_mdp_sec_cb { + compatible = "qcom,smmu_mdp_sec"; + iommus = <&mmss_bimc_smmu 1>; + gdsc-mmagic-mdss-supply = <&gdsc_bimc_smmu>; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>; + clock-names = "mmss_noc_axi_clk", + "mmss_noc_ahb_clk", + "mmss_smmu_ahb_clk", + "mmss_smmu_axi_clk"; + }; + + mdss_fb0: qcom,mdss_fb_primary { + cell-index = <0>; + compatible = "qcom,mdss-fb"; + }; + + mdss_fb1: qcom,mdss_fb_wfd { + cell-index = <1>; + compatible = "qcom,mdss-fb"; + }; + + mdss_fb2: qcom,mdss_fb_dp { + cell-index = <2>; + compatible = "qcom,mdss-fb"; + qcom,mdss-intf = <&mdss_dp_ctrl>; + }; + + }; + + mdss_dsi: qcom,mdss_dsi@0 { + compatible = "qcom,mdss-dsi"; + #address-cells = <1>; + #size-cells = <1>; + gdsc-supply = <&gdsc_mdss>; + vdda-1p2-supply = <&pm660_l1>; + vdda-0p9-supply = <&pm660l_l1>; + ranges = <0xc994000 0xc994000 0x400 + 0xc994400 0xc994400 0x588 + 0xc828000 0xc828000 0xac + 0xc996000 0xc996000 0x400 + 0xc996400 0xc996400 0x588 + 0xc828000 0xc828000 0xac>; + + /* Bus Scale Settings */ + qcom,msm-bus,name = "mdss_dsi"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 1000>; + + qcom,mmss-ulp-clamp-ctrl-offset = <0x14>; + + clocks = <&clock_mmss MMSS_MDSS_MDP_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_MDSS_AHB_CLK>, + <&clock_mmss MMSS_MDSS_AXI_CLK>, + <&clock_mmss MMSS_MISC_AHB_CLK>, + <&mdss_dsi0_pll BYTE0_MUX_CLK>, + <&mdss_dsi1_pll BYTE1_MUX_CLK>, + <&mdss_dsi0_pll PIX0_MUX_CLK>, + <&mdss_dsi1_pll PIX1_MUX_CLK>; + clock-names = "mdp_core_clk", + "mnoc_clk", "iface_clk", + "bus_clk", "core_mmss_clk", + "ext_byte0_clk", "ext_byte1_clk", + "ext_pixel0_clk", "ext_pixel1_clk"; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1250000>; + qcom,supply-enable-load = <12560>; + qcom,supply-disable-load = <4>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <925000>; + qcom,supply-enable-load = <73400>; + qcom,supply-disable-load = <32>; + }; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@c994000 { + compatible = "qcom,mdss-dsi-ctrl"; + label = "MDSS DSI CTRL->0"; + cell-index = <0>; + reg = <0xc994000 0x400>, + <0xc994400 0x588>, + <0xc828000 0xac>; + reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys"; + + qcom,timing-db-mode; + wqhd-vddio-supply = <&pm660_l11>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + qcom,mdss-mdp = <&mdss_mdp>; + qcom,mdss-fb-map = <&mdss_fb0>; + + clocks = <&clock_mmss MMSS_MDSS_BYTE0_CLK>, + <&clock_mmss MMSS_MDSS_PCLK0_CLK>, + <&clock_mmss MMSS_MDSS_ESC0_CLK>, + <&clock_mmss BYTE0_CLK_SRC>, + <&clock_mmss PCLK0_CLK_SRC>, + <&clock_mmss MMSS_MDSS_BYTE0_INTF_CLK>; + clock-names = "byte_clk", "pixel_clk", "core_clk", + "byte_clk_rcg", "pixel_clk_rcg", + "byte_intf_clk"; + + qcom,platform-strength-ctrl = [ff 06 + ff 06 + ff 06 + ff 06 + ff 00]; + qcom,platform-regulator-settings = [1d + 1d 1d 1d 1d]; + qcom,platform-lane-config = [00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 8f]; + }; + + mdss_dsi1: qcom,mdss_dsi_ctrl1@c996000 { + compatible = "qcom,mdss-dsi-ctrl"; + label = "MDSS DSI CTRL->1"; + cell-index = <1>; + reg = <0xc996000 0x400>, + <0xc996400 0x588>, + <0xc828000 0xac>; + reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys"; + + qcom,timing-db-mode; + wqhd-vddio-supply = <&pm660_l11>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + qcom,mdss-mdp = <&mdss_mdp>; + qcom,mdss-fb-map = <&mdss_fb0>; + + clocks = <&clock_mmss MMSS_MDSS_BYTE1_CLK>, + <&clock_mmss MMSS_MDSS_PCLK1_CLK>, + <&clock_mmss MMSS_MDSS_ESC1_CLK>, + <&clock_mmss BYTE1_CLK_SRC>, + <&clock_mmss PCLK1_CLK_SRC>, + <&clock_mmss MMSS_MDSS_BYTE1_INTF_CLK>; + clock-names = "byte_clk", "pixel_clk", "core_clk", + "byte_clk_rcg", "pixel_clk_rcg", + "byte_intf_clk"; + + qcom,platform-strength-ctrl = [ff 06 + ff 06 + ff 06 + ff 06 + ff 00]; + qcom,platform-regulator-settings = [1d + 1d 1d 1d 1d]; + qcom,platform-lane-config = [00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 0f + 00 00 10 8f]; + }; + }; + + qcom,mdss_wb_panel { + compatible = "qcom,mdss_wb"; + qcom,mdss_pan_res = <640 480>; + qcom,mdss_pan_bpp = <24>; + qcom,mdss-fb-map = <&mdss_fb1>; + }; + + msm_ext_disp: qcom,msm_ext_disp { + status = "disabled"; + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + qcom,msm_ext_disp = <&msm_ext_disp>; + }; + }; + + mdss_dp_ctrl: qcom,dp_ctrl@c990000 { + status = "disabled"; + cell-index = <0>; + compatible = "qcom,mdss-dp"; + qcom,mdss-fb-map = <&mdss_fb2>; + + gdsc-supply = <&gdsc_mdss>; + vdda-1p2-supply = <&pm660_l1>; + vdda-0p9-supply = <&pm660l_l1>; + + reg = <0xc990000 0xa84>, + <0xc011000 0x910>, + <0x1fcb200 0x050>, + <0xc8c2200 0x1a0>, + <0x780000 0x621c>, + <0xc9e1000 0x02c>; + reg-names = "dp_ctrl", "dp_phy", "tcsr_regs", "dp_mmss_cc", + "qfprom_physical","hdcp_physical"; + + qcom,msm_ext_disp = <&msm_ext_disp>; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "gdsc"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1250000>; + qcom,supply-enable-load = <12560>; + qcom,supply-disable-load = <4>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <925000>; + qcom,supply-enable-load = <73400>; + qcom,supply-disable-load = <32>; + }; + }; + }; + + mdss_rotator: qcom,mdss_rotator { + compatible = "qcom,sde_rotator"; + reg = <0x0c900000 0xab100>, + <0x0c9b0000 0x1040>; + reg-names = "mdp_phys", + "rot_vbif_phys"; + + qcom,mdss-rot-mode = <1>; + qcom,mdss-highest-bank-bit = <0x2>; + + /* Bus Scale Settings */ + qcom,msm-bus,name = "mdss_rotator"; + qcom,msm-bus,num-cases = <3>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <22 512 0 0>, + <22 512 0 6400000>, + <22 512 0 6400000>; + + rot-vdd-supply = <&gdsc_mdss>; + qcom,supply-names = "rot-vdd"; + + clocks = <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_MDSS_AHB_CLK>, + <&clock_mmss ROT_CLK_SRC>, + <&clock_mmss MMSS_MDSS_ROT_CLK>, + <&clock_mmss MMSS_MDSS_AXI_CLK>; + clock-names = "mnoc_clk", + "iface_clk", "rot_core_clk", + "rot_clk", "axi_clk"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <2 0>; + + /* VBIF QoS remapper settings*/ + qcom,mdss-rot-vbif-qos-setting = <1 1 1 1>; + + qcom,mdss-default-ot-rd-limit = <32>; + qcom,mdss-default-ot-wr-limit = <40>; + + smmu_rot_unsec: qcom,smmu_rot_unsec_cb { + compatible = "qcom,smmu_sde_rot_unsec"; + iommus = <&mmss_bimc_smmu 0xe00>; + gdsc-mdss-supply = <&gdsc_bimc_smmu>; + + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>; + clock-names = "mmss_noc_axi_clk", + "mmss_noc_ahb_clk", + "mmss_smmu_ahb_clk", + "mmss_smmu_axi_clk"; + }; + + smmu_rot_sec: qcom,smmu_rot_sec_cb { + compatible = "qcom,smmu_sde_rot_sec"; + iommus = <&mmss_bimc_smmu 0xe01>; + gdsc-mdss-supply = <&gdsc_bimc_smmu>; + + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>; + clock-names = "mmss_noc_axi_clk", + "mmss_noc_ahb_clk", + "mmss_smmu_ahb_clk", + "mmss_smmu_axi_clk"; + }; + }; + +}; + +#include "sdm660-mdss-panels.dtsi" diff --git a/arch/arm/boot/dts/qcom/sdm660-mtp.dts b/arch/arm/boot/dts/qcom/sdm660-mtp.dts new file mode 100644 index 000000000000..3e5a6e1a38b9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-mtp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L MTP"; + compatible = "qcom,sdm660-mtp", "qcom,sdm660", "qcom,mtp"; + qcom,board-id = <8 0>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-mtp.dtsi b/arch/arm/boot/dts/qcom/sdm660-mtp.dtsi new file mode 100644 index 000000000000..ef324de2de9f --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-mtp.dtsi @@ -0,0 +1,99 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdm660-pinctrl.dtsi" +#include "sdm660-camera-sensor-mtp.dtsi" +/ { +}; + +&uartblsp1dm1 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&ufsphy1 { + vdda-phy-supply = <&pm660l_l1>; + vdda-pll-supply = <&pm660_l10>; + vddp-ref-clk-supply = <&pm660_l1>; + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14200>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; + status = "ok"; +}; + +&ufs1 { + vdd-hba-supply = <&gdsc_ufs>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm660l_l4>; + vccq2-supply = <&pm660_l8>; + vcc-max-microamp = <500000>; + vccq2-max-microamp = <600000>; + status = "ok"; +}; + +&mdss_mdp { + qcom,mdss-pref-prim-intf = "dsi"; +}; + +&mdss_dsi { + hw-config = "split_dsi"; +}; + +&mdss_dsi0 { + qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; + pinctrl-names = "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; + pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; + qcom,platform-reset-gpio = <&tlmm 53 0>; + qcom,platform-te-gpio = <&tlmm 59 0>; +}; + +&mdss_dsi1 { + qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; + pinctrl-names = "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; + pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; + qcom,platform-reset-gpio = <&tlmm 53 0>; + qcom,platform-te-gpio = <&tlmm 59 0>; +}; + +&pm660l_wled { + qcom,led-strings-list = [01 02]; +}; + +&dsi_dual_nt35597_truly_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&soc { + qcom,msm-ssc-sensors { + compatible = "qcom,msm-ssc-sensors"; + }; +}; + +&mem_client_3_size { + qcom,peripheral-size = <0x500000>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-pinctrl.dtsi b/arch/arm/boot/dts/qcom/sdm660-pinctrl.dtsi new file mode 100644 index 000000000000..29343a243b9c --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-pinctrl.dtsi @@ -0,0 +1,1293 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + tlmm: pinctrl@03000000 { + compatible = "qcom,sdm660-pinctrl"; + reg = <0x03000000 0xc00000>; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + uart_console_active: uart_console_active { + mux { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + + led_enable: led_enable { + mux { + pins = "gpio40"; + drive_strength = <16>; + output-high; + }; + }; + + led_disable: led_disable { + mux { + pins = "gpio40"; + drive_strength = <2>; + output-low; + }; + }; + + trigout_b: trigout_b { + mux { + pins = "gpio12"; + function = "qdss_cti1_b"; + }; + + config { + pins = "gpio12"; + drive-strength = <16>; + bias-disable; + }; + }; + + /* SDC pin type */ + sdc1_clk_on: sdc1_clk_on { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc1_clk_off: sdc1_clk_off { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_cmd_on: sdc1_cmd_on { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_cmd_off: sdc1_cmd_off { + config { + pins = "sdc1_cmd"; + num-grp-pins = <1>; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_data_on: sdc1_data_on { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc1_data_off: sdc1_data_off { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_rclk_on: sdc1_rclk_on { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + sdc1_rclk_off: sdc1_rclk_off { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + /* I2C CONFIGURATION */ + i2c_1 { + i2c_1_active: i2c_1_active { + mux { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_1_sleep: i2c_1_sleep { + mux { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_2 { + i2c_2_active: i2c_2_active { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_2_sleep: i2c_2_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_3 { + i2c_3_active: i2c_3_active { + mux { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_3_sleep: i2c_3_sleep { + mux { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_4 { + i2c_4_active: i2c_4_active { + mux { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_4_sleep: i2c_4_sleep { + mux { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_5 { + i2c_5_active: i2c_5_active { + mux { + pins = "gpio18", "gpio19"; + function = "blsp_i2c5"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_5_sleep: i2c_5_sleep { + mux { + pins = "gpio18", "gpio19"; + function = "blsp_i2c5"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_6 { + i2c_6_active: i2c_6_active { + mux { + pins = "gpio22", "gpio23"; + function = "blsp_i2c6"; + }; + + config { + pins = "gpio22", "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_6_sleep: i2c_6_sleep { + mux { + pins = "gpio22", "gpio23"; + function = "blsp_i2c6"; + }; + + config { + pins = "gpio22", "gpio23"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_7 { + i2c_7_active: i2c_7_active { + mux { + pins = "gpio26", "gpio27"; + function = "blsp_i2c7"; + }; + + config { + pins = "gpio26", "gpio27"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_7_sleep: i2c_7_sleep { + mux { + pins = "gpio26", "gpio27"; + function = "blsp_i2c7"; + }; + + config { + pins = "gpio26", "gpio27"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + i2c_8 { + i2c_8_active: i2c_8_active { + mux { + pins = "gpio30", "gpio31"; + function = "blsp_i2c8_a"; + }; + + config { + pins = "gpio30", "gpio31"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c_8_sleep: i2c_8_sleep { + mux { + pins = "gpio30", "gpio31"; + function = "blsp_i2c8_a"; + }; + + config { + pins = "gpio30", "gpio31"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + /* SPI CONFIGURATION */ + spi_1 { + spi_1_active: spi_1_active { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "blsp_spi1"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_1_sleep: spi_1_sleep { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "blsp_spi1"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_2 { + spi_2_active: spi_2_active { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "blsp_spi2"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_2_sleep: spi_2_sleep { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "blsp_spi2"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_3 { + spi_3_active: spi_3_active { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_3_sleep: spi_3_sleep { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_4 { + spi_4_active: spi_4_active { + mux { + pins = "gpio12", "gpio13", + "gpio14", "gpio15"; + function = "blsp_spi4"; + }; + + config { + pins = "gpio12", "gpio13", + "gpio14", "gpio15"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_4_sleep: spi_4_sleep { + mux { + pins = "gpio12", "gpio13", + "gpio14", "gpio15"; + function = "blsp_spi4"; + }; + + config { + pins = "gpio12", "gpio13", + "gpio14", "gpio15"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_5 { + spi_5_active: spi_5_active { + mux { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + function = "blsp_spi5"; + }; + + config { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_5_sleep: spi_5_sleep { + mux { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + function = "blsp_spi5"; + }; + + config { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_6 { + spi_6_active: spi_6_active { + mux { + pins = "gpio49", "gpio52", + "gpio22", "gpio23"; + function = "blsp_spi6"; + }; + + config { + pins = "gpio49", "gpio52", + "gpio22", "gpio23"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_6_sleep: spi_6_sleep { + mux { + pins = "gpio49", "gpio52", + "gpio22", "gpio23"; + function = "blsp_spi6"; + }; + + config { + pins = "gpio49", "gpio52", + "gpio22", "gpio23"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_7 { + spi_7_active: spi_7_active { + mux { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + function = "blsp_spi7"; + }; + + config { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_7_sleep: spi_7_sleep { + mux { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + function = "blsp_spi7"; + }; + + config { + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_8 { + spi_8_active: spi_8_active { + mux { + pins = "gpio28", "gpio29", + "gpio30", "gpio31"; + function = "blsp_spi8_a"; + }; + + config { + pins = "gpio28", "gpio29", + "gpio30", "gpio31"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_8_sleep: spi_8_sleep { + mux { + pins = "gpio28", "gpio29", + "gpio30", "gpio31"; + function = "blsp_spi8_a"; + }; + + config { + pins = "gpio28", "gpio29", + "gpio30", "gpio31"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + sdw_clk_pin { + sdw_clk_sleep: sdw_clk_sleep { + mux { + pins = "gpio24"; + function = "sndwire_clk"; + }; + + config { + pins = "gpio24"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + sdw_clk_active: sdw_clk_active { + mux { + pins = "gpio24"; + function = "sndwire_clk"; + }; + + config { + pins = "gpio24"; + drive-strength = <16>; + bias-disable; + }; + }; + }; + + sdw_clk_data { + sdw_data_sleep: sdw_data_sleep { + mux { + pins = "gpio25"; + function = "sndwire_data"; + }; + + config { + pins = "gpio25"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + sdw_data_active: sdw_data_active { + mux { + pins = "gpio25"; + function = "sndwire_data"; + }; + + config { + pins = "gpio25"; + drive-strength = <16>; + bias-disable; + }; + }; + }; + + /* WSA speaker reset pins */ + spkr_1_sd_n { + spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_1_sd_n_active: spkr_1_sd_n_active { + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + spkr_2_sd_n { + spkr_2_sd_n_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio27"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_2_sd_n_active: spkr_2_sd_n_active { + mux { + pins = "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio27"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + wcd_gnd_mic_swap { + wcd_gnd_mic_swap_idle: wcd_gnd_mic_swap_idle { + mux { + pins = "gpio63"; + function = "gpio"; + }; + config { + pins = "gpio63"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + wcd_gnd_mic_swap_active: wcd_gnd_mic_swap_active { + mux { + pins = "gpio63"; + function = "gpio"; + }; + config { + pins = "gpio63"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + msm_hph_en0 { + hph_en0_sleep: hph_en0_sleep { + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + output-low; + }; + }; + + hph_en0_active: hph_en0_active { + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + output-high; + }; + }; + }; + + msm_hph_en1 { + hph_en1_sleep: hph_en1_sleep { + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + output-low; + }; + }; + + hph_en1_active: hph_en1_active { + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + output-high; + }; + }; + }; + + cci0_active: cci0_active { + mux { + /* CLK, DATA */ + pins = "gpio36","gpio37"; // Only 2 + function = "cci_i2c"; + }; + + config { + pins = "gpio36","gpio37"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio36","gpio37"; + function = "cci_i2c"; + }; + + config { + pins = "gpio36","gpio37"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA */ + pins = "gpio38","gpio39"; + function = "cci_i2c"; + }; + + config { + pins = "gpio38","gpio39"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio38","gpio39"; + function = "cci_i2c"; + }; + + + config { + pins = "gpio38","gpio39"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_actuator_vaf_active: cam_actuator_vaf_active { + /* ACTUATOR POWER */ + mux { + pins = "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio50"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_actuator_vaf_suspend: cam_actuator_vaf_suspend { + /* ACTUATOR POWER */ + mux { + pins = "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio50"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio32"; + function = "cam_mclk"; + }; + + config { + pins = "gpio32"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio32"; + function = "cam_mclk"; + }; + + config { + pins = "gpio32"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_active: cam_sensor_rear_active { + /* RESET, STANDBY */ + mux { + pins = "gpio46","gpio44"; + function = "gpio"; + }; + + config { + pins = "gpio46","gpio44"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_suspend: cam_sensor_rear_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio46","gpio44"; + function = "gpio"; + }; + + config { + pins = "gpio46","gpio44"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio33"; + function = "cam_mclk"; + }; + + config { + pins = "gpio33"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio33"; + function = "cam_mclk"; + }; + + config { + pins = "gpio33"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear2_active: cam_sensor_rear2_active { + /* RESET, STANDBY */ + mux { + pins = "gpio48","gpio51"; + function = "gpio"; + }; + + config { + pins = "gpio48","gpio51"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear2_suspend: cam_sensor_rear2_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio48","gpio51"; + function = "gpio"; + }; + config { + pins = "gpio48","gpio51"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio34"; + function = "cam_mclk"; + }; + + config { + pins = "gpio34"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio34"; + function = "cam_mclk"; + }; + + config { + pins = "gpio34"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_active: cam_sensor_front_active { + /* RESET VANA*/ + mux { + pins = "gpio47", "gpio44"; + function = "gpio"; + }; + + config { + pins = "gpio47", "gpio44"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_suspend: cam_sensor_front_suspend { + /* RESET */ + mux { + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + /* HS UART CONFIGURATION */ + blsp1_uart1_active: blsp1_uart1_active { + mux { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1_sleep: blsp1_uart1_sleep { + mux { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2_active: blsp1_uart2_active { + mux { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "blsp_uart2 "; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2_sleep: blsp1_uart2_sleep { + mux { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart1_active: blsp2_uart1_active { + mux { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "blsp_uart5"; + }; + + config { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart1_sleep: blsp2_uart1_sleep { + mux { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart2_active: blsp2_uart2_active { + mux { + pins = "gpio24", "gpio25", "gpio26", "gpio27"; + function = "blsp_uart6_a"; + }; + + config { + pins = "gpio24", "gpio25", "gpio26", "gpio27"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart2_sleep: blsp2_uart2_sleep { + mux { + pins = "gpio24", "gpio25", "gpio26", "gpio27"; + function = "gpio"; + }; + + config { + pins = "gpio24", "gpio25", "gpio26", "gpio27"; + drive-strength = <2>; + bias-disable; + }; + }; + + tlmm_gpio_key { + gpio_key_active: gpio_key_active { + mux { + pins = "gpio64", "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio64", "gpio113"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + gpio_key_suspend: gpio_key_suspend { + mux { + pins = "gpio64", "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio64", "gpio113"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pmx_mdss: pmx_mdss { + mdss_dsi_active: mdss_dsi_active { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + mdss_dsi_suspend: mdss_dsi_suspend { + mux { + pins = "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio53"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + }; + + pmx_mdss_te { + mdss_te_active: mdss_te_active { + mux { + pins = "gpio59"; + function = "mdp_vsync_p"; + }; + config { + pins = "gpio59"; + drive-strength = <2>; /* 8 mA */ + bias-pull-down; /* pull down*/ + }; + }; + + mdss_te_suspend: mdss_te_suspend { + mux { + pins = "gpio59"; + function = "mdp_vsync_p"; + }; + config { + pins = "gpio59"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + }; + + ts_mux { + ts_active: ts_active { + mux { + pins = "gpio66", "gpio67"; + function = "gpio"; + }; + + config { + pins = "gpio66", "gpio67"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio66"; + function = "gpio"; + }; + + config { + pins = "gpio66"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio67"; + function = "gpio"; + }; + + config { + pins = "gpio67"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-pm.dtsi b/arch/arm/boot/dts/qcom/sdm660-pm.dtsi new file mode 100644 index 000000000000..6a9fc5bde361 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-pm.dtsi @@ -0,0 +1,821 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include + +&soc { + qcom,spm@178120000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x17812000 0x1000>; + qcom,name = "gold-l2"; /* Gold L2 SAW */ + qcom,saw2-ver-reg = <0xfd0>; + qcom,cpu-vctl-list = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,vctl-timeout-us = <500>; + qcom,vctl-port = <0x0>; + qcom,phase-port = <0x1>; + qcom,saw2-avs-ctl = <0x1010031>; + qcom,saw2-avs-limit = <0x4580458>; + qcom,pfm-port = <0x2>; + }; + + qcom,spm@179120000 { + compatible = "qcom,spm-v2"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x17912000 0x1000>; + qcom,name = "silver-l2"; /* Silver L2 SAW */ + qcom,saw2-ver-reg = <0xfd0>; + qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,vctl-timeout-us = <500>; + qcom,vctl-port = <0x0>; + qcom,phase-port = <0x1>; + qcom,saw2-avs-ctl = <0x1010031>; + qcom,saw2-avs-limit = <0x4580458>; + qcom,pfm-port = <0x2>; + }; + + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + qcom,use-psci; + #address-cells = <1>; + #size-cells = <0>; + qcom,pm-cluster@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + label = "system"; + qcom,spm-device-names = "cci"; + qcom,psci-mode-shift = <8>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cluster-level@0{ + reg = <0>; + label = "system-wfi"; + qcom,psci-mode = <0x0>; + qcom,latency-us = <100>; + qcom,ss-power = <725>; + qcom,energy-overhead = <85000>; + qcom,time-overhead = <120>; + }; + + qcom,pm-cluster-level@1{ /* E3 */ + reg = <1>; + label = "system-pc"; + qcom,psci-mode = <0x3>; + qcom,latency-us = <350>; + qcom,ss-power = <530>; + qcom,energy-overhead = <160000>; + qcom,time-overhead = <550>; + qcom,min-child-idx = <3>; + qcom,is-reset; + qcom,notify-rpm; + }; + + qcom,pm-cluster@0{ + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + label = "pwr"; + qcom,spm-device-names = "l2"; + qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cluster-level@0{ /* D1 */ + reg = <0>; + label = "pwr-l2-wfi"; + qcom,psci-mode = <0x1>; + qcom,latency-us = <40>; + qcom,ss-power = <740>; + qcom,energy-overhead = <65000>; + qcom,time-overhead = <85>; + }; + qcom,pm-cluster-level@1{ /* D2D */ + reg = <1>; + label = "pwr-l2-dynret"; + qcom,psci-mode = <0x2>; + qcom,latency-us = <60>; + qcom,ss-power = <700>; + qcom,energy-overhead = <85000>; + qcom,time-overhead = <85>; + qcom,min-child-idx = <1>; + }; + + qcom,pm-cluster-level@2{ /* D2E */ + reg = <2>; + label = "pwr-l2-ret"; + qcom,psci-mode = <0x3>; + qcom,latency-us = <100>; + qcom,ss-power = <640>; + qcom,energy-overhead = <135000>; + qcom,time-overhead = <85>; + qcom,min-child-idx = <2>; + }; + + qcom,pm-cluster-level@3{ /* D4 */ + reg = <3>; + label = "pwr-l2-pc"; + qcom,psci-mode = <0x4>; + qcom,latency-us = <700>; + qcom,ss-power = <450>; + qcom,energy-overhead = <210000>; + qcom,time-overhead = <11500>; + qcom,min-child-idx = <2>; + qcom,is-reset; + }; + + qcom,pm-cpu { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + qcom,spm-cpu-mode = "wfi"; + qcom,psci-cpu-mode = <0x1>; + qcom,latency-us = <20>; + qcom,ss-power = <750>; + qcom,energy-overhead = <32000>; + qcom,time-overhead = <60>; + }; + + qcom,pm-cpu-level@1 { /* C2D */ + reg = <1>; + qcom,psci-cpu-mode = <2>; + qcom,spm-cpu-mode = "ret"; + qcom,latency-us = <40>; + qcom,ss-power = <730>; + qcom,energy-overhead = <85500>; + qcom,time-overhead = <110>; + }; + + qcom,pm-cpu-level@2 { /* C3 */ + reg = <2>; + qcom,spm-cpu-mode = "pc"; + qcom,psci-cpu-mode = <0x3>; + qcom,latency-us = <80>; + qcom,ss-power = <700>; + qcom,energy-overhead = <126480>; + qcom,time-overhead = <160>; + qcom,is-reset; + }; + }; + }; + + qcom,pm-cluster@1{ + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + label = "perf"; + qcom,spm-device-names = "l2"; + qcom,cpu = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cluster-level@0{ /* D1 */ + reg = <0>; + label = "perf-l2-wfi"; + qcom,psci-mode = <0x1>; + qcom,latency-us = <40>; + qcom,ss-power = <740>; + qcom,energy-overhead = <70000>; + qcom,time-overhead = <80>; + }; + + qcom,pm-cluster-level@1{ /* D2D */ + reg = <1>; + label = "perf-l2-dynret"; + qcom,psci-mode = <2>; + qcom,latency-us = <60>; + qcom,ss-power = <700>; + qcom,energy-overhead = <85000>; + qcom,time-overhead = <85>; + qcom,min-child-idx = <1>; + }; + + qcom,pm-cluster-level@2{ /* D2E */ + reg = <2>; + label = "perf-l2-ret"; + qcom,psci-mode = <3>; + qcom,latency-us = <100>; + qcom,ss-power = <640>; + qcom,energy-overhead = <135000>; + qcom,time-overhead = <85>; + qcom,min-child-idx = <2>; + }; + + qcom,pm-cluster-level@3{ /* D4 */ + reg = <3>; + label = "perf-l2-pc"; + qcom,psci-mode = <0x4>; + qcom,latency-us = <800>; + qcom,ss-power = <450>; + qcom,energy-overhead = <240000>; + qcom,time-overhead = <11500>; + qcom,min-child-idx = <2>; + qcom,is-reset; + }; + + qcom,pm-cpu { + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + + qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + qcom,spm-cpu-mode = "wfi"; + qcom,psci-cpu-mode = <0x1>; + qcom,latency-us = <25>; + qcom,ss-power = <750>; + qcom,energy-overhead = <37000>; + qcom,time-overhead = <50>; + }; + + qcom,pm-cpu-level@1 { /* C2D */ + reg = <1>; + qcom,psci-cpu-mode = <2>; + qcom,spm-cpu-mode = "ret"; + qcom,latency-us = <40>; + qcom,ss-power = <730>; + qcom,energy-overhead = <85500>; + qcom,time-overhead = <110>; + }; + + qcom,pm-cpu-level@2 { /* C3 */ + reg = <2>; + qcom,spm-cpu-mode = "pc"; + qcom,psci-cpu-mode = <0x3>; + qcom,latency-us = <80>; + qcom,ss-power = <700>; + qcom,energy-overhead = <136480>; + qcom,time-overhead = <160>; + qcom,is-reset; + }; + }; + }; + }; + }; + + qcom,rpm-stats@200000 { + compatible = "qcom,rpm-stats"; + reg = <0x200000 0x1000>, + <0x290014 0x4>, + <0x29001c 0x4>; + reg-names = "phys_addr_base", + "offset_addr", + "heap_phys_addrbase"; + qcom,sleep-stats-version = <2>; + }; + + qcom,rpm-rail-stats@200000 { + compatible = "qcom,rpm-rail-stats"; + reg = <0x200000 0x100>, + <0x29000c 0x4>; + reg-names = "phys_addr_base", + "offset_addr"; + }; + + qcom,rpm-log@200000 { + compatible = "qcom,rpm-log"; + reg = <0x200000 0x4000>, + <0x290018 0x4>; + qcom,rpm-addr-phys = <0x200000>; + qcom,offset-version = <4>; + qcom,offset-page-buffer-addr = <36>; + qcom,offset-log-len = <40>; + qcom,offset-log-len-mask = <44>; + qcom,offset-page-indices = <56>; + }; + + qcom,rpm-master-stats@778150 { + compatible = "qcom,rpm-master-stats"; + reg = <0x778150 0x5000>; + qcom,masters = "APSS", "MPSS", "ADSP", "CDSP", "TZ"; + qcom,master-stats-version = <2>; + qcom,master-offset = <4096>; + }; + + rpm_msg_ram: memory@0x200000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x200000 0x1000>, + <0x290000 0x1000>; + }; + + rpm_code_ram: rpm-memory@0x778000 { + compatible = "qcom,rpm-code-ram"; + reg = <0x778000 0x5000>; + }; + + qcom,system-stats { + compatible = "qcom,system-stats"; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + qcom,rpm-code-ram = <&rpm_code_ram>; + qcom,masters = "APSS", "MPSS", "ADSP", "CDSP", "TZ"; + }; + + qcom,mpm@7781b8 { + compatible = "qcom,mpm-v2"; + reg = <0x7781b8 0x1000>, /* MSM_RPM_MPM_BASE 4K */ + <0x17911008 0x4>; /* MSM_APCS_GCC_BASE 4K */ + reg-names = "vmpm", "ipc"; + interrupts = ; + clocks = <&clock_rpmcc CXO_LPM_CLK>; + clock-names = "xo"; + qcom,num-mpm-irqs = <96>; + + qcom,ipc-bit-offset = <1>; + + qcom,gic-parent = <&intc>; + qcom,gic-map = + <0x02 216>, /* tsens1_tsens_upper_lower_int */ + <0x34 275>, /* qmp_usb3_lfps_rxterm_irq_cx */ + <0x4f 379>, /* qusb2phy_intr */ + <0x51 379>, /* qusb2phy_intr */ + <0x57 358>, /* ee0_apps_hlos_spmi_periph_irq */ + <0x5b 519>, /* lpass_pmu_tmr_timeout_irq_cx */ + <0xff 16>, /* APC[0-7]_qgicQTmrHypPhysIrptReq */ + <0xff 17>, /* APC[0-7]_qgicQTmrSecPhysIrptReq */ + <0xff 18>, /* APC[0-7]_qgicQTmrNonSecPhysIrptReq */ + <0xff 19>, /* APC[0-7]_qgicQTmrVirtIrptReq */ + <0xff 20>, /* APC[0-7]_dbgCommRxFull */ + <0xff 21>, /* APC[0-7]_dbgCommTxEmpty */ + <0xff 22>, /* APC[0-7]_qgicPerfMonIrptReq */ + <0xff 23>, /* corespm_vote_int[0-7] */ + <0xff 24>, /* APC[0-3]_qgicExtFaultIrptReq */ + <0xff 28>, /* qgicWakeupSync[0-7] */ + <0xff 29>, /* APCC_cti_SPI_intx[0-7] */ + <0xff 30>, /* APCC_cti_SPI_inty[0-7] */ + <0xff 32>, /* l2spm_vote_int[0] */ + <0xff 33>, /* l2spm_vote_int[1] */ + <0xff 34>, /* APCC_qgicL2ErrorIrptReq */ + <0xff 35>, /* WDT_barkInt */ + <0xff 36>, /* WDT_biteExpired */ + <0xff 39>, /* QTMR_qgicFrm0VirtIrq */ + <0xff 40>, /* QTMR_qgicFrm0PhyIrq */ + <0xff 41>, /* QTMR_qgicFrm1PhyIrq */ + <0xff 42>, /* QTMR_qgicFrm2PhyIrq */ + <0xff 43>, /* QTMR_qgicFrm3PhyIrq */ + <0xff 44>, /* QTMR_qgicFrm4PhyIrq */ + <0xff 45>, /* QTMR_qgicFrm5PhyIrq */ + <0xff 46>, /* QTMR_qgicFrm6PhyIrq */ + <0xff 47>, /* rbif_Irq[0] */ + <0xff 48>, /* rbif_Irq[1] */ + <0xff 49>, /* rbif_Irq[2] */ + <0xff 50>, /* rbif_Irq[3] */ + <0xff 51>, /* rbif_Irq[4] */ + <0xff 52>, /* cci_spm_vote_summary_int */ + <0xff 54>, /* nERRORIRQ */ + <0xff 55>, /* nEVNTCNTOVERFLOW_cci */ + <0xff 56>, /* QTMR_qgicFrm0VirtIrq */ + <0xff 57>, /* QTMR_qgicFrm0PhyIrq */ + <0xff 58>, /* QTMR_qgicFrm1PhyIrq */ + <0xff 59>, /* QTMR_qgicFrm2PhyIrq */ + <0xff 60>, /* QTMR_qgicFrm3PhyIrq */ + <0xff 61>, /* QTMR_qgicFrm4PhyIrq */ + <0xff 62>, /* QTMR_qgicFrm5PhyIrq */ + <0xff 63>, /* QTMR_qgicFrm6PhyIrq */ + <0xff 64>, /* wakeup_counter_irq_OR */ + <0xff 65>, /* APC[0-3]_vs_alarm */ + <0xff 66>, /* apc1_vs_alarm */ + <0xff 67>, /* o_pwr_osm_irq */ + <0xff 68>, /* o_perf_osm_irq */ + <0xff 69>, /* o_pwr_dcvsh_interrupt */ + <0xff 70>, /* o_perf_dcvsh_interrupt */ + <0xff 73>, /* L2_EXTERRIRQ_C0 */ + <0xff 74>, /* L2_EXTERRIRQ_C1 */ + <0xff 75>, /* L2_INTERRIRQ_C0 */ + <0xff 76>, /* L2_INTERRIRQ_C1 */ + <0xff 77>, /* L2SPM_svicInt[0] */ + <0xff 78>, /* L2SPM_svicInt[1] */ + <0xff 79>, /* L2SPM_svicIntSwDone[0] */ + <0xff 80>, /* L2SPM_svicIntSwDone[1] */ + <0xff 81>, /* l2_avs_err[0] */ + <0xff 82>, /* l2_avs_err[1] */ + <0xff 83>, /* l2_avs_ack[0] */ + <0xff 84>, /* l2_avs_ack[1] */ + <0xff 98>, /* o_qm_interrupt */ + <0xff 100>, /* camss_vbif_1_irpt */ + <0xff 101>, /* processor_1_user_int */ + <0xff 102>, /* processor_1_kernel_int */ + <0xff 106>, /* dir_conn_irq_lpa_dsp[2] */ + <0xff 107>, /* dir_conn_irq_lpa_dsp[1] */ + <0xff 109>, /* camss_vbif_0_irpt */ + <0xff 110>, /* csiphy_0_irq */ + <0xff 111>, /* csiphy_1_irq */ + <0xff 112>, /* csiphy_2_irq */ + <0xff 115>, /* mdss_irq */ + <0xff 116>, /* mdss_vbif_irpt */ + <0xff 117>, /* dir_conn_irq_lpa_dsp[0] */ + <0xff 119>, /* lpass_irq_out_apcs[11] */ + <0xff 122>, /* o_pimem_tpdm_bc_irq_ofsat */ + <0xff 123>, /* o_pimem_tpdm_tc_irq_ofsat */ + <0xff 124>, /* dir_conn_irq_sensors[1] */ + <0xff 125>, /* dir_conn_irq_sensors[0] */ + <0xff 127>, /* peripheral_irq[2] */ + <0xff 128>, /* peripheral_irq[3] */ + <0xff 129>, /* peripheral_irq[4] */ + <0xff 130>, /* peripheral_irq[5] */ + <0xff 133>, /* peripheral_irq[2] */ + <0xff 134>, /* peripheral_irq[3] */ + <0xff 135>, /* peripheral_irq[4] */ + <0xff 136>, /* peripheral_irq[5] */ + <0xff 139>, /* peripheral_irq[0] */ + <0xff 140>, /* peripheral_irq[1] */ + <0xff 142>, /* sdcc_irq[0] */ + <0xff 143>, /* sdcc_irq[1] */ + <0xff 144>, /* sdcc_pwr_cmd_irq */ + <0xff 145>, /* peripheral_irq[0] */ + <0xff 146>, /* peripheral_irq[1] */ + <0xff 148>, /* osmmu_CIrpt[4] */ + <0xff 149>, /* osmmu_CIrpt[5] */ + <0xff 150>, /* sdio_wakeup_irq */ + <0xff 151>, /* acvremoval_int */ + <0xff 152>, /* trs_int */ + <0xff 155>, /* dir_conn_irq_lpa_dsp[5] */ + <0xff 156>, /* dir_conn_irq_lpa_dsp[4] */ + <0xff 157>, /* sdcc_irq[0] */ + <0xff 158>, /* sdcc_irq[1] */ + <0xff 159>, /* lpass_irq_out_apcs[39] */ + <0xff 160>, /* lpass_irq_out_apcs[38] */ + <0xff 163>, /* usb30_ctrl_irq[0] */ + <0xff 164>, /* usb30_bam_irq[0] */ + <0xff 165>, /* usb30_hs_phy_irq */ + <0xff 166>, /* o_lm_int_2qgic */ + <0xff 169>, /* lpass_irq_out_apcs[33] */ + <0xff 171>, /* usb20s_hs_phy_irq */ + <0xff 172>, /* dcvs_int[6] */ + <0xff 173>, /* dcvs_int[7] */ + <0xff 175>, /* usb20s_ee1_irq */ + <0xff 176>, /* usb20s_power_event_irq */ + <0xff 184>, /* dir_conn_irq_lpa_dsp[3] */ + <0xff 185>, /* camss_vbif_2_irpt */ + <0xff 186>, /* mnoc_obs_mainfault */ + <0xff 188>, /* lpass_irq_out_apcs[00] */ + <0xff 189>, /* lpass_irq_out_apcs[01] */ + <0xff 190>, /* lpass_irq_out_apcs[02] */ + <0xff 191>, /* lpass_irq_out_apcs[03] */ + <0xff 192>, /* lpass_irq_out_apcs[04] */ + <0xff 193>, /* lpass_irq_out_apcs[05] */ + <0xff 194>, /* lpass_irq_out_apcs[06] */ + <0xff 195>, /* lpass_irq_out_apcs[07] */ + <0xff 196>, /* lpass_irq_out_apcs[08] */ + <0xff 197>, /* lpass_irq_out_apcs[09] */ + <0xff 199>, /* qdss_usb_trace_bam_irq[0] */ + <0xff 200>, /* rpm_ipc[4] */ + <0xff 201>, /* rpm_ipc[5] */ + <0xff 202>, /* rpm_ipc[6] */ + <0xff 203>, /* rpm_ipc[7] */ + <0xff 204>, /* rpm_ipc[20] */ + <0xff 205>, /* rpm_ipc[21] */ + <0xff 206>, /* rpm_ipc[22] */ + <0xff 207>, /* rpm_ipc[23] */ + <0xff 208>, /* lpi_dir_conn_irq_apps[0] */ + <0xff 209>, /* lpi_dir_conn_irq_apps[1] */ + <0xff 210>, /* lpi_dir_conn_irq_apps[2] */ + <0xff 213>, /* secure_wdog_bark_irq */ + <0xff 214>, /* tsens1_tsens_max_min_int */ + <0xff 215>, /* o_bimc_intr[0] */ + <0xff 217>, /* o_ocimem_nonsec_irq */ + <0xff 218>, /* cpr_irq[1] */ + <0xff 219>, /* lpass_irq_out_vmm[00] */ + <0xff 220>, /* spmi_protocol_irq */ + <0xff 221>, /* lpass_irq_out_vmm[01] */ + <0xff 222>, /* lpass_irq_out_vmm[02] */ + <0xff 223>, /* spdm_offline_irq */ + <0xff 224>, /* spdm_realtime_irq[1] */ + <0xff 225>, /* snoc_obs_mainFault */ + <0xff 226>, /* cnoc_obs_mainFault */ + <0xff 227>, /* o_tcsr_xpu3_sec_summary_intr */ + <0xff 228>, /* o_tcsr_xpu3_non_sec_summary_intr */ + <0xff 229>, /* o_timeout_slave_hmss_summary_intr */ + <0xff 230>, /* o_tcsr_vmidmt_client_sec_summary_intr */ + <0xff 231>, /* o_tcsr_vmidmt_client_nsec_summary_intr */ + <0xff 232>, /* o_tcsr_vmidmt_cfg_sec_summary_intr */ + <0xff 233>, /* o_tcsr_vmidmt_cfg_non_sec_summary_intr */ + <0xff 234>, /* lpass_irq_out_vmm[03] */ + <0xff 235>, /* cpr_irq[0] */ + <0xff 236>, /* crypto_core_irq[0] */ + <0xff 237>, /* crypto_core_irq[1] */ + <0xff 238>, /* crypto_bam_irq[0] */ + <0xff 239>, /* crypto_bam_irq[1] */ + <0xff 240>, /* summary_irq_hmss */ + <0xff 241>, /* dir_conn_irq_hmss[7] */ + <0xff 242>, /* dir_conn_irq_hmss[6] */ + <0xff 243>, /* dir_conn_irq_hmss[5] */ + <0xff 244>, /* dir_conn_irq_hmss[4] */ + <0xff 245>, /* dir_conn_irq_hmss[3] */ + <0xff 246>, /* dir_conn_irq_hmss[2] */ + <0xff 247>, /* dir_conn_irq_hmss[1] */ + <0xff 248>, /* dir_conn_irq_hmss[0] */ + <0xff 249>, /* summary_irq_hmss_tz */ + <0xff 250>, /* cpr_irq[3] */ + <0xff 251>, /* cpr_irq[2] */ + <0xff 252>, /* cpr_irq[1] */ + <0xff 253>, /* sdcc_pwr_cmd_irq */ + <0xff 254>, /* sdio_wakeup_irq */ + <0xff 255>, /* cpr_irq[0] */ + <0xff 256>, /* lpass_irq_out_apcs[34] */ + <0xff 257>, /* lpass_irq_out_apcs[35] */ + <0xff 258>, /* lpass_irq_out_apcs[21] */ + <0xff 261>, /* o_tcsr_mmu_nsgcfglrpt_summary_intr */ + <0xff 262>, /* o_tcsr_mmu_gcfglrpt_summary_intr */ + <0xff 263>, /* o_tcsr_mmu_nsglrpt_summary_intr */ + <0xff 264>, /* o_tcsr_mmu_glrpt_summary_intr */ + <0xff 265>, /* vbif_irpt */ + <0xff 266>, /* lpass_irq_out_apcs[20] */ + <0xff 267>, /* lpass_irq_out_apcs[19] */ + <0xff 269>, /* rpm_wdog_expired_irq */ + <0xff 270>, /* bam_irq[0] */ + <0xff 271>, /* bam_irq[0] */ + <0xff 276>, /* mmss_bimc_smmu_cirpt[4] */ + <0xff 277>, /* mmss_bimc_smmu_cirpt[5] */ + <0xff 278>, /* usb30_ctrl_irq[1] */ + <0xff 279>, /* mmss_bimc_smmu_cirpt[6] */ + <0xff 280>, /* mmss_bimc_smmu_cirpt[7] */ + <0xff 281>, /* mmss_bimc_smmu_cirpt[8] */ + <0xff 282>, /* mmss_bimc_smmu_cirpt[9] */ + <0xff 283>, /* mmss_bimc_smmu_cirpt[10] */ + <0xff 284>, /* mmss_bimc_smmu_cirpt[11] */ + <0xff 285>, /* mmss_bimc_smmu_cirpt[12] */ + <0xff 286>, /* mmss_bimc_smmu_cirpt[13] */ + <0xff 287>, /* mmss_bimc_smmu_cirpt[14] */ + <0xff 288>, /* mmss_bimc_smmu_cirpt[15] */ + <0xff 289>, /* ufs_ice_sec_level_irq */ + <0xff 291>, /* lpass_irq_out_apcs[18] */ + <0xff 292>, /* mmss_bimc_smmu_cirpt[16] */ + <0xff 293>, /* mmss_bimc_smmu_cirpt[17] */ + <0xff 294>, /* mmss_bimc_smmu_cirpt[18] */ + <0xff 295>, /* mmss_bimc_smmu_cirpt[0] */ + <0xff 296>, /* mmss_bimc_smmu_pmirpt */ + <0xff 297>, /* ufs_intrq */ + <0xff 298>, /* mmss_bimc_smmu_cirpt[1] */ + <0xff 299>, /* mmss_bimc_smmu_cirpt[2] */ + <0xff 300>, /* mmss_bimc_smmu_cirpt[3] */ + <0xff 301>, /* lpass_irq_out_apcs[17] */ + <0xff 302>, /* qdss_etrbytecnt_irq */ + <0xff 303>, /* lpass_irq_out_apcs[16] */ + <0xff 304>, /* mmss_bimc_smmu_cirpt[19] */ + <0xff 305>, /* mmss_bimc_smmu_cirpt[20] */ + <0xff 306>, /* mmss_bimc_smmu_cirpt[21] */ + <0xff 307>, /* mmss_bimc_smmu_cirpt[22] */ + <0xff 308>, /* mmss_bimc_smmu_cirpt[23] */ + <0xff 316>, /* lpass_irq_out_apcs[13] */ + <0xff 317>, /* rbif_irq */ + <0xff 318>, /* gpu_cc_gpu_cx_gds_hw_ctrl_irq_out */ + <0xff 319>, /* venus0_irq */ + <0xff 323>, /* lpass_irq_out_apcs[14] */ + <0xff 324>, /* lpass_irq_out_apcs[15] */ + <0xff 325>, /* camss_irq18 */ + <0xff 326>, /* camss_irq0 */ + <0xff 327>, /* camss_irq1 */ + <0xff 328>, /* camss_irq2 */ + <0xff 329>, /* camss_irq3 */ + <0xff 330>, /* camss_irq4 */ + <0xff 331>, /* camss_irq5 */ + <0xff 332>, /* GC_SYS_irq[0] */ + <0xff 333>, /* GC_SYS_irq[1] */ + <0xff 334>, /* GC_SYS_irq[2] */ + <0xff 335>, /* GC_SYS_irq[3] */ + <0xff 336>, /* camss_irq13 */ + <0xff 337>, /* camss_irq14 */ + <0xff 338>, /* camss_irq15 */ + <0xff 339>, /* camss_irq16 */ + <0xff 340>, /* camss_irq17 */ + <0xff 341>, /* camss_irq6 */ + <0xff 342>, /* lpass_irq_out_apcs[36] */ + <0xff 345>, /* camss_irq7 */ + <0xff 346>, /* camss_irq8 */ + <0xff 347>, /* camss_irq9 */ + <0xff 348>, /* camss_irq10 */ + <0xff 350>, /* camss_irq12 */ + <0xff 351>, /* lpass_irq_out_apcs[12] */ + <0xff 357>, /* o_pimem_nonfatal_irq */ + <0xff 359>, /* ee1_apps_trustzone_spmi_periph_irq */ + <0xff 360>, /* o_pimem_fatal_irq */ + <0xff 361>, /* osmmu_CIrpt[0] */ + <0xff 362>, /* osmmu_CIrpt[1] */ + <0xff 363>, /* osmmu_CIrpt[2] */ + <0xff 364>, /* osmmu_CIrpt[3] */ + <0xff 365>, /* ipa_irq[0] */ + <0xff 366>, /* osmmu_PMIrpt */ + <0xff 380>, /* qusb2phy_intr */ + <0xff 381>, /* osmmu_CIrpt[6] */ + <0xff 382>, /* osmmu_CIrpt[7] */ + <0xff 385>, /* osmmu_CIrpt[12] */ + <0xff 386>, /* osmmu_CIrpt[13] */ + <0xff 387>, /* osmmu_CIrpt[14] */ + <0xff 388>, /* osmmu_CIrpt[15] */ + <0xff 389>, /* osmmu_CIrpt[16] */ + <0xff 390>, /* osmmu_CIrpt[17] */ + <0xff 391>, /* osmmu_CIrpt[18] */ + <0xff 392>, /* osmmu_CIrpt[19] */ + <0xff 393>, /* o_dcc_crc_fail_int */ + <0xff 404>, /* aggre2noc_obs_mainFault */ + <0xff 405>, /* osmmu_CIrpt[0] */ + <0xff 406>, /* osmmu_CIrpt[1] */ + <0xff 407>, /* osmmu_CIrpt[2] */ + <0xff 408>, /* osmmu_CIrpt[3] */ + <0xff 409>, /* osmmu_CIrpt[4] */ + <0xff 410>, /* osmmu_CIrpt[5] */ + <0xff 411>, /* o_dcc_task_done_int */ + <0xff 412>, /* vsense_apps_alarm_irq */ + <0xff 413>, /* osmmu_PMIrpt */ + <0xff 414>, /* channel0_apps_hlos_trans_done_irq */ + <0xff 415>, /* channel1_apps_trustzone_trans_done_irq */ + <0xff 416>, /* rpm_ipc[28] */ + <0xff 417>, /* rpm_ipc[29] */ + <0xff 418>, /* rpm_ipc[30] */ + <0xff 419>, /* rpm_ipc[31] */ + <0xff 423>, /* lpass_irq_out_apcs[40] */ + <0xff 424>, /* ipa_irq[2] */ + <0xff 425>, /* lpass_irq_out_apcs[22] */ + <0xff 426>, /* lpass_irq_out_apcs[23] */ + <0xff 427>, /* lpass_irq_out_apcs[24] */ + <0xff 428>, /* lpass_irq_out_apcs[25] */ + <0xff 429>, /* lpass_irq_out_apcs[26] */ + <0xff 430>, /* lpass_irq_out_apcs[27] */ + <0xff 431>, /* lpass_irq_out_apcs[28] */ + <0xff 432>, /* lpass_irq_out_apcs[29] */ + <0xff 433>, /* lpass_irq_out_apcs[30] */ + <0xff 434>, /* lpass_irq_out_apcs[31] */ + <0xff 435>, /* lpass_irq_out_apcs[32] */ + <0xff 436>, /* lpass_irq_out_apcs[37] */ + <0xff 445>, /* wcss_apss_ce_intr[0] */ + <0xff 446>, /* wcss_apss_ce_intr[1] */ + <0xff 447>, /* wcss_apss_ce_intr[2] */ + <0xff 448>, /* wcss_apss_ce_intr[3] */ + <0xff 449>, /* wcss_apss_ce_intr[4] */ + <0xff 450>, /* wcss_apss_ce_intr[5] */ + <0xff 452>, /* wcss_apss_ce_intr[6] */ + <0xff 453>, /* wcss_apss_ce_intr[7] */ + <0xff 454>, /* wcss_apss_ce_intr[8] */ + <0xff 455>, /* wcss_apss_ce_intr[9] */ + <0xff 456>, /* wcss_apss_ce_intr[10] */ + <0xff 457>, /* wcss_apss_ce_intr[11] */ + <0xff 458>, /* wcss_apss_status_intr */ + <0xff 462>, /* tsens1_tsens_critical_int */ + <0xff 464>, /* ipa_bam_irq[0] */ + <0xff 465>, /* ipa_bam_irq[2] */ + <0xff 466>, /* ssc_uart_int */ + <0xff 468>, /* cri_cm_irq_tz */ + <0xff 469>, /* cri_cm_irq_hyp */ + <0xff 471>, /* mmss_bimc_smmu_gds_hw_ctrl_irq_out */ + <0xff 472>, /* gcc_gds_hw_ctrl_irq_out */ + <0xff 474>, /* osmmu_CIrpt[20] */ + <0xff 475>, /* osmmu_CIrpt[21] */ + <0xff 476>, /* osmmu_CIrpt[22] */ + <0xff 477>, /* tsens0_tsens_critical_int */ + <0xff 478>, /* tsens0_tsens_max_min_int */ + <0xff 479>, /* osmmu_CIrpt[23] */ + <0xff 480>, /* q6_wdog_expired_irq */ + <0xff 481>, /* mss_ipc_out_irq[4] */ + <0xff 482>, /* mss_ipc_out_irq[5] */ + <0xff 483>, /* mss_ipc_out_irq[6] */ + <0xff 484>, /* mss_ipc_out_irq[7] */ + <0xff 485>, /* mss_ipc_out_irq[28] */ + <0xff 486>, /* mss_ipc_out_irq[29] */ + <0xff 487>, /* mss_ipc_out_irq[30] */ + <0xff 488>, /* mss_ipc_out_irq[31] */ + <0xff 490>, /* tsens0_tsens_upper_lower_int */ + <0xff 491>, /* qspi_irq0 */ + <0xff 492>, /* sdcc_ice_sec_level_irq */ + <0xff 494>, /* osmmu_CIrpt[6] */ + <0xff 495>, /* osmmu_CIrpt[7] */ + <0xff 496>, /* osmmu_CIrpt[8] */ + <0xff 497>, /* osmmu_CIrpt[9] */ + <0xff 498>, /* osmmu_CIrpt[10] */ + <0xff 499>, /* osmmu_CIrpt[11] */ + <0xff 500>, /* osmmu_CIrpt[24] */ + <0xff 501>, /* osmmu_CIrpt[25] */ + <0xff 503>, /* o_bimc_intr[1] */ + <0xff 504>, /* osmmu_CIrpt[26] */ + <0xff 505>, /* osmmu_CIrpt[27] */ + <0xff 506>, /* osmmu_CIrpt[28] */ + <0xff 512>, /* turing_irq_out_vmm[0] */ + <0xff 513>, /* turing_irq_out_vmm[1] */ + <0xff 514>, /* turing_irq_out_vmm[2] */ + <0xff 515>, /* turing_irq_out_vmm[3] */ + <0xff 516>, /* lpass_irq_out_apcs[41] */ + <0xff 517>, /* lpass_irq_out_apcs[42] */ + <0xff 520>, /* lpass_irq_out_apcs[45] */ + <0xff 544>, /* turing_irq_out_apcs[00] */ + <0xff 545>, /* turing_irq_out_apcs[01] */ + <0xff 546>, /* turing_irq_out_apcs[02] */ + <0xff 547>, /* turing_irq_out_apcs[03] */ + <0xff 548>, /* turing_irq_out_apcs[04] */ + <0xff 549>, /* turing_irq_out_apcs[05] */ + <0xff 550>, /* turing_irq_out_apcs[06] */ + <0xff 551>, /* turing_irq_out_apcs[07] */ + <0xff 552>, /* turing_irq_out_apcs[08] */ + <0xff 553>, /* turing_irq_out_apcs[09] */ + <0xff 554>, /* turing_irq_out_apcs[10] */ + <0xff 556>, /* turing_irq_out_apcs[12] */ + <0xff 557>, /* turing_irq_out_apcs[13] */ + <0xff 558>, /* turing_irq_out_apcs[14] */ + <0xff 559>, /* turing_irq_out_apcs[15] */ + <0xff 560>, /* turing_irq_out_apcs[16] */ + <0xff 561>, /* turing_irq_out_apcs[17] */ + <0xff 562>, /* turing_irq_out_apcs[18] */ + <0xff 563>, /* turing_irq_out_apcs[19] */ + <0xff 564>, /* turing_irq_out_apcs[20] */ + <0xff 565>, /* turing_irq_out_apcs[21] */ + <0xff 566>, /* turing_irq_out_apcs[22] */ + <0xff 567>, /* turing_irq_out_apcs[23] */ + <0xff 568>, /* turing_irq_out_apcs[24] */ + <0xff 569>, /* turing_irq_out_apcs[25] */ + <0xff 570>, /* turing_irq_out_apcs[26] */ + <0xff 571>, /* turing_irq_out_apcs[27] */ + <0xff 572>, /* turing_irq_out_apcs[28] */ + <0xff 573>, /* turing_irq_out_apcs[29] */ + <0xff 574>, /* turing_irq_out_apcs[30] */ + <0xff 575>, /* turing_irq_out_apcs[31] */ + <0xff 576>, /* turing_irq_out_apcs[32] */ + <0xff 577>, /* turing_irq_out_apcs[33] */ + <0xff 578>, /* turing_irq_out_apcs[34] */ + <0xff 579>, /* turing_irq_out_apcs[35] */ + <0xff 580>, /* turing_irq_out_apcs[36] */ + <0xff 581>, /* turing_irq_out_apcs[37] */ + <0xff 582>, /* turing_irq_out_apcs[38] */ + <0xff 583>, /* turing_irq_out_apcs[39] */ + <0xff 584>; /* turing_irq_out_apcs[40] */ + + qcom,gpio-parent = <&tlmm>; + qcom,gpio-map = + <3 1>, + <4 5>, + <5 9>, + <6 10>, + <7 66>, + <8 22>, + <9 25>, + <10 28>, + <11 58>, + <13 41>, + <14 43>, + <15 40>, + <16 42>, + <17 46>, + <18 50>, + <19 44>, + <21 56>, + <22 45>, + <23 68>, + <24 69>, + <25 70>, + <26 71>, + <27 72>, + <28 73>, + <29 64>, + <30 2>, + <31 13>, + <32 111>, + <33 74>, + <34 75>, + <35 76>, + <36 82>, + <37 17>, + <38 77>, + <39 47>, + <40 54>, + <41 48>, + <42 101>, + <43 49>, + <44 51>, + <45 86>, + <46 90>, + <47 91>, + <48 52>, + <50 55>, + <51 6>, + <53 65>, + <55 67>, + <56 83>, + <57 84>, + <58 85>, + <59 87>, + <63 21>, + <64 78>, + <65 113>, + <66 60>, + <67 98>, + <68 30>, + <70 31>, + <71 29>, + <76 107>, + <83 109>, + <84 103>, + <85 105>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-pm660a-cdp.dts b/arch/arm/boot/dts/qcom/sdm660-pm660a-cdp.dts new file mode 100644 index 000000000000..7621c8aef432 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-pm660a-cdp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-cdp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A CDP"; + compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp"; + qcom,board-id = <1 0>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-pm660a-mtp.dts b/arch/arm/boot/dts/qcom/sdm660-pm660a-mtp.dts new file mode 100644 index 000000000000..1ea6dbde11ce --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-pm660a-mtp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-mtp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A MTP"; + compatible = "qcom,sdm660-mtp", "qcom,sdm660", "qcom,mtp"; + qcom,board-id = <8 0>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-pm660a-qrd.dts b/arch/arm/boot/dts/qcom/sdm660-pm660a-qrd.dts new file mode 100644 index 000000000000..b1078c53acdf --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-pm660a-qrd.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-qrd.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A QRD"; + compatible = "qcom,sdm660-qrd", "qcom,sdm660", "qcom,qrd"; + qcom,board-id = <0x1000b 0>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-pm660a-rcm.dts b/arch/arm/boot/dts/qcom/sdm660-pm660a-rcm.dts new file mode 100644 index 000000000000..0b65b4a3631c --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-pm660a-rcm.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-cdp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A RCM"; + compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp"; + qcom,board-id = <21 0>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-pm660a-rumi.dts b/arch/arm/boot/dts/qcom/sdm660-pm660a-rumi.dts new file mode 100644 index 000000000000..16f1efb92f74 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-pm660a-rumi.dts @@ -0,0 +1,146 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-pinctrl.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A RUMI"; + compatible = "qcom,sdm660-rumi", "qcom,sdm660", "qcom,rumi"; + qcom,board-id = <15 0>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; + + chosen { + bootargs = "lpm_levels.sleep_disabled=1"; + }; +}; + +&usb3 { + /delete-property/ USB3_GDSC-supply; + /delete-property/ extcon; + dwc3@a800000 { + maximum-speed = "high-speed"; + }; +}; + +&ssphy { + compatible = "usb-nop-xceiv"; +}; + +&qusb_phy0 { + reg = <0x0a928000 0x8000>, + <0x0a8f8800 0x400>, + <0x0a920000 0x100>; + reg-names = "qusb_phy_base", + "qscratch_base", + "emu_phy_base"; + qcom,emulation; + qcom,qusb-phy-init-seq = <0x19 0x1404 + 0x20 0x1414 + 0x79 0x1410 + 0x00 0x1418 + 0x99 0x1404 + 0x04 0x1408 + 0xd9 0x1404>; + qcom,emu-dcm-reset-seq = <0x100000 0x20 + 0x0 0x20 + 0x1a0 0x20 + 0x5 0x14>; +}; + +&uartblsp1dm1 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&sdhc_1 { + /* device core power supply */ + vdd-supply = <&pm660l_l4>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <200 570000>; + + /* device communication power supply */ + vdd-io-supply = <&pm660_l8>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <200 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 192000000 + 384000000>; + + qcom,nonremovable; + qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; + + status = "ok"; +}; + +&clock_gcc { + compatible = "qcom,dummycc"; + clock-output-names = "gcc_clocks"; +}; + +&pm660_charger { + status = "disabled"; +}; + +&pm660_fg { + status = "disabled"; +}; + +&clock_gfx { + compatible = "qcom,dummycc"; + clock-output-names = "gfx_clocks"; +}; + +&pm660_pdphy { + status = "disabled"; +}; + +&clock_mmss { + compatible = "qcom,dummycc"; + clock-output-names = "mmss_clocks"; +}; + +&ufsphy1 { + vdda-phy-supply = <&pm660l_l1>; + vdda-pll-supply = <&pm660_l10>; + vddp-ref-clk-supply = <&pm660_l1>; + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14200>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; +}; + +&ufs1 { + vdd-hba-supply = <&gdsc_ufs>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm660l_l4>; + vccq2-supply = <&pm660_l8>; + vcc-max-microamp = <500000>; + vccq2-max-microamp = <600000>; + qcom,disable-lpm; +}; + +&clock_debug { + compatible = "qcom,dummycc"; + clock-output-names = "debug_clocks"; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-pm660a-sim.dts b/arch/arm/boot/dts/qcom/sdm660-pm660a-sim.dts new file mode 100644 index 000000000000..2e2e1ac3993c --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-pm660a-sim.dts @@ -0,0 +1,111 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-pinctrl.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A SIM"; + compatible = "qcom,sdm660-sim", "qcom,sdm660", "qcom,sim"; + qcom,board-id = <16 0>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; + + chosen { + bootargs = "lpm_levels.sleep_disabled=1"; + }; +}; + +&usb3 { + reg = <0xa800000 0xfc000>; + reg-names = "core_base"; + /delete-property/ extcon; + dwc3@a800000 { + maximum-speed = "high-speed"; + }; +}; + +&ssphy { + compatible = "usb-nop-xceiv"; +}; + +&qusb_phy0 { + compatible = "usb-nop-xceiv"; +}; + +&uartblsp1dm1 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&sdhc_1 { + /* device core power supply */ + vdd-supply = <&pm660l_l4>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <200 570000>; + + /* device communication power supply */ + vdd-io-supply = <&pm660_l8>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <200 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 192000000 + 384000000>; + + qcom,nonremovable; + qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; + + status = "ok"; +}; + +&pm660_charger { + status = "disabled"; +}; + +&pm660_fg { + status = "disabled"; +}; + +&pm660_pdphy { + status = "disabled"; +}; + +&ufsphy1 { + vdda-phy-supply = <&pm660l_l1>; + vdda-pll-supply = <&pm660_l10>; + vddp-ref-clk-supply = <&pm660_l1>; + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14200>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; + status = "ok"; +}; + +&ufs1 { + vdd-hba-supply = <&gdsc_ufs>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm660l_l4>; + vccq2-supply = <&pm660_l8>; + vcc-max-microamp = <500000>; + vccq2-max-microamp = <600000>; + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-qrd.dts b/arch/arm/boot/dts/qcom/sdm660-qrd.dts new file mode 100644 index 000000000000..29fc0d776fd0 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-qrd.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L QRD"; + compatible = "qcom,sdm660-qrd", "qcom,sdm660", "qcom,qrd"; + qcom,board-id = <0x1000b 0>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-qrd.dtsi b/arch/arm/boot/dts/qcom/sdm660-qrd.dtsi new file mode 100644 index 000000000000..115b48568fe9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-qrd.dtsi @@ -0,0 +1,24 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdm660-pinctrl.dtsi" +/ { +}; + +&uartblsp1dm1 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&soc { +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-rcm.dts b/arch/arm/boot/dts/qcom/sdm660-rcm.dts new file mode 100644 index 000000000000..a3f9445d4164 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-rcm.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L RCM"; + compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp"; + qcom,board-id = <21 0>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-regulator.dtsi b/arch/arm/boot/dts/qcom/sdm660-regulator.dtsi new file mode 100644 index 000000000000..4869a8af08d6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-regulator.dtsi @@ -0,0 +1,498 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&rpm_bus { + rpm-regulator-smpa4 { + status = "okay"; + pm660_s4: regulator-s4 { + regulator-min-microvolt = <1805000>; + regulator-max-microvolt = <2040000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa5 { + status = "okay"; + pm660_s5: regulator-s5 { + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa6 { + status = "okay"; + pm660_s6: regulator-s6 { + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <992000>; + status = "okay"; + }; + }; + + rpm-regulator-smpb1 { + status = "okay"; + pm660l_s1: regulator-s1 { + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1125000>; + status = "okay"; + }; + }; + + rpm-regulator-smpb2 { + status = "okay"; + pm660l_s2: regulator-s2 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + status = "okay"; + }; + }; + + /* PM660L S3 + S4 - VDD_CX supply */ + rpm-regulator-smpb3 { + status = "okay"; + pm660l_s3_level: regulator-s3-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_s3_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + pm660l_s3_floor_level: regulator-s3-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_s3_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + pm660l_s3_level_ao: regulator-s3-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_s3_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + /* PM660L S5 - VDD_MX supply */ + rpm-regulator-smpb5 { + status = "okay"; + pm660l_s5_level: regulator-s5-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_s5_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + pm660l_s5_floor_level: regulator-s5-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_s5_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + pm660l_s5_level_ao: regulator-s5-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_s5_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + rpm-regulator-ldoa1 { + status = "okay"; + pm660_l1: regulator-l1 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + pm660_l2: regulator-l2 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1010000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + status = "okay"; + pm660_l3: regulator-l3 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1010000>; + status = "okay"; + }; + }; + + /* TODO: remove if ADRASTEA CX/MX not voted from APPS */ + rpm-regulator-ldoa5 { + status = "okay"; + pm660_l5: regulator-l5 { + regulator-min-microvolt = <525000>; + regulator-max-microvolt = <950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + pm660_l6: regulator-l6 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1370000>; + status = "okay"; + }; + + pm660_l6_pin_ctrl: regulator-l6-pin-ctrl { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660_l6_pin_ctrl"; + qcom,set = <3>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1370000>; + /* Force NPM follows HW_EN1 */ + qcom,init-pin-ctrl-mode = <2>; + /* Enable follows HW_EN1 */ + qcom,enable-with-pin-ctrl = <0 2>; + }; + }; + + rpm-regulator-ldoa7 { + status = "okay"; + pm660_l7: regulator-l7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa8 { + status = "okay"; + pm660_l8: regulator-l8 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1900000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa9 { + status = "okay"; + pm660_l9: regulator-l9 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1900000>; + status = "okay"; + }; + + pm660_l9_pin_ctrl: regulator-l9-pin-ctrl { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660_l9_pin_ctrl"; + qcom,set = <3>; + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1900000>; + /* Force NPM follows HW_EN1 */ + qcom,init-pin-ctrl-mode = <2>; + /* Enable follows HW_EN1 */ + qcom,enable-with-pin-ctrl = <0 2>; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + pm660_l10: regulator-l10 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa11 { + status = "okay"; + pm660_l11: regulator-l11 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + pm660_l12: regulator-l12 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa13 { + status = "okay"; + pm660_l13: regulator-l13 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa14 { + status = "okay"; + pm660_l14: regulator-l14 { + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1900000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa15 { + status = "okay"; + pm660_l15: regulator-l15 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa17 { + status = "okay"; + pm660_l17: regulator-l17 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa19 { + status = "okay"; + pm660_l19: regulator-l19 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + status = "okay"; + }; + + pm660_l19_pin_ctrl: regulator-l19-pin-ctrl { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660_l19_pin_ctrl"; + qcom,set = <3>; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + /* Force NPM follows HW_EN1 */ + qcom,init-pin-ctrl-mode = <2>; + /* Enable follows HW_EN1 */ + qcom,enable-with-pin-ctrl = <0 2>; + }; + }; + + rpm-regulator-ldob1 { + status = "okay"; + pm660l_l1: regulator-l1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <925000>; + status = "okay"; + }; + }; + + rpm-regulator-ldob2 { + status = "okay"; + pm660l_l2: regulator-l2 { + regulator-min-microvolt = <350000>; + regulator-max-microvolt = <3100000>; + status = "okay"; + }; + }; + + rpm-regulator-ldob3 { + status = "okay"; + pm660l_l3: regulator-l3 { + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <3600000>; + status = "okay"; + }; + }; + + rpm-regulator-ldob4 { + status = "okay"; + pm660l_l4: regulator-l4 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldob5 { + status = "okay"; + pm660l_l5: regulator-l5 { + regulator-min-microvolt = <1721000>; + regulator-max-microvolt = <3600000>; + status = "okay"; + }; + }; + + rpm-regulator-ldob6 { + status = "okay"; + pm660l_l6: regulator-l6 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3300000>; + status = "okay"; + }; + }; + + rpm-regulator-ldob7 { + status = "okay"; + pm660l_l7: regulator-l7 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3125000>; + status = "okay"; + }; + }; + + rpm-regulator-ldob8 { + status = "okay"; + pm660l_l8: regulator-l8 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + status = "okay"; + }; + }; + + /* PM660L L9 = VDD_SSC_CX supply */ + rpm-regulator-ldob9 { + status = "okay"; + pm660l_l9_level: regulator-l9-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_l9_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + pm660l_l9_floor_level: regulator-l9-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_l9_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + }; + + /* PM660L L10 = VDD_SSC_MX supply */ + rpm-regulator-ldob10 { + status = "okay"; + pm660l_l10_level: regulator-l10-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_l10_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + pm660l_l10_floor_level: regulator-l10-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_l10_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + }; + + rpm-regulator-bobb { + status = "okay"; + pm660l_bob: regulator-bob { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + status = "okay"; + }; + + pm660l_bob_pin1: regulator-bob-pin1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_bob_pin1"; + qcom,set = <3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + qcom,use-pin-ctrl-voltage1; + }; + + pm660l_bob_pin2: regulator-bob-pin2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_bob_pin2"; + qcom,set = <3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + qcom,use-pin-ctrl-voltage2; + }; + + pm660l_bob_pin3: regulator-bob-pin3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_bob_pin3"; + qcom,set = <3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + qcom,use-pin-ctrl-voltage3; + }; + }; +}; + +&pm660_charger { + smb2_vbus: qcom,smb2-vbus { + regulator-name = "smb2-vbus"; + }; + + smb2_vconn: qcom,smb2-vconn { + regulator-name = "smb2-vconn"; + }; +}; + +/* Stub regulators */ +/ { + /* GFX Supply */ + gfx_vreg_corner: regulator-gfx-corner { + compatible = "qcom,stub-regulator"; + regulator-name = "gfx_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-rumi.dts b/arch/arm/boot/dts/qcom/sdm660-rumi.dts new file mode 100644 index 000000000000..f5759b6af7fd --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-rumi.dts @@ -0,0 +1,146 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-pinctrl.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L RUMI"; + compatible = "qcom,sdm660-rumi", "qcom,sdm660", "qcom,rumi"; + qcom,board-id = <15 0>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; + + chosen { + bootargs = "lpm_levels.sleep_disabled=1"; + }; +}; + +&usb3 { + /delete-property/ USB3_GDSC-supply; + /delete-property/ extcon; + dwc3@a800000 { + maximum-speed = "high-speed"; + }; +}; + +&ssphy { + compatible = "usb-nop-xceiv"; +}; + +&qusb_phy0 { + reg = <0x0a928000 0x8000>, + <0x0a8f8800 0x400>, + <0x0a920000 0x100>; + reg-names = "qusb_phy_base", + "qscratch_base", + "emu_phy_base"; + qcom,emulation; + qcom,qusb-phy-init-seq = <0x19 0x1404 + 0x20 0x1414 + 0x79 0x1410 + 0x00 0x1418 + 0x99 0x1404 + 0x04 0x1408 + 0xd9 0x1404>; + qcom,emu-dcm-reset-seq = <0x100000 0x20 + 0x0 0x20 + 0x1a0 0x20 + 0x5 0x14>; +}; + +&uartblsp1dm1 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&sdhc_1 { + /* device core power supply */ + vdd-supply = <&pm660l_l4>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <200 570000>; + + /* device communication power supply */ + vdd-io-supply = <&pm660_l8>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <200 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 192000000 + 384000000>; + + qcom,nonremovable; + qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; + + status = "ok"; +}; + +&clock_gcc { + compatible = "qcom,dummycc"; + clock-output-names = "gcc_clocks"; +}; + +&pm660_charger { + status = "disabled"; +}; + +&pm660_fg { + status = "disabled"; +}; + +&clock_gfx { + compatible = "qcom,dummycc"; + clock-output-names = "gfx_clocks"; +}; + +&pm660_pdphy { + status = "disabled"; +}; + +&clock_mmss { + compatible = "qcom,dummycc"; + clock-output-names = "mmss_clocks"; +}; + +&ufsphy1 { + vdda-phy-supply = <&pm660l_l1>; + vdda-pll-supply = <&pm660_l10>; + vddp-ref-clk-supply = <&pm660_l1>; + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14200>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; +}; + +&ufs1 { + vdd-hba-supply = <&gdsc_ufs>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm660l_l4>; + vccq2-supply = <&pm660_l8>; + vcc-max-microamp = <500000>; + vccq2-max-microamp = <600000>; + qcom,disable-lpm; +}; + +&clock_debug { + compatible = "qcom,dummycc"; + clock-output-names = "debug_clocks"; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-sim.dts b/arch/arm/boot/dts/qcom/sdm660-sim.dts new file mode 100644 index 000000000000..bb896cb7437d --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-sim.dts @@ -0,0 +1,111 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-pinctrl.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L SIM"; + compatible = "qcom,sdm660-sim", "qcom,sdm660", "qcom,sim"; + qcom,board-id = <16 0>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; + + chosen { + bootargs = "lpm_levels.sleep_disabled=1"; + }; +}; + +&usb3 { + reg = <0xa800000 0xfc000>; + reg-names = "core_base"; + /delete-property/ extcon; + dwc3@a800000 { + maximum-speed = "high-speed"; + }; +}; + +&ssphy { + compatible = "usb-nop-xceiv"; +}; + +&qusb_phy0 { + compatible = "usb-nop-xceiv"; +}; + +&uartblsp1dm1 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&sdhc_1 { + /* device core power supply */ + vdd-supply = <&pm660l_l4>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <200 570000>; + + /* device communication power supply */ + vdd-io-supply = <&pm660_l8>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <200 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 192000000 + 384000000>; + + qcom,nonremovable; + qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; + + status = "ok"; +}; + +&pm660_charger { + status = "disabled"; +}; + +&pm660_fg { + status = "disabled"; +}; + +&pm660_pdphy { + status = "disabled"; +}; + +&ufsphy1 { + vdda-phy-supply = <&pm660l_l1>; + vdda-pll-supply = <&pm660_l10>; + vddp-ref-clk-supply = <&pm660_l1>; + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14200>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; + status = "ok"; +}; + +&ufs1 { + vdd-hba-supply = <&gdsc_ufs>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm660l_l4>; + vccq2-supply = <&pm660_l8>; + vcc-max-microamp = <500000>; + vccq2-max-microamp = <600000>; + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-smp2p.dtsi b/arch/arm/boot/dts/qcom/sdm660-smp2p.dtsi new file mode 100644 index 000000000000..b43fae954ec2 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-smp2p.dtsi @@ -0,0 +1,244 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +&soc { + qcom,smp2p-modem@17911008 { + compatible = "qcom,smp2p"; + reg = <0x17911008 0x4>; + qcom,remote-pid = <1>; + qcom,irq-bitmask = <0x4000>; + interrupts = <0 451 1>; + }; + + qcom,smp2p-adsp@17911008 { + compatible = "qcom,smp2p"; + reg = <0x17911008 0x4>; + qcom,remote-pid = <2>; + qcom,irq-bitmask = <0x400>; + interrupts = <0 158 1>; + }; + + qcom,smp2p-cdsp@17911008 { + compatible = "qcom,smp2p"; + reg = <0x17911008 0x4>; + qcom,remote-pid = <5>; + qcom,irq-bitmask = <0x40000000>; + interrupts = <0 514 1>; + }; + + smp2pgpio_smp2p_15_in: qcom,smp2pgpio-smp2p-15-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <15>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_15_in { + compatible = "qcom,smp2pgpio_test_smp2p_15_in"; + gpios = <&smp2pgpio_smp2p_15_in 0 0>; + }; + + smp2pgpio_smp2p_15_out: qcom,smp2pgpio-smp2p-15-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <15>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_15_out { + compatible = "qcom,smp2pgpio_test_smp2p_15_out"; + gpios = <&smp2pgpio_smp2p_15_out 0 0>; + }; + + smp2pgpio_smp2p_1_in: qcom,smp2pgpio-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_in { + compatible = "qcom,smp2pgpio_test_smp2p_1_in"; + gpios = <&smp2pgpio_smp2p_1_in 0 0>; + }; + + smp2pgpio_smp2p_1_out: qcom,smp2pgpio-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_1_out { + compatible = "qcom,smp2pgpio_test_smp2p_1_out"; + gpios = <&smp2pgpio_smp2p_1_out 0 0>; + }; + + smp2pgpio_smp2p_2_in: qcom,smp2pgpio-smp2p-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_in { + compatible = "qcom,smp2pgpio_test_smp2p_2_in"; + gpios = <&smp2pgpio_smp2p_2_in 0 0>; + }; + + smp2pgpio_smp2p_2_out: qcom,smp2pgpio-smp2p-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_2_out { + compatible = "qcom,smp2pgpio_test_smp2p_2_out"; + gpios = <&smp2pgpio_smp2p_2_out 0 0>; + }; + + smp2pgpio_sleepstate_2_out: qcom,smp2pgpio-sleepstate-gpio-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "sleepstate"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio-sleepstate-2-out { + compatible = "qcom,smp2pgpio-sleepstate-out"; + gpios = <&smp2pgpio_sleepstate_2_out 0 0>; + }; + + smp2pgpio_smp2p_5_in: qcom,smp2pgpio-smp2p-5-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <5>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_5_in { + compatible = "qcom,smp2pgpio_test_smp2p_5_in"; + gpios = <&smp2pgpio_smp2p_5_in 0 0>; + }; + + smp2pgpio_smp2p_5_out: qcom,smp2pgpio-smp2p-5-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "smp2p"; + qcom,remote-pid = <5>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + qcom,smp2pgpio_test_smp2p_5_out { + compatible = "qcom,smp2pgpio_test_smp2p_5_out"; + gpios = <&smp2pgpio_smp2p_5_out 0 0>; + }; + + /* ssr - inbound entry from mss */ + smp2pgpio_ssr_smp2p_1_in: qcom,smp2pgpio-ssr-smp2p-1-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <1>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* ssr - outbound entry to mss */ + smp2pgpio_ssr_smp2p_1_out: qcom,smp2pgpio-ssr-smp2p-1-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* ssr - inbound entry from lpass */ + smp2pgpio_ssr_smp2p_2_in: qcom,smp2pgpio-ssr-smp2p-2-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <2>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* ssr - outbound entry to lpass */ + smp2pgpio_ssr_smp2p_2_out: qcom,smp2pgpio-ssr-smp2p-2-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* ssr - inbound entry from turing */ + smp2pgpio_ssr_smp2p_5_in: qcom,smp2pgpio-ssr-smp2p-5-in { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "slave-kernel"; + qcom,remote-pid = <5>; + qcom,is-inbound; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* ssr - outbound entry to turing */ + smp2pgpio_ssr_smp2p_5_out: qcom,smp2pgpio-ssr-smp2p-5-out { + compatible = "qcom,smp2pgpio"; + qcom,entry-name = "master-kernel"; + qcom,remote-pid = <5>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-vidc.dtsi b/arch/arm/boot/dts/qcom/sdm660-vidc.dtsi new file mode 100644 index 000000000000..8e5561da5deb --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-vidc.dtsi @@ -0,0 +1,264 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + + +&soc { + msm_vidc: qcom,vidc@cc00000 { + compatible = "qcom,msm-vidc"; + status = "ok"; + reg = <0xcc00000 0x100000>; + interrupts = ; + qcom,hfi = "venus"; + qcom,hfi-version = "3xx"; + qcom,firmware-name = "venus"; + qcom,sw-power-collapse; + qcom,reg-presets = + <0x80010 0x00000003>, + <0x80018 0x05555556>, + <0x8001c 0x05555556>; + + qcom,max-hw-load = <1036800>; /* Full 4k @ 30 */ + qcom,allowed-clock-rates = + /* TURBO NOM+ NOM + * SVS+ SVS SVS- + */ + <518400000 441600000 404000000 + 320000000 269330000 133330000>; + + qcom,dcvs-tbl = + /* Dec UHD@30 All decoder - NOM to SVS+ */ + <897600 734400 979200 0x3f00000c>, + + /* Dec DCI@24 HEVC - NOM to SVS+ */ + <816000 734400 829440 0x0c000000>, + + /* Enc UHD@30 H264/HEVC - TURBO to NOM+ */ + <897600 897600 979200 0x4000004>; + qcom,dcvs-limit = + <32400 30>, /* Encoder UHD */ + <32400 24>; /* Decoder UHD */ + + /* Regulators */ + smmu-vdd-supply = <&gdsc_bimc_smmu>; + venus-supply = <&gdsc_venus>; + venus-core0-supply = <&gdsc_venus_core0>; + + /* Clocks */ + clock-names = "gcc_mmss_sys_noc_axi_clk", + "mmssnoc_axi_clk", "mmss_mnoc_ahb_clk", + "mmss_bimc_smmu_ahb_clk", "mmss_bimc_smmu_axi_clk", + "mmss_video_core_clk", "mmss_video_ahb_clk", + "mmss_video_axi_clk", + "mmss_video_core0_clk"; + clocks = <&clock_gcc GCC_MMSS_SYS_NOC_AXI_CLK>, + <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_VIDEO_CORE_CLK>, + <&clock_mmss MMSS_VIDEO_AHB_CLK>, + <&clock_mmss MMSS_VIDEO_AXI_CLK>, + <&clock_mmss MMSS_VIDEO_SUBCORE0_CLK>; + qcom,clock-configs = <0x0 0x0 0x0 0x0 0x0 + 0x3 0x0 0x2 0x3>; + + /* Buses */ + bus_cnoc { + compatible = "qcom,msm-vidc,bus"; + label = "cnoc"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1 1>; + }; + + venus_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-ddr"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "venus-ddr-gov"; + qcom,bus-range-kbps = <1000 2365000>; + }; + + arm9_bus_ddr { + compatible = "qcom,msm-vidc,bus"; + label = "venus-arm9-ddr"; + qcom,bus-master = ; + qcom,bus-slave = ; + qcom,bus-governor = "performance"; + qcom,bus-range-kbps = <1 1>; + }; + + qcom,clock-freq-tbl { + qcom,profile-enc { + qcom,codec-mask = <0x55555555>; + qcom,cycles-per-mb = <863>; + qcom,low-power-mode-factor = <35616>; + }; + qcom,profile-dec { + qcom,codec-mask = <0xf3ffffff>; + qcom,cycles-per-mb = <355>; + }; + qcom,profile-hevcdec { + qcom,codec-mask = <0x0c000000>; + qcom,cycles-per-mb = <400>; + }; + }; + + venus-ddr-gov { + compatible = "qcom,msm-vidc,governor,table"; + name = "venus-ddr-gov"; + status = "ok"; + qcom,bus-freq-table { + qcom,profile-enc { + qcom,codec-mask = <0x55555555>; + qcom,load-busfreq-tbl = + <979200 1044000>, /* UHD30E */ + <864000 887000>, /* 720p240LPE */ + <489600 666000>, /* 1080p60E */ + <432000 578000>, /* 720p120E */ + <244800 346000>, /* 1080p30E */ + <216000 293000>, /* 720p60E */ + <108000 151000>, /* 720p30E */ + <0 0>; + }; + qcom,profile-dec { + qcom,codec-mask = <0xffffffff>; + qcom,load-busfreq-tbl = + <979200 2365000>, /* UHD30D */ + <864000 1978000>, /* 720p240D */ + <489600 1133000>, /* 1080p60D */ + <432000 994000>, /* 720p120D */ + <244800 580000>, /* 1080p30D */ + <216000 501000>, /* 720p60E */ + <108000 255000>, /* 720p30D */ + <0 0>; + }; + qcom,profile-dec-ubwc { + qcom,codec-mask = <0xffffffff>; + qcom,ubwc-mode; + qcom,load-busfreq-tbl = + <979200 1892000>, /* UHD30D */ + <864000 1554000>, /* 720p240D */ + <489600 895000>, /* 1080p60D */ + <432000 781000>, /* 720p120D */ + <244800 460000>, /* 1080p30D */ + <216000 301000>, /* 720p60E */ + <108000 202000>, /* 720p30D */ + <0 0>; + }; + qcom,profile-dec-ubwc-10bit { + qcom,codec-mask = <0xffffffff>; + qcom,ubwc-10bit; + qcom,load-busfreq-tbl = + <979200 2446336>, /* UHD30D */ + <864000 2108416>, /* 720p240D */ + <489600 1207296>, /* 1080p60D */ + <432000 1058816>, /* 720p120D */ + <244800 616448>, /* 1080p30D */ + <216000 534528>, /* 720p60D */ + <108000 271360>, /* 720p30D */ + <0 0>; + }; + }; + }; + + + /* MMUs */ + non_secure_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_ns"; + iommus = + <&mmss_bimc_smmu 0x400>, + <&mmss_bimc_smmu 0x401>, + <&mmss_bimc_smmu 0x40a>, + <&mmss_bimc_smmu 0x407>, + <&mmss_bimc_smmu 0x40e>, + <&mmss_bimc_smmu 0x40f>, + <&mmss_bimc_smmu 0x408>, + <&mmss_bimc_smmu 0x409>, + <&mmss_bimc_smmu 0x40b>, + <&mmss_bimc_smmu 0x40c>, + <&mmss_bimc_smmu 0x40d>, + <&mmss_bimc_smmu 0x410>, + <&mmss_bimc_smmu 0x421>, + <&mmss_bimc_smmu 0x428>, + <&mmss_bimc_smmu 0x429>, + <&mmss_bimc_smmu 0x42b>, + <&mmss_bimc_smmu 0x42c>, + <&mmss_bimc_smmu 0x42d>, + <&mmss_bimc_smmu 0x411>, + <&mmss_bimc_smmu 0x431>; + buffer-types = <0xfff>; + virtual-addr-pool = <0x70800000 0x6f800000>; + }; + + firmware_cb { + compatible = "qcom,msm-vidc,context-bank"; + qcom,fw-context-bank; + iommus = <&mmss_bimc_smmu 0x580>, + <&mmss_bimc_smmu 0x586>; + }; + secure_bitstream_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_bitstream"; + iommus = <&mmss_bimc_smmu 0x500>, + <&mmss_bimc_smmu 0x502>, + <&mmss_bimc_smmu 0x509>, + <&mmss_bimc_smmu 0x50a>, + <&mmss_bimc_smmu 0x50b>, + <&mmss_bimc_smmu 0x50e>, + <&mmss_bimc_smmu 0x526>, + <&mmss_bimc_smmu 0x529>, + <&mmss_bimc_smmu 0x52b>; + buffer-types = <0x241>; + virtual-addr-pool = <0x4b000000 0x25800000>; + qcom,secure-context-bank; + }; + + venus_secure_pixel_cb: secure_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_pixel"; + iommus = <&mmss_bimc_smmu 0x504>, + <&mmss_bimc_smmu 0x50c>, + <&mmss_bimc_smmu 0x510>, + <&mmss_bimc_smmu 0x52c>; + buffer-types = <0x106>; + virtual-addr-pool = <0x25800000 0x25800000>; + qcom,secure-context-bank; + }; + + venus_secure_non_pixel_cb: secure_non_pixel_cb { + compatible = "qcom,msm-vidc,context-bank"; + label = "venus_sec_non_pixel"; + iommus = <&mmss_bimc_smmu 0x505>, + <&mmss_bimc_smmu 0x507>, + <&mmss_bimc_smmu 0x508>, + <&mmss_bimc_smmu 0x50d>, + <&mmss_bimc_smmu 0x50f>, + <&mmss_bimc_smmu 0x525>, + <&mmss_bimc_smmu 0x528>, + <&mmss_bimc_smmu 0x52d>, + <&mmss_bimc_smmu 0x540>; + buffer-types = <0x480>; + virtual-addr-pool = <0x1000000 0x24800000>; + qcom,secure-context-bank; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-wcd.dtsi b/arch/arm/boot/dts/qcom/sdm660-wcd.dtsi new file mode 100644 index 000000000000..006bf0175874 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-wcd.dtsi @@ -0,0 +1,197 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&slim_aud { + tasha_codec { + wsa_spkr_sd1: msm_cdc_pinctrll { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-1 = <&spkr_1_sd_n_sleep>; + }; + + wsa_spkr_sd2: msm_cdc_pinctrlr { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_2_sd_n_active>; + pinctrl-1 = <&spkr_2_sd_n_sleep>; + }; + + tasha_hph_en0: msm_cdc_pinctrl_hph_en0 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&hph_en0_active>; + pinctrl-1 = <&hph_en0_sleep>; + }; + + tasha_hph_en1: msm_cdc_pinctrl_hph_en1 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&hph_en1_active>; + pinctrl-1 = <&hph_en1_sleep>; + }; + }; + + tavil_codec { + wcd: wcd_pinctrl@5 { + compatible = "qcom,wcd-pinctrl"; + qcom,num-gpios = <5>; + gpio-controller; + #gpio-cells = <2>; + + us_euro_sw_wcd_active: us_euro_sw_wcd_active { + mux { + pins = "gpio1"; + }; + + config { + pins = "gpio1"; + output-high; + }; + }; + + us_euro_sw_wcd_sleep: us_euro_sw_wcd_sleep { + mux { + pins = "gpio1"; + }; + + config { + pins = "gpio1"; + output-low; + }; + }; + + spkr_1_wcd_en_active: spkr_1_wcd_en_active { + mux { + pins = "gpio2"; + }; + + config { + pins = "gpio2"; + output-high; + }; + }; + + spkr_1_wcd_en_sleep: spkr_1_wcd_en_sleep { + mux { + pins = "gpio2"; + }; + + config { + pins = "gpio2"; + input-enable; + }; + }; + + spkr_2_wcd_en_active: spkr_2_sd_n_active { + mux { + pins = "gpio3"; + }; + + config { + pins = "gpio3"; + output-high; + }; + }; + + spkr_2_wcd_en_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio3"; + }; + + config { + pins = "gpio3"; + input-enable; + }; + }; + + hph_en0_wcd_active: hph_en0_wcd_active { + mux { + pins = "gpio4"; + }; + + config { + pins = "gpio4"; + output-high; + }; + }; + + hph_en0_wcd_sleep: hph_en0_wcd_sleep { + mux { + pins = "gpio4"; + }; + + config { + pins = "gpio4"; + output-low; + }; + }; + + hph_en1_wcd_active: hph_en1_wcd_active { + mux { + pins = "gpio5"; + }; + + config { + pins = "gpio5"; + output-high; + }; + }; + + hph_en1_wcd_sleep: hph_en1_wcd_sleep { + mux { + pins = "gpio5"; + }; + + config { + pins = "gpio5"; + output-low; + }; + }; + }; + + wsa_spkr_wcd_sd1: msm_cdc_pinctrll { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_wcd_en_active>; + pinctrl-1 = <&spkr_1_wcd_en_sleep>; + }; + + wsa_spkr_wcd_sd2: msm_cdc_pinctrlr { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_2_wcd_en_active>; + pinctrl-1 = <&spkr_2_wcd_en_sleep>; + }; + + tavil_us_euro_sw: msm_cdc_pinctrl_us_euro_sw { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&us_euro_sw_wcd_active>; + pinctrl-1 = <&us_euro_sw_wcd_sleep>; + }; + + tavil_hph_en0: msm_cdc_pinctrl_hph_en0 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&hph_en0_wcd_active>; + pinctrl-1 = <&hph_en0_wcd_sleep>; + }; + + tavil_hph_en1: msm_cdc_pinctrl_hph_en1 { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&hph_en1_wcd_active>; + pinctrl-1 = <&hph_en1_wcd_sleep>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-wsa881x.dtsi b/arch/arm/boot/dts/qcom/sdm660-wsa881x.dtsi new file mode 100644 index 000000000000..a71aa7ded60b --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-wsa881x.dtsi @@ -0,0 +1,79 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdm660-wcd.dtsi" + +&slim_aud { + tasha_codec { + swr_master { + compatible = "qcom,swr-wcd"; + #address-cells = <2>; + #size-cells = <0>; + + wsa881x_211: wsa881x@20170211 { + compatible = "qcom,wsa881x"; + reg = <0x0 0x20170211>; + qcom,spkr-sd-n-node = <&wsa_spkr_sd1>; + }; + + wsa881x_212: wsa881x@20170212 { + compatible = "qcom,wsa881x"; + reg = <0x0 0x20170212>; + qcom,spkr-sd-n-node = <&wsa_spkr_sd2>; + }; + + wsa881x_213: wsa881x@21170213 { + compatible = "qcom,wsa881x"; + reg = <0x0 0x21170213>; + qcom,spkr-sd-n-node = <&wsa_spkr_sd1>; + }; + + wsa881x_214: wsa881x@21170214 { + compatible = "qcom,wsa881x"; + reg = <0x0 0x21170214>; + qcom,spkr-sd-n-node = <&wsa_spkr_sd2>; + }; + }; + }; + + tavil_codec { + swr_master { + compatible = "qcom,swr-wcd"; + #address-cells = <2>; + #size-cells = <0>; + + wsa881x_0211: wsa881x@20170211 { + compatible = "qcom,wsa881x"; + reg = <0x0 0x20170211>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>; + }; + + wsa881x_0212: wsa881x@20170212 { + compatible = "qcom,wsa881x"; + reg = <0x0 0x20170212>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd2>; + }; + + wsa881x_0213: wsa881x@21170213 { + compatible = "qcom,wsa881x"; + reg = <0x0 0x21170213>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>; + }; + + wsa881x_0214: wsa881x@21170214 { + compatible = "qcom,wsa881x"; + reg = <0x0 0x21170214>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd2>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660.dtsi b/arch/arm/boot/dts/qcom/sdm660.dtsi new file mode 100644 index 000000000000..856608e4e47a --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660.dtsi @@ -0,0 +1,2278 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "skeleton64.dtsi" +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. SDM 660"; + compatible = "qcom,sdm660"; + qcom,msm-id = <317 0x0>; + interrupt-parent = <&intc>; + + aliases { + serial0 = &uartblsp1dm1; + sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ + }; + + chosen { + stdout-path = "serial0"; + bootargs = "rcupdate.rcu_expedited=1"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + qcom,limits-info = <&mitigation_profile0>; + qcom,ea = <&ea0>; + efficiency = <1024>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + /* A53 L2 dump not supported */ + qcom,dump-size = <0x0>; + }; + L1_I_0: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + L1_D_0: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + qcom,limits-info = <&mitigation_profile0>; + qcom,ea = <&ea1>; + efficiency = <1024>; + next-level-cache = <&L2_0>; + L1_I_1: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + L1_D_1: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + qcom,limits-info = <&mitigation_profile0>; + qcom,ea = <&ea2>; + efficiency = <1024>; + next-level-cache = <&L2_0>; + L1_I_2: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + L1_D_2: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + qcom,limits-info = <&mitigation_profile0>; + qcom,ea = <&ea3>; + efficiency = <1024>; + next-level-cache = <&L2_0>; + L1_I_3: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + L1_D_3: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x9040>; + }; + }; + + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + qcom,limits-info = <&mitigation_profile1>; + qcom,ea = <&ea4>; + efficiency = <1536>; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + }; + L1_I_100: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + L1_D_100: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + }; + + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + qcom,limits-info = <&mitigation_profile2>; + qcom,ea = <&ea5>; + efficiency = <1536>; + next-level-cache = <&L2_1>; + L1_I_101: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + L1_D_101: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + }; + + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x102>; + enable-method = "psci"; + qcom,limits-info = <&mitigation_profile3>; + qcom,ea = <&ea6>; + efficiency = <1536>; + next-level-cache = <&L2_1>; + L1_I_102: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + L1_D_102: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + }; + + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x103>; + enable-method = "psci"; + qcom,limits-info = <&mitigation_profile4>; + qcom,ea = <&ea7>; + efficiency = <1536>; + next-level-cache = <&L2_1>; + L1_I_103: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + L1_D_103: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x12000>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; + + clocks { + xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "xo_board"; + }; + + sleep_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32764>; + clock-output-names = "sleep_clk"; + }; + }; + + soc: soc { }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + removed_regions: removed_regions@85800000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x85800000 0x0 0x3700000>; + }; + + modem_fw_mem: modem_fw_region@8ac00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x8ac00000 0x0 0x7e00000>; + }; + + adsp_fw_mem: adsp_fw_region@92a00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x92a00000 0x0 0x1e00000>; + }; + + cdsp_fw_mem: cdsp_fw_region@94800000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x94800000 0x0 0x600000>; + }; + + venus_fw_mem: venus_fw_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x80000000 0x0 0x20000000>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x800000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x400000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + secure_display_memory: secure_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x5c00000>; + }; + }; + + bluetooth: bt_wcn3990 { + compatible = "qca,wcn3990"; + qca,bt-vdd-core-supply = <&pm660_l9_pin_ctrl>; + qca,bt-vdd-pa-supply = <&pm660_l6_pin_ctrl>; + qca,bt-vdd-ldo-supply = <&pm660_l19_pin_ctrl>; + qca,bt-chip-pwd-supply = <&pm660l_bob_pin1>; + clocks = <&clock_rpmcc RPM_RF_CLK1>; + clock-names = "rf_clk1"; + + qca,bt-vdd-core-voltage-level = <1800000 1900000>; + qca,bt-vdd-pa-voltage-level = <1304000 1370000>; + qca,bt-vdd-ldo-voltage-level = <3312000 3400000>; + qca,bt-chip-pwd-voltage-level = <3600000 3600000>; + + qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */ + }; +}; + +#include "sdm660-smp2p.dtsi" +#include "sdm660-coresight.dtsi" +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17b00000 0x100000>; /* GICR * 8 */ + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + interrupts = <1 9 4>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 1 0xf08>, + <1 2 0xf08>, + <1 3 0xf08>, + <1 0 0xf08>; + clock-frequency = <19200000>; + }; + + dma_blsp1: qcom,sps-dma@0xc144000{ /* BLSP1 */ + #dma-cells = <4>; + compatible = "qcom,sps-dma"; + reg = <0xc144000 0x1F000>; + interrupts = <0 238 0>; + qcom,summing-threshold = <0x10>; + }; + + dma_blsp2: qcom,sps-dma@0xc184000{ /* BLSP2 */ + #dma-cells = <4>; + compatible = "qcom,sps-dma"; + reg = <0xc184000 0x1F000>; + interrupts = <0 239 0>; + qcom,summing-threshold = <0x10>; + }; + + restart@10ac000 { + compatible = "qcom,pshold"; + reg = <0x10ac000 0x4>, + <0x1fd3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + spmi_bus: qcom,spmi@800f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x800f000 0x1000>, + <0x8400000 0x1000000>, + <0x9400000 0x1000000>, + <0xa400000 0x220000>, + <0x800a000 0x3000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + qcom,not-wakeup; /* Needed until Full-boot-chain enabled */ + status = "ok"; + }; + + cpuss_dump { + compatible = "qcom,cpuss-dump"; + qcom,l1_i_cache0 { + qcom,dump-node = <&L1_I_0>; + qcom,dump-id = <0x60>; + }; + qcom,l1_i_cache1 { + qcom,dump-node = <&L1_I_1>; + qcom,dump-id = <0x61>; + }; + qcom,l1_i_cache2 { + qcom,dump-node = <&L1_I_2>; + qcom,dump-id = <0x62>; + }; + qcom,l1_i_cache3 { + qcom,dump-node = <&L1_I_3>; + qcom,dump-id = <0x63>; + }; + qcom,l1_i_cache100 { + qcom,dump-node = <&L1_I_100>; + qcom,dump-id = <0x64>; + }; + qcom,l1_i_cache101 { + qcom,dump-node = <&L1_I_101>; + qcom,dump-id = <0x65>; + }; + qcom,l1_i_cache102 { + qcom,dump-node = <&L1_I_102>; + qcom,dump-id = <0x66>; + }; + qcom,l1_i_cache103 { + qcom,dump-node = <&L1_I_103>; + qcom,dump-id = <0x67>; + }; + qcom,l1_d_cache0 { + qcom,dump-node = <&L1_D_0>; + qcom,dump-id = <0x80>; + }; + qcom,l1_d_cache1 { + qcom,dump-node = <&L1_D_1>; + qcom,dump-id = <0x81>; + }; + qcom,l1_d_cache2 { + qcom,dump-node = <&L1_D_2>; + qcom,dump-id = <0x82>; + }; + qcom,l1_d_cache3 { + qcom,dump-node = <&L1_D_3>; + qcom,dump-id = <0x83>; + }; + qcom,l1_d_cache100 { + qcom,dump-node = <&L1_D_100>; + qcom,dump-id = <0x84>; + }; + qcom,l1_d_cache101 { + qcom,dump-node = <&L1_D_101>; + qcom,dump-id = <0x85>; + }; + qcom,l1_d_cache102 { + qcom,dump-node = <&L1_D_102>; + qcom,dump-id = <0x86>; + }; + qcom,l1_d_cache103 { + qcom,dump-node = <&L1_D_103>; + qcom,dump-id = <0x87>; + }; + }; + + wdog: qcom,wdt@17817000 { + status = "disabled"; + compatible = "qcom,msm-watchdog"; + reg = <0x17817000 0x1000>; + reg-names = "wdt-base"; + interrupts = <0 3 0>, <0 4 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <10000>; + qcom,ipi-ping; + qcom,wakeup-enable; + }; + + qcom,sps { + compatible = "qcom,msm_sps_4k"; + qcom,pipe-attr-ee; + }; + + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x200000>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x300000>; + qcom,client-id = <2>; + label = "modem"; + }; + + mem_client_3_size: qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <1>; + label = "modem"; + }; + }; + + tsens: tsens@10ad000 { + compatible = "qcom,sdm660-tsens"; + reg = <0x10ad000 0x2000>, + <0x784240 0x1000>; + reg-names = "tsens_physical", "tsens_eeprom_physical"; + interrupts = <0 184 0>, <0 430 0>; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + qcom,sensors = <14>; + qcom,slope = <3200 3200 3200 3200 3200 3200 3200 3200 + 3200 3200 3200 3200 3200 3200>; + }; + + uartblsp1dm1: serial@0c170000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xc170000 0x1000>; + interrupts = <0 108 0>; + status = "disabled"; + clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>, + <&clock_gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + }; + + qcom,sensor-information { + compatible = "qcom,sensor-information"; + sensor_information0: qcom,sensor-information-0 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor0"; + qcom,scaling-factor = <10>; + }; + sensor_information1: qcom,sensor-information-1 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor1"; + qcom,scaling-factor = <10>; + }; + sensor_information2: qcom,sensor-information-2 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor2"; + qcom,scaling-factor = <10>; + }; + sensor_information3: qcom,sensor-information-3 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor3"; + qcom,scaling-factor = <10>; + }; + sensor_information4: qcom,sensor-information-4 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor4"; + qcom,scaling-factor = <10>; + }; + sensor_information5: qcom,sensor-information-5 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor5"; + qcom,scaling-factor = <10>; + }; + sensor_information6: qcom,sensor-information-6 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor6"; + qcom,scaling-factor = <10>; + }; + sensor_information7: qcom,sensor-information-7 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor7"; + qcom,scaling-factor = <10>; + }; + sensor_information8: qcom,sensor-information-8 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor8"; + qcom,scaling-factor = <10>; + qcom,alias-name = "gpu"; + }; + sensor_information9: qcom,sensor-information-9 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor9"; + qcom,scaling-factor = <10>; + }; + sensor_information10: qcom,sensor-information-10 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor10"; + qcom,scaling-factor = <10>; + }; + sensor_information11: qcom,sensor-information-11 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor11"; + qcom,scaling-factor = <10>; + }; + sensor_information12: qcom,sensor-information-12 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor12"; + qcom,scaling-factor = <10>; + }; + sensor_information13: qcom,sensor-information-13 { + qcom,sensor-type = "tsens"; + qcom,sensor-name = "tsens_tz_sensor13"; + qcom,scaling-factor = <10>; + }; + sensor_information14: qcom,sensor-information-14 { + qcom,sensor-type = "alarm"; + qcom,sensor-name = "pm660_tz"; + qcom,scaling-factor = <1000>; + }; + sensor_information15: qcom,sensor-information-15 { + qcom,sensor-type = "adc"; + qcom,sensor-name = "msm_therm"; + }; + sensor_information16: qcom,sensor-information-16 { + qcom,sensor-type = "adc"; + qcom,sensor-name = "xo_therm"; + }; + sensor_information17: qcom,sensor-information-17 { + qcom,sensor-type = "adc"; + qcom,sensor-name = "pa_therm0"; + }; + sensor_information18: qcom,sensor-information-18 { + qcom,sensor-type = "adc"; + qcom,sensor-name = "pa_therm1"; + }; + sensor_information19: qcom,sensor-information-19 { + qcom,sensor-type = "adc"; + qcom,sensor-name = "quiet_therm"; + }; + sensor_information20: qcom,sensor-information-20 { + qcom,sensor-type = "llm"; + qcom,sensor-name = "limits_sensor-00"; + }; + sensor_information21: qcom,sensor-information-21 { + qcom,sensor-type = "llm"; + qcom,sensor-name = "limits_sensor-01"; + }; + }; + + mitigation_profile0: qcom,limit_info-0 { + qcom,temperature-sensor = <&sensor_information1>; + qcom,hotplug-mitigation-enable; + }; + + mitigation_profile1: qcom,limit_info-1 { + qcom,temperature-sensor = <&sensor_information3>; + qcom,hotplug-mitigation-enable; + }; + + mitigation_profile2: qcom,limit_info-2 { + qcom,temperature-sensor = <&sensor_information4>; + qcom,hotplug-mitigation-enable; + }; + + mitigation_profile3: qcom,limit_info-3 { + qcom,temperature-sensor = <&sensor_information5>; + qcom,hotplug-mitigation-enable; + }; + + mitigation_profile4: qcom,limit_info-4 { + qcom,temperature-sensor = <&sensor_information6>; + qcom,hotplug-mitigation-enable; + }; + + qcom,msm-thermal { + compatible = "qcom,msm-thermal"; + qcom,sensor-id = <1>; + qcom,poll-ms = <100>; + qcom,therm-reset-temp = <115>; + qcom,core-limit-temp = <70>; + qcom,core-temp-hysteresis = <10>; + qcom,hotplug-temp = <105>; + qcom,hotplug-temp-hysteresis = <20>; + qcom,online-hotplug-core; + qcom,synchronous-cluster-id = <0 1>; + qcom,synchronous-cluster-map = <0 4 &CPU0 &CPU1 &CPU2 &CPU3>, + <1 4 &CPU4 &CPU5 &CPU6 &CPU7>; + + qcom,vdd-restriction-temp = <5>; + qcom,vdd-restriction-temp-hysteresis = <10>; + + vdd-dig-supply = <&pm660l_s3_floor_level>; + vdd-gfx-supply = <&gfx_vreg_corner>; + + qcom,vdd-dig-rstr{ + qcom,vdd-rstr-reg = "vdd-dig"; + qcom,levels = ; + qcom,min-level = ; + }; + + qcom,vdd-gfx-rstr{ + qcom,vdd-rstr-reg = "vdd-gfx"; + qcom,levels = <5 6 6>; /* Nominal, Turbo, Turbo */ + qcom,min-level = <1>; /* No Request */ + }; + + msm_thermal_freq: qcom,vdd-apps-rstr{ + qcom,vdd-rstr-reg = "vdd-apps"; + qcom,levels = <1248000>; + qcom,freq-req; + }; + }; + + qcom,lmh { + compatible = "qcom,lmh_v1"; + interrupts = ; + }; + + qcom,msm-core@780000 { + compatible = "qcom,apss-core-ea"; + reg = <0x780000 0x1000>; + qcom,low-hyst-temp = <10>; + qcom,high-hyst-temp = <5>; + + ea0: ea0 { + sensor = <&sensor_information1>; + }; + + ea1: ea1 { + sensor = <&sensor_information1>; + }; + + ea2: ea2 { + sensor = <&sensor_information1>; + }; + + ea3: ea3 { + sensor = <&sensor_information1>; + }; + + ea4: ea4 { + sensor = <&sensor_information3>; + }; + + ea5: ea5 { + sensor = <&sensor_information4>; + }; + + ea6: ea6 { + sensor = <&sensor_information5>; + }; + + ea7: ea7 { + sensor = <&sensor_information6>; + }; + }; + + uartblsp2dm1: serial@0c1b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xc1b0000 0x1000>; + interrupts = <0 114 0>; + status = "disabled"; + clocks = <&clock_gcc GCC_BLSP2_UART2_APPS_CLK>, + <&clock_gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + }; + + slim_aud: slim@151c0000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0x151c0000 0x2c000>, + <0x15180000 0x2e000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 163 0>, <0 164 0>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + qcom,apps-ch-pipes = <0x7e0000>; + qcom,ea-pc = <0x260>; + status = "disabled"; + }; + + slim_qca: slim@15240000 { + cell-index = <3>; + compatible = "qcom,slim-ngd"; + reg = <0x15240000 0x2c000>, + <0x15200000 0x24000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 291 0>, <0 292 0>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + qcom,apps-ch-pipes = <0x1800>; + status = "disabled"; + }; + + timer@17920000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17920000 0x1000>; + clock-frequency = <19200000>; + + frame@17921000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0x17921000 0x1000>, + <0x17922000 0x1000>; + }; + + frame@17923000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0x17923000 0x1000>; + status = "disabled"; + }; + + frame@17924000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0x17924000 0x1000>; + status = "disabled"; + }; + + frame@17925000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0x17925000 0x1000>; + status = "disabled"; + }; + + frame@17926000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0x17926000 0x1000>; + status = "disabled"; + }; + + frame@17927000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0x17927000 0x1000>; + status = "disabled"; + }; + + frame@17928000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0x17928000 0x1000>; + status = "disabled"; + }; + }; + + arm64-cpu-erp { + compatible = "arm,arm64-cpu-erp"; + interrupts = <0 43 4>, + <0 44 4>, + <0 41 4>, + <0 42 4>; + + interrupt-names = "pri-dbe-irq", + "sec-dbe-irq", + "pri-ext-irq", + "sec-ext-irq"; + + poll-delay-ms = <5000>; + }; + + clock_rpmcc: qcom,rpmcc { + compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; + #clock-cells = <1>; + }; + + clock_gcc: clock-controller@100000 { + compatible = "qcom,gcc-sdm660", "syscon"; + reg = <0x100000 0x94000>; + vdd_dig-supply = <&pm660l_s3_level>; + vdd_dig_ao-supply = <&pm660l_s3_level_ao>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_mmss: clock-controller@c8c0000 { + compatible = "qcom,mmcc-sdm660"; + reg = <0xc8c0000 0x40000>; + vdd_mx_mmss-supply = <&pm660l_s5_level>; + vdd_dig_mmss-supply = <&pm660l_s3_level>; + vdda-supply = <&pm660_l10>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_gfx: clock-controller@5065000 { + compatible = "qcom,gpucc-sdm660"; + reg = <0x5065000 0x10000>; + vdd_dig_gfx-supply = <&pm660l_s3_level>; + vdd_mx_gfx-supply = <&pm660l_s5_level>; + vdd_gfx-supply = <&gfx_vreg_corner>; + qcom,gfxfreq-corner = + < 0 0>, + < 160000000 1>, /* MinSVS */ + < 266000000 2>, /* LowSVS */ + < 370000000 3>, /* SVS */ + < 465000000 4>, /* SVS_L1 */ + < 588000000 5>, /* NOM */ + < 647000000 6>, /* NOM_L1 */ + < 700000000 7>, /* TURBO */ + < 750000000 7>; /* TURBO */ + #clock-cells = <1>; + #reset-cells = <1>; + }; + + cpu_debug: syscon@1791101c { + compatible = "syscon"; + reg = <0x1791101c 0x4>; + }; + + gpu_debug: syscon@05065120 { + compatible = "syscon"; + reg = <0x05065120 0x4>; + }; + + mmss_debug: syscon@c8c0900 { + compatible = "syscon"; + reg = <0xc8c0900 0x4>; + }; + + clock_debug: qcom,cc-debug@62000 { + compatible = "qcom,gcc-debug-sdm660"; + reg = <0x62000 0x4>; + reg-names = "dbg_offset"; + clocks = <&clock_rpmcc RPM_XO_CLK_SRC>; + clock-names = "xo_clk_src"; + qcom,cc-count = <4>; + qcom,gcc = <&clock_gcc>; + qcom,cpu = <&cpu_debug>; + qcom,mmss = <&mmss_debug>; + qcom,gpu = <&gpu_debug>; + #clock-cells = <1>; + }; + + cpubw: qcom,cpubw { + compatible = "qcom,devbw"; + governor = "performance"; + qcom,src-dst-ports = <1 512>; + qcom,active-only; + qcom,bw-tbl = + < 762 /* 100 MHz */ >, + < 1144 /* 150 MHz */ >, + < 1525 /* 200 MHz */ >, + < 2288 /* 300 MHz */ >, + < 3143 /* 412 MHz */ >, + < 4173 /* 547 MHz */ >, + < 5195 /* 681 MHz */ >, + < 5859 /* 768 MHz */ >, + < 7759 /* 1017 MHz */ >, + < 9887 /* 1296 MHz */ >, + < 10327 /* 1353 MHz */ >, + < 11863 /* 1555 MHz */ >, + < 13763 /* 1804 MHz */ >; + }; + + bwmon: qcom,cpu-bwmon { + compatible = "qcom,bimc-bwmon3"; + reg = <0x01008000 0x300>, <0x01001000 0x200>; + reg-names = "base", "global_base"; + interrupts = <0 183 4>; + qcom,mport = <0>; + qcom,target-dev = <&cpubw>; + }; + + mincpubw: qcom,mincpubw { + compatible = "qcom,devbw"; + governor = "powersave"; + qcom,src-dst-ports = <1 512>; + qcom,active-only; + qcom,bw-tbl = + < 762 /* 100 MHz */ >, + < 1144 /* 150 MHz */ >, + < 1525 /* 200 MHz */ >, + < 2288 /* 300 MHz */ >, + < 3143 /* 412 MHz */ >, + < 4173 /* 547 MHz */ >, + < 5195 /* 681 MHz */ >, + < 5859 /* 768 MHz */ >, + < 7759 /* 1017 MHz */ >, + < 9887 /* 1296 MHz */ >, + < 10327 /* 1353 MHz */ >, + < 11863 /* 1555 MHz */ >, + < 13763 /* 1804 MHz */ >; + }; + + memlat_cpu0: qcom,memlat-cpu0 { + compatible = "qcom,devbw"; + governor = "powersave"; + qcom,src-dst-ports = <1 512>; + qcom,active-only; + qcom,bw-tbl = + < 762 /* 100 MHz */ >, + < 1144 /* 150 MHz */ >, + < 1525 /* 200 MHz */ >, + < 2288 /* 300 MHz */ >, + < 3143 /* 412 MHz */ >, + < 4173 /* 547 MHz */ >, + < 5195 /* 681 MHz */ >, + < 5859 /* 768 MHz */ >, + < 7759 /* 1017 MHz */ >, + < 9887 /* 1296 MHz */ >, + < 10327 /* 1353 MHz */ >, + < 11863 /* 1555 MHz */ >, + < 13763 /* 1804 MHz */ >; + }; + + memlat_cpu4: qcom,memlat-cpu4 { + compatible = "qcom,devbw"; + governor = "powersave"; + qcom,src-dst-ports = <1 512>; + qcom,active-only; + qcom,bw-tbl = + < 762 /* 100 MHz */ >, + < 1144 /* 150 MHz */ >, + < 1525 /* 200 MHz */ >, + < 2288 /* 300 MHz */ >, + < 3143 /* 412 MHz */ >, + < 4173 /* 547 MHz */ >, + < 5195 /* 681 MHz */ >, + < 5859 /* 768 MHz */ >, + < 7759 /* 1017 MHz */ >, + < 9887 /* 1296 MHz */ >, + < 10327 /* 1353 MHz */ >, + < 11863 /* 1555 MHz */ >, + < 13763 /* 1804 MHz */ >; + }; + + devfreq_memlat_0: qcom,arm-memlat-mon-0 { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,target-dev = <&memlat_cpu0>; + qcom,core-dev-table = + < 633600 1525 >, + < 1401600 4173 >, + < 1881600 7759 >; + }; + + devfreq_memlat_4: qcom,arm-memlat-mon-4 { + compatible = "qcom,arm-memlat-mon"; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; + qcom,target-dev = <&memlat_cpu4>; + qcom,core-dev-table = + < 1113600 1525 >, + < 1401600 7759 >, + < 2150400 11863 >, + < 2457600 13763 >; + }; + + devfreq_cpufreq: devfreq-cpufreq { + mincpubw-cpufreq { + target-dev = <&mincpubw>; + cpu-to-dev-map-0 = + < 633600 1525 >, + < 1401600 3143 >, + < 1881600 5859 >; + cpu-to-dev-map-4 = + < 1113600 1525 >, + < 1401600 4173 >, + < 1747200 5859 >, + < 2150400 7759 >, + < 2457600 13763 >; + }; + }; + + clock_cpu: qcom,clk-cpu-660@179c0000 { + compatible = "qcom,clk-cpu-osm"; + status = "disabled"; + reg = <0x179c0000 0x4000>, <0x17916000 0x1000>, + <0x17816000 0x1000>, <0x179d1000 0x1000>, + <0x00784130 0x8>; + reg-names = "osm", "pwrcl_pll", "perfcl_pll", + "apcs_common", "perfcl_efuse"; + + /* ToDo: Add power and perf supply rails */ + + interrupts = , + ; + interrupt-names = "pwrcl-irq", "perfcl-irq"; + + qcom,pwrcl-speedbin0-v0 = + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 633600000 0x05040021 0x03200020 0x1 1 >, + < 902400000 0x0404002f 0x04260026 0x1 2 >, + < 1113600000 0x0404003a 0x052e002e 0x2 3 >, + < 1401600000 0x04040049 0x073a003a 0x2 4 >, + < 1536000000 0x04040050 0x08400040 0x3 5 >, + < 1747200000 0x0404005b 0x09480048 0x3 6 >, + < 1843200000 0x04040060 0x094c004c 0x3 7 >; + + qcom,perfcl-speedbin0-v0 = + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 1113600000 0x0404003a 0x052e002e 0x1 1 >, + < 1401600000 0x04040049 0x073a003a 0x2 2 >, + < 1747200000 0x0404005b 0x09480048 0x2 3 >, + < 1958400000 0x04040066 0x0a510051 0x3 4 >, + < 2150400000 0x04040070 0x0b590059 0x3 5 >, + < 2457600000 0x04040080 0x0c660066 0x3 6 >; + + qcom,perfcl-speedbin1-v0 = + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 1113600000 0x0404003a 0x052e002e 0x1 1 >, + < 1401600000 0x04040049 0x073a003a 0x2 2 >, + < 1747200000 0x0404005b 0x09480048 0x2 3 >, + < 1958400000 0x04040066 0x0a510051 0x3 4 >, + < 2150400000 0x04040070 0x0b590059 0x3 5 >, + < 2208000000 0x04040073 0x0b5c005c 0x3 6 >; + + qcom,up-timer = <1000 1000>; + qcom,down-timer = <1000 1000>; + qcom,pc-override-index = <0 0>; + qcom,set-ret-inactive; + qcom,enable-llm-freq-vote; + qcom,llm-freq-up-timer = <327675 327675>; + qcom,llm-freq-down-timer = <327675 327675>; + qcom,enable-llm-volt-vote; + qcom,llm-volt-up-timer = <327675 327675>; + qcom,llm-volt-down-timer = <327675 327675>; + qcom,cc-reads = <10>; + qcom,cc-delay = <5>; + qcom,cc-factor = <100>; + qcom,osm-clk-rate = <200000000>; + qcom,xo-clk-rate = <19200000>; + + qcom,l-val-base = <0x17916004 0x17816004>; + qcom,apcs-itm-present = <0x179d143c 0x179d143c>; + qcom,apcs-pll-user-ctl = <0x1791600c 0x1781600c>; + qcom,apcs-cfg-rcgr = <0x17911054 0x17811054>; + qcom,apcs-cmd-rcgr = <0x17911050 0x17811050>; + qcom,apm-mode-ctl = <0x179d0004 0x179d0010>; + qcom,apm-ctrl-status = <0x179d000c 0x179d0018>; + + qcom,apm-threshold-voltage = <832000>; + qcom,boost-fsm-en; + qcom,safe-fsm-en; + qcom,ps-fsm-en; + qcom,droop-fsm-en; + qcom,wfx-fsm-en; + qcom,pc-fsm-en; + + qcom,pwrcl-apcs-mem-acc-cfg = + <0x179d1360 0x179d1364 0x179d1364>; + qcom,perfcl-apcs-mem-acc-cfg = + <0x179d1368 0x179d136C 0x179d1370>; + qcom,pwrcl-apcs-mem-acc-val = + <0x00000000 0x80000000 0x80000000>, + <0x00000000 0x00000000 0x00000000>, + <0x00000000 0x00000001 0x00000001>; + qcom,perfcl-apcs-mem-acc-val = + <0x00000000 0x00000000 0x80000000>, + <0x00000000 0x00000000 0x00000000>, + <0x00000000 0x00000000 0x00000001>; + + clock-names = "aux_clk", "xo_a"; + clocks = <&clock_gcc HMSS_GPLL0_CLK_SRC>, + <&clock_rpmcc RPM_XO_A_CLK_SRC>; + + #clock-cells = <1>; + }; + + sdhc_1: sdhci@c0c4000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0xc0c4000 0x1000>, <0xc0c5000 0x1000>; + reg-names = "hc_mem", "cmdq_mem"; + + interrupts = <0 129 0>, <0 227 0>; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <8>; + qcom,large-address-bus; + + qcom,devfreq,freq-table = <50000000 200000000>; + + clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>, + <&clock_gcc GCC_SDCC1_APPS_CLK>; + clock-names = "iface_clk", "core_clk"; + + status = "disabled"; + }; + + ipa_hw: qcom,ipa@14780000 { + compatible = "qcom,ipa"; + reg = <0x14780000 0x4effc>, <0x14784000 0x26934>; + reg-names = "ipa-base", "bam-base"; + interrupts = <0 333 0>, + <0 432 0>; + interrupt-names = "ipa-irq", "bam-irq"; + qcom,ipa-hw-ver = <6>; /* IPA core version = IPAv2.6L */ + qcom,ipa-hw-mode = <0>; /* IPA hw type = Normal */ + qcom,wan-rx-ring-size = <192>; /* IPA WAN-rx-ring-size*/ + qcom,lan-rx-ring-size = <192>; /* IPA LAN-rx-ring-size*/ + clocks = <&clock_rpmcc RPM_IPA_CLK>, + <&clock_rpmcc RPM_AGGR2_NOC_CLK>; + clock-names = "core_clk", "smmu_clk"; + qcom,arm-smmu; + qcom,smmu-disable-htw; + qcom,smmu-s1-bypass; + qcom,ee = <0>; + qcom,use-ipa-tethering-bridge; + qcom,modem-cfg-emb-pipe-flt; + qcom,msm-bus,name = "ipa"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + /* No vote */ + <90 512 0 0>, + <1 676 0 0>, + /* SVS */ + <90 512 80000 640000>, + <1 676 80000 80000>, + /* NOMINAL */ + <90 512 206000 960000>, + <1 676 206000 160000>, + /* TURBO */ + <90 512 206000 960000>, + <1 676 206000 160000>; + qcom,bus-vector-names = "MIN", "SVS", "PERF", "TURBO"; + qcom,rx-polling-sleep-ms = <2>; /* Polling sleep interval */ + qcom,ipa-polling-iteration = <5>; /* Polling Iteration */ + + ipa_smmu_ap: ipa_smmu_ap { + compatible = "qcom,ipa-smmu-ap-cb"; + iommus = <&anoc2_smmu 0x19C0>; + qcom,iova-mapping = <0x10000000 0x40000000>; + }; + + ipa_smmu_wlan: ipa_smmu_wlan { + status = "disabled"; + compatible = "qcom,ipa-smmu-wlan-cb"; + iommus = <&anoc2_smmu 0x19C1>; + }; + + ipa_smmu_uc: ipa_smmu_uc { + compatible = "qcom,ipa-smmu-uc-cb"; + iommus = <&anoc2_smmu 0x19C2>; + qcom,iova-mapping = <0x40000000 0x20000000>; + }; + }; + + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x200000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + }; + + qcom,rmnet-ipa { + compatible = "qcom,rmnet-ipa"; + qcom,rmnet-ipa-ssr; + qcom,ipa-loaduC; + qcom,ipa-advertise-sg-support; + }; + + qcom,ipc-spinlock@1f40000 { + compatible = "qcom,ipc-spinlock-sfpb"; + reg = <0x1f40000 0x8000>; + qcom,num-locks = <8>; + }; + + qcom,smem@86000000 { + compatible = "qcom,smem"; + reg = <0x86000000 0x200000>, + <0x17911008 0x4>, + <0x778000 0x7000>, + <0x1fd4000 0x8>; + reg-names = "smem", "irq-reg-base", "aux-mem1", + "smem_targ_info_reg"; + qcom,mpu-enabled; + }; + + + qcom,msm-adsprpc-mem { + compatible = "qcom,msm-adsprpc-mem-region"; + memory-region = <&adsp_mem>; + }; + + qcom,msm_fastrpc { + compatible = "qcom,msm-fastrpc-adsp"; + qcom,fastrpc-glink; + + qcom,msm_fastrpc_compute_cb1 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 3>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb2 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 7>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb3 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 8>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb4 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "adsprpc-smd"; + iommus = <&lpass_q6_smmu 9>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb5 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&turing_q6_smmu 3>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb6 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&turing_q6_smmu 4>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb7 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&turing_q6_smmu 5>; + dma-coherent; + }; + + qcom,msm_fastrpc_compute_cb8 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&turing_q6_smmu 6>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb9 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&turing_q6_smmu 7>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb10 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&turing_q6_smmu 8>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb11 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&turing_q6_smmu 9>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb12 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&turing_q6_smmu 10>; + dma-coherent; + }; + qcom,msm_fastrpc_compute_cb13 { + compatible = "qcom,msm-fastrpc-compute-cb"; + label = "cdsprpc-smd"; + iommus = <&turing_q6_smmu 11>; + dma-coherent; + }; + }; + + + dcc: dcc@10b3000 { + compatible = "qcom,dcc"; + reg = <0x10b3000 0x1000>, + <0x10b4000 0x800>; + reg-names = "dcc-base", "dcc-ram-base"; + + clocks = <&clock_gcc GCC_DCC_AHB_CLK>; + clock-names = "dcc_clk"; + }; + + qcom,glink-smem-native-xprt-modem@86000000 { + compatible = "qcom,glink-smem-native-xprt"; + reg = <0x86000000 0x200000>, + <0x17911008 0x4>; + reg-names = "smem", "irq-reg-base"; + qcom,irq-mask = <0x8000>; + interrupts = <0 452 1>; + label = "mpss"; + }; + + qcom,glink-smem-native-xprt-adsp@86000000 { + compatible = "qcom,glink-smem-native-xprt"; + reg = <0x86000000 0x200000>, + <0x17911008 0x4>; + reg-names = "smem", "irq-reg-base"; + qcom,irq-mask = <0x200>; + interrupts = <0 157 1>; + label = "lpass"; + qcom,qos-config = <&glink_qos_adsp>; + qcom,ramp-time = <0xaf>; + }; + + glink_qos_adsp: qcom,glink-qos-config-adsp { + compatible = "qcom,glink-qos-config"; + qcom,flow-info = <0x3c 0x0>, + <0x3c 0x0>, + <0x3c 0x0>, + <0x3c 0x0>; + qcom,mtu-size = <0x800>; + qcom,tput-stats-cycle = <0xa>; + }; + + qcom,glink-smem-native-xprt-cdsp@86000000 { + compatible = "qcom,glink-smem-native-xprt"; + reg = <0x86000000 0x200000>, + <0x17911008 0x4>; + reg-names = "smem", "irq-reg-base"; + qcom,irq-mask = <0x20000000>; + interrupts = <0 513 1>; + label = "cdsp"; + }; + + qcom,glink-smem-native-xprt-rpm@778000 { + compatible = "qcom,glink-rpm-native-xprt"; + reg = <0x778000 0x7000>, + <0x17911008 0x4>; + reg-names = "msgram", "irq-reg-base"; + qcom,irq-mask = <0x1>; + interrupts = <0 168 1>; + label = "rpm"; + }; + + glink_mpss: qcom,glink-ssr-modem { + compatible = "qcom,glink_ssr"; + label = "modem"; + qcom,edge = "mpss"; + qcom,notify-edges = <&glink_lpass>, <&glink_rpm>, + <&glink_cdsp>; + qcom,xprt = "smem"; + }; + + glink_lpass: qcom,glink-ssr-adsp { + compatible = "qcom,glink_ssr"; + label = "adsp"; + qcom,edge = "lpass"; + qcom,notify-edges = <&glink_mpss>, <&glink_rpm>, + <&glink_cdsp>; + qcom,xprt = "smem"; + }; + + glink_rpm: qcom,glink-ssr-rpm { + compatible = "qcom,glink_ssr"; + label = "rpm"; + qcom,edge = "rpm"; + qcom,notify-edges = <&glink_lpass>, <&glink_mpss>, + <&glink_cdsp>; + qcom,xprt = "smem"; + }; + + glink_cdsp: qcom,glink-ssr-cdsp { + compatible = "qcom,glink_ssr"; + label = "cdsp"; + qcom,edge = "cdsp"; + qcom,notify-edges = <&glink_lpass>, <&glink_mpss>, + <&glink_rpm>; + qcom,xprt = "smem"; + }; + + qcom,glink_pkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-loopback_cntl { + qcom,glinkpkt-transport = "lloop"; + qcom,glinkpkt-edge = "local"; + qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT"; + qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl"; + }; + + qcom,glinkpkt-loopback_data { + qcom,glinkpkt-transport = "lloop"; + qcom,glinkpkt-edge = "local"; + qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT"; + qcom,glinkpkt-dev-name = "glink_pkt_loopback"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-transport = "smem"; + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-glink"; + qcom,glink-edge = "rpm"; + rpm-channel-name = "rpm_requests"; + }; + + qcom,ipc_router { + compatible = "qcom,ipc_router"; + qcom,node-id = <1>; + }; + + qcom,ipc_router_modem_xprt { + compatible = "qcom,ipc_router_glink_xprt"; + qcom,ch-name = "IPCRTR"; + qcom,xprt-remote = "mpss"; + qcom,glink-xprt = "smem"; + qcom,xprt-linkid = <1>; + qcom,xprt-version = <1>; + qcom,fragmented-data; + }; + + qcom,ipc_router_q6_xprt { + compatible = "qcom,ipc_router_glink_xprt"; + qcom,ch-name = "IPCRTR"; + qcom,xprt-remote = "lpass"; + qcom,glink-xprt = "smem"; + qcom,xprt-linkid = <1>; + qcom,xprt-version = <1>; + qcom,fragmented-data; + }; + + qcom,ipc_router_cdsp_xprt { + compatible = "qcom,ipc_router_glink_xprt"; + qcom,ch-name = "IPCRTR"; + qcom,xprt-remote = "cdsp"; + qcom,glink-xprt = "smem"; + qcom,xprt-linkid = <1>; + qcom,xprt-version = <1>; + qcom,fragmented-data; + }; + + qcom,venus@cce0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xcce0000 0x4000>; + + vdd-supply = <&gdsc_venus>; + qcom,proxy-reg-names = "vdd"; + + clocks = <&clock_mmss MMSS_VIDEO_CORE_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_VIDEO_AHB_CLK>, + <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_VIDEO_AXI_CLK>; + clock-names = "core_clk", "mnoc_ahb_clk", "iface_clk", + "noc_axi_clk", "bus_clk"; + qcom,proxy-clock-names = "core_clk", "mnoc_ahb_clk", + "iface_clk", "noc_axi_clk", "bus_clk"; + + qcom,msm-bus,name = "pil-venus"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <63 512 0 0>, + <63 512 0 304000>; + + qcom,pas-id = <9>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&venus_fw_mem>; + status = "ok"; + }; + + qcom,icnss@18800000 { + status = "disabled"; + compatible = "qcom,icnss"; + reg = <0x18800000 0x800000>, + <0x10ac000 0x20>; + reg-names = "membase", "mpm_config"; + interrupts = <0 413 0>, /* CE0 */ + <0 414 0>, /* CE1 */ + <0 415 0>, /* CE2 */ + <0 416 0>, /* CE3 */ + <0 417 0>, /* CE4 */ + <0 418 0>, /* CE5 */ + <0 420 0>, /* CE6 */ + <0 421 0>, /* CE7 */ + <0 422 0>, /* CE8 */ + <0 423 0>, /* CE9 */ + <0 424 0>, /* CE10 */ + <0 425 0>; /* CE11 */ + qcom,wlan-msa-memory = <0x100000>; + }; + + qcom,lpass@15700000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x15700000 0x00100>; + interrupts = <0 162 1>; + + vdd_cx-supply = <&pm660l_l9_level>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + + clocks = <&clock_rpmcc CXO_PIL_LPASS_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <1>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <423>; + qcom,sysmon-id = <1>; + qcom,ssctl-instance-id = <0x14>; + qcom,firmware-name = "adsp"; + memory-region = <&adsp_fw_mem>; + + /* GPIO inputs from lpass */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>; + qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>; + + /* GPIO output to lpass */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>; + status = "ok"; + }; + + qcom,turing@1a300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x1a300000 0x00100>; + interrupts = <0 518 1>; + + vdd_cx-supply = <&pm660l_s3_level>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + + clocks = <&clock_rpmcc CXO_PIL_CDSP_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <18>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <601>; + qcom,sysmon-id = <7>; + qcom,ssctl-instance-id = <0x17>; + qcom,firmware-name = "cdsp"; + memory-region = <&cdsp_fw_mem>; + + /* GPIO inputs from turing */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_5_in 0 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_5_in 2 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_5_in 1 0>; + qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_5_in 3 0>; + + /* GPIO output to turing*/ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_5_out 0 0>; + status = "ok"; + }; + + pil_modem: qcom,mss@4080000 { + compatible = "qcom,pil-q6v55-mss"; + reg = <0x4080000 0x100>, + <0x1f63000 0x008>, + <0x1f65000 0x008>, + <0x1f64000 0x008>, + <0x4180000 0x040>, + <0x00179000 0x004>, + <0x01fe5048 0x004>; + reg-names = "qdsp6_base", "halt_q6", "halt_modem", + "halt_nc", "rmb_base", "restart_reg", + "cxip_lm_vote_clear"; + + clocks = <&clock_rpmcc RPM_XO_CLK_SRC>, + <&clock_gcc GCC_MSS_CFG_AHB_CLK>, + <&clock_gcc GCC_BIMC_MSS_Q6_AXI_CLK>, + <&clock_gcc GCC_BOOT_ROM_AHB_CLK>, + <&clock_gcc GPLL0_OUT_MSSCC>, + <&clock_gcc GCC_MSS_SNOC_AXI_CLK>, + <&clock_gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, + <&clock_rpmcc RPM_QDSS_CLK>; + clock-names = "xo", "iface_clk", "bus_clk", + "mem_clk", "gpll0_mss_clk", "snoc_axi_clk", + "mnoc_axi_clk", "qdss_clk"; + qcom,proxy-clock-names = "xo", "qdss_clk"; + qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk", + "gpll0_mss_clk", "snoc_axi_clk", + "mnoc_axi_clk"; + + interrupts = <0 448 1>; + vdd_cx-supply = <&pm660l_s3_level>; + vdd_cx-voltage = ; + vdd_mx-supply = <&pm660l_s5_level>; + vdd_mx-uV = ; + qcom,firmware-name = "modem"; + qcom,pil-self-auth; + qcom,sysmon-id = <0>; + qcom,ssctl-instance-id = <0x12>; + qcom,qdsp6v62-1-5; + memory-region = <&modem_fw_mem>; + qcom,mem-protect-id = <0xF>; + qcom,cx-ipeak-vote; + + /* GPIO inputs from mss */ + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>; + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>; + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>; + qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>; + qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>; + + /* GPIO output to mss */ + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; + status = "ok"; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + qcom,mpm2-sleep-counter@10a3000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0x10a3000 0x1000>; + clock-frequency = <32768>; + }; + + qcom,msm-imem@146bf000 { + compatible = "qcom,msm-imem"; + reg = <0x146bf000 0x1000>; + ranges = <0x0 0x146bf000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 8>; + }; + + dload_type@18 { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x18 4>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 32>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 200>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 200>; + }; + }; + + qcom,ghd { + compatible = "qcom,gladiator-hang-detect"; + qcom,threshold-arr = <0x179d141c 0x179d1420 + 0x179d1424 0x179d1428 + 0x179d142c 0x179d1430>; + qcom,config-reg = <0x179d1434>; + }; + + qcom,msm-gladiator-v2@17900000 { + compatible = "qcom,msm-gladiator-v2"; + reg = <0x17900000 0xe000>; + reg-names = "gladiator_base"; + interrupts = <0 22 0>; + clock-names = "atb_clk"; + clocks = <&clock_rpmcc RPM_QDSS_CLK>; + }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = <1 6 4>; + }; + + qcom_seecom: qseecom@86d00000 { + compatible = "qcom,qseecom"; + reg = <0x86d00000 0x2200000>; + reg-names = "secapp-region"; + qcom,hlos-num-ce-hw-instances = <1>; + qcom,hlos-ce-hw-instance = <0>; + qcom,qsee-ce-hw-instance = <0>; + qcom,disk-encrypt-pipe-pair = <2>; + qcom,support-fde; + qcom,no-clock-support; + qcom,msm-bus,name = "qseecom-noc"; + qcom,msm-bus,num-cases = <4>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 200000 400000>, + <55 512 300000 800000>, + <55 512 400000 1000000>; + clock-names = "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = <&clock_rpmcc QSEECOM_CE1_CLK>, + <&clock_rpmcc QSEECOM_CE1_CLK>, + <&clock_rpmcc QSEECOM_CE1_CLK>, + <&clock_rpmcc QSEECOM_CE1_CLK>; + qcom,ce-opp-freq = <171430000>; + qcom,qsee-reentrancy-support = <2>; + }; + + qcom_cedev: qcedev@1de0000{ + compatible = "qcom,qcedev"; + reg = <0x1de0000 0x20000>, + <0x1dc4000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 0>; + qcom,bam-pipe-pair = <1>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,ce-hw-shared; + qcom,bam-ee = <0>; + qcom,msm-bus,name = "qcedev-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 393600 393600>; + clock-names = "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = <&clock_rpmcc QCEDEV_CE1_CLK>, + <&clock_rpmcc QCEDEV_CE1_CLK>, + <&clock_rpmcc QCEDEV_CE1_CLK>, + <&clock_rpmcc QCEDEV_CE1_CLK>; + qcom,ce-opp-freq = <171430000>; + }; + + qcom_crypto: qcrypto@1de0000 { + compatible = "qcom,qcrypto"; + reg = <0x1de0000 0x20000>, + <0x1dc4000 0x24000>; + reg-names = "crypto-base","crypto-bam-base"; + interrupts = <0 207 0>; + qcom,bam-pipe-pair = <2>; + qcom,ce-hw-instance = <0>; + qcom,ce-device = <0>; + qcom,bam-ee = <0>; + qcom,ce-hw-shared; + qcom,clk-mgmt-sus-res; + qcom,msm-bus,name = "qcrypto-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <55 512 0 0>, + <55 512 393600 393600>; + clock-names = "core_clk_src", "core_clk", + "iface_clk", "bus_clk"; + clocks = <&clock_rpmcc QCRYPTO_CE1_CLK>, + <&clock_rpmcc QCRYPTO_CE1_CLK>, + <&clock_rpmcc QCRYPTO_CE1_CLK>, + <&clock_rpmcc QCRYPTO_CE1_CLK>; + qcom,ce-opp-freq = <171430000>; + qcom,use-sw-aes-cbc-ecb-ctr-algo; + qcom,use-sw-aes-xts-algo; + qcom,use-sw-aes-ccm-algo; + qcom,use-sw-ahash-algo; + qcom,use-sw-aead-algo; + qcom,use-sw-hmac-algo; + }; + + qcom_tzlog: tz-log@146bf720 { + compatible = "qcom,tz-log"; + reg = <0x146bf720 0x3000>; + qcom,hyplog-enabled; + hyplog-address-offset = <0x410>; + hyplog-size-offset = <0x414>; + }; + + qcom_rng: qrng@794000 { + compatible = "qcom,msm-rng"; + reg = <0x794000 0x1000>; + qcom,msm-rng-iface-clk; + qcom,no-qrng-config; + qcom,msm-bus,name = "msm-rng-noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 618 0 0>, /* No vote */ + <1 618 0 800>; /* 100 KHz */ + clocks = <&clock_gcc GCC_PRNG_AHB_CLK>; + clock-names = "iface_clk"; + }; + + qcom,chd_silver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0x179880b0 0x179980b0 + 0x179a80b0 0x179b80b0>; + qcom,config-arr = <0x179880b8 0x179980b8 + 0x179a80b8 0x179b80b8>; + }; + + qcom,chd_gold { + compatible = "qcom,core-hang-detect"; + label = "gold"; + qcom,threshold-arr = <0x178880b0 0x178980b0 + 0x178a80b0 0x178b80b0>; + qcom,config-arr = <0x178880b8 0x178980b8 + 0x178a80b8 0x178b80b8>; + }; + + ufsphy1: ufsphy@1da7000 { + compatible = "qcom,ufs-phy-qmp-v3-660"; + reg = <0x1da7000 0xdb8>; + reg-names = "phy_mem"; + #phy-cells = <0>; + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&clock_rpmcc RPM_LN_BB_CLK1>, + <&clock_gcc GCC_UFS_CLKREF_CLK>, + <&clock_gcc GCC_UFS_PHY_AUX_CLK>; + status = "disabled"; + }; + + ufs1: ufshc@1da4000 { + compatible = "qcom,ufshc"; + reg = <0x1da4000 0x3000>; + interrupts = <0 265 0>; + phys = <&ufsphy1>; + phy-names = "ufsphy"; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + clocks = + <&clock_gcc GCC_UFS_AXI_CLK>, + <&clock_gcc GCC_AGGRE2_UFS_AXI_CLK>, + <&clock_gcc GCC_UFS_AHB_CLK>, + <&clock_gcc GCC_UFS_UNIPRO_CORE_CLK>, + <&clock_gcc GCC_UFS_ICE_CORE_CLK>, + <&clock_rpmcc RPM_LN_BB_CLK1>, + <&clock_gcc GCC_UFS_TX_SYMBOL_0_CLK>, + <&clock_gcc GCC_UFS_RX_SYMBOL_0_CLK>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + + lanes-per-direction = <1>; + + qcom,msm-bus,name = "ufs1"; + qcom,msm-bus,num-cases = <12>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-KBps = + <95 512 0 0>, <1 650 0 0>, /* No vote */ + <95 512 922 0>, <1 650 1000 0>, /* PWM G1 */ + <95 512 1844 0>, <1 650 1000 0>, /* PWM G2 */ + <95 512 3688 0>, <1 650 1000 0>, /* PWM G3 */ + <95 512 7376 0>, <1 650 1000 0>, /* PWM G4 */ + <95 512 127796 0>, <1 650 1000 0>, /* HS G1 RA */ + <95 512 255591 0>, <1 650 1000 0>, /* HS G2 RA */ + <95 512 2097152 0>, <1 650 102400 0>, /* HS G3 RA */ + <95 512 149422 0>, <1 650 1000 0>, /* HS G1 RB */ + <95 512 298189 0>, <1 650 1000 0>, /* HS G2 RB */ + <95 512 2097152 0>, <1 650 102400 0>, /* HS G3 RB */ + <95 512 7643136 0>, <1 650 307200 0>; /* Max. bandwidth */ + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", + "MAX"; + + resets = <&clock_gcc GCC_UFS_BCR>; + reset-names = "core_reset"; + + status = "disabled"; + }; + + jtag_fuse: jtagfuse@786040 { + compatible = "qcom,jtag-fuse-v4"; + reg = <0x786040 0x8>; + reg-names = "fuse-base"; + }; + + jtag_mm0: jtagmm@7840000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7840000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU0>; + }; + + jtag_mm1: jtagmm@7940000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7940000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU1>; + }; + + jtag_mm2: jtagmm@7a40000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7a40000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU2>; + }; + + jtag_mm3: jtagmm@7b40000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7b40000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU3>; + }; + + jtag_mm4: jtagmm@7c40000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7c40000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU0>; + }; + + jtag_mm5: jtagmm@7d40000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7d40000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU1>; + }; + + jtag_mm6: jtagmm@7e40000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7e40000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU2>; + }; + + jtag_mm7: jtagmm@7f40000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7f40000 0x1000>; + reg-names = "etm-base"; + + clocks = <&clock_rpmcc RPM_QDSS_CLK>, + <&clock_rpmcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU3>; + }; +}; + +#include "sdm660-ion.dtsi" +#include "sdm660-bus.dtsi" +#include "msm-pm660.dtsi" +#include "msm-pm660l.dtsi" +#include "msm-pm660-rpm-regulator.dtsi" +#include "msm-pm660l-rpm-regulator.dtsi" +#include "sdm660-regulator.dtsi" +#include "msm-gdsc-660.dtsi" +#include "sdm660-gpu.dtsi" +#include "sdm660-pm.dtsi" +#include "msm-audio.dtsi" +#include "sdm660-audio.dtsi" + +&gdsc_usb30 { + status = "ok"; +}; + +&gdsc_ufs { + status = "ok"; +}; + +&gdsc_bimc_smmu { + clock-names = "bus_clk"; + clocks = <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>; + proxy-supply = <&gdsc_bimc_smmu>; + qcom,proxy-consumer-enable; + status = "ok"; +}; + +&gdsc_hlos1_vote_lpass_adsp { + status = "ok"; +}; + +&gdsc_hlos1_vote_turing_adsp { + status = "ok"; +}; + +&gdsc_hlos2_vote_turing_adsp { + status = "ok"; +}; + +&gdsc_venus { + status = "ok"; +}; + +&gdsc_venus_core0 { + qcom,support-hw-trigger; + status = "ok"; +}; + +&gdsc_camss_top { + status = "ok"; +}; + +&gdsc_vfe0 { + parent-supply = <&gdsc_camss_top>; + status = "ok"; +}; + +&gdsc_vfe1 { + parent-supply = <&gdsc_camss_top>; + status = "ok"; +}; + +&gdsc_cpp { + parent-supply = <&gdsc_camss_top>; + status = "ok"; +}; + +&gdsc_mdss { + proxy-supply = <&gdsc_mdss>; + qcom,proxy-consumer-enable; + status = "ok"; +}; + +&gdsc_gpu_gx { + clock-names = "core_root_clk"; + clocks = <&clock_gfx GFX3D_CLK_SRC>; + qcom,force-enable-root-clk; + parent-supply = <&gfx_vreg_corner>; + status = "ok"; +}; + +&gdsc_gpu_cx { + status = "ok"; +}; + +#include "msm-arm-smmu-660.dtsi" +#include "msm-arm-smmu-impl-defs-660.dtsi" +#include "sdm660-common.dtsi" +#include "sdm660-blsp.dtsi" +#include "sdm660-camera.dtsi" +#include "sdm660-vidc.dtsi" + +&pm660l_gpios { + /* GPIO 7 for VOL_UP */ + gpio@c600 { + status = "okay"; + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <0>; + qcom,src-sel = <0>; + qcom,out-strength = <1>; + }; +}; + +&soc { + gpio_keys { + status = "okay"; + compatible = "gpio-keys"; + input-name = "gpio-keys"; + pinctrl-names = "tlmm_gpio_key_active","tlmm_gpio_key_suspend"; + pinctrl-0 = <&gpio_key_active>; + pinctrl-1 = <&gpio_key_suspend>; + + camera_focus { + label = "camera_focus"; + gpios = <&tlmm 64 0x1>; + linux,input-type = <1>; + linux,code = <0x210>; + debounce-interval = <15>; + }; + + camera_snapshot { + label = "camera_snapshot"; + gpios = <&tlmm 113 0x1>; + linux,input-type = <1>; + linux,code = <0x2fe>; + debounce-interval = <15>; + }; + + vol_up { + label = "volume_up"; + gpios = <&pm660l_gpios 7 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; +}; + +#include "sdm660-mdss.dtsi" +#include "sdm660-mdss-pll.dtsi" diff --git a/arch/arm/configs/msmcortex_defconfig b/arch/arm/configs/msmcortex_defconfig index 5e9afadeb7ae..c5c7d924aab6 100644 --- a/arch/arm/configs/msmcortex_defconfig +++ b/arch/arm/configs/msmcortex_defconfig @@ -38,7 +38,7 @@ CONFIG_MODULE_SIG_SHA512=y CONFIG_PARTITION_ADVANCED=y # CONFIG_IOSCHED_DEADLINE is not set CONFIG_ARCH_QCOM=y -CONFIG_ARCH_MSMFALCON=y +CONFIG_ARCH_SDM660=y CONFIG_SMP=y CONFIG_SCHED_MC=y CONFIG_NR_CPUS=8 @@ -289,7 +289,7 @@ CONFIG_SPI_QUP=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y CONFIG_PINCTRL_MSM8998=y -CONFIG_PINCTRL_MSMFALCON=y +CONFIG_PINCTRL_SDM660=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_QPNP_PIN=y CONFIG_APSS_CORE_EA=y diff --git a/arch/arm/configs/msmfalcon-perf_defconfig b/arch/arm/configs/msmfalcon-perf_defconfig deleted file mode 100644 index 211ec1c6cabc..000000000000 --- a/arch/arm/configs/msmfalcon-perf_defconfig +++ /dev/null @@ -1,621 +0,0 @@ -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_AUDIT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_RCU_EXPERT=y -CONFIG_RCU_FAST_NO_HZ=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_CPU_MAX_BUF_SHIFT=17 -CONFIG_CGROUP_FREEZER=y -CONFIG_CPUSETS=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_CGROUP_SCHEDTUNE=y -CONFIG_MEMCG=y -CONFIG_MEMCG_SWAP=y -CONFIG_RT_GROUP_SCHED=y -CONFIG_SCHED_HMP=y -CONFIG_SCHED_HMP_CSTATE_AWARE=y -CONFIG_SCHED_CORE_CTL=y -CONFIG_NAMESPACES=y -# CONFIG_UTS_NS is not set -# CONFIG_PID_NS is not set -CONFIG_SCHED_AUTOGROUP=y -CONFIG_SCHED_TUNE=y -CONFIG_BLK_DEV_INITRD=y -# CONFIG_RD_XZ is not set -# CONFIG_RD_LZO is not set -# CONFIG_RD_LZ4 is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_KALLSYMS_ALL=y -# CONFIG_MEMBARRIER is not set -CONFIG_EMBEDDED=y -# CONFIG_SLUB_DEBUG is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_PROFILING=y -CONFIG_CC_STACKPROTECTOR_REGULAR=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SIG=y -CONFIG_MODULE_SIG_FORCE=y -CONFIG_MODULE_SIG_SHA512=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_PARTITION_ADVANCED=y -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_ARCH_QCOM=y -CONFIG_ARCH_MSMFALCON=y -CONFIG_ARCH_MSMTRITON=y -CONFIG_ARM_KERNMEM_PERMS=y -CONFIG_SMP=y -CONFIG_SCHED_MC=y -CONFIG_NR_CPUS=8 -CONFIG_ARM_PSCI=y -CONFIG_PREEMPT=y -CONFIG_AEABI=y -CONFIG_HIGHMEM=y -# CONFIG_HIGHPTE is not set -CONFIG_CLEANCACHE=y -CONFIG_CMA=y -CONFIG_CMA_DEBUGFS=y -CONFIG_ZSMALLOC=y -CONFIG_PROCESS_RECLAIM=y -CONFIG_SECCOMP=y -CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE=y -# CONFIG_CPU_FREQ_STAT is not set -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_INTERACTIVE=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_BOOST=y -CONFIG_CPU_IDLE=y -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_KERNEL_MODE_NEON=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_PM_AUTOSLEEP=y -CONFIG_PM_WAKELOCKS=y -CONFIG_PM_WAKELOCKS_LIMIT=0 -# CONFIG_PM_WAKELOCKS_GC is not set -CONFIG_PM_DEBUG=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM_USER=y -CONFIG_XFRM_STATISTICS=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_INET_AH=y -CONFIG_INET_ESP=y -CONFIG_INET_IPCOMP=y -# CONFIG_INET_LRO is not set -CONFIG_INET_DIAG_DESTROY=y -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y -CONFIG_IPV6_OPTIMISTIC_DAD=y -CONFIG_INET6_AH=y -CONFIG_INET6_ESP=y -CONFIG_INET6_IPCOMP=y -CONFIG_IPV6_MIP6=y -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_IPV6_SUBTREES=y -CONFIG_NETFILTER=y -CONFIG_NF_CONNTRACK=y -CONFIG_NF_CONNTRACK_SECMARK=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CT_PROTO_DCCP=y -CONFIG_NF_CT_PROTO_SCTP=y -CONFIG_NF_CT_PROTO_UDPLITE=y -CONFIG_NF_CONNTRACK_AMANDA=y -CONFIG_NF_CONNTRACK_FTP=y -CONFIG_NF_CONNTRACK_H323=y -CONFIG_NF_CONNTRACK_IRC=y -CONFIG_NF_CONNTRACK_NETBIOS_NS=y -CONFIG_NF_CONNTRACK_PPTP=y -CONFIG_NF_CONNTRACK_SANE=y -CONFIG_NF_CONNTRACK_TFTP=y -CONFIG_NF_CT_NETLINK=y -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y -CONFIG_NETFILTER_XT_TARGET_CONNMARK=y -CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y -CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y -CONFIG_NETFILTER_XT_TARGET_HARDIDLETIMER=y -CONFIG_NETFILTER_XT_TARGET_LOG=y -CONFIG_NETFILTER_XT_TARGET_MARK=y -CONFIG_NETFILTER_XT_TARGET_NFLOG=y -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y -CONFIG_NETFILTER_XT_TARGET_NOTRACK=y -CONFIG_NETFILTER_XT_TARGET_TEE=y -CONFIG_NETFILTER_XT_TARGET_TPROXY=y -CONFIG_NETFILTER_XT_TARGET_TRACE=y -CONFIG_NETFILTER_XT_TARGET_SECMARK=y -CONFIG_NETFILTER_XT_TARGET_TCPMSS=y -CONFIG_NETFILTER_XT_MATCH_COMMENT=y -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y -CONFIG_NETFILTER_XT_MATCH_CONNMARK=y -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y -CONFIG_NETFILTER_XT_MATCH_DSCP=y -CONFIG_NETFILTER_XT_MATCH_ESP=y -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y -CONFIG_NETFILTER_XT_MATCH_HELPER=y -CONFIG_NETFILTER_XT_MATCH_IPRANGE=y -# CONFIG_NETFILTER_XT_MATCH_L2TP is not set -CONFIG_NETFILTER_XT_MATCH_LENGTH=y -CONFIG_NETFILTER_XT_MATCH_LIMIT=y -CONFIG_NETFILTER_XT_MATCH_MAC=y -CONFIG_NETFILTER_XT_MATCH_MARK=y -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y -CONFIG_NETFILTER_XT_MATCH_POLICY=y -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y -CONFIG_NETFILTER_XT_MATCH_QTAGUID=y -CONFIG_NETFILTER_XT_MATCH_QUOTA=y -CONFIG_NETFILTER_XT_MATCH_QUOTA2=y -CONFIG_NETFILTER_XT_MATCH_SOCKET=y -CONFIG_NETFILTER_XT_MATCH_STATE=y -CONFIG_NETFILTER_XT_MATCH_STATISTIC=y -CONFIG_NETFILTER_XT_MATCH_STRING=y -CONFIG_NETFILTER_XT_MATCH_TIME=y -CONFIG_NETFILTER_XT_MATCH_U32=y -CONFIG_NF_CONNTRACK_IPV4=y -CONFIG_IP_NF_IPTABLES=y -CONFIG_IP_NF_MATCH_AH=y -CONFIG_IP_NF_MATCH_ECN=y -CONFIG_IP_NF_MATCH_RPFILTER=y -CONFIG_IP_NF_MATCH_TTL=y -CONFIG_IP_NF_FILTER=y -CONFIG_IP_NF_TARGET_REJECT=y -CONFIG_IP_NF_NAT=y -CONFIG_IP_NF_TARGET_MASQUERADE=y -CONFIG_IP_NF_TARGET_NETMAP=y -CONFIG_IP_NF_TARGET_REDIRECT=y -CONFIG_IP_NF_MANGLE=y -CONFIG_IP_NF_RAW=y -CONFIG_IP_NF_SECURITY=y -CONFIG_IP_NF_ARPTABLES=y -CONFIG_IP_NF_ARPFILTER=y -CONFIG_IP_NF_ARP_MANGLE=y -CONFIG_NF_CONNTRACK_IPV6=y -CONFIG_IP6_NF_IPTABLES=y -CONFIG_IP6_NF_MATCH_RPFILTER=y -CONFIG_IP6_NF_FILTER=y -CONFIG_IP6_NF_TARGET_REJECT=y -CONFIG_IP6_NF_MANGLE=y -CONFIG_IP6_NF_RAW=y -CONFIG_BRIDGE_NF_EBTABLES=y -CONFIG_BRIDGE_EBT_BROUTE=y -CONFIG_L2TP=y -CONFIG_L2TP_DEBUGFS=y -CONFIG_L2TP_V3=y -CONFIG_L2TP_IP=y -CONFIG_L2TP_ETH=y -CONFIG_BRIDGE=y -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_HTB=y -CONFIG_NET_SCH_PRIO=y -CONFIG_NET_SCH_MULTIQ=y -CONFIG_NET_SCH_INGRESS=y -CONFIG_NET_CLS_FW=y -CONFIG_NET_CLS_U32=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_FLOW=y -CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_CMP=y -CONFIG_NET_EMATCH_NBYTE=y -CONFIG_NET_EMATCH_U32=y -CONFIG_NET_EMATCH_META=y -CONFIG_NET_EMATCH_TEXT=y -CONFIG_NET_CLS_ACT=y -CONFIG_NET_ACT_GACT=y -CONFIG_NET_ACT_MIRRED=y -CONFIG_NET_ACT_SKBEDIT=y -CONFIG_DNS_RESOLVER=y -CONFIG_RMNET_DATA=y -CONFIG_RMNET_DATA_FC=y -CONFIG_RMNET_DATA_DEBUG_PKT=y -CONFIG_SOCKEV_NLMCAST=y -CONFIG_BT=y -CONFIG_MSM_BT_POWER=y -CONFIG_BTFM_SLIM=y -CONFIG_BTFM_SLIM_WCN3990=y -CONFIG_CFG80211=y -CONFIG_CFG80211_INTERNAL_REGDB=y -# CONFIG_CFG80211_CRDA_SUPPORT is not set -CONFIG_RFKILL=y -CONFIG_NFC_NQ=y -CONFIG_IPC_ROUTER=y -CONFIG_IPC_ROUTER_SECURITY=y -CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y -CONFIG_DMA_CMA=y -CONFIG_CMA_SIZE_MBYTES=40 -CONFIG_ZRAM=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_QSEECOM=y -CONFIG_HDCP_QSEECOM=y -CONFIG_UID_CPUTIME=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -CONFIG_CHR_DEV_SCH=y -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y -CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_SCSI_UFSHCD=y -CONFIG_SCSI_UFSHCD_PLATFORM=y -CONFIG_SCSI_UFS_QCOM=y -CONFIG_SCSI_UFS_QCOM_ICE=y -CONFIG_MD=y -CONFIG_BLK_DEV_DM=y -CONFIG_DM_CRYPT=y -CONFIG_DM_REQ_CRYPT=y -CONFIG_DM_UEVENT=y -CONFIG_DM_VERITY=y -CONFIG_NETDEVICES=y -CONFIG_BONDING=y -CONFIG_DUMMY=y -CONFIG_TUN=y -CONFIG_RNDIS_IPA=y -CONFIG_PPP=y -CONFIG_PPP_BSDCOMP=y -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_MPPE=y -CONFIG_PPP_MULTILINK=y -CONFIG_PPPOE=y -CONFIG_PPPOL2TP=y -CONFIG_PPPOLAC=y -CONFIG_PPPOPNS=y -CONFIG_PPP_ASYNC=y -CONFIG_PPP_SYNC_TTY=y -CONFIG_USB_USBNET=y -CONFIG_WCNSS_MEM_PRE_ALLOC=y -CONFIG_ATH_CARDS=y -CONFIG_CLD_LL_CORE=y -CONFIG_QPNP_POWER_ON=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_KEYRESET=y -CONFIG_KEYBOARD_GPIO=y -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_JOYSTICK=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_v21=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y -CONFIG_SECURE_TOUCH=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_HBTP_INPUT=y -CONFIG_INPUT_KEYCHORD=y -CONFIG_INPUT_UINPUT=y -CONFIG_INPUT_GPIO=y -# CONFIG_SERIO_SERPORT is not set -# CONFIG_VT is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_DEVMEM is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_MSM=y -CONFIG_SERIAL_MSM_HS=y -CONFIG_SERIAL_MSM_SMD=y -CONFIG_DIAG_CHAR=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MSM_LEGACY=y -CONFIG_MSM_ADSPRPC=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MSM_V2=y -CONFIG_SLIMBUS_MSM_NGD=y -CONFIG_SOUNDWIRE=y -CONFIG_SPI=y -CONFIG_SPI_QUP=y -CONFIG_SPI_SPIDEV=y -CONFIG_SPMI=y -CONFIG_PINCTRL_MSMFALCON=y -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_QPNP_PIN=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_QCOM=y -CONFIG_QCOM_DLOAD_MODE=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_APSS_CORE_EA=y -CONFIG_MSM_APM=y -CONFIG_QPNP_SMBCHARGER=y -CONFIG_SMB135X_CHARGER=y -CONFIG_SMB1351_USB_CHARGER=y -CONFIG_MSM_BCL_CTL=y -CONFIG_MSM_BCL_PERIPHERAL_CTL=y -CONFIG_BATTERY_BCL=y -CONFIG_QPNP_SMB2=y -CONFIG_SMB138X_CHARGER=y -CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y -CONFIG_THERMAL=y -CONFIG_CPU_THERMAL=y -CONFIG_LIMITS_MONITOR=y -CONFIG_LIMITS_LITE_HW=y -CONFIG_THERMAL_MONITOR=y -CONFIG_THERMAL_TSENS8974=y -CONFIG_THERMAL_QPNP=y -CONFIG_THERMAL_QPNP_ADC_TM=y -CONFIG_QCOM_THERMAL_LIMITS_DCVS=y -CONFIG_MFD_SPMI_PMIC=y -CONFIG_MFD_I2C_PMIC=y -CONFIG_WCD9335_CODEC=y -CONFIG_WCD934X_CODEC=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_MSM_GFX_LDO=y -CONFIG_REGULATOR_RPM_SMD=y -CONFIG_REGULATOR_QPNP=y -CONFIG_REGULATOR_QPNP_LABIBB=y -CONFIG_REGULATOR_SPM=y -CONFIG_REGULATOR_CPR3_HMSS=y -CONFIG_REGULATOR_CPR3_MMSS=y -CONFIG_REGULATOR_CPRH_KBSS=y -CONFIG_REGULATOR_CPR4_MMSS_LDO=y -CONFIG_REGULATOR_MEM_ACC=y -CONFIG_REGULATOR_PROXY_CONSUMER=y -CONFIG_REGULATOR_STUB=y -CONFIG_MEDIA_SUPPORT=y -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_CONTROLLER=y -CONFIG_VIDEO_V4L2_SUBDEV_API=y -CONFIG_VIDEO_ADV_DEBUG=y -CONFIG_VIDEO_FIXED_MINOR_RANGES=y -CONFIG_MEDIA_USB_SUPPORT=y -CONFIG_USB_VIDEO_CLASS=y -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_MSM_CAMERA=y -CONFIG_MSM_CAMERA_DEBUG=y -CONFIG_MSM_SDE_ROTATOR=y -CONFIG_QCOM_KGSL=y -CONFIG_FB=y -CONFIG_FB_VIRTUAL=y -CONFIG_FB_MSM=y -CONFIG_FB_MSM_MDSS=y -CONFIG_FB_MSM_MDSS_WRITEBACK=y -CONFIG_FB_MSM_MDSS_HDMI_PANEL=y -CONFIG_FB_MSM_MDSS_DP_PANEL=y -CONFIG_FB_MSM_MDSS_XLOG_DEBUG=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_USB_AUDIO=y -CONFIG_SND_USB_AUDIO_QMI=y -CONFIG_SND_SOC=y -CONFIG_SND_SOC_FALCON=y -CONFIG_UHID=y -CONFIG_HID_APPLE=y -CONFIG_HID_ELECOM=y -CONFIG_HID_MAGICMOUSE=y -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MULTITOUCH=y -CONFIG_HID_PLANTRONICS=y -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_STORAGE=y -CONFIG_USB_DWC3=y -CONFIG_USB_ISP1760=y -CONFIG_USB_ISP1760_HOST_ROLE=y -CONFIG_USB_PD_POLICY=y -CONFIG_QPNP_USB_PDPHY=y -CONFIG_USB_EHSET_TEST_FIXTURE=y -CONFIG_USB_OTG_WAKELOCK=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_USB_MSM_SSPHY_QMP=y -CONFIG_MSM_QUSB_PHY=y -CONFIG_DUAL_ROLE_USB_INTF=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_VBUS_DRAW=500 -CONFIG_USB_CONFIGFS=y -CONFIG_USB_CONFIGFS_NCM=y -CONFIG_USB_CONFIGFS_QCRNDIS=y -CONFIG_USB_CONFIGFS_RMNET_BAM=y -CONFIG_USB_CONFIGFS_MASS_STORAGE=y -CONFIG_USB_CONFIGFS_F_FS=y -CONFIG_USB_CONFIGFS_F_MTP=y -CONFIG_USB_CONFIGFS_F_PTP=y -CONFIG_USB_CONFIGFS_F_ACC=y -CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y -CONFIG_USB_CONFIGFS_UEVENT=y -CONFIG_USB_CONFIGFS_F_MIDI=y -CONFIG_USB_CONFIGFS_F_HID=y -CONFIG_USB_CONFIGFS_F_DIAG=y -CONFIG_USB_CONFIGFS_F_GSI=y -CONFIG_USB_CONFIGFS_F_CDEV=y -CONFIG_USB_CONFIGFS_F_QDSS=y -CONFIG_MMC=y -CONFIG_MMC_PERF_PROFILING=y -CONFIG_MMC_PARANOID_SD_INIT=y -CONFIG_MMC_CLKGATE=y -CONFIG_MMC_BLOCK_MINORS=32 -CONFIG_MMC_TEST=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_MSM=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_QPNP=y -CONFIG_LEDS_QPNP_FLASH_V2=y -CONFIG_LEDS_QPNP_WLED=y -CONFIG_LEDS_SYSCON=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_SWITCH=y -CONFIG_EDAC=y -CONFIG_EDAC_MM_EDAC=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_QPNP=y -CONFIG_DMADEVICES=y -CONFIG_QCOM_SPS_DMA=y -CONFIG_UIO=y -CONFIG_UIO_MSM_SHAREDMEM=y -CONFIG_STAGING=y -CONFIG_ASHMEM=y -CONFIG_ANDROID_TIMED_GPIO=y -CONFIG_ANDROID_LOW_MEMORY_KILLER=y -CONFIG_ION=y -CONFIG_ION_MSM=y -CONFIG_QPNP_REVID=y -CONFIG_QPNP_COINCELL=y -CONFIG_SPS=y -CONFIG_SPS_SUPPORT_NDP_BAM=y -CONFIG_IPA=y -CONFIG_RMNET_IPA=y -CONFIG_GSI=y -CONFIG_IPA3=y -CONFIG_RMNET_IPA3=y -CONFIG_GPIO_USB_DETECT=y -CONFIG_SEEMP_CORE=y -CONFIG_USB_BAM=y -CONFIG_QCOM_CLK_SMD_RPM=y -CONFIG_MSM_GCC_FALCON=y -CONFIG_QCOM_MDSS_PLL=y -CONFIG_REMOTE_SPINLOCK_MSM=y -CONFIG_ARM_SMMU=y -CONFIG_QCOM_COMMON_LOG=y -CONFIG_MSM_SMEM=y -CONFIG_QPNP_HAPTIC=y -CONFIG_MSM_SMD=y -CONFIG_MSM_SMD_DEBUG=y -CONFIG_MSM_GLINK=y -CONFIG_MSM_GLINK_LOOPBACK_SERVER=y -CONFIG_MSM_GLINK_SMD_XPRT=y -CONFIG_MSM_GLINK_SMEM_NATIVE_XPRT=y -CONFIG_MSM_SPCOM=y -CONFIG_MSM_SMEM_LOGGING=y -CONFIG_MSM_SMP2P=y -CONFIG_MSM_SMP2P_TEST=y -CONFIG_MSM_QMI_INTERFACE=y -CONFIG_QCOM_BUS_SCALING=y -CONFIG_MSM_SERVICE_LOCATOR=y -CONFIG_QCOM_DCC=y -CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y -CONFIG_MSM_SYSMON_GLINK_COMM=y -CONFIG_MSM_IPC_ROUTER_GLINK_XPRT=y -CONFIG_MSM_GLINK_PKT=y -CONFIG_MSM_SPM=y -CONFIG_QCOM_SCM=y -CONFIG_QCOM_WATCHDOG_V2=y -CONFIG_QCOM_IRQ_HELPER=y -CONFIG_QCOM_MEMORY_DUMP_V2=y -CONFIG_ICNSS=y -CONFIG_MSM_GLADIATOR_ERP_V2=y -CONFIG_PANIC_ON_GLADIATOR_ERROR_V2=y -CONFIG_MSM_GLADIATOR_HANG_DETECT=y -CONFIG_MSM_RUN_QUEUE_STATS=y -CONFIG_MSM_BOOT_STATS=y -CONFIG_QCOM_CPUSS_DUMP=y -CONFIG_MSM_ADSP_LOADER=y -CONFIG_MSM_PERFORMANCE=y -CONFIG_MSM_SUBSYSTEM_RESTART=y -CONFIG_MSM_PIL=y -CONFIG_MSM_PIL_SSR_GENERIC=y -CONFIG_MSM_PIL_MSS_QDSP6V5=y -CONFIG_TRACER_PKT=y -CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y -CONFIG_MSM_MPM_OF=y -CONFIG_MSM_EVENT_TIMER=y -CONFIG_MSM_AVTIMER=y -CONFIG_QCOM_REMOTEQDSS=y -CONFIG_MSM_SERVICE_NOTIFIER=y -CONFIG_MSM_RPM_RBCPR_STATS_V2_LOG=y -CONFIG_MSM_RPM_LOG=y -CONFIG_MSM_RPM_STATS_LOG=y -# CONFIG_WCD_DSP_GLINK is not set -CONFIG_QCOM_SMCINVOKE=y -CONFIG_MEM_SHARE_QMI_SERVICE=y -CONFIG_QCOM_BIMC_BWMON=y -CONFIG_ARM_MEMLAT_MON=y -CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y -CONFIG_DEVFREQ_GOV_MEMLAT=y -CONFIG_QCOM_DEVFREQ_DEVBW=y -CONFIG_DEVFREQ_SPDM=y -CONFIG_PM_DEVFREQ_EVENT=y -CONFIG_EXTCON=y -CONFIG_IIO=y -CONFIG_QCOM_RRADC=y -CONFIG_QCOM_TADC=y -CONFIG_PWM=y -CONFIG_PWM_QPNP=y -CONFIG_ARM_GIC_V3_ACL=y -CONFIG_ANDROID=y -CONFIG_ANDROID_BINDER_IPC=y -CONFIG_MSM_TZ_LOG=y -CONFIG_SENSORS_SSC=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT3_FS=y -CONFIG_EXT4_FS_SECURITY=y -CONFIG_EXT4_ENCRYPTION=y -CONFIG_EXT4_FS_ENCRYPTION=y -CONFIG_EXT4_FS_ICE_ENCRYPTION=y -CONFIG_EXT4_DEBUG=y -CONFIG_FUSE_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_ECRYPT_FS=y -CONFIG_ECRYPT_FS_MESSAGING=y -# CONFIG_NETWORK_FILESYSTEMS is not set -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_INFO=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_PAGE_EXTENSION=y -CONFIG_LOCKUP_DETECTOR=y -CONFIG_WQ_WATCHDOG=y -CONFIG_PANIC_TIMEOUT=5 -# CONFIG_SCHED_DEBUG is not set -CONFIG_PANIC_ON_SCHED_BUG=y -CONFIG_PANIC_ON_RT_THROTTLING=y -CONFIG_SCHEDSTATS=y -CONFIG_SCHED_STACK_END_CHECK=y -CONFIG_TIMER_STATS=y -# CONFIG_DEBUG_PREEMPT is not set -CONFIG_IPC_LOGGING=y -CONFIG_FUNCTION_TRACER=y -CONFIG_TRACER_SNAPSHOT=y -CONFIG_BLK_DEV_IO_TRACE=y -CONFIG_CPU_FREQ_SWITCH_PROFILER=y -CONFIG_PID_IN_CONTEXTIDR=y -CONFIG_DEBUG_SET_MODULE_RONX=y -CONFIG_CORESIGHT=y -CONFIG_CORESIGHT_EVENT=y -CONFIG_CORESIGHT_QCOM_REPLICATOR=y -CONFIG_CORESIGHT_STM=y -CONFIG_CORESIGHT_HWEVENT=y -CONFIG_CORESIGHT_CTI=y -CONFIG_CORESIGHT_TPDA=y -CONFIG_CORESIGHT_TPDM=y -CONFIG_CORESIGHT_QPDI=y -CONFIG_CORESIGHT_SOURCE_DUMMY=y -CONFIG_PFK=y -CONFIG_SECURITY=y -CONFIG_SECURITY_SELINUX=y -CONFIG_SECURITY_SMACK=y -CONFIG_CRYPTO_ECHAINIV=y -CONFIG_CRYPTO_XCBC=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_ANSI_CPRNG=y -CONFIG_CRYPTO_DEV_QCRYPTO=y -CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y -CONFIG_CRYPTO_DEV_QCEDEV=y -CONFIG_CRYPTO_DEV_OTA_CRYPTO=y -CONFIG_CRYPTO_DEV_QCOM_ICE=y -CONFIG_XZ_DEC=y diff --git a/arch/arm/configs/msmfalcon_defconfig b/arch/arm/configs/msmfalcon_defconfig deleted file mode 100644 index 10981157afc3..000000000000 --- a/arch/arm/configs/msmfalcon_defconfig +++ /dev/null @@ -1,665 +0,0 @@ -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_AUDIT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_RCU_EXPERT=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_CPU_MAX_BUF_SHIFT=17 -CONFIG_CGROUPS=y -CONFIG_CGROUP_DEBUG=y -CONFIG_CGROUP_FREEZER=y -CONFIG_CPUSETS=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_CGROUP_SCHEDTUNE=y -CONFIG_MEMCG=y -CONFIG_MEMCG_SWAP=y -CONFIG_CGROUP_SCHED=y -CONFIG_RT_GROUP_SCHED=y -CONFIG_SCHED_HMP=y -CONFIG_SCHED_HMP_CSTATE_AWARE=y -CONFIG_SCHED_CORE_CTL=y -CONFIG_NAMESPACES=y -# CONFIG_UTS_NS is not set -# CONFIG_PID_NS is not set -CONFIG_SCHED_TUNE=y -CONFIG_BLK_DEV_INITRD=y -# CONFIG_RD_XZ is not set -# CONFIG_RD_LZO is not set -# CONFIG_RD_LZ4 is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_KALLSYMS_ALL=y -# CONFIG_MEMBARRIER is not set -CONFIG_EMBEDDED=y -# CONFIG_COMPAT_BRK is not set -CONFIG_PROFILING=y -CONFIG_CC_STACKPROTECTOR_REGULAR=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SIG=y -CONFIG_MODULE_SIG_FORCE=y -CONFIG_MODULE_SIG_SHA512=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_PARTITION_ADVANCED=y -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_ARCH_QCOM=y -CONFIG_ARCH_MSMFALCON=y -CONFIG_ARCH_MSMTRITON=y -CONFIG_ARM_KERNMEM_PERMS=y -CONFIG_SMP=y -CONFIG_SCHED_MC=y -CONFIG_NR_CPUS=8 -CONFIG_ARM_PSCI=y -CONFIG_PREEMPT=y -CONFIG_AEABI=y -CONFIG_HIGHMEM=y -# CONFIG_HIGHPTE is not set -CONFIG_CLEANCACHE=y -CONFIG_CMA=y -CONFIG_CMA_DEBUGFS=y -CONFIG_ZSMALLOC=y -CONFIG_PROCESS_RECLAIM=y -CONFIG_SECCOMP=y -CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE=y -# CONFIG_CPU_FREQ_STAT is not set -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_INTERACTIVE=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_IDLE=y -CONFIG_VFP=y -CONFIG_NEON=y -CONFIG_KERNEL_MODE_NEON=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_PM_AUTOSLEEP=y -CONFIG_PM_WAKELOCKS=y -CONFIG_PM_WAKELOCKS_LIMIT=0 -# CONFIG_PM_WAKELOCKS_GC is not set -CONFIG_PM_DEBUG=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM_USER=y -CONFIG_XFRM_STATISTICS=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_INET_AH=y -CONFIG_INET_ESP=y -CONFIG_INET_IPCOMP=y -# CONFIG_INET_LRO is not set -CONFIG_INET_DIAG_DESTROY=y -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y -CONFIG_IPV6_OPTIMISTIC_DAD=y -CONFIG_INET6_AH=y -CONFIG_INET6_ESP=y -CONFIG_INET6_IPCOMP=y -CONFIG_IPV6_MIP6=y -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_IPV6_SUBTREES=y -CONFIG_NETFILTER=y -CONFIG_NF_CONNTRACK=y -CONFIG_NF_CONNTRACK_SECMARK=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CT_PROTO_DCCP=y -CONFIG_NF_CT_PROTO_SCTP=y -CONFIG_NF_CT_PROTO_UDPLITE=y -CONFIG_NF_CONNTRACK_AMANDA=y -CONFIG_NF_CONNTRACK_FTP=y -CONFIG_NF_CONNTRACK_H323=y -CONFIG_NF_CONNTRACK_IRC=y -CONFIG_NF_CONNTRACK_NETBIOS_NS=y -CONFIG_NF_CONNTRACK_PPTP=y -CONFIG_NF_CONNTRACK_SANE=y -CONFIG_NF_CONNTRACK_TFTP=y -CONFIG_NF_CT_NETLINK=y -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y -CONFIG_NETFILTER_XT_TARGET_CONNMARK=y -CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y -CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y -CONFIG_NETFILTER_XT_TARGET_HARDIDLETIMER=y -CONFIG_NETFILTER_XT_TARGET_LOG=y -CONFIG_NETFILTER_XT_TARGET_MARK=y -CONFIG_NETFILTER_XT_TARGET_NFLOG=y -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y -CONFIG_NETFILTER_XT_TARGET_NOTRACK=y -CONFIG_NETFILTER_XT_TARGET_TEE=y -CONFIG_NETFILTER_XT_TARGET_TPROXY=y -CONFIG_NETFILTER_XT_TARGET_TRACE=y -CONFIG_NETFILTER_XT_TARGET_SECMARK=y -CONFIG_NETFILTER_XT_TARGET_TCPMSS=y -CONFIG_NETFILTER_XT_MATCH_COMMENT=y -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y -CONFIG_NETFILTER_XT_MATCH_CONNMARK=y -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y -CONFIG_NETFILTER_XT_MATCH_DSCP=y -CONFIG_NETFILTER_XT_MATCH_ESP=y -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y -CONFIG_NETFILTER_XT_MATCH_HELPER=y -CONFIG_NETFILTER_XT_MATCH_IPRANGE=y -# CONFIG_NETFILTER_XT_MATCH_L2TP is not set -CONFIG_NETFILTER_XT_MATCH_LENGTH=y -CONFIG_NETFILTER_XT_MATCH_LIMIT=y -CONFIG_NETFILTER_XT_MATCH_MAC=y -CONFIG_NETFILTER_XT_MATCH_MARK=y -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y -CONFIG_NETFILTER_XT_MATCH_POLICY=y -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y -CONFIG_NETFILTER_XT_MATCH_QTAGUID=y -CONFIG_NETFILTER_XT_MATCH_QUOTA=y -CONFIG_NETFILTER_XT_MATCH_QUOTA2=y -CONFIG_NETFILTER_XT_MATCH_SOCKET=y -CONFIG_NETFILTER_XT_MATCH_STATE=y -CONFIG_NETFILTER_XT_MATCH_STATISTIC=y -CONFIG_NETFILTER_XT_MATCH_STRING=y -CONFIG_NETFILTER_XT_MATCH_TIME=y -CONFIG_NETFILTER_XT_MATCH_U32=y -CONFIG_NF_CONNTRACK_IPV4=y -CONFIG_IP_NF_IPTABLES=y -CONFIG_IP_NF_MATCH_AH=y -CONFIG_IP_NF_MATCH_ECN=y -CONFIG_IP_NF_MATCH_RPFILTER=y -CONFIG_IP_NF_MATCH_TTL=y -CONFIG_IP_NF_FILTER=y -CONFIG_IP_NF_TARGET_REJECT=y -CONFIG_IP_NF_NAT=y -CONFIG_IP_NF_TARGET_MASQUERADE=y -CONFIG_IP_NF_TARGET_NETMAP=y -CONFIG_IP_NF_TARGET_REDIRECT=y -CONFIG_IP_NF_MANGLE=y -CONFIG_IP_NF_RAW=y -CONFIG_IP_NF_SECURITY=y -CONFIG_IP_NF_ARPTABLES=y -CONFIG_IP_NF_ARPFILTER=y -CONFIG_IP_NF_ARP_MANGLE=y -CONFIG_NF_CONNTRACK_IPV6=y -CONFIG_IP6_NF_IPTABLES=y -CONFIG_IP6_NF_MATCH_RPFILTER=y -CONFIG_IP6_NF_FILTER=y -CONFIG_IP6_NF_TARGET_REJECT=y -CONFIG_IP6_NF_MANGLE=y -CONFIG_IP6_NF_RAW=y -CONFIG_BRIDGE_NF_EBTABLES=y -CONFIG_BRIDGE_EBT_BROUTE=y -CONFIG_L2TP=y -CONFIG_L2TP_DEBUGFS=y -CONFIG_L2TP_V3=y -CONFIG_L2TP_IP=y -CONFIG_L2TP_ETH=y -CONFIG_BRIDGE=y -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_HTB=y -CONFIG_NET_SCH_PRIO=y -CONFIG_NET_SCH_MULTIQ=y -CONFIG_NET_SCH_INGRESS=y -CONFIG_NET_CLS_FW=y -CONFIG_NET_CLS_U32=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_FLOW=y -CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_CMP=y -CONFIG_NET_EMATCH_NBYTE=y -CONFIG_NET_EMATCH_U32=y -CONFIG_NET_EMATCH_META=y -CONFIG_NET_EMATCH_TEXT=y -CONFIG_NET_CLS_ACT=y -CONFIG_NET_ACT_GACT=y -CONFIG_NET_ACT_MIRRED=y -CONFIG_NET_ACT_SKBEDIT=y -CONFIG_DNS_RESOLVER=y -CONFIG_RMNET_DATA=y -CONFIG_RMNET_DATA_FC=y -CONFIG_RMNET_DATA_DEBUG_PKT=y -CONFIG_SOCKEV_NLMCAST=y -CONFIG_BT=y -CONFIG_MSM_BT_POWER=y -CONFIG_BTFM_SLIM=y -CONFIG_BTFM_SLIM_WCN3990=y -CONFIG_CFG80211=y -CONFIG_CFG80211_INTERNAL_REGDB=y -# CONFIG_CFG80211_CRDA_SUPPORT is not set -CONFIG_RFKILL=y -CONFIG_NFC_NQ=y -CONFIG_IPC_ROUTER=y -CONFIG_IPC_ROUTER_SECURITY=y -CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y -CONFIG_DMA_CMA=y -CONFIG_CMA_SIZE_MBYTES=40 -CONFIG_ZRAM=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_QSEECOM=y -CONFIG_HDCP_QSEECOM=y -CONFIG_UID_CPUTIME=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -CONFIG_CHR_DEV_SCH=y -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y -CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_SCSI_UFSHCD=y -CONFIG_SCSI_UFSHCD_PLATFORM=y -CONFIG_SCSI_UFS_QCOM=y -CONFIG_SCSI_UFS_QCOM_ICE=y -CONFIG_MD=y -CONFIG_BLK_DEV_DM=y -CONFIG_DM_CRYPT=y -CONFIG_DM_REQ_CRYPT=y -CONFIG_DM_UEVENT=y -CONFIG_DM_VERITY=y -CONFIG_NETDEVICES=y -CONFIG_BONDING=y -CONFIG_DUMMY=y -CONFIG_TUN=y -CONFIG_RNDIS_IPA=y -CONFIG_PPP=y -CONFIG_PPP_BSDCOMP=y -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_MPPE=y -CONFIG_PPP_MULTILINK=y -CONFIG_PPPOE=y -CONFIG_PPPOL2TP=y -CONFIG_PPPOLAC=y -CONFIG_PPPOPNS=y -CONFIG_PPP_ASYNC=y -CONFIG_PPP_SYNC_TTY=y -CONFIG_USB_USBNET=y -CONFIG_WCNSS_MEM_PRE_ALLOC=y -CONFIG_ATH_CARDS=y -CONFIG_CLD_LL_CORE=y -CONFIG_QPNP_POWER_ON=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_KEYRESET=y -CONFIG_KEYBOARD_GPIO=y -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_JOYSTICK=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_v21=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y -CONFIG_SECURE_TOUCH=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_HBTP_INPUT=y -CONFIG_INPUT_KEYCHORD=y -CONFIG_INPUT_UINPUT=y -CONFIG_INPUT_GPIO=y -# CONFIG_SERIO_SERPORT is not set -# CONFIG_VT is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_MSM=y -CONFIG_SERIAL_MSM_CONSOLE=y -CONFIG_SERIAL_MSM_HS=y -CONFIG_SERIAL_MSM_SMD=y -CONFIG_DIAG_CHAR=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MSM_LEGACY=y -CONFIG_MSM_ADSPRPC=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MSM_V2=y -CONFIG_SLIMBUS_MSM_NGD=y -CONFIG_SOUNDWIRE=y -CONFIG_SPI=y -CONFIG_SPI_QUP=y -CONFIG_SPI_SPIDEV=y -CONFIG_SPMI=y -CONFIG_PINCTRL_MSMFALCON=y -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_QPNP_PIN=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_QCOM=y -CONFIG_QCOM_DLOAD_MODE=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_APSS_CORE_EA=y -CONFIG_MSM_APM=y -CONFIG_QPNP_SMBCHARGER=y -CONFIG_SMB135X_CHARGER=y -CONFIG_SMB1351_USB_CHARGER=y -CONFIG_MSM_BCL_CTL=y -CONFIG_MSM_BCL_PERIPHERAL_CTL=y -CONFIG_BATTERY_BCL=y -CONFIG_QPNP_SMB2=y -CONFIG_SMB138X_CHARGER=y -CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y -CONFIG_THERMAL=y -CONFIG_CPU_THERMAL=y -CONFIG_LIMITS_MONITOR=y -CONFIG_LIMITS_LITE_HW=y -CONFIG_THERMAL_MONITOR=y -CONFIG_THERMAL_TSENS8974=y -CONFIG_THERMAL_QPNP=y -CONFIG_THERMAL_QPNP_ADC_TM=y -CONFIG_QCOM_THERMAL_LIMITS_DCVS=y -CONFIG_MFD_SPMI_PMIC=y -CONFIG_MFD_I2C_PMIC=y -CONFIG_WCD9335_CODEC=y -CONFIG_WCD934X_CODEC=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_MSM_GFX_LDO=y -CONFIG_REGULATOR_RPM_SMD=y -CONFIG_REGULATOR_QPNP=y -CONFIG_REGULATOR_QPNP_LABIBB=y -CONFIG_REGULATOR_QPNP_LCDB=y -CONFIG_REGULATOR_SPM=y -CONFIG_REGULATOR_CPR3_HMSS=y -CONFIG_REGULATOR_CPR3_MMSS=y -CONFIG_REGULATOR_CPRH_KBSS=y -CONFIG_REGULATOR_CPR4_MMSS_LDO=y -CONFIG_REGULATOR_MEM_ACC=y -CONFIG_REGULATOR_PROXY_CONSUMER=y -CONFIG_REGULATOR_STUB=y -CONFIG_MEDIA_SUPPORT=y -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_CONTROLLER=y -CONFIG_VIDEO_V4L2_SUBDEV_API=y -CONFIG_VIDEO_ADV_DEBUG=y -CONFIG_VIDEO_FIXED_MINOR_RANGES=y -CONFIG_MEDIA_USB_SUPPORT=y -CONFIG_USB_VIDEO_CLASS=y -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_MSM_CAMERA=y -CONFIG_MSM_CAMERA_DEBUG=y -CONFIG_MSM_VIDC_V4L2=m -CONFIG_MSM_VIDC_GOVERNORS=m -CONFIG_MSM_SDE_ROTATOR=y -CONFIG_MSM_SDE_ROTATOR_EVTLOG_DEBUG=y -CONFIG_QCOM_KGSL=y -CONFIG_FB=y -CONFIG_FB_VIRTUAL=y -CONFIG_FB_MSM=y -CONFIG_FB_MSM_MDSS=y -CONFIG_FB_MSM_MDSS_WRITEBACK=y -CONFIG_FB_MSM_MDSS_HDMI_PANEL=y -CONFIG_FB_MSM_MDSS_DP_PANEL=y -CONFIG_FB_MSM_MDSS_XLOG_DEBUG=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_USB_AUDIO=y -CONFIG_SND_USB_AUDIO_QMI=y -CONFIG_SND_SOC=y -CONFIG_SND_SOC_FALCON=y -CONFIG_UHID=y -CONFIG_HID_APPLE=y -CONFIG_HID_ELECOM=y -CONFIG_HID_MAGICMOUSE=y -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MULTITOUCH=y -CONFIG_HID_PLANTRONICS=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_STORAGE=y -CONFIG_USB_DWC3=y -CONFIG_USB_ISP1760=y -CONFIG_USB_ISP1760_HOST_ROLE=y -CONFIG_USB_PD_POLICY=y -CONFIG_QPNP_USB_PDPHY=y -CONFIG_USB_EHSET_TEST_FIXTURE=y -CONFIG_USB_OTG_WAKELOCK=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_USB_MSM_SSPHY_QMP=y -CONFIG_MSM_QUSB_PHY=y -CONFIG_DUAL_ROLE_USB_INTF=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_VBUS_DRAW=500 -CONFIG_USB_CONFIGFS=y -CONFIG_USB_CONFIGFS_NCM=y -CONFIG_USB_CONFIGFS_QCRNDIS=y -CONFIG_USB_CONFIGFS_RMNET_BAM=y -CONFIG_USB_CONFIGFS_MASS_STORAGE=y -CONFIG_USB_CONFIGFS_F_FS=y -CONFIG_USB_CONFIGFS_F_MTP=y -CONFIG_USB_CONFIGFS_F_PTP=y -CONFIG_USB_CONFIGFS_F_ACC=y -CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y -CONFIG_USB_CONFIGFS_UEVENT=y -CONFIG_USB_CONFIGFS_F_MIDI=y -CONFIG_USB_CONFIGFS_F_HID=y -CONFIG_USB_CONFIGFS_F_DIAG=y -CONFIG_USB_CONFIGFS_F_GSI=y -CONFIG_USB_CONFIGFS_F_CDEV=y -CONFIG_USB_CONFIGFS_F_QDSS=y -CONFIG_MMC=y -CONFIG_MMC_PERF_PROFILING=y -CONFIG_MMC_PARANOID_SD_INIT=y -CONFIG_MMC_CLKGATE=y -CONFIG_MMC_BLOCK_MINORS=32 -CONFIG_MMC_TEST=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_MSM=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_QPNP=y -CONFIG_LEDS_QPNP_FLASH_V2=y -CONFIG_LEDS_QPNP_WLED=y -CONFIG_LEDS_SYSCON=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_SWITCH=y -CONFIG_EDAC=y -CONFIG_EDAC_MM_EDAC=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_QPNP=y -CONFIG_DMADEVICES=y -CONFIG_QCOM_SPS_DMA=y -CONFIG_UIO=y -CONFIG_UIO_MSM_SHAREDMEM=y -CONFIG_STAGING=y -CONFIG_ASHMEM=y -CONFIG_ANDROID_TIMED_GPIO=y -CONFIG_ANDROID_LOW_MEMORY_KILLER=y -CONFIG_ION=y -CONFIG_ION_MSM=y -CONFIG_QPNP_REVID=y -CONFIG_QPNP_COINCELL=y -CONFIG_SPS=y -CONFIG_SPS_SUPPORT_NDP_BAM=y -CONFIG_IPA=y -CONFIG_RMNET_IPA=y -CONFIG_GSI=y -CONFIG_IPA3=y -CONFIG_RMNET_IPA3=y -CONFIG_GPIO_USB_DETECT=y -CONFIG_SEEMP_CORE=y -CONFIG_USB_BAM=y -CONFIG_QCOM_CLK_SMD_RPM=y -CONFIG_MSM_GPUCC_FALCON=y -CONFIG_MSM_MMCC_FALCON=y -CONFIG_CLOCK_CPU_OSM=y -CONFIG_QCOM_MDSS_PLL=y -CONFIG_REMOTE_SPINLOCK_MSM=y -CONFIG_ARM_SMMU=y -CONFIG_IOMMU_DEBUG=y -CONFIG_IOMMU_DEBUG_TRACKING=y -CONFIG_IOMMU_TESTS=y -CONFIG_QCOM_COMMON_LOG=y -CONFIG_MSM_SMEM=y -CONFIG_QPNP_HAPTIC=y -CONFIG_MSM_SMD=y -CONFIG_MSM_SMD_DEBUG=y -CONFIG_MSM_GLINK=y -CONFIG_MSM_GLINK_LOOPBACK_SERVER=y -CONFIG_MSM_GLINK_SMD_XPRT=y -CONFIG_MSM_GLINK_SMEM_NATIVE_XPRT=y -CONFIG_MSM_SPCOM=y -CONFIG_MSM_SPSS_UTILS=y -CONFIG_MSM_SMEM_LOGGING=y -CONFIG_MSM_SMP2P=y -CONFIG_MSM_SMP2P_TEST=y -CONFIG_MSM_QMI_INTERFACE=y -CONFIG_QCOM_BUS_SCALING=y -CONFIG_MSM_SERVICE_LOCATOR=y -CONFIG_QCOM_DCC=y -CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y -CONFIG_MSM_SYSMON_GLINK_COMM=y -CONFIG_MSM_IPC_ROUTER_GLINK_XPRT=y -CONFIG_MSM_GLINK_PKT=y -CONFIG_MSM_SPM=y -CONFIG_QCOM_SCM=y -CONFIG_QCOM_WATCHDOG_V2=y -CONFIG_QCOM_IRQ_HELPER=y -CONFIG_QCOM_MEMORY_DUMP_V2=y -CONFIG_ICNSS=y -CONFIG_ICNSS_DEBUG=y -CONFIG_MSM_GLADIATOR_ERP_V2=y -CONFIG_PANIC_ON_GLADIATOR_ERROR_V2=y -CONFIG_MSM_GLADIATOR_HANG_DETECT=y -CONFIG_MSM_CORE_HANG_DETECT=y -CONFIG_MSM_RUN_QUEUE_STATS=y -# CONFIG_MSM_JTAGV8 is not set -CONFIG_MSM_BOOT_STATS=y -CONFIG_QCOM_CPUSS_DUMP=y -CONFIG_MSM_ADSP_LOADER=y -CONFIG_MSM_PERFORMANCE=y -CONFIG_MSM_SUBSYSTEM_RESTART=y -CONFIG_MSM_PIL=y -CONFIG_MSM_PIL_SSR_GENERIC=y -CONFIG_MSM_PIL_MSS_QDSP6V5=y -CONFIG_TRACER_PKT=y -CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y -CONFIG_MSM_MPM_OF=y -CONFIG_MSM_EVENT_TIMER=y -CONFIG_MSM_AVTIMER=y -CONFIG_QCOM_REMOTEQDSS=y -CONFIG_MSM_SERVICE_NOTIFIER=y -CONFIG_MSM_RPM_RBCPR_STATS_V2_LOG=y -CONFIG_MSM_RPM_LOG=y -CONFIG_MSM_RPM_STATS_LOG=y -# CONFIG_WCD_DSP_GLINK is not set -CONFIG_QCOM_SMCINVOKE=y -CONFIG_QCOM_EARLY_RANDOM=y -CONFIG_MEM_SHARE_QMI_SERVICE=y -CONFIG_QCOM_BIMC_BWMON=y -CONFIG_ARM_MEMLAT_MON=y -CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y -CONFIG_DEVFREQ_GOV_MEMLAT=y -CONFIG_QCOM_DEVFREQ_DEVBW=y -CONFIG_SPDM_SCM=y -CONFIG_DEVFREQ_SPDM=y -CONFIG_EXTCON=y -CONFIG_IIO=y -CONFIG_QCOM_RRADC=y -CONFIG_QCOM_TADC=y -CONFIG_PWM=y -CONFIG_PWM_QPNP=y -CONFIG_ARM_GIC_V3_ACL=y -CONFIG_ANDROID=y -CONFIG_ANDROID_BINDER_IPC=y -CONFIG_MSM_TZ_LOG=y -CONFIG_SENSORS_SSC=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT3_FS=y -CONFIG_EXT4_FS_SECURITY=y -CONFIG_EXT4_ENCRYPTION=y -CONFIG_EXT4_FS_ENCRYPTION=y -CONFIG_EXT4_FS_ICE_ENCRYPTION=y -CONFIG_FUSE_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_ECRYPT_FS=y -CONFIG_ECRYPT_FS_MESSAGING=y -# CONFIG_NETWORK_FILESYSTEMS is not set -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_PRINTK_TIME=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_DEBUG_INFO=y -CONFIG_PAGE_OWNER=y -CONFIG_PAGE_OWNER_ENABLE_DEFAULT=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_PAGEALLOC=y -CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT=y -CONFIG_SLUB_DEBUG_PANIC_ON=y -CONFIG_DEBUG_OBJECTS=y -CONFIG_DEBUG_OBJECTS_FREE=y -CONFIG_DEBUG_OBJECTS_TIMERS=y -CONFIG_DEBUG_OBJECTS_WORK=y -CONFIG_DEBUG_OBJECTS_RCU_HEAD=y -CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y -CONFIG_SLUB_DEBUG_ON=y -CONFIG_DEBUG_KMEMLEAK=y -CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=4000 -CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y -CONFIG_DEBUG_STACK_USAGE=y -CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_LOCKUP_DETECTOR=y -CONFIG_WQ_WATCHDOG=y -CONFIG_PANIC_TIMEOUT=5 -CONFIG_PANIC_ON_SCHED_BUG=y -CONFIG_PANIC_ON_RT_THROTTLING=y -CONFIG_SCHEDSTATS=y -CONFIG_SCHED_STACK_END_CHECK=y -CONFIG_TIMER_STATS=y -# CONFIG_DEBUG_PREEMPT is not set -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_ATOMIC_SLEEP=y -CONFIG_DEBUG_LIST=y -CONFIG_FAULT_INJECTION=y -CONFIG_FAIL_PAGE_ALLOC=y -CONFIG_UFS_FAULT_INJECTION=y -CONFIG_FAULT_INJECTION_DEBUG_FS=y -CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y -CONFIG_IPC_LOGGING=y -CONFIG_QCOM_RTB=y -CONFIG_QCOM_RTB_SEPARATE_CPUS=y -CONFIG_FUNCTION_TRACER=y -CONFIG_IRQSOFF_TRACER=y -CONFIG_PREEMPT_TRACER=y -CONFIG_BLK_DEV_IO_TRACE=y -CONFIG_CPU_FREQ_SWITCH_PROFILER=y -CONFIG_MEMTEST=y -CONFIG_PANIC_ON_DATA_CORRUPTION=y -CONFIG_PID_IN_CONTEXTIDR=y -CONFIG_DEBUG_SET_MODULE_RONX=y -CONFIG_CORESIGHT=y -CONFIG_CORESIGHT_EVENT=y -CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y -CONFIG_CORESIGHT_SOURCE_ETM4X=y -CONFIG_CORESIGHT_REMOTE_ETM=y -CONFIG_CORESIGHT_REMOTE_ETM_DEFAULT_ENABLE=0 -CONFIG_CORESIGHT_QCOM_REPLICATOR=y -CONFIG_CORESIGHT_STM=y -CONFIG_CORESIGHT_HWEVENT=y -CONFIG_CORESIGHT_CTI=y -CONFIG_CORESIGHT_TPDA=y -CONFIG_CORESIGHT_TPDM=y -CONFIG_CORESIGHT_QPDI=y -CONFIG_CORESIGHT_SOURCE_DUMMY=y -CONFIG_PFK=y -CONFIG_SECURITY=y -CONFIG_SECURITY_SELINUX=y -CONFIG_SECURITY_SMACK=y -CONFIG_CRYPTO_ECHAINIV=y -CONFIG_CRYPTO_XCBC=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_ANSI_CPRNG=y -CONFIG_CRYPTO_DEV_QCRYPTO=y -CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y -CONFIG_CRYPTO_DEV_QCEDEV=y -CONFIG_CRYPTO_DEV_OTA_CRYPTO=y -CONFIG_CRYPTO_DEV_QCOM_ICE=y -CONFIG_XZ_DEC=y diff --git a/arch/arm/configs/sdm660-perf_defconfig b/arch/arm/configs/sdm660-perf_defconfig new file mode 100644 index 000000000000..76cbdbac479a --- /dev/null +++ b/arch/arm/configs/sdm660-perf_defconfig @@ -0,0 +1,621 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_AUDIT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_RCU_EXPERT=y +CONFIG_RCU_FAST_NO_HZ=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_CPU_MAX_BUF_SHIFT=17 +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_SCHEDTUNE=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_SCHED_HMP=y +CONFIG_SCHED_HMP_CSTATE_AWARE=y +CONFIG_SCHED_CORE_CTL=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_PID_NS is not set +CONFIG_SCHED_AUTOGROUP=y +CONFIG_SCHED_TUNE=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_MEMBARRIER is not set +CONFIG_EMBEDDED=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_PROFILING=y +CONFIG_CC_STACKPROTECTOR_REGULAR=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SIG=y +CONFIG_MODULE_SIG_FORCE=y +CONFIG_MODULE_SIG_SHA512=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_ARCH_QCOM=y +CONFIG_ARCH_SDM660=y +CONFIG_ARCH_MSMTRITON=y +CONFIG_ARM_KERNMEM_PERMS=y +CONFIG_SMP=y +CONFIG_SCHED_MC=y +CONFIG_NR_CPUS=8 +CONFIG_ARM_PSCI=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_CLEANCACHE=y +CONFIG_CMA=y +CONFIG_CMA_DEBUGFS=y +CONFIG_ZSMALLOC=y +CONFIG_PROCESS_RECLAIM=y +CONFIG_SECCOMP=y +CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE=y +# CONFIG_CPU_FREQ_STAT is not set +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_BOOST=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_PM_AUTOSLEEP=y +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=0 +# CONFIG_PM_WAKELOCKS_GC is not set +CONFIG_PM_DEBUG=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +CONFIG_INET_IPCOMP=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG_DESTROY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SANE=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y +CONFIG_NETFILTER_XT_TARGET_HARDIDLETIMER=y +CONFIG_NETFILTER_XT_TARGET_LOG=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +CONFIG_NETFILTER_XT_TARGET_NOTRACK=y +CONFIG_NETFILTER_XT_TARGET_TEE=y +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +CONFIG_NETFILTER_XT_TARGET_SECMARK=y +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_DSCP=y +CONFIG_NETFILTER_XT_MATCH_ESP=y +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y +CONFIG_NETFILTER_XT_MATCH_HELPER=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +# CONFIG_NETFILTER_XT_MATCH_L2TP is not set +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_NETFILTER_XT_MATCH_POLICY=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_QTAGUID=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2=y +CONFIG_NETFILTER_XT_MATCH_SOCKET=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +CONFIG_NETFILTER_XT_MATCH_TIME=y +CONFIG_NETFILTER_XT_MATCH_U32=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_RPFILTER=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_SECURITY=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_MATCH_RPFILTER=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +CONFIG_BRIDGE_NF_EBTABLES=y +CONFIG_BRIDGE_EBT_BROUTE=y +CONFIG_L2TP=y +CONFIG_L2TP_DEBUGFS=y +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=y +CONFIG_L2TP_ETH=y +CONFIG_BRIDGE=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_PRIO=y +CONFIG_NET_SCH_MULTIQ=y +CONFIG_NET_SCH_INGRESS=y +CONFIG_NET_CLS_FW=y +CONFIG_NET_CLS_U32=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_FLOW=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=y +CONFIG_NET_EMATCH_NBYTE=y +CONFIG_NET_EMATCH_U32=y +CONFIG_NET_EMATCH_META=y +CONFIG_NET_EMATCH_TEXT=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_GACT=y +CONFIG_NET_ACT_MIRRED=y +CONFIG_NET_ACT_SKBEDIT=y +CONFIG_DNS_RESOLVER=y +CONFIG_RMNET_DATA=y +CONFIG_RMNET_DATA_FC=y +CONFIG_RMNET_DATA_DEBUG_PKT=y +CONFIG_SOCKEV_NLMCAST=y +CONFIG_BT=y +CONFIG_MSM_BT_POWER=y +CONFIG_BTFM_SLIM=y +CONFIG_BTFM_SLIM_WCN3990=y +CONFIG_CFG80211=y +CONFIG_CFG80211_INTERNAL_REGDB=y +# CONFIG_CFG80211_CRDA_SUPPORT is not set +CONFIG_RFKILL=y +CONFIG_NFC_NQ=y +CONFIG_IPC_ROUTER=y +CONFIG_IPC_ROUTER_SECURITY=y +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=40 +CONFIG_ZRAM=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_QSEECOM=y +CONFIG_HDCP_QSEECOM=y +CONFIG_UID_CPUTIME=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_UFSHCD=y +CONFIG_SCSI_UFSHCD_PLATFORM=y +CONFIG_SCSI_UFS_QCOM=y +CONFIG_SCSI_UFS_QCOM_ICE=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=y +CONFIG_DM_REQ_CRYPT=y +CONFIG_DM_UEVENT=y +CONFIG_DM_VERITY=y +CONFIG_NETDEVICES=y +CONFIG_BONDING=y +CONFIG_DUMMY=y +CONFIG_TUN=y +CONFIG_RNDIS_IPA=y +CONFIG_PPP=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=y +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOE=y +CONFIG_PPPOL2TP=y +CONFIG_PPPOLAC=y +CONFIG_PPPOPNS=y +CONFIG_PPP_ASYNC=y +CONFIG_PPP_SYNC_TTY=y +CONFIG_USB_USBNET=y +CONFIG_WCNSS_MEM_PRE_ALLOC=y +CONFIG_ATH_CARDS=y +CONFIG_CLD_LL_CORE=y +CONFIG_QPNP_POWER_ON=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_KEYRESET=y +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_JOYSTICK=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_v21=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y +CONFIG_SECURE_TOUCH=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_HBTP_INPUT=y +CONFIG_INPUT_KEYCHORD=y +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_GPIO=y +# CONFIG_SERIO_SERPORT is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVMEM is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_HS=y +CONFIG_SERIAL_MSM_SMD=y +CONFIG_DIAG_CHAR=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MSM_LEGACY=y +CONFIG_MSM_ADSPRPC=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MSM_V2=y +CONFIG_SLIMBUS_MSM_NGD=y +CONFIG_SOUNDWIRE=y +CONFIG_SPI=y +CONFIG_SPI_QUP=y +CONFIG_SPI_SPIDEV=y +CONFIG_SPMI=y +CONFIG_PINCTRL_SDM660=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_QPNP_PIN=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_QCOM=y +CONFIG_QCOM_DLOAD_MODE=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_APSS_CORE_EA=y +CONFIG_MSM_APM=y +CONFIG_QPNP_SMBCHARGER=y +CONFIG_SMB135X_CHARGER=y +CONFIG_SMB1351_USB_CHARGER=y +CONFIG_MSM_BCL_CTL=y +CONFIG_MSM_BCL_PERIPHERAL_CTL=y +CONFIG_BATTERY_BCL=y +CONFIG_QPNP_SMB2=y +CONFIG_SMB138X_CHARGER=y +CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_LIMITS_MONITOR=y +CONFIG_LIMITS_LITE_HW=y +CONFIG_THERMAL_MONITOR=y +CONFIG_THERMAL_TSENS8974=y +CONFIG_THERMAL_QPNP=y +CONFIG_THERMAL_QPNP_ADC_TM=y +CONFIG_QCOM_THERMAL_LIMITS_DCVS=y +CONFIG_MFD_SPMI_PMIC=y +CONFIG_MFD_I2C_PMIC=y +CONFIG_WCD9335_CODEC=y +CONFIG_WCD934X_CODEC=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_MSM_GFX_LDO=y +CONFIG_REGULATOR_RPM_SMD=y +CONFIG_REGULATOR_QPNP=y +CONFIG_REGULATOR_QPNP_LABIBB=y +CONFIG_REGULATOR_SPM=y +CONFIG_REGULATOR_CPR3_HMSS=y +CONFIG_REGULATOR_CPR3_MMSS=y +CONFIG_REGULATOR_CPRH_KBSS=y +CONFIG_REGULATOR_CPR4_MMSS_LDO=y +CONFIG_REGULATOR_MEM_ACC=y +CONFIG_REGULATOR_PROXY_CONSUMER=y +CONFIG_REGULATOR_STUB=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_VIDEO_ADV_DEBUG=y +CONFIG_VIDEO_FIXED_MINOR_RANGES=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_MSM_CAMERA=y +CONFIG_MSM_CAMERA_DEBUG=y +CONFIG_MSM_SDE_ROTATOR=y +CONFIG_QCOM_KGSL=y +CONFIG_FB=y +CONFIG_FB_VIRTUAL=y +CONFIG_FB_MSM=y +CONFIG_FB_MSM_MDSS=y +CONFIG_FB_MSM_MDSS_WRITEBACK=y +CONFIG_FB_MSM_MDSS_HDMI_PANEL=y +CONFIG_FB_MSM_MDSS_DP_PANEL=y +CONFIG_FB_MSM_MDSS_XLOG_DEBUG=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_USB_AUDIO=y +CONFIG_SND_USB_AUDIO_QMI=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_660=y +CONFIG_UHID=y +CONFIG_HID_APPLE=y +CONFIG_HID_ELECOM=y +CONFIG_HID_MAGICMOUSE=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MULTITOUCH=y +CONFIG_HID_PLANTRONICS=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3=y +CONFIG_USB_ISP1760=y +CONFIG_USB_ISP1760_HOST_ROLE=y +CONFIG_USB_PD_POLICY=y +CONFIG_QPNP_USB_PDPHY=y +CONFIG_USB_EHSET_TEST_FIXTURE=y +CONFIG_USB_OTG_WAKELOCK=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MSM_SSPHY_QMP=y +CONFIG_MSM_QUSB_PHY=y +CONFIG_DUAL_ROLE_USB_INTF=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VBUS_DRAW=500 +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_QCRNDIS=y +CONFIG_USB_CONFIGFS_RMNET_BAM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_MTP=y +CONFIG_USB_CONFIGFS_F_PTP=y +CONFIG_USB_CONFIGFS_F_ACC=y +CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y +CONFIG_USB_CONFIGFS_UEVENT=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_DIAG=y +CONFIG_USB_CONFIGFS_F_GSI=y +CONFIG_USB_CONFIGFS_F_CDEV=y +CONFIG_USB_CONFIGFS_F_QDSS=y +CONFIG_MMC=y +CONFIG_MMC_PERF_PROFILING=y +CONFIG_MMC_PARANOID_SD_INIT=y +CONFIG_MMC_CLKGATE=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_TEST=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_QPNP=y +CONFIG_LEDS_QPNP_FLASH_V2=y +CONFIG_LEDS_QPNP_WLED=y +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_SWITCH=y +CONFIG_EDAC=y +CONFIG_EDAC_MM_EDAC=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_QPNP=y +CONFIG_DMADEVICES=y +CONFIG_QCOM_SPS_DMA=y +CONFIG_UIO=y +CONFIG_UIO_MSM_SHAREDMEM=y +CONFIG_STAGING=y +CONFIG_ASHMEM=y +CONFIG_ANDROID_TIMED_GPIO=y +CONFIG_ANDROID_LOW_MEMORY_KILLER=y +CONFIG_ION=y +CONFIG_ION_MSM=y +CONFIG_QPNP_REVID=y +CONFIG_QPNP_COINCELL=y +CONFIG_SPS=y +CONFIG_SPS_SUPPORT_NDP_BAM=y +CONFIG_IPA=y +CONFIG_RMNET_IPA=y +CONFIG_GSI=y +CONFIG_IPA3=y +CONFIG_RMNET_IPA3=y +CONFIG_GPIO_USB_DETECT=y +CONFIG_SEEMP_CORE=y +CONFIG_USB_BAM=y +CONFIG_QCOM_CLK_SMD_RPM=y +CONFIG_MSM_GCC_660=y +CONFIG_QCOM_MDSS_PLL=y +CONFIG_REMOTE_SPINLOCK_MSM=y +CONFIG_ARM_SMMU=y +CONFIG_QCOM_COMMON_LOG=y +CONFIG_MSM_SMEM=y +CONFIG_QPNP_HAPTIC=y +CONFIG_MSM_SMD=y +CONFIG_MSM_SMD_DEBUG=y +CONFIG_MSM_GLINK=y +CONFIG_MSM_GLINK_LOOPBACK_SERVER=y +CONFIG_MSM_GLINK_SMD_XPRT=y +CONFIG_MSM_GLINK_SMEM_NATIVE_XPRT=y +CONFIG_MSM_SPCOM=y +CONFIG_MSM_SMEM_LOGGING=y +CONFIG_MSM_SMP2P=y +CONFIG_MSM_SMP2P_TEST=y +CONFIG_MSM_QMI_INTERFACE=y +CONFIG_QCOM_BUS_SCALING=y +CONFIG_MSM_SERVICE_LOCATOR=y +CONFIG_QCOM_DCC=y +CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y +CONFIG_MSM_SYSMON_GLINK_COMM=y +CONFIG_MSM_IPC_ROUTER_GLINK_XPRT=y +CONFIG_MSM_GLINK_PKT=y +CONFIG_MSM_SPM=y +CONFIG_QCOM_SCM=y +CONFIG_QCOM_WATCHDOG_V2=y +CONFIG_QCOM_IRQ_HELPER=y +CONFIG_QCOM_MEMORY_DUMP_V2=y +CONFIG_ICNSS=y +CONFIG_MSM_GLADIATOR_ERP_V2=y +CONFIG_PANIC_ON_GLADIATOR_ERROR_V2=y +CONFIG_MSM_GLADIATOR_HANG_DETECT=y +CONFIG_MSM_RUN_QUEUE_STATS=y +CONFIG_MSM_BOOT_STATS=y +CONFIG_QCOM_CPUSS_DUMP=y +CONFIG_MSM_ADSP_LOADER=y +CONFIG_MSM_PERFORMANCE=y +CONFIG_MSM_SUBSYSTEM_RESTART=y +CONFIG_MSM_PIL=y +CONFIG_MSM_PIL_SSR_GENERIC=y +CONFIG_MSM_PIL_MSS_QDSP6V5=y +CONFIG_TRACER_PKT=y +CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y +CONFIG_MSM_MPM_OF=y +CONFIG_MSM_EVENT_TIMER=y +CONFIG_MSM_AVTIMER=y +CONFIG_QCOM_REMOTEQDSS=y +CONFIG_MSM_SERVICE_NOTIFIER=y +CONFIG_MSM_RPM_RBCPR_STATS_V2_LOG=y +CONFIG_MSM_RPM_LOG=y +CONFIG_MSM_RPM_STATS_LOG=y +# CONFIG_WCD_DSP_GLINK is not set +CONFIG_QCOM_SMCINVOKE=y +CONFIG_MEM_SHARE_QMI_SERVICE=y +CONFIG_QCOM_BIMC_BWMON=y +CONFIG_ARM_MEMLAT_MON=y +CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y +CONFIG_DEVFREQ_GOV_MEMLAT=y +CONFIG_QCOM_DEVFREQ_DEVBW=y +CONFIG_DEVFREQ_SPDM=y +CONFIG_PM_DEVFREQ_EVENT=y +CONFIG_EXTCON=y +CONFIG_IIO=y +CONFIG_QCOM_RRADC=y +CONFIG_QCOM_TADC=y +CONFIG_PWM=y +CONFIG_PWM_QPNP=y +CONFIG_ARM_GIC_V3_ACL=y +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_MSM_TZ_LOG=y +CONFIG_SENSORS_SSC=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_EXT4_ENCRYPTION=y +CONFIG_EXT4_FS_ENCRYPTION=y +CONFIG_EXT4_FS_ICE_ENCRYPTION=y +CONFIG_EXT4_DEBUG=y +CONFIG_FUSE_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_ECRYPT_FS=y +CONFIG_ECRYPT_FS_MESSAGING=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_INFO=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_PAGE_EXTENSION=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_WQ_WATCHDOG=y +CONFIG_PANIC_TIMEOUT=5 +# CONFIG_SCHED_DEBUG is not set +CONFIG_PANIC_ON_SCHED_BUG=y +CONFIG_PANIC_ON_RT_THROTTLING=y +CONFIG_SCHEDSTATS=y +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_IPC_LOGGING=y +CONFIG_FUNCTION_TRACER=y +CONFIG_TRACER_SNAPSHOT=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_CPU_FREQ_SWITCH_PROFILER=y +CONFIG_PID_IN_CONTEXTIDR=y +CONFIG_DEBUG_SET_MODULE_RONX=y +CONFIG_CORESIGHT=y +CONFIG_CORESIGHT_EVENT=y +CONFIG_CORESIGHT_QCOM_REPLICATOR=y +CONFIG_CORESIGHT_STM=y +CONFIG_CORESIGHT_HWEVENT=y +CONFIG_CORESIGHT_CTI=y +CONFIG_CORESIGHT_TPDA=y +CONFIG_CORESIGHT_TPDM=y +CONFIG_CORESIGHT_QPDI=y +CONFIG_CORESIGHT_SOURCE_DUMMY=y +CONFIG_PFK=y +CONFIG_SECURITY=y +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SMACK=y +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_XCBC=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_DEV_QCRYPTO=y +CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y +CONFIG_CRYPTO_DEV_QCEDEV=y +CONFIG_CRYPTO_DEV_OTA_CRYPTO=y +CONFIG_CRYPTO_DEV_QCOM_ICE=y +CONFIG_XZ_DEC=y diff --git a/arch/arm/configs/sdm660_defconfig b/arch/arm/configs/sdm660_defconfig new file mode 100644 index 000000000000..40614f2b872b --- /dev/null +++ b/arch/arm/configs/sdm660_defconfig @@ -0,0 +1,665 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_AUDIT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_RCU_EXPERT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_CPU_MAX_BUF_SHIFT=17 +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_SCHEDTUNE=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +CONFIG_CGROUP_SCHED=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_SCHED_HMP=y +CONFIG_SCHED_HMP_CSTATE_AWARE=y +CONFIG_SCHED_CORE_CTL=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_PID_NS is not set +CONFIG_SCHED_TUNE=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_MEMBARRIER is not set +CONFIG_EMBEDDED=y +# CONFIG_COMPAT_BRK is not set +CONFIG_PROFILING=y +CONFIG_CC_STACKPROTECTOR_REGULAR=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SIG=y +CONFIG_MODULE_SIG_FORCE=y +CONFIG_MODULE_SIG_SHA512=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_ARCH_QCOM=y +CONFIG_ARCH_SDM660=y +CONFIG_ARCH_MSMTRITON=y +CONFIG_ARM_KERNMEM_PERMS=y +CONFIG_SMP=y +CONFIG_SCHED_MC=y +CONFIG_NR_CPUS=8 +CONFIG_ARM_PSCI=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_CLEANCACHE=y +CONFIG_CMA=y +CONFIG_CMA_DEBUGFS=y +CONFIG_ZSMALLOC=y +CONFIG_PROCESS_RECLAIM=y +CONFIG_SECCOMP=y +CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE=y +# CONFIG_CPU_FREQ_STAT is not set +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_PM_AUTOSLEEP=y +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=0 +# CONFIG_PM_WAKELOCKS_GC is not set +CONFIG_PM_DEBUG=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +CONFIG_INET_IPCOMP=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG_DESTROY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SANE=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y +CONFIG_NETFILTER_XT_TARGET_HARDIDLETIMER=y +CONFIG_NETFILTER_XT_TARGET_LOG=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +CONFIG_NETFILTER_XT_TARGET_NOTRACK=y +CONFIG_NETFILTER_XT_TARGET_TEE=y +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +CONFIG_NETFILTER_XT_TARGET_SECMARK=y +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_DSCP=y +CONFIG_NETFILTER_XT_MATCH_ESP=y +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y +CONFIG_NETFILTER_XT_MATCH_HELPER=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +# CONFIG_NETFILTER_XT_MATCH_L2TP is not set +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_NETFILTER_XT_MATCH_POLICY=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_QTAGUID=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2=y +CONFIG_NETFILTER_XT_MATCH_SOCKET=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +CONFIG_NETFILTER_XT_MATCH_TIME=y +CONFIG_NETFILTER_XT_MATCH_U32=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_RPFILTER=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_SECURITY=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_MATCH_RPFILTER=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +CONFIG_BRIDGE_NF_EBTABLES=y +CONFIG_BRIDGE_EBT_BROUTE=y +CONFIG_L2TP=y +CONFIG_L2TP_DEBUGFS=y +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=y +CONFIG_L2TP_ETH=y +CONFIG_BRIDGE=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_PRIO=y +CONFIG_NET_SCH_MULTIQ=y +CONFIG_NET_SCH_INGRESS=y +CONFIG_NET_CLS_FW=y +CONFIG_NET_CLS_U32=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_FLOW=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=y +CONFIG_NET_EMATCH_NBYTE=y +CONFIG_NET_EMATCH_U32=y +CONFIG_NET_EMATCH_META=y +CONFIG_NET_EMATCH_TEXT=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_GACT=y +CONFIG_NET_ACT_MIRRED=y +CONFIG_NET_ACT_SKBEDIT=y +CONFIG_DNS_RESOLVER=y +CONFIG_RMNET_DATA=y +CONFIG_RMNET_DATA_FC=y +CONFIG_RMNET_DATA_DEBUG_PKT=y +CONFIG_SOCKEV_NLMCAST=y +CONFIG_BT=y +CONFIG_MSM_BT_POWER=y +CONFIG_BTFM_SLIM=y +CONFIG_BTFM_SLIM_WCN3990=y +CONFIG_CFG80211=y +CONFIG_CFG80211_INTERNAL_REGDB=y +# CONFIG_CFG80211_CRDA_SUPPORT is not set +CONFIG_RFKILL=y +CONFIG_NFC_NQ=y +CONFIG_IPC_ROUTER=y +CONFIG_IPC_ROUTER_SECURITY=y +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=40 +CONFIG_ZRAM=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_QSEECOM=y +CONFIG_HDCP_QSEECOM=y +CONFIG_UID_CPUTIME=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_UFSHCD=y +CONFIG_SCSI_UFSHCD_PLATFORM=y +CONFIG_SCSI_UFS_QCOM=y +CONFIG_SCSI_UFS_QCOM_ICE=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=y +CONFIG_DM_REQ_CRYPT=y +CONFIG_DM_UEVENT=y +CONFIG_DM_VERITY=y +CONFIG_NETDEVICES=y +CONFIG_BONDING=y +CONFIG_DUMMY=y +CONFIG_TUN=y +CONFIG_RNDIS_IPA=y +CONFIG_PPP=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=y +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOE=y +CONFIG_PPPOL2TP=y +CONFIG_PPPOLAC=y +CONFIG_PPPOPNS=y +CONFIG_PPP_ASYNC=y +CONFIG_PPP_SYNC_TTY=y +CONFIG_USB_USBNET=y +CONFIG_WCNSS_MEM_PRE_ALLOC=y +CONFIG_ATH_CARDS=y +CONFIG_CLD_LL_CORE=y +CONFIG_QPNP_POWER_ON=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_KEYRESET=y +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_JOYSTICK=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_v21=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y +CONFIG_SECURE_TOUCH=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_HBTP_INPUT=y +CONFIG_INPUT_KEYCHORD=y +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_GPIO=y +# CONFIG_SERIO_SERPORT is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y +CONFIG_SERIAL_MSM_HS=y +CONFIG_SERIAL_MSM_SMD=y +CONFIG_DIAG_CHAR=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MSM_LEGACY=y +CONFIG_MSM_ADSPRPC=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MSM_V2=y +CONFIG_SLIMBUS_MSM_NGD=y +CONFIG_SOUNDWIRE=y +CONFIG_SPI=y +CONFIG_SPI_QUP=y +CONFIG_SPI_SPIDEV=y +CONFIG_SPMI=y +CONFIG_PINCTRL_SDM660=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_QPNP_PIN=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_QCOM=y +CONFIG_QCOM_DLOAD_MODE=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_APSS_CORE_EA=y +CONFIG_MSM_APM=y +CONFIG_QPNP_SMBCHARGER=y +CONFIG_SMB135X_CHARGER=y +CONFIG_SMB1351_USB_CHARGER=y +CONFIG_MSM_BCL_CTL=y +CONFIG_MSM_BCL_PERIPHERAL_CTL=y +CONFIG_BATTERY_BCL=y +CONFIG_QPNP_SMB2=y +CONFIG_SMB138X_CHARGER=y +CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_LIMITS_MONITOR=y +CONFIG_LIMITS_LITE_HW=y +CONFIG_THERMAL_MONITOR=y +CONFIG_THERMAL_TSENS8974=y +CONFIG_THERMAL_QPNP=y +CONFIG_THERMAL_QPNP_ADC_TM=y +CONFIG_QCOM_THERMAL_LIMITS_DCVS=y +CONFIG_MFD_SPMI_PMIC=y +CONFIG_MFD_I2C_PMIC=y +CONFIG_WCD9335_CODEC=y +CONFIG_WCD934X_CODEC=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_MSM_GFX_LDO=y +CONFIG_REGULATOR_RPM_SMD=y +CONFIG_REGULATOR_QPNP=y +CONFIG_REGULATOR_QPNP_LABIBB=y +CONFIG_REGULATOR_QPNP_LCDB=y +CONFIG_REGULATOR_SPM=y +CONFIG_REGULATOR_CPR3_HMSS=y +CONFIG_REGULATOR_CPR3_MMSS=y +CONFIG_REGULATOR_CPRH_KBSS=y +CONFIG_REGULATOR_CPR4_MMSS_LDO=y +CONFIG_REGULATOR_MEM_ACC=y +CONFIG_REGULATOR_PROXY_CONSUMER=y +CONFIG_REGULATOR_STUB=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_VIDEO_ADV_DEBUG=y +CONFIG_VIDEO_FIXED_MINOR_RANGES=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_MSM_CAMERA=y +CONFIG_MSM_CAMERA_DEBUG=y +CONFIG_MSM_VIDC_V4L2=m +CONFIG_MSM_VIDC_GOVERNORS=m +CONFIG_MSM_SDE_ROTATOR=y +CONFIG_MSM_SDE_ROTATOR_EVTLOG_DEBUG=y +CONFIG_QCOM_KGSL=y +CONFIG_FB=y +CONFIG_FB_VIRTUAL=y +CONFIG_FB_MSM=y +CONFIG_FB_MSM_MDSS=y +CONFIG_FB_MSM_MDSS_WRITEBACK=y +CONFIG_FB_MSM_MDSS_HDMI_PANEL=y +CONFIG_FB_MSM_MDSS_DP_PANEL=y +CONFIG_FB_MSM_MDSS_XLOG_DEBUG=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_USB_AUDIO=y +CONFIG_SND_USB_AUDIO_QMI=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_660=y +CONFIG_UHID=y +CONFIG_HID_APPLE=y +CONFIG_HID_ELECOM=y +CONFIG_HID_MAGICMOUSE=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MULTITOUCH=y +CONFIG_HID_PLANTRONICS=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3=y +CONFIG_USB_ISP1760=y +CONFIG_USB_ISP1760_HOST_ROLE=y +CONFIG_USB_PD_POLICY=y +CONFIG_QPNP_USB_PDPHY=y +CONFIG_USB_EHSET_TEST_FIXTURE=y +CONFIG_USB_OTG_WAKELOCK=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MSM_SSPHY_QMP=y +CONFIG_MSM_QUSB_PHY=y +CONFIG_DUAL_ROLE_USB_INTF=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VBUS_DRAW=500 +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_QCRNDIS=y +CONFIG_USB_CONFIGFS_RMNET_BAM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_MTP=y +CONFIG_USB_CONFIGFS_F_PTP=y +CONFIG_USB_CONFIGFS_F_ACC=y +CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y +CONFIG_USB_CONFIGFS_UEVENT=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_DIAG=y +CONFIG_USB_CONFIGFS_F_GSI=y +CONFIG_USB_CONFIGFS_F_CDEV=y +CONFIG_USB_CONFIGFS_F_QDSS=y +CONFIG_MMC=y +CONFIG_MMC_PERF_PROFILING=y +CONFIG_MMC_PARANOID_SD_INIT=y +CONFIG_MMC_CLKGATE=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_TEST=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_QPNP=y +CONFIG_LEDS_QPNP_FLASH_V2=y +CONFIG_LEDS_QPNP_WLED=y +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_SWITCH=y +CONFIG_EDAC=y +CONFIG_EDAC_MM_EDAC=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_QPNP=y +CONFIG_DMADEVICES=y +CONFIG_QCOM_SPS_DMA=y +CONFIG_UIO=y +CONFIG_UIO_MSM_SHAREDMEM=y +CONFIG_STAGING=y +CONFIG_ASHMEM=y +CONFIG_ANDROID_TIMED_GPIO=y +CONFIG_ANDROID_LOW_MEMORY_KILLER=y +CONFIG_ION=y +CONFIG_ION_MSM=y +CONFIG_QPNP_REVID=y +CONFIG_QPNP_COINCELL=y +CONFIG_SPS=y +CONFIG_SPS_SUPPORT_NDP_BAM=y +CONFIG_IPA=y +CONFIG_RMNET_IPA=y +CONFIG_GSI=y +CONFIG_IPA3=y +CONFIG_RMNET_IPA3=y +CONFIG_GPIO_USB_DETECT=y +CONFIG_SEEMP_CORE=y +CONFIG_USB_BAM=y +CONFIG_QCOM_CLK_SMD_RPM=y +CONFIG_MSM_GPUCC_660=y +CONFIG_MSM_MMCC_660=y +CONFIG_CLOCK_CPU_OSM=y +CONFIG_QCOM_MDSS_PLL=y +CONFIG_REMOTE_SPINLOCK_MSM=y +CONFIG_ARM_SMMU=y +CONFIG_IOMMU_DEBUG=y +CONFIG_IOMMU_DEBUG_TRACKING=y +CONFIG_IOMMU_TESTS=y +CONFIG_QCOM_COMMON_LOG=y +CONFIG_MSM_SMEM=y +CONFIG_QPNP_HAPTIC=y +CONFIG_MSM_SMD=y +CONFIG_MSM_SMD_DEBUG=y +CONFIG_MSM_GLINK=y +CONFIG_MSM_GLINK_LOOPBACK_SERVER=y +CONFIG_MSM_GLINK_SMD_XPRT=y +CONFIG_MSM_GLINK_SMEM_NATIVE_XPRT=y +CONFIG_MSM_SPCOM=y +CONFIG_MSM_SPSS_UTILS=y +CONFIG_MSM_SMEM_LOGGING=y +CONFIG_MSM_SMP2P=y +CONFIG_MSM_SMP2P_TEST=y +CONFIG_MSM_QMI_INTERFACE=y +CONFIG_QCOM_BUS_SCALING=y +CONFIG_MSM_SERVICE_LOCATOR=y +CONFIG_QCOM_DCC=y +CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y +CONFIG_MSM_SYSMON_GLINK_COMM=y +CONFIG_MSM_IPC_ROUTER_GLINK_XPRT=y +CONFIG_MSM_GLINK_PKT=y +CONFIG_MSM_SPM=y +CONFIG_QCOM_SCM=y +CONFIG_QCOM_WATCHDOG_V2=y +CONFIG_QCOM_IRQ_HELPER=y +CONFIG_QCOM_MEMORY_DUMP_V2=y +CONFIG_ICNSS=y +CONFIG_ICNSS_DEBUG=y +CONFIG_MSM_GLADIATOR_ERP_V2=y +CONFIG_PANIC_ON_GLADIATOR_ERROR_V2=y +CONFIG_MSM_GLADIATOR_HANG_DETECT=y +CONFIG_MSM_CORE_HANG_DETECT=y +CONFIG_MSM_RUN_QUEUE_STATS=y +# CONFIG_MSM_JTAGV8 is not set +CONFIG_MSM_BOOT_STATS=y +CONFIG_QCOM_CPUSS_DUMP=y +CONFIG_MSM_ADSP_LOADER=y +CONFIG_MSM_PERFORMANCE=y +CONFIG_MSM_SUBSYSTEM_RESTART=y +CONFIG_MSM_PIL=y +CONFIG_MSM_PIL_SSR_GENERIC=y +CONFIG_MSM_PIL_MSS_QDSP6V5=y +CONFIG_TRACER_PKT=y +CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y +CONFIG_MSM_MPM_OF=y +CONFIG_MSM_EVENT_TIMER=y +CONFIG_MSM_AVTIMER=y +CONFIG_QCOM_REMOTEQDSS=y +CONFIG_MSM_SERVICE_NOTIFIER=y +CONFIG_MSM_RPM_RBCPR_STATS_V2_LOG=y +CONFIG_MSM_RPM_LOG=y +CONFIG_MSM_RPM_STATS_LOG=y +# CONFIG_WCD_DSP_GLINK is not set +CONFIG_QCOM_SMCINVOKE=y +CONFIG_QCOM_EARLY_RANDOM=y +CONFIG_MEM_SHARE_QMI_SERVICE=y +CONFIG_QCOM_BIMC_BWMON=y +CONFIG_ARM_MEMLAT_MON=y +CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y +CONFIG_DEVFREQ_GOV_MEMLAT=y +CONFIG_QCOM_DEVFREQ_DEVBW=y +CONFIG_SPDM_SCM=y +CONFIG_DEVFREQ_SPDM=y +CONFIG_EXTCON=y +CONFIG_IIO=y +CONFIG_QCOM_RRADC=y +CONFIG_QCOM_TADC=y +CONFIG_PWM=y +CONFIG_PWM_QPNP=y +CONFIG_ARM_GIC_V3_ACL=y +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_MSM_TZ_LOG=y +CONFIG_SENSORS_SSC=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_EXT4_ENCRYPTION=y +CONFIG_EXT4_FS_ENCRYPTION=y +CONFIG_EXT4_FS_ICE_ENCRYPTION=y +CONFIG_FUSE_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_ECRYPT_FS=y +CONFIG_ECRYPT_FS_MESSAGING=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DEBUG_INFO=y +CONFIG_PAGE_OWNER=y +CONFIG_PAGE_OWNER_ENABLE_DEFAULT=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_PAGEALLOC=y +CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT=y +CONFIG_SLUB_DEBUG_PANIC_ON=y +CONFIG_DEBUG_OBJECTS=y +CONFIG_DEBUG_OBJECTS_FREE=y +CONFIG_DEBUG_OBJECTS_TIMERS=y +CONFIG_DEBUG_OBJECTS_WORK=y +CONFIG_DEBUG_OBJECTS_RCU_HEAD=y +CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y +CONFIG_SLUB_DEBUG_ON=y +CONFIG_DEBUG_KMEMLEAK=y +CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=4000 +CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y +CONFIG_DEBUG_STACK_USAGE=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_WQ_WATCHDOG=y +CONFIG_PANIC_TIMEOUT=5 +CONFIG_PANIC_ON_SCHED_BUG=y +CONFIG_PANIC_ON_RT_THROTTLING=y +CONFIG_SCHEDSTATS=y +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +CONFIG_DEBUG_ATOMIC_SLEEP=y +CONFIG_DEBUG_LIST=y +CONFIG_FAULT_INJECTION=y +CONFIG_FAIL_PAGE_ALLOC=y +CONFIG_UFS_FAULT_INJECTION=y +CONFIG_FAULT_INJECTION_DEBUG_FS=y +CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y +CONFIG_IPC_LOGGING=y +CONFIG_QCOM_RTB=y +CONFIG_QCOM_RTB_SEPARATE_CPUS=y +CONFIG_FUNCTION_TRACER=y +CONFIG_IRQSOFF_TRACER=y +CONFIG_PREEMPT_TRACER=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_CPU_FREQ_SWITCH_PROFILER=y +CONFIG_MEMTEST=y +CONFIG_PANIC_ON_DATA_CORRUPTION=y +CONFIG_PID_IN_CONTEXTIDR=y +CONFIG_DEBUG_SET_MODULE_RONX=y +CONFIG_CORESIGHT=y +CONFIG_CORESIGHT_EVENT=y +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y +CONFIG_CORESIGHT_SOURCE_ETM4X=y +CONFIG_CORESIGHT_REMOTE_ETM=y +CONFIG_CORESIGHT_REMOTE_ETM_DEFAULT_ENABLE=0 +CONFIG_CORESIGHT_QCOM_REPLICATOR=y +CONFIG_CORESIGHT_STM=y +CONFIG_CORESIGHT_HWEVENT=y +CONFIG_CORESIGHT_CTI=y +CONFIG_CORESIGHT_TPDA=y +CONFIG_CORESIGHT_TPDM=y +CONFIG_CORESIGHT_QPDI=y +CONFIG_CORESIGHT_SOURCE_DUMMY=y +CONFIG_PFK=y +CONFIG_SECURITY=y +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SMACK=y +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_XCBC=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_DEV_QCRYPTO=y +CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y +CONFIG_CRYPTO_DEV_QCEDEV=y +CONFIG_CRYPTO_DEV_OTA_CRYPTO=y +CONFIG_CRYPTO_DEV_QCOM_ICE=y +CONFIG_XZ_DEC=y diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig index a4fba1af7744..1910acb1cce9 100644 --- a/arch/arm/mach-qcom/Kconfig +++ b/arch/arm/mach-qcom/Kconfig @@ -1,8 +1,8 @@ if ARCH_QCOM menu "QCOM SoC Type" -config ARCH_MSMFALCON - bool "Enable Support for MSMFALCON" +config ARCH_SDM660 + bool "Enable Support for SDM660" select CLKDEV_LOOKUP select HAVE_CLK select HAVE_CLK_PREPARE @@ -36,7 +36,7 @@ config ARCH_MSMFALCON select GENERIC_IRQ_MIGRATION select MSM_JTAGV8 if CORESIGHT_ETMV4 help - This enables support for the MSMFALCON chipset. If you do not + This enables support for the SDM660 chipset. If you do not wish to build a kernel that runs on this chipset, say 'N' here. config ARCH_MSMTRITON diff --git a/arch/arm/mach-qcom/Makefile b/arch/arm/mach-qcom/Makefile index c5e30fff2b1e..c79ab416701c 100644 --- a/arch/arm/mach-qcom/Makefile +++ b/arch/arm/mach-qcom/Makefile @@ -1,4 +1,4 @@ obj-y := board.o obj-$(CONFIG_USE_OF) += board-dt.o -obj-$(CONFIG_ARCH_MSMFALCON) += board-falcon.o +obj-$(CONFIG_ARCH_SDM660) += board-660.o obj-$(CONFIG_SMP) += platsmp.o diff --git a/arch/arm/mach-qcom/board-660.c b/arch/arm/mach-qcom/board-660.c new file mode 100644 index 000000000000..f1bf7e08bbac --- /dev/null +++ b/arch/arm/mach-qcom/board-660.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "board-dt.h" + +static const char *sdm660_dt_match[] __initconst = { + "qcom,sdm660", + "qcom,sda660", + NULL +}; + +static void __init sdm660_init(void) +{ + board_dt_populate(NULL); +} + +DT_MACHINE_START(SDM660_DT, + "Qualcomm Technologies, Inc. SDM 660 (Flattened Device Tree)") + .init_machine = sdm660_init, + .dt_compat = sdm660_dt_match, +MACHINE_END + +static const char *msmtriton_dt_match[] __initconst = { + "qcom,msmtriton", + "qcom,apqtriton", + NULL +}; + +static void __init msmtriton_init(void) +{ + board_dt_populate(NULL); +} + +DT_MACHINE_START(MSMTRITON_DT, + "Qualcomm Technologies, Inc. MSM TRITON (Flattened Device Tree)") + .init_machine = msmtriton_init, + .dt_compat = msmtriton_dt_match, +MACHINE_END diff --git a/arch/arm/mach-qcom/board-falcon.c b/arch/arm/mach-qcom/board-falcon.c deleted file mode 100644 index aec16886308d..000000000000 --- a/arch/arm/mach-qcom/board-falcon.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "board-dt.h" - -static const char *msmfalcon_dt_match[] __initconst = { - "qcom,msmfalcon", - "qcom,apqfalcon", - NULL -}; - -static void __init msmfalcon_init(void) -{ - board_dt_populate(NULL); -} - -DT_MACHINE_START(MSMFALCON_DT, - "Qualcomm Technologies, Inc. MSM FALCON (Flattened Device Tree)") - .init_machine = msmfalcon_init, - .dt_compat = msmfalcon_dt_match, -MACHINE_END - -static const char *msmtriton_dt_match[] __initconst = { - "qcom,msmtriton", - "qcom,apqtriton", - NULL -}; - -static void __init msmtriton_init(void) -{ - board_dt_populate(NULL); -} - -DT_MACHINE_START(MSMTRITON_DT, - "Qualcomm Technologies, Inc. MSM TRITON (Flattened Device Tree)") - .init_machine = msmtriton_init, - .dt_compat = msmtriton_dt_match, -MACHINE_END diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 56b7f310ddbc..5d22639491c0 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -86,14 +86,14 @@ config ARCH_MSMHAMSTER If you do not wish to build a kernel that runs on this chipset,say 'N' here. -config ARCH_MSMFALCON - bool "Enable Support for Qualcomm Technologies Inc MSMFALCON" +config ARCH_SDM660 + bool "Enable Support for Qualcomm Technologies Inc SDM660" depends on ARCH_QCOM select COMMON_CLK select COMMON_CLK_QCOM select QCOM_GDSC help - This enables support for the MSMFALCON chipset. + This enables support for the SDM660 chipset. If you do not wish to build a kernel that runs on this chipset,say 'N' here. diff --git a/arch/arm64/configs/msmcortex-perf_defconfig b/arch/arm64/configs/msmcortex-perf_defconfig index 97a082dd4fcd..71d067b27ddd 100644 --- a/arch/arm64/configs/msmcortex-perf_defconfig +++ b/arch/arm64/configs/msmcortex-perf_defconfig @@ -308,7 +308,7 @@ CONFIG_SPI_QUP=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y CONFIG_PINCTRL_MSM8998=y -CONFIG_PINCTRL_MSMFALCON=y +CONFIG_PINCTRL_SDM660=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_QPNP_PIN=y diff --git a/arch/arm64/configs/msmcortex_defconfig b/arch/arm64/configs/msmcortex_defconfig index 965a13caaeb5..02b9e08955f6 100644 --- a/arch/arm64/configs/msmcortex_defconfig +++ b/arch/arm64/configs/msmcortex_defconfig @@ -311,7 +311,7 @@ CONFIG_SPI_QUP=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y CONFIG_PINCTRL_MSM8998=y -CONFIG_PINCTRL_MSMFALCON=y +CONFIG_PINCTRL_SDM660=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_QPNP_PIN=y diff --git a/arch/arm64/configs/msmfalcon-perf_defconfig b/arch/arm64/configs/msmfalcon-perf_defconfig deleted file mode 100644 index b84168e18478..000000000000 --- a/arch/arm64/configs/msmfalcon-perf_defconfig +++ /dev/null @@ -1,645 +0,0 @@ -CONFIG_LOCALVERSION="-perf" -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_AUDIT=y -# CONFIG_AUDITSYSCALL is not set -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_RCU_EXPERT=y -CONFIG_RCU_FAST_NO_HZ=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_CPU_MAX_BUF_SHIFT=17 -CONFIG_CGROUP_FREEZER=y -CONFIG_CPUSETS=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_CGROUP_SCHEDTUNE=y -CONFIG_MEMCG=y -CONFIG_MEMCG_SWAP=y -CONFIG_RT_GROUP_SCHED=y -CONFIG_SCHED_HMP=y -CONFIG_SCHED_HMP_CSTATE_AWARE=y -CONFIG_SCHED_CORE_CTL=y -CONFIG_NAMESPACES=y -# CONFIG_UTS_NS is not set -# CONFIG_PID_NS is not set -CONFIG_SCHED_AUTOGROUP=y -CONFIG_SCHED_TUNE=y -CONFIG_BLK_DEV_INITRD=y -# CONFIG_RD_XZ is not set -# CONFIG_RD_LZO is not set -# CONFIG_RD_LZ4 is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_KALLSYMS_ALL=y -# CONFIG_MEMBARRIER is not set -CONFIG_EMBEDDED=y -# CONFIG_SLUB_DEBUG is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_PROFILING=y -CONFIG_CC_STACKPROTECTOR_REGULAR=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SIG=y -CONFIG_MODULE_SIG_FORCE=y -CONFIG_MODULE_SIG_SHA512=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_ARCH_QCOM=y -CONFIG_ARCH_MSMFALCON=y -CONFIG_ARCH_MSMTRITON=y -CONFIG_PCI=y -CONFIG_PCI_MSM=y -CONFIG_SCHED_MC=y -CONFIG_NR_CPUS=8 -CONFIG_PREEMPT=y -CONFIG_HZ_100=y -CONFIG_ARM64_REG_REBALANCE_ON_CTX_SW=y -CONFIG_CMA=y -CONFIG_CMA_DEBUGFS=y -CONFIG_ZSMALLOC=y -CONFIG_BALANCE_ANON_FILE_RECLAIM=y -CONFIG_FORCE_ALLOC_FROM_DMA_ZONE=y -CONFIG_PROCESS_RECLAIM=y -CONFIG_SECCOMP=y -CONFIG_ARMV8_DEPRECATED=y -CONFIG_SWP_EMULATION=y -CONFIG_CP15_BARRIER_EMULATION=y -CONFIG_SETEND_EMULATION=y -# CONFIG_EFI is not set -CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_COMPAT=y -CONFIG_PM_AUTOSLEEP=y -CONFIG_PM_WAKELOCKS=y -CONFIG_PM_WAKELOCKS_LIMIT=0 -# CONFIG_PM_WAKELOCKS_GC is not set -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_INTERACTIVE=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_BOOST=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM_USER=y -CONFIG_XFRM_STATISTICS=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_INET_AH=y -CONFIG_INET_ESP=y -CONFIG_INET_IPCOMP=y -CONFIG_INET_DIAG_DESTROY=y -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y -CONFIG_IPV6_OPTIMISTIC_DAD=y -CONFIG_INET6_AH=y -CONFIG_INET6_ESP=y -CONFIG_INET6_IPCOMP=y -CONFIG_IPV6_MIP6=y -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_IPV6_SUBTREES=y -CONFIG_NETFILTER=y -CONFIG_NF_CONNTRACK=y -CONFIG_NF_CONNTRACK_SECMARK=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CT_PROTO_DCCP=y -CONFIG_NF_CT_PROTO_SCTP=y -CONFIG_NF_CT_PROTO_UDPLITE=y -CONFIG_NF_CONNTRACK_AMANDA=y -CONFIG_NF_CONNTRACK_FTP=y -CONFIG_NF_CONNTRACK_H323=y -CONFIG_NF_CONNTRACK_IRC=y -CONFIG_NF_CONNTRACK_NETBIOS_NS=y -CONFIG_NF_CONNTRACK_PPTP=y -CONFIG_NF_CONNTRACK_SANE=y -CONFIG_NF_CONNTRACK_TFTP=y -CONFIG_NF_CT_NETLINK=y -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y -CONFIG_NETFILTER_XT_TARGET_CONNMARK=y -CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y -CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y -CONFIG_NETFILTER_XT_TARGET_HARDIDLETIMER=y -CONFIG_NETFILTER_XT_TARGET_LOG=y -CONFIG_NETFILTER_XT_TARGET_MARK=y -CONFIG_NETFILTER_XT_TARGET_NFLOG=y -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y -CONFIG_NETFILTER_XT_TARGET_NOTRACK=y -CONFIG_NETFILTER_XT_TARGET_TEE=y -CONFIG_NETFILTER_XT_TARGET_TPROXY=y -CONFIG_NETFILTER_XT_TARGET_TRACE=y -CONFIG_NETFILTER_XT_TARGET_SECMARK=y -CONFIG_NETFILTER_XT_TARGET_TCPMSS=y -CONFIG_NETFILTER_XT_MATCH_COMMENT=y -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y -CONFIG_NETFILTER_XT_MATCH_CONNMARK=y -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y -CONFIG_NETFILTER_XT_MATCH_DSCP=y -CONFIG_NETFILTER_XT_MATCH_ESP=y -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y -CONFIG_NETFILTER_XT_MATCH_HELPER=y -CONFIG_NETFILTER_XT_MATCH_IPRANGE=y -# CONFIG_NETFILTER_XT_MATCH_L2TP is not set -CONFIG_NETFILTER_XT_MATCH_LENGTH=y -CONFIG_NETFILTER_XT_MATCH_LIMIT=y -CONFIG_NETFILTER_XT_MATCH_MAC=y -CONFIG_NETFILTER_XT_MATCH_MARK=y -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y -CONFIG_NETFILTER_XT_MATCH_POLICY=y -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y -CONFIG_NETFILTER_XT_MATCH_QTAGUID=y -CONFIG_NETFILTER_XT_MATCH_QUOTA=y -CONFIG_NETFILTER_XT_MATCH_QUOTA2=y -CONFIG_NETFILTER_XT_MATCH_SOCKET=y -CONFIG_NETFILTER_XT_MATCH_STATE=y -CONFIG_NETFILTER_XT_MATCH_STATISTIC=y -CONFIG_NETFILTER_XT_MATCH_STRING=y -CONFIG_NETFILTER_XT_MATCH_TIME=y -CONFIG_NETFILTER_XT_MATCH_U32=y -CONFIG_NF_CONNTRACK_IPV4=y -CONFIG_IP_NF_IPTABLES=y -CONFIG_IP_NF_MATCH_AH=y -CONFIG_IP_NF_MATCH_ECN=y -CONFIG_IP_NF_MATCH_RPFILTER=y -CONFIG_IP_NF_MATCH_TTL=y -CONFIG_IP_NF_FILTER=y -CONFIG_IP_NF_TARGET_REJECT=y -CONFIG_IP_NF_NAT=y -CONFIG_IP_NF_TARGET_MASQUERADE=y -CONFIG_IP_NF_TARGET_NETMAP=y -CONFIG_IP_NF_TARGET_REDIRECT=y -CONFIG_IP_NF_MANGLE=y -CONFIG_IP_NF_RAW=y -CONFIG_IP_NF_SECURITY=y -CONFIG_IP_NF_ARPTABLES=y -CONFIG_IP_NF_ARPFILTER=y -CONFIG_IP_NF_ARP_MANGLE=y -CONFIG_NF_CONNTRACK_IPV6=y -CONFIG_IP6_NF_IPTABLES=y -CONFIG_IP6_NF_MATCH_RPFILTER=y -CONFIG_IP6_NF_FILTER=y -CONFIG_IP6_NF_TARGET_REJECT=y -CONFIG_IP6_NF_MANGLE=y -CONFIG_IP6_NF_RAW=y -CONFIG_BRIDGE_NF_EBTABLES=y -CONFIG_BRIDGE_EBT_BROUTE=y -CONFIG_L2TP=y -CONFIG_L2TP_V3=y -CONFIG_L2TP_IP=y -CONFIG_L2TP_ETH=y -CONFIG_BRIDGE=y -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_HTB=y -CONFIG_NET_SCH_PRIO=y -CONFIG_NET_SCH_MULTIQ=y -CONFIG_NET_SCH_INGRESS=y -CONFIG_NET_CLS_FW=y -CONFIG_NET_CLS_U32=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_FLOW=y -CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_CMP=y -CONFIG_NET_EMATCH_NBYTE=y -CONFIG_NET_EMATCH_U32=y -CONFIG_NET_EMATCH_META=y -CONFIG_NET_EMATCH_TEXT=y -CONFIG_NET_CLS_ACT=y -CONFIG_NET_ACT_GACT=y -CONFIG_NET_ACT_MIRRED=y -CONFIG_NET_ACT_SKBEDIT=y -CONFIG_RMNET_DATA=y -CONFIG_RMNET_DATA_FC=y -CONFIG_RMNET_DATA_DEBUG_PKT=y -CONFIG_SOCKEV_NLMCAST=y -CONFIG_BT=y -CONFIG_MSM_BT_POWER=y -CONFIG_BTFM_SLIM=y -CONFIG_BTFM_SLIM_WCN3990=y -CONFIG_CFG80211=y -CONFIG_CFG80211_INTERNAL_REGDB=y -CONFIG_RFKILL=y -CONFIG_NFC_NQ=y -CONFIG_IPC_ROUTER=y -CONFIG_IPC_ROUTER_SECURITY=y -CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y -CONFIG_DMA_CMA=y -# CONFIG_PNP_DEBUG_MESSAGES is not set -CONFIG_ZRAM=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_QSEECOM=y -CONFIG_HDCP_QSEECOM=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -CONFIG_CHR_DEV_SCH=y -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y -CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_SCSI_UFSHCD=y -CONFIG_SCSI_UFSHCD_PLATFORM=y -CONFIG_SCSI_UFS_QCOM=y -CONFIG_SCSI_UFS_QCOM_ICE=y -CONFIG_MD=y -CONFIG_BLK_DEV_DM=y -CONFIG_DM_CRYPT=y -CONFIG_DM_REQ_CRYPT=y -CONFIG_DM_UEVENT=y -CONFIG_DM_VERITY=y -CONFIG_NETDEVICES=y -CONFIG_BONDING=y -CONFIG_DUMMY=y -CONFIG_TUN=y -CONFIG_SKY2=y -CONFIG_RNDIS_IPA=y -CONFIG_SMSC911X=y -CONFIG_PPP=y -CONFIG_PPP_BSDCOMP=y -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_MPPE=y -CONFIG_PPP_MULTILINK=y -CONFIG_PPPOE=y -CONFIG_PPPOL2TP=y -CONFIG_PPPOLAC=y -CONFIG_PPPOPNS=y -CONFIG_PPP_ASYNC=y -CONFIG_PPP_SYNC_TTY=y -CONFIG_USB_USBNET=y -CONFIG_WCNSS_MEM_PRE_ALLOC=y -CONFIG_ATH_CARDS=y -CONFIG_WIL6210=m -CONFIG_CLD_LL_CORE=y -CONFIG_QPNP_POWER_ON=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_KEYRESET=y -CONFIG_KEYBOARD_GPIO=y -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_v21=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y -CONFIG_SECURE_TOUCH=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_HBTP_INPUT=y -CONFIG_INPUT_UINPUT=y -# CONFIG_SERIO_SERPORT is not set -# CONFIG_VT is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_DEVMEM is not set -# CONFIG_DEVKMEM is not set -CONFIG_SERIAL_MSM_HS=y -CONFIG_SERIAL_MSM_SMD=y -CONFIG_DIAG_CHAR=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MSM_LEGACY=y -CONFIG_MSM_ADSPRPC=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MSM_V2=y -CONFIG_SLIMBUS_MSM_NGD=y -CONFIG_SOUNDWIRE=y -CONFIG_SPI=y -CONFIG_SPI_QUP=y -CONFIG_SPI_SPIDEV=y -CONFIG_SPMI=y -CONFIG_PINCTRL_MSM8998=y -CONFIG_PINCTRL_MSMFALCON=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_QPNP_PIN=y -CONFIG_POWER_RESET_QCOM=y -CONFIG_QCOM_DLOAD_MODE=y -CONFIG_POWER_RESET_XGENE=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_MSM_PM=y -CONFIG_APSS_CORE_EA=y -CONFIG_MSM_APM=y -CONFIG_QPNP_SMBCHARGER=y -CONFIG_QPNP_FG_GEN3=y -CONFIG_SMB135X_CHARGER=y -CONFIG_SMB1351_USB_CHARGER=y -CONFIG_MSM_BCL_CTL=y -CONFIG_MSM_BCL_PERIPHERAL_CTL=y -CONFIG_BATTERY_BCL=y -CONFIG_QPNP_SMB2=y -CONFIG_SMB138X_CHARGER=y -CONFIG_QPNP_QNOVO=y -CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y -CONFIG_CPU_THERMAL=y -CONFIG_LIMITS_MONITOR=y -CONFIG_LIMITS_LITE_HW=y -CONFIG_THERMAL_MONITOR=y -CONFIG_THERMAL_TSENS8974=y -CONFIG_THERMAL_QPNP=y -CONFIG_THERMAL_QPNP_ADC_TM=y -CONFIG_QCOM_THERMAL_LIMITS_DCVS=y -CONFIG_MFD_SPMI_PMIC=y -CONFIG_MFD_I2C_PMIC=y -CONFIG_WCD9335_CODEC=y -CONFIG_WCD934X_CODEC=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_MSM_GFX_LDO=y -CONFIG_REGULATOR_RPM_SMD=y -CONFIG_REGULATOR_QPNP=y -CONFIG_REGULATOR_QPNP_LABIBB=y -CONFIG_REGULATOR_QPNP_LCDB=y -CONFIG_REGULATOR_SPM=y -CONFIG_REGULATOR_CPR3_HMSS=y -CONFIG_REGULATOR_CPR3_MMSS=y -CONFIG_REGULATOR_CPRH_KBSS=y -CONFIG_REGULATOR_CPR4_MMSS_LDO=y -CONFIG_REGULATOR_MEM_ACC=y -CONFIG_REGULATOR_PROXY_CONSUMER=y -CONFIG_REGULATOR_STUB=y -CONFIG_MEDIA_SUPPORT=y -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_CONTROLLER=y -CONFIG_VIDEO_V4L2_SUBDEV_API=y -CONFIG_VIDEO_ADV_DEBUG=y -CONFIG_VIDEO_FIXED_MINOR_RANGES=y -CONFIG_MEDIA_USB_SUPPORT=y -CONFIG_USB_VIDEO_CLASS=y -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_MSM_CAMERA=y -CONFIG_MSM_CAMERA_DEBUG=y -CONFIG_MSMB_CAMERA=y -CONFIG_MSMB_CAMERA_DEBUG=y -CONFIG_MSM_CAMERA_SENSOR=y -CONFIG_MSM_CPP=y -CONFIG_MSM_CCI=y -CONFIG_MSM_CSI20_HEADER=y -CONFIG_MSM_CSI22_HEADER=y -CONFIG_MSM_CSI30_HEADER=y -CONFIG_MSM_CSI31_HEADER=y -CONFIG_MSM_CSIPHY=y -CONFIG_MSM_CSID=y -CONFIG_MSM_EEPROM=y -CONFIG_MSM_ISPIF=y -CONFIG_IMX134=y -CONFIG_IMX132=y -CONFIG_OV9724=y -CONFIG_OV5648=y -CONFIG_GC0339=y -CONFIG_OV8825=y -CONFIG_OV8865=y -CONFIG_s5k4e1=y -CONFIG_OV12830=y -CONFIG_MSM_V4L2_VIDEO_OVERLAY_DEVICE=y -CONFIG_MSMB_JPEG=y -CONFIG_MSM_FD=y -CONFIG_MSM_JPEGDMA=y -CONFIG_MSM_VIDC_V4L2=m -CONFIG_MSM_VIDC_VMEM=m -CONFIG_MSM_VIDC_GOVERNORS=m -CONFIG_MSM_SDE_ROTATOR=y -CONFIG_MSM_SDE_ROTATOR_EVTLOG_DEBUG=y -CONFIG_QCOM_KGSL=y -CONFIG_FB=y -CONFIG_FB_ARMCLCD=y -CONFIG_FB_MSM=y -CONFIG_FB_MSM_MDSS=y -CONFIG_FB_MSM_MDSS_WRITEBACK=y -CONFIG_FB_MSM_MDSS_HDMI_PANEL=y -CONFIG_FB_MSM_MDSS_DP_PANEL=y -CONFIG_FB_MSM_MDSS_XLOG_DEBUG=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_USB_AUDIO=y -CONFIG_SND_USB_AUDIO_QMI=y -CONFIG_SND_SOC=y -CONFIG_SND_SOC_MSM8998=y -CONFIG_SND_SOC_FALCON=y -CONFIG_UHID=y -CONFIG_HID_APPLE=y -CONFIG_HID_ELECOM=y -CONFIG_HID_MAGICMOUSE=y -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MULTITOUCH=y -CONFIG_HID_PLANTRONICS=y -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_STORAGE=y -CONFIG_USB_DWC3=y -CONFIG_USB_ISP1760=y -CONFIG_USB_ISP1760_HOST_ROLE=y -CONFIG_USB_PD_POLICY=y -CONFIG_QPNP_USB_PDPHY=y -CONFIG_USB_EHSET_TEST_FIXTURE=y -CONFIG_USB_OTG_WAKELOCK=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_USB_MSM_SSPHY_QMP=y -CONFIG_MSM_QUSB_PHY=y -CONFIG_DUAL_ROLE_USB_INTF=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_VBUS_DRAW=500 -CONFIG_USB_CONFIGFS=y -CONFIG_USB_CONFIGFS_NCM=y -CONFIG_USB_CONFIGFS_QCRNDIS=y -CONFIG_USB_CONFIGFS_RMNET_BAM=y -CONFIG_USB_CONFIGFS_MASS_STORAGE=y -CONFIG_USB_CONFIGFS_F_FS=y -CONFIG_USB_CONFIGFS_F_MTP=y -CONFIG_USB_CONFIGFS_F_PTP=y -CONFIG_USB_CONFIGFS_F_ACC=y -CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y -CONFIG_USB_CONFIGFS_UEVENT=y -CONFIG_USB_CONFIGFS_F_MIDI=y -CONFIG_USB_CONFIGFS_F_HID=y -CONFIG_USB_CONFIGFS_F_DIAG=y -CONFIG_USB_CONFIGFS_F_GSI=y -CONFIG_USB_CONFIGFS_F_CDEV=y -CONFIG_USB_CONFIGFS_F_QDSS=y -CONFIG_MMC=y -CONFIG_MMC_PERF_PROFILING=y -CONFIG_MMC_CLKGATE=y -CONFIG_MMC_BLOCK_MINORS=32 -CONFIG_MMC_TEST=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_MSM=y -CONFIG_LEDS_QPNP=y -CONFIG_LEDS_QPNP_FLASH_V2=y -CONFIG_LEDS_QPNP_WLED=y -CONFIG_LEDS_SYSCON=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_SWITCH=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_QPNP=y -CONFIG_DMADEVICES=y -CONFIG_QCOM_SPS_DMA=y -CONFIG_UIO=y -CONFIG_UIO_MSM_SHAREDMEM=y -CONFIG_STAGING=y -CONFIG_ASHMEM=y -CONFIG_ANDROID_TIMED_GPIO=y -CONFIG_ANDROID_LOW_MEMORY_KILLER=y -CONFIG_ION=y -CONFIG_ION_MSM=y -CONFIG_QPNP_REVID=y -CONFIG_QPNP_COINCELL=y -CONFIG_SPS=y -CONFIG_SPS_SUPPORT_NDP_BAM=y -CONFIG_IPA=y -CONFIG_RMNET_IPA=y -CONFIG_GSI=y -CONFIG_IPA3=y -CONFIG_RMNET_IPA3=y -CONFIG_GPIO_USB_DETECT=y -CONFIG_SEEMP_CORE=y -CONFIG_USB_BAM=y -CONFIG_QCOM_CLK_SMD_RPM=y -CONFIG_MSM_GPUCC_FALCON=y -CONFIG_MSM_MMCC_FALCON=y -CONFIG_CLOCK_CPU_OSM=y -CONFIG_QCOM_MDSS_PLL=y -CONFIG_REMOTE_SPINLOCK_MSM=y -CONFIG_IOMMU_IO_PGTABLE_FAST=y -CONFIG_ARM_SMMU=y -CONFIG_IOMMU_DEBUG=y -CONFIG_IOMMU_DEBUG_TRACKING=y -CONFIG_IOMMU_TESTS=y -CONFIG_MSM_SMEM=y -CONFIG_QPNP_HAPTIC=y -CONFIG_MSM_SMD=y -CONFIG_MSM_GLINK=y -CONFIG_MSM_GLINK_LOOPBACK_SERVER=y -CONFIG_MSM_GLINK_SMD_XPRT=y -CONFIG_MSM_GLINK_SMEM_NATIVE_XPRT=y -CONFIG_MSM_GLINK_SPI_XPRT=y -CONFIG_MSM_SPCOM=y -CONFIG_MSM_SPSS_UTILS=y -CONFIG_MSM_SMEM_LOGGING=y -CONFIG_MSM_SMP2P=y -CONFIG_MSM_SMP2P_TEST=y -CONFIG_MSM_QMI_INTERFACE=y -CONFIG_MSM_RPM_SMD=y -CONFIG_QCOM_BUS_SCALING=y -CONFIG_MSM_SERVICE_LOCATOR=y -CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y -CONFIG_MSM_SYSMON_GLINK_COMM=y -CONFIG_MSM_IPC_ROUTER_GLINK_XPRT=y -CONFIG_MSM_GLINK_PKT=y -CONFIG_MSM_SPM=y -CONFIG_QCOM_SCM=y -CONFIG_QCOM_WATCHDOG_V2=y -CONFIG_QCOM_IRQ_HELPER=y -CONFIG_QCOM_MEMORY_DUMP_V2=y -CONFIG_ICNSS=y -CONFIG_MSM_RUN_QUEUE_STATS=y -CONFIG_MSM_BOOT_STATS=y -CONFIG_MSM_ADSP_LOADER=y -CONFIG_MSM_PERFORMANCE=y -CONFIG_MSM_SUBSYSTEM_RESTART=y -CONFIG_MSM_PIL=y -CONFIG_MSM_PIL_SSR_GENERIC=y -CONFIG_MSM_PIL_MSS_QDSP6V5=y -CONFIG_TRACER_PKT=y -CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y -CONFIG_MSM_MPM_OF=y -CONFIG_MSM_EVENT_TIMER=y -CONFIG_MSM_AVTIMER=y -CONFIG_QCOM_REMOTEQDSS=y -CONFIG_MSM_SERVICE_NOTIFIER=y -CONFIG_MSM_RPM_RBCPR_STATS_V2_LOG=y -CONFIG_MSM_RPM_LOG=y -CONFIG_MSM_RPM_STATS_LOG=y -CONFIG_QSEE_IPC_IRQ_BRIDGE=y -CONFIG_QCOM_SMCINVOKE=y -CONFIG_QCOM_EARLY_RANDOM=y -CONFIG_MEM_SHARE_QMI_SERVICE=y -CONFIG_QCOM_BIMC_BWMON=y -CONFIG_ARM_MEMLAT_MON=y -CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y -CONFIG_DEVFREQ_GOV_MEMLAT=y -CONFIG_QCOM_DEVFREQ_DEVBW=y -CONFIG_SPDM_SCM=y -CONFIG_DEVFREQ_SPDM=y -CONFIG_EXTCON=y -CONFIG_IIO=y -CONFIG_QCOM_RRADC=y -CONFIG_QCOM_TADC=y -CONFIG_PWM=y -CONFIG_PWM_QPNP=y -CONFIG_ARM_GIC_V3_ACL=y -CONFIG_ANDROID=y -CONFIG_ANDROID_BINDER_IPC=y -CONFIG_MSM_TZ_LOG=y -CONFIG_SENSORS_SSC=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT3_FS=y -CONFIG_EXT4_FS_SECURITY=y -CONFIG_EXT4_ENCRYPTION=y -CONFIG_EXT4_FS_ENCRYPTION=y -CONFIG_EXT4_FS_ICE_ENCRYPTION=y -CONFIG_FUSE_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_ECRYPT_FS=y -CONFIG_ECRYPT_FS_MESSAGING=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_INFO=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_PANIC_TIMEOUT=5 -CONFIG_SCHEDSTATS=y -CONFIG_TIMER_STATS=y -# CONFIG_DEBUG_PREEMPT is not set -CONFIG_IPC_LOGGING=y -CONFIG_CPU_FREQ_SWITCH_PROFILER=y -CONFIG_DEBUG_SET_MODULE_RONX=y -CONFIG_DEBUG_RODATA=y -CONFIG_DEBUG_ALIGN_RODATA=y -CONFIG_CORESIGHT=y -CONFIG_CORESIGHT_EVENT=y -CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y -CONFIG_CORESIGHT_QCOM_REPLICATOR=y -CONFIG_CORESIGHT_STM=y -CONFIG_CORESIGHT_HWEVENT=y -CONFIG_CORESIGHT_CTI=y -CONFIG_CORESIGHT_TPDA=y -CONFIG_CORESIGHT_TPDM=y -CONFIG_CORESIGHT_QPDI=y -CONFIG_CORESIGHT_SOURCE_DUMMY=y -CONFIG_PFK=y -CONFIG_SECURITY=y -CONFIG_SECURITY_SELINUX=y -CONFIG_SECURITY_SMACK=y -CONFIG_CRYPTO_ECHAINIV=y -CONFIG_CRYPTO_XCBC=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_ANSI_CPRNG=y -CONFIG_CRYPTO_DEV_QCRYPTO=y -CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y -CONFIG_CRYPTO_DEV_QCEDEV=y -CONFIG_CRYPTO_DEV_OTA_CRYPTO=y -CONFIG_CRYPTO_DEV_QCOM_ICE=y -CONFIG_ARM64_CRYPTO=y -CONFIG_CRYPTO_SHA1_ARM64_CE=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y -CONFIG_CRYPTO_CRC32_ARM64=y -CONFIG_QMI_ENCDEC=y diff --git a/arch/arm64/configs/msmfalcon_defconfig b/arch/arm64/configs/msmfalcon_defconfig deleted file mode 100644 index ce91e8992b46..000000000000 --- a/arch/arm64/configs/msmfalcon_defconfig +++ /dev/null @@ -1,712 +0,0 @@ -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_AUDIT=y -# CONFIG_AUDITSYSCALL is not set -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_RCU_EXPERT=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_CPU_MAX_BUF_SHIFT=17 -CONFIG_CGROUPS=y -CONFIG_CGROUP_DEBUG=y -CONFIG_CGROUP_FREEZER=y -CONFIG_CPUSETS=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_CGROUP_SCHEDTUNE=y -CONFIG_MEMCG=y -CONFIG_MEMCG_SWAP=y -CONFIG_CGROUP_SCHED=y -CONFIG_RT_GROUP_SCHED=y -CONFIG_SCHED_HMP=y -CONFIG_SCHED_HMP_CSTATE_AWARE=y -CONFIG_SCHED_CORE_CTL=y -CONFIG_NAMESPACES=y -# CONFIG_UTS_NS is not set -# CONFIG_PID_NS is not set -CONFIG_SCHED_TUNE=y -CONFIG_BLK_DEV_INITRD=y -# CONFIG_RD_XZ is not set -# CONFIG_RD_LZO is not set -# CONFIG_RD_LZ4 is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_KALLSYMS_ALL=y -# CONFIG_MEMBARRIER is not set -CONFIG_EMBEDDED=y -# CONFIG_COMPAT_BRK is not set -CONFIG_PROFILING=y -CONFIG_CC_STACKPROTECTOR_REGULAR=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SIG=y -CONFIG_MODULE_SIG_FORCE=y -CONFIG_MODULE_SIG_SHA512=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_PARTITION_ADVANCED=y -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_ARCH_QCOM=y -CONFIG_ARCH_MSMFALCON=y -CONFIG_ARCH_MSMTRITON=y -CONFIG_PCI=y -CONFIG_PCI_MSM=y -CONFIG_SCHED_MC=y -CONFIG_NR_CPUS=8 -CONFIG_PREEMPT=y -CONFIG_HZ_100=y -CONFIG_CLEANCACHE=y -CONFIG_CMA=y -CONFIG_CMA_DEBUGFS=y -CONFIG_ZSMALLOC=y -CONFIG_PROCESS_RECLAIM=y -CONFIG_SECCOMP=y -CONFIG_ARMV8_DEPRECATED=y -CONFIG_SWP_EMULATION=y -CONFIG_CP15_BARRIER_EMULATION=y -CONFIG_SETEND_EMULATION=y -CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_COMPAT=y -CONFIG_PM_AUTOSLEEP=y -CONFIG_PM_WAKELOCKS=y -CONFIG_PM_WAKELOCKS_LIMIT=0 -# CONFIG_PM_WAKELOCKS_GC is not set -CONFIG_PM_DEBUG=y -CONFIG_CPU_FREQ=y -# CONFIG_CPU_FREQ_STAT is not set -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_INTERACTIVE=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM_USER=y -CONFIG_XFRM_STATISTICS=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_INET_AH=y -CONFIG_INET_ESP=y -CONFIG_INET_IPCOMP=y -CONFIG_INET_DIAG_DESTROY=y -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y -CONFIG_IPV6_OPTIMISTIC_DAD=y -CONFIG_INET6_AH=y -CONFIG_INET6_ESP=y -CONFIG_INET6_IPCOMP=y -CONFIG_IPV6_MIP6=y -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_IPV6_SUBTREES=y -CONFIG_NETFILTER=y -CONFIG_NF_CONNTRACK=y -CONFIG_NF_CONNTRACK_SECMARK=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CT_PROTO_DCCP=y -CONFIG_NF_CT_PROTO_SCTP=y -CONFIG_NF_CT_PROTO_UDPLITE=y -CONFIG_NF_CONNTRACK_AMANDA=y -CONFIG_NF_CONNTRACK_FTP=y -CONFIG_NF_CONNTRACK_H323=y -CONFIG_NF_CONNTRACK_IRC=y -CONFIG_NF_CONNTRACK_NETBIOS_NS=y -CONFIG_NF_CONNTRACK_PPTP=y -CONFIG_NF_CONNTRACK_SANE=y -CONFIG_NF_CONNTRACK_TFTP=y -CONFIG_NF_CT_NETLINK=y -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y -CONFIG_NETFILTER_XT_TARGET_CONNMARK=y -CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y -CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y -CONFIG_NETFILTER_XT_TARGET_HARDIDLETIMER=y -CONFIG_NETFILTER_XT_TARGET_LOG=y -CONFIG_NETFILTER_XT_TARGET_MARK=y -CONFIG_NETFILTER_XT_TARGET_NFLOG=y -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y -CONFIG_NETFILTER_XT_TARGET_NOTRACK=y -CONFIG_NETFILTER_XT_TARGET_TEE=y -CONFIG_NETFILTER_XT_TARGET_TPROXY=y -CONFIG_NETFILTER_XT_TARGET_TRACE=y -CONFIG_NETFILTER_XT_TARGET_SECMARK=y -CONFIG_NETFILTER_XT_TARGET_TCPMSS=y -CONFIG_NETFILTER_XT_MATCH_COMMENT=y -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y -CONFIG_NETFILTER_XT_MATCH_CONNMARK=y -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y -CONFIG_NETFILTER_XT_MATCH_DSCP=y -CONFIG_NETFILTER_XT_MATCH_ESP=y -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y -CONFIG_NETFILTER_XT_MATCH_HELPER=y -CONFIG_NETFILTER_XT_MATCH_IPRANGE=y -# CONFIG_NETFILTER_XT_MATCH_L2TP is not set -CONFIG_NETFILTER_XT_MATCH_LENGTH=y -CONFIG_NETFILTER_XT_MATCH_LIMIT=y -CONFIG_NETFILTER_XT_MATCH_MAC=y -CONFIG_NETFILTER_XT_MATCH_MARK=y -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y -CONFIG_NETFILTER_XT_MATCH_POLICY=y -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y -CONFIG_NETFILTER_XT_MATCH_QTAGUID=y -CONFIG_NETFILTER_XT_MATCH_QUOTA=y -CONFIG_NETFILTER_XT_MATCH_QUOTA2=y -CONFIG_NETFILTER_XT_MATCH_SOCKET=y -CONFIG_NETFILTER_XT_MATCH_STATE=y -CONFIG_NETFILTER_XT_MATCH_STATISTIC=y -CONFIG_NETFILTER_XT_MATCH_STRING=y -CONFIG_NETFILTER_XT_MATCH_TIME=y -CONFIG_NETFILTER_XT_MATCH_U32=y -CONFIG_NF_CONNTRACK_IPV4=y -CONFIG_IP_NF_IPTABLES=y -CONFIG_IP_NF_MATCH_AH=y -CONFIG_IP_NF_MATCH_ECN=y -CONFIG_IP_NF_MATCH_RPFILTER=y -CONFIG_IP_NF_MATCH_TTL=y -CONFIG_IP_NF_FILTER=y -CONFIG_IP_NF_TARGET_REJECT=y -CONFIG_IP_NF_NAT=y -CONFIG_IP_NF_TARGET_MASQUERADE=y -CONFIG_IP_NF_TARGET_NETMAP=y -CONFIG_IP_NF_TARGET_REDIRECT=y -CONFIG_IP_NF_MANGLE=y -CONFIG_IP_NF_RAW=y -CONFIG_IP_NF_SECURITY=y -CONFIG_IP_NF_ARPTABLES=y -CONFIG_IP_NF_ARPFILTER=y -CONFIG_IP_NF_ARP_MANGLE=y -CONFIG_NF_CONNTRACK_IPV6=y -CONFIG_IP6_NF_IPTABLES=y -CONFIG_IP6_NF_MATCH_RPFILTER=y -CONFIG_IP6_NF_FILTER=y -CONFIG_IP6_NF_TARGET_REJECT=y -CONFIG_IP6_NF_MANGLE=y -CONFIG_IP6_NF_RAW=y -CONFIG_BRIDGE_NF_EBTABLES=y -CONFIG_BRIDGE_EBT_BROUTE=y -CONFIG_L2TP=y -CONFIG_L2TP_DEBUGFS=y -CONFIG_L2TP_V3=y -CONFIG_L2TP_IP=y -CONFIG_L2TP_ETH=y -CONFIG_BRIDGE=y -CONFIG_NET_SCHED=y -CONFIG_NET_SCH_HTB=y -CONFIG_NET_SCH_PRIO=y -CONFIG_NET_SCH_MULTIQ=y -CONFIG_NET_SCH_INGRESS=y -CONFIG_NET_CLS_FW=y -CONFIG_NET_CLS_U32=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_FLOW=y -CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_CMP=y -CONFIG_NET_EMATCH_NBYTE=y -CONFIG_NET_EMATCH_U32=y -CONFIG_NET_EMATCH_META=y -CONFIG_NET_EMATCH_TEXT=y -CONFIG_NET_CLS_ACT=y -CONFIG_NET_ACT_GACT=y -CONFIG_NET_ACT_MIRRED=y -CONFIG_NET_ACT_SKBEDIT=y -CONFIG_DNS_RESOLVER=y -CONFIG_RMNET_DATA=y -CONFIG_RMNET_DATA_FC=y -CONFIG_RMNET_DATA_DEBUG_PKT=y -CONFIG_SOCKEV_NLMCAST=y -CONFIG_BT=y -CONFIG_MSM_BT_POWER=y -CONFIG_BTFM_SLIM=y -CONFIG_BTFM_SLIM_WCN3990=y -CONFIG_CFG80211=y -CONFIG_CFG80211_INTERNAL_REGDB=y -# CONFIG_CFG80211_CRDA_SUPPORT is not set -CONFIG_RFKILL=y -CONFIG_NFC_NQ=y -CONFIG_IPC_ROUTER=y -CONFIG_IPC_ROUTER_SECURITY=y -CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y -CONFIG_DMA_CMA=y -CONFIG_ZRAM=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_QSEECOM=y -CONFIG_HDCP_QSEECOM=y -CONFIG_UID_CPUTIME=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -CONFIG_CHR_DEV_SCH=y -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_LOGGING=y -CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_SCSI_UFSHCD=y -CONFIG_SCSI_UFSHCD_PLATFORM=y -CONFIG_SCSI_UFS_QCOM=y -CONFIG_SCSI_UFS_QCOM_ICE=y -CONFIG_MD=y -CONFIG_BLK_DEV_DM=y -CONFIG_DM_CRYPT=y -CONFIG_DM_REQ_CRYPT=y -CONFIG_DM_UEVENT=y -CONFIG_DM_VERITY=y -CONFIG_NETDEVICES=y -CONFIG_BONDING=y -CONFIG_DUMMY=y -CONFIG_TUN=y -CONFIG_RNDIS_IPA=y -CONFIG_PPP=y -CONFIG_PPP_BSDCOMP=y -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_MPPE=y -CONFIG_PPP_MULTILINK=y -CONFIG_PPPOE=y -CONFIG_PPPOL2TP=y -CONFIG_PPPOLAC=y -CONFIG_PPPOPNS=y -CONFIG_PPP_ASYNC=y -CONFIG_PPP_SYNC_TTY=y -CONFIG_USB_USBNET=y -CONFIG_WCNSS_MEM_PRE_ALLOC=y -CONFIG_ATH_CARDS=y -CONFIG_WIL6210=m -CONFIG_CLD_LL_CORE=y -CONFIG_QPNP_POWER_ON=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_KEYRESET=y -CONFIG_KEYBOARD_GPIO=y -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_JOYSTICK=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_v21=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y -CONFIG_SECURE_TOUCH=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_HBTP_INPUT=y -CONFIG_INPUT_KEYCHORD=y -CONFIG_INPUT_UINPUT=y -CONFIG_INPUT_GPIO=y -# CONFIG_SERIO_SERPORT is not set -# CONFIG_VT is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_MSM=y -CONFIG_SERIAL_MSM_CONSOLE=y -CONFIG_SERIAL_MSM_HS=y -CONFIG_SERIAL_MSM_SMD=y -CONFIG_DIAG_CHAR=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MSM_LEGACY=y -CONFIG_MSM_ADSPRPC=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MSM_V2=y -CONFIG_SLIMBUS_MSM_NGD=y -CONFIG_SOUNDWIRE=y -CONFIG_SPI=y -CONFIG_SPI_QUP=y -CONFIG_SPI_SPIDEV=y -CONFIG_SPMI=y -CONFIG_PINCTRL_MSMFALCON=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_QPNP_PIN=y -CONFIG_POWER_RESET_QCOM=y -CONFIG_QCOM_DLOAD_MODE=y -CONFIG_POWER_RESET_XGENE=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_MSM_PM=y -CONFIG_APSS_CORE_EA=y -CONFIG_MSM_APM=y -CONFIG_QPNP_SMBCHARGER=y -CONFIG_QPNP_FG_GEN3=y -CONFIG_SMB135X_CHARGER=y -CONFIG_SMB1351_USB_CHARGER=y -CONFIG_MSM_BCL_CTL=y -CONFIG_MSM_BCL_PERIPHERAL_CTL=y -CONFIG_BATTERY_BCL=y -CONFIG_QPNP_SMB2=y -CONFIG_SMB138X_CHARGER=y -CONFIG_QPNP_QNOVO=y -CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y -CONFIG_CPU_THERMAL=y -CONFIG_LIMITS_MONITOR=y -CONFIG_LIMITS_LITE_HW=y -CONFIG_THERMAL_MONITOR=y -CONFIG_THERMAL_TSENS8974=y -CONFIG_THERMAL_QPNP=y -CONFIG_THERMAL_QPNP_ADC_TM=y -CONFIG_QCOM_THERMAL_LIMITS_DCVS=y -CONFIG_MFD_SPMI_PMIC=y -CONFIG_MFD_I2C_PMIC=y -CONFIG_WCD9335_CODEC=y -CONFIG_WCD934X_CODEC=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_MSM_GFX_LDO=y -CONFIG_REGULATOR_RPM_SMD=y -CONFIG_REGULATOR_QPNP=y -CONFIG_REGULATOR_QPNP_LABIBB=y -CONFIG_REGULATOR_QPNP_LCDB=y -CONFIG_REGULATOR_SPM=y -CONFIG_REGULATOR_CPR3_HMSS=y -CONFIG_REGULATOR_CPR3_MMSS=y -CONFIG_REGULATOR_CPRH_KBSS=y -CONFIG_REGULATOR_CPR4_MMSS_LDO=y -CONFIG_REGULATOR_MEM_ACC=y -CONFIG_REGULATOR_PROXY_CONSUMER=y -CONFIG_REGULATOR_STUB=y -CONFIG_MEDIA_SUPPORT=y -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_CONTROLLER=y -CONFIG_VIDEO_V4L2_SUBDEV_API=y -CONFIG_VIDEO_ADV_DEBUG=y -CONFIG_VIDEO_FIXED_MINOR_RANGES=y -CONFIG_MEDIA_USB_SUPPORT=y -CONFIG_USB_VIDEO_CLASS=y -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_MSM_CAMERA=y -CONFIG_MSM_CAMERA_DEBUG=y -CONFIG_MSMB_CAMERA=y -CONFIG_MSMB_CAMERA_DEBUG=y -CONFIG_MSM_CAMERA_SENSOR=y -CONFIG_MSM_CPP=y -CONFIG_MSM_CCI=y -CONFIG_MSM_CSI20_HEADER=y -CONFIG_MSM_CSI22_HEADER=y -CONFIG_MSM_CSI30_HEADER=y -CONFIG_MSM_CSI31_HEADER=y -CONFIG_MSM_CSIPHY=y -CONFIG_MSM_CSID=y -CONFIG_MSM_EEPROM=y -CONFIG_MSM_ISPIF=y -CONFIG_IMX134=y -CONFIG_IMX132=y -CONFIG_OV9724=y -CONFIG_OV5648=y -CONFIG_GC0339=y -CONFIG_OV8825=y -CONFIG_OV8865=y -CONFIG_s5k4e1=y -CONFIG_OV12830=y -CONFIG_MSM_V4L2_VIDEO_OVERLAY_DEVICE=y -CONFIG_MSMB_JPEG=y -CONFIG_MSM_FD=y -CONFIG_MSM_JPEGDMA=y -CONFIG_MSM_VIDC_V4L2=m -CONFIG_MSM_VIDC_VMEM=m -CONFIG_MSM_VIDC_GOVERNORS=m -CONFIG_MSM_SDE_ROTATOR=y -CONFIG_MSM_SDE_ROTATOR_EVTLOG_DEBUG=y -CONFIG_QCOM_KGSL=y -CONFIG_FB=y -CONFIG_FB_VIRTUAL=y -CONFIG_FB_MSM=y -CONFIG_FB_MSM_MDSS=y -CONFIG_FB_MSM_MDSS_WRITEBACK=y -CONFIG_FB_MSM_MDSS_HDMI_PANEL=y -CONFIG_FB_MSM_MDSS_DP_PANEL=y -CONFIG_FB_MSM_MDSS_XLOG_DEBUG=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_USB_AUDIO=y -CONFIG_SND_USB_AUDIO_QMI=y -CONFIG_SND_SOC=y -CONFIG_SND_SOC_MSM8998=y -CONFIG_SND_SOC_FALCON=y -CONFIG_UHID=y -CONFIG_HID_APPLE=y -CONFIG_HID_ELECOM=y -CONFIG_HID_MAGICMOUSE=y -CONFIG_HID_MICROSOFT=y -CONFIG_HID_MULTITOUCH=y -CONFIG_HID_PLANTRONICS=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_STORAGE=y -CONFIG_USB_DWC3=y -CONFIG_USB_ISP1760=y -CONFIG_USB_ISP1760_HOST_ROLE=y -CONFIG_USB_PD_POLICY=y -CONFIG_QPNP_USB_PDPHY=y -CONFIG_USB_EHSET_TEST_FIXTURE=y -CONFIG_USB_OTG_WAKELOCK=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_USB_MSM_SSPHY_QMP=y -CONFIG_MSM_QUSB_PHY=y -CONFIG_DUAL_ROLE_USB_INTF=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_VBUS_DRAW=500 -CONFIG_USB_CONFIGFS=y -CONFIG_USB_CONFIGFS_NCM=y -CONFIG_USB_CONFIGFS_QCRNDIS=y -CONFIG_USB_CONFIGFS_RMNET_BAM=y -CONFIG_USB_CONFIGFS_MASS_STORAGE=y -CONFIG_USB_CONFIGFS_F_FS=y -CONFIG_USB_CONFIGFS_F_MTP=y -CONFIG_USB_CONFIGFS_F_PTP=y -CONFIG_USB_CONFIGFS_F_ACC=y -CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y -CONFIG_USB_CONFIGFS_UEVENT=y -CONFIG_USB_CONFIGFS_F_MIDI=y -CONFIG_USB_CONFIGFS_F_HID=y -CONFIG_USB_CONFIGFS_F_DIAG=y -CONFIG_USB_CONFIGFS_F_GSI=y -CONFIG_USB_CONFIGFS_F_CDEV=y -CONFIG_USB_CONFIGFS_F_QDSS=y -CONFIG_MMC=y -CONFIG_MMC_PERF_PROFILING=y -CONFIG_MMC_PARANOID_SD_INIT=y -CONFIG_MMC_CLKGATE=y -CONFIG_MMC_BLOCK_MINORS=32 -CONFIG_MMC_TEST=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_MSM=y -CONFIG_LEDS_QPNP=y -CONFIG_LEDS_QPNP_FLASH_V2=y -CONFIG_LEDS_QPNP_WLED=y -CONFIG_LEDS_SYSCON=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_SWITCH=y -CONFIG_EDAC=y -CONFIG_EDAC_MM_EDAC=y -CONFIG_EDAC_CORTEX_ARM64=y -CONFIG_EDAC_CORTEX_ARM64_PANIC_ON_CE=y -CONFIG_EDAC_CORTEX_ARM64_PANIC_ON_UE=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_QPNP=y -CONFIG_DMADEVICES=y -CONFIG_QCOM_SPS_DMA=y -CONFIG_UIO=y -CONFIG_UIO_MSM_SHAREDMEM=y -CONFIG_STAGING=y -CONFIG_ASHMEM=y -CONFIG_ANDROID_TIMED_GPIO=y -CONFIG_ANDROID_LOW_MEMORY_KILLER=y -CONFIG_ION=y -CONFIG_ION_MSM=y -CONFIG_QPNP_REVID=y -CONFIG_QPNP_COINCELL=y -CONFIG_SPS=y -CONFIG_SPS_SUPPORT_NDP_BAM=y -CONFIG_IPA=y -CONFIG_RMNET_IPA=y -CONFIG_GSI=y -CONFIG_IPA3=y -CONFIG_RMNET_IPA3=y -CONFIG_GPIO_USB_DETECT=y -CONFIG_SEEMP_CORE=y -CONFIG_USB_BAM=y -CONFIG_QCOM_CLK_SMD_RPM=y -CONFIG_MSM_GPUCC_FALCON=y -CONFIG_MSM_MMCC_FALCON=y -CONFIG_CLOCK_CPU_OSM=y -CONFIG_QCOM_MDSS_PLL=y -CONFIG_REMOTE_SPINLOCK_MSM=y -CONFIG_IOMMU_IO_PGTABLE_FAST=y -CONFIG_IOMMU_IO_PGTABLE_FAST_SELFTEST=y -CONFIG_ARM_SMMU=y -CONFIG_IOMMU_DEBUG=y -CONFIG_IOMMU_DEBUG_TRACKING=y -CONFIG_IOMMU_TESTS=y -CONFIG_QCOM_COMMON_LOG=y -CONFIG_MSM_SMEM=y -CONFIG_QPNP_HAPTIC=y -CONFIG_MSM_SMD=y -CONFIG_MSM_SMD_DEBUG=y -CONFIG_MSM_GLINK=y -CONFIG_MSM_GLINK_LOOPBACK_SERVER=y -CONFIG_MSM_GLINK_SMD_XPRT=y -CONFIG_MSM_GLINK_SMEM_NATIVE_XPRT=y -CONFIG_MSM_GLINK_SPI_XPRT=y -CONFIG_MSM_SPCOM=y -CONFIG_MSM_SPSS_UTILS=y -CONFIG_MSM_SMEM_LOGGING=y -CONFIG_MSM_SMP2P=y -CONFIG_MSM_SMP2P_TEST=y -CONFIG_MSM_QMI_INTERFACE=y -CONFIG_MSM_RPM_SMD=y -CONFIG_QCOM_BUS_SCALING=y -CONFIG_MSM_SERVICE_LOCATOR=y -CONFIG_QCOM_DCC=y -CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y -CONFIG_MSM_SYSMON_GLINK_COMM=y -CONFIG_MSM_IPC_ROUTER_GLINK_XPRT=y -CONFIG_MSM_GLINK_PKT=y -CONFIG_MSM_SPM=y -CONFIG_QCOM_SCM=y -CONFIG_QCOM_WATCHDOG_V2=y -CONFIG_QCOM_IRQ_HELPER=y -CONFIG_QCOM_MEMORY_DUMP_V2=y -CONFIG_ICNSS=y -CONFIG_ICNSS_DEBUG=y -CONFIG_MSM_GLADIATOR_ERP_V2=y -CONFIG_PANIC_ON_GLADIATOR_ERROR_V2=y -CONFIG_MSM_GLADIATOR_HANG_DETECT=y -CONFIG_MSM_CORE_HANG_DETECT=y -CONFIG_MSM_RUN_QUEUE_STATS=y -CONFIG_MSM_BOOT_STATS=y -CONFIG_QCOM_CPUSS_DUMP=y -CONFIG_MSM_ADSP_LOADER=y -CONFIG_MSM_PERFORMANCE=y -CONFIG_MSM_SUBSYSTEM_RESTART=y -CONFIG_MSM_PIL=y -CONFIG_MSM_PIL_SSR_GENERIC=y -CONFIG_MSM_PIL_MSS_QDSP6V5=y -CONFIG_TRACER_PKT=y -CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y -CONFIG_MSM_MPM_OF=y -CONFIG_MSM_EVENT_TIMER=y -CONFIG_MSM_AVTIMER=y -CONFIG_QCOM_REMOTEQDSS=y -CONFIG_MSM_SERVICE_NOTIFIER=y -CONFIG_MSM_RPM_RBCPR_STATS_V2_LOG=y -CONFIG_MSM_RPM_LOG=y -CONFIG_MSM_RPM_STATS_LOG=y -CONFIG_QSEE_IPC_IRQ_BRIDGE=y -CONFIG_QCOM_SMCINVOKE=y -CONFIG_QCOM_EARLY_RANDOM=y -CONFIG_MEM_SHARE_QMI_SERVICE=y -CONFIG_QCOM_BIMC_BWMON=y -CONFIG_ARM_MEMLAT_MON=y -CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y -CONFIG_DEVFREQ_GOV_MEMLAT=y -CONFIG_QCOM_DEVFREQ_DEVBW=y -CONFIG_SPDM_SCM=y -CONFIG_DEVFREQ_SPDM=y -CONFIG_EXTCON=y -CONFIG_IIO=y -CONFIG_QCOM_RRADC=y -CONFIG_QCOM_TADC=y -CONFIG_PWM=y -CONFIG_PWM_QPNP=y -CONFIG_ARM_GIC_V3_ACL=y -CONFIG_PHY_XGENE=y -CONFIG_ANDROID=y -CONFIG_ANDROID_BINDER_IPC=y -CONFIG_MSM_TZ_LOG=y -CONFIG_SENSORS_SSC=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT3_FS=y -CONFIG_EXT4_FS_SECURITY=y -CONFIG_EXT4_ENCRYPTION=y -CONFIG_EXT4_FS_ENCRYPTION=y -CONFIG_EXT4_FS_ICE_ENCRYPTION=y -CONFIG_FUSE_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_EFIVAR_FS=y -CONFIG_ECRYPT_FS=y -CONFIG_ECRYPT_FS_MESSAGING=y -# CONFIG_NETWORK_FILESYSTEMS is not set -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_PRINTK_TIME=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_DEBUG_INFO=y -CONFIG_PAGE_OWNER=y -CONFIG_PAGE_OWNER_ENABLE_DEFAULT=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT=y -CONFIG_SLUB_DEBUG_PANIC_ON=y -CONFIG_DEBUG_OBJECTS=y -CONFIG_DEBUG_OBJECTS_FREE=y -CONFIG_DEBUG_OBJECTS_TIMERS=y -CONFIG_DEBUG_OBJECTS_WORK=y -CONFIG_DEBUG_OBJECTS_RCU_HEAD=y -CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y -CONFIG_SLUB_DEBUG_ON=y -CONFIG_DEBUG_KMEMLEAK=y -CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=4000 -CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y -CONFIG_DEBUG_STACK_USAGE=y -CONFIG_DEBUG_MEMORY_INIT=y -CONFIG_LOCKUP_DETECTOR=y -CONFIG_WQ_WATCHDOG=y -CONFIG_PANIC_TIMEOUT=5 -CONFIG_PANIC_ON_SCHED_BUG=y -CONFIG_PANIC_ON_RT_THROTTLING=y -CONFIG_SCHEDSTATS=y -CONFIG_SCHED_STACK_END_CHECK=y -CONFIG_TIMER_STATS=y -# CONFIG_DEBUG_PREEMPT is not set -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_ATOMIC_SLEEP=y -CONFIG_DEBUG_LIST=y -CONFIG_FAULT_INJECTION=y -CONFIG_FAIL_PAGE_ALLOC=y -CONFIG_UFS_FAULT_INJECTION=y -CONFIG_FAULT_INJECTION_DEBUG_FS=y -CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y -CONFIG_IPC_LOGGING=y -CONFIG_QCOM_RTB=y -CONFIG_QCOM_RTB_SEPARATE_CPUS=y -CONFIG_FUNCTION_TRACER=y -CONFIG_IRQSOFF_TRACER=y -CONFIG_PREEMPT_TRACER=y -CONFIG_BLK_DEV_IO_TRACE=y -CONFIG_CPU_FREQ_SWITCH_PROFILER=y -CONFIG_MEMTEST=y -CONFIG_PANIC_ON_DATA_CORRUPTION=y -CONFIG_ARM64_PTDUMP=y -CONFIG_PID_IN_CONTEXTIDR=y -CONFIG_DEBUG_SET_MODULE_RONX=y -CONFIG_DEBUG_RODATA=y -CONFIG_FREE_PAGES_RDONLY=y -CONFIG_CORESIGHT=y -CONFIG_CORESIGHT_EVENT=y -CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y -CONFIG_CORESIGHT_SOURCE_ETM4X=y -CONFIG_CORESIGHT_REMOTE_ETM=y -CONFIG_CORESIGHT_REMOTE_ETM_DEFAULT_ENABLE=0 -CONFIG_CORESIGHT_QCOM_REPLICATOR=y -CONFIG_CORESIGHT_STM=y -CONFIG_CORESIGHT_HWEVENT=y -CONFIG_CORESIGHT_CTI=y -CONFIG_CORESIGHT_TPDA=y -CONFIG_CORESIGHT_TPDM=y -CONFIG_CORESIGHT_QPDI=y -CONFIG_CORESIGHT_SOURCE_DUMMY=y -CONFIG_PFK=y -CONFIG_SECURITY=y -CONFIG_SECURITY_SELINUX=y -CONFIG_SECURITY_SMACK=y -CONFIG_CRYPTO_ECHAINIV=y -CONFIG_CRYPTO_XCBC=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_ANSI_CPRNG=y -CONFIG_CRYPTO_DEV_QCRYPTO=y -CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y -CONFIG_CRYPTO_DEV_QCEDEV=y -CONFIG_CRYPTO_DEV_OTA_CRYPTO=y -CONFIG_CRYPTO_DEV_QCOM_ICE=y -CONFIG_ARM64_CRYPTO=y -CONFIG_CRYPTO_SHA1_ARM64_CE=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y -CONFIG_CRYPTO_CRC32_ARM64=y -CONFIG_XZ_DEC=y -CONFIG_QMI_ENCDEC=y diff --git a/arch/arm64/configs/sdm660-perf_defconfig b/arch/arm64/configs/sdm660-perf_defconfig new file mode 100644 index 000000000000..239debeb6f0b --- /dev/null +++ b/arch/arm64/configs/sdm660-perf_defconfig @@ -0,0 +1,645 @@ +CONFIG_LOCALVERSION="-perf" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_AUDIT=y +# CONFIG_AUDITSYSCALL is not set +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_RCU_EXPERT=y +CONFIG_RCU_FAST_NO_HZ=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_CPU_MAX_BUF_SHIFT=17 +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_SCHEDTUNE=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_SCHED_HMP=y +CONFIG_SCHED_HMP_CSTATE_AWARE=y +CONFIG_SCHED_CORE_CTL=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_PID_NS is not set +CONFIG_SCHED_AUTOGROUP=y +CONFIG_SCHED_TUNE=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_MEMBARRIER is not set +CONFIG_EMBEDDED=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_PROFILING=y +CONFIG_CC_STACKPROTECTOR_REGULAR=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SIG=y +CONFIG_MODULE_SIG_FORCE=y +CONFIG_MODULE_SIG_SHA512=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_ARCH_QCOM=y +CONFIG_ARCH_SDM660=y +CONFIG_ARCH_MSMTRITON=y +CONFIG_PCI=y +CONFIG_PCI_MSM=y +CONFIG_SCHED_MC=y +CONFIG_NR_CPUS=8 +CONFIG_PREEMPT=y +CONFIG_HZ_100=y +CONFIG_ARM64_REG_REBALANCE_ON_CTX_SW=y +CONFIG_CMA=y +CONFIG_CMA_DEBUGFS=y +CONFIG_ZSMALLOC=y +CONFIG_BALANCE_ANON_FILE_RECLAIM=y +CONFIG_FORCE_ALLOC_FROM_DMA_ZONE=y +CONFIG_PROCESS_RECLAIM=y +CONFIG_SECCOMP=y +CONFIG_ARMV8_DEPRECATED=y +CONFIG_SWP_EMULATION=y +CONFIG_CP15_BARRIER_EMULATION=y +CONFIG_SETEND_EMULATION=y +# CONFIG_EFI is not set +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_COMPAT=y +CONFIG_PM_AUTOSLEEP=y +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=0 +# CONFIG_PM_WAKELOCKS_GC is not set +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_BOOST=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +CONFIG_INET_IPCOMP=y +CONFIG_INET_DIAG_DESTROY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SANE=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y +CONFIG_NETFILTER_XT_TARGET_HARDIDLETIMER=y +CONFIG_NETFILTER_XT_TARGET_LOG=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +CONFIG_NETFILTER_XT_TARGET_NOTRACK=y +CONFIG_NETFILTER_XT_TARGET_TEE=y +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +CONFIG_NETFILTER_XT_TARGET_SECMARK=y +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_DSCP=y +CONFIG_NETFILTER_XT_MATCH_ESP=y +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y +CONFIG_NETFILTER_XT_MATCH_HELPER=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +# CONFIG_NETFILTER_XT_MATCH_L2TP is not set +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_NETFILTER_XT_MATCH_POLICY=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_QTAGUID=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2=y +CONFIG_NETFILTER_XT_MATCH_SOCKET=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +CONFIG_NETFILTER_XT_MATCH_TIME=y +CONFIG_NETFILTER_XT_MATCH_U32=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_RPFILTER=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_SECURITY=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_MATCH_RPFILTER=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +CONFIG_BRIDGE_NF_EBTABLES=y +CONFIG_BRIDGE_EBT_BROUTE=y +CONFIG_L2TP=y +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=y +CONFIG_L2TP_ETH=y +CONFIG_BRIDGE=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_PRIO=y +CONFIG_NET_SCH_MULTIQ=y +CONFIG_NET_SCH_INGRESS=y +CONFIG_NET_CLS_FW=y +CONFIG_NET_CLS_U32=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_FLOW=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=y +CONFIG_NET_EMATCH_NBYTE=y +CONFIG_NET_EMATCH_U32=y +CONFIG_NET_EMATCH_META=y +CONFIG_NET_EMATCH_TEXT=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_GACT=y +CONFIG_NET_ACT_MIRRED=y +CONFIG_NET_ACT_SKBEDIT=y +CONFIG_RMNET_DATA=y +CONFIG_RMNET_DATA_FC=y +CONFIG_RMNET_DATA_DEBUG_PKT=y +CONFIG_SOCKEV_NLMCAST=y +CONFIG_BT=y +CONFIG_MSM_BT_POWER=y +CONFIG_BTFM_SLIM=y +CONFIG_BTFM_SLIM_WCN3990=y +CONFIG_CFG80211=y +CONFIG_CFG80211_INTERNAL_REGDB=y +CONFIG_RFKILL=y +CONFIG_NFC_NQ=y +CONFIG_IPC_ROUTER=y +CONFIG_IPC_ROUTER_SECURITY=y +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y +CONFIG_DMA_CMA=y +# CONFIG_PNP_DEBUG_MESSAGES is not set +CONFIG_ZRAM=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_QSEECOM=y +CONFIG_HDCP_QSEECOM=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_UFSHCD=y +CONFIG_SCSI_UFSHCD_PLATFORM=y +CONFIG_SCSI_UFS_QCOM=y +CONFIG_SCSI_UFS_QCOM_ICE=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=y +CONFIG_DM_REQ_CRYPT=y +CONFIG_DM_UEVENT=y +CONFIG_DM_VERITY=y +CONFIG_NETDEVICES=y +CONFIG_BONDING=y +CONFIG_DUMMY=y +CONFIG_TUN=y +CONFIG_SKY2=y +CONFIG_RNDIS_IPA=y +CONFIG_SMSC911X=y +CONFIG_PPP=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=y +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOE=y +CONFIG_PPPOL2TP=y +CONFIG_PPPOLAC=y +CONFIG_PPPOPNS=y +CONFIG_PPP_ASYNC=y +CONFIG_PPP_SYNC_TTY=y +CONFIG_USB_USBNET=y +CONFIG_WCNSS_MEM_PRE_ALLOC=y +CONFIG_ATH_CARDS=y +CONFIG_WIL6210=m +CONFIG_CLD_LL_CORE=y +CONFIG_QPNP_POWER_ON=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_KEYRESET=y +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_v21=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y +CONFIG_SECURE_TOUCH=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_HBTP_INPUT=y +CONFIG_INPUT_UINPUT=y +# CONFIG_SERIO_SERPORT is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVMEM is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_MSM_HS=y +CONFIG_SERIAL_MSM_SMD=y +CONFIG_DIAG_CHAR=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MSM_LEGACY=y +CONFIG_MSM_ADSPRPC=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MSM_V2=y +CONFIG_SLIMBUS_MSM_NGD=y +CONFIG_SOUNDWIRE=y +CONFIG_SPI=y +CONFIG_SPI_QUP=y +CONFIG_SPI_SPIDEV=y +CONFIG_SPMI=y +CONFIG_PINCTRL_MSM8998=y +CONFIG_PINCTRL_SDM660=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_QPNP_PIN=y +CONFIG_POWER_RESET_QCOM=y +CONFIG_QCOM_DLOAD_MODE=y +CONFIG_POWER_RESET_XGENE=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_MSM_PM=y +CONFIG_APSS_CORE_EA=y +CONFIG_MSM_APM=y +CONFIG_QPNP_SMBCHARGER=y +CONFIG_QPNP_FG_GEN3=y +CONFIG_SMB135X_CHARGER=y +CONFIG_SMB1351_USB_CHARGER=y +CONFIG_MSM_BCL_CTL=y +CONFIG_MSM_BCL_PERIPHERAL_CTL=y +CONFIG_BATTERY_BCL=y +CONFIG_QPNP_SMB2=y +CONFIG_SMB138X_CHARGER=y +CONFIG_QPNP_QNOVO=y +CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y +CONFIG_CPU_THERMAL=y +CONFIG_LIMITS_MONITOR=y +CONFIG_LIMITS_LITE_HW=y +CONFIG_THERMAL_MONITOR=y +CONFIG_THERMAL_TSENS8974=y +CONFIG_THERMAL_QPNP=y +CONFIG_THERMAL_QPNP_ADC_TM=y +CONFIG_QCOM_THERMAL_LIMITS_DCVS=y +CONFIG_MFD_SPMI_PMIC=y +CONFIG_MFD_I2C_PMIC=y +CONFIG_WCD9335_CODEC=y +CONFIG_WCD934X_CODEC=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_MSM_GFX_LDO=y +CONFIG_REGULATOR_RPM_SMD=y +CONFIG_REGULATOR_QPNP=y +CONFIG_REGULATOR_QPNP_LABIBB=y +CONFIG_REGULATOR_QPNP_LCDB=y +CONFIG_REGULATOR_SPM=y +CONFIG_REGULATOR_CPR3_HMSS=y +CONFIG_REGULATOR_CPR3_MMSS=y +CONFIG_REGULATOR_CPRH_KBSS=y +CONFIG_REGULATOR_CPR4_MMSS_LDO=y +CONFIG_REGULATOR_MEM_ACC=y +CONFIG_REGULATOR_PROXY_CONSUMER=y +CONFIG_REGULATOR_STUB=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_VIDEO_ADV_DEBUG=y +CONFIG_VIDEO_FIXED_MINOR_RANGES=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_MSM_CAMERA=y +CONFIG_MSM_CAMERA_DEBUG=y +CONFIG_MSMB_CAMERA=y +CONFIG_MSMB_CAMERA_DEBUG=y +CONFIG_MSM_CAMERA_SENSOR=y +CONFIG_MSM_CPP=y +CONFIG_MSM_CCI=y +CONFIG_MSM_CSI20_HEADER=y +CONFIG_MSM_CSI22_HEADER=y +CONFIG_MSM_CSI30_HEADER=y +CONFIG_MSM_CSI31_HEADER=y +CONFIG_MSM_CSIPHY=y +CONFIG_MSM_CSID=y +CONFIG_MSM_EEPROM=y +CONFIG_MSM_ISPIF=y +CONFIG_IMX134=y +CONFIG_IMX132=y +CONFIG_OV9724=y +CONFIG_OV5648=y +CONFIG_GC0339=y +CONFIG_OV8825=y +CONFIG_OV8865=y +CONFIG_s5k4e1=y +CONFIG_OV12830=y +CONFIG_MSM_V4L2_VIDEO_OVERLAY_DEVICE=y +CONFIG_MSMB_JPEG=y +CONFIG_MSM_FD=y +CONFIG_MSM_JPEGDMA=y +CONFIG_MSM_VIDC_V4L2=m +CONFIG_MSM_VIDC_VMEM=m +CONFIG_MSM_VIDC_GOVERNORS=m +CONFIG_MSM_SDE_ROTATOR=y +CONFIG_MSM_SDE_ROTATOR_EVTLOG_DEBUG=y +CONFIG_QCOM_KGSL=y +CONFIG_FB=y +CONFIG_FB_ARMCLCD=y +CONFIG_FB_MSM=y +CONFIG_FB_MSM_MDSS=y +CONFIG_FB_MSM_MDSS_WRITEBACK=y +CONFIG_FB_MSM_MDSS_HDMI_PANEL=y +CONFIG_FB_MSM_MDSS_DP_PANEL=y +CONFIG_FB_MSM_MDSS_XLOG_DEBUG=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_USB_AUDIO=y +CONFIG_SND_USB_AUDIO_QMI=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_MSM8998=y +CONFIG_SND_SOC_660=y +CONFIG_UHID=y +CONFIG_HID_APPLE=y +CONFIG_HID_ELECOM=y +CONFIG_HID_MAGICMOUSE=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MULTITOUCH=y +CONFIG_HID_PLANTRONICS=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3=y +CONFIG_USB_ISP1760=y +CONFIG_USB_ISP1760_HOST_ROLE=y +CONFIG_USB_PD_POLICY=y +CONFIG_QPNP_USB_PDPHY=y +CONFIG_USB_EHSET_TEST_FIXTURE=y +CONFIG_USB_OTG_WAKELOCK=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MSM_SSPHY_QMP=y +CONFIG_MSM_QUSB_PHY=y +CONFIG_DUAL_ROLE_USB_INTF=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VBUS_DRAW=500 +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_QCRNDIS=y +CONFIG_USB_CONFIGFS_RMNET_BAM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_MTP=y +CONFIG_USB_CONFIGFS_F_PTP=y +CONFIG_USB_CONFIGFS_F_ACC=y +CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y +CONFIG_USB_CONFIGFS_UEVENT=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_DIAG=y +CONFIG_USB_CONFIGFS_F_GSI=y +CONFIG_USB_CONFIGFS_F_CDEV=y +CONFIG_USB_CONFIGFS_F_QDSS=y +CONFIG_MMC=y +CONFIG_MMC_PERF_PROFILING=y +CONFIG_MMC_CLKGATE=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_TEST=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_LEDS_QPNP=y +CONFIG_LEDS_QPNP_FLASH_V2=y +CONFIG_LEDS_QPNP_WLED=y +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_SWITCH=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_QPNP=y +CONFIG_DMADEVICES=y +CONFIG_QCOM_SPS_DMA=y +CONFIG_UIO=y +CONFIG_UIO_MSM_SHAREDMEM=y +CONFIG_STAGING=y +CONFIG_ASHMEM=y +CONFIG_ANDROID_TIMED_GPIO=y +CONFIG_ANDROID_LOW_MEMORY_KILLER=y +CONFIG_ION=y +CONFIG_ION_MSM=y +CONFIG_QPNP_REVID=y +CONFIG_QPNP_COINCELL=y +CONFIG_SPS=y +CONFIG_SPS_SUPPORT_NDP_BAM=y +CONFIG_IPA=y +CONFIG_RMNET_IPA=y +CONFIG_GSI=y +CONFIG_IPA3=y +CONFIG_RMNET_IPA3=y +CONFIG_GPIO_USB_DETECT=y +CONFIG_SEEMP_CORE=y +CONFIG_USB_BAM=y +CONFIG_QCOM_CLK_SMD_RPM=y +CONFIG_MSM_GPUCC_660=y +CONFIG_MSM_MMCC_660=y +CONFIG_CLOCK_CPU_OSM=y +CONFIG_QCOM_MDSS_PLL=y +CONFIG_REMOTE_SPINLOCK_MSM=y +CONFIG_IOMMU_IO_PGTABLE_FAST=y +CONFIG_ARM_SMMU=y +CONFIG_IOMMU_DEBUG=y +CONFIG_IOMMU_DEBUG_TRACKING=y +CONFIG_IOMMU_TESTS=y +CONFIG_MSM_SMEM=y +CONFIG_QPNP_HAPTIC=y +CONFIG_MSM_SMD=y +CONFIG_MSM_GLINK=y +CONFIG_MSM_GLINK_LOOPBACK_SERVER=y +CONFIG_MSM_GLINK_SMD_XPRT=y +CONFIG_MSM_GLINK_SMEM_NATIVE_XPRT=y +CONFIG_MSM_GLINK_SPI_XPRT=y +CONFIG_MSM_SPCOM=y +CONFIG_MSM_SPSS_UTILS=y +CONFIG_MSM_SMEM_LOGGING=y +CONFIG_MSM_SMP2P=y +CONFIG_MSM_SMP2P_TEST=y +CONFIG_MSM_QMI_INTERFACE=y +CONFIG_MSM_RPM_SMD=y +CONFIG_QCOM_BUS_SCALING=y +CONFIG_MSM_SERVICE_LOCATOR=y +CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y +CONFIG_MSM_SYSMON_GLINK_COMM=y +CONFIG_MSM_IPC_ROUTER_GLINK_XPRT=y +CONFIG_MSM_GLINK_PKT=y +CONFIG_MSM_SPM=y +CONFIG_QCOM_SCM=y +CONFIG_QCOM_WATCHDOG_V2=y +CONFIG_QCOM_IRQ_HELPER=y +CONFIG_QCOM_MEMORY_DUMP_V2=y +CONFIG_ICNSS=y +CONFIG_MSM_RUN_QUEUE_STATS=y +CONFIG_MSM_BOOT_STATS=y +CONFIG_MSM_ADSP_LOADER=y +CONFIG_MSM_PERFORMANCE=y +CONFIG_MSM_SUBSYSTEM_RESTART=y +CONFIG_MSM_PIL=y +CONFIG_MSM_PIL_SSR_GENERIC=y +CONFIG_MSM_PIL_MSS_QDSP6V5=y +CONFIG_TRACER_PKT=y +CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y +CONFIG_MSM_MPM_OF=y +CONFIG_MSM_EVENT_TIMER=y +CONFIG_MSM_AVTIMER=y +CONFIG_QCOM_REMOTEQDSS=y +CONFIG_MSM_SERVICE_NOTIFIER=y +CONFIG_MSM_RPM_RBCPR_STATS_V2_LOG=y +CONFIG_MSM_RPM_LOG=y +CONFIG_MSM_RPM_STATS_LOG=y +CONFIG_QSEE_IPC_IRQ_BRIDGE=y +CONFIG_QCOM_SMCINVOKE=y +CONFIG_QCOM_EARLY_RANDOM=y +CONFIG_MEM_SHARE_QMI_SERVICE=y +CONFIG_QCOM_BIMC_BWMON=y +CONFIG_ARM_MEMLAT_MON=y +CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y +CONFIG_DEVFREQ_GOV_MEMLAT=y +CONFIG_QCOM_DEVFREQ_DEVBW=y +CONFIG_SPDM_SCM=y +CONFIG_DEVFREQ_SPDM=y +CONFIG_EXTCON=y +CONFIG_IIO=y +CONFIG_QCOM_RRADC=y +CONFIG_QCOM_TADC=y +CONFIG_PWM=y +CONFIG_PWM_QPNP=y +CONFIG_ARM_GIC_V3_ACL=y +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_MSM_TZ_LOG=y +CONFIG_SENSORS_SSC=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_EXT4_ENCRYPTION=y +CONFIG_EXT4_FS_ENCRYPTION=y +CONFIG_EXT4_FS_ICE_ENCRYPTION=y +CONFIG_FUSE_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_ECRYPT_FS=y +CONFIG_ECRYPT_FS_MESSAGING=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_INFO=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_PANIC_TIMEOUT=5 +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_IPC_LOGGING=y +CONFIG_CPU_FREQ_SWITCH_PROFILER=y +CONFIG_DEBUG_SET_MODULE_RONX=y +CONFIG_DEBUG_RODATA=y +CONFIG_DEBUG_ALIGN_RODATA=y +CONFIG_CORESIGHT=y +CONFIG_CORESIGHT_EVENT=y +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y +CONFIG_CORESIGHT_QCOM_REPLICATOR=y +CONFIG_CORESIGHT_STM=y +CONFIG_CORESIGHT_HWEVENT=y +CONFIG_CORESIGHT_CTI=y +CONFIG_CORESIGHT_TPDA=y +CONFIG_CORESIGHT_TPDM=y +CONFIG_CORESIGHT_QPDI=y +CONFIG_CORESIGHT_SOURCE_DUMMY=y +CONFIG_PFK=y +CONFIG_SECURITY=y +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SMACK=y +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_XCBC=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_DEV_QCRYPTO=y +CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y +CONFIG_CRYPTO_DEV_QCEDEV=y +CONFIG_CRYPTO_DEV_OTA_CRYPTO=y +CONFIG_CRYPTO_DEV_QCOM_ICE=y +CONFIG_ARM64_CRYPTO=y +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y +CONFIG_CRYPTO_CRC32_ARM64=y +CONFIG_QMI_ENCDEC=y diff --git a/arch/arm64/configs/sdm660_defconfig b/arch/arm64/configs/sdm660_defconfig new file mode 100644 index 000000000000..c5d93a065e87 --- /dev/null +++ b/arch/arm64/configs/sdm660_defconfig @@ -0,0 +1,712 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_AUDIT=y +# CONFIG_AUDITSYSCALL is not set +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_RCU_EXPERT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_CPU_MAX_BUF_SHIFT=17 +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_SCHEDTUNE=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +CONFIG_CGROUP_SCHED=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_SCHED_HMP=y +CONFIG_SCHED_HMP_CSTATE_AWARE=y +CONFIG_SCHED_CORE_CTL=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_PID_NS is not set +CONFIG_SCHED_TUNE=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_MEMBARRIER is not set +CONFIG_EMBEDDED=y +# CONFIG_COMPAT_BRK is not set +CONFIG_PROFILING=y +CONFIG_CC_STACKPROTECTOR_REGULAR=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SIG=y +CONFIG_MODULE_SIG_FORCE=y +CONFIG_MODULE_SIG_SHA512=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_ARCH_QCOM=y +CONFIG_ARCH_SDM660=y +CONFIG_ARCH_MSMTRITON=y +CONFIG_PCI=y +CONFIG_PCI_MSM=y +CONFIG_SCHED_MC=y +CONFIG_NR_CPUS=8 +CONFIG_PREEMPT=y +CONFIG_HZ_100=y +CONFIG_CLEANCACHE=y +CONFIG_CMA=y +CONFIG_CMA_DEBUGFS=y +CONFIG_ZSMALLOC=y +CONFIG_PROCESS_RECLAIM=y +CONFIG_SECCOMP=y +CONFIG_ARMV8_DEPRECATED=y +CONFIG_SWP_EMULATION=y +CONFIG_CP15_BARRIER_EMULATION=y +CONFIG_SETEND_EMULATION=y +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_COMPAT=y +CONFIG_PM_AUTOSLEEP=y +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=0 +# CONFIG_PM_WAKELOCKS_GC is not set +CONFIG_PM_DEBUG=y +CONFIG_CPU_FREQ=y +# CONFIG_CPU_FREQ_STAT is not set +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +CONFIG_INET_IPCOMP=y +CONFIG_INET_DIAG_DESTROY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SANE=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y +CONFIG_NETFILTER_XT_TARGET_HARDIDLETIMER=y +CONFIG_NETFILTER_XT_TARGET_LOG=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +CONFIG_NETFILTER_XT_TARGET_NOTRACK=y +CONFIG_NETFILTER_XT_TARGET_TEE=y +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +CONFIG_NETFILTER_XT_TARGET_SECMARK=y +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_DSCP=y +CONFIG_NETFILTER_XT_MATCH_ESP=y +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y +CONFIG_NETFILTER_XT_MATCH_HELPER=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +# CONFIG_NETFILTER_XT_MATCH_L2TP is not set +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_NETFILTER_XT_MATCH_POLICY=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_QTAGUID=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2=y +CONFIG_NETFILTER_XT_MATCH_SOCKET=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +CONFIG_NETFILTER_XT_MATCH_TIME=y +CONFIG_NETFILTER_XT_MATCH_U32=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_RPFILTER=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_SECURITY=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_MATCH_RPFILTER=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +CONFIG_BRIDGE_NF_EBTABLES=y +CONFIG_BRIDGE_EBT_BROUTE=y +CONFIG_L2TP=y +CONFIG_L2TP_DEBUGFS=y +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=y +CONFIG_L2TP_ETH=y +CONFIG_BRIDGE=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_PRIO=y +CONFIG_NET_SCH_MULTIQ=y +CONFIG_NET_SCH_INGRESS=y +CONFIG_NET_CLS_FW=y +CONFIG_NET_CLS_U32=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_FLOW=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=y +CONFIG_NET_EMATCH_NBYTE=y +CONFIG_NET_EMATCH_U32=y +CONFIG_NET_EMATCH_META=y +CONFIG_NET_EMATCH_TEXT=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_GACT=y +CONFIG_NET_ACT_MIRRED=y +CONFIG_NET_ACT_SKBEDIT=y +CONFIG_DNS_RESOLVER=y +CONFIG_RMNET_DATA=y +CONFIG_RMNET_DATA_FC=y +CONFIG_RMNET_DATA_DEBUG_PKT=y +CONFIG_SOCKEV_NLMCAST=y +CONFIG_BT=y +CONFIG_MSM_BT_POWER=y +CONFIG_BTFM_SLIM=y +CONFIG_BTFM_SLIM_WCN3990=y +CONFIG_CFG80211=y +CONFIG_CFG80211_INTERNAL_REGDB=y +# CONFIG_CFG80211_CRDA_SUPPORT is not set +CONFIG_RFKILL=y +CONFIG_NFC_NQ=y +CONFIG_IPC_ROUTER=y +CONFIG_IPC_ROUTER_SECURITY=y +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y +CONFIG_DMA_CMA=y +CONFIG_ZRAM=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_QSEECOM=y +CONFIG_HDCP_QSEECOM=y +CONFIG_UID_CPUTIME=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_UFSHCD=y +CONFIG_SCSI_UFSHCD_PLATFORM=y +CONFIG_SCSI_UFS_QCOM=y +CONFIG_SCSI_UFS_QCOM_ICE=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=y +CONFIG_DM_REQ_CRYPT=y +CONFIG_DM_UEVENT=y +CONFIG_DM_VERITY=y +CONFIG_NETDEVICES=y +CONFIG_BONDING=y +CONFIG_DUMMY=y +CONFIG_TUN=y +CONFIG_RNDIS_IPA=y +CONFIG_PPP=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=y +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOE=y +CONFIG_PPPOL2TP=y +CONFIG_PPPOLAC=y +CONFIG_PPPOPNS=y +CONFIG_PPP_ASYNC=y +CONFIG_PPP_SYNC_TTY=y +CONFIG_USB_USBNET=y +CONFIG_WCNSS_MEM_PRE_ALLOC=y +CONFIG_ATH_CARDS=y +CONFIG_WIL6210=m +CONFIG_CLD_LL_CORE=y +CONFIG_QPNP_POWER_ON=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_KEYRESET=y +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_JOYSTICK=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_v21=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y +CONFIG_SECURE_TOUCH=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_HBTP_INPUT=y +CONFIG_INPUT_KEYCHORD=y +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_GPIO=y +# CONFIG_SERIO_SERPORT is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y +CONFIG_SERIAL_MSM_HS=y +CONFIG_SERIAL_MSM_SMD=y +CONFIG_DIAG_CHAR=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MSM_LEGACY=y +CONFIG_MSM_ADSPRPC=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MSM_V2=y +CONFIG_SLIMBUS_MSM_NGD=y +CONFIG_SOUNDWIRE=y +CONFIG_SPI=y +CONFIG_SPI_QUP=y +CONFIG_SPI_SPIDEV=y +CONFIG_SPMI=y +CONFIG_PINCTRL_SDM660=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_QPNP_PIN=y +CONFIG_POWER_RESET_QCOM=y +CONFIG_QCOM_DLOAD_MODE=y +CONFIG_POWER_RESET_XGENE=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_MSM_PM=y +CONFIG_APSS_CORE_EA=y +CONFIG_MSM_APM=y +CONFIG_QPNP_SMBCHARGER=y +CONFIG_QPNP_FG_GEN3=y +CONFIG_SMB135X_CHARGER=y +CONFIG_SMB1351_USB_CHARGER=y +CONFIG_MSM_BCL_CTL=y +CONFIG_MSM_BCL_PERIPHERAL_CTL=y +CONFIG_BATTERY_BCL=y +CONFIG_QPNP_SMB2=y +CONFIG_SMB138X_CHARGER=y +CONFIG_QPNP_QNOVO=y +CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y +CONFIG_CPU_THERMAL=y +CONFIG_LIMITS_MONITOR=y +CONFIG_LIMITS_LITE_HW=y +CONFIG_THERMAL_MONITOR=y +CONFIG_THERMAL_TSENS8974=y +CONFIG_THERMAL_QPNP=y +CONFIG_THERMAL_QPNP_ADC_TM=y +CONFIG_QCOM_THERMAL_LIMITS_DCVS=y +CONFIG_MFD_SPMI_PMIC=y +CONFIG_MFD_I2C_PMIC=y +CONFIG_WCD9335_CODEC=y +CONFIG_WCD934X_CODEC=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_MSM_GFX_LDO=y +CONFIG_REGULATOR_RPM_SMD=y +CONFIG_REGULATOR_QPNP=y +CONFIG_REGULATOR_QPNP_LABIBB=y +CONFIG_REGULATOR_QPNP_LCDB=y +CONFIG_REGULATOR_SPM=y +CONFIG_REGULATOR_CPR3_HMSS=y +CONFIG_REGULATOR_CPR3_MMSS=y +CONFIG_REGULATOR_CPRH_KBSS=y +CONFIG_REGULATOR_CPR4_MMSS_LDO=y +CONFIG_REGULATOR_MEM_ACC=y +CONFIG_REGULATOR_PROXY_CONSUMER=y +CONFIG_REGULATOR_STUB=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_VIDEO_ADV_DEBUG=y +CONFIG_VIDEO_FIXED_MINOR_RANGES=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_MSM_CAMERA=y +CONFIG_MSM_CAMERA_DEBUG=y +CONFIG_MSMB_CAMERA=y +CONFIG_MSMB_CAMERA_DEBUG=y +CONFIG_MSM_CAMERA_SENSOR=y +CONFIG_MSM_CPP=y +CONFIG_MSM_CCI=y +CONFIG_MSM_CSI20_HEADER=y +CONFIG_MSM_CSI22_HEADER=y +CONFIG_MSM_CSI30_HEADER=y +CONFIG_MSM_CSI31_HEADER=y +CONFIG_MSM_CSIPHY=y +CONFIG_MSM_CSID=y +CONFIG_MSM_EEPROM=y +CONFIG_MSM_ISPIF=y +CONFIG_IMX134=y +CONFIG_IMX132=y +CONFIG_OV9724=y +CONFIG_OV5648=y +CONFIG_GC0339=y +CONFIG_OV8825=y +CONFIG_OV8865=y +CONFIG_s5k4e1=y +CONFIG_OV12830=y +CONFIG_MSM_V4L2_VIDEO_OVERLAY_DEVICE=y +CONFIG_MSMB_JPEG=y +CONFIG_MSM_FD=y +CONFIG_MSM_JPEGDMA=y +CONFIG_MSM_VIDC_V4L2=m +CONFIG_MSM_VIDC_VMEM=m +CONFIG_MSM_VIDC_GOVERNORS=m +CONFIG_MSM_SDE_ROTATOR=y +CONFIG_MSM_SDE_ROTATOR_EVTLOG_DEBUG=y +CONFIG_QCOM_KGSL=y +CONFIG_FB=y +CONFIG_FB_VIRTUAL=y +CONFIG_FB_MSM=y +CONFIG_FB_MSM_MDSS=y +CONFIG_FB_MSM_MDSS_WRITEBACK=y +CONFIG_FB_MSM_MDSS_HDMI_PANEL=y +CONFIG_FB_MSM_MDSS_DP_PANEL=y +CONFIG_FB_MSM_MDSS_XLOG_DEBUG=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_USB_AUDIO=y +CONFIG_SND_USB_AUDIO_QMI=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_MSM8998=y +CONFIG_SND_SOC_660=y +CONFIG_UHID=y +CONFIG_HID_APPLE=y +CONFIG_HID_ELECOM=y +CONFIG_HID_MAGICMOUSE=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MULTITOUCH=y +CONFIG_HID_PLANTRONICS=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3=y +CONFIG_USB_ISP1760=y +CONFIG_USB_ISP1760_HOST_ROLE=y +CONFIG_USB_PD_POLICY=y +CONFIG_QPNP_USB_PDPHY=y +CONFIG_USB_EHSET_TEST_FIXTURE=y +CONFIG_USB_OTG_WAKELOCK=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MSM_SSPHY_QMP=y +CONFIG_MSM_QUSB_PHY=y +CONFIG_DUAL_ROLE_USB_INTF=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VBUS_DRAW=500 +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_QCRNDIS=y +CONFIG_USB_CONFIGFS_RMNET_BAM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_MTP=y +CONFIG_USB_CONFIGFS_F_PTP=y +CONFIG_USB_CONFIGFS_F_ACC=y +CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y +CONFIG_USB_CONFIGFS_UEVENT=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_DIAG=y +CONFIG_USB_CONFIGFS_F_GSI=y +CONFIG_USB_CONFIGFS_F_CDEV=y +CONFIG_USB_CONFIGFS_F_QDSS=y +CONFIG_MMC=y +CONFIG_MMC_PERF_PROFILING=y +CONFIG_MMC_PARANOID_SD_INIT=y +CONFIG_MMC_CLKGATE=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_TEST=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_LEDS_QPNP=y +CONFIG_LEDS_QPNP_FLASH_V2=y +CONFIG_LEDS_QPNP_WLED=y +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_SWITCH=y +CONFIG_EDAC=y +CONFIG_EDAC_MM_EDAC=y +CONFIG_EDAC_CORTEX_ARM64=y +CONFIG_EDAC_CORTEX_ARM64_PANIC_ON_CE=y +CONFIG_EDAC_CORTEX_ARM64_PANIC_ON_UE=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_QPNP=y +CONFIG_DMADEVICES=y +CONFIG_QCOM_SPS_DMA=y +CONFIG_UIO=y +CONFIG_UIO_MSM_SHAREDMEM=y +CONFIG_STAGING=y +CONFIG_ASHMEM=y +CONFIG_ANDROID_TIMED_GPIO=y +CONFIG_ANDROID_LOW_MEMORY_KILLER=y +CONFIG_ION=y +CONFIG_ION_MSM=y +CONFIG_QPNP_REVID=y +CONFIG_QPNP_COINCELL=y +CONFIG_SPS=y +CONFIG_SPS_SUPPORT_NDP_BAM=y +CONFIG_IPA=y +CONFIG_RMNET_IPA=y +CONFIG_GSI=y +CONFIG_IPA3=y +CONFIG_RMNET_IPA3=y +CONFIG_GPIO_USB_DETECT=y +CONFIG_SEEMP_CORE=y +CONFIG_USB_BAM=y +CONFIG_QCOM_CLK_SMD_RPM=y +CONFIG_MSM_GPUCC_660=y +CONFIG_MSM_MMCC_660=y +CONFIG_CLOCK_CPU_OSM=y +CONFIG_QCOM_MDSS_PLL=y +CONFIG_REMOTE_SPINLOCK_MSM=y +CONFIG_IOMMU_IO_PGTABLE_FAST=y +CONFIG_IOMMU_IO_PGTABLE_FAST_SELFTEST=y +CONFIG_ARM_SMMU=y +CONFIG_IOMMU_DEBUG=y +CONFIG_IOMMU_DEBUG_TRACKING=y +CONFIG_IOMMU_TESTS=y +CONFIG_QCOM_COMMON_LOG=y +CONFIG_MSM_SMEM=y +CONFIG_QPNP_HAPTIC=y +CONFIG_MSM_SMD=y +CONFIG_MSM_SMD_DEBUG=y +CONFIG_MSM_GLINK=y +CONFIG_MSM_GLINK_LOOPBACK_SERVER=y +CONFIG_MSM_GLINK_SMD_XPRT=y +CONFIG_MSM_GLINK_SMEM_NATIVE_XPRT=y +CONFIG_MSM_GLINK_SPI_XPRT=y +CONFIG_MSM_SPCOM=y +CONFIG_MSM_SPSS_UTILS=y +CONFIG_MSM_SMEM_LOGGING=y +CONFIG_MSM_SMP2P=y +CONFIG_MSM_SMP2P_TEST=y +CONFIG_MSM_QMI_INTERFACE=y +CONFIG_MSM_RPM_SMD=y +CONFIG_QCOM_BUS_SCALING=y +CONFIG_MSM_SERVICE_LOCATOR=y +CONFIG_QCOM_DCC=y +CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y +CONFIG_MSM_SYSMON_GLINK_COMM=y +CONFIG_MSM_IPC_ROUTER_GLINK_XPRT=y +CONFIG_MSM_GLINK_PKT=y +CONFIG_MSM_SPM=y +CONFIG_QCOM_SCM=y +CONFIG_QCOM_WATCHDOG_V2=y +CONFIG_QCOM_IRQ_HELPER=y +CONFIG_QCOM_MEMORY_DUMP_V2=y +CONFIG_ICNSS=y +CONFIG_ICNSS_DEBUG=y +CONFIG_MSM_GLADIATOR_ERP_V2=y +CONFIG_PANIC_ON_GLADIATOR_ERROR_V2=y +CONFIG_MSM_GLADIATOR_HANG_DETECT=y +CONFIG_MSM_CORE_HANG_DETECT=y +CONFIG_MSM_RUN_QUEUE_STATS=y +CONFIG_MSM_BOOT_STATS=y +CONFIG_QCOM_CPUSS_DUMP=y +CONFIG_MSM_ADSP_LOADER=y +CONFIG_MSM_PERFORMANCE=y +CONFIG_MSM_SUBSYSTEM_RESTART=y +CONFIG_MSM_PIL=y +CONFIG_MSM_PIL_SSR_GENERIC=y +CONFIG_MSM_PIL_MSS_QDSP6V5=y +CONFIG_TRACER_PKT=y +CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y +CONFIG_MSM_MPM_OF=y +CONFIG_MSM_EVENT_TIMER=y +CONFIG_MSM_AVTIMER=y +CONFIG_QCOM_REMOTEQDSS=y +CONFIG_MSM_SERVICE_NOTIFIER=y +CONFIG_MSM_RPM_RBCPR_STATS_V2_LOG=y +CONFIG_MSM_RPM_LOG=y +CONFIG_MSM_RPM_STATS_LOG=y +CONFIG_QSEE_IPC_IRQ_BRIDGE=y +CONFIG_QCOM_SMCINVOKE=y +CONFIG_QCOM_EARLY_RANDOM=y +CONFIG_MEM_SHARE_QMI_SERVICE=y +CONFIG_QCOM_BIMC_BWMON=y +CONFIG_ARM_MEMLAT_MON=y +CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y +CONFIG_DEVFREQ_GOV_MEMLAT=y +CONFIG_QCOM_DEVFREQ_DEVBW=y +CONFIG_SPDM_SCM=y +CONFIG_DEVFREQ_SPDM=y +CONFIG_EXTCON=y +CONFIG_IIO=y +CONFIG_QCOM_RRADC=y +CONFIG_QCOM_TADC=y +CONFIG_PWM=y +CONFIG_PWM_QPNP=y +CONFIG_ARM_GIC_V3_ACL=y +CONFIG_PHY_XGENE=y +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_MSM_TZ_LOG=y +CONFIG_SENSORS_SSC=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_EXT4_ENCRYPTION=y +CONFIG_EXT4_FS_ENCRYPTION=y +CONFIG_EXT4_FS_ICE_ENCRYPTION=y +CONFIG_FUSE_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_EFIVAR_FS=y +CONFIG_ECRYPT_FS=y +CONFIG_ECRYPT_FS_MESSAGING=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DEBUG_INFO=y +CONFIG_PAGE_OWNER=y +CONFIG_PAGE_OWNER_ENABLE_DEFAULT=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT=y +CONFIG_SLUB_DEBUG_PANIC_ON=y +CONFIG_DEBUG_OBJECTS=y +CONFIG_DEBUG_OBJECTS_FREE=y +CONFIG_DEBUG_OBJECTS_TIMERS=y +CONFIG_DEBUG_OBJECTS_WORK=y +CONFIG_DEBUG_OBJECTS_RCU_HEAD=y +CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y +CONFIG_SLUB_DEBUG_ON=y +CONFIG_DEBUG_KMEMLEAK=y +CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=4000 +CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y +CONFIG_DEBUG_STACK_USAGE=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_WQ_WATCHDOG=y +CONFIG_PANIC_TIMEOUT=5 +CONFIG_PANIC_ON_SCHED_BUG=y +CONFIG_PANIC_ON_RT_THROTTLING=y +CONFIG_SCHEDSTATS=y +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +CONFIG_DEBUG_ATOMIC_SLEEP=y +CONFIG_DEBUG_LIST=y +CONFIG_FAULT_INJECTION=y +CONFIG_FAIL_PAGE_ALLOC=y +CONFIG_UFS_FAULT_INJECTION=y +CONFIG_FAULT_INJECTION_DEBUG_FS=y +CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y +CONFIG_IPC_LOGGING=y +CONFIG_QCOM_RTB=y +CONFIG_QCOM_RTB_SEPARATE_CPUS=y +CONFIG_FUNCTION_TRACER=y +CONFIG_IRQSOFF_TRACER=y +CONFIG_PREEMPT_TRACER=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_CPU_FREQ_SWITCH_PROFILER=y +CONFIG_MEMTEST=y +CONFIG_PANIC_ON_DATA_CORRUPTION=y +CONFIG_ARM64_PTDUMP=y +CONFIG_PID_IN_CONTEXTIDR=y +CONFIG_DEBUG_SET_MODULE_RONX=y +CONFIG_DEBUG_RODATA=y +CONFIG_FREE_PAGES_RDONLY=y +CONFIG_CORESIGHT=y +CONFIG_CORESIGHT_EVENT=y +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y +CONFIG_CORESIGHT_SOURCE_ETM4X=y +CONFIG_CORESIGHT_REMOTE_ETM=y +CONFIG_CORESIGHT_REMOTE_ETM_DEFAULT_ENABLE=0 +CONFIG_CORESIGHT_QCOM_REPLICATOR=y +CONFIG_CORESIGHT_STM=y +CONFIG_CORESIGHT_HWEVENT=y +CONFIG_CORESIGHT_CTI=y +CONFIG_CORESIGHT_TPDA=y +CONFIG_CORESIGHT_TPDM=y +CONFIG_CORESIGHT_QPDI=y +CONFIG_CORESIGHT_SOURCE_DUMMY=y +CONFIG_PFK=y +CONFIG_SECURITY=y +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SMACK=y +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_XCBC=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_DEV_QCRYPTO=y +CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y +CONFIG_CRYPTO_DEV_QCEDEV=y +CONFIG_CRYPTO_DEV_OTA_CRYPTO=y +CONFIG_CRYPTO_DEV_QCOM_ICE=y +CONFIG_ARM64_CRYPTO=y +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y +CONFIG_CRYPTO_CRC32_ARM64=y +CONFIG_XZ_DEC=y +CONFIG_QMI_ENCDEC=y diff --git a/drivers/clk/msm/Kconfig b/drivers/clk/msm/Kconfig index bfb697347ec5..3829f6aec124 100644 --- a/drivers/clk/msm/Kconfig +++ b/drivers/clk/msm/Kconfig @@ -7,7 +7,7 @@ config COMMON_CLK_MSM This support clock controller used by MSM devices which support global, mmss and gpu clock controller. Say Y if you want to support the clocks exposed by the MSM on - platforms such as msm8996, msm8998, msmfalcon etc. + platforms such as msm8996, msm8998 etc. config MSM_CLK_CONTROLLER_V2 bool "QTI clock driver" diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index b5dd556b3f96..5a6b62892328 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -153,33 +153,33 @@ config MSM_MMCC_8996 Say Y if you want to support multimedia devices such as display, graphics, video encode/decode, camera, etc. -config MSM_GCC_FALCON - tristate "MSMFALCON Global Clock Controller" +config MSM_GCC_660 + tristate "SDM660 Global Clock Controller" select QCOM_GDSC depends on COMMON_CLK_QCOM ---help--- Support for the global clock controller on Qualcomm Technologies, Inc - MSMfalcon devices. + SDM660 devices. Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, UFS, SD/eMMC, PCIe, etc. -config MSM_GPUCC_FALCON - tristate "MSMFALCON Graphics Clock Controller" - select MSM_GCC_FALCON +config MSM_GPUCC_660 + tristate "SDM660 Graphics Clock Controller" + select MSM_GCC_660 depends on COMMON_CLK_QCOM help Support for the graphics clock controller on Qualcomm Technologies, Inc - MSMfalcon devices. + SDM660 devices. Say Y if you want to support graphics controller devices which will be required to enable those device. -config MSM_MMCC_FALCON - tristate "MSMFALCON Multimedia Clock Controller" - select MSM_GCC_FALCON +config MSM_MMCC_660 + tristate "SDM660 Multimedia Clock Controller" + select MSM_GCC_660 depends on COMMON_CLK_QCOM help Support for the multimedia clock controller on Qualcomm Technologies, Inc - MSMfalcon devices. + SDM660 devices. Say Y if you want to support multimedia devices such as display, video encode/decode, camera, etc. diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index a63065c97319..481cda67974b 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -25,12 +25,12 @@ obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o -obj-$(CONFIG_MSM_GCC_FALCON) += gcc-msmfalcon.o +obj-$(CONFIG_MSM_GCC_660) += gcc-sdm660.o obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o -obj-$(CONFIG_MSM_GPUCC_FALCON) += gpucc-msmfalcon.o -obj-$(CONFIG_MSM_MMCC_FALCON) += mmcc-msmfalcon.o +obj-$(CONFIG_MSM_GPUCC_660) += gpucc-sdm660.o +obj-$(CONFIG_MSM_MMCC_660) += mmcc-sdm660.o obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o obj-$(CONFIG_QCOM_HFPLL) += hfpll.o obj-$(CONFIG_KRAITCC) += krait-cc.o diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index d14c32bffe14..9332e99e642b 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -656,75 +656,75 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { .num_clks = ARRAY_SIZE(msm8996_clks), }; -/* msmfalcon */ -DEFINE_CLK_SMD_RPM_BRANCH(msmfalcon, cxo, cxo_a, QCOM_SMD_RPM_MISC_CLK, 0, +/* sdm660 */ +DEFINE_CLK_SMD_RPM_BRANCH(sdm660, cxo, cxo_a, QCOM_SMD_RPM_MISC_CLK, 0, 19200000); -DEFINE_CLK_SMD_RPM(msmfalcon, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); -DEFINE_CLK_SMD_RPM(msmfalcon, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); -DEFINE_CLK_SMD_RPM(msmfalcon, cnoc_periph_clk, cnoc_periph_a_clk, +DEFINE_CLK_SMD_RPM(sdm660, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); +DEFINE_CLK_SMD_RPM(sdm660, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); +DEFINE_CLK_SMD_RPM(sdm660, cnoc_periph_clk, cnoc_periph_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); -DEFINE_CLK_SMD_RPM(msmfalcon, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); -DEFINE_CLK_SMD_RPM(msmfalcon, mmssnoc_axi_clk, mmssnoc_axi_a_clk, +DEFINE_CLK_SMD_RPM(sdm660, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); +DEFINE_CLK_SMD_RPM(sdm660, mmssnoc_axi_clk, mmssnoc_axi_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 0); -DEFINE_CLK_SMD_RPM(msmfalcon, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); -DEFINE_CLK_SMD_RPM(msmfalcon, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); -DEFINE_CLK_SMD_RPM(msmfalcon, aggre2_noc_clk, aggre2_noc_a_clk, +DEFINE_CLK_SMD_RPM(sdm660, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); +DEFINE_CLK_SMD_RPM(sdm660, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); +DEFINE_CLK_SMD_RPM(sdm660, aggre2_noc_clk, aggre2_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 2); -DEFINE_CLK_SMD_RPM_QDSS(msmfalcon, qdss_clk, qdss_a_clk, +DEFINE_CLK_SMD_RPM_QDSS(sdm660, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, rf_clk1, rf_clk1_ao, 4); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, div_clk1, div_clk1_ao, 0xb); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, ln_bb_clk1, ln_bb_clk1_ao, 0x1); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, ln_bb_clk2, ln_bb_clk2_ao, 0x2); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, ln_bb_clk3, ln_bb_clk3_ao, 0x3); - -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, rf_clk1_pin, rf_clk1_ao_pin, 4); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk1_pin, +DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, rf_clk1, rf_clk1_ao, 4); +DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, div_clk1, div_clk1_ao, 0xb); +DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk1, ln_bb_clk1_ao, 0x1); +DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk2, ln_bb_clk2_ao, 0x2); +DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_ao, 0x3); + +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, rf_clk1_pin, rf_clk1_ao_pin, 4); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk1_pin, ln_bb_clk1_pin_ao, 0x1); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk2_pin, +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk2_pin, ln_bb_clk2_pin_ao, 0x2); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk3_pin, +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin, ln_bb_clk3_pin_ao, 0x3); -static struct clk_hw *msmfalcon_clks[] = { - [RPM_XO_CLK_SRC] = &msmfalcon_cxo.hw, - [RPM_XO_A_CLK_SRC] = &msmfalcon_cxo_a.hw, - [RPM_SNOC_CLK] = &msmfalcon_snoc_clk.hw, - [RPM_SNOC_A_CLK] = &msmfalcon_snoc_a_clk.hw, - [RPM_BIMC_CLK] = &msmfalcon_bimc_clk.hw, - [RPM_BIMC_A_CLK] = &msmfalcon_bimc_a_clk.hw, - [RPM_QDSS_CLK] = &msmfalcon_qdss_clk.hw, - [RPM_QDSS_A_CLK] = &msmfalcon_qdss_a_clk.hw, - [RPM_RF_CLK1] = &msmfalcon_rf_clk1.hw, - [RPM_RF_CLK1_A] = &msmfalcon_rf_clk1_ao.hw, - [RPM_RF_CLK1_PIN] = &msmfalcon_rf_clk1_pin.hw, - [RPM_RF_CLK1_A_PIN] = &msmfalcon_rf_clk1_ao_pin.hw, - [RPM_AGGR2_NOC_CLK] = &msmfalcon_aggre2_noc_clk.hw, - [RPM_AGGR2_NOC_A_CLK] = &msmfalcon_aggre2_noc_a_clk.hw, - [RPM_CNOC_CLK] = &msmfalcon_cnoc_clk.hw, - [RPM_CNOC_A_CLK] = &msmfalcon_cnoc_a_clk.hw, - [RPM_IPA_CLK] = &msmfalcon_ipa_clk.hw, - [RPM_IPA_A_CLK] = &msmfalcon_ipa_a_clk.hw, - [RPM_CE1_CLK] = &msmfalcon_ce1_clk.hw, - [RPM_CE1_A_CLK] = &msmfalcon_ce1_a_clk.hw, - [RPM_DIV_CLK1] = &msmfalcon_div_clk1.hw, - [RPM_DIV_CLK1_AO] = &msmfalcon_div_clk1_ao.hw, - [RPM_LN_BB_CLK1] = &msmfalcon_ln_bb_clk1.hw, - [RPM_LN_BB_CLK1] = &msmfalcon_ln_bb_clk1_ao.hw, - [RPM_LN_BB_CLK1_PIN] = &msmfalcon_ln_bb_clk1_pin.hw, - [RPM_LN_BB_CLK1_PIN_AO] = &msmfalcon_ln_bb_clk1_pin_ao.hw, - [RPM_LN_BB_CLK2] = &msmfalcon_ln_bb_clk2.hw, - [RPM_LN_BB_CLK2_AO] = &msmfalcon_ln_bb_clk2_ao.hw, - [RPM_LN_BB_CLK2_PIN] = &msmfalcon_ln_bb_clk2_pin.hw, - [RPM_LN_BB_CLK2_PIN_AO] = &msmfalcon_ln_bb_clk2_pin_ao.hw, - [RPM_LN_BB_CLK3] = &msmfalcon_ln_bb_clk3.hw, - [RPM_LN_BB_CLK3_AO] = &msmfalcon_ln_bb_clk3_ao.hw, - [RPM_LN_BB_CLK3_PIN] = &msmfalcon_ln_bb_clk3_pin.hw, - [RPM_LN_BB_CLK3_PIN_AO] = &msmfalcon_ln_bb_clk3_pin_ao.hw, - [RPM_CNOC_PERIPH_CLK] = &msmfalcon_cnoc_periph_clk.hw, - [RPM_CNOC_PERIPH_A_CLK] = &msmfalcon_cnoc_periph_a_clk.hw, - [MMSSNOC_AXI_CLK] = &msmfalcon_mmssnoc_axi_clk.hw, - [MMSSNOC_AXI_A_CLK] = &msmfalcon_mmssnoc_axi_a_clk.hw, +static struct clk_hw *sdm660_clks[] = { + [RPM_XO_CLK_SRC] = &sdm660_cxo.hw, + [RPM_XO_A_CLK_SRC] = &sdm660_cxo_a.hw, + [RPM_SNOC_CLK] = &sdm660_snoc_clk.hw, + [RPM_SNOC_A_CLK] = &sdm660_snoc_a_clk.hw, + [RPM_BIMC_CLK] = &sdm660_bimc_clk.hw, + [RPM_BIMC_A_CLK] = &sdm660_bimc_a_clk.hw, + [RPM_QDSS_CLK] = &sdm660_qdss_clk.hw, + [RPM_QDSS_A_CLK] = &sdm660_qdss_a_clk.hw, + [RPM_RF_CLK1] = &sdm660_rf_clk1.hw, + [RPM_RF_CLK1_A] = &sdm660_rf_clk1_ao.hw, + [RPM_RF_CLK1_PIN] = &sdm660_rf_clk1_pin.hw, + [RPM_RF_CLK1_A_PIN] = &sdm660_rf_clk1_ao_pin.hw, + [RPM_AGGR2_NOC_CLK] = &sdm660_aggre2_noc_clk.hw, + [RPM_AGGR2_NOC_A_CLK] = &sdm660_aggre2_noc_a_clk.hw, + [RPM_CNOC_CLK] = &sdm660_cnoc_clk.hw, + [RPM_CNOC_A_CLK] = &sdm660_cnoc_a_clk.hw, + [RPM_IPA_CLK] = &sdm660_ipa_clk.hw, + [RPM_IPA_A_CLK] = &sdm660_ipa_a_clk.hw, + [RPM_CE1_CLK] = &sdm660_ce1_clk.hw, + [RPM_CE1_A_CLK] = &sdm660_ce1_a_clk.hw, + [RPM_DIV_CLK1] = &sdm660_div_clk1.hw, + [RPM_DIV_CLK1_AO] = &sdm660_div_clk1_ao.hw, + [RPM_LN_BB_CLK1] = &sdm660_ln_bb_clk1.hw, + [RPM_LN_BB_CLK1] = &sdm660_ln_bb_clk1_ao.hw, + [RPM_LN_BB_CLK1_PIN] = &sdm660_ln_bb_clk1_pin.hw, + [RPM_LN_BB_CLK1_PIN_AO] = &sdm660_ln_bb_clk1_pin_ao.hw, + [RPM_LN_BB_CLK2] = &sdm660_ln_bb_clk2.hw, + [RPM_LN_BB_CLK2_AO] = &sdm660_ln_bb_clk2_ao.hw, + [RPM_LN_BB_CLK2_PIN] = &sdm660_ln_bb_clk2_pin.hw, + [RPM_LN_BB_CLK2_PIN_AO] = &sdm660_ln_bb_clk2_pin_ao.hw, + [RPM_LN_BB_CLK3] = &sdm660_ln_bb_clk3.hw, + [RPM_LN_BB_CLK3_AO] = &sdm660_ln_bb_clk3_ao.hw, + [RPM_LN_BB_CLK3_PIN] = &sdm660_ln_bb_clk3_pin.hw, + [RPM_LN_BB_CLK3_PIN_AO] = &sdm660_ln_bb_clk3_pin_ao.hw, + [RPM_CNOC_PERIPH_CLK] = &sdm660_cnoc_periph_clk.hw, + [RPM_CNOC_PERIPH_A_CLK] = &sdm660_cnoc_periph_a_clk.hw, + [MMSSNOC_AXI_CLK] = &sdm660_mmssnoc_axi_clk.hw, + [MMSSNOC_AXI_A_CLK] = &sdm660_mmssnoc_axi_a_clk.hw, /* Voter Clocks */ [BIMC_MSMBUS_CLK] = &bimc_msmbus_clk.hw, @@ -746,16 +746,16 @@ static struct clk_hw *msmfalcon_clks[] = { [CNOC_PERIPH_KEEPALIVE_A_CLK] = &cnoc_periph_keepalive_a_clk.hw, }; -static const struct rpm_smd_clk_desc rpm_clk_msmfalcon = { - .clks = msmfalcon_clks, +static const struct rpm_smd_clk_desc rpm_clk_sdm660 = { + .clks = sdm660_clks, .num_rpm_clks = RPM_CNOC_PERIPH_A_CLK, - .num_clks = ARRAY_SIZE(msmfalcon_clks), + .num_clks = ARRAY_SIZE(sdm660_clks), }; static const struct of_device_id rpm_smd_clk_match_table[] = { { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916}, { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996}, - { .compatible = "qcom,rpmcc-msmfalcon", .data = &rpm_clk_msmfalcon}, + { .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660}, { } }; MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table); @@ -766,21 +766,21 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) struct clk *clk; struct rpm_cc *rcc; struct clk_onecell_data *data; - int ret, is_8996 = 0, is_falcon = 0; + int ret, is_8996 = 0, is_660 = 0; size_t num_clks, i; struct clk_hw **hw_clks; const struct rpm_smd_clk_desc *desc; is_8996 = of_device_is_compatible(pdev->dev.of_node, "qcom,rpmcc-msm8996"); - is_falcon = of_device_is_compatible(pdev->dev.of_node, - "qcom,rpmcc-msmfalcon"); + is_660 = of_device_is_compatible(pdev->dev.of_node, + "qcom,rpmcc-sdm660"); if (is_8996) { ret = clk_vote_bimc(&msm8996_bimc_clk.hw, INT_MAX); if (ret < 0) return ret; - } else if (is_falcon) { - ret = clk_vote_bimc(&msmfalcon_bimc_clk.hw, INT_MAX); + } else if (is_660) { + ret = clk_vote_bimc(&sdm660_bimc_clk.hw, INT_MAX); if (ret < 0) return ret; } @@ -849,8 +849,8 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) clk_prepare_enable(pnoc_keepalive_a_clk.hw.clk); clk_prepare_enable(mmssnoc_a_clk_cpu_vote.hw.clk); - } else if (is_falcon) { - clk_prepare_enable(msmfalcon_cxo_a.hw.clk); + } else if (is_660) { + clk_prepare_enable(sdm660_cxo_a.hw.clk); /* Hold an active set vote for the cnoc_periph resource */ clk_set_rate(cnoc_periph_keepalive_a_clk.hw.clk, 19200000); diff --git a/drivers/clk/qcom/gcc-msmfalcon.c b/drivers/clk/qcom/gcc-msmfalcon.c deleted file mode 100644 index 1e1c871ef22c..000000000000 --- a/drivers/clk/qcom/gcc-msmfalcon.c +++ /dev/null @@ -1,3322 +0,0 @@ -/* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "clk-alpha-pll.h" -#include "clk-branch.h" -#include "common.h" -#include "clk-pll.h" -#include "clk-regmap.h" -#include "clk-rcg.h" -#include "reset.h" -#include "vdd-level-falcon.h" - -#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } - -static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner); -static DEFINE_VDD_REGULATORS(vdd_dig_ao, VDD_DIG_NUM, 1, vdd_corner); - -enum { - P_CORE_BI_PLL_TEST_SE, - P_GPLL0_OUT_MAIN, - P_GPLL1_OUT_MAIN, - P_GPLL4_OUT_MAIN, - P_PLL0_EARLY_DIV_CLK_SRC, - P_PLL1_EARLY_DIV_CLK_SRC, - P_SLEEP_CLK, - P_XO, -}; - -static const struct parent_map gcc_parent_map_0[] = { - { P_XO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gcc_parent_names_0[] = { - "xo", - "gpll0_out_main", - "gpll0_out_early_div", - "core_bi_pll_test_se", -}; - -static const struct parent_map gcc_parent_map_1[] = { - { P_XO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gcc_parent_names_1[] = { - "xo", - "gpll0_out_main", - "core_bi_pll_test_se", -}; - -static const struct parent_map gcc_parent_map_2[] = { - { P_XO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_SLEEP_CLK, 5 }, - { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gcc_parent_names_2[] = { - "xo", - "gpll0_out_main", - "core_pi_sleep_clk", - "gpll0_out_early_div", - "core_bi_pll_test_se", -}; - -static const struct parent_map gcc_parent_map_3[] = { - { P_XO, 0 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gcc_parent_names_3[] = { - "xo", - "core_bi_pll_test_se", -}; - -static const struct parent_map gcc_parent_map_4[] = { - { P_XO, 0 }, - { P_SLEEP_CLK, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gcc_parent_names_4[] = { - "xo", - "core_pi_sleep_clk", - "core_bi_pll_test_se", -}; - -static const struct parent_map gcc_parent_map_5[] = { - { P_XO, 0 }, - { P_GPLL4_OUT_MAIN, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gcc_parent_names_5[] = { - "xo", - "gpll4_out_main", - "core_bi_pll_test_se", -}; - -static const struct parent_map gcc_parent_map_6[] = { - { P_XO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_PLL0_EARLY_DIV_CLK_SRC, 3 }, - { P_GPLL1_OUT_MAIN, 4 }, - { P_GPLL4_OUT_MAIN, 5 }, - { P_PLL1_EARLY_DIV_CLK_SRC, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gcc_parent_names_6[] = { - "xo", - "gpll0_out_main", - "gpll0_out_early_div", - "gpll1_out_main", - "gpll4_out_main", - "gpll1_out_early_div", - "core_bi_pll_test_se", -}; - -static const struct parent_map gcc_parent_map_7[] = { - { P_XO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL4_OUT_MAIN, 5 }, - { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gcc_parent_names_7[] = { - "xo", - "gpll0_out_main", - "gpll4_out_main", - "gpll0_out_early_div", - "core_bi_pll_test_se", -}; - -static const struct parent_map gcc_parent_map_8[] = { - { P_XO, 0 }, - { P_GPLL0_OUT_MAIN, 1 }, - { P_PLL0_EARLY_DIV_CLK_SRC, 2 }, - { P_GPLL4_OUT_MAIN, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gcc_parent_names_8[] = { - "xo", - "gpll0_out_main", - "gpll0_out_early_div", - "gpll4_out_main", - "core_bi_pll_test_se", -}; - -static struct clk_fixed_factor xo = { - .mult = 1, - .div = 1, - .hw.init = &(struct clk_init_data){ - .name = "xo", - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, - .ops = &clk_fixed_factor_ops, - }, -}; - -static struct clk_alpha_pll gpll0_out_main = { - .offset = 0x0, - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpll0_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - }, - }, -}; - -static struct clk_fixed_factor gpll0_out_early_div = { - .mult = 1, - .div = 2, - .hw.init = &(struct clk_init_data){ - .name = "gpll0_out_early_div", - .parent_names = (const char *[]){ "gpll0_out_main" }, - .num_parents = 1, - .ops = &clk_fixed_factor_ops, - }, -}; - -static struct clk_alpha_pll gpll1_out_main = { - .offset = 0x1000, - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gpll1_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - }, - }, -}; - -static struct clk_fixed_factor gpll1_out_early_div = { - .mult = 1, - .div = 2, - .hw.init = &(struct clk_init_data){ - .name = "gpll1_out_early_div", - .parent_names = (const char *[]){ "gpll1_out_main" }, - .num_parents = 1, - .ops = &clk_fixed_factor_ops, - }, -}; - -static struct clk_alpha_pll gpll4_out_main = { - .offset = 0x77000, - .clkr = { - .enable_reg = 0x52000, - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gpll4_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - }, - }, -}; - -static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = { - F(19200000, P_XO, 1, 0, 0), - F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), - { } -}; - -static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { - .cmd_rcgr = 0x19020, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp1_qup1_i2c_apps_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 19200000, - LOW, 50000000), - }, -}; - -static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = { - F(960000, P_XO, 10, 1, 2), - F(4800000, P_XO, 4, 0, 0), - F(9600000, P_XO, 2, 0, 0), - F(15000000, P_GPLL0_OUT_MAIN, 10, 1, 4), - F(19200000, P_XO, 1, 0, 0), - F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), - F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), - { } -}; - -static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { - .cmd_rcgr = 0x1900c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp1_qup1_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 25000000, - NOMINAL, 50000000), - }, -}; - -static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { - .cmd_rcgr = 0x1b020, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp1_qup2_i2c_apps_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 19200000, - LOW, 50000000), - }, -}; - -static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { - .cmd_rcgr = 0x1b00c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp1_qup2_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 25000000, - NOMINAL, 50000000), - }, -}; - -static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { - .cmd_rcgr = 0x1d020, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp1_qup3_i2c_apps_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 19200000, - LOW, 50000000), - }, -}; - -static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { - .cmd_rcgr = 0x1d00c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp1_qup3_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 25000000, - NOMINAL, 50000000), - }, -}; - -static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { - .cmd_rcgr = 0x1f020, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp1_qup4_i2c_apps_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 19200000, - LOW, 50000000), - }, -}; - -static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { - .cmd_rcgr = 0x1f00c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp1_qup4_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 25000000, - NOMINAL, 50000000), - }, -}; - -static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = { - F(3686400, P_GPLL0_OUT_MAIN, 1, 96, 15625), - F(7372800, P_GPLL0_OUT_MAIN, 1, 192, 15625), - F(14745600, P_GPLL0_OUT_MAIN, 1, 384, 15625), - F(16000000, P_GPLL0_OUT_MAIN, 5, 2, 15), - F(19200000, P_XO, 1, 0, 0), - F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5), - F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75), - F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0), - F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375), - F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), - F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375), - F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75), - F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625), - F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), - F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0), - { } -}; - -static struct clk_rcg2 blsp1_uart1_apps_clk_src = { - .cmd_rcgr = 0x1a00c, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp1_uart1_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 31578947, - NOMINAL, 63157895), - }, -}; - -static struct clk_rcg2 blsp1_uart2_apps_clk_src = { - .cmd_rcgr = 0x1c00c, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp1_uart2_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 31578947, - NOMINAL, 63157895), - }, -}; - -static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { - .cmd_rcgr = 0x26020, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp2_qup1_i2c_apps_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 19200000, - LOW, 50000000), - }, -}; - -static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { - .cmd_rcgr = 0x2600c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp2_qup1_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 25000000, - NOMINAL, 50000000), - }, -}; - -static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { - .cmd_rcgr = 0x28020, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp2_qup2_i2c_apps_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 19200000, - LOW, 50000000), - }, -}; - -static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { - .cmd_rcgr = 0x2800c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp2_qup2_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 25000000, - NOMINAL, 50000000), - }, -}; - -static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { - .cmd_rcgr = 0x2a020, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp2_qup3_i2c_apps_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 19200000, - LOW, 50000000), - }, -}; - -static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { - .cmd_rcgr = 0x2a00c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp2_qup3_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 25000000, - NOMINAL, 50000000), - }, -}; - -static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { - .cmd_rcgr = 0x2c020, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp2_qup4_i2c_apps_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 19200000, - LOW, 50000000), - }, -}; - -static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { - .cmd_rcgr = 0x2c00c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp2_qup4_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 25000000, - NOMINAL, 50000000), - }, -}; - -static struct clk_rcg2 blsp2_uart1_apps_clk_src = { - .cmd_rcgr = 0x2700c, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp2_uart1_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 31578947, - NOMINAL, 63157895), - }, -}; - -static struct clk_rcg2 blsp2_uart2_apps_clk_src = { - .cmd_rcgr = 0x2900c, - .mnd_width = 16, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "blsp2_uart2_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 31578947, - NOMINAL, 63157895), - }, -}; - -static const struct freq_tbl ftbl_gp1_clk_src[] = { - F(19200000, P_XO, 1, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - { } -}; - -static struct clk_rcg2 gp1_clk_src = { - .cmd_rcgr = 0x64004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gp1_clk_src", - .parent_names = gcc_parent_names_2, - .num_parents = 5, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 50000000, - LOW, 100000000, - NOMINAL, 200000000), - }, -}; - -static struct clk_rcg2 gp2_clk_src = { - .cmd_rcgr = 0x65004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gp2_clk_src", - .parent_names = gcc_parent_names_2, - .num_parents = 5, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 50000000, - LOW, 100000000, - NOMINAL, 200000000), - }, -}; - -static struct clk_rcg2 gp3_clk_src = { - .cmd_rcgr = 0x66004, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_2, - .freq_tbl = ftbl_gp1_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gp3_clk_src", - .parent_names = gcc_parent_names_2, - .num_parents = 5, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 50000000, - LOW, 100000000, - NOMINAL, 200000000), - }, -}; - -static const struct freq_tbl ftbl_hmss_ahb_clk_src[] = { - F(19200000, P_XO, 1, 0, 0), - F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0), - F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - { } -}; - -static struct clk_rcg2 hmss_ahb_clk_src = { - .cmd_rcgr = 0x48014, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_hmss_ahb_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "hmss_ahb_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3_AO( - LOWER, 19200000, - LOW, 50000000, - NOMINAL, 100000000), - }, -}; - -static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] = { - F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0), - { } -}; - -static struct clk_rcg2 hmss_gpll0_clk_src = { - .cmd_rcgr = 0x4805c, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_hmss_gpll0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "hmss_gpll0_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP1_AO( - LOWER, 600000000), - }, -}; - -static const struct freq_tbl ftbl_hmss_gpll4_clk_src[] = { - F(384000000, P_GPLL4_OUT_MAIN, 4, 0, 0), - F(768000000, P_GPLL4_OUT_MAIN, 2, 0, 0), - F(1536000000, P_GPLL4_OUT_MAIN, 1, 0, 0), - { } -}; - -static struct clk_rcg2 hmss_gpll4_clk_src = { - .cmd_rcgr = 0x48074, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_5, - .freq_tbl = ftbl_hmss_gpll4_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "hmss_gpll4_clk_src", - .parent_names = gcc_parent_names_5, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3_AO( - LOWER, 400000000, - LOW, 800000000, - NOMINAL, 1600000000), - }, -}; - -static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = { - F(19200000, P_XO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 hmss_rbcpr_clk_src = { - .cmd_rcgr = 0x48044, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_hmss_rbcpr_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "hmss_rbcpr_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 19200000, - NOMINAL, 50000000), - }, -}; - -static const struct freq_tbl ftbl_pdm2_clk_src[] = { - F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), - { } -}; - -static struct clk_rcg2 pdm2_clk_src = { - .cmd_rcgr = 0x33010, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_1, - .freq_tbl = ftbl_pdm2_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "pdm2_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 19200000, - LOW, 60000000), - }, -}; - -static const struct freq_tbl ftbl_qspi_ser_clk_src[] = { - F(19200000, P_XO, 1, 0, 0), - F(80200000, P_PLL1_EARLY_DIV_CLK_SRC, 5, 0, 0), - F(160400000, P_GPLL1_OUT_MAIN, 5, 0, 0), - F(267333333, P_GPLL1_OUT_MAIN, 3, 0, 0), - { } -}; - -static struct clk_rcg2 qspi_ser_clk_src = { - .cmd_rcgr = 0x4d00c, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_6, - .freq_tbl = ftbl_qspi_ser_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "qspi_ser_clk_src", - .parent_names = gcc_parent_names_6, - .num_parents = 7, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 80200000, - LOW, 160400000, - NOMINAL, 267333333), - }, -}; - -static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = { - F(144000, P_XO, 16, 3, 25), - F(400000, P_XO, 12, 1, 4), - F(20000000, P_PLL0_EARLY_DIV_CLK_SRC, 5, 1, 3), - F(25000000, P_PLL0_EARLY_DIV_CLK_SRC, 6, 1, 2), - F(50000000, P_PLL0_EARLY_DIV_CLK_SRC, 6, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - F(192000000, P_GPLL4_OUT_MAIN, 8, 0, 0), - F(384000000, P_GPLL4_OUT_MAIN, 4, 0, 0), - { } -}; - -static struct clk_rcg2 sdcc1_apps_clk_src = { - .cmd_rcgr = 0x1602c, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_7, - .freq_tbl = ftbl_sdcc1_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "sdcc1_apps_clk_src", - .parent_names = gcc_parent_names_7, - .num_parents = 5, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 50000000, - LOW, 100000000, - NOMINAL, 400000000), - }, -}; - -static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = { - F(75000000, P_PLL0_EARLY_DIV_CLK_SRC, 4, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 sdcc1_ice_core_clk_src = { - .cmd_rcgr = 0x16010, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_sdcc1_ice_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "sdcc1_ice_core_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 75000000, - LOW, 150000000, - NOMINAL, 300000000), - }, -}; - -static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = { - F(144000, P_XO, 16, 3, 25), - F(400000, P_XO, 12, 1, 4), - F(20000000, P_PLL0_EARLY_DIV_CLK_SRC, 5, 1, 3), - F(25000000, P_PLL0_EARLY_DIV_CLK_SRC, 6, 1, 2), - F(50000000, P_PLL0_EARLY_DIV_CLK_SRC, 6, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - F(192000000, P_GPLL4_OUT_MAIN, 8, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - { } -}; - -static struct clk_rcg2 sdcc2_apps_clk_src = { - .cmd_rcgr = 0x14010, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_8, - .freq_tbl = ftbl_sdcc2_apps_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "sdcc2_apps_clk_src", - .parent_names = gcc_parent_names_8, - .num_parents = 5, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 50000000, - LOW, 100000000, - NOMINAL, 200000000), - }, -}; - -static const struct freq_tbl ftbl_ufs_axi_clk_src[] = { - F(50000000, P_PLL0_EARLY_DIV_CLK_SRC, 6, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), - { } -}; - -static struct clk_rcg2 ufs_axi_clk_src = { - .cmd_rcgr = 0x75018, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_ufs_axi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "ufs_axi_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP5( - LOWER, 50000000, - LOW, 100000000, - LOW_L1, 150000000, - NOMINAL, 200000000, - HIGH, 240000000), - }, -}; - -static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = { - F(75000000, P_PLL0_EARLY_DIV_CLK_SRC, 4, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 ufs_ice_core_clk_src = { - .cmd_rcgr = 0x76010, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_ufs_ice_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "ufs_ice_core_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 75000000, - LOW, 150000000, - NOMINAL, 300000000), - }, -}; - -static struct clk_rcg2 ufs_phy_aux_clk_src = { - .cmd_rcgr = 0x76044, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_3, - .freq_tbl = ftbl_hmss_rbcpr_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "ufs_phy_aux_clk_src", - .parent_names = gcc_parent_names_3, - .num_parents = 2, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP1( - LOWER, 19200000), - }, -}; - -static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = { - F(37500000, P_PLL0_EARLY_DIV_CLK_SRC, 8, 0, 0), - F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - { } -}; - -static struct clk_rcg2 ufs_unipro_core_clk_src = { - .cmd_rcgr = 0x76028, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_ufs_unipro_core_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "ufs_unipro_core_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 37500000, - LOW, 75000000, - NOMINAL, 150000000), - }, -}; - -static const struct freq_tbl ftbl_usb20_master_clk_src[] = { - F(19200000, P_XO, 1, 0, 0), - F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), - F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), - { } -}; - -static struct clk_rcg2 usb20_master_clk_src = { - .cmd_rcgr = 0x2f010, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_usb20_master_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "usb20_master_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 60000000, - NOMINAL, 120000000), - }, -}; - -static const struct freq_tbl ftbl_usb20_mock_utmi_clk_src[] = { - F(19200000, P_XO, 1, 0, 0), - F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), - { } -}; - -static struct clk_rcg2 usb20_mock_utmi_clk_src = { - .cmd_rcgr = 0x2f024, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_usb20_mock_utmi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "usb20_mock_utmi_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 19200000, - LOW, 60000000), - }, -}; - -static const struct freq_tbl ftbl_usb30_master_clk_src[] = { - F(19200000, P_XO, 1, 0, 0), - F(66666667, P_PLL0_EARLY_DIV_CLK_SRC, 4.5, 0, 0), - F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), - F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), - { } -}; - -static struct clk_rcg2 usb30_master_clk_src = { - .cmd_rcgr = 0xf014, - .mnd_width = 8, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_usb30_master_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "usb30_master_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP4( - LOWER, 66666667, - LOW, 133333333, - NOMINAL, 200000000, - HIGH, 240000000), - }, -}; - -static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = { - F(40000000, P_PLL0_EARLY_DIV_CLK_SRC, 7.5, 0, 0), - F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), - { } -}; - -static struct clk_rcg2 usb30_mock_utmi_clk_src = { - .cmd_rcgr = 0xf028, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_0, - .freq_tbl = ftbl_usb30_mock_utmi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "usb30_mock_utmi_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 40000000, - LOW, 60000000), - }, -}; - -static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = { - F(1200000, P_XO, 16, 0, 0), - F(19200000, P_XO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 usb3_phy_aux_clk_src = { - .cmd_rcgr = 0x5000c, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gcc_parent_map_4, - .freq_tbl = ftbl_usb3_phy_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "usb3_phy_aux_clk_src", - .parent_names = gcc_parent_names_4, - .num_parents = 3, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP1( - LOWER, 19200000), - }, -}; - -static struct clk_branch gcc_aggre2_ufs_axi_clk = { - .halt_reg = 0x75034, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x75034, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre2_ufs_axi_clk", - .parent_names = (const char *[]){ - "ufs_axi_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_aggre2_usb3_axi_clk = { - .halt_reg = 0xf03c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf03c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_aggre2_usb3_axi_clk", - .parent_names = (const char *[]){ - "usb30_master_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_bimc_gfx_clk = { - .halt_reg = 0x7106c, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x7106c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_bimc_gfx_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_bimc_hmss_axi_clk = { - .halt_reg = 0x48004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(22), - .hw.init = &(struct clk_init_data){ - .name = "gcc_bimc_hmss_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_bimc_mss_q6_axi_clk = { - .halt_reg = 0x4401c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x4401c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_bimc_mss_q6_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp1_ahb_clk = { - .halt_reg = 0x17004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(17), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp1_ahb_clk", - .flags = CLK_ENABLE_HAND_OFF, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { - .halt_reg = 0x19008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x19008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp1_qup1_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup1_i2c_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { - .halt_reg = 0x19004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x19004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp1_qup1_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup1_spi_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { - .halt_reg = 0x1b008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1b008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp1_qup2_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup2_i2c_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { - .halt_reg = 0x1b004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1b004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp1_qup2_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup2_spi_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { - .halt_reg = 0x1d008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1d008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp1_qup3_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup3_i2c_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { - .halt_reg = 0x1d004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1d004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp1_qup3_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup3_spi_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { - .halt_reg = 0x1f008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1f008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp1_qup4_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup4_i2c_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { - .halt_reg = 0x1f004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1f004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp1_qup4_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup4_spi_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp1_uart1_apps_clk = { - .halt_reg = 0x1a004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1a004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp1_uart1_apps_clk", - .parent_names = (const char *[]){ - "blsp1_uart1_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp1_uart2_apps_clk = { - .halt_reg = 0x1c004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1c004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp1_uart2_apps_clk", - .parent_names = (const char *[]){ - "blsp1_uart2_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp2_ahb_clk = { - .halt_reg = 0x25004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(15), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp2_ahb_clk", - .flags = CLK_ENABLE_HAND_OFF, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { - .halt_reg = 0x26008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x26008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp2_qup1_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup1_i2c_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { - .halt_reg = 0x26004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x26004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp2_qup1_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup1_spi_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { - .halt_reg = 0x28008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x28008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp2_qup2_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup2_i2c_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { - .halt_reg = 0x28004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x28004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp2_qup2_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup2_spi_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { - .halt_reg = 0x2a008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2a008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp2_qup3_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup3_i2c_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { - .halt_reg = 0x2a004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2a004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp2_qup3_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup3_spi_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { - .halt_reg = 0x2c008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2c008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp2_qup4_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup4_i2c_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { - .halt_reg = 0x2c004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2c004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp2_qup4_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup4_spi_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp2_uart1_apps_clk = { - .halt_reg = 0x27004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x27004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp2_uart1_apps_clk", - .parent_names = (const char *[]){ - "blsp2_uart1_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_blsp2_uart2_apps_clk = { - .halt_reg = 0x29004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x29004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_blsp2_uart2_apps_clk", - .parent_names = (const char *[]){ - "blsp2_uart2_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_boot_rom_ahb_clk = { - .halt_reg = 0x38004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(10), - .hw.init = &(struct clk_init_data){ - .name = "gcc_boot_rom_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cfg_noc_usb2_axi_clk = { - .halt_reg = 0x5058, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x5058, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cfg_noc_usb2_axi_clk", - .parent_names = (const char *[]){ - "usb20_master_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_cfg_noc_usb3_axi_clk = { - .halt_reg = 0x5018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x5018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cfg_noc_usb3_axi_clk", - .parent_names = (const char *[]){ - "usb30_master_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_dcc_ahb_clk = { - .halt_reg = 0x84004, - .clkr = { - .enable_reg = 0x84004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_dcc_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp1_clk = { - .halt_reg = 0x64000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x64000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gp1_clk", - .parent_names = (const char *[]){ - "gp1_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp2_clk = { - .halt_reg = 0x65000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x65000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gp2_clk", - .parent_names = (const char *[]){ - "gp2_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gp3_clk = { - .halt_reg = 0x66000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x66000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gp3_clk", - .parent_names = (const char *[]){ - "gp3_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_bimc_gfx_clk = { - .halt_reg = 0x71010, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x71010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_bimc_gfx_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_bimc_gfx_src_clk = { - .halt_reg = 0x7100c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x7100c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_bimc_gfx_src_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_cfg_ahb_clk = { - .halt_reg = 0x71004, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x71004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_cfg_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_gate2 gpll0_out_msscc = { - .udelay = 1, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(2), - .hw.init = &(struct clk_init_data){ - .name = "gpll0_out_msscc", - .ops = &clk_gate2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_gpll0_clk = { - .halt_reg = 0x5200c, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_gpll0_clk", - .parent_names = (const char *[]){ - "gpll0_out_main", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_gpll0_div_clk = { - .halt_reg = 0x5200c, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(3), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_gpll0_div_clk", - .parent_names = (const char *[]){ - "gpll0_out_early_div", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { - .halt_reg = 0x71018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x71018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_snoc_dvm_gfx_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_hmss_ahb_clk = { - .halt_reg = 0x48000, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(21), - .hw.init = &(struct clk_init_data){ - .name = "gcc_hmss_ahb_clk", - .parent_names = (const char *[]){ - "hmss_ahb_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_hmss_dvm_bus_clk = { - .halt_reg = 0x4808c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x4808c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_hmss_dvm_bus_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_hmss_rbcpr_clk = { - .halt_reg = 0x48008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x48008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_hmss_rbcpr_clk", - .parent_names = (const char *[]){ - "hmss_rbcpr_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mmss_gpll0_clk = { - .halt_reg = 0x5200c, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_mmss_gpll0_clk", - .parent_names = (const char *[]){ - "gpll0_out_main", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mmss_gpll0_div_clk = { - .halt_reg = 0x5200c, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x5200c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_mmss_gpll0_div_clk", - .parent_names = (const char *[]){ - "gpll0_out_early_div", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { - .halt_reg = 0x9004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x9004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_mmss_noc_cfg_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mmss_sys_noc_axi_clk = { - .halt_reg = 0x9000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x9000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_mmss_sys_noc_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mss_cfg_ahb_clk = { - .halt_reg = 0x8a000, - .clkr = { - .enable_reg = 0x8a000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_mss_cfg_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = { - .halt_reg = 0x8a004, - .clkr = { - .enable_reg = 0x8a004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_mss_mnoc_bimc_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mss_q6_bimc_axi_clk = { - .halt_reg = 0x8a040, - .clkr = { - .enable_reg = 0x8a040, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_mss_q6_bimc_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mss_snoc_axi_clk = { - .halt_reg = 0x8a03c, - .clkr = { - .enable_reg = 0x8a03c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_mss_snoc_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pdm2_clk = { - .halt_reg = 0x3300c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3300c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pdm2_clk", - .parent_names = (const char *[]){ - "pdm2_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_pdm_ahb_clk = { - .halt_reg = 0x33004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x33004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_pdm_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_prng_ahb_clk = { - .halt_reg = 0x34004, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x52004, - .enable_mask = BIT(13), - .hw.init = &(struct clk_init_data){ - .name = "gcc_prng_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qspi_ahb_clk = { - .halt_reg = 0x4d004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x4d004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qspi_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_qspi_ser_clk = { - .halt_reg = 0x4d008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x4d008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_qspi_ser_clk", - .parent_names = (const char *[]){ - "qspi_ser_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_rx0_usb2_clkref_clk = { - .halt_reg = 0x88018, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x88018, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_rx0_usb2_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_rx1_usb2_clkref_clk = { - .halt_reg = 0x88014, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x88014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_rx1_usb2_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_rx2_qlink_clkref_clk = { - .halt_reg = 0x88034, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x88034, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_rx2_qlink_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc1_ahb_clk = { - .halt_reg = 0x16008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x16008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc1_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc1_apps_clk = { - .halt_reg = 0x16004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x16004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc1_apps_clk", - .parent_names = (const char *[]){ - "sdcc1_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc1_ice_core_clk = { - .halt_reg = 0x1600c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1600c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc1_ice_core_clk", - .parent_names = (const char *[]){ - "sdcc1_ice_core_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc2_ahb_clk = { - .halt_reg = 0x14008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x14008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc2_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sdcc2_apps_clk = { - .halt_reg = 0x14004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x14004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sdcc2_apps_clk", - .parent_names = (const char *[]){ - "sdcc2_apps_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_ahb_clk = { - .halt_reg = 0x7500c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x7500c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_ahb_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_axi_clk = { - .halt_reg = 0x75008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x75008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_axi_clk", - .parent_names = (const char *[]){ - "ufs_axi_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_axi_hw_ctl_clk = { - .halt_reg = 0x75008, - .clkr = { - .enable_reg = 0x75008, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_axi_hw_ctl_clk", - .parent_names = (const char *[]){ - "gcc_ufs_axi_clk", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_hw_ctl_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_clkref_clk = { - .halt_reg = 0x88008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x88008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_ice_core_clk = { - .halt_reg = 0x7600c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x7600c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_ice_core_clk", - .parent_names = (const char *[]){ - "ufs_ice_core_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_ice_core_hw_ctl_clk = { - .halt_reg = 0x7600c, - .clkr = { - .enable_reg = 0x7600c, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_ice_core_hw_ctl_clk", - .parent_names = (const char *[]){ - "gcc_ufs_ice_core_clk", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_hw_ctl_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_aux_clk = { - .halt_reg = 0x76040, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x76040, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_aux_clk", - .parent_names = (const char *[]){ - "ufs_phy_aux_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_phy_aux_hw_ctl_clk = { - .halt_reg = 0x76040, - .clkr = { - .enable_reg = 0x76040, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_phy_aux_hw_ctl_clk", - .parent_names = (const char *[]){ - "gcc_ufs_phy_aux_clk", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_hw_ctl_ops, - }, - }, -}; - -static struct clk_gate2 gcc_ufs_rx_symbol_0_clk = { - .udelay = 500, - .clkr = { - .enable_reg = 0x75014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_rx_symbol_0_clk", - .ops = &clk_gate2_ops, - }, - }, -}; - -static struct clk_gate2 gcc_ufs_rx_symbol_1_clk = { - .udelay = 500, - .clkr = { - .enable_reg = 0x7605c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_rx_symbol_1_clk", - .ops = &clk_gate2_ops, - }, - }, -}; - -static struct clk_gate2 gcc_ufs_tx_symbol_0_clk = { - .udelay = 500, - .clkr = { - .enable_reg = 0x75010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_tx_symbol_0_clk", - .ops = &clk_gate2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_unipro_core_clk = { - .halt_reg = 0x76008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x76008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_unipro_core_clk", - .parent_names = (const char *[]){ - "ufs_unipro_core_clk_src", - }, - .flags = CLK_SET_RATE_PARENT, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_ufs_unipro_core_hw_ctl_clk = { - .halt_reg = 0x76008, - .clkr = { - .enable_reg = 0x76008, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gcc_ufs_unipro_core_hw_ctl_clk", - .parent_names = (const char *[]){ - "gcc_ufs_unipro_core_clk", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_hw_ctl_ops, - }, - }, -}; - -static struct clk_branch gcc_usb20_master_clk = { - .halt_reg = 0x2f004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2f004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb20_master_clk", - .parent_names = (const char *[]){ - "usb20_master_clk_src", - }, - .flags = CLK_SET_RATE_PARENT, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb20_mock_utmi_clk = { - .halt_reg = 0x2f00c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2f00c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb20_mock_utmi_clk", - .parent_names = (const char *[]){ - "usb20_mock_utmi_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb20_sleep_clk = { - .halt_reg = 0x2f008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2f008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb20_sleep_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_master_clk = { - .halt_reg = 0xf008, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_master_clk", - .parent_names = (const char *[]){ - "usb30_master_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_mock_utmi_clk = { - .halt_reg = 0xf010, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf010, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_mock_utmi_clk", - .parent_names = (const char *[]){ - "usb30_mock_utmi_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb30_sleep_clk = { - .halt_reg = 0xf00c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xf00c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb30_sleep_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_clkref_clk = { - .halt_reg = 0x8800c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x8800c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_clkref_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb3_phy_aux_clk = { - .halt_reg = 0x50000, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x50000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_phy_aux_clk", - .parent_names = (const char *[]){ - "usb3_phy_aux_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_gate2 gcc_usb3_phy_pipe_clk = { - .udelay = 50, - .clkr = { - .enable_reg = 0x50004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb3_phy_pipe_clk", - .ops = &clk_gate2_ops, - }, - }, -}; - -static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { - .halt_reg = 0x6a004, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x6a004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_usb_phy_cfg_ahb2phy_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk = { - .halt_reg = 0x7d014, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x7d014, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "hlos1_vote_lpass_adsp_smmu_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch hlos1_vote_turing_adsp_smmu_clk = { - .halt_reg = 0x7d048, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x7d048, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "hlos1_vote_turing_adsp_smmu_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch hlos2_vote_turing_adsp_smmu_clk = { - .halt_reg = 0x7e048, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x7e048, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "hlos2_vote_turing_adsp_smmu_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_fixed_factor gcc_ce1_ahb_m_clk = { - .hw.init = &(struct clk_init_data){ - .name = "gcc_ce1_ahb_m_clk", - .ops = &clk_dummy_ops, - }, -}; - -static struct clk_fixed_factor gcc_ce1_axi_m_clk = { - .hw.init = &(struct clk_init_data){ - .name = "gcc_ce1_axi_m_clk", - .ops = &clk_dummy_ops, - }, -}; - -struct clk_hw *gcc_msmfalcon_hws[] = { - [GCC_XO] = &xo.hw, - [GCC_GPLL0_EARLY_DIV] = &gpll0_out_early_div.hw, - [GCC_GPLL1_EARLY_DIV] = &gpll1_out_early_div.hw, - [GCC_CE1_AHB_M_CLK] = &gcc_ce1_ahb_m_clk.hw, - [GCC_CE1_AXI_M_CLK] = &gcc_ce1_axi_m_clk.hw, -}; - -static struct clk_regmap *gcc_falcon_clocks[] = { - [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, - [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, - [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, - [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, - [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, - [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, - [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, - [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, - [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, - [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, - [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, - [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, - [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, - [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, - [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, - [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, - [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, - [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, - [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, - [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, - [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr, - [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr, - [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, - [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr, - [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr, - [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, - [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, - [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, - [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, - [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, - [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, - [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, - [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, - [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, - [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, - [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, - [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, - [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, - [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, - [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, - [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, - [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, - [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, - [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, - [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, - [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, - [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, - [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, - [GCC_CFG_NOC_USB2_AXI_CLK] = &gcc_cfg_noc_usb2_axi_clk.clkr, - [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr, - [GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr, - [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, - [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, - [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, - [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr, - [GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr, - [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, - [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr, - [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr, - [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, - [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr, - [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr, - [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr, - [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr, - [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr, - [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr, - [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr, - [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, - [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr, - [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, - [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, - [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, - [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, - [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, - [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr, - [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr, - [GCC_RX0_USB2_CLKREF_CLK] = &gcc_rx0_usb2_clkref_clk.clkr, - [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr, - [GCC_RX2_QLINK_CLKREF_CLK] = &gcc_rx2_qlink_clkref_clk.clkr, - [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, - [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, - [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, - [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, - [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, - [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr, - [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr, - [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, - [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr, - [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr, - [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr, - [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr, - [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr, - [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr, - [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr, - [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr, - [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr, - [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, - [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, - [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, - [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr, - [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, - [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, - [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, - [GP1_CLK_SRC] = &gp1_clk_src.clkr, - [GP2_CLK_SRC] = &gp2_clk_src.clkr, - [GP3_CLK_SRC] = &gp3_clk_src.clkr, - [GPLL0] = &gpll0_out_main.clkr, - [GPLL1] = &gpll1_out_main.clkr, - [GPLL4] = &gpll4_out_main.clkr, - [HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &hlos1_vote_lpass_adsp_smmu_clk.clkr, - [HMSS_AHB_CLK_SRC] = &hmss_ahb_clk_src.clkr, - [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr, - [HMSS_GPLL4_CLK_SRC] = &hmss_gpll4_clk_src.clkr, - [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr, - [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, - [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr, - [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, - [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr, - [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, - [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, - [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr, - [UFS_PHY_AUX_CLK_SRC] = &ufs_phy_aux_clk_src.clkr, - [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr, - [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr, - [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr, - [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, - [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, - [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, - [GPLL0_OUT_MSSCC] = &gpll0_out_msscc.clkr, - [GCC_UFS_AXI_HW_CTL_CLK] = &gcc_ufs_axi_hw_ctl_clk.clkr, - [GCC_UFS_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_ice_core_hw_ctl_clk.clkr, - [GCC_UFS_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_aux_hw_ctl_clk.clkr, - [GCC_UFS_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_unipro_core_hw_ctl_clk.clkr, - [HLOS1_VOTE_TURING_ADSP_SMMU_CLK] = - &hlos1_vote_turing_adsp_smmu_clk.clkr, - [HLOS2_VOTE_TURING_ADSP_SMMU_CLK] = - &hlos2_vote_turing_adsp_smmu_clk.clkr, -}; - -static const struct qcom_reset_map gcc_falcon_resets[] = { - [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, - [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, - [GCC_UFS_BCR] = { 0x75000 }, - [GCC_USB3_DP_PHY_BCR] = { 0x50028 }, - [GCC_USB3_PHY_BCR] = { 0x50020 }, - [GCC_USB3PHY_PHY_BCR] = { 0x50024 }, - [GCC_USB_20_BCR] = { 0x2f000 }, - [GCC_USB_30_BCR] = { 0xf000 }, - [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, -}; - -static const struct regmap_config gcc_falcon_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0x94000, - .fast_io = true, -}; - -static const struct qcom_cc_desc gcc_falcon_desc = { - .config = &gcc_falcon_regmap_config, - .clks = gcc_falcon_clocks, - .num_clks = ARRAY_SIZE(gcc_falcon_clocks), - .hwclks = gcc_msmfalcon_hws, - .num_hwclks = ARRAY_SIZE(gcc_msmfalcon_hws), - .resets = gcc_falcon_resets, - .num_resets = ARRAY_SIZE(gcc_falcon_resets), -}; - -static const struct of_device_id gcc_falcon_match_table[] = { - { .compatible = "qcom,gcc-msmfalcon" }, - { } -}; -MODULE_DEVICE_TABLE(of, gcc_falcon_match_table); - -static int gcc_falcon_probe(struct platform_device *pdev) -{ - int ret = 0; - struct regmap *regmap; - - regmap = qcom_cc_map(pdev, &gcc_falcon_desc); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); - - /* - * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be - * turned off by hardware during certain apps low power modes. - */ - regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); - - vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig"); - if (IS_ERR(vdd_dig.regulator[0])) { - if (!(PTR_ERR(vdd_dig.regulator[0]) == -EPROBE_DEFER)) - dev_err(&pdev->dev, - "Unable to get vdd_dig regulator\n"); - return PTR_ERR(vdd_dig.regulator[0]); - } - - vdd_dig_ao.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig_ao"); - if (IS_ERR(vdd_dig_ao.regulator[0])) { - if (!(PTR_ERR(vdd_dig_ao.regulator[0]) == -EPROBE_DEFER)) - dev_err(&pdev->dev, - "Unable to get vdd_dig_ao regulator\n"); - return PTR_ERR(vdd_dig_ao.regulator[0]); - } - - ret = qcom_cc_really_probe(pdev, &gcc_falcon_desc, regmap); - if (ret) { - dev_err(&pdev->dev, "Failed to register GCC clocks\n"); - return ret; - } - - /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */ - regmap_update_bits(regmap, 0x0902c, 0x3, 0x3); - regmap_update_bits(regmap, 0x71028, 0x3, 0x3); - - /* This clock is used for all MMSSCC register access */ - clk_prepare_enable(gcc_mmss_noc_cfg_ahb_clk.clkr.hw.clk); - - /* This clock is used for all GPUCC register access */ - clk_prepare_enable(gcc_gpu_cfg_ahb_clk.clkr.hw.clk); - - dev_info(&pdev->dev, "Registered GCC clocks\n"); - - return ret; -} - -static struct platform_driver gcc_falcon_driver = { - .probe = gcc_falcon_probe, - .driver = { - .name = "gcc-msmfalcon", - .of_match_table = gcc_falcon_match_table, - }, -}; - -static int __init gcc_falcon_init(void) -{ - return platform_driver_register(&gcc_falcon_driver); -} -core_initcall_sync(gcc_falcon_init); - -static void __exit gcc_falcon_exit(void) -{ - platform_driver_unregister(&gcc_falcon_driver); -} -module_exit(gcc_falcon_exit); - -/* Debug Mux for measure */ -static struct measure_clk_data debug_mux_priv = { - .xo_div4_cbcr = 0x43008, - .ctl_reg = 0x62004, - .status_reg = 0x62008, -}; - -static const char *const debug_mux_parent_names[] = { - "snoc_clk", - "cnoc_clk", - "cnoc_periph_clk", - "bimc_clk", - "ce1_clk", - "ipa_clk", - "gcc_aggre2_ufs_axi_clk", - "gcc_aggre2_usb3_axi_clk", - "gcc_bimc_gfx_clk", - "gcc_bimc_hmss_axi_clk", - "gcc_bimc_mss_q6_axi_clk", - "gcc_blsp1_ahb_clk", - "gcc_blsp1_qup1_i2c_apps_clk", - "gcc_blsp1_qup1_spi_apps_clk", - "gcc_blsp1_qup2_i2c_apps_clk", - "gcc_blsp1_qup2_spi_apps_clk", - "gcc_blsp1_qup3_i2c_apps_clk", - "gcc_blsp1_qup3_spi_apps_clk", - "gcc_blsp1_qup4_i2c_apps_clk", - "gcc_blsp1_qup4_spi_apps_clk", - "gcc_blsp1_uart1_apps_clk", - "gcc_blsp1_uart2_apps_clk", - "gcc_blsp2_ahb_clk", - "gcc_blsp2_qup1_i2c_apps_clk", - "gcc_blsp2_qup1_spi_apps_clk", - "gcc_blsp2_qup2_i2c_apps_clk", - "gcc_blsp2_qup2_spi_apps_clk", - "gcc_blsp2_qup3_i2c_apps_clk", - "gcc_blsp2_qup3_spi_apps_clk", - "gcc_blsp2_qup4_i2c_apps_clk", - "gcc_blsp2_qup4_spi_apps_clk", - "gcc_blsp2_uart1_apps_clk", - "gcc_blsp2_uart2_apps_clk", - "gcc_boot_rom_ahb_clk", - "gcc_ce1_ahb_m_clk", - "gcc_ce1_axi_m_clk", - "gcc_cfg_noc_usb2_axi_clk", - "gcc_cfg_noc_usb3_axi_clk", - "gcc_dcc_ahb_clk", - "gcc_gp1_clk", - "gcc_gp2_clk", - "gcc_gp3_clk", - "gcc_gpu_bimc_gfx_clk", - "gcc_gpu_bimc_gfx_src_clk", - "gcc_gpu_cfg_ahb_clk", - "gcc_gpu_snoc_dvm_gfx_clk", - "gcc_hmss_ahb_clk", - "gcc_hmss_dvm_bus_clk", - "gcc_hmss_rbcpr_clk", - "gcc_mmss_noc_cfg_ahb_clk", - "gcc_mmss_sys_noc_axi_clk", - "gcc_mss_cfg_ahb_clk", - "gcc_mss_mnoc_bimc_axi_clk", - "gcc_mss_q6_bimc_axi_clk", - "gcc_mss_snoc_axi_clk", - "gcc_pdm2_clk", - "gcc_pdm_ahb_clk", - "gcc_prng_ahb_clk", - "gcc_qspi_ahb_clk", - "gcc_qspi_ser_clk", - "gcc_sdcc1_ahb_clk", - "gcc_sdcc1_apps_clk", - "gcc_sdcc1_ice_core_clk", - "gcc_sdcc2_ahb_clk", - "gcc_sdcc2_apps_clk", - "gcc_ufs_ahb_clk", - "gcc_ufs_axi_clk", - "gcc_ufs_ice_core_clk", - "gcc_ufs_phy_aux_clk", - "gcc_ufs_unipro_core_clk", - "gcc_usb20_master_clk", - "gcc_usb20_mock_utmi_clk", - "gcc_usb20_sleep_clk", - "gcc_usb30_master_clk", - "gcc_usb30_mock_utmi_clk", - "gcc_usb30_sleep_clk", - "gcc_usb3_phy_aux_clk", - "gcc_usb_phy_cfg_ahb2phy_clk", - "gcc_ufs_rx_symbol_0_clk", - "gcc_ufs_rx_symbol_1_clk", - "gcc_ufs_tx_symbol_0_clk", - "gcc_usb3_phy_pipe_clk", - "mmssnoc_axi_clk", - "mmss_bimc_smmu_ahb_clk", - "mmss_bimc_smmu_axi_clk", - "mmss_camss_ahb_clk", - "mmss_camss_cci_ahb_clk", - "mmss_camss_cci_clk", - "mmss_camss_cphy_csid0_clk", - "mmss_camss_cphy_csid1_clk", - "mmss_camss_cphy_csid2_clk", - "mmss_camss_cphy_csid3_clk", - "mmss_camss_cpp_ahb_clk", - "mmss_camss_cpp_axi_clk", - "mmss_camss_cpp_clk", - "mmss_camss_cpp_vbif_ahb_clk", - "mmss_camss_csi0_ahb_clk", - "mmss_camss_csi0_clk", - "mmss_camss_csi0phytimer_clk", - "mmss_camss_csi0pix_clk", - "mmss_camss_csi0rdi_clk", - "mmss_camss_csi1_ahb_clk", - "mmss_camss_csi1_clk", - "mmss_camss_csi1phytimer_clk", - "mmss_camss_csi1pix_clk", - "mmss_camss_csi1rdi_clk", - "mmss_camss_csi2_ahb_clk", - "mmss_camss_csi2_clk", - "mmss_camss_csi2phytimer_clk", - "mmss_camss_csi2pix_clk", - "mmss_camss_csi2rdi_clk", - "mmss_camss_csi3_ahb_clk", - "mmss_camss_csi3_clk", - "mmss_camss_csi3pix_clk", - "mmss_camss_csi3rdi_clk", - "mmss_camss_csi_vfe0_clk", - "mmss_camss_csi_vfe1_clk", - "mmss_camss_csiphy0_clk", - "mmss_camss_csiphy1_clk", - "mmss_camss_csiphy2_clk", - "mmss_camss_gp0_clk", - "mmss_camss_gp1_clk", - "mmss_camss_ispif_ahb_clk", - "mmss_camss_jpeg0_clk", - "mmss_camss_jpeg_ahb_clk", - "mmss_camss_jpeg_axi_clk", - "mmss_camss_mclk0_clk", - "mmss_camss_mclk1_clk", - "mmss_camss_mclk2_clk", - "mmss_camss_mclk3_clk", - "mmss_camss_micro_ahb_clk", - "mmss_camss_top_ahb_clk", - "mmss_camss_vfe0_ahb_clk", - "mmss_camss_vfe0_clk", - "mmss_camss_vfe0_stream_clk", - "mmss_camss_vfe1_ahb_clk", - "mmss_camss_vfe1_clk", - "mmss_camss_vfe1_stream_clk", - "mmss_camss_vfe_vbif_ahb_clk", - "mmss_camss_vfe_vbif_axi_clk", - "mmss_csiphy_ahb2crif_clk", - "mmss_mdss_ahb_clk", - "mmss_mdss_axi_clk", - "mmss_mdss_byte0_clk", - "mmss_mdss_byte0_intf_clk", - "mmss_mdss_byte1_clk", - "mmss_mdss_byte1_intf_clk", - "mmss_mdss_dp_aux_clk", - "mmss_mdss_dp_crypto_clk", - "mmss_mdss_dp_gtc_clk", - "mmss_mdss_dp_link_clk", - "mmss_mdss_dp_link_intf_clk", - "mmss_mdss_dp_pixel_clk", - "mmss_mdss_esc0_clk", - "mmss_mdss_esc1_clk", - "mmss_mdss_hdmi_dp_ahb_clk", - "mmss_mdss_mdp_clk", - "mmss_mdss_pclk0_clk", - "mmss_mdss_pclk1_clk", - "mmss_mdss_rot_clk", - "mmss_mdss_vsync_clk", - "mmss_misc_ahb_clk", - "mmss_misc_cxo_clk", - "mmss_mnoc_ahb_clk", - "mmss_snoc_dvm_axi_clk", - "mmss_video_ahb_clk", - "mmss_video_axi_clk", - "mmss_video_core_clk", - "mmss_video_subcore0_clk", - "gpucc_gfx3d_clk", - "gpucc_rbbmtimer_clk", - "gpucc_rbcpr_clk", - "pwrcl_clk", - "perfcl_clk", -}; - -static struct clk_debug_mux gcc_debug_mux = { - .priv = &debug_mux_priv, - .en_mask = BIT(16), - .mask = 0x3FF, - MUX_SRC_LIST( - { "snoc_clk", 0x000 }, - { "cnoc_clk", 0x00E }, - { "cnoc_periph_clk", 0x198 }, - { "bimc_clk", 0x14E }, - { "ce1_clk", 0x097 }, - { "ipa_clk", 0x11b }, - { "gcc_aggre2_ufs_axi_clk", 0x10B }, - { "gcc_aggre2_usb3_axi_clk", 0x10A }, - { "gcc_bimc_gfx_clk", 0x0AC }, - { "gcc_bimc_hmss_axi_clk", 0x0BB }, - { "gcc_bimc_mss_q6_axi_clk", 0x0A3 }, - { "gcc_blsp1_ahb_clk", 0x04A }, - { "gcc_blsp1_qup1_i2c_apps_clk", 0x04D }, - { "gcc_blsp1_qup1_spi_apps_clk", 0x04C }, - { "gcc_blsp1_qup2_i2c_apps_clk", 0x051 }, - { "gcc_blsp1_qup2_spi_apps_clk", 0x050 }, - { "gcc_blsp1_qup3_i2c_apps_clk", 0x055 }, - { "gcc_blsp1_qup3_spi_apps_clk", 0x054 }, - { "gcc_blsp1_qup4_i2c_apps_clk", 0x059 }, - { "gcc_blsp1_qup4_spi_apps_clk", 0x058 }, - { "gcc_blsp1_uart1_apps_clk", 0x04E }, - { "gcc_blsp1_uart2_apps_clk", 0x052 }, - { "gcc_blsp2_ahb_clk", 0x05E }, - { "gcc_blsp2_qup1_i2c_apps_clk", 0x061 }, - { "gcc_blsp2_qup1_spi_apps_clk", 0x060 }, - { "gcc_blsp2_qup2_i2c_apps_clk", 0x065 }, - { "gcc_blsp2_qup2_spi_apps_clk", 0x064 }, - { "gcc_blsp2_qup3_i2c_apps_clk", 0x069 }, - { "gcc_blsp2_qup3_spi_apps_clk", 0x068 }, - { "gcc_blsp2_qup4_i2c_apps_clk", 0x06D }, - { "gcc_blsp2_qup4_spi_apps_clk", 0x06C }, - { "gcc_blsp2_uart1_apps_clk", 0x062 }, - { "gcc_blsp2_uart2_apps_clk", 0x066 }, - { "gcc_boot_rom_ahb_clk", 0x07A }, - { "gcc_ce1_ahb_m_clk", 0x099 }, - { "gcc_ce1_axi_m_clk", 0x098 }, - { "gcc_cfg_noc_usb2_axi_clk", 0x168 }, - { "gcc_cfg_noc_usb3_axi_clk", 0x014 }, - { "gcc_dcc_ahb_clk", 0x119 }, - { "gcc_gp1_clk", 0x0DF }, - { "gcc_gp2_clk", 0x0E0 }, - { "gcc_gp3_clk", 0x0E1 }, - { "gcc_gpu_bimc_gfx_clk", 0x13F }, - { "gcc_gpu_bimc_gfx_src_clk", 0x13E }, - { "gcc_gpu_cfg_ahb_clk", 0x13B }, - { "gcc_gpu_snoc_dvm_gfx_clk", 0x141 }, - { "gcc_hmss_ahb_clk", 0x0BA }, - { "gcc_hmss_dvm_bus_clk", 0x0BF }, - { "gcc_hmss_rbcpr_clk", 0x0BC }, - { "gcc_mmss_noc_cfg_ahb_clk", 0x020 }, - { "gcc_mmss_sys_noc_axi_clk", 0x01F }, - { "gcc_mss_cfg_ahb_clk", 0x11F }, - { "gcc_mss_mnoc_bimc_axi_clk", 0x120 }, - { "gcc_mss_q6_bimc_axi_clk", 0x124 }, - { "gcc_mss_snoc_axi_clk", 0x123 }, - { "gcc_pdm2_clk", 0x074 }, - { "gcc_pdm_ahb_clk", 0x072 }, - { "gcc_prng_ahb_clk", 0x075 }, - { "gcc_qspi_ahb_clk", 0x172 }, - { "gcc_qspi_ser_clk", 0x173 }, - { "gcc_sdcc1_ahb_clk", 0x16E }, - { "gcc_sdcc1_apps_clk", 0x16D }, - { "gcc_sdcc1_ice_core_clk", 0x16F }, - { "gcc_sdcc2_ahb_clk", 0x047 }, - { "gcc_sdcc2_apps_clk", 0x046 }, - { "gcc_ufs_ahb_clk", 0x0EB }, - { "gcc_ufs_axi_clk", 0x0EA }, - { "gcc_ufs_ice_core_clk", 0x0F1 }, - { "gcc_ufs_phy_aux_clk", 0x0F2 }, - { "gcc_ufs_unipro_core_clk", 0x0F0 }, - { "gcc_usb20_master_clk", 0x169 }, - { "gcc_usb20_mock_utmi_clk", 0x16B }, - { "gcc_usb20_sleep_clk", 0x16A }, - { "gcc_usb30_master_clk", 0x03C }, - { "gcc_usb30_mock_utmi_clk", 0x03E }, - { "gcc_usb30_sleep_clk", 0x03D }, - { "gcc_usb3_phy_aux_clk", 0x03F }, - { "gcc_usb_phy_cfg_ahb2phy_clk", 0x045 }, - { "gcc_ufs_rx_symbol_0_clk", 0x0ED }, - { "gcc_ufs_rx_symbol_1_clk", 0x162 }, - { "gcc_ufs_tx_symbol_0_clk", 0x0EC }, - { "gcc_usb3_phy_pipe_clk", 0x040 }, - { "mmssnoc_axi_clk", 0x22, MMCC, 0x004 }, - { "mmss_bimc_smmu_ahb_clk", 0x22, MMCC, 0x00C }, - { "mmss_bimc_smmu_axi_clk", 0x22, MMCC, 0x00D }, - { "mmss_camss_ahb_clk", 0x22, MMCC, 0x037 }, - { "mmss_camss_cci_ahb_clk", 0x22, MMCC, 0x02E }, - { "mmss_camss_cci_clk", 0x22, MMCC, 0x02D }, - { "mmss_camss_cphy_csid0_clk", 0x22, MMCC, 0x08D }, - { "mmss_camss_cphy_csid1_clk", 0x22, MMCC, 0x08E }, - { "mmss_camss_cphy_csid2_clk", 0x22, MMCC, 0x08F }, - { "mmss_camss_cphy_csid3_clk", 0x22, MMCC, 0x090 }, - { "mmss_camss_cpp_ahb_clk", 0x22, MMCC, 0x03B }, - { "mmss_camss_cpp_axi_clk", 0x22, MMCC, 0x07A }, - { "mmss_camss_cpp_clk", 0x22, MMCC, 0x03A }, - { "mmss_camss_cpp_vbif_ahb_clk", 0x22, MMCC, 0x073 }, - { "mmss_camss_csi0_ahb_clk", 0x22, MMCC, 0x042 }, - { "mmss_camss_csi0_clk", 0x22, MMCC, 0x041 }, - { "mmss_camss_csi0phytimer_clk", 0x22, MMCC, 0x02F }, - { "mmss_camss_csi0pix_clk", 0x22, MMCC, 0x045 }, - { "mmss_camss_csi0rdi_clk", 0x22, MMCC, 0x044 }, - { "mmss_camss_csi1_ahb_clk", 0x22, MMCC, 0x047 }, - { "mmss_camss_csi1_clk", 0x22, MMCC, 0x046 }, - { "mmss_camss_csi1phytimer_clk", 0x22, MMCC, 0x030 }, - { "mmss_camss_csi1pix_clk", 0x22, MMCC, 0x04A }, - { "mmss_camss_csi1rdi_clk", 0x22, MMCC, 0x049 }, - { "mmss_camss_csi2_ahb_clk", 0x22, MMCC, 0x04C }, - { "mmss_camss_csi2_clk", 0x22, MMCC, 0x04B }, - { "mmss_camss_csi2phytimer_clk", 0x22, MMCC, 0x031 }, - { "mmss_camss_csi2pix_clk", 0x22, MMCC, 0x04F }, - { "mmss_camss_csi2rdi_clk", 0x22, MMCC, 0x04E }, - { "mmss_camss_csi3_ahb_clk", 0x22, MMCC, 0x051 }, - { "mmss_camss_csi3_clk", 0x22, MMCC, 0x050 }, - { "mmss_camss_csi3pix_clk", 0x22, MMCC, 0x054 }, - { "mmss_camss_csi3rdi_clk", 0x22, MMCC, 0x053 }, - { "mmss_camss_csi_vfe0_clk", 0x22, MMCC, 0x03F }, - { "mmss_camss_csi_vfe1_clk", 0x22, MMCC, 0x040 }, - { "mmss_camss_csiphy0_clk", 0x22, MMCC, 0x043 }, - { "mmss_camss_csiphy1_clk", 0x22, MMCC, 0x085 }, - { "mmss_camss_csiphy2_clk", 0x22, MMCC, 0x088 }, - { "mmss_camss_gp0_clk", 0x22, MMCC, 0x027 }, - { "mmss_camss_gp1_clk", 0x22, MMCC, 0x028 }, - { "mmss_camss_ispif_ahb_clk", 0x22, MMCC, 0x033 }, - { "mmss_camss_jpeg0_clk", 0x22, MMCC, 0x032 }, - { "mmss_camss_jpeg_ahb_clk", 0x22, MMCC, 0x035 }, - { "mmss_camss_jpeg_axi_clk", 0x22, MMCC, 0x036 }, - { "mmss_camss_mclk0_clk", 0x22, MMCC, 0x029 }, - { "mmss_camss_mclk1_clk", 0x22, MMCC, 0x02A }, - { "mmss_camss_mclk2_clk", 0x22, MMCC, 0x02B }, - { "mmss_camss_mclk3_clk", 0x22, MMCC, 0x02C }, - { "mmss_camss_micro_ahb_clk", 0x22, MMCC, 0x026 }, - { "mmss_camss_top_ahb_clk", 0x22, MMCC, 0x025 }, - { "mmss_camss_vfe0_ahb_clk", 0x22, MMCC, 0x086 }, - { "mmss_camss_vfe0_clk", 0x22, MMCC, 0x038 }, - { "mmss_camss_vfe0_stream_clk", 0x22, MMCC, 0x071 }, - { "mmss_camss_vfe1_ahb_clk", 0x22, MMCC, 0x087 }, - { "mmss_camss_vfe1_clk", 0x22, MMCC, 0x039 }, - { "mmss_camss_vfe1_stream_clk", 0x22, MMCC, 0x072 }, - { "mmss_camss_vfe_vbif_ahb_clk", 0x22, MMCC, 0x03C }, - { "mmss_camss_vfe_vbif_axi_clk", 0x22, MMCC, 0x03D }, - { "mmss_csiphy_ahb2crif_clk", 0x22, MMCC, 0x0B8 }, - { "mmss_mdss_ahb_clk", 0x22, MMCC, 0x022 }, - { "mmss_mdss_axi_clk", 0x22, MMCC, 0x024 }, - { "mmss_mdss_byte0_clk", 0x22, MMCC, 0x01E }, - { "mmss_mdss_byte0_intf_clk", 0x22, MMCC, 0x0AD }, - { "mmss_mdss_byte1_clk", 0x22, MMCC, 0x01F }, - { "mmss_mdss_byte1_intf_clk", 0x22, MMCC, 0x0B6 }, - { "mmss_mdss_dp_aux_clk", 0x22, MMCC, 0x09C }, - { "mmss_mdss_dp_crypto_clk", 0x22, MMCC, 0x09A }, - { "mmss_mdss_dp_gtc_clk", 0x22, MMCC, 0x09D }, - { "mmss_mdss_dp_link_clk", 0x22, MMCC, 0x098 }, - { "mmss_mdss_dp_link_intf_clk", 0x22, MMCC, 0x099 }, - { "mmss_mdss_dp_pixel_clk", 0x22, MMCC, 0x09B }, - { "mmss_mdss_esc0_clk", 0x22, MMCC, 0x020 }, - { "mmss_mdss_esc1_clk", 0x22, MMCC, 0x021 }, - { "mmss_mdss_hdmi_dp_ahb_clk", 0x22, MMCC, 0x023 }, - { "mmss_mdss_mdp_clk", 0x22, MMCC, 0x014 }, - { "mmss_mdss_pclk0_clk", 0x22, MMCC, 0x016 }, - { "mmss_mdss_pclk1_clk", 0x22, MMCC, 0x017 }, - { "mmss_mdss_rot_clk", 0x22, MMCC, 0x012 }, - { "mmss_mdss_vsync_clk", 0x22, MMCC, 0x01C }, - { "mmss_misc_ahb_clk", 0x22, MMCC, 0x003 }, - { "mmss_misc_cxo_clk", 0x22, MMCC, 0x077 }, - { "mmss_mnoc_ahb_clk", 0x22, MMCC, 0x001 }, - { "mmss_snoc_dvm_axi_clk", 0x22, MMCC, 0x013 }, - { "mmss_video_ahb_clk", 0x22, MMCC, 0x011 }, - { "mmss_video_axi_clk", 0x22, MMCC, 0x00F }, - { "mmss_video_core_clk", 0x22, MMCC, 0x00E }, - { "mmss_video_subcore0_clk", 0x22, MMCC, 0x01A }, - { "gpucc_gfx3d_clk", 0x13d, GPU, 0x008 }, - { "gpucc_rbbmtimer_clk", 0x13d, GPU, 0x005 }, - { "gpucc_rbcpr_clk", 0x13d, GPU, 0x003 }, - { "pwrcl_clk", 0x0c0, CPU, 0x000, 0x3, 8, 0x0FF }, - { "perfcl_clk", 0x0c0, CPU, 0x100, 0x3, 8, 0x0FF }, - ), - .hw.init = &(struct clk_init_data){ - .name = "gcc_debug_mux", - .ops = &clk_debug_mux_ops, - .parent_names = debug_mux_parent_names, - .num_parents = ARRAY_SIZE(debug_mux_parent_names), - .flags = CLK_IS_MEASURE, - }, -}; - -static const struct of_device_id clk_debug_match_table[] = { - { .compatible = "qcom,gcc-debug-msmfalcon" }, - {} -}; - -static int clk_debug_falcon_probe(struct platform_device *pdev) -{ - struct resource *res; - struct clk *clk; - int ret = 0, count; - - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbg_offset"); - if (!res) { - dev_err(&pdev->dev, "Failed to get debug offset.\n"); - return -EINVAL; - } - gcc_debug_mux.debug_offset = res->start; - - clk = devm_clk_get(&pdev->dev, "xo_clk_src"); - if (IS_ERR(clk)) { - if (PTR_ERR(clk) != -EPROBE_DEFER) - dev_err(&pdev->dev, "Unable to get xo clock\n"); - return PTR_ERR(clk); - } - - debug_mux_priv.cxo = clk; - - ret = of_property_read_u32(pdev->dev.of_node, "qcom,cc-count", - &count); - if (ret < 0) { - dev_err(&pdev->dev, "Num of debug clock controller not specified\n"); - return ret; - } - - if (!count) { - dev_err(&pdev->dev, "Count of CC cannot be zero\n"); - return -EINVAL; - } - - gcc_debug_mux.num_parent_regmap = count; - - gcc_debug_mux.regmap = devm_kzalloc(&pdev->dev, - sizeof(struct regmap *) * count, GFP_KERNEL); - if (!gcc_debug_mux.regmap) - return -ENOMEM; - - if (of_get_property(pdev->dev.of_node, "qcom,gcc", NULL)) { - gcc_debug_mux.regmap[GCC] = - syscon_regmap_lookup_by_phandle(pdev->dev.of_node, - "qcom,gcc"); - if (IS_ERR(gcc_debug_mux.regmap[GCC])) - return PTR_ERR(gcc_debug_mux.regmap[GCC]); - } - - if (of_get_property(pdev->dev.of_node, "qcom,cpu", NULL)) { - gcc_debug_mux.regmap[CPU] = - syscon_regmap_lookup_by_phandle(pdev->dev.of_node, - "qcom,cpu"); - if (IS_ERR(gcc_debug_mux.regmap[CPU])) - return PTR_ERR(gcc_debug_mux.regmap[CPU]); - } - - if (of_get_property(pdev->dev.of_node, "qcom,mmss", NULL)) { - gcc_debug_mux.regmap[MMCC] = - syscon_regmap_lookup_by_phandle(pdev->dev.of_node, - "qcom,mmss"); - if (IS_ERR(gcc_debug_mux.regmap[MMCC])) - return PTR_ERR(gcc_debug_mux.regmap[MMCC]); - - /* Clear the DBG_CLK_DIV bits of the MMSS debug register */ - regmap_update_bits(gcc_debug_mux.regmap[MMCC], 0x0, - 0x60000, 0x0); - } - - if (of_get_property(pdev->dev.of_node, "qcom,gpu", NULL)) { - gcc_debug_mux.regmap[GPU] = - syscon_regmap_lookup_by_phandle(pdev->dev.of_node, - "qcom,gpu"); - if (IS_ERR(gcc_debug_mux.regmap[GPU])) - return PTR_ERR(gcc_debug_mux.regmap[GPU]); - - /* Clear the DBG_CLK_DIV bits of the GPU debug register */ - regmap_update_bits(gcc_debug_mux.regmap[GPU], 0x0, - 0x60000, 0x0); - } - - clk = devm_clk_register(&pdev->dev, &gcc_debug_mux.hw); - if (IS_ERR(clk)) { - dev_err(&pdev->dev, "Unable to register GCC debug mux\n"); - return PTR_ERR(clk); - } - - dev_info(&pdev->dev, "Registered debug mux successfully\n"); - - return ret; -} - -static struct platform_driver clk_debug_driver = { - .probe = clk_debug_falcon_probe, - .driver = { - .name = "gcc-debug-msmfalcon", - .of_match_table = clk_debug_match_table, - .owner = THIS_MODULE, - }, -}; - -int __init clk_debug_falcon_init(void) -{ - return platform_driver_register(&clk_debug_driver); -} -fs_initcall(clk_debug_falcon_init); diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c new file mode 100644 index 000000000000..da4c6e8797d7 --- /dev/null +++ b/drivers/clk/qcom/gcc-sdm660.c @@ -0,0 +1,3322 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "common.h" +#include "clk-pll.h" +#include "clk-regmap.h" +#include "clk-rcg.h" +#include "reset.h" +#include "vdd-level-660.h" + +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } + +static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner); +static DEFINE_VDD_REGULATORS(vdd_dig_ao, VDD_DIG_NUM, 1, vdd_corner); + +enum { + P_CORE_BI_PLL_TEST_SE, + P_GPLL0_OUT_MAIN, + P_GPLL1_OUT_MAIN, + P_GPLL4_OUT_MAIN, + P_PLL0_EARLY_DIV_CLK_SRC, + P_PLL1_EARLY_DIV_CLK_SRC, + P_SLEEP_CLK, + P_XO, +}; + +static const struct parent_map gcc_parent_map_0[] = { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_0[] = { + "xo", + "gpll0_out_main", + "gpll0_out_early_div", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_1[] = { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_1[] = { + "xo", + "gpll0_out_main", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_2[] = { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, + { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_2[] = { + "xo", + "gpll0_out_main", + "core_pi_sleep_clk", + "gpll0_out_early_div", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_3[] = { + { P_XO, 0 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_3[] = { + "xo", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_4[] = { + { P_XO, 0 }, + { P_SLEEP_CLK, 5 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_4[] = { + "xo", + "core_pi_sleep_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_5[] = { + { P_XO, 0 }, + { P_GPLL4_OUT_MAIN, 5 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_5[] = { + "xo", + "gpll4_out_main", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_6[] = { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_PLL0_EARLY_DIV_CLK_SRC, 3 }, + { P_GPLL1_OUT_MAIN, 4 }, + { P_GPLL4_OUT_MAIN, 5 }, + { P_PLL1_EARLY_DIV_CLK_SRC, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_6[] = { + "xo", + "gpll0_out_main", + "gpll0_out_early_div", + "gpll1_out_main", + "gpll4_out_main", + "gpll1_out_early_div", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_7[] = { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL4_OUT_MAIN, 5 }, + { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_7[] = { + "xo", + "gpll0_out_main", + "gpll4_out_main", + "gpll0_out_early_div", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_8[] = { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_PLL0_EARLY_DIV_CLK_SRC, 2 }, + { P_GPLL4_OUT_MAIN, 5 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_8[] = { + "xo", + "gpll0_out_main", + "gpll0_out_early_div", + "gpll4_out_main", + "core_bi_pll_test_se", +}; + +static struct clk_fixed_factor xo = { + .mult = 1, + .div = 1, + .hw.init = &(struct clk_init_data){ + .name = "xo", + .parent_names = (const char *[]){ "cxo" }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_alpha_pll gpll0_out_main = { + .offset = 0x0, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpll0_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_fixed_factor gpll0_out_early_div = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "gpll0_out_early_div", + .parent_names = (const char *[]){ "gpll0_out_main" }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_alpha_pll gpll1_out_main = { + .offset = 0x1000, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gpll1_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_fixed_factor gpll1_out_early_div = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "gpll1_out_early_div", + .parent_names = (const char *[]){ "gpll1_out_main" }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_alpha_pll gpll4_out_main = { + .offset = 0x77000, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gpll4_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), + { } +}; + +static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { + .cmd_rcgr = 0x19020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup1_i2c_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 50000000), + }, +}; + +static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = { + F(960000, P_XO, 10, 1, 2), + F(4800000, P_XO, 4, 0, 0), + F(9600000, P_XO, 2, 0, 0), + F(15000000, P_GPLL0_OUT_MAIN, 10, 1, 4), + F(19200000, P_XO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), + F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), + { } +}; + +static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { + .cmd_rcgr = 0x1900c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup1_spi_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 25000000, + NOMINAL, 50000000), + }, +}; + +static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { + .cmd_rcgr = 0x1b020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup2_i2c_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 50000000), + }, +}; + +static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { + .cmd_rcgr = 0x1b00c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup2_spi_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 25000000, + NOMINAL, 50000000), + }, +}; + +static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { + .cmd_rcgr = 0x1d020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup3_i2c_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 50000000), + }, +}; + +static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { + .cmd_rcgr = 0x1d00c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup3_spi_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 25000000, + NOMINAL, 50000000), + }, +}; + +static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { + .cmd_rcgr = 0x1f020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup4_i2c_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 50000000), + }, +}; + +static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { + .cmd_rcgr = 0x1f00c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup4_spi_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 25000000, + NOMINAL, 50000000), + }, +}; + +static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = { + F(3686400, P_GPLL0_OUT_MAIN, 1, 96, 15625), + F(7372800, P_GPLL0_OUT_MAIN, 1, 192, 15625), + F(14745600, P_GPLL0_OUT_MAIN, 1, 384, 15625), + F(16000000, P_GPLL0_OUT_MAIN, 5, 2, 15), + F(19200000, P_XO, 1, 0, 0), + F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5), + F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75), + F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0), + F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375), + F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), + F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375), + F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75), + F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625), + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0), + { } +}; + +static struct clk_rcg2 blsp1_uart1_apps_clk_src = { + .cmd_rcgr = 0x1a00c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart1_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 31578947, + NOMINAL, 63157895), + }, +}; + +static struct clk_rcg2 blsp1_uart2_apps_clk_src = { + .cmd_rcgr = 0x1c00c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart2_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 31578947, + NOMINAL, 63157895), + }, +}; + +static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { + .cmd_rcgr = 0x26020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup1_i2c_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 50000000), + }, +}; + +static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { + .cmd_rcgr = 0x2600c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup1_spi_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 25000000, + NOMINAL, 50000000), + }, +}; + +static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { + .cmd_rcgr = 0x28020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup2_i2c_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 50000000), + }, +}; + +static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { + .cmd_rcgr = 0x2800c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup2_spi_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 25000000, + NOMINAL, 50000000), + }, +}; + +static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { + .cmd_rcgr = 0x2a020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup3_i2c_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 50000000), + }, +}; + +static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { + .cmd_rcgr = 0x2a00c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup3_spi_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 25000000, + NOMINAL, 50000000), + }, +}; + +static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { + .cmd_rcgr = 0x2c020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup4_i2c_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 50000000), + }, +}; + +static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { + .cmd_rcgr = 0x2c00c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup4_spi_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 25000000, + NOMINAL, 50000000), + }, +}; + +static struct clk_rcg2 blsp2_uart1_apps_clk_src = { + .cmd_rcgr = 0x2700c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_uart1_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 31578947, + NOMINAL, 63157895), + }, +}; + +static struct clk_rcg2 blsp2_uart2_apps_clk_src = { + .cmd_rcgr = 0x2900c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_uart2_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 31578947, + NOMINAL, 63157895), + }, +}; + +static const struct freq_tbl ftbl_gp1_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gp1_clk_src = { + .cmd_rcgr = 0x64004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp1_clk_src", + .parent_names = gcc_parent_names_2, + .num_parents = 5, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 50000000, + LOW, 100000000, + NOMINAL, 200000000), + }, +}; + +static struct clk_rcg2 gp2_clk_src = { + .cmd_rcgr = 0x65004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp2_clk_src", + .parent_names = gcc_parent_names_2, + .num_parents = 5, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 50000000, + LOW, 100000000, + NOMINAL, 200000000), + }, +}; + +static struct clk_rcg2 gp3_clk_src = { + .cmd_rcgr = 0x66004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp3_clk_src", + .parent_names = gcc_parent_names_2, + .num_parents = 5, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 50000000, + LOW, 100000000, + NOMINAL, 200000000), + }, +}; + +static const struct freq_tbl ftbl_hmss_ahb_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0), + F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_rcg2 hmss_ahb_clk_src = { + .cmd_rcgr = 0x48014, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_hmss_ahb_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "hmss_ahb_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3_AO( + LOWER, 19200000, + LOW, 50000000, + NOMINAL, 100000000), + }, +}; + +static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] = { + F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 hmss_gpll0_clk_src = { + .cmd_rcgr = 0x4805c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_hmss_gpll0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "hmss_gpll0_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1_AO( + LOWER, 600000000), + }, +}; + +static const struct freq_tbl ftbl_hmss_gpll4_clk_src[] = { + F(384000000, P_GPLL4_OUT_MAIN, 4, 0, 0), + F(768000000, P_GPLL4_OUT_MAIN, 2, 0, 0), + F(1536000000, P_GPLL4_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 hmss_gpll4_clk_src = { + .cmd_rcgr = 0x48074, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_5, + .freq_tbl = ftbl_hmss_gpll4_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "hmss_gpll4_clk_src", + .parent_names = gcc_parent_names_5, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3_AO( + LOWER, 400000000, + LOW, 800000000, + NOMINAL, 1600000000), + }, +}; + +static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 hmss_rbcpr_clk_src = { + .cmd_rcgr = 0x48044, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_hmss_rbcpr_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "hmss_rbcpr_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + NOMINAL, 50000000), + }, +}; + +static const struct freq_tbl ftbl_pdm2_clk_src[] = { + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 pdm2_clk_src = { + .cmd_rcgr = 0x33010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_pdm2_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pdm2_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 60000000), + }, +}; + +static const struct freq_tbl ftbl_qspi_ser_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(80200000, P_PLL1_EARLY_DIV_CLK_SRC, 5, 0, 0), + F(160400000, P_GPLL1_OUT_MAIN, 5, 0, 0), + F(267333333, P_GPLL1_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 qspi_ser_clk_src = { + .cmd_rcgr = 0x4d00c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_6, + .freq_tbl = ftbl_qspi_ser_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "qspi_ser_clk_src", + .parent_names = gcc_parent_names_6, + .num_parents = 7, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 80200000, + LOW, 160400000, + NOMINAL, 267333333), + }, +}; + +static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = { + F(144000, P_XO, 16, 3, 25), + F(400000, P_XO, 12, 1, 4), + F(20000000, P_PLL0_EARLY_DIV_CLK_SRC, 5, 1, 3), + F(25000000, P_PLL0_EARLY_DIV_CLK_SRC, 6, 1, 2), + F(50000000, P_PLL0_EARLY_DIV_CLK_SRC, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(192000000, P_GPLL4_OUT_MAIN, 8, 0, 0), + F(384000000, P_GPLL4_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 sdcc1_apps_clk_src = { + .cmd_rcgr = 0x1602c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_7, + .freq_tbl = ftbl_sdcc1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc1_apps_clk_src", + .parent_names = gcc_parent_names_7, + .num_parents = 5, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 50000000, + LOW, 100000000, + NOMINAL, 400000000), + }, +}; + +static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = { + F(75000000, P_PLL0_EARLY_DIV_CLK_SRC, 4, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 sdcc1_ice_core_clk_src = { + .cmd_rcgr = 0x16010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_sdcc1_ice_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc1_ice_core_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 75000000, + LOW, 150000000, + NOMINAL, 300000000), + }, +}; + +static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = { + F(144000, P_XO, 16, 3, 25), + F(400000, P_XO, 12, 1, 4), + F(20000000, P_PLL0_EARLY_DIV_CLK_SRC, 5, 1, 3), + F(25000000, P_PLL0_EARLY_DIV_CLK_SRC, 6, 1, 2), + F(50000000, P_PLL0_EARLY_DIV_CLK_SRC, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(192000000, P_GPLL4_OUT_MAIN, 8, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 sdcc2_apps_clk_src = { + .cmd_rcgr = 0x14010, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_8, + .freq_tbl = ftbl_sdcc2_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc2_apps_clk_src", + .parent_names = gcc_parent_names_8, + .num_parents = 5, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 50000000, + LOW, 100000000, + NOMINAL, 200000000), + }, +}; + +static const struct freq_tbl ftbl_ufs_axi_clk_src[] = { + F(50000000, P_PLL0_EARLY_DIV_CLK_SRC, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 ufs_axi_clk_src = { + .cmd_rcgr = 0x75018, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_ufs_axi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ufs_axi_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP5( + LOWER, 50000000, + LOW, 100000000, + LOW_L1, 150000000, + NOMINAL, 200000000, + HIGH, 240000000), + }, +}; + +static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = { + F(75000000, P_PLL0_EARLY_DIV_CLK_SRC, 4, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 ufs_ice_core_clk_src = { + .cmd_rcgr = 0x76010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_ufs_ice_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ufs_ice_core_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 75000000, + LOW, 150000000, + NOMINAL, 300000000), + }, +}; + +static struct clk_rcg2 ufs_phy_aux_clk_src = { + .cmd_rcgr = 0x76044, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_hmss_rbcpr_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ufs_phy_aux_clk_src", + .parent_names = gcc_parent_names_3, + .num_parents = 2, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1( + LOWER, 19200000), + }, +}; + +static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = { + F(37500000, P_PLL0_EARLY_DIV_CLK_SRC, 8, 0, 0), + F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 ufs_unipro_core_clk_src = { + .cmd_rcgr = 0x76028, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_ufs_unipro_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ufs_unipro_core_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 37500000, + LOW, 75000000, + NOMINAL, 150000000), + }, +}; + +static const struct freq_tbl ftbl_usb20_master_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_rcg2 usb20_master_clk_src = { + .cmd_rcgr = 0x2f010, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_usb20_master_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb20_master_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 60000000, + NOMINAL, 120000000), + }, +}; + +static const struct freq_tbl ftbl_usb20_mock_utmi_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 usb20_mock_utmi_clk_src = { + .cmd_rcgr = 0x2f024, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_usb20_mock_utmi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb20_mock_utmi_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 60000000), + }, +}; + +static const struct freq_tbl ftbl_usb30_master_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(66666667, P_PLL0_EARLY_DIV_CLK_SRC, 4.5, 0, 0), + F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), + F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 usb30_master_clk_src = { + .cmd_rcgr = 0xf014, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_usb30_master_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb30_master_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4( + LOWER, 66666667, + LOW, 133333333, + NOMINAL, 200000000, + HIGH, 240000000), + }, +}; + +static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = { + F(40000000, P_PLL0_EARLY_DIV_CLK_SRC, 7.5, 0, 0), + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 usb30_mock_utmi_clk_src = { + .cmd_rcgr = 0xf028, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_usb30_mock_utmi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb30_mock_utmi_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 40000000, + LOW, 60000000), + }, +}; + +static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = { + F(1200000, P_XO, 16, 0, 0), + F(19200000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 usb3_phy_aux_clk_src = { + .cmd_rcgr = 0x5000c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_4, + .freq_tbl = ftbl_usb3_phy_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb3_phy_aux_clk_src", + .parent_names = gcc_parent_names_4, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1( + LOWER, 19200000), + }, +}; + +static struct clk_branch gcc_aggre2_ufs_axi_clk = { + .halt_reg = 0x75034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x75034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_aggre2_ufs_axi_clk", + .parent_names = (const char *[]){ + "ufs_axi_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre2_usb3_axi_clk = { + .halt_reg = 0xf03c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xf03c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_aggre2_usb3_axi_clk", + .parent_names = (const char *[]){ + "usb30_master_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_bimc_gfx_clk = { + .halt_reg = 0x7106c, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x7106c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_bimc_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_bimc_hmss_axi_clk = { + .halt_reg = 0x48004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(22), + .hw.init = &(struct clk_init_data){ + .name = "gcc_bimc_hmss_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_bimc_mss_q6_axi_clk = { + .halt_reg = 0x4401c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4401c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_bimc_mss_q6_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_ahb_clk = { + .halt_reg = 0x17004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(17), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_ahb_clk", + .flags = CLK_ENABLE_HAND_OFF, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { + .halt_reg = 0x19008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x19008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup1_i2c_apps_clk", + .parent_names = (const char *[]){ + "blsp1_qup1_i2c_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { + .halt_reg = 0x19004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x19004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup1_spi_apps_clk", + .parent_names = (const char *[]){ + "blsp1_qup1_spi_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { + .halt_reg = 0x1b008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1b008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup2_i2c_apps_clk", + .parent_names = (const char *[]){ + "blsp1_qup2_i2c_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { + .halt_reg = 0x1b004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1b004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup2_spi_apps_clk", + .parent_names = (const char *[]){ + "blsp1_qup2_spi_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { + .halt_reg = 0x1d008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1d008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup3_i2c_apps_clk", + .parent_names = (const char *[]){ + "blsp1_qup3_i2c_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { + .halt_reg = 0x1d004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1d004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup3_spi_apps_clk", + .parent_names = (const char *[]){ + "blsp1_qup3_spi_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { + .halt_reg = 0x1f008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1f008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup4_i2c_apps_clk", + .parent_names = (const char *[]){ + "blsp1_qup4_i2c_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { + .halt_reg = 0x1f004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1f004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup4_spi_apps_clk", + .parent_names = (const char *[]){ + "blsp1_qup4_spi_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart1_apps_clk = { + .halt_reg = 0x1a004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart1_apps_clk", + .parent_names = (const char *[]){ + "blsp1_uart1_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart2_apps_clk = { + .halt_reg = 0x1c004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1c004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart2_apps_clk", + .parent_names = (const char *[]){ + "blsp1_uart2_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_ahb_clk = { + .halt_reg = 0x25004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(15), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_ahb_clk", + .flags = CLK_ENABLE_HAND_OFF, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { + .halt_reg = 0x26008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x26008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup1_i2c_apps_clk", + .parent_names = (const char *[]){ + "blsp2_qup1_i2c_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { + .halt_reg = 0x26004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x26004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup1_spi_apps_clk", + .parent_names = (const char *[]){ + "blsp2_qup1_spi_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { + .halt_reg = 0x28008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x28008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup2_i2c_apps_clk", + .parent_names = (const char *[]){ + "blsp2_qup2_i2c_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { + .halt_reg = 0x28004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x28004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup2_spi_apps_clk", + .parent_names = (const char *[]){ + "blsp2_qup2_spi_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { + .halt_reg = 0x2a008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2a008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup3_i2c_apps_clk", + .parent_names = (const char *[]){ + "blsp2_qup3_i2c_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { + .halt_reg = 0x2a004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2a004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup3_spi_apps_clk", + .parent_names = (const char *[]){ + "blsp2_qup3_spi_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { + .halt_reg = 0x2c008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2c008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup4_i2c_apps_clk", + .parent_names = (const char *[]){ + "blsp2_qup4_i2c_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { + .halt_reg = 0x2c004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2c004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup4_spi_apps_clk", + .parent_names = (const char *[]){ + "blsp2_qup4_spi_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_uart1_apps_clk = { + .halt_reg = 0x27004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x27004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_uart1_apps_clk", + .parent_names = (const char *[]){ + "blsp2_uart1_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_uart2_apps_clk = { + .halt_reg = 0x29004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x29004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_uart2_apps_clk", + .parent_names = (const char *[]){ + "blsp2_uart2_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk = { + .halt_reg = 0x38004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(10), + .hw.init = &(struct clk_init_data){ + .name = "gcc_boot_rom_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb2_axi_clk = { + .halt_reg = 0x5058, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cfg_noc_usb2_axi_clk", + .parent_names = (const char *[]){ + "usb20_master_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb3_axi_clk = { + .halt_reg = 0x5018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cfg_noc_usb3_axi_clk", + .parent_names = (const char *[]){ + "usb30_master_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_dcc_ahb_clk = { + .halt_reg = 0x84004, + .clkr = { + .enable_reg = 0x84004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_dcc_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk = { + .halt_reg = 0x64000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x64000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp1_clk", + .parent_names = (const char *[]){ + "gp1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk = { + .halt_reg = 0x65000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x65000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp2_clk", + .parent_names = (const char *[]){ + "gp2_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk = { + .halt_reg = 0x66000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x66000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp3_clk", + .parent_names = (const char *[]){ + "gp3_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_bimc_gfx_clk = { + .halt_reg = 0x71010, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x71010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_bimc_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_bimc_gfx_src_clk = { + .halt_reg = 0x7100c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x7100c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_bimc_gfx_src_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_cfg_ahb_clk = { + .halt_reg = 0x71004, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x71004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_gate2 gpll0_out_msscc = { + .udelay = 1, + .clkr = { + .enable_reg = 0x5200c, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data){ + .name = "gpll0_out_msscc", + .ops = &clk_gate2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_clk = { + .halt_reg = 0x5200c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x5200c, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_clk", + .parent_names = (const char *[]){ + "gpll0_out_main", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_div_clk = { + .halt_reg = 0x5200c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x5200c, + .enable_mask = BIT(3), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_div_clk", + .parent_names = (const char *[]){ + "gpll0_out_early_div", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { + .halt_reg = 0x71018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x71018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_snoc_dvm_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_hmss_ahb_clk = { + .halt_reg = 0x48000, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(21), + .hw.init = &(struct clk_init_data){ + .name = "gcc_hmss_ahb_clk", + .parent_names = (const char *[]){ + "hmss_ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_hmss_dvm_bus_clk = { + .halt_reg = 0x4808c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4808c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_hmss_dvm_bus_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_hmss_rbcpr_clk = { + .halt_reg = 0x48008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x48008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_hmss_rbcpr_clk", + .parent_names = (const char *[]){ + "hmss_rbcpr_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mmss_gpll0_clk = { + .halt_reg = 0x5200c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x5200c, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mmss_gpll0_clk", + .parent_names = (const char *[]){ + "gpll0_out_main", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mmss_gpll0_div_clk = { + .halt_reg = 0x5200c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x5200c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mmss_gpll0_div_clk", + .parent_names = (const char *[]){ + "gpll0_out_early_div", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { + .halt_reg = 0x9004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mmss_noc_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mmss_sys_noc_axi_clk = { + .halt_reg = 0x9000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mmss_sys_noc_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_cfg_ahb_clk = { + .halt_reg = 0x8a000, + .clkr = { + .enable_reg = 0x8a000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = { + .halt_reg = 0x8a004, + .clkr = { + .enable_reg = 0x8a004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_mnoc_bimc_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_q6_bimc_axi_clk = { + .halt_reg = 0x8a040, + .clkr = { + .enable_reg = 0x8a040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_q6_bimc_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_snoc_axi_clk = { + .halt_reg = 0x8a03c, + .clkr = { + .enable_reg = 0x8a03c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_snoc_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk = { + .halt_reg = 0x3300c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3300c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm2_clk", + .parent_names = (const char *[]){ + "pdm2_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk = { + .halt_reg = 0x33004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x33004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_prng_ahb_clk = { + .halt_reg = 0x34004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(13), + .hw.init = &(struct clk_init_data){ + .name = "gcc_prng_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qspi_ahb_clk = { + .halt_reg = 0x4d004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4d004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qspi_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qspi_ser_clk = { + .halt_reg = 0x4d008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4d008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qspi_ser_clk", + .parent_names = (const char *[]){ + "qspi_ser_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_rx0_usb2_clkref_clk = { + .halt_reg = 0x88018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x88018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_rx0_usb2_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_rx1_usb2_clkref_clk = { + .halt_reg = 0x88014, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x88014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_rx1_usb2_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_rx2_qlink_clkref_clk = { + .halt_reg = 0x88034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x88034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_rx2_qlink_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ahb_clk = { + .halt_reg = 0x16008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x16008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_apps_clk = { + .halt_reg = 0x16004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x16004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_apps_clk", + .parent_names = (const char *[]){ + "sdcc1_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ice_core_clk = { + .halt_reg = 0x1600c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1600c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_ice_core_clk", + .parent_names = (const char *[]){ + "sdcc1_ice_core_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_ahb_clk = { + .halt_reg = 0x14008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x14008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc2_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_apps_clk = { + .halt_reg = 0x14004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x14004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc2_apps_clk", + .parent_names = (const char *[]){ + "sdcc2_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_ahb_clk = { + .halt_reg = 0x7500c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x7500c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_axi_clk = { + .halt_reg = 0x75008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x75008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_axi_clk", + .parent_names = (const char *[]){ + "ufs_axi_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_axi_hw_ctl_clk = { + .halt_reg = 0x75008, + .clkr = { + .enable_reg = 0x75008, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_axi_hw_ctl_clk", + .parent_names = (const char *[]){ + "gcc_ufs_axi_clk", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_hw_ctl_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_clkref_clk = { + .halt_reg = 0x88008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x88008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_ice_core_clk = { + .halt_reg = 0x7600c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x7600c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_ice_core_clk", + .parent_names = (const char *[]){ + "ufs_ice_core_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_ice_core_hw_ctl_clk = { + .halt_reg = 0x7600c, + .clkr = { + .enable_reg = 0x7600c, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_ice_core_hw_ctl_clk", + .parent_names = (const char *[]){ + "gcc_ufs_ice_core_clk", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_hw_ctl_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_aux_clk = { + .halt_reg = 0x76040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x76040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_aux_clk", + .parent_names = (const char *[]){ + "ufs_phy_aux_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_aux_hw_ctl_clk = { + .halt_reg = 0x76040, + .clkr = { + .enable_reg = 0x76040, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_aux_hw_ctl_clk", + .parent_names = (const char *[]){ + "gcc_ufs_phy_aux_clk", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_hw_ctl_ops, + }, + }, +}; + +static struct clk_gate2 gcc_ufs_rx_symbol_0_clk = { + .udelay = 500, + .clkr = { + .enable_reg = 0x75014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_rx_symbol_0_clk", + .ops = &clk_gate2_ops, + }, + }, +}; + +static struct clk_gate2 gcc_ufs_rx_symbol_1_clk = { + .udelay = 500, + .clkr = { + .enable_reg = 0x7605c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_rx_symbol_1_clk", + .ops = &clk_gate2_ops, + }, + }, +}; + +static struct clk_gate2 gcc_ufs_tx_symbol_0_clk = { + .udelay = 500, + .clkr = { + .enable_reg = 0x75010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_tx_symbol_0_clk", + .ops = &clk_gate2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_unipro_core_clk = { + .halt_reg = 0x76008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x76008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_unipro_core_clk", + .parent_names = (const char *[]){ + "ufs_unipro_core_clk_src", + }, + .flags = CLK_SET_RATE_PARENT, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_unipro_core_hw_ctl_clk = { + .halt_reg = 0x76008, + .clkr = { + .enable_reg = 0x76008, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_unipro_core_hw_ctl_clk", + .parent_names = (const char *[]){ + "gcc_ufs_unipro_core_clk", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_hw_ctl_ops, + }, + }, +}; + +static struct clk_branch gcc_usb20_master_clk = { + .halt_reg = 0x2f004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2f004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb20_master_clk", + .parent_names = (const char *[]){ + "usb20_master_clk_src", + }, + .flags = CLK_SET_RATE_PARENT, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb20_mock_utmi_clk = { + .halt_reg = 0x2f00c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2f00c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb20_mock_utmi_clk", + .parent_names = (const char *[]){ + "usb20_mock_utmi_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb20_sleep_clk = { + .halt_reg = 0x2f008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2f008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb20_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_master_clk = { + .halt_reg = 0xf008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xf008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_master_clk", + .parent_names = (const char *[]){ + "usb30_master_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_mock_utmi_clk = { + .halt_reg = 0xf010, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xf010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_mock_utmi_clk", + .parent_names = (const char *[]){ + "usb30_mock_utmi_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_sleep_clk = { + .halt_reg = 0xf00c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xf00c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_clkref_clk = { + .halt_reg = 0x8800c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8800c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_phy_aux_clk = { + .halt_reg = 0x50000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x50000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_phy_aux_clk", + .parent_names = (const char *[]){ + "usb3_phy_aux_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_gate2 gcc_usb3_phy_pipe_clk = { + .udelay = 50, + .clkr = { + .enable_reg = 0x50004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_phy_pipe_clk", + .ops = &clk_gate2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { + .halt_reg = 0x6a004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6a004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb_phy_cfg_ahb2phy_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk = { + .halt_reg = 0x7d014, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x7d014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "hlos1_vote_lpass_adsp_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch hlos1_vote_turing_adsp_smmu_clk = { + .halt_reg = 0x7d048, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x7d048, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "hlos1_vote_turing_adsp_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch hlos2_vote_turing_adsp_smmu_clk = { + .halt_reg = 0x7e048, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x7e048, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "hlos2_vote_turing_adsp_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_fixed_factor gcc_ce1_ahb_m_clk = { + .hw.init = &(struct clk_init_data){ + .name = "gcc_ce1_ahb_m_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_fixed_factor gcc_ce1_axi_m_clk = { + .hw.init = &(struct clk_init_data){ + .name = "gcc_ce1_axi_m_clk", + .ops = &clk_dummy_ops, + }, +}; + +struct clk_hw *gcc_sdm660_hws[] = { + [GCC_XO] = &xo.hw, + [GCC_GPLL0_EARLY_DIV] = &gpll0_out_early_div.hw, + [GCC_GPLL1_EARLY_DIV] = &gpll1_out_early_div.hw, + [GCC_CE1_AHB_M_CLK] = &gcc_ce1_ahb_m_clk.hw, + [GCC_CE1_AXI_M_CLK] = &gcc_ce1_axi_m_clk.hw, +}; + +static struct clk_regmap *gcc_660_clocks[] = { + [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, + [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, + [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, + [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, + [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, + [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, + [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, + [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, + [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, + [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, + [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, + [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, + [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, + [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, + [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, + [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, + [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, + [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, + [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, + [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, + [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr, + [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr, + [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, + [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr, + [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr, + [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, + [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, + [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, + [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, + [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, + [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, + [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, + [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, + [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, + [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, + [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, + [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, + [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, + [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, + [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, + [GCC_CFG_NOC_USB2_AXI_CLK] = &gcc_cfg_noc_usb2_axi_clk.clkr, + [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr, + [GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr, + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, + [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, + [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr, + [GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr, + [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, + [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr, + [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr, + [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, + [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr, + [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr, + [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr, + [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr, + [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr, + [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr, + [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr, + [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, + [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr, + [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, + [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, + [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, + [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, + [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, + [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr, + [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr, + [GCC_RX0_USB2_CLKREF_CLK] = &gcc_rx0_usb2_clkref_clk.clkr, + [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr, + [GCC_RX2_QLINK_CLKREF_CLK] = &gcc_rx2_qlink_clkref_clk.clkr, + [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, + [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, + [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, + [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr, + [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr, + [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, + [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr, + [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr, + [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr, + [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr, + [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr, + [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr, + [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr, + [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr, + [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr, + [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, + [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, + [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, + [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr, + [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, + [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, + [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, + [GP1_CLK_SRC] = &gp1_clk_src.clkr, + [GP2_CLK_SRC] = &gp2_clk_src.clkr, + [GP3_CLK_SRC] = &gp3_clk_src.clkr, + [GPLL0] = &gpll0_out_main.clkr, + [GPLL1] = &gpll1_out_main.clkr, + [GPLL4] = &gpll4_out_main.clkr, + [HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &hlos1_vote_lpass_adsp_smmu_clk.clkr, + [HMSS_AHB_CLK_SRC] = &hmss_ahb_clk_src.clkr, + [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr, + [HMSS_GPLL4_CLK_SRC] = &hmss_gpll4_clk_src.clkr, + [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr, + [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, + [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr, + [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, + [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr, + [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, + [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, + [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr, + [UFS_PHY_AUX_CLK_SRC] = &ufs_phy_aux_clk_src.clkr, + [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr, + [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr, + [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr, + [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, + [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, + [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, + [GPLL0_OUT_MSSCC] = &gpll0_out_msscc.clkr, + [GCC_UFS_AXI_HW_CTL_CLK] = &gcc_ufs_axi_hw_ctl_clk.clkr, + [GCC_UFS_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_ice_core_hw_ctl_clk.clkr, + [GCC_UFS_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_aux_hw_ctl_clk.clkr, + [GCC_UFS_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_unipro_core_hw_ctl_clk.clkr, + [HLOS1_VOTE_TURING_ADSP_SMMU_CLK] = + &hlos1_vote_turing_adsp_smmu_clk.clkr, + [HLOS2_VOTE_TURING_ADSP_SMMU_CLK] = + &hlos2_vote_turing_adsp_smmu_clk.clkr, +}; + +static const struct qcom_reset_map gcc_660_resets[] = { + [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, + [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, + [GCC_UFS_BCR] = { 0x75000 }, + [GCC_USB3_DP_PHY_BCR] = { 0x50028 }, + [GCC_USB3_PHY_BCR] = { 0x50020 }, + [GCC_USB3PHY_PHY_BCR] = { 0x50024 }, + [GCC_USB_20_BCR] = { 0x2f000 }, + [GCC_USB_30_BCR] = { 0xf000 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, +}; + +static const struct regmap_config gcc_660_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x94000, + .fast_io = true, +}; + +static const struct qcom_cc_desc gcc_660_desc = { + .config = &gcc_660_regmap_config, + .clks = gcc_660_clocks, + .num_clks = ARRAY_SIZE(gcc_660_clocks), + .hwclks = gcc_sdm660_hws, + .num_hwclks = ARRAY_SIZE(gcc_sdm660_hws), + .resets = gcc_660_resets, + .num_resets = ARRAY_SIZE(gcc_660_resets), +}; + +static const struct of_device_id gcc_660_match_table[] = { + { .compatible = "qcom,gcc-sdm660" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_660_match_table); + +static int gcc_660_probe(struct platform_device *pdev) +{ + int ret = 0; + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gcc_660_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* + * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be + * turned off by hardware during certain apps low power modes. + */ + regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); + + vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig"); + if (IS_ERR(vdd_dig.regulator[0])) { + if (!(PTR_ERR(vdd_dig.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_dig regulator\n"); + return PTR_ERR(vdd_dig.regulator[0]); + } + + vdd_dig_ao.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig_ao"); + if (IS_ERR(vdd_dig_ao.regulator[0])) { + if (!(PTR_ERR(vdd_dig_ao.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_dig_ao regulator\n"); + return PTR_ERR(vdd_dig_ao.regulator[0]); + } + + ret = qcom_cc_really_probe(pdev, &gcc_660_desc, regmap); + if (ret) { + dev_err(&pdev->dev, "Failed to register GCC clocks\n"); + return ret; + } + + /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */ + regmap_update_bits(regmap, 0x0902c, 0x3, 0x3); + regmap_update_bits(regmap, 0x71028, 0x3, 0x3); + + /* This clock is used for all MMSSCC register access */ + clk_prepare_enable(gcc_mmss_noc_cfg_ahb_clk.clkr.hw.clk); + + /* This clock is used for all GPUCC register access */ + clk_prepare_enable(gcc_gpu_cfg_ahb_clk.clkr.hw.clk); + + dev_info(&pdev->dev, "Registered GCC clocks\n"); + + return ret; +} + +static struct platform_driver gcc_660_driver = { + .probe = gcc_660_probe, + .driver = { + .name = "gcc-sdm660", + .of_match_table = gcc_660_match_table, + }, +}; + +static int __init gcc_660_init(void) +{ + return platform_driver_register(&gcc_660_driver); +} +core_initcall_sync(gcc_660_init); + +static void __exit gcc_660_exit(void) +{ + platform_driver_unregister(&gcc_660_driver); +} +module_exit(gcc_660_exit); + +/* Debug Mux for measure */ +static struct measure_clk_data debug_mux_priv = { + .xo_div4_cbcr = 0x43008, + .ctl_reg = 0x62004, + .status_reg = 0x62008, +}; + +static const char *const debug_mux_parent_names[] = { + "snoc_clk", + "cnoc_clk", + "cnoc_periph_clk", + "bimc_clk", + "ce1_clk", + "ipa_clk", + "gcc_aggre2_ufs_axi_clk", + "gcc_aggre2_usb3_axi_clk", + "gcc_bimc_gfx_clk", + "gcc_bimc_hmss_axi_clk", + "gcc_bimc_mss_q6_axi_clk", + "gcc_blsp1_ahb_clk", + "gcc_blsp1_qup1_i2c_apps_clk", + "gcc_blsp1_qup1_spi_apps_clk", + "gcc_blsp1_qup2_i2c_apps_clk", + "gcc_blsp1_qup2_spi_apps_clk", + "gcc_blsp1_qup3_i2c_apps_clk", + "gcc_blsp1_qup3_spi_apps_clk", + "gcc_blsp1_qup4_i2c_apps_clk", + "gcc_blsp1_qup4_spi_apps_clk", + "gcc_blsp1_uart1_apps_clk", + "gcc_blsp1_uart2_apps_clk", + "gcc_blsp2_ahb_clk", + "gcc_blsp2_qup1_i2c_apps_clk", + "gcc_blsp2_qup1_spi_apps_clk", + "gcc_blsp2_qup2_i2c_apps_clk", + "gcc_blsp2_qup2_spi_apps_clk", + "gcc_blsp2_qup3_i2c_apps_clk", + "gcc_blsp2_qup3_spi_apps_clk", + "gcc_blsp2_qup4_i2c_apps_clk", + "gcc_blsp2_qup4_spi_apps_clk", + "gcc_blsp2_uart1_apps_clk", + "gcc_blsp2_uart2_apps_clk", + "gcc_boot_rom_ahb_clk", + "gcc_ce1_ahb_m_clk", + "gcc_ce1_axi_m_clk", + "gcc_cfg_noc_usb2_axi_clk", + "gcc_cfg_noc_usb3_axi_clk", + "gcc_dcc_ahb_clk", + "gcc_gp1_clk", + "gcc_gp2_clk", + "gcc_gp3_clk", + "gcc_gpu_bimc_gfx_clk", + "gcc_gpu_bimc_gfx_src_clk", + "gcc_gpu_cfg_ahb_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gcc_hmss_ahb_clk", + "gcc_hmss_dvm_bus_clk", + "gcc_hmss_rbcpr_clk", + "gcc_mmss_noc_cfg_ahb_clk", + "gcc_mmss_sys_noc_axi_clk", + "gcc_mss_cfg_ahb_clk", + "gcc_mss_mnoc_bimc_axi_clk", + "gcc_mss_q6_bimc_axi_clk", + "gcc_mss_snoc_axi_clk", + "gcc_pdm2_clk", + "gcc_pdm_ahb_clk", + "gcc_prng_ahb_clk", + "gcc_qspi_ahb_clk", + "gcc_qspi_ser_clk", + "gcc_sdcc1_ahb_clk", + "gcc_sdcc1_apps_clk", + "gcc_sdcc1_ice_core_clk", + "gcc_sdcc2_ahb_clk", + "gcc_sdcc2_apps_clk", + "gcc_ufs_ahb_clk", + "gcc_ufs_axi_clk", + "gcc_ufs_ice_core_clk", + "gcc_ufs_phy_aux_clk", + "gcc_ufs_unipro_core_clk", + "gcc_usb20_master_clk", + "gcc_usb20_mock_utmi_clk", + "gcc_usb20_sleep_clk", + "gcc_usb30_master_clk", + "gcc_usb30_mock_utmi_clk", + "gcc_usb30_sleep_clk", + "gcc_usb3_phy_aux_clk", + "gcc_usb_phy_cfg_ahb2phy_clk", + "gcc_ufs_rx_symbol_0_clk", + "gcc_ufs_rx_symbol_1_clk", + "gcc_ufs_tx_symbol_0_clk", + "gcc_usb3_phy_pipe_clk", + "mmssnoc_axi_clk", + "mmss_bimc_smmu_ahb_clk", + "mmss_bimc_smmu_axi_clk", + "mmss_camss_ahb_clk", + "mmss_camss_cci_ahb_clk", + "mmss_camss_cci_clk", + "mmss_camss_cphy_csid0_clk", + "mmss_camss_cphy_csid1_clk", + "mmss_camss_cphy_csid2_clk", + "mmss_camss_cphy_csid3_clk", + "mmss_camss_cpp_ahb_clk", + "mmss_camss_cpp_axi_clk", + "mmss_camss_cpp_clk", + "mmss_camss_cpp_vbif_ahb_clk", + "mmss_camss_csi0_ahb_clk", + "mmss_camss_csi0_clk", + "mmss_camss_csi0phytimer_clk", + "mmss_camss_csi0pix_clk", + "mmss_camss_csi0rdi_clk", + "mmss_camss_csi1_ahb_clk", + "mmss_camss_csi1_clk", + "mmss_camss_csi1phytimer_clk", + "mmss_camss_csi1pix_clk", + "mmss_camss_csi1rdi_clk", + "mmss_camss_csi2_ahb_clk", + "mmss_camss_csi2_clk", + "mmss_camss_csi2phytimer_clk", + "mmss_camss_csi2pix_clk", + "mmss_camss_csi2rdi_clk", + "mmss_camss_csi3_ahb_clk", + "mmss_camss_csi3_clk", + "mmss_camss_csi3pix_clk", + "mmss_camss_csi3rdi_clk", + "mmss_camss_csi_vfe0_clk", + "mmss_camss_csi_vfe1_clk", + "mmss_camss_csiphy0_clk", + "mmss_camss_csiphy1_clk", + "mmss_camss_csiphy2_clk", + "mmss_camss_gp0_clk", + "mmss_camss_gp1_clk", + "mmss_camss_ispif_ahb_clk", + "mmss_camss_jpeg0_clk", + "mmss_camss_jpeg_ahb_clk", + "mmss_camss_jpeg_axi_clk", + "mmss_camss_mclk0_clk", + "mmss_camss_mclk1_clk", + "mmss_camss_mclk2_clk", + "mmss_camss_mclk3_clk", + "mmss_camss_micro_ahb_clk", + "mmss_camss_top_ahb_clk", + "mmss_camss_vfe0_ahb_clk", + "mmss_camss_vfe0_clk", + "mmss_camss_vfe0_stream_clk", + "mmss_camss_vfe1_ahb_clk", + "mmss_camss_vfe1_clk", + "mmss_camss_vfe1_stream_clk", + "mmss_camss_vfe_vbif_ahb_clk", + "mmss_camss_vfe_vbif_axi_clk", + "mmss_csiphy_ahb2crif_clk", + "mmss_mdss_ahb_clk", + "mmss_mdss_axi_clk", + "mmss_mdss_byte0_clk", + "mmss_mdss_byte0_intf_clk", + "mmss_mdss_byte1_clk", + "mmss_mdss_byte1_intf_clk", + "mmss_mdss_dp_aux_clk", + "mmss_mdss_dp_crypto_clk", + "mmss_mdss_dp_gtc_clk", + "mmss_mdss_dp_link_clk", + "mmss_mdss_dp_link_intf_clk", + "mmss_mdss_dp_pixel_clk", + "mmss_mdss_esc0_clk", + "mmss_mdss_esc1_clk", + "mmss_mdss_hdmi_dp_ahb_clk", + "mmss_mdss_mdp_clk", + "mmss_mdss_pclk0_clk", + "mmss_mdss_pclk1_clk", + "mmss_mdss_rot_clk", + "mmss_mdss_vsync_clk", + "mmss_misc_ahb_clk", + "mmss_misc_cxo_clk", + "mmss_mnoc_ahb_clk", + "mmss_snoc_dvm_axi_clk", + "mmss_video_ahb_clk", + "mmss_video_axi_clk", + "mmss_video_core_clk", + "mmss_video_subcore0_clk", + "gpucc_gfx3d_clk", + "gpucc_rbbmtimer_clk", + "gpucc_rbcpr_clk", + "pwrcl_clk", + "perfcl_clk", +}; + +static struct clk_debug_mux gcc_debug_mux = { + .priv = &debug_mux_priv, + .en_mask = BIT(16), + .mask = 0x3FF, + MUX_SRC_LIST( + { "snoc_clk", 0x000 }, + { "cnoc_clk", 0x00E }, + { "cnoc_periph_clk", 0x198 }, + { "bimc_clk", 0x14E }, + { "ce1_clk", 0x097 }, + { "ipa_clk", 0x11b }, + { "gcc_aggre2_ufs_axi_clk", 0x10B }, + { "gcc_aggre2_usb3_axi_clk", 0x10A }, + { "gcc_bimc_gfx_clk", 0x0AC }, + { "gcc_bimc_hmss_axi_clk", 0x0BB }, + { "gcc_bimc_mss_q6_axi_clk", 0x0A3 }, + { "gcc_blsp1_ahb_clk", 0x04A }, + { "gcc_blsp1_qup1_i2c_apps_clk", 0x04D }, + { "gcc_blsp1_qup1_spi_apps_clk", 0x04C }, + { "gcc_blsp1_qup2_i2c_apps_clk", 0x051 }, + { "gcc_blsp1_qup2_spi_apps_clk", 0x050 }, + { "gcc_blsp1_qup3_i2c_apps_clk", 0x055 }, + { "gcc_blsp1_qup3_spi_apps_clk", 0x054 }, + { "gcc_blsp1_qup4_i2c_apps_clk", 0x059 }, + { "gcc_blsp1_qup4_spi_apps_clk", 0x058 }, + { "gcc_blsp1_uart1_apps_clk", 0x04E }, + { "gcc_blsp1_uart2_apps_clk", 0x052 }, + { "gcc_blsp2_ahb_clk", 0x05E }, + { "gcc_blsp2_qup1_i2c_apps_clk", 0x061 }, + { "gcc_blsp2_qup1_spi_apps_clk", 0x060 }, + { "gcc_blsp2_qup2_i2c_apps_clk", 0x065 }, + { "gcc_blsp2_qup2_spi_apps_clk", 0x064 }, + { "gcc_blsp2_qup3_i2c_apps_clk", 0x069 }, + { "gcc_blsp2_qup3_spi_apps_clk", 0x068 }, + { "gcc_blsp2_qup4_i2c_apps_clk", 0x06D }, + { "gcc_blsp2_qup4_spi_apps_clk", 0x06C }, + { "gcc_blsp2_uart1_apps_clk", 0x062 }, + { "gcc_blsp2_uart2_apps_clk", 0x066 }, + { "gcc_boot_rom_ahb_clk", 0x07A }, + { "gcc_ce1_ahb_m_clk", 0x099 }, + { "gcc_ce1_axi_m_clk", 0x098 }, + { "gcc_cfg_noc_usb2_axi_clk", 0x168 }, + { "gcc_cfg_noc_usb3_axi_clk", 0x014 }, + { "gcc_dcc_ahb_clk", 0x119 }, + { "gcc_gp1_clk", 0x0DF }, + { "gcc_gp2_clk", 0x0E0 }, + { "gcc_gp3_clk", 0x0E1 }, + { "gcc_gpu_bimc_gfx_clk", 0x13F }, + { "gcc_gpu_bimc_gfx_src_clk", 0x13E }, + { "gcc_gpu_cfg_ahb_clk", 0x13B }, + { "gcc_gpu_snoc_dvm_gfx_clk", 0x141 }, + { "gcc_hmss_ahb_clk", 0x0BA }, + { "gcc_hmss_dvm_bus_clk", 0x0BF }, + { "gcc_hmss_rbcpr_clk", 0x0BC }, + { "gcc_mmss_noc_cfg_ahb_clk", 0x020 }, + { "gcc_mmss_sys_noc_axi_clk", 0x01F }, + { "gcc_mss_cfg_ahb_clk", 0x11F }, + { "gcc_mss_mnoc_bimc_axi_clk", 0x120 }, + { "gcc_mss_q6_bimc_axi_clk", 0x124 }, + { "gcc_mss_snoc_axi_clk", 0x123 }, + { "gcc_pdm2_clk", 0x074 }, + { "gcc_pdm_ahb_clk", 0x072 }, + { "gcc_prng_ahb_clk", 0x075 }, + { "gcc_qspi_ahb_clk", 0x172 }, + { "gcc_qspi_ser_clk", 0x173 }, + { "gcc_sdcc1_ahb_clk", 0x16E }, + { "gcc_sdcc1_apps_clk", 0x16D }, + { "gcc_sdcc1_ice_core_clk", 0x16F }, + { "gcc_sdcc2_ahb_clk", 0x047 }, + { "gcc_sdcc2_apps_clk", 0x046 }, + { "gcc_ufs_ahb_clk", 0x0EB }, + { "gcc_ufs_axi_clk", 0x0EA }, + { "gcc_ufs_ice_core_clk", 0x0F1 }, + { "gcc_ufs_phy_aux_clk", 0x0F2 }, + { "gcc_ufs_unipro_core_clk", 0x0F0 }, + { "gcc_usb20_master_clk", 0x169 }, + { "gcc_usb20_mock_utmi_clk", 0x16B }, + { "gcc_usb20_sleep_clk", 0x16A }, + { "gcc_usb30_master_clk", 0x03C }, + { "gcc_usb30_mock_utmi_clk", 0x03E }, + { "gcc_usb30_sleep_clk", 0x03D }, + { "gcc_usb3_phy_aux_clk", 0x03F }, + { "gcc_usb_phy_cfg_ahb2phy_clk", 0x045 }, + { "gcc_ufs_rx_symbol_0_clk", 0x0ED }, + { "gcc_ufs_rx_symbol_1_clk", 0x162 }, + { "gcc_ufs_tx_symbol_0_clk", 0x0EC }, + { "gcc_usb3_phy_pipe_clk", 0x040 }, + { "mmssnoc_axi_clk", 0x22, MMCC, 0x004 }, + { "mmss_bimc_smmu_ahb_clk", 0x22, MMCC, 0x00C }, + { "mmss_bimc_smmu_axi_clk", 0x22, MMCC, 0x00D }, + { "mmss_camss_ahb_clk", 0x22, MMCC, 0x037 }, + { "mmss_camss_cci_ahb_clk", 0x22, MMCC, 0x02E }, + { "mmss_camss_cci_clk", 0x22, MMCC, 0x02D }, + { "mmss_camss_cphy_csid0_clk", 0x22, MMCC, 0x08D }, + { "mmss_camss_cphy_csid1_clk", 0x22, MMCC, 0x08E }, + { "mmss_camss_cphy_csid2_clk", 0x22, MMCC, 0x08F }, + { "mmss_camss_cphy_csid3_clk", 0x22, MMCC, 0x090 }, + { "mmss_camss_cpp_ahb_clk", 0x22, MMCC, 0x03B }, + { "mmss_camss_cpp_axi_clk", 0x22, MMCC, 0x07A }, + { "mmss_camss_cpp_clk", 0x22, MMCC, 0x03A }, + { "mmss_camss_cpp_vbif_ahb_clk", 0x22, MMCC, 0x073 }, + { "mmss_camss_csi0_ahb_clk", 0x22, MMCC, 0x042 }, + { "mmss_camss_csi0_clk", 0x22, MMCC, 0x041 }, + { "mmss_camss_csi0phytimer_clk", 0x22, MMCC, 0x02F }, + { "mmss_camss_csi0pix_clk", 0x22, MMCC, 0x045 }, + { "mmss_camss_csi0rdi_clk", 0x22, MMCC, 0x044 }, + { "mmss_camss_csi1_ahb_clk", 0x22, MMCC, 0x047 }, + { "mmss_camss_csi1_clk", 0x22, MMCC, 0x046 }, + { "mmss_camss_csi1phytimer_clk", 0x22, MMCC, 0x030 }, + { "mmss_camss_csi1pix_clk", 0x22, MMCC, 0x04A }, + { "mmss_camss_csi1rdi_clk", 0x22, MMCC, 0x049 }, + { "mmss_camss_csi2_ahb_clk", 0x22, MMCC, 0x04C }, + { "mmss_camss_csi2_clk", 0x22, MMCC, 0x04B }, + { "mmss_camss_csi2phytimer_clk", 0x22, MMCC, 0x031 }, + { "mmss_camss_csi2pix_clk", 0x22, MMCC, 0x04F }, + { "mmss_camss_csi2rdi_clk", 0x22, MMCC, 0x04E }, + { "mmss_camss_csi3_ahb_clk", 0x22, MMCC, 0x051 }, + { "mmss_camss_csi3_clk", 0x22, MMCC, 0x050 }, + { "mmss_camss_csi3pix_clk", 0x22, MMCC, 0x054 }, + { "mmss_camss_csi3rdi_clk", 0x22, MMCC, 0x053 }, + { "mmss_camss_csi_vfe0_clk", 0x22, MMCC, 0x03F }, + { "mmss_camss_csi_vfe1_clk", 0x22, MMCC, 0x040 }, + { "mmss_camss_csiphy0_clk", 0x22, MMCC, 0x043 }, + { "mmss_camss_csiphy1_clk", 0x22, MMCC, 0x085 }, + { "mmss_camss_csiphy2_clk", 0x22, MMCC, 0x088 }, + { "mmss_camss_gp0_clk", 0x22, MMCC, 0x027 }, + { "mmss_camss_gp1_clk", 0x22, MMCC, 0x028 }, + { "mmss_camss_ispif_ahb_clk", 0x22, MMCC, 0x033 }, + { "mmss_camss_jpeg0_clk", 0x22, MMCC, 0x032 }, + { "mmss_camss_jpeg_ahb_clk", 0x22, MMCC, 0x035 }, + { "mmss_camss_jpeg_axi_clk", 0x22, MMCC, 0x036 }, + { "mmss_camss_mclk0_clk", 0x22, MMCC, 0x029 }, + { "mmss_camss_mclk1_clk", 0x22, MMCC, 0x02A }, + { "mmss_camss_mclk2_clk", 0x22, MMCC, 0x02B }, + { "mmss_camss_mclk3_clk", 0x22, MMCC, 0x02C }, + { "mmss_camss_micro_ahb_clk", 0x22, MMCC, 0x026 }, + { "mmss_camss_top_ahb_clk", 0x22, MMCC, 0x025 }, + { "mmss_camss_vfe0_ahb_clk", 0x22, MMCC, 0x086 }, + { "mmss_camss_vfe0_clk", 0x22, MMCC, 0x038 }, + { "mmss_camss_vfe0_stream_clk", 0x22, MMCC, 0x071 }, + { "mmss_camss_vfe1_ahb_clk", 0x22, MMCC, 0x087 }, + { "mmss_camss_vfe1_clk", 0x22, MMCC, 0x039 }, + { "mmss_camss_vfe1_stream_clk", 0x22, MMCC, 0x072 }, + { "mmss_camss_vfe_vbif_ahb_clk", 0x22, MMCC, 0x03C }, + { "mmss_camss_vfe_vbif_axi_clk", 0x22, MMCC, 0x03D }, + { "mmss_csiphy_ahb2crif_clk", 0x22, MMCC, 0x0B8 }, + { "mmss_mdss_ahb_clk", 0x22, MMCC, 0x022 }, + { "mmss_mdss_axi_clk", 0x22, MMCC, 0x024 }, + { "mmss_mdss_byte0_clk", 0x22, MMCC, 0x01E }, + { "mmss_mdss_byte0_intf_clk", 0x22, MMCC, 0x0AD }, + { "mmss_mdss_byte1_clk", 0x22, MMCC, 0x01F }, + { "mmss_mdss_byte1_intf_clk", 0x22, MMCC, 0x0B6 }, + { "mmss_mdss_dp_aux_clk", 0x22, MMCC, 0x09C }, + { "mmss_mdss_dp_crypto_clk", 0x22, MMCC, 0x09A }, + { "mmss_mdss_dp_gtc_clk", 0x22, MMCC, 0x09D }, + { "mmss_mdss_dp_link_clk", 0x22, MMCC, 0x098 }, + { "mmss_mdss_dp_link_intf_clk", 0x22, MMCC, 0x099 }, + { "mmss_mdss_dp_pixel_clk", 0x22, MMCC, 0x09B }, + { "mmss_mdss_esc0_clk", 0x22, MMCC, 0x020 }, + { "mmss_mdss_esc1_clk", 0x22, MMCC, 0x021 }, + { "mmss_mdss_hdmi_dp_ahb_clk", 0x22, MMCC, 0x023 }, + { "mmss_mdss_mdp_clk", 0x22, MMCC, 0x014 }, + { "mmss_mdss_pclk0_clk", 0x22, MMCC, 0x016 }, + { "mmss_mdss_pclk1_clk", 0x22, MMCC, 0x017 }, + { "mmss_mdss_rot_clk", 0x22, MMCC, 0x012 }, + { "mmss_mdss_vsync_clk", 0x22, MMCC, 0x01C }, + { "mmss_misc_ahb_clk", 0x22, MMCC, 0x003 }, + { "mmss_misc_cxo_clk", 0x22, MMCC, 0x077 }, + { "mmss_mnoc_ahb_clk", 0x22, MMCC, 0x001 }, + { "mmss_snoc_dvm_axi_clk", 0x22, MMCC, 0x013 }, + { "mmss_video_ahb_clk", 0x22, MMCC, 0x011 }, + { "mmss_video_axi_clk", 0x22, MMCC, 0x00F }, + { "mmss_video_core_clk", 0x22, MMCC, 0x00E }, + { "mmss_video_subcore0_clk", 0x22, MMCC, 0x01A }, + { "gpucc_gfx3d_clk", 0x13d, GPU, 0x008 }, + { "gpucc_rbbmtimer_clk", 0x13d, GPU, 0x005 }, + { "gpucc_rbcpr_clk", 0x13d, GPU, 0x003 }, + { "pwrcl_clk", 0x0c0, CPU, 0x000, 0x3, 8, 0x0FF }, + { "perfcl_clk", 0x0c0, CPU, 0x100, 0x3, 8, 0x0FF }, + ), + .hw.init = &(struct clk_init_data){ + .name = "gcc_debug_mux", + .ops = &clk_debug_mux_ops, + .parent_names = debug_mux_parent_names, + .num_parents = ARRAY_SIZE(debug_mux_parent_names), + .flags = CLK_IS_MEASURE, + }, +}; + +static const struct of_device_id clk_debug_match_table[] = { + { .compatible = "qcom,gcc-debug-sdm660" }, + {} +}; + +static int clk_debug_660_probe(struct platform_device *pdev) +{ + struct resource *res; + struct clk *clk; + int ret = 0, count; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbg_offset"); + if (!res) { + dev_err(&pdev->dev, "Failed to get debug offset.\n"); + return -EINVAL; + } + gcc_debug_mux.debug_offset = res->start; + + clk = devm_clk_get(&pdev->dev, "xo_clk_src"); + if (IS_ERR(clk)) { + if (PTR_ERR(clk) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get xo clock\n"); + return PTR_ERR(clk); + } + + debug_mux_priv.cxo = clk; + + ret = of_property_read_u32(pdev->dev.of_node, "qcom,cc-count", + &count); + if (ret < 0) { + dev_err(&pdev->dev, "Num of debug clock controller not specified\n"); + return ret; + } + + if (!count) { + dev_err(&pdev->dev, "Count of CC cannot be zero\n"); + return -EINVAL; + } + + gcc_debug_mux.num_parent_regmap = count; + + gcc_debug_mux.regmap = devm_kzalloc(&pdev->dev, + sizeof(struct regmap *) * count, GFP_KERNEL); + if (!gcc_debug_mux.regmap) + return -ENOMEM; + + if (of_get_property(pdev->dev.of_node, "qcom,gcc", NULL)) { + gcc_debug_mux.regmap[GCC] = + syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "qcom,gcc"); + if (IS_ERR(gcc_debug_mux.regmap[GCC])) + return PTR_ERR(gcc_debug_mux.regmap[GCC]); + } + + if (of_get_property(pdev->dev.of_node, "qcom,cpu", NULL)) { + gcc_debug_mux.regmap[CPU] = + syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "qcom,cpu"); + if (IS_ERR(gcc_debug_mux.regmap[CPU])) + return PTR_ERR(gcc_debug_mux.regmap[CPU]); + } + + if (of_get_property(pdev->dev.of_node, "qcom,mmss", NULL)) { + gcc_debug_mux.regmap[MMCC] = + syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "qcom,mmss"); + if (IS_ERR(gcc_debug_mux.regmap[MMCC])) + return PTR_ERR(gcc_debug_mux.regmap[MMCC]); + + /* Clear the DBG_CLK_DIV bits of the MMSS debug register */ + regmap_update_bits(gcc_debug_mux.regmap[MMCC], 0x0, + 0x60000, 0x0); + } + + if (of_get_property(pdev->dev.of_node, "qcom,gpu", NULL)) { + gcc_debug_mux.regmap[GPU] = + syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "qcom,gpu"); + if (IS_ERR(gcc_debug_mux.regmap[GPU])) + return PTR_ERR(gcc_debug_mux.regmap[GPU]); + + /* Clear the DBG_CLK_DIV bits of the GPU debug register */ + regmap_update_bits(gcc_debug_mux.regmap[GPU], 0x0, + 0x60000, 0x0); + } + + clk = devm_clk_register(&pdev->dev, &gcc_debug_mux.hw); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "Unable to register GCC debug mux\n"); + return PTR_ERR(clk); + } + + dev_info(&pdev->dev, "Registered debug mux successfully\n"); + + return ret; +} + +static struct platform_driver clk_debug_driver = { + .probe = clk_debug_660_probe, + .driver = { + .name = "gcc-debug-sdm660", + .of_match_table = clk_debug_match_table, + .owner = THIS_MODULE, + }, +}; + +int __init clk_debug_660_init(void) +{ + return platform_driver_register(&clk_debug_driver); +} +fs_initcall(clk_debug_660_init); diff --git a/drivers/clk/qcom/gpucc-msmfalcon.c b/drivers/clk/qcom/gpucc-msmfalcon.c deleted file mode 100644 index 9b7dd907a6f3..000000000000 --- a/drivers/clk/qcom/gpucc-msmfalcon.c +++ /dev/null @@ -1,498 +0,0 @@ -/* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "clk-alpha-pll.h" -#include "common.h" -#include "clk-regmap.h" -#include "clk-pll.h" -#include "clk-rcg.h" -#include "clk-branch.h" -#include "vdd-level-falcon.h" - -#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } -#define F_GFX(f, s, h, m, n, sf) { (f), (s), (2 * (h) - 1), (m), (n), (sf) } - -static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner); -static DEFINE_VDD_REGULATORS(vdd_mx, VDD_DIG_NUM, 1, vdd_corner); -static DEFINE_VDD_REGS_INIT(vdd_gfx, 1); - -enum { - P_CORE_BI_PLL_TEST_SE, - P_GPLL0_OUT_MAIN, - P_GPLL0_OUT_MAIN_DIV, - P_GPU_PLL0_PLL_OUT_MAIN, - P_GPU_PLL1_PLL_OUT_MAIN, - P_XO, -}; - -static const struct parent_map gpucc_parent_map_0[] = { - { P_XO, 0 }, - { P_GPLL0_OUT_MAIN, 5 }, - { P_GPLL0_OUT_MAIN_DIV, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gpucc_parent_names_0[] = { - "cxo_a", - "gcc_gpu_gpll0_clk", - "gcc_gpu_gpll0_div_clk", - "core_bi_pll_test_se", -}; - -static const struct parent_map gpucc_parent_map_1[] = { - { P_XO, 0 }, - { P_GPU_PLL0_PLL_OUT_MAIN, 1 }, - { P_GPU_PLL1_PLL_OUT_MAIN, 3 }, - { P_GPLL0_OUT_MAIN, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const gpucc_parent_names_1[] = { - "xo", - "gpu_pll0_pll_out_main", - "gpu_pll1_pll_out_main", - "gcc_gpu_gpll0_clk", - "core_bi_pll_test_se", -}; - -static struct pll_vco gpu_vco[] = { - { 1000000000, 2000000000, 0 }, - { 500000000, 1000000000, 2 }, - { 250000000, 500000000, 3 }, -}; - -/* 800MHz configuration */ -static const struct pll_config gpu_pll0_config = { - .l = 0x29, - .config_ctl_val = 0x4001055b, - .alpha = 0xaaaaab00, - .alpha_u = 0xaa, - .alpha_en_mask = BIT(24), - .vco_val = 0x2 << 20, - .vco_mask = 0x3 << 20, - .main_output_mask = 0x1, -}; - -static struct pll_vco_data pll_data[] = { - /* Frequency post-div */ - { 640000000, 0x1 }, -}; - -static struct clk_alpha_pll gpu_pll0_pll_out_main = { - .offset = 0x0, - .vco_table = gpu_vco, - .num_vco = ARRAY_SIZE(gpu_vco), - .vco_data = pll_data, - .num_vco_data = ARRAY_SIZE(pll_data), - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "gpu_pll0_pll_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - VDD_GPU_PLL_FMAX_MAP1(LOW_L1, 1500000000), - }, - }, -}; - -static struct clk_alpha_pll gpu_pll1_pll_out_main = { - .offset = 0x40, - .vco_table = gpu_vco, - .num_vco = ARRAY_SIZE(gpu_vco), - .vco_data = pll_data, - .num_vco_data = ARRAY_SIZE(pll_data), - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "gpu_pll1_pll_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - VDD_GPU_PLL_FMAX_MAP1(LOW_L1, 1500000000), - }, - }, -}; - -/* GFX clock init data */ -static struct clk_init_data gpu_clks_init[] = { - [0] = { - .name = "gfx3d_clk_src", - .parent_names = gpucc_parent_names_1, - .num_parents = 3, - .ops = &clk_gfx3d_src_ops, - .flags = CLK_SET_RATE_PARENT, - }, - [1] = { - .name = "gpucc_gfx3d_clk", - .parent_names = (const char *[]){ - "gfx3d_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - .flags = CLK_SET_RATE_PARENT, - .vdd_class = &vdd_gfx, - }, -}; - -/* - * Frequencies and PLL configuration - * The PLL source would be to ping-pong between GPU-PLL0 - * and GPU-PLL1. - * ==================================================== - * | F | PLL SRC Freq | PLL postdiv | RCG Div | - * ==================================================== - * | 160000000 | 640000000 | 2 | 2 | - * | 266000000 | 532000000 | 1 | 2 | - * | 370000000 | 740000000 | 1 | 2 | - * | 465000000 | 930000000 | 1 | 2 | - * | 588000000 | 1176000000 | 1 | 2 | - * | 647000000 | 1294000000 | 1 | 2 | - * | 700000000 | 1400000000 | 1 | 2 | - * | 750000000 | 1500000000 | 1 | 2 | - * ==================================================== -*/ - -static const struct freq_tbl ftbl_gfx3d_clk_src[] = { - F_GFX( 19200000, 0, 1, 0, 0, 0), - F_GFX(160000000, 0, 2, 0, 0, 640000000), - F_GFX(266000000, 0, 2, 0, 0, 532000000), - F_GFX(370000000, 0, 2, 0, 0, 740000000), - F_GFX(465000000, 0, 2, 0, 0, 930000000), - F_GFX(588000000, 0, 2, 0, 0, 1176000000), - F_GFX(647000000, 0, 2, 0, 0, 1294000000), - F_GFX(700000000, 0, 2, 0, 0, 1400000000), - F_GFX(750000000, 0, 2, 0, 0, 1500000000), - { } -}; - -static const struct freq_tbl ftbl_gfx3d_clk_src_triton[] = { - F_GFX( 19200000, 0, 1, 0, 0, 0), - F_GFX(160000000, 0, 2, 0, 0, 640000000), - F_GFX(240000000, 0, 2, 0, 0, 480000000), - F_GFX(370000000, 0, 2, 0, 0, 740000000), - F_GFX(465000000, 0, 2, 0, 0, 930000000), - F_GFX(588000000, 0, 2, 0, 0, 1176000000), - F_GFX(647000000, 0, 2, 0, 0, 1294000000), - F_GFX(700000000, 0, 2, 0, 0, 1400000000), - F_GFX(775000000, 0, 2, 0, 0, 1550000000), - { } -}; - -static struct clk_rcg2 gfx3d_clk_src = { - .cmd_rcgr = 0x1070, - .mnd_width = 0, - .hid_width = 5, - .freq_tbl = ftbl_gfx3d_clk_src, - .parent_map = gpucc_parent_map_1, - .flags = FORCE_ENABLE_RCGR, - .clkr.hw.init = &gpu_clks_init[0], -}; - -static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = { - F(19200000, P_XO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 rbbmtimer_clk_src = { - .cmd_rcgr = 0x10b0, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gpucc_parent_map_0, - .freq_tbl = ftbl_rbbmtimer_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "rbbmtimer_clk_src", - .parent_names = gpucc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP1(MIN, 19200000), - }, -}; - -static const struct freq_tbl ftbl_rbcpr_clk_src[] = { - F(19200000, P_XO, 1, 0, 0), - F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0), - { } -}; - -static struct clk_rcg2 rbcpr_clk_src = { - .cmd_rcgr = 0x1030, - .mnd_width = 0, - .hid_width = 5, - .parent_map = gpucc_parent_map_0, - .freq_tbl = ftbl_rbcpr_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "rbcpr_clk_src", - .parent_names = gpucc_parent_names_0, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - MIN, 19200000, - NOMINAL, 50000000), - }, -}; - -static struct clk_branch gpucc_cxo_clk = { - .halt_reg = 0x1020, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1020, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpucc_cxo_clk", - .parent_names = (const char *[]) { - "cxo_a", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gpucc_gfx3d_clk = { - .halt_reg = 0x1098, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1098, - .enable_mask = BIT(0), - .hw.init = &gpu_clks_init[1], - }, -}; - -static struct clk_branch gpucc_rbbmtimer_clk = { - .halt_reg = 0x10d0, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x10d0, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpucc_rbbmtimer_clk", - .parent_names = (const char *[]){ - "rbbmtimer_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gpucc_rbcpr_clk = { - .halt_reg = 0x1054, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1054, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpucc_rbcpr_clk", - .parent_names = (const char *[]){ - "rbcpr_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_regmap *gpucc_falcon_clocks[] = { - [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, - [GPU_PLL0_PLL] = &gpu_pll0_pll_out_main.clkr, - [GPU_PLL1_PLL] = &gpu_pll1_pll_out_main.clkr, - [GPUCC_CXO_CLK] = &gpucc_cxo_clk.clkr, - [GPUCC_GFX3D_CLK] = &gpucc_gfx3d_clk.clkr, - [GPUCC_RBBMTIMER_CLK] = &gpucc_rbbmtimer_clk.clkr, - [GPUCC_RBCPR_CLK] = &gpucc_rbcpr_clk.clkr, - [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr, - [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, -}; - -static const struct regmap_config gpucc_falcon_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0x9034, - .fast_io = true, -}; - -static const struct qcom_cc_desc gpucc_falcon_desc = { - .config = &gpucc_falcon_regmap_config, - .clks = gpucc_falcon_clocks, - .num_clks = ARRAY_SIZE(gpucc_falcon_clocks), -}; - -static const struct of_device_id gpucc_falcon_match_table[] = { - { .compatible = "qcom,gpucc-msmfalcon" }, - { .compatible = "qcom,gpucc-msmtriton" }, - { } -}; -MODULE_DEVICE_TABLE(of, gpucc_falcon_match_table); - -static int of_get_fmax_vdd_class(struct platform_device *pdev, - struct clk_hw *hw, char *prop_name, u32 index) -{ - struct device_node *of = pdev->dev.of_node; - int prop_len, i, j; - struct clk_vdd_class *vdd = hw->init->vdd_class; - int num = vdd->num_regulators + 1; - u32 *array; - - if (!of_find_property(of, prop_name, &prop_len)) { - dev_err(&pdev->dev, "missing %s\n", prop_name); - return -EINVAL; - } - - prop_len /= sizeof(u32); - if (prop_len % num) { - dev_err(&pdev->dev, "bad length %d\n", prop_len); - return -EINVAL; - } - - prop_len /= num; - vdd->level_votes = devm_kzalloc(&pdev->dev, prop_len * sizeof(int), - GFP_KERNEL); - if (!vdd->level_votes) - return -ENOMEM; - - vdd->vdd_uv = devm_kzalloc(&pdev->dev, - prop_len * sizeof(int) * (num - 1), GFP_KERNEL); - if (!vdd->vdd_uv) - return -ENOMEM; - - gpu_clks_init[index].rate_max = devm_kzalloc(&pdev->dev, prop_len * - sizeof(unsigned long), GFP_KERNEL); - if (!gpu_clks_init[index].rate_max) - return -ENOMEM; - - array = devm_kzalloc(&pdev->dev, prop_len * sizeof(u32) * num, - GFP_KERNEL); - if (!array) - return -ENOMEM; - - of_property_read_u32_array(of, prop_name, array, prop_len * num); - for (i = 0; i < prop_len; i++) { - gpu_clks_init[index].rate_max[i] = array[num * i]; - for (j = 1; j < num; j++) { - vdd->vdd_uv[(num - 1) * i + (j - 1)] = - array[num * i + j]; - } - } - - devm_kfree(&pdev->dev, array); - vdd->num_levels = prop_len; - vdd->cur_level = prop_len; - gpu_clks_init[index].num_rate_max = prop_len; - - return 0; -} - -static int gpucc_falcon_probe(struct platform_device *pdev) -{ - int ret = 0; - struct regmap *regmap; - bool is_triton = 0; - - regmap = qcom_cc_map(pdev, &gpucc_falcon_desc); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); - - /* CX Regulator for RBBMTimer and RBCPR clock */ - vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig_gfx"); - if (IS_ERR(vdd_dig.regulator[0])) { - if (!(PTR_ERR(vdd_dig.regulator[0]) == -EPROBE_DEFER)) - dev_err(&pdev->dev, - "Unable to get vdd_dig regulator\n"); - return PTR_ERR(vdd_dig.regulator[0]); - } - - /* Mx Regulator for GPU-PLLs */ - vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx_gfx"); - if (IS_ERR(vdd_mx.regulator[0])) { - if (!(PTR_ERR(vdd_mx.regulator[0]) == -EPROBE_DEFER)) - dev_err(&pdev->dev, - "Unable to get vdd_mx regulator\n"); - return PTR_ERR(vdd_mx.regulator[0]); - } - - /* GFX Rail Regulator for GFX3D clock */ - vdd_gfx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_gfx"); - if (IS_ERR(vdd_gfx.regulator[0])) { - if (!(PTR_ERR(vdd_gfx.regulator[0]) == -EPROBE_DEFER)) - dev_err(&pdev->dev, - "Unable to get vdd_gfx regulator\n"); - return PTR_ERR(vdd_gfx.regulator[0]); - } - - is_triton = of_device_is_compatible(pdev->dev.of_node, - "qcom,gpucc-msmtriton"); - if (is_triton) { - gpu_pll0_pll_out_main.clkr.hw.init->rate_max[VDD_DIG_LOW_L1] - = 1550000000; - gpu_pll1_pll_out_main.clkr.hw.init->rate_max[VDD_DIG_LOW_L1] - = 1550000000; - /* Add new frequency table */ - gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_triton; - } - - /* GFX rail fmax data linked to branch clock */ - of_get_fmax_vdd_class(pdev, &gpucc_gfx3d_clk.clkr.hw, - "qcom,gfxfreq-corner", 1); - - clk_alpha_pll_configure(&gpu_pll0_pll_out_main, regmap, - &gpu_pll0_config); - clk_alpha_pll_configure(&gpu_pll1_pll_out_main, regmap, - &gpu_pll0_config); - - ret = qcom_cc_really_probe(pdev, &gpucc_falcon_desc, regmap); - if (ret) { - dev_err(&pdev->dev, "Failed to register GPUCC clocks\n"); - return ret; - } - - clk_prepare_enable(gpucc_cxo_clk.clkr.hw.clk); - - dev_info(&pdev->dev, "Registered GPUCC clocks\n"); - - return ret; -} - -static struct platform_driver gpucc_falcon_driver = { - .probe = gpucc_falcon_probe, - .driver = { - .name = "gpucc-msmfalcon", - .of_match_table = gpucc_falcon_match_table, - }, -}; - -static int __init gpucc_falcon_init(void) -{ - return platform_driver_register(&gpucc_falcon_driver); -} -core_initcall_sync(gpucc_falcon_init); - -static void __exit gpucc_falcon_exit(void) -{ - platform_driver_unregister(&gpucc_falcon_driver); -} -module_exit(gpucc_falcon_exit); diff --git a/drivers/clk/qcom/gpucc-sdm660.c b/drivers/clk/qcom/gpucc-sdm660.c new file mode 100644 index 000000000000..b16b17451c76 --- /dev/null +++ b/drivers/clk/qcom/gpucc-sdm660.c @@ -0,0 +1,498 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk-alpha-pll.h" +#include "common.h" +#include "clk-regmap.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-branch.h" +#include "vdd-level-660.h" + +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } +#define F_GFX(f, s, h, m, n, sf) { (f), (s), (2 * (h) - 1), (m), (n), (sf) } + +static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner); +static DEFINE_VDD_REGULATORS(vdd_mx, VDD_DIG_NUM, 1, vdd_corner); +static DEFINE_VDD_REGS_INIT(vdd_gfx, 1); + +enum { + P_CORE_BI_PLL_TEST_SE, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_PLL0_PLL_OUT_MAIN, + P_GPU_PLL1_PLL_OUT_MAIN, + P_XO, +}; + +static const struct parent_map gpucc_parent_map_0[] = { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gpucc_parent_names_0[] = { + "cxo_a", + "gcc_gpu_gpll0_clk", + "gcc_gpu_gpll0_div_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map gpucc_parent_map_1[] = { + { P_XO, 0 }, + { P_GPU_PLL0_PLL_OUT_MAIN, 1 }, + { P_GPU_PLL1_PLL_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gpucc_parent_names_1[] = { + "xo", + "gpu_pll0_pll_out_main", + "gpu_pll1_pll_out_main", + "gcc_gpu_gpll0_clk", + "core_bi_pll_test_se", +}; + +static struct pll_vco gpu_vco[] = { + { 1000000000, 2000000000, 0 }, + { 500000000, 1000000000, 2 }, + { 250000000, 500000000, 3 }, +}; + +/* 800MHz configuration */ +static const struct pll_config gpu_pll0_config = { + .l = 0x29, + .config_ctl_val = 0x4001055b, + .alpha = 0xaaaaab00, + .alpha_u = 0xaa, + .alpha_en_mask = BIT(24), + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, +}; + +static struct pll_vco_data pll_data[] = { + /* Frequency post-div */ + { 640000000, 0x1 }, +}; + +static struct clk_alpha_pll gpu_pll0_pll_out_main = { + .offset = 0x0, + .vco_table = gpu_vco, + .num_vco = ARRAY_SIZE(gpu_vco), + .vco_data = pll_data, + .num_vco_data = ARRAY_SIZE(pll_data), + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_pll0_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + VDD_GPU_PLL_FMAX_MAP1(LOW_L1, 1500000000), + }, + }, +}; + +static struct clk_alpha_pll gpu_pll1_pll_out_main = { + .offset = 0x40, + .vco_table = gpu_vco, + .num_vco = ARRAY_SIZE(gpu_vco), + .vco_data = pll_data, + .num_vco_data = ARRAY_SIZE(pll_data), + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_pll1_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + VDD_GPU_PLL_FMAX_MAP1(LOW_L1, 1500000000), + }, + }, +}; + +/* GFX clock init data */ +static struct clk_init_data gpu_clks_init[] = { + [0] = { + .name = "gfx3d_clk_src", + .parent_names = gpucc_parent_names_1, + .num_parents = 3, + .ops = &clk_gfx3d_src_ops, + .flags = CLK_SET_RATE_PARENT, + }, + [1] = { + .name = "gpucc_gfx3d_clk", + .parent_names = (const char *[]){ + "gfx3d_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = CLK_SET_RATE_PARENT, + .vdd_class = &vdd_gfx, + }, +}; + +/* + * Frequencies and PLL configuration + * The PLL source would be to ping-pong between GPU-PLL0 + * and GPU-PLL1. + * ==================================================== + * | F | PLL SRC Freq | PLL postdiv | RCG Div | + * ==================================================== + * | 160000000 | 640000000 | 2 | 2 | + * | 266000000 | 532000000 | 1 | 2 | + * | 370000000 | 740000000 | 1 | 2 | + * | 465000000 | 930000000 | 1 | 2 | + * | 588000000 | 1176000000 | 1 | 2 | + * | 647000000 | 1294000000 | 1 | 2 | + * | 700000000 | 1400000000 | 1 | 2 | + * | 750000000 | 1500000000 | 1 | 2 | + * ==================================================== +*/ + +static const struct freq_tbl ftbl_gfx3d_clk_src[] = { + F_GFX( 19200000, 0, 1, 0, 0, 0), + F_GFX(160000000, 0, 2, 0, 0, 640000000), + F_GFX(266000000, 0, 2, 0, 0, 532000000), + F_GFX(370000000, 0, 2, 0, 0, 740000000), + F_GFX(465000000, 0, 2, 0, 0, 930000000), + F_GFX(588000000, 0, 2, 0, 0, 1176000000), + F_GFX(647000000, 0, 2, 0, 0, 1294000000), + F_GFX(700000000, 0, 2, 0, 0, 1400000000), + F_GFX(750000000, 0, 2, 0, 0, 1500000000), + { } +}; + +static const struct freq_tbl ftbl_gfx3d_clk_src_triton[] = { + F_GFX( 19200000, 0, 1, 0, 0, 0), + F_GFX(160000000, 0, 2, 0, 0, 640000000), + F_GFX(240000000, 0, 2, 0, 0, 480000000), + F_GFX(370000000, 0, 2, 0, 0, 740000000), + F_GFX(465000000, 0, 2, 0, 0, 930000000), + F_GFX(588000000, 0, 2, 0, 0, 1176000000), + F_GFX(647000000, 0, 2, 0, 0, 1294000000), + F_GFX(700000000, 0, 2, 0, 0, 1400000000), + F_GFX(775000000, 0, 2, 0, 0, 1550000000), + { } +}; + +static struct clk_rcg2 gfx3d_clk_src = { + .cmd_rcgr = 0x1070, + .mnd_width = 0, + .hid_width = 5, + .freq_tbl = ftbl_gfx3d_clk_src, + .parent_map = gpucc_parent_map_1, + .flags = FORCE_ENABLE_RCGR, + .clkr.hw.init = &gpu_clks_init[0], +}; + +static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 rbbmtimer_clk_src = { + .cmd_rcgr = 0x10b0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpucc_parent_map_0, + .freq_tbl = ftbl_rbbmtimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "rbbmtimer_clk_src", + .parent_names = gpucc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1(MIN, 19200000), + }, +}; + +static const struct freq_tbl ftbl_rbcpr_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0), + { } +}; + +static struct clk_rcg2 rbcpr_clk_src = { + .cmd_rcgr = 0x1030, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpucc_parent_map_0, + .freq_tbl = ftbl_rbcpr_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "rbcpr_clk_src", + .parent_names = gpucc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + MIN, 19200000, + NOMINAL, 50000000), + }, +}; + +static struct clk_branch gpucc_cxo_clk = { + .halt_reg = 0x1020, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1020, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_cxo_clk", + .parent_names = (const char *[]) { + "cxo_a", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_gfx3d_clk = { + .halt_reg = 0x1098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1098, + .enable_mask = BIT(0), + .hw.init = &gpu_clks_init[1], + }, +}; + +static struct clk_branch gpucc_rbbmtimer_clk = { + .halt_reg = 0x10d0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10d0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_rbbmtimer_clk", + .parent_names = (const char *[]){ + "rbbmtimer_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_rbcpr_clk = { + .halt_reg = 0x1054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_rbcpr_clk", + .parent_names = (const char *[]){ + "rbcpr_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *gpucc_660_clocks[] = { + [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, + [GPU_PLL0_PLL] = &gpu_pll0_pll_out_main.clkr, + [GPU_PLL1_PLL] = &gpu_pll1_pll_out_main.clkr, + [GPUCC_CXO_CLK] = &gpucc_cxo_clk.clkr, + [GPUCC_GFX3D_CLK] = &gpucc_gfx3d_clk.clkr, + [GPUCC_RBBMTIMER_CLK] = &gpucc_rbbmtimer_clk.clkr, + [GPUCC_RBCPR_CLK] = &gpucc_rbcpr_clk.clkr, + [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr, + [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, +}; + +static const struct regmap_config gpucc_660_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9034, + .fast_io = true, +}; + +static const struct qcom_cc_desc gpucc_660_desc = { + .config = &gpucc_660_regmap_config, + .clks = gpucc_660_clocks, + .num_clks = ARRAY_SIZE(gpucc_660_clocks), +}; + +static const struct of_device_id gpucc_660_match_table[] = { + { .compatible = "qcom,gpucc-sdm660" }, + { .compatible = "qcom,gpucc-msmtriton" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpucc_660_match_table); + +static int of_get_fmax_vdd_class(struct platform_device *pdev, + struct clk_hw *hw, char *prop_name, u32 index) +{ + struct device_node *of = pdev->dev.of_node; + int prop_len, i, j; + struct clk_vdd_class *vdd = hw->init->vdd_class; + int num = vdd->num_regulators + 1; + u32 *array; + + if (!of_find_property(of, prop_name, &prop_len)) { + dev_err(&pdev->dev, "missing %s\n", prop_name); + return -EINVAL; + } + + prop_len /= sizeof(u32); + if (prop_len % num) { + dev_err(&pdev->dev, "bad length %d\n", prop_len); + return -EINVAL; + } + + prop_len /= num; + vdd->level_votes = devm_kzalloc(&pdev->dev, prop_len * sizeof(int), + GFP_KERNEL); + if (!vdd->level_votes) + return -ENOMEM; + + vdd->vdd_uv = devm_kzalloc(&pdev->dev, + prop_len * sizeof(int) * (num - 1), GFP_KERNEL); + if (!vdd->vdd_uv) + return -ENOMEM; + + gpu_clks_init[index].rate_max = devm_kzalloc(&pdev->dev, prop_len * + sizeof(unsigned long), GFP_KERNEL); + if (!gpu_clks_init[index].rate_max) + return -ENOMEM; + + array = devm_kzalloc(&pdev->dev, prop_len * sizeof(u32) * num, + GFP_KERNEL); + if (!array) + return -ENOMEM; + + of_property_read_u32_array(of, prop_name, array, prop_len * num); + for (i = 0; i < prop_len; i++) { + gpu_clks_init[index].rate_max[i] = array[num * i]; + for (j = 1; j < num; j++) { + vdd->vdd_uv[(num - 1) * i + (j - 1)] = + array[num * i + j]; + } + } + + devm_kfree(&pdev->dev, array); + vdd->num_levels = prop_len; + vdd->cur_level = prop_len; + gpu_clks_init[index].num_rate_max = prop_len; + + return 0; +} + +static int gpucc_660_probe(struct platform_device *pdev) +{ + int ret = 0; + struct regmap *regmap; + bool is_triton = 0; + + regmap = qcom_cc_map(pdev, &gpucc_660_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* CX Regulator for RBBMTimer and RBCPR clock */ + vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig_gfx"); + if (IS_ERR(vdd_dig.regulator[0])) { + if (!(PTR_ERR(vdd_dig.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_dig regulator\n"); + return PTR_ERR(vdd_dig.regulator[0]); + } + + /* Mx Regulator for GPU-PLLs */ + vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx_gfx"); + if (IS_ERR(vdd_mx.regulator[0])) { + if (!(PTR_ERR(vdd_mx.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_mx regulator\n"); + return PTR_ERR(vdd_mx.regulator[0]); + } + + /* GFX Rail Regulator for GFX3D clock */ + vdd_gfx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_gfx"); + if (IS_ERR(vdd_gfx.regulator[0])) { + if (!(PTR_ERR(vdd_gfx.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_gfx regulator\n"); + return PTR_ERR(vdd_gfx.regulator[0]); + } + + is_triton = of_device_is_compatible(pdev->dev.of_node, + "qcom,gpucc-msmtriton"); + if (is_triton) { + gpu_pll0_pll_out_main.clkr.hw.init->rate_max[VDD_DIG_LOW_L1] + = 1550000000; + gpu_pll1_pll_out_main.clkr.hw.init->rate_max[VDD_DIG_LOW_L1] + = 1550000000; + /* Add new frequency table */ + gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_triton; + } + + /* GFX rail fmax data linked to branch clock */ + of_get_fmax_vdd_class(pdev, &gpucc_gfx3d_clk.clkr.hw, + "qcom,gfxfreq-corner", 1); + + clk_alpha_pll_configure(&gpu_pll0_pll_out_main, regmap, + &gpu_pll0_config); + clk_alpha_pll_configure(&gpu_pll1_pll_out_main, regmap, + &gpu_pll0_config); + + ret = qcom_cc_really_probe(pdev, &gpucc_660_desc, regmap); + if (ret) { + dev_err(&pdev->dev, "Failed to register GPUCC clocks\n"); + return ret; + } + + clk_prepare_enable(gpucc_cxo_clk.clkr.hw.clk); + + dev_info(&pdev->dev, "Registered GPUCC clocks\n"); + + return ret; +} + +static struct platform_driver gpucc_660_driver = { + .probe = gpucc_660_probe, + .driver = { + .name = "gpucc-sdm660", + .of_match_table = gpucc_660_match_table, + }, +}; + +static int __init gpucc_660_init(void) +{ + return platform_driver_register(&gpucc_660_driver); +} +core_initcall_sync(gpucc_660_init); + +static void __exit gpucc_660_exit(void) +{ + platform_driver_unregister(&gpucc_660_driver); +} +module_exit(gpucc_660_exit); diff --git a/drivers/clk/qcom/mdss/mdss-pll.c b/drivers/clk/qcom/mdss/mdss-pll.c index b51ab4f21561..f356be38a25c 100644 --- a/drivers/clk/qcom/mdss/mdss-pll.c +++ b/drivers/clk/qcom/mdss/mdss-pll.c @@ -133,9 +133,9 @@ static int mdss_pll_resource_parse(struct platform_device *pdev, pll_res->pll_interface_type = MDSS_DSI_PLL_8996; pll_res->target_id = MDSS_PLL_TARGET_8996; pll_res->revision = 2; - } else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_msmfalcon")) { + } else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_sdm660")) { pll_res->pll_interface_type = MDSS_DSI_PLL_8996; - pll_res->target_id = MDSS_PLL_TARGET_MSMFALCON; + pll_res->target_id = MDSS_PLL_TARGET_SDM660; pll_res->revision = 2; } else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8998")) { pll_res->pll_interface_type = MDSS_DSI_PLL_8998; @@ -382,7 +382,7 @@ static const struct of_device_id mdss_pll_dt_match[] = { {.compatible = "qcom,mdss_hdmi_pll_8996_v3_1p8"}, {.compatible = "qcom,mdss_dp_pll_8998"}, {.compatible = "qcom,mdss_hdmi_pll_8998"}, - {.compatible = "qcom,mdss_dsi_pll_msmfalcon"}, + {.compatible = "qcom,mdss_dsi_pll_sdm660"}, {} }; diff --git a/drivers/clk/qcom/mdss/mdss-pll.h b/drivers/clk/qcom/mdss/mdss-pll.h index 01664eaa815c..e0e62a0f379b 100644 --- a/drivers/clk/qcom/mdss/mdss-pll.h +++ b/drivers/clk/qcom/mdss/mdss-pll.h @@ -51,7 +51,7 @@ enum { enum { MDSS_PLL_TARGET_8996, - MDSS_PLL_TARGET_MSMFALCON, + MDSS_PLL_TARGET_SDM660, }; #define DFPS_MAX_NUM_OF_FRAME_RATES 20 diff --git a/drivers/clk/qcom/mmcc-msmfalcon.c b/drivers/clk/qcom/mmcc-msmfalcon.c deleted file mode 100644 index 59dbebd825fd..000000000000 --- a/drivers/clk/qcom/mmcc-msmfalcon.c +++ /dev/null @@ -1,3056 +0,0 @@ -/* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "clk-alpha-pll.h" -#include "clk-branch.h" -#include "common.h" -#include "clk-pll.h" -#include "clk-rcg.h" -#include "clk-regmap.h" -#include "clk-regmap-divider.h" -#include "clk-voter.h" -#include "reset.h" -#include "vdd-level-falcon.h" - -#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } -#define F_SLEW(f, s, h, m, n, src_freq) { (f), (s), (2 * (h) - 1), (m), (n), \ - (src_freq) } - -enum vdd_a_levels { - VDDA_NONE, - VDDA_LOWER, /* SVS2 */ - VDDA_NUM, -}; - -static int vdda_levels[] = { - 0, - 1800000, -}; - -#define VDDA_FMAX_MAP1(l1, f1) \ - .vdd_class = &vdda, \ - .rate_max = (unsigned long[VDDA_NUM]) { \ - [VDDA_##l1] = (f1), \ - }, \ - .num_rate_max = VDDA_NUM - -static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner); -static DEFINE_VDD_REGULATORS(vdd_mx, VDD_DIG_NUM, 1, vdd_corner); -static DEFINE_VDD_REGULATORS(vdda, VDDA_NUM, 1, vdda_levels); - -enum { - P_CORE_BI_PLL_TEST_SE, - P_CORE_PI_SLEEP_CLK, - P_CXO, - P_DP_PHY_PLL_LINK_CLK, - P_DP_PHY_PLL_VCO_DIV, - P_DSI0_PHY_PLL_OUT_BYTECLK, - P_DSI0_PHY_PLL_OUT_DSICLK, - P_DSI1_PHY_PLL_OUT_BYTECLK, - P_DSI1_PHY_PLL_OUT_DSICLK, - P_GPLL0_OUT_MAIN, - P_GPLL0_OUT_MAIN_DIV, - P_MMPLL0_PLL_OUT_MAIN, - P_MMPLL10_PLL_OUT_MAIN, - P_MMPLL3_PLL_OUT_MAIN, - P_MMPLL4_PLL_OUT_MAIN, - P_MMPLL5_PLL_OUT_MAIN, - P_MMPLL6_PLL_OUT_MAIN, - P_MMPLL7_PLL_OUT_MAIN, - P_MMPLL8_PLL_OUT_MAIN, -}; - -static const struct parent_map mmcc_parent_map_0[] = { - { P_CXO, 0 }, - { P_MMPLL0_PLL_OUT_MAIN, 1 }, - { P_MMPLL4_PLL_OUT_MAIN, 2 }, - { P_MMPLL7_PLL_OUT_MAIN, 3 }, - { P_MMPLL8_PLL_OUT_MAIN, 4 }, - { P_GPLL0_OUT_MAIN, 5 }, - { P_GPLL0_OUT_MAIN_DIV, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_0[] = { - "xo", - "mmpll0_pll_out_main", - "mmpll4_pll_out_main", - "mmpll7_pll_out_main", - "mmpll8_pll_out_main", - "gcc_mmss_gpll0_clk", - "gcc_mmss_gpll0_div_clk", - "core_bi_pll_test_se", -}; - -static const struct parent_map mmcc_parent_map_1[] = { - { P_CXO, 0 }, - { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, - { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_1[] = { - "xo", - "dsi0pll_byte_clk_mux", - "dsi1pll_byte_clk_mux", - "core_bi_pll_test_se", -}; - -static const struct parent_map mmcc_parent_map_2[] = { - { P_CXO, 0 }, - { P_MMPLL0_PLL_OUT_MAIN, 1 }, - { P_MMPLL4_PLL_OUT_MAIN, 2 }, - { P_MMPLL7_PLL_OUT_MAIN, 3 }, - { P_MMPLL10_PLL_OUT_MAIN, 4 }, - { P_GPLL0_OUT_MAIN, 5 }, - { P_GPLL0_OUT_MAIN_DIV, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_2[] = { - "xo", - "mmpll0_pll_out_main", - "mmpll4_pll_out_main", - "mmpll7_pll_out_main", - "mmpll10_pll_out_main", - "gcc_mmss_gpll0_clk", - "gcc_mmss_gpll0_div_clk", - "core_bi_pll_test_se", -}; - -static const struct parent_map mmcc_parent_map_3[] = { - { P_CXO, 0 }, - { P_MMPLL4_PLL_OUT_MAIN, 1 }, - { P_MMPLL7_PLL_OUT_MAIN, 2 }, - { P_MMPLL10_PLL_OUT_MAIN, 3 }, - { P_CORE_PI_SLEEP_CLK, 4 }, - { P_GPLL0_OUT_MAIN, 5 }, - { P_GPLL0_OUT_MAIN_DIV, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_3[] = { - "xo", - "mmpll4_pll_out_main", - "mmpll7_pll_out_main", - "mmpll10_pll_out_main", - "core_pi_sleep_clk", - "gcc_mmss_gpll0_clk", - "gcc_mmss_gpll0_div_clk", - "core_bi_pll_test_se", -}; - -static const struct parent_map mmcc_parent_map_4[] = { - { P_CXO, 0 }, - { P_MMPLL0_PLL_OUT_MAIN, 1 }, - { P_MMPLL7_PLL_OUT_MAIN, 2 }, - { P_MMPLL10_PLL_OUT_MAIN, 3 }, - { P_CORE_PI_SLEEP_CLK, 4 }, - { P_GPLL0_OUT_MAIN, 5 }, - { P_GPLL0_OUT_MAIN_DIV, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_4[] = { - "xo", - "mmpll0_pll_out_main", - "mmpll7_pll_out_main", - "mmpll10_pll_out_main", - "core_pi_sleep_clk", - "gcc_mmss_gpll0_clk", - "gcc_mmss_gpll0_div_clk", - "core_bi_pll_test_se", -}; - -static const struct parent_map mmcc_parent_map_5[] = { - { P_CXO, 0 }, - { P_GPLL0_OUT_MAIN, 5 }, - { P_GPLL0_OUT_MAIN_DIV, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_5[] = { - "xo", - "gcc_mmss_gpll0_clk", - "gcc_mmss_gpll0_div_clk", - "core_bi_pll_test_se", -}; - -static const struct parent_map mmcc_parent_map_6[] = { - { P_CXO, 0 }, - { P_DP_PHY_PLL_LINK_CLK, 1 }, - { P_DP_PHY_PLL_VCO_DIV, 2 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_6[] = { - "xo", - "dp_phy_pll_link_clk", - "dp_phy_pll_vco_div", - "core_bi_pll_test_se", -}; - -static const struct parent_map mmcc_parent_map_7[] = { - { P_CXO, 0 }, - { P_MMPLL0_PLL_OUT_MAIN, 1 }, - { P_MMPLL5_PLL_OUT_MAIN, 2 }, - { P_MMPLL7_PLL_OUT_MAIN, 3 }, - { P_GPLL0_OUT_MAIN, 5 }, - { P_GPLL0_OUT_MAIN_DIV, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_7[] = { - "xo", - "mmpll0_pll_out_main", - "mmpll5_pll_out_main", - "mmpll7_pll_out_main", - "gcc_mmss_gpll0_clk", - "gcc_mmss_gpll0_div_clk", - "core_bi_pll_test_se", -}; - -static const struct parent_map mmcc_parent_map_8[] = { - { P_CXO, 0 }, - { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, - { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_8[] = { - "xo", - "dsi0pll_pixel_clk_mux", - "dsi1pll_pixel_clk_mux", - "core_bi_pll_test_se", -}; - -static const struct parent_map mmcc_parent_map_9[] = { - { P_CXO, 0 }, - { P_MMPLL0_PLL_OUT_MAIN, 1 }, - { P_MMPLL4_PLL_OUT_MAIN, 2 }, - { P_MMPLL7_PLL_OUT_MAIN, 3 }, - { P_MMPLL10_PLL_OUT_MAIN, 4 }, - { P_MMPLL6_PLL_OUT_MAIN, 5 }, - { P_GPLL0_OUT_MAIN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_9[] = { - "xo", - "mmpll0_pll_out_main", - "mmpll4_pll_out_main", - "mmpll7_pll_out_main", - "mmpll10_pll_out_main", - "mmpll6_pll_out_main", - "gcc_mmss_gpll0_clk", - "core_bi_pll_test_se", -}; - -static const struct parent_map mmcc_parent_map_10[] = { - { P_CXO, 0 }, - { P_MMPLL0_PLL_OUT_MAIN, 1 }, - { P_GPLL0_OUT_MAIN, 5 }, - { P_GPLL0_OUT_MAIN_DIV, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_10[] = { - "xo", - "mmpll0_pll_out_main", - "gcc_mmss_gpll0_clk", - "gcc_mmss_gpll0_div_clk", - "core_bi_pll_test_se", -}; - -static const struct parent_map mmcc_parent_map_11[] = { - { P_CXO, 0 }, - { P_MMPLL0_PLL_OUT_MAIN, 1 }, - { P_MMPLL4_PLL_OUT_MAIN, 2 }, - { P_MMPLL7_PLL_OUT_MAIN, 3 }, - { P_MMPLL10_PLL_OUT_MAIN, 4 }, - { P_GPLL0_OUT_MAIN, 5 }, - { P_MMPLL6_PLL_OUT_MAIN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_11[] = { - "xo", - "mmpll0_pll_out_main", - "mmpll4_pll_out_main", - "mmpll7_pll_out_main", - "mmpll10_pll_out_main", - "gcc_mmss_gpll0_clk", - "mmpll6_pll_out_main", - "core_bi_pll_test_se", -}; - -static const struct parent_map mmcc_parent_map_12[] = { - { P_CXO, 0 }, - { P_MMPLL0_PLL_OUT_MAIN, 1 }, - { P_MMPLL8_PLL_OUT_MAIN, 2 }, - { P_MMPLL3_PLL_OUT_MAIN, 3 }, - { P_MMPLL6_PLL_OUT_MAIN, 4 }, - { P_GPLL0_OUT_MAIN, 5 }, - { P_MMPLL7_PLL_OUT_MAIN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, -}; - -static const char * const mmcc_parent_names_12[] = { - "xo", - "mmpll0_pll_out_main", - "mmpll8_pll_out_main", - "mmpll3_pll_out_main", - "mmpll6_pll_out_main", - "gcc_mmss_gpll0_clk", - "mmpll7_pll_out_main", - "core_bi_pll_test_se", -}; - -/* Voteable PLL */ -static struct clk_alpha_pll mmpll0_pll_out_main = { - .offset = 0xc000, - .clkr = { - .enable_reg = 0x1f0, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmpll0_pll_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 404000000, - LOW, 808000000), - }, - }, -}; - -static struct clk_alpha_pll mmpll6_pll_out_main = { - .offset = 0xf0, - .clkr = { - .enable_reg = 0x1f0, - .enable_mask = BIT(2), - .hw.init = &(struct clk_init_data){ - .name = "mmpll6_pll_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 540000000, - LOW_L1, 1080000000), - }, - }, -}; - -/* APSS controlled PLLs */ -static struct pll_vco vco[] = { - { 1000000000, 2000000000, 0 }, - { 750000000, 1500000000, 1 }, - { 500000000, 1000000000, 2 }, - { 250000000, 500000000, 3 }, -}; - -static const struct pll_config mmpll10_config = { - .l = 0x1e, - .config_ctl_val = 0x00004289, - .main_output_mask = 0x1, -}; - -static struct clk_alpha_pll mmpll10_pll_out_main = { - .offset = 0x190, - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "mmpll10_pll_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - VDDA_FMAX_MAP1(LOWER, 576000000), - }, - }, -}; - -static struct pll_vco mmpll3_vco[] = { - { 750000000, 1500000000, 1 }, -}; - -static const struct pll_config mmpll3_config = { - .l = 0x2e, - .config_ctl_val = 0x4001055b, - .vco_val = 0x1 << 20, - .vco_mask = 0x3 << 20, - .main_output_mask = 0x1, -}; - -static struct clk_alpha_pll mmpll3_pll_out_main = { - .offset = 0x0, - .vco_table = mmpll3_vco, - .num_vco = ARRAY_SIZE(mmpll3_vco), - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "mmpll3_pll_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_slew_ops, - VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 441600000, - NOMINAL, 1036800000), - }, - }, -}; - -static const struct pll_config mmpll4_config = { - .l = 0x28, - .config_ctl_val = 0x4001055b, - .vco_val = 0x2 << 20, - .vco_mask = 0x3 << 20, - .main_output_mask = 0x1, -}; - -static struct clk_alpha_pll mmpll4_pll_out_main = { - .offset = 0x50, - .vco_table = vco, - .num_vco = ARRAY_SIZE(vco), - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "mmpll4_pll_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 384000000, - LOW, 768000000), - }, - }, -}; - -static const struct pll_config mmpll5_config = { - .l = 0x2a, - .config_ctl_val = 0x4001055b, - .alpha_u = 0xf8, - .alpha_en_mask = BIT(24), - .vco_val = 0x2 << 20, - .vco_mask = 0x3 << 20, - .main_output_mask = 0x1, -}; - -static struct clk_alpha_pll mmpll5_pll_out_main = { - .offset = 0xa0, - .vco_table = vco, - .num_vco = ARRAY_SIZE(vco), - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "mmpll5_pll_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 421500000, - LOW, 825000000), - }, - }, -}; - -static const struct pll_config mmpll7_config = { - .l = 0x32, - .config_ctl_val = 0x4001055b, - .vco_val = 0x2 << 20, - .vco_mask = 0x3 << 20, - .main_output_mask = 0x1, -}; - -static struct clk_alpha_pll mmpll7_pll_out_main = { - .offset = 0x140, - .vco_table = vco, - .num_vco = ARRAY_SIZE(vco), - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "mmpll7_pll_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 480000000, - LOW, 960000000), - }, - }, -}; - -static const struct pll_config mmpll8_config = { - .l = 0x30, - .alpha_u = 0x70, - .alpha_en_mask = BIT(24), - .config_ctl_val = 0x4001055b, - .vco_val = 0x2 << 20, - .vco_mask = 0x3 << 20, - .main_output_mask = 0x1, -}; - -static struct clk_alpha_pll mmpll8_pll_out_main = { - .offset = 0x1c0, - .vco_table = vco, - .num_vco = ARRAY_SIZE(vco), - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "mmpll8_pll_out_main", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 465000000, - LOW, 930000000), - }, - }, -}; - -static const struct freq_tbl ftbl_ahb_clk_src[] = { - F(19200000, P_CXO, 1, 0, 0), - F(40000000, P_GPLL0_OUT_MAIN_DIV, 7.5, 0, 0), - F(80800000, P_MMPLL0_PLL_OUT_MAIN, 10, 0, 0), - { } -}; - -static struct clk_rcg2 ahb_clk_src = { - .cmd_rcgr = 0x5000, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_10, - .freq_tbl = ftbl_ahb_clk_src, - .flags = FORCE_ENABLE_RCGR, - .clkr.hw.init = &(struct clk_init_data){ - .name = "ahb_clk_src", - .parent_names = mmcc_parent_names_10, - .num_parents = 5, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 19200000, - LOW, 40000000, - NOMINAL, 80800000), - }, -}; - -static struct clk_rcg2 byte0_clk_src = { - .cmd_rcgr = 0x2120, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_1, - .clkr.hw.init = &(struct clk_init_data){ - .name = "byte0_clk_src", - .parent_names = mmcc_parent_names_1, - .num_parents = 4, - .ops = &clk_byte2_ops, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - VDD_DIG_FMAX_MAP3( - LOWER, 131250000, - LOW, 210000000, - NOMINAL, 262500000), - }, -}; - -static struct clk_rcg2 byte1_clk_src = { - .cmd_rcgr = 0x2140, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_1, - .clkr.hw.init = &(struct clk_init_data){ - .name = "byte1_clk_src", - .parent_names = mmcc_parent_names_1, - .num_parents = 4, - .ops = &clk_byte2_ops, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - VDD_DIG_FMAX_MAP3( - LOWER, 131250000, - LOW, 210000000, - NOMINAL, 262500000), - }, -}; - -static const struct freq_tbl ftbl_camss_gp0_clk_src[] = { - F(10000, P_CXO, 16, 1, 120), - F(24000, P_CXO, 16, 1, 50), - F(6000000, P_GPLL0_OUT_MAIN_DIV, 10, 1, 5), - F(12000000, P_GPLL0_OUT_MAIN_DIV, 10, 2, 5), - F(13043478, P_GPLL0_OUT_MAIN_DIV, 1, 1, 23), - F(24000000, P_GPLL0_OUT_MAIN_DIV, 1, 2, 25), - F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN_DIV, 3, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - { } -}; - -static struct clk_rcg2 camss_gp0_clk_src = { - .cmd_rcgr = 0x3420, - .mnd_width = 8, - .hid_width = 5, - .parent_map = mmcc_parent_map_4, - .freq_tbl = ftbl_camss_gp0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "camss_gp0_clk_src", - .parent_names = mmcc_parent_names_4, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 50000000, - LOW, 100000000, - NOMINAL, 200000000), - }, -}; - -static struct clk_rcg2 camss_gp1_clk_src = { - .cmd_rcgr = 0x3450, - .mnd_width = 8, - .hid_width = 5, - .parent_map = mmcc_parent_map_4, - .freq_tbl = ftbl_camss_gp0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "camss_gp1_clk_src", - .parent_names = mmcc_parent_names_4, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 50000000, - LOW, 100000000, - NOMINAL, 200000000), - }, -}; - -static const struct freq_tbl ftbl_cci_clk_src[] = { - F(37500000, P_GPLL0_OUT_MAIN_DIV, 8, 0, 0), - F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0), - F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), - { } -}; - -static struct clk_rcg2 cci_clk_src = { - .cmd_rcgr = 0x3300, - .mnd_width = 8, - .hid_width = 5, - .parent_map = mmcc_parent_map_4, - .freq_tbl = ftbl_cci_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cci_clk_src", - .parent_names = mmcc_parent_names_4, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 37500000, - LOW, 50000000, - NOMINAL, 100000000), - }, -}; - -static const struct freq_tbl ftbl_cpp_clk_src[] = { - F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), - F(256000000, P_MMPLL4_PLL_OUT_MAIN, 3, 0, 0), - F(384000000, P_MMPLL4_PLL_OUT_MAIN, 2, 0, 0), - F(480000000, P_MMPLL7_PLL_OUT_MAIN, 2, 0, 0), - F(540000000, P_MMPLL6_PLL_OUT_MAIN, 2, 0, 0), - F(576000000, P_MMPLL10_PLL_OUT_MAIN, 1, 0, 0), - { } -}; - -static struct clk_rcg2 cpp_clk_src = { - .cmd_rcgr = 0x3640, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_11, - .freq_tbl = ftbl_cpp_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "cpp_clk_src", - .parent_names = mmcc_parent_names_11, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP6( - LOWER, 120000000, - LOW, 256000000, - LOW_L1, 384000000, - NOMINAL, 480000000, - NOMINAL_L1, 540000000, - HIGH, 576000000), - }, -}; - -static const struct freq_tbl ftbl_csi0_clk_src[] = { - F(100000000, P_GPLL0_OUT_MAIN_DIV, 3, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(310000000, P_MMPLL8_PLL_OUT_MAIN, 3, 0, 0), - F(404000000, P_MMPLL0_PLL_OUT_MAIN, 2, 0, 0), - F(465000000, P_MMPLL8_PLL_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 csi0_clk_src = { - .cmd_rcgr = 0x3090, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_0, - .freq_tbl = ftbl_csi0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "csi0_clk_src", - .parent_names = mmcc_parent_names_0, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP5( - LOWER, 100000000, - LOW, 200000000, - LOW_L1, 310000000, - NOMINAL, 404000000, - NOMINAL_L1, 465000000), - }, -}; - -static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = { - F(100000000, P_GPLL0_OUT_MAIN_DIV, 3, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(269333333, P_MMPLL0_PLL_OUT_MAIN, 3, 0, 0), - { } -}; - -static struct clk_rcg2 csi0phytimer_clk_src = { - .cmd_rcgr = 0x3000, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_2, - .freq_tbl = ftbl_csi0phytimer_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "csi0phytimer_clk_src", - .parent_names = mmcc_parent_names_2, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 100000000, - LOW, 200000000, - LOW_L1, 269333333), - }, -}; - -static struct clk_rcg2 csi1_clk_src = { - .cmd_rcgr = 0x3100, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_0, - .freq_tbl = ftbl_csi0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "csi1_clk_src", - .parent_names = mmcc_parent_names_0, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP5( - LOWER, 100000000, - LOW, 200000000, - LOW_L1, 310000000, - NOMINAL, 404000000, - NOMINAL_L1, 465000000), - }, -}; - -static struct clk_rcg2 csi1phytimer_clk_src = { - .cmd_rcgr = 0x3030, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_2, - .freq_tbl = ftbl_csi0phytimer_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "csi1phytimer_clk_src", - .parent_names = mmcc_parent_names_2, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 100000000, - LOW, 200000000, - LOW_L1, 269333333), - }, -}; - -static struct clk_rcg2 csi2_clk_src = { - .cmd_rcgr = 0x3160, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_0, - .freq_tbl = ftbl_csi0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "csi2_clk_src", - .parent_names = mmcc_parent_names_0, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP5( - LOWER, 100000000, - LOW, 200000000, - LOW_L1, 310000000, - NOMINAL, 404000000, - NOMINAL_L1, 465000000), - }, -}; - -static struct clk_rcg2 csi2phytimer_clk_src = { - .cmd_rcgr = 0x3060, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_2, - .freq_tbl = ftbl_csi0phytimer_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "csi2phytimer_clk_src", - .parent_names = mmcc_parent_names_2, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 100000000, - LOW, 200000000, - LOW_L1, 269333333), - }, -}; - -static struct clk_rcg2 csi3_clk_src = { - .cmd_rcgr = 0x31c0, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_0, - .freq_tbl = ftbl_csi0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "csi3_clk_src", - .parent_names = mmcc_parent_names_0, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP5( - LOWER, 100000000, - LOW, 200000000, - LOW_L1, 310000000, - NOMINAL, 404000000, - NOMINAL_L1, 465000000), - }, -}; - -static const struct freq_tbl ftbl_csiphy_clk_src[] = { - F(100000000, P_GPLL0_OUT_MAIN_DIV, 3, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(269333333, P_MMPLL0_PLL_OUT_MAIN, 3, 0, 0), - F(320000000, P_MMPLL7_PLL_OUT_MAIN, 3, 0, 0), - { } -}; - -static struct clk_rcg2 csiphy_clk_src = { - .cmd_rcgr = 0x3800, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_0, - .freq_tbl = ftbl_csiphy_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "csiphy_clk_src", - .parent_names = mmcc_parent_names_0, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP4( - LOWER, 100000000, - LOW, 200000000, - LOW_L1, 269333333, - NOMINAL, 320000000), - }, -}; - -static const struct freq_tbl ftbl_dp_aux_clk_src[] = { - F(19200000, P_CXO, 1, 0, 0), - { } -}; - -static struct clk_rcg2 dp_aux_clk_src = { - .cmd_rcgr = 0x2260, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_5, - .freq_tbl = ftbl_dp_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "dp_aux_clk_src", - .parent_names = mmcc_parent_names_5, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP1( - LOWER, 19200000), - }, -}; - -static const struct freq_tbl ftbl_dp_crypto_clk_src[] = { - F(101250000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0), - F(168750000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0), - F(337500000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0), - { } -}; - -static struct clk_rcg2 dp_crypto_clk_src = { - .cmd_rcgr = 0x2220, - .mnd_width = 8, - .hid_width = 5, - .parent_map = mmcc_parent_map_6, - .freq_tbl = ftbl_dp_crypto_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "dp_crypto_clk_src", - .parent_names = mmcc_parent_names_6, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 101250000, - LOW, 168750000, - NOMINAL, 337500000), - }, -}; - -static const struct freq_tbl ftbl_dp_gtc_clk_src[] = { - F(40000000, P_GPLL0_OUT_MAIN_DIV, 7.5, 0, 0), - F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), - { } -}; - -static struct clk_rcg2 dp_gtc_clk_src = { - .cmd_rcgr = 0x2280, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_5, - .freq_tbl = ftbl_dp_gtc_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "dp_gtc_clk_src", - .parent_names = mmcc_parent_names_5, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 40000000, - LOW, 60000000), - }, -}; - -static const struct freq_tbl ftbl_dp_link_clk_src[] = { - F(162000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0), - F(270000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0), - F(540000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0), - { } -}; - -static struct clk_rcg2 dp_link_clk_src = { - .cmd_rcgr = 0x2200, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_6, - .freq_tbl = ftbl_dp_link_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "dp_link_clk_src", - .parent_names = mmcc_parent_names_6, - .num_parents = 4, - .ops = &clk_rcg2_ops, - .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, - VDD_DIG_FMAX_MAP3( - LOWER, 162000000, - LOW, 270000000, - NOMINAL, 540000000), - }, -}; - -static struct clk_rcg2 dp_pixel_clk_src = { - .cmd_rcgr = 0x2240, - .mnd_width = 16, - .hid_width = 5, - .parent_map = mmcc_parent_map_6, - .clkr.hw.init = &(struct clk_init_data){ - .name = "dp_pixel_clk_src", - .parent_names = mmcc_parent_names_6, - .num_parents = 4, - .ops = &clk_dp_ops, - VDD_DIG_FMAX_MAP3( - LOWER, 148380000, - LOW, 296740000, - NOMINAL, 593470000), - }, -}; - -static struct clk_rcg2 esc0_clk_src = { - .cmd_rcgr = 0x2160, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_1, - .freq_tbl = ftbl_dp_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "esc0_clk_src", - .parent_names = mmcc_parent_names_1, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP1( - LOWER, 19200000), - }, -}; - -static struct clk_rcg2 esc1_clk_src = { - .cmd_rcgr = 0x2180, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_1, - .freq_tbl = ftbl_dp_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "esc1_clk_src", - .parent_names = mmcc_parent_names_1, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP1( - LOWER, 19200000), - }, -}; - -static const struct freq_tbl ftbl_jpeg0_clk_src[] = { - F(66666667, P_GPLL0_OUT_MAIN_DIV, 4.5, 0, 0), - F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), - F(219428571, P_MMPLL4_PLL_OUT_MAIN, 3.5, 0, 0), - F(320000000, P_MMPLL7_PLL_OUT_MAIN, 3, 0, 0), - F(480000000, P_MMPLL7_PLL_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 jpeg0_clk_src = { - .cmd_rcgr = 0x3500, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_2, - .freq_tbl = ftbl_jpeg0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "jpeg0_clk_src", - .parent_names = mmcc_parent_names_2, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP5( - LOWER, 66666667, - LOW, 133333333, - LOW_L1, 219428571, - NOMINAL, 320000000, - NOMINAL_L1, 480000000), - }, -}; - -static const struct freq_tbl ftbl_mclk0_clk_src[] = { - F(4800000, P_CXO, 4, 0, 0), - F(6000000, P_GPLL0_OUT_MAIN_DIV, 10, 1, 5), - F(8000000, P_GPLL0_OUT_MAIN_DIV, 1, 2, 75), - F(9600000, P_CXO, 2, 0, 0), - F(16666667, P_GPLL0_OUT_MAIN_DIV, 2, 1, 9), - F(19200000, P_CXO, 1, 0, 0), - F(24000000, P_GPLL0_OUT_MAIN_DIV, 1, 2, 25), - F(33333333, P_GPLL0_OUT_MAIN_DIV, 1, 1, 9), - F(48000000, P_GPLL0_OUT_MAIN, 1, 2, 25), - F(66666667, P_GPLL0_OUT_MAIN, 1, 1, 9), - { } -}; - -static struct clk_rcg2 mclk0_clk_src = { - .cmd_rcgr = 0x3360, - .mnd_width = 8, - .hid_width = 5, - .parent_map = mmcc_parent_map_3, - .freq_tbl = ftbl_mclk0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "mclk0_clk_src", - .parent_names = mmcc_parent_names_3, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 33333333, - LOW, 66666667), - }, -}; - -static struct clk_rcg2 mclk1_clk_src = { - .cmd_rcgr = 0x3390, - .mnd_width = 8, - .hid_width = 5, - .parent_map = mmcc_parent_map_3, - .freq_tbl = ftbl_mclk0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "mclk1_clk_src", - .parent_names = mmcc_parent_names_3, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 33333333, - LOW, 66666667), - }, -}; - -static struct clk_rcg2 mclk2_clk_src = { - .cmd_rcgr = 0x33c0, - .mnd_width = 8, - .hid_width = 5, - .parent_map = mmcc_parent_map_3, - .freq_tbl = ftbl_mclk0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "mclk2_clk_src", - .parent_names = mmcc_parent_names_3, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 33333333, - LOW, 66666667), - }, -}; - -static struct clk_rcg2 mclk3_clk_src = { - .cmd_rcgr = 0x33f0, - .mnd_width = 8, - .hid_width = 5, - .parent_map = mmcc_parent_map_3, - .freq_tbl = ftbl_mclk0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "mclk3_clk_src", - .parent_names = mmcc_parent_names_3, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - LOWER, 33333333, - LOW, 66666667), - }, -}; - -static const struct freq_tbl ftbl_mdp_clk_src[] = { - F(100000000, P_GPLL0_OUT_MAIN_DIV, 3, 0, 0), - F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0), - F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(275000000, P_MMPLL5_PLL_OUT_MAIN, 3, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - F(330000000, P_MMPLL5_PLL_OUT_MAIN, 2.5, 0, 0), - F(412500000, P_MMPLL5_PLL_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 mdp_clk_src = { - .cmd_rcgr = 0x2040, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_7, - .freq_tbl = ftbl_mdp_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "mdp_clk_src", - .parent_names = mmcc_parent_names_7, - .num_parents = 7, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP5( - LOWER, 171428571, - LOW, 275000000, - LOW_L1, 300000000, - NOMINAL, 330000000, - HIGH, 412500000), - }, -}; - -static struct clk_rcg2 pclk0_clk_src = { - .cmd_rcgr = 0x2000, - .mnd_width = 8, - .hid_width = 5, - .parent_map = mmcc_parent_map_8, - .clkr.hw.init = &(struct clk_init_data){ - .name = "pclk0_clk_src", - .parent_names = mmcc_parent_names_8, - .num_parents = 4, - .ops = &clk_pixel_ops, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - VDD_DIG_FMAX_MAP3( - LOWER, 175000000, - LOW, 280000000, - NOMINAL, 350000000), - }, -}; - -static struct clk_rcg2 pclk1_clk_src = { - .cmd_rcgr = 0x2020, - .mnd_width = 8, - .hid_width = 5, - .parent_map = mmcc_parent_map_8, - .clkr.hw.init = &(struct clk_init_data){ - .name = "pclk1_clk_src", - .parent_names = mmcc_parent_names_8, - .num_parents = 4, - .ops = &clk_pixel_ops, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - VDD_DIG_FMAX_MAP3( - LOWER, 175000000, - LOW, 280000000, - NOMINAL, 350000000), - }, -}; - -static const struct freq_tbl ftbl_rot_clk_src[] = { - F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0), - F(275000000, P_MMPLL5_PLL_OUT_MAIN, 3, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - F(330000000, P_MMPLL5_PLL_OUT_MAIN, 2.5, 0, 0), - F(412500000, P_MMPLL5_PLL_OUT_MAIN, 2, 0, 0), - { } -}; - -static struct clk_rcg2 rot_clk_src = { - .cmd_rcgr = 0x21a0, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_7, - .freq_tbl = ftbl_rot_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "rot_clk_src", - .parent_names = mmcc_parent_names_7, - .num_parents = 7, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP5( - LOWER, 171428571, - LOW, 275000000, - LOW_L1, 300000000, - NOMINAL, 330000000, - HIGH, 412500000), - }, -}; - -static const struct freq_tbl ftbl_vfe0_clk_src[] = { - F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), - F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), - F(256000000, P_MMPLL4_PLL_OUT_MAIN, 3, 0, 0), - F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), - F(404000000, P_MMPLL0_PLL_OUT_MAIN, 2, 0, 0), - F(480000000, P_MMPLL7_PLL_OUT_MAIN, 2, 0, 0), - F(540000000, P_MMPLL6_PLL_OUT_MAIN, 2, 0, 0), - F(576000000, P_MMPLL10_PLL_OUT_MAIN, 1, 0, 0), - { } -}; - -static struct clk_rcg2 vfe0_clk_src = { - .cmd_rcgr = 0x3600, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_9, - .freq_tbl = ftbl_vfe0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "vfe0_clk_src", - .parent_names = mmcc_parent_names_9, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP6( - LOWER, 120000000, - LOW, 256000000, - LOW_L1, 404000000, - NOMINAL, 480000000, - NOMINAL_L1, 540000000, - HIGH, 576000000), - }, -}; - -static struct clk_rcg2 vfe1_clk_src = { - .cmd_rcgr = 0x3620, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_9, - .freq_tbl = ftbl_vfe0_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "vfe1_clk_src", - .parent_names = mmcc_parent_names_9, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP6( - LOWER, 120000000, - LOW, 256000000, - LOW_L1, 404000000, - NOMINAL, 480000000, - NOMINAL_L1, 540000000, - HIGH, 576000000), - }, -}; - -static const struct freq_tbl ftbl_video_core_clk_src[] = { - F_SLEW(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0, FIXED_FREQ_SRC), - F_SLEW(269333333, P_MMPLL0_PLL_OUT_MAIN, 3, 0, 0, FIXED_FREQ_SRC), - F_SLEW(320000000, P_MMPLL7_PLL_OUT_MAIN, 3, 0, 0, FIXED_FREQ_SRC), - F_SLEW(404000000, P_MMPLL0_PLL_OUT_MAIN, 2, 0, 0, FIXED_FREQ_SRC), - F_SLEW(441600000, P_MMPLL3_PLL_OUT_MAIN, 2, 0, 0, 883200000), - F_SLEW(518400000, P_MMPLL3_PLL_OUT_MAIN, 2, 0, 0, 1036800000), - { } -}; - -static struct clk_rcg2 video_core_clk_src = { - .cmd_rcgr = 0x1000, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_12, - .freq_tbl = ftbl_video_core_clk_src, - .flags = FORCE_ENABLE_RCGR, - .clkr.hw.init = &(struct clk_init_data){ - .name = "video_core_clk_src", - .parent_names = mmcc_parent_names_12, - .num_parents = 8, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP6( - LOWER, 133333333, - LOW, 269333333, - LOW_L1, 320000000, - NOMINAL, 404000000, - NOMINAL_L1, 441600000, - HIGH, 518400000), - }, -}; - -static struct clk_rcg2 vsync_clk_src = { - .cmd_rcgr = 0x2080, - .mnd_width = 0, - .hid_width = 5, - .parent_map = mmcc_parent_map_5, - .freq_tbl = ftbl_dp_aux_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "vsync_clk_src", - .parent_names = mmcc_parent_names_5, - .num_parents = 4, - .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP1( - LOWER, 19200000), - }, -}; - -static struct clk_branch mmss_bimc_smmu_ahb_clk = { - .halt_reg = 0xe004, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0xe004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_bimc_smmu_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .flags = CLK_ENABLE_HAND_OFF, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_bimc_smmu_axi_clk = { - .halt_reg = 0xe008, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0xe008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_bimc_smmu_axi_clk", - .flags = CLK_ENABLE_HAND_OFF, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_ahb_clk = { - .halt_reg = 0x348c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x348c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_cci_ahb_clk = { - .halt_reg = 0x3348, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3348, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_cci_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_cci_clk = { - .halt_reg = 0x3344, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3344, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_cci_clk", - .parent_names = (const char *[]){ - "cci_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_cphy_csid0_clk = { - .halt_reg = 0x3730, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3730, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_cphy_csid0_clk", - .parent_names = (const char *[]){ - "csiphy_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_cphy_csid1_clk = { - .halt_reg = 0x3734, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3734, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_cphy_csid1_clk", - .parent_names = (const char *[]){ - "csiphy_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_cphy_csid2_clk = { - .halt_reg = 0x3738, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3738, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_cphy_csid2_clk", - .parent_names = (const char *[]){ - "csiphy_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_cphy_csid3_clk = { - .halt_reg = 0x373c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x373c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_cphy_csid3_clk", - .parent_names = (const char *[]){ - "csiphy_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_cpp_ahb_clk = { - .halt_reg = 0x36b4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36b4, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_cpp_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_cpp_axi_clk = { - .halt_reg = 0x36c4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36c4, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_cpp_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_cpp_clk = { - .halt_reg = 0x36b0, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36b0, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_cpp_clk", - .parent_names = (const char *[]){ - "cpp_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_cpp_vbif_ahb_clk = { - .halt_reg = 0x36c8, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36c8, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_cpp_vbif_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi0_ahb_clk = { - .halt_reg = 0x30bc, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x30bc, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi0_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi0_clk = { - .halt_reg = 0x30b4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x30b4, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi0_clk", - .parent_names = (const char *[]){ - "csi0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi0phytimer_clk = { - .halt_reg = 0x3024, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3024, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi0phytimer_clk", - .parent_names = (const char *[]){ - "csi0phytimer_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi0pix_clk = { - .halt_reg = 0x30e4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x30e4, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi0pix_clk", - .parent_names = (const char *[]){ - "csi0_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi0rdi_clk = { - .halt_reg = 0x30d4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x30d4, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi0rdi_clk", - .parent_names = (const char *[]){ - "csi0_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi1_ahb_clk = { - .halt_reg = 0x3128, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3128, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi1_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi1_clk = { - .halt_reg = 0x3124, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3124, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi1_clk", - .parent_names = (const char *[]){ - "csi1_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi1phytimer_clk = { - .halt_reg = 0x3054, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3054, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi1phytimer_clk", - .parent_names = (const char *[]){ - "csi1phytimer_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi1pix_clk = { - .halt_reg = 0x3154, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3154, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi1pix_clk", - .parent_names = (const char *[]){ - "csi1_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi1rdi_clk = { - .halt_reg = 0x3144, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3144, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi1rdi_clk", - .parent_names = (const char *[]){ - "csi1_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi2_ahb_clk = { - .halt_reg = 0x3188, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3188, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi2_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi2_clk = { - .halt_reg = 0x3184, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3184, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi2_clk", - .parent_names = (const char *[]){ - "csi2_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi2phytimer_clk = { - .halt_reg = 0x3084, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3084, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi2phytimer_clk", - .parent_names = (const char *[]){ - "csi2phytimer_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi2pix_clk = { - .halt_reg = 0x31b4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x31b4, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi2pix_clk", - .parent_names = (const char *[]){ - "csi2_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi2rdi_clk = { - .halt_reg = 0x31a4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x31a4, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi2rdi_clk", - .parent_names = (const char *[]){ - "csi2_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi3_ahb_clk = { - .halt_reg = 0x31e8, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x31e8, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi3_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi3_clk = { - .halt_reg = 0x31e4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x31e4, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi3_clk", - .parent_names = (const char *[]){ - "csi3_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi3pix_clk = { - .halt_reg = 0x3214, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3214, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi3pix_clk", - .parent_names = (const char *[]){ - "csi3_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi3rdi_clk = { - .halt_reg = 0x3204, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3204, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi3rdi_clk", - .parent_names = (const char *[]){ - "csi3_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi_vfe0_clk = { - .halt_reg = 0x3704, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3704, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi_vfe0_clk", - .parent_names = (const char *[]){ - "vfe0_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csi_vfe1_clk = { - .halt_reg = 0x3714, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3714, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csi_vfe1_clk", - .parent_names = (const char *[]){ - "vfe1_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csiphy0_clk = { - .halt_reg = 0x3740, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3740, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csiphy0_clk", - .parent_names = (const char *[]){ - "csiphy_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csiphy1_clk = { - .halt_reg = 0x3744, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3744, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csiphy1_clk", - .parent_names = (const char *[]){ - "csiphy_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_csiphy2_clk = { - .halt_reg = 0x3748, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3748, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_csiphy2_clk", - .parent_names = (const char *[]){ - "csiphy_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_gp0_clk = { - .halt_reg = 0x3444, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3444, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_gp0_clk", - .parent_names = (const char *[]){ - "camss_gp0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_gp1_clk = { - .halt_reg = 0x3474, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3474, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_gp1_clk", - .parent_names = (const char *[]){ - "camss_gp1_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_ispif_ahb_clk = { - .halt_reg = 0x3224, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3224, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_ispif_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_jpeg0_clk = { - .halt_reg = 0x35a8, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x35a8, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_jpeg0_clk", - .parent_names = (const char *[]){ - "jpeg0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static DEFINE_CLK_VOTER(mmss_camss_jpeg0_vote_clk, mmss_camss_jpeg0_clk, 0); -static DEFINE_CLK_VOTER(mmss_camss_jpeg0_dma_vote_clk, - mmss_camss_jpeg0_clk, 0); - -static struct clk_branch mmss_camss_jpeg_ahb_clk = { - .halt_reg = 0x35b4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x35b4, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_jpeg_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_jpeg_axi_clk = { - .halt_reg = 0x35b8, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x35b8, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_jpeg_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_mclk0_clk = { - .halt_reg = 0x3384, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3384, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_mclk0_clk", - .parent_names = (const char *[]){ - "mclk0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_mclk1_clk = { - .halt_reg = 0x33b4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x33b4, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_mclk1_clk", - .parent_names = (const char *[]){ - "mclk1_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_mclk2_clk = { - .halt_reg = 0x33e4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x33e4, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_mclk2_clk", - .parent_names = (const char *[]){ - "mclk2_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_mclk3_clk = { - .halt_reg = 0x3414, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3414, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_mclk3_clk", - .parent_names = (const char *[]){ - "mclk3_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_micro_ahb_clk = { - .halt_reg = 0x3494, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3494, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_micro_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_top_ahb_clk = { - .halt_reg = 0x3484, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3484, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_top_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_vfe0_ahb_clk = { - .halt_reg = 0x3668, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3668, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_vfe0_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_vfe0_clk = { - .halt_reg = 0x36a8, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36a8, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_vfe0_clk", - .parent_names = (const char *[]){ - "vfe0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_vfe0_stream_clk = { - .halt_reg = 0x3720, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3720, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_vfe0_stream_clk", - .parent_names = (const char *[]){ - "vfe0_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_vfe1_ahb_clk = { - .halt_reg = 0x3678, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3678, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_vfe1_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_vfe1_clk = { - .halt_reg = 0x36ac, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36ac, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_vfe1_clk", - .parent_names = (const char *[]){ - "vfe1_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_vfe1_stream_clk = { - .halt_reg = 0x3724, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x3724, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_vfe1_stream_clk", - .parent_names = (const char *[]){ - "vfe1_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_vfe_vbif_ahb_clk = { - .halt_reg = 0x36b8, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36b8, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_vfe_vbif_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_camss_vfe_vbif_axi_clk = { - .halt_reg = 0x36bc, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x36bc, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_camss_vfe_vbif_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_csiphy_ahb2crif_clk = { - .halt_reg = 0x374c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x374c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_csiphy_ahb2crif_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_ahb_clk = { - .halt_reg = 0x2308, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2308, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .flags = CLK_ENABLE_HAND_OFF, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_axi_clk = { - .halt_reg = 0x2310, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2310, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_byte0_clk = { - .halt_reg = 0x233c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x233c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_byte0_clk", - .parent_names = (const char *[]){ - "byte0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_byte0_intf_clk = { - .halt_reg = 0x2374, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2374, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_byte0_intf_clk", - .parent_names = (const char *[]){ - "mmss_mdss_byte0_intf_div_clk", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_regmap_div mmss_mdss_byte0_intf_div_clk = { - .reg = 0x237c, - .shift = 0, - .width = 2, - /* - * NOTE: Op does not work for div-3. Current assumption is that div-3 - * is not a recommended setting for this divider. - */ - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_byte0_intf_div_clk", - .parent_names = (const char *[]){ - "byte0_clk_src", - }, - .num_parents = 1, - .ops = &clk_regmap_div_ops, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - }, - }, -}; - -static struct clk_branch mmss_mdss_byte1_clk = { - .halt_reg = 0x2340, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2340, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_byte1_clk", - .parent_names = (const char *[]){ - "byte1_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_byte1_intf_clk = { - .halt_reg = 0x2378, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2378, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_byte1_intf_clk", - .parent_names = (const char *[]){ - "byte1_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_dp_aux_clk = { - .halt_reg = 0x2364, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2364, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_dp_aux_clk", - .parent_names = (const char *[]){ - "dp_aux_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_dp_crypto_clk = { - .halt_reg = 0x235c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x235c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_dp_crypto_clk", - .parent_names = (const char *[]){ - "dp_crypto_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_dp_gtc_clk = { - .halt_reg = 0x2368, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2368, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_dp_gtc_clk", - .parent_names = (const char *[]){ - "dp_gtc_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_dp_link_clk = { - .halt_reg = 0x2354, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2354, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_dp_link_clk", - .parent_names = (const char *[]){ - "dp_link_clk_src", - }, - .num_parents = 1, - .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -/* Reset state of MMSS_MDSS_DP_LINK_INTF_DIV is 0x3 (div-4) */ -static struct clk_branch mmss_mdss_dp_link_intf_clk = { - .halt_reg = 0x2358, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2358, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_dp_link_intf_clk", - .parent_names = (const char *[]){ - "dp_link_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_dp_pixel_clk = { - .halt_reg = 0x2360, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2360, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_dp_pixel_clk", - .parent_names = (const char *[]){ - "dp_pixel_clk_src", - }, - .num_parents = 1, - .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_esc0_clk = { - .halt_reg = 0x2344, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2344, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_esc0_clk", - .parent_names = (const char *[]){ - "esc0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_esc1_clk = { - .halt_reg = 0x2348, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2348, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_esc1_clk", - .parent_names = (const char *[]){ - "esc1_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_hdmi_dp_ahb_clk = { - .halt_reg = 0x230c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x230c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_hdmi_dp_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_mdp_clk = { - .halt_reg = 0x231c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x231c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_mdp_clk", - .parent_names = (const char *[]){ - "mdp_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_ENABLE_HAND_OFF, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_pclk0_clk = { - .halt_reg = 0x2314, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2314, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_pclk0_clk", - .parent_names = (const char *[]){ - "pclk0_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_pclk1_clk = { - .halt_reg = 0x2318, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2318, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_pclk1_clk", - .parent_names = (const char *[]){ - "pclk1_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_rot_clk = { - .halt_reg = 0x2350, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2350, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_rot_clk", - .parent_names = (const char *[]){ - "rot_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mdss_vsync_clk = { - .halt_reg = 0x2328, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2328, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mdss_vsync_clk", - .parent_names = (const char *[]){ - "vsync_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_misc_ahb_clk = { - .halt_reg = 0x328, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x328, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_misc_ahb_clk", - /* - * Dependency to be enabled before the branch is - * enabled. - */ - .parent_names = (const char *[]){ - "mmss_mnoc_ahb_clk", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_misc_cxo_clk = { - .halt_reg = 0x324, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x324, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_misc_cxo_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_mnoc_ahb_clk = { - .halt_reg = 0x5024, - .halt_check = BRANCH_VOTED, - .clkr = { - .enable_reg = 0x5024, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mnoc_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_snoc_dvm_axi_clk = { - .halt_reg = 0xe040, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0xe040, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_snoc_dvm_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_video_ahb_clk = { - .halt_reg = 0x1030, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1030, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_video_ahb_clk", - .parent_names = (const char *[]){ - "ahb_clk_src", - }, - .num_parents = 1, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_video_axi_clk = { - .halt_reg = 0x1034, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1034, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_video_axi_clk", - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_video_core_clk = { - .halt_reg = 0x1028, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1028, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_video_core_clk", - .parent_names = (const char *[]){ - "video_core_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmss_video_subcore0_clk = { - .halt_reg = 0x1048, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1048, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_video_subcore0_clk", - .parent_names = (const char *[]){ - "video_core_clk_src", - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - .ops = &clk_branch2_ops, - }, - }, -}; - -struct clk_hw *mmcc_msmfalcon_hws[] = { - [MMSS_CAMSS_JPEG0_VOTE_CLK] = &mmss_camss_jpeg0_vote_clk.hw, - [MMSS_CAMSS_JPEG0_DMA_VOTE_CLK] = &mmss_camss_jpeg0_dma_vote_clk.hw, -}; - -static struct clk_regmap *mmcc_falcon_clocks[] = { - [AHB_CLK_SRC] = &ahb_clk_src.clkr, - [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, - [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, - [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, - [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, - [CCI_CLK_SRC] = &cci_clk_src.clkr, - [CPP_CLK_SRC] = &cpp_clk_src.clkr, - [CSI0_CLK_SRC] = &csi0_clk_src.clkr, - [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, - [CSI1_CLK_SRC] = &csi1_clk_src.clkr, - [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, - [CSI2_CLK_SRC] = &csi2_clk_src.clkr, - [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr, - [CSI3_CLK_SRC] = &csi3_clk_src.clkr, - [CSIPHY_CLK_SRC] = &csiphy_clk_src.clkr, - [DP_AUX_CLK_SRC] = &dp_aux_clk_src.clkr, - [DP_CRYPTO_CLK_SRC] = &dp_crypto_clk_src.clkr, - [DP_GTC_CLK_SRC] = &dp_gtc_clk_src.clkr, - [DP_LINK_CLK_SRC] = &dp_link_clk_src.clkr, - [DP_PIXEL_CLK_SRC] = &dp_pixel_clk_src.clkr, - [ESC0_CLK_SRC] = &esc0_clk_src.clkr, - [ESC1_CLK_SRC] = &esc1_clk_src.clkr, - [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, - [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, - [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, - [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr, - [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr, - [MDP_CLK_SRC] = &mdp_clk_src.clkr, - [MMPLL0_PLL] = &mmpll0_pll_out_main.clkr, - [MMPLL10_PLL] = &mmpll10_pll_out_main.clkr, - [MMPLL3_PLL] = &mmpll3_pll_out_main.clkr, - [MMPLL4_PLL] = &mmpll4_pll_out_main.clkr, - [MMPLL5_PLL] = &mmpll5_pll_out_main.clkr, - [MMPLL6_PLL] = &mmpll6_pll_out_main.clkr, - [MMPLL7_PLL] = &mmpll7_pll_out_main.clkr, - [MMPLL8_PLL] = &mmpll8_pll_out_main.clkr, - [MMSS_BIMC_SMMU_AHB_CLK] = &mmss_bimc_smmu_ahb_clk.clkr, - [MMSS_BIMC_SMMU_AXI_CLK] = &mmss_bimc_smmu_axi_clk.clkr, - [MMSS_CAMSS_AHB_CLK] = &mmss_camss_ahb_clk.clkr, - [MMSS_CAMSS_CCI_AHB_CLK] = &mmss_camss_cci_ahb_clk.clkr, - [MMSS_CAMSS_CCI_CLK] = &mmss_camss_cci_clk.clkr, - [MMSS_CAMSS_CPHY_CSID0_CLK] = &mmss_camss_cphy_csid0_clk.clkr, - [MMSS_CAMSS_CPHY_CSID1_CLK] = &mmss_camss_cphy_csid1_clk.clkr, - [MMSS_CAMSS_CPHY_CSID2_CLK] = &mmss_camss_cphy_csid2_clk.clkr, - [MMSS_CAMSS_CPHY_CSID3_CLK] = &mmss_camss_cphy_csid3_clk.clkr, - [MMSS_CAMSS_CPP_AHB_CLK] = &mmss_camss_cpp_ahb_clk.clkr, - [MMSS_CAMSS_CPP_AXI_CLK] = &mmss_camss_cpp_axi_clk.clkr, - [MMSS_CAMSS_CPP_CLK] = &mmss_camss_cpp_clk.clkr, - [MMSS_CAMSS_CPP_VBIF_AHB_CLK] = &mmss_camss_cpp_vbif_ahb_clk.clkr, - [MMSS_CAMSS_CSI0_AHB_CLK] = &mmss_camss_csi0_ahb_clk.clkr, - [MMSS_CAMSS_CSI0_CLK] = &mmss_camss_csi0_clk.clkr, - [MMSS_CAMSS_CSI0PHYTIMER_CLK] = &mmss_camss_csi0phytimer_clk.clkr, - [MMSS_CAMSS_CSI0PIX_CLK] = &mmss_camss_csi0pix_clk.clkr, - [MMSS_CAMSS_CSI0RDI_CLK] = &mmss_camss_csi0rdi_clk.clkr, - [MMSS_CAMSS_CSI1_AHB_CLK] = &mmss_camss_csi1_ahb_clk.clkr, - [MMSS_CAMSS_CSI1_CLK] = &mmss_camss_csi1_clk.clkr, - [MMSS_CAMSS_CSI1PHYTIMER_CLK] = &mmss_camss_csi1phytimer_clk.clkr, - [MMSS_CAMSS_CSI1PIX_CLK] = &mmss_camss_csi1pix_clk.clkr, - [MMSS_CAMSS_CSI1RDI_CLK] = &mmss_camss_csi1rdi_clk.clkr, - [MMSS_CAMSS_CSI2_AHB_CLK] = &mmss_camss_csi2_ahb_clk.clkr, - [MMSS_CAMSS_CSI2_CLK] = &mmss_camss_csi2_clk.clkr, - [MMSS_CAMSS_CSI2PHYTIMER_CLK] = &mmss_camss_csi2phytimer_clk.clkr, - [MMSS_CAMSS_CSI2PIX_CLK] = &mmss_camss_csi2pix_clk.clkr, - [MMSS_CAMSS_CSI2RDI_CLK] = &mmss_camss_csi2rdi_clk.clkr, - [MMSS_CAMSS_CSI3_AHB_CLK] = &mmss_camss_csi3_ahb_clk.clkr, - [MMSS_CAMSS_CSI3_CLK] = &mmss_camss_csi3_clk.clkr, - [MMSS_CAMSS_CSI3PIX_CLK] = &mmss_camss_csi3pix_clk.clkr, - [MMSS_CAMSS_CSI3RDI_CLK] = &mmss_camss_csi3rdi_clk.clkr, - [MMSS_CAMSS_CSI_VFE0_CLK] = &mmss_camss_csi_vfe0_clk.clkr, - [MMSS_CAMSS_CSI_VFE1_CLK] = &mmss_camss_csi_vfe1_clk.clkr, - [MMSS_CAMSS_CSIPHY0_CLK] = &mmss_camss_csiphy0_clk.clkr, - [MMSS_CAMSS_CSIPHY1_CLK] = &mmss_camss_csiphy1_clk.clkr, - [MMSS_CAMSS_CSIPHY2_CLK] = &mmss_camss_csiphy2_clk.clkr, - [MMSS_CAMSS_GP0_CLK] = &mmss_camss_gp0_clk.clkr, - [MMSS_CAMSS_GP1_CLK] = &mmss_camss_gp1_clk.clkr, - [MMSS_CAMSS_ISPIF_AHB_CLK] = &mmss_camss_ispif_ahb_clk.clkr, - [MMSS_CAMSS_JPEG0_CLK] = &mmss_camss_jpeg0_clk.clkr, - [MMSS_CAMSS_JPEG_AHB_CLK] = &mmss_camss_jpeg_ahb_clk.clkr, - [MMSS_CAMSS_JPEG_AXI_CLK] = &mmss_camss_jpeg_axi_clk.clkr, - [MMSS_CAMSS_MCLK0_CLK] = &mmss_camss_mclk0_clk.clkr, - [MMSS_CAMSS_MCLK1_CLK] = &mmss_camss_mclk1_clk.clkr, - [MMSS_CAMSS_MCLK2_CLK] = &mmss_camss_mclk2_clk.clkr, - [MMSS_CAMSS_MCLK3_CLK] = &mmss_camss_mclk3_clk.clkr, - [MMSS_CAMSS_MICRO_AHB_CLK] = &mmss_camss_micro_ahb_clk.clkr, - [MMSS_CAMSS_TOP_AHB_CLK] = &mmss_camss_top_ahb_clk.clkr, - [MMSS_CAMSS_VFE0_AHB_CLK] = &mmss_camss_vfe0_ahb_clk.clkr, - [MMSS_CAMSS_VFE0_CLK] = &mmss_camss_vfe0_clk.clkr, - [MMSS_CAMSS_VFE0_STREAM_CLK] = &mmss_camss_vfe0_stream_clk.clkr, - [MMSS_CAMSS_VFE1_AHB_CLK] = &mmss_camss_vfe1_ahb_clk.clkr, - [MMSS_CAMSS_VFE1_CLK] = &mmss_camss_vfe1_clk.clkr, - [MMSS_CAMSS_VFE1_STREAM_CLK] = &mmss_camss_vfe1_stream_clk.clkr, - [MMSS_CAMSS_VFE_VBIF_AHB_CLK] = &mmss_camss_vfe_vbif_ahb_clk.clkr, - [MMSS_CAMSS_VFE_VBIF_AXI_CLK] = &mmss_camss_vfe_vbif_axi_clk.clkr, - [MMSS_CSIPHY_AHB2CRIF_CLK] = &mmss_csiphy_ahb2crif_clk.clkr, - [MMSS_MDSS_AHB_CLK] = &mmss_mdss_ahb_clk.clkr, - [MMSS_MDSS_AXI_CLK] = &mmss_mdss_axi_clk.clkr, - [MMSS_MDSS_BYTE0_CLK] = &mmss_mdss_byte0_clk.clkr, - [MMSS_MDSS_BYTE0_INTF_CLK] = &mmss_mdss_byte0_intf_clk.clkr, - [MMSS_MDSS_BYTE0_INTF_DIV_CLK] = &mmss_mdss_byte0_intf_div_clk.clkr, - [MMSS_MDSS_BYTE1_CLK] = &mmss_mdss_byte1_clk.clkr, - [MMSS_MDSS_BYTE1_INTF_CLK] = &mmss_mdss_byte1_intf_clk.clkr, - [MMSS_MDSS_DP_AUX_CLK] = &mmss_mdss_dp_aux_clk.clkr, - [MMSS_MDSS_DP_CRYPTO_CLK] = &mmss_mdss_dp_crypto_clk.clkr, - [MMSS_MDSS_DP_GTC_CLK] = &mmss_mdss_dp_gtc_clk.clkr, - [MMSS_MDSS_DP_LINK_CLK] = &mmss_mdss_dp_link_clk.clkr, - [MMSS_MDSS_DP_LINK_INTF_CLK] = &mmss_mdss_dp_link_intf_clk.clkr, - [MMSS_MDSS_DP_PIXEL_CLK] = &mmss_mdss_dp_pixel_clk.clkr, - [MMSS_MDSS_ESC0_CLK] = &mmss_mdss_esc0_clk.clkr, - [MMSS_MDSS_ESC1_CLK] = &mmss_mdss_esc1_clk.clkr, - [MMSS_MDSS_HDMI_DP_AHB_CLK] = &mmss_mdss_hdmi_dp_ahb_clk.clkr, - [MMSS_MDSS_MDP_CLK] = &mmss_mdss_mdp_clk.clkr, - [MMSS_MDSS_PCLK0_CLK] = &mmss_mdss_pclk0_clk.clkr, - [MMSS_MDSS_PCLK1_CLK] = &mmss_mdss_pclk1_clk.clkr, - [MMSS_MDSS_ROT_CLK] = &mmss_mdss_rot_clk.clkr, - [MMSS_MDSS_VSYNC_CLK] = &mmss_mdss_vsync_clk.clkr, - [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, - [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr, - [MMSS_MNOC_AHB_CLK] = &mmss_mnoc_ahb_clk.clkr, - [MMSS_SNOC_DVM_AXI_CLK] = &mmss_snoc_dvm_axi_clk.clkr, - [MMSS_VIDEO_AHB_CLK] = &mmss_video_ahb_clk.clkr, - [MMSS_VIDEO_AXI_CLK] = &mmss_video_axi_clk.clkr, - [MMSS_VIDEO_CORE_CLK] = &mmss_video_core_clk.clkr, - [MMSS_VIDEO_SUBCORE0_CLK] = &mmss_video_subcore0_clk.clkr, - [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, - [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr, - [ROT_CLK_SRC] = &rot_clk_src.clkr, - [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, - [VFE1_CLK_SRC] = &vfe1_clk_src.clkr, - [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr, - [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, -}; - -static const struct qcom_reset_map mmcc_falcon_resets[] = { - [CAMSS_MICRO_BCR] = { 0x3490 }, -}; - -static const struct regmap_config mmcc_falcon_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0x10004, - .fast_io = true, -}; - -static const struct qcom_cc_desc mmcc_falcon_desc = { - .config = &mmcc_falcon_regmap_config, - .clks = mmcc_falcon_clocks, - .num_clks = ARRAY_SIZE(mmcc_falcon_clocks), - .hwclks = mmcc_msmfalcon_hws, - .num_hwclks = ARRAY_SIZE(mmcc_msmfalcon_hws), - .resets = mmcc_falcon_resets, - .num_resets = ARRAY_SIZE(mmcc_falcon_resets), -}; - -static const struct of_device_id mmcc_falcon_match_table[] = { - { .compatible = "qcom,mmcc-msmfalcon" }, - { } -}; -MODULE_DEVICE_TABLE(of, mmcc_falcon_match_table); - -static int mmcc_falcon_probe(struct platform_device *pdev) -{ - int ret = 0; - struct regmap *regmap; - - regmap = qcom_cc_map(pdev, &mmcc_falcon_desc); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); - - /* PLLs connected on Mx rails of MMSS_CC */ - vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx_mmss"); - if (IS_ERR(vdd_mx.regulator[0])) { - if (!(PTR_ERR(vdd_mx.regulator[0]) == -EPROBE_DEFER)) - dev_err(&pdev->dev, - "Unable to get vdd_mx_mmss regulator\n"); - return PTR_ERR(vdd_mx.regulator[0]); - } - - vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig_mmss"); - if (IS_ERR(vdd_dig.regulator[0])) { - if (!(PTR_ERR(vdd_dig.regulator[0]) == -EPROBE_DEFER)) - dev_err(&pdev->dev, - "Unable to get vdd_dig regulator\n"); - return PTR_ERR(vdd_dig.regulator[0]); - } - - /* MMPLL10 connected to the Analog Rail */ - vdda.regulator[0] = devm_regulator_get(&pdev->dev, "vdda"); - if (IS_ERR(vdda.regulator[0])) { - if (!(PTR_ERR(vdda.regulator[0]) == -EPROBE_DEFER)) - dev_err(&pdev->dev, - "Unable to get vdda regulator\n"); - return PTR_ERR(vdda.regulator[0]); - } - - clk_alpha_pll_configure(&mmpll3_pll_out_main, regmap, &mmpll3_config); - clk_alpha_pll_configure(&mmpll4_pll_out_main, regmap, &mmpll4_config); - clk_alpha_pll_configure(&mmpll5_pll_out_main, regmap, &mmpll5_config); - clk_alpha_pll_configure(&mmpll7_pll_out_main, regmap, &mmpll7_config); - clk_alpha_pll_configure(&mmpll8_pll_out_main, regmap, &mmpll8_config); - clk_alpha_pll_configure(&mmpll10_pll_out_main, regmap, &mmpll10_config); - - ret = qcom_cc_really_probe(pdev, &mmcc_falcon_desc, regmap); - if (ret) { - dev_err(&pdev->dev, "Failed to register MMSS clocks\n"); - return ret; - } - - dev_info(&pdev->dev, "Registered MMSS clocks\n"); - - return ret; -} - -static struct platform_driver mmcc_falcon_driver = { - .probe = mmcc_falcon_probe, - .driver = { - .name = "mmcc-msmfalcon", - .of_match_table = mmcc_falcon_match_table, - }, -}; - -static int __init mmcc_falcon_init(void) -{ - return platform_driver_register(&mmcc_falcon_driver); -} -core_initcall_sync(mmcc_falcon_init); - -static void __exit mmcc_falcon_exit(void) -{ - platform_driver_unregister(&mmcc_falcon_driver); -} -module_exit(mmcc_falcon_exit); diff --git a/drivers/clk/qcom/mmcc-sdm660.c b/drivers/clk/qcom/mmcc-sdm660.c new file mode 100644 index 000000000000..daece455454c --- /dev/null +++ b/drivers/clk/qcom/mmcc-sdm660.c @@ -0,0 +1,3056 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "common.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-voter.h" +#include "reset.h" +#include "vdd-level-660.h" + +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } +#define F_SLEW(f, s, h, m, n, src_freq) { (f), (s), (2 * (h) - 1), (m), (n), \ + (src_freq) } + +enum vdd_a_levels { + VDDA_NONE, + VDDA_LOWER, /* SVS2 */ + VDDA_NUM, +}; + +static int vdda_levels[] = { + 0, + 1800000, +}; + +#define VDDA_FMAX_MAP1(l1, f1) \ + .vdd_class = &vdda, \ + .rate_max = (unsigned long[VDDA_NUM]) { \ + [VDDA_##l1] = (f1), \ + }, \ + .num_rate_max = VDDA_NUM + +static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner); +static DEFINE_VDD_REGULATORS(vdd_mx, VDD_DIG_NUM, 1, vdd_corner); +static DEFINE_VDD_REGULATORS(vdda, VDDA_NUM, 1, vdda_levels); + +enum { + P_CORE_BI_PLL_TEST_SE, + P_CORE_PI_SLEEP_CLK, + P_CXO, + P_DP_PHY_PLL_LINK_CLK, + P_DP_PHY_PLL_VCO_DIV, + P_DSI0_PHY_PLL_OUT_BYTECLK, + P_DSI0_PHY_PLL_OUT_DSICLK, + P_DSI1_PHY_PLL_OUT_BYTECLK, + P_DSI1_PHY_PLL_OUT_DSICLK, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_MMPLL0_PLL_OUT_MAIN, + P_MMPLL10_PLL_OUT_MAIN, + P_MMPLL3_PLL_OUT_MAIN, + P_MMPLL4_PLL_OUT_MAIN, + P_MMPLL5_PLL_OUT_MAIN, + P_MMPLL6_PLL_OUT_MAIN, + P_MMPLL7_PLL_OUT_MAIN, + P_MMPLL8_PLL_OUT_MAIN, +}; + +static const struct parent_map mmcc_parent_map_0[] = { + { P_CXO, 0 }, + { P_MMPLL0_PLL_OUT_MAIN, 1 }, + { P_MMPLL4_PLL_OUT_MAIN, 2 }, + { P_MMPLL7_PLL_OUT_MAIN, 3 }, + { P_MMPLL8_PLL_OUT_MAIN, 4 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_0[] = { + "xo", + "mmpll0_pll_out_main", + "mmpll4_pll_out_main", + "mmpll7_pll_out_main", + "mmpll8_pll_out_main", + "gcc_mmss_gpll0_clk", + "gcc_mmss_gpll0_div_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_1[] = { + { P_CXO, 0 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, + { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_1[] = { + "xo", + "dsi0pll_byte_clk_mux", + "dsi1pll_byte_clk_mux", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_2[] = { + { P_CXO, 0 }, + { P_MMPLL0_PLL_OUT_MAIN, 1 }, + { P_MMPLL4_PLL_OUT_MAIN, 2 }, + { P_MMPLL7_PLL_OUT_MAIN, 3 }, + { P_MMPLL10_PLL_OUT_MAIN, 4 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_2[] = { + "xo", + "mmpll0_pll_out_main", + "mmpll4_pll_out_main", + "mmpll7_pll_out_main", + "mmpll10_pll_out_main", + "gcc_mmss_gpll0_clk", + "gcc_mmss_gpll0_div_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_3[] = { + { P_CXO, 0 }, + { P_MMPLL4_PLL_OUT_MAIN, 1 }, + { P_MMPLL7_PLL_OUT_MAIN, 2 }, + { P_MMPLL10_PLL_OUT_MAIN, 3 }, + { P_CORE_PI_SLEEP_CLK, 4 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_3[] = { + "xo", + "mmpll4_pll_out_main", + "mmpll7_pll_out_main", + "mmpll10_pll_out_main", + "core_pi_sleep_clk", + "gcc_mmss_gpll0_clk", + "gcc_mmss_gpll0_div_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_4[] = { + { P_CXO, 0 }, + { P_MMPLL0_PLL_OUT_MAIN, 1 }, + { P_MMPLL7_PLL_OUT_MAIN, 2 }, + { P_MMPLL10_PLL_OUT_MAIN, 3 }, + { P_CORE_PI_SLEEP_CLK, 4 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_4[] = { + "xo", + "mmpll0_pll_out_main", + "mmpll7_pll_out_main", + "mmpll10_pll_out_main", + "core_pi_sleep_clk", + "gcc_mmss_gpll0_clk", + "gcc_mmss_gpll0_div_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_5[] = { + { P_CXO, 0 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_5[] = { + "xo", + "gcc_mmss_gpll0_clk", + "gcc_mmss_gpll0_div_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_6[] = { + { P_CXO, 0 }, + { P_DP_PHY_PLL_LINK_CLK, 1 }, + { P_DP_PHY_PLL_VCO_DIV, 2 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_6[] = { + "xo", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_7[] = { + { P_CXO, 0 }, + { P_MMPLL0_PLL_OUT_MAIN, 1 }, + { P_MMPLL5_PLL_OUT_MAIN, 2 }, + { P_MMPLL7_PLL_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_7[] = { + "xo", + "mmpll0_pll_out_main", + "mmpll5_pll_out_main", + "mmpll7_pll_out_main", + "gcc_mmss_gpll0_clk", + "gcc_mmss_gpll0_div_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_8[] = { + { P_CXO, 0 }, + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, + { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_8[] = { + "xo", + "dsi0pll_pixel_clk_mux", + "dsi1pll_pixel_clk_mux", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_9[] = { + { P_CXO, 0 }, + { P_MMPLL0_PLL_OUT_MAIN, 1 }, + { P_MMPLL4_PLL_OUT_MAIN, 2 }, + { P_MMPLL7_PLL_OUT_MAIN, 3 }, + { P_MMPLL10_PLL_OUT_MAIN, 4 }, + { P_MMPLL6_PLL_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_9[] = { + "xo", + "mmpll0_pll_out_main", + "mmpll4_pll_out_main", + "mmpll7_pll_out_main", + "mmpll10_pll_out_main", + "mmpll6_pll_out_main", + "gcc_mmss_gpll0_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_10[] = { + { P_CXO, 0 }, + { P_MMPLL0_PLL_OUT_MAIN, 1 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_10[] = { + "xo", + "mmpll0_pll_out_main", + "gcc_mmss_gpll0_clk", + "gcc_mmss_gpll0_div_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_11[] = { + { P_CXO, 0 }, + { P_MMPLL0_PLL_OUT_MAIN, 1 }, + { P_MMPLL4_PLL_OUT_MAIN, 2 }, + { P_MMPLL7_PLL_OUT_MAIN, 3 }, + { P_MMPLL10_PLL_OUT_MAIN, 4 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_MMPLL6_PLL_OUT_MAIN, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_11[] = { + "xo", + "mmpll0_pll_out_main", + "mmpll4_pll_out_main", + "mmpll7_pll_out_main", + "mmpll10_pll_out_main", + "gcc_mmss_gpll0_clk", + "mmpll6_pll_out_main", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_12[] = { + { P_CXO, 0 }, + { P_MMPLL0_PLL_OUT_MAIN, 1 }, + { P_MMPLL8_PLL_OUT_MAIN, 2 }, + { P_MMPLL3_PLL_OUT_MAIN, 3 }, + { P_MMPLL6_PLL_OUT_MAIN, 4 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_MMPLL7_PLL_OUT_MAIN, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_12[] = { + "xo", + "mmpll0_pll_out_main", + "mmpll8_pll_out_main", + "mmpll3_pll_out_main", + "mmpll6_pll_out_main", + "gcc_mmss_gpll0_clk", + "mmpll7_pll_out_main", + "core_bi_pll_test_se", +}; + +/* Voteable PLL */ +static struct clk_alpha_pll mmpll0_pll_out_main = { + .offset = 0xc000, + .clkr = { + .enable_reg = 0x1f0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmpll0_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 404000000, + LOW, 808000000), + }, + }, +}; + +static struct clk_alpha_pll mmpll6_pll_out_main = { + .offset = 0xf0, + .clkr = { + .enable_reg = 0x1f0, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data){ + .name = "mmpll6_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 540000000, + LOW_L1, 1080000000), + }, + }, +}; + +/* APSS controlled PLLs */ +static struct pll_vco vco[] = { + { 1000000000, 2000000000, 0 }, + { 750000000, 1500000000, 1 }, + { 500000000, 1000000000, 2 }, + { 250000000, 500000000, 3 }, +}; + +static const struct pll_config mmpll10_config = { + .l = 0x1e, + .config_ctl_val = 0x00004289, + .main_output_mask = 0x1, +}; + +static struct clk_alpha_pll mmpll10_pll_out_main = { + .offset = 0x190, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mmpll10_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + VDDA_FMAX_MAP1(LOWER, 576000000), + }, + }, +}; + +static struct pll_vco mmpll3_vco[] = { + { 750000000, 1500000000, 1 }, +}; + +static const struct pll_config mmpll3_config = { + .l = 0x2e, + .config_ctl_val = 0x4001055b, + .vco_val = 0x1 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, +}; + +static struct clk_alpha_pll mmpll3_pll_out_main = { + .offset = 0x0, + .vco_table = mmpll3_vco, + .num_vco = ARRAY_SIZE(mmpll3_vco), + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mmpll3_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_slew_ops, + VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 441600000, + NOMINAL, 1036800000), + }, + }, +}; + +static const struct pll_config mmpll4_config = { + .l = 0x28, + .config_ctl_val = 0x4001055b, + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, +}; + +static struct clk_alpha_pll mmpll4_pll_out_main = { + .offset = 0x50, + .vco_table = vco, + .num_vco = ARRAY_SIZE(vco), + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mmpll4_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 384000000, + LOW, 768000000), + }, + }, +}; + +static const struct pll_config mmpll5_config = { + .l = 0x2a, + .config_ctl_val = 0x4001055b, + .alpha_u = 0xf8, + .alpha_en_mask = BIT(24), + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, +}; + +static struct clk_alpha_pll mmpll5_pll_out_main = { + .offset = 0xa0, + .vco_table = vco, + .num_vco = ARRAY_SIZE(vco), + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mmpll5_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 421500000, + LOW, 825000000), + }, + }, +}; + +static const struct pll_config mmpll7_config = { + .l = 0x32, + .config_ctl_val = 0x4001055b, + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, +}; + +static struct clk_alpha_pll mmpll7_pll_out_main = { + .offset = 0x140, + .vco_table = vco, + .num_vco = ARRAY_SIZE(vco), + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mmpll7_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 480000000, + LOW, 960000000), + }, + }, +}; + +static const struct pll_config mmpll8_config = { + .l = 0x30, + .alpha_u = 0x70, + .alpha_en_mask = BIT(24), + .config_ctl_val = 0x4001055b, + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, +}; + +static struct clk_alpha_pll mmpll8_pll_out_main = { + .offset = 0x1c0, + .vco_table = vco, + .num_vco = ARRAY_SIZE(vco), + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mmpll8_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 465000000, + LOW, 930000000), + }, + }, +}; + +static const struct freq_tbl ftbl_ahb_clk_src[] = { + F(19200000, P_CXO, 1, 0, 0), + F(40000000, P_GPLL0_OUT_MAIN_DIV, 7.5, 0, 0), + F(80800000, P_MMPLL0_PLL_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 ahb_clk_src = { + .cmd_rcgr = 0x5000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_10, + .freq_tbl = ftbl_ahb_clk_src, + .flags = FORCE_ENABLE_RCGR, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ahb_clk_src", + .parent_names = mmcc_parent_names_10, + .num_parents = 5, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 40000000, + NOMINAL, 80800000), + }, +}; + +static struct clk_rcg2 byte0_clk_src = { + .cmd_rcgr = 0x2120, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data){ + .name = "byte0_clk_src", + .parent_names = mmcc_parent_names_1, + .num_parents = 4, + .ops = &clk_byte2_ops, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + VDD_DIG_FMAX_MAP3( + LOWER, 131250000, + LOW, 210000000, + NOMINAL, 262500000), + }, +}; + +static struct clk_rcg2 byte1_clk_src = { + .cmd_rcgr = 0x2140, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data){ + .name = "byte1_clk_src", + .parent_names = mmcc_parent_names_1, + .num_parents = 4, + .ops = &clk_byte2_ops, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + VDD_DIG_FMAX_MAP3( + LOWER, 131250000, + LOW, 210000000, + NOMINAL, 262500000), + }, +}; + +static const struct freq_tbl ftbl_camss_gp0_clk_src[] = { + F(10000, P_CXO, 16, 1, 120), + F(24000, P_CXO, 16, 1, 50), + F(6000000, P_GPLL0_OUT_MAIN_DIV, 10, 1, 5), + F(12000000, P_GPLL0_OUT_MAIN_DIV, 10, 2, 5), + F(13043478, P_GPLL0_OUT_MAIN_DIV, 1, 1, 23), + F(24000000, P_GPLL0_OUT_MAIN_DIV, 1, 2, 25), + F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN_DIV, 3, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 camss_gp0_clk_src = { + .cmd_rcgr = 0x3420, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_4, + .freq_tbl = ftbl_camss_gp0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "camss_gp0_clk_src", + .parent_names = mmcc_parent_names_4, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 50000000, + LOW, 100000000, + NOMINAL, 200000000), + }, +}; + +static struct clk_rcg2 camss_gp1_clk_src = { + .cmd_rcgr = 0x3450, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_4, + .freq_tbl = ftbl_camss_gp0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "camss_gp1_clk_src", + .parent_names = mmcc_parent_names_4, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 50000000, + LOW, 100000000, + NOMINAL, 200000000), + }, +}; + +static const struct freq_tbl ftbl_cci_clk_src[] = { + F(37500000, P_GPLL0_OUT_MAIN_DIV, 8, 0, 0), + F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_rcg2 cci_clk_src = { + .cmd_rcgr = 0x3300, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_4, + .freq_tbl = ftbl_cci_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cci_clk_src", + .parent_names = mmcc_parent_names_4, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 37500000, + LOW, 50000000, + NOMINAL, 100000000), + }, +}; + +static const struct freq_tbl ftbl_cpp_clk_src[] = { + F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), + F(256000000, P_MMPLL4_PLL_OUT_MAIN, 3, 0, 0), + F(384000000, P_MMPLL4_PLL_OUT_MAIN, 2, 0, 0), + F(480000000, P_MMPLL7_PLL_OUT_MAIN, 2, 0, 0), + F(540000000, P_MMPLL6_PLL_OUT_MAIN, 2, 0, 0), + F(576000000, P_MMPLL10_PLL_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cpp_clk_src = { + .cmd_rcgr = 0x3640, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_11, + .freq_tbl = ftbl_cpp_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cpp_clk_src", + .parent_names = mmcc_parent_names_11, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP6( + LOWER, 120000000, + LOW, 256000000, + LOW_L1, 384000000, + NOMINAL, 480000000, + NOMINAL_L1, 540000000, + HIGH, 576000000), + }, +}; + +static const struct freq_tbl ftbl_csi0_clk_src[] = { + F(100000000, P_GPLL0_OUT_MAIN_DIV, 3, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(310000000, P_MMPLL8_PLL_OUT_MAIN, 3, 0, 0), + F(404000000, P_MMPLL0_PLL_OUT_MAIN, 2, 0, 0), + F(465000000, P_MMPLL8_PLL_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 csi0_clk_src = { + .cmd_rcgr = 0x3090, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_0, + .freq_tbl = ftbl_csi0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi0_clk_src", + .parent_names = mmcc_parent_names_0, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP5( + LOWER, 100000000, + LOW, 200000000, + LOW_L1, 310000000, + NOMINAL, 404000000, + NOMINAL_L1, 465000000), + }, +}; + +static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = { + F(100000000, P_GPLL0_OUT_MAIN_DIV, 3, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(269333333, P_MMPLL0_PLL_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 csi0phytimer_clk_src = { + .cmd_rcgr = 0x3000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_2, + .freq_tbl = ftbl_csi0phytimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi0phytimer_clk_src", + .parent_names = mmcc_parent_names_2, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 100000000, + LOW, 200000000, + LOW_L1, 269333333), + }, +}; + +static struct clk_rcg2 csi1_clk_src = { + .cmd_rcgr = 0x3100, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_0, + .freq_tbl = ftbl_csi0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi1_clk_src", + .parent_names = mmcc_parent_names_0, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP5( + LOWER, 100000000, + LOW, 200000000, + LOW_L1, 310000000, + NOMINAL, 404000000, + NOMINAL_L1, 465000000), + }, +}; + +static struct clk_rcg2 csi1phytimer_clk_src = { + .cmd_rcgr = 0x3030, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_2, + .freq_tbl = ftbl_csi0phytimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi1phytimer_clk_src", + .parent_names = mmcc_parent_names_2, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 100000000, + LOW, 200000000, + LOW_L1, 269333333), + }, +}; + +static struct clk_rcg2 csi2_clk_src = { + .cmd_rcgr = 0x3160, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_0, + .freq_tbl = ftbl_csi0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi2_clk_src", + .parent_names = mmcc_parent_names_0, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP5( + LOWER, 100000000, + LOW, 200000000, + LOW_L1, 310000000, + NOMINAL, 404000000, + NOMINAL_L1, 465000000), + }, +}; + +static struct clk_rcg2 csi2phytimer_clk_src = { + .cmd_rcgr = 0x3060, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_2, + .freq_tbl = ftbl_csi0phytimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi2phytimer_clk_src", + .parent_names = mmcc_parent_names_2, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 100000000, + LOW, 200000000, + LOW_L1, 269333333), + }, +}; + +static struct clk_rcg2 csi3_clk_src = { + .cmd_rcgr = 0x31c0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_0, + .freq_tbl = ftbl_csi0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi3_clk_src", + .parent_names = mmcc_parent_names_0, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP5( + LOWER, 100000000, + LOW, 200000000, + LOW_L1, 310000000, + NOMINAL, 404000000, + NOMINAL_L1, 465000000), + }, +}; + +static const struct freq_tbl ftbl_csiphy_clk_src[] = { + F(100000000, P_GPLL0_OUT_MAIN_DIV, 3, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(269333333, P_MMPLL0_PLL_OUT_MAIN, 3, 0, 0), + F(320000000, P_MMPLL7_PLL_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 csiphy_clk_src = { + .cmd_rcgr = 0x3800, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_0, + .freq_tbl = ftbl_csiphy_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csiphy_clk_src", + .parent_names = mmcc_parent_names_0, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4( + LOWER, 100000000, + LOW, 200000000, + LOW_L1, 269333333, + NOMINAL, 320000000), + }, +}; + +static const struct freq_tbl ftbl_dp_aux_clk_src[] = { + F(19200000, P_CXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 dp_aux_clk_src = { + .cmd_rcgr = 0x2260, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_5, + .freq_tbl = ftbl_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "dp_aux_clk_src", + .parent_names = mmcc_parent_names_5, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1( + LOWER, 19200000), + }, +}; + +static const struct freq_tbl ftbl_dp_crypto_clk_src[] = { + F(101250000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0), + F(168750000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0), + F(337500000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0), + { } +}; + +static struct clk_rcg2 dp_crypto_clk_src = { + .cmd_rcgr = 0x2220, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_6, + .freq_tbl = ftbl_dp_crypto_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "dp_crypto_clk_src", + .parent_names = mmcc_parent_names_6, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 101250000, + LOW, 168750000, + NOMINAL, 337500000), + }, +}; + +static const struct freq_tbl ftbl_dp_gtc_clk_src[] = { + F(40000000, P_GPLL0_OUT_MAIN_DIV, 7.5, 0, 0), + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 dp_gtc_clk_src = { + .cmd_rcgr = 0x2280, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_5, + .freq_tbl = ftbl_dp_gtc_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "dp_gtc_clk_src", + .parent_names = mmcc_parent_names_5, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 40000000, + LOW, 60000000), + }, +}; + +static const struct freq_tbl ftbl_dp_link_clk_src[] = { + F(162000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0), + F(270000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0), + F(540000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0), + { } +}; + +static struct clk_rcg2 dp_link_clk_src = { + .cmd_rcgr = 0x2200, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_6, + .freq_tbl = ftbl_dp_link_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "dp_link_clk_src", + .parent_names = mmcc_parent_names_6, + .num_parents = 4, + .ops = &clk_rcg2_ops, + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, + VDD_DIG_FMAX_MAP3( + LOWER, 162000000, + LOW, 270000000, + NOMINAL, 540000000), + }, +}; + +static struct clk_rcg2 dp_pixel_clk_src = { + .cmd_rcgr = 0x2240, + .mnd_width = 16, + .hid_width = 5, + .parent_map = mmcc_parent_map_6, + .clkr.hw.init = &(struct clk_init_data){ + .name = "dp_pixel_clk_src", + .parent_names = mmcc_parent_names_6, + .num_parents = 4, + .ops = &clk_dp_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 148380000, + LOW, 296740000, + NOMINAL, 593470000), + }, +}; + +static struct clk_rcg2 esc0_clk_src = { + .cmd_rcgr = 0x2160, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_1, + .freq_tbl = ftbl_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "esc0_clk_src", + .parent_names = mmcc_parent_names_1, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1( + LOWER, 19200000), + }, +}; + +static struct clk_rcg2 esc1_clk_src = { + .cmd_rcgr = 0x2180, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_1, + .freq_tbl = ftbl_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "esc1_clk_src", + .parent_names = mmcc_parent_names_1, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1( + LOWER, 19200000), + }, +}; + +static const struct freq_tbl ftbl_jpeg0_clk_src[] = { + F(66666667, P_GPLL0_OUT_MAIN_DIV, 4.5, 0, 0), + F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), + F(219428571, P_MMPLL4_PLL_OUT_MAIN, 3.5, 0, 0), + F(320000000, P_MMPLL7_PLL_OUT_MAIN, 3, 0, 0), + F(480000000, P_MMPLL7_PLL_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 jpeg0_clk_src = { + .cmd_rcgr = 0x3500, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_2, + .freq_tbl = ftbl_jpeg0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "jpeg0_clk_src", + .parent_names = mmcc_parent_names_2, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP5( + LOWER, 66666667, + LOW, 133333333, + LOW_L1, 219428571, + NOMINAL, 320000000, + NOMINAL_L1, 480000000), + }, +}; + +static const struct freq_tbl ftbl_mclk0_clk_src[] = { + F(4800000, P_CXO, 4, 0, 0), + F(6000000, P_GPLL0_OUT_MAIN_DIV, 10, 1, 5), + F(8000000, P_GPLL0_OUT_MAIN_DIV, 1, 2, 75), + F(9600000, P_CXO, 2, 0, 0), + F(16666667, P_GPLL0_OUT_MAIN_DIV, 2, 1, 9), + F(19200000, P_CXO, 1, 0, 0), + F(24000000, P_GPLL0_OUT_MAIN_DIV, 1, 2, 25), + F(33333333, P_GPLL0_OUT_MAIN_DIV, 1, 1, 9), + F(48000000, P_GPLL0_OUT_MAIN, 1, 2, 25), + F(66666667, P_GPLL0_OUT_MAIN, 1, 1, 9), + { } +}; + +static struct clk_rcg2 mclk0_clk_src = { + .cmd_rcgr = 0x3360, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_3, + .freq_tbl = ftbl_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mclk0_clk_src", + .parent_names = mmcc_parent_names_3, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 33333333, + LOW, 66666667), + }, +}; + +static struct clk_rcg2 mclk1_clk_src = { + .cmd_rcgr = 0x3390, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_3, + .freq_tbl = ftbl_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mclk1_clk_src", + .parent_names = mmcc_parent_names_3, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 33333333, + LOW, 66666667), + }, +}; + +static struct clk_rcg2 mclk2_clk_src = { + .cmd_rcgr = 0x33c0, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_3, + .freq_tbl = ftbl_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mclk2_clk_src", + .parent_names = mmcc_parent_names_3, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 33333333, + LOW, 66666667), + }, +}; + +static struct clk_rcg2 mclk3_clk_src = { + .cmd_rcgr = 0x33f0, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_3, + .freq_tbl = ftbl_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mclk3_clk_src", + .parent_names = mmcc_parent_names_3, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 33333333, + LOW, 66666667), + }, +}; + +static const struct freq_tbl ftbl_mdp_clk_src[] = { + F(100000000, P_GPLL0_OUT_MAIN_DIV, 3, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0), + F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(275000000, P_MMPLL5_PLL_OUT_MAIN, 3, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + F(330000000, P_MMPLL5_PLL_OUT_MAIN, 2.5, 0, 0), + F(412500000, P_MMPLL5_PLL_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 mdp_clk_src = { + .cmd_rcgr = 0x2040, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_7, + .freq_tbl = ftbl_mdp_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mdp_clk_src", + .parent_names = mmcc_parent_names_7, + .num_parents = 7, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP5( + LOWER, 171428571, + LOW, 275000000, + LOW_L1, 300000000, + NOMINAL, 330000000, + HIGH, 412500000), + }, +}; + +static struct clk_rcg2 pclk0_clk_src = { + .cmd_rcgr = 0x2000, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_8, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pclk0_clk_src", + .parent_names = mmcc_parent_names_8, + .num_parents = 4, + .ops = &clk_pixel_ops, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + VDD_DIG_FMAX_MAP3( + LOWER, 175000000, + LOW, 280000000, + NOMINAL, 350000000), + }, +}; + +static struct clk_rcg2 pclk1_clk_src = { + .cmd_rcgr = 0x2020, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_8, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pclk1_clk_src", + .parent_names = mmcc_parent_names_8, + .num_parents = 4, + .ops = &clk_pixel_ops, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + VDD_DIG_FMAX_MAP3( + LOWER, 175000000, + LOW, 280000000, + NOMINAL, 350000000), + }, +}; + +static const struct freq_tbl ftbl_rot_clk_src[] = { + F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0), + F(275000000, P_MMPLL5_PLL_OUT_MAIN, 3, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + F(330000000, P_MMPLL5_PLL_OUT_MAIN, 2.5, 0, 0), + F(412500000, P_MMPLL5_PLL_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 rot_clk_src = { + .cmd_rcgr = 0x21a0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_7, + .freq_tbl = ftbl_rot_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "rot_clk_src", + .parent_names = mmcc_parent_names_7, + .num_parents = 7, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP5( + LOWER, 171428571, + LOW, 275000000, + LOW_L1, 300000000, + NOMINAL, 330000000, + HIGH, 412500000), + }, +}; + +static const struct freq_tbl ftbl_vfe0_clk_src[] = { + F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(256000000, P_MMPLL4_PLL_OUT_MAIN, 3, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + F(404000000, P_MMPLL0_PLL_OUT_MAIN, 2, 0, 0), + F(480000000, P_MMPLL7_PLL_OUT_MAIN, 2, 0, 0), + F(540000000, P_MMPLL6_PLL_OUT_MAIN, 2, 0, 0), + F(576000000, P_MMPLL10_PLL_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 vfe0_clk_src = { + .cmd_rcgr = 0x3600, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_9, + .freq_tbl = ftbl_vfe0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "vfe0_clk_src", + .parent_names = mmcc_parent_names_9, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP6( + LOWER, 120000000, + LOW, 256000000, + LOW_L1, 404000000, + NOMINAL, 480000000, + NOMINAL_L1, 540000000, + HIGH, 576000000), + }, +}; + +static struct clk_rcg2 vfe1_clk_src = { + .cmd_rcgr = 0x3620, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_9, + .freq_tbl = ftbl_vfe0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "vfe1_clk_src", + .parent_names = mmcc_parent_names_9, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP6( + LOWER, 120000000, + LOW, 256000000, + LOW_L1, 404000000, + NOMINAL, 480000000, + NOMINAL_L1, 540000000, + HIGH, 576000000), + }, +}; + +static const struct freq_tbl ftbl_video_core_clk_src[] = { + F_SLEW(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0, FIXED_FREQ_SRC), + F_SLEW(269333333, P_MMPLL0_PLL_OUT_MAIN, 3, 0, 0, FIXED_FREQ_SRC), + F_SLEW(320000000, P_MMPLL7_PLL_OUT_MAIN, 3, 0, 0, FIXED_FREQ_SRC), + F_SLEW(404000000, P_MMPLL0_PLL_OUT_MAIN, 2, 0, 0, FIXED_FREQ_SRC), + F_SLEW(441600000, P_MMPLL3_PLL_OUT_MAIN, 2, 0, 0, 883200000), + F_SLEW(518400000, P_MMPLL3_PLL_OUT_MAIN, 2, 0, 0, 1036800000), + { } +}; + +static struct clk_rcg2 video_core_clk_src = { + .cmd_rcgr = 0x1000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_12, + .freq_tbl = ftbl_video_core_clk_src, + .flags = FORCE_ENABLE_RCGR, + .clkr.hw.init = &(struct clk_init_data){ + .name = "video_core_clk_src", + .parent_names = mmcc_parent_names_12, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP6( + LOWER, 133333333, + LOW, 269333333, + LOW_L1, 320000000, + NOMINAL, 404000000, + NOMINAL_L1, 441600000, + HIGH, 518400000), + }, +}; + +static struct clk_rcg2 vsync_clk_src = { + .cmd_rcgr = 0x2080, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_5, + .freq_tbl = ftbl_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "vsync_clk_src", + .parent_names = mmcc_parent_names_5, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1( + LOWER, 19200000), + }, +}; + +static struct clk_branch mmss_bimc_smmu_ahb_clk = { + .halt_reg = 0xe004, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0xe004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_bimc_smmu_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .flags = CLK_ENABLE_HAND_OFF, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_bimc_smmu_axi_clk = { + .halt_reg = 0xe008, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0xe008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_bimc_smmu_axi_clk", + .flags = CLK_ENABLE_HAND_OFF, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_ahb_clk = { + .halt_reg = 0x348c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x348c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cci_ahb_clk = { + .halt_reg = 0x3348, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3348, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cci_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cci_clk = { + .halt_reg = 0x3344, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3344, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cci_clk", + .parent_names = (const char *[]){ + "cci_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cphy_csid0_clk = { + .halt_reg = 0x3730, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3730, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cphy_csid0_clk", + .parent_names = (const char *[]){ + "csiphy_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cphy_csid1_clk = { + .halt_reg = 0x3734, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3734, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cphy_csid1_clk", + .parent_names = (const char *[]){ + "csiphy_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cphy_csid2_clk = { + .halt_reg = 0x3738, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3738, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cphy_csid2_clk", + .parent_names = (const char *[]){ + "csiphy_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cphy_csid3_clk = { + .halt_reg = 0x373c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x373c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cphy_csid3_clk", + .parent_names = (const char *[]){ + "csiphy_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cpp_ahb_clk = { + .halt_reg = 0x36b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36b4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cpp_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cpp_axi_clk = { + .halt_reg = 0x36c4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36c4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cpp_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cpp_clk = { + .halt_reg = 0x36b0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36b0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cpp_clk", + .parent_names = (const char *[]){ + "cpp_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cpp_vbif_ahb_clk = { + .halt_reg = 0x36c8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36c8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cpp_vbif_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi0_ahb_clk = { + .halt_reg = 0x30bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x30bc, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi0_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi0_clk = { + .halt_reg = 0x30b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x30b4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi0_clk", + .parent_names = (const char *[]){ + "csi0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi0phytimer_clk = { + .halt_reg = 0x3024, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3024, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi0phytimer_clk", + .parent_names = (const char *[]){ + "csi0phytimer_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi0pix_clk = { + .halt_reg = 0x30e4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x30e4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi0pix_clk", + .parent_names = (const char *[]){ + "csi0_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi0rdi_clk = { + .halt_reg = 0x30d4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x30d4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi0rdi_clk", + .parent_names = (const char *[]){ + "csi0_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi1_ahb_clk = { + .halt_reg = 0x3128, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3128, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi1_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi1_clk = { + .halt_reg = 0x3124, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3124, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi1_clk", + .parent_names = (const char *[]){ + "csi1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi1phytimer_clk = { + .halt_reg = 0x3054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi1phytimer_clk", + .parent_names = (const char *[]){ + "csi1phytimer_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi1pix_clk = { + .halt_reg = 0x3154, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3154, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi1pix_clk", + .parent_names = (const char *[]){ + "csi1_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi1rdi_clk = { + .halt_reg = 0x3144, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3144, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi1rdi_clk", + .parent_names = (const char *[]){ + "csi1_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi2_ahb_clk = { + .halt_reg = 0x3188, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3188, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi2_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi2_clk = { + .halt_reg = 0x3184, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3184, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi2_clk", + .parent_names = (const char *[]){ + "csi2_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi2phytimer_clk = { + .halt_reg = 0x3084, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3084, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi2phytimer_clk", + .parent_names = (const char *[]){ + "csi2phytimer_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi2pix_clk = { + .halt_reg = 0x31b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x31b4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi2pix_clk", + .parent_names = (const char *[]){ + "csi2_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi2rdi_clk = { + .halt_reg = 0x31a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x31a4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi2rdi_clk", + .parent_names = (const char *[]){ + "csi2_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi3_ahb_clk = { + .halt_reg = 0x31e8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x31e8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi3_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi3_clk = { + .halt_reg = 0x31e4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x31e4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi3_clk", + .parent_names = (const char *[]){ + "csi3_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi3pix_clk = { + .halt_reg = 0x3214, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3214, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi3pix_clk", + .parent_names = (const char *[]){ + "csi3_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi3rdi_clk = { + .halt_reg = 0x3204, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3204, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi3rdi_clk", + .parent_names = (const char *[]){ + "csi3_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi_vfe0_clk = { + .halt_reg = 0x3704, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3704, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi_vfe0_clk", + .parent_names = (const char *[]){ + "vfe0_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi_vfe1_clk = { + .halt_reg = 0x3714, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3714, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi_vfe1_clk", + .parent_names = (const char *[]){ + "vfe1_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csiphy0_clk = { + .halt_reg = 0x3740, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3740, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csiphy0_clk", + .parent_names = (const char *[]){ + "csiphy_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csiphy1_clk = { + .halt_reg = 0x3744, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3744, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csiphy1_clk", + .parent_names = (const char *[]){ + "csiphy_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csiphy2_clk = { + .halt_reg = 0x3748, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3748, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csiphy2_clk", + .parent_names = (const char *[]){ + "csiphy_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_gp0_clk = { + .halt_reg = 0x3444, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3444, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_gp0_clk", + .parent_names = (const char *[]){ + "camss_gp0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_gp1_clk = { + .halt_reg = 0x3474, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3474, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_gp1_clk", + .parent_names = (const char *[]){ + "camss_gp1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_ispif_ahb_clk = { + .halt_reg = 0x3224, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3224, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_ispif_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_jpeg0_clk = { + .halt_reg = 0x35a8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x35a8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_jpeg0_clk", + .parent_names = (const char *[]){ + "jpeg0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static DEFINE_CLK_VOTER(mmss_camss_jpeg0_vote_clk, mmss_camss_jpeg0_clk, 0); +static DEFINE_CLK_VOTER(mmss_camss_jpeg0_dma_vote_clk, + mmss_camss_jpeg0_clk, 0); + +static struct clk_branch mmss_camss_jpeg_ahb_clk = { + .halt_reg = 0x35b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x35b4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_jpeg_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_jpeg_axi_clk = { + .halt_reg = 0x35b8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x35b8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_jpeg_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_mclk0_clk = { + .halt_reg = 0x3384, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3384, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_mclk0_clk", + .parent_names = (const char *[]){ + "mclk0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_mclk1_clk = { + .halt_reg = 0x33b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x33b4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_mclk1_clk", + .parent_names = (const char *[]){ + "mclk1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_mclk2_clk = { + .halt_reg = 0x33e4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x33e4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_mclk2_clk", + .parent_names = (const char *[]){ + "mclk2_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_mclk3_clk = { + .halt_reg = 0x3414, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3414, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_mclk3_clk", + .parent_names = (const char *[]){ + "mclk3_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_micro_ahb_clk = { + .halt_reg = 0x3494, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3494, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_micro_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_top_ahb_clk = { + .halt_reg = 0x3484, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3484, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_top_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_vfe0_ahb_clk = { + .halt_reg = 0x3668, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3668, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_vfe0_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_vfe0_clk = { + .halt_reg = 0x36a8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36a8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_vfe0_clk", + .parent_names = (const char *[]){ + "vfe0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_vfe0_stream_clk = { + .halt_reg = 0x3720, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3720, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_vfe0_stream_clk", + .parent_names = (const char *[]){ + "vfe0_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_vfe1_ahb_clk = { + .halt_reg = 0x3678, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3678, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_vfe1_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_vfe1_clk = { + .halt_reg = 0x36ac, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36ac, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_vfe1_clk", + .parent_names = (const char *[]){ + "vfe1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_vfe1_stream_clk = { + .halt_reg = 0x3724, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3724, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_vfe1_stream_clk", + .parent_names = (const char *[]){ + "vfe1_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_vfe_vbif_ahb_clk = { + .halt_reg = 0x36b8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36b8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_vfe_vbif_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_vfe_vbif_axi_clk = { + .halt_reg = 0x36bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36bc, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_vfe_vbif_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_csiphy_ahb2crif_clk = { + .halt_reg = 0x374c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x374c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_csiphy_ahb2crif_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_ahb_clk = { + .halt_reg = 0x2308, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2308, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .flags = CLK_ENABLE_HAND_OFF, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_axi_clk = { + .halt_reg = 0x2310, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2310, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_byte0_clk = { + .halt_reg = 0x233c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x233c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_byte0_clk", + .parent_names = (const char *[]){ + "byte0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_byte0_intf_clk = { + .halt_reg = 0x2374, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2374, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_byte0_intf_clk", + .parent_names = (const char *[]){ + "mmss_mdss_byte0_intf_div_clk", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_div mmss_mdss_byte0_intf_div_clk = { + .reg = 0x237c, + .shift = 0, + .width = 2, + /* + * NOTE: Op does not work for div-3. Current assumption is that div-3 + * is not a recommended setting for this divider. + */ + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_byte0_intf_div_clk", + .parent_names = (const char *[]){ + "byte0_clk_src", + }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + }, + }, +}; + +static struct clk_branch mmss_mdss_byte1_clk = { + .halt_reg = 0x2340, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2340, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_byte1_clk", + .parent_names = (const char *[]){ + "byte1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_byte1_intf_clk = { + .halt_reg = 0x2378, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2378, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_byte1_intf_clk", + .parent_names = (const char *[]){ + "byte1_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_dp_aux_clk = { + .halt_reg = 0x2364, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2364, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_dp_aux_clk", + .parent_names = (const char *[]){ + "dp_aux_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_dp_crypto_clk = { + .halt_reg = 0x235c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x235c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_dp_crypto_clk", + .parent_names = (const char *[]){ + "dp_crypto_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_dp_gtc_clk = { + .halt_reg = 0x2368, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2368, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_dp_gtc_clk", + .parent_names = (const char *[]){ + "dp_gtc_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_dp_link_clk = { + .halt_reg = 0x2354, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2354, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_dp_link_clk", + .parent_names = (const char *[]){ + "dp_link_clk_src", + }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +/* Reset state of MMSS_MDSS_DP_LINK_INTF_DIV is 0x3 (div-4) */ +static struct clk_branch mmss_mdss_dp_link_intf_clk = { + .halt_reg = 0x2358, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2358, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_dp_link_intf_clk", + .parent_names = (const char *[]){ + "dp_link_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_dp_pixel_clk = { + .halt_reg = 0x2360, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2360, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_dp_pixel_clk", + .parent_names = (const char *[]){ + "dp_pixel_clk_src", + }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_esc0_clk = { + .halt_reg = 0x2344, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2344, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_esc0_clk", + .parent_names = (const char *[]){ + "esc0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_esc1_clk = { + .halt_reg = 0x2348, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2348, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_esc1_clk", + .parent_names = (const char *[]){ + "esc1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_hdmi_dp_ahb_clk = { + .halt_reg = 0x230c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x230c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_hdmi_dp_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_mdp_clk = { + .halt_reg = 0x231c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x231c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_mdp_clk", + .parent_names = (const char *[]){ + "mdp_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_ENABLE_HAND_OFF, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_pclk0_clk = { + .halt_reg = 0x2314, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2314, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_pclk0_clk", + .parent_names = (const char *[]){ + "pclk0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_pclk1_clk = { + .halt_reg = 0x2318, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2318, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_pclk1_clk", + .parent_names = (const char *[]){ + "pclk1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_rot_clk = { + .halt_reg = 0x2350, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2350, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_rot_clk", + .parent_names = (const char *[]){ + "rot_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_vsync_clk = { + .halt_reg = 0x2328, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2328, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_vsync_clk", + .parent_names = (const char *[]){ + "vsync_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_misc_ahb_clk = { + .halt_reg = 0x328, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x328, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_misc_ahb_clk", + /* + * Dependency to be enabled before the branch is + * enabled. + */ + .parent_names = (const char *[]){ + "mmss_mnoc_ahb_clk", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_misc_cxo_clk = { + .halt_reg = 0x324, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x324, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_misc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mnoc_ahb_clk = { + .halt_reg = 0x5024, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x5024, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mnoc_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_snoc_dvm_axi_clk = { + .halt_reg = 0xe040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xe040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_snoc_dvm_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_video_ahb_clk = { + .halt_reg = 0x1030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1030, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_video_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_video_axi_clk = { + .halt_reg = 0x1034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_video_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_video_core_clk = { + .halt_reg = 0x1028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1028, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_video_core_clk", + .parent_names = (const char *[]){ + "video_core_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_video_subcore0_clk = { + .halt_reg = 0x1048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1048, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_video_subcore0_clk", + .parent_names = (const char *[]){ + "video_core_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +struct clk_hw *mmcc_sdm660_hws[] = { + [MMSS_CAMSS_JPEG0_VOTE_CLK] = &mmss_camss_jpeg0_vote_clk.hw, + [MMSS_CAMSS_JPEG0_DMA_VOTE_CLK] = &mmss_camss_jpeg0_dma_vote_clk.hw, +}; + +static struct clk_regmap *mmcc_660_clocks[] = { + [AHB_CLK_SRC] = &ahb_clk_src.clkr, + [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, + [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, + [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, + [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, + [CCI_CLK_SRC] = &cci_clk_src.clkr, + [CPP_CLK_SRC] = &cpp_clk_src.clkr, + [CSI0_CLK_SRC] = &csi0_clk_src.clkr, + [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, + [CSI1_CLK_SRC] = &csi1_clk_src.clkr, + [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, + [CSI2_CLK_SRC] = &csi2_clk_src.clkr, + [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr, + [CSI3_CLK_SRC] = &csi3_clk_src.clkr, + [CSIPHY_CLK_SRC] = &csiphy_clk_src.clkr, + [DP_AUX_CLK_SRC] = &dp_aux_clk_src.clkr, + [DP_CRYPTO_CLK_SRC] = &dp_crypto_clk_src.clkr, + [DP_GTC_CLK_SRC] = &dp_gtc_clk_src.clkr, + [DP_LINK_CLK_SRC] = &dp_link_clk_src.clkr, + [DP_PIXEL_CLK_SRC] = &dp_pixel_clk_src.clkr, + [ESC0_CLK_SRC] = &esc0_clk_src.clkr, + [ESC1_CLK_SRC] = &esc1_clk_src.clkr, + [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, + [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, + [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, + [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr, + [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr, + [MDP_CLK_SRC] = &mdp_clk_src.clkr, + [MMPLL0_PLL] = &mmpll0_pll_out_main.clkr, + [MMPLL10_PLL] = &mmpll10_pll_out_main.clkr, + [MMPLL3_PLL] = &mmpll3_pll_out_main.clkr, + [MMPLL4_PLL] = &mmpll4_pll_out_main.clkr, + [MMPLL5_PLL] = &mmpll5_pll_out_main.clkr, + [MMPLL6_PLL] = &mmpll6_pll_out_main.clkr, + [MMPLL7_PLL] = &mmpll7_pll_out_main.clkr, + [MMPLL8_PLL] = &mmpll8_pll_out_main.clkr, + [MMSS_BIMC_SMMU_AHB_CLK] = &mmss_bimc_smmu_ahb_clk.clkr, + [MMSS_BIMC_SMMU_AXI_CLK] = &mmss_bimc_smmu_axi_clk.clkr, + [MMSS_CAMSS_AHB_CLK] = &mmss_camss_ahb_clk.clkr, + [MMSS_CAMSS_CCI_AHB_CLK] = &mmss_camss_cci_ahb_clk.clkr, + [MMSS_CAMSS_CCI_CLK] = &mmss_camss_cci_clk.clkr, + [MMSS_CAMSS_CPHY_CSID0_CLK] = &mmss_camss_cphy_csid0_clk.clkr, + [MMSS_CAMSS_CPHY_CSID1_CLK] = &mmss_camss_cphy_csid1_clk.clkr, + [MMSS_CAMSS_CPHY_CSID2_CLK] = &mmss_camss_cphy_csid2_clk.clkr, + [MMSS_CAMSS_CPHY_CSID3_CLK] = &mmss_camss_cphy_csid3_clk.clkr, + [MMSS_CAMSS_CPP_AHB_CLK] = &mmss_camss_cpp_ahb_clk.clkr, + [MMSS_CAMSS_CPP_AXI_CLK] = &mmss_camss_cpp_axi_clk.clkr, + [MMSS_CAMSS_CPP_CLK] = &mmss_camss_cpp_clk.clkr, + [MMSS_CAMSS_CPP_VBIF_AHB_CLK] = &mmss_camss_cpp_vbif_ahb_clk.clkr, + [MMSS_CAMSS_CSI0_AHB_CLK] = &mmss_camss_csi0_ahb_clk.clkr, + [MMSS_CAMSS_CSI0_CLK] = &mmss_camss_csi0_clk.clkr, + [MMSS_CAMSS_CSI0PHYTIMER_CLK] = &mmss_camss_csi0phytimer_clk.clkr, + [MMSS_CAMSS_CSI0PIX_CLK] = &mmss_camss_csi0pix_clk.clkr, + [MMSS_CAMSS_CSI0RDI_CLK] = &mmss_camss_csi0rdi_clk.clkr, + [MMSS_CAMSS_CSI1_AHB_CLK] = &mmss_camss_csi1_ahb_clk.clkr, + [MMSS_CAMSS_CSI1_CLK] = &mmss_camss_csi1_clk.clkr, + [MMSS_CAMSS_CSI1PHYTIMER_CLK] = &mmss_camss_csi1phytimer_clk.clkr, + [MMSS_CAMSS_CSI1PIX_CLK] = &mmss_camss_csi1pix_clk.clkr, + [MMSS_CAMSS_CSI1RDI_CLK] = &mmss_camss_csi1rdi_clk.clkr, + [MMSS_CAMSS_CSI2_AHB_CLK] = &mmss_camss_csi2_ahb_clk.clkr, + [MMSS_CAMSS_CSI2_CLK] = &mmss_camss_csi2_clk.clkr, + [MMSS_CAMSS_CSI2PHYTIMER_CLK] = &mmss_camss_csi2phytimer_clk.clkr, + [MMSS_CAMSS_CSI2PIX_CLK] = &mmss_camss_csi2pix_clk.clkr, + [MMSS_CAMSS_CSI2RDI_CLK] = &mmss_camss_csi2rdi_clk.clkr, + [MMSS_CAMSS_CSI3_AHB_CLK] = &mmss_camss_csi3_ahb_clk.clkr, + [MMSS_CAMSS_CSI3_CLK] = &mmss_camss_csi3_clk.clkr, + [MMSS_CAMSS_CSI3PIX_CLK] = &mmss_camss_csi3pix_clk.clkr, + [MMSS_CAMSS_CSI3RDI_CLK] = &mmss_camss_csi3rdi_clk.clkr, + [MMSS_CAMSS_CSI_VFE0_CLK] = &mmss_camss_csi_vfe0_clk.clkr, + [MMSS_CAMSS_CSI_VFE1_CLK] = &mmss_camss_csi_vfe1_clk.clkr, + [MMSS_CAMSS_CSIPHY0_CLK] = &mmss_camss_csiphy0_clk.clkr, + [MMSS_CAMSS_CSIPHY1_CLK] = &mmss_camss_csiphy1_clk.clkr, + [MMSS_CAMSS_CSIPHY2_CLK] = &mmss_camss_csiphy2_clk.clkr, + [MMSS_CAMSS_GP0_CLK] = &mmss_camss_gp0_clk.clkr, + [MMSS_CAMSS_GP1_CLK] = &mmss_camss_gp1_clk.clkr, + [MMSS_CAMSS_ISPIF_AHB_CLK] = &mmss_camss_ispif_ahb_clk.clkr, + [MMSS_CAMSS_JPEG0_CLK] = &mmss_camss_jpeg0_clk.clkr, + [MMSS_CAMSS_JPEG_AHB_CLK] = &mmss_camss_jpeg_ahb_clk.clkr, + [MMSS_CAMSS_JPEG_AXI_CLK] = &mmss_camss_jpeg_axi_clk.clkr, + [MMSS_CAMSS_MCLK0_CLK] = &mmss_camss_mclk0_clk.clkr, + [MMSS_CAMSS_MCLK1_CLK] = &mmss_camss_mclk1_clk.clkr, + [MMSS_CAMSS_MCLK2_CLK] = &mmss_camss_mclk2_clk.clkr, + [MMSS_CAMSS_MCLK3_CLK] = &mmss_camss_mclk3_clk.clkr, + [MMSS_CAMSS_MICRO_AHB_CLK] = &mmss_camss_micro_ahb_clk.clkr, + [MMSS_CAMSS_TOP_AHB_CLK] = &mmss_camss_top_ahb_clk.clkr, + [MMSS_CAMSS_VFE0_AHB_CLK] = &mmss_camss_vfe0_ahb_clk.clkr, + [MMSS_CAMSS_VFE0_CLK] = &mmss_camss_vfe0_clk.clkr, + [MMSS_CAMSS_VFE0_STREAM_CLK] = &mmss_camss_vfe0_stream_clk.clkr, + [MMSS_CAMSS_VFE1_AHB_CLK] = &mmss_camss_vfe1_ahb_clk.clkr, + [MMSS_CAMSS_VFE1_CLK] = &mmss_camss_vfe1_clk.clkr, + [MMSS_CAMSS_VFE1_STREAM_CLK] = &mmss_camss_vfe1_stream_clk.clkr, + [MMSS_CAMSS_VFE_VBIF_AHB_CLK] = &mmss_camss_vfe_vbif_ahb_clk.clkr, + [MMSS_CAMSS_VFE_VBIF_AXI_CLK] = &mmss_camss_vfe_vbif_axi_clk.clkr, + [MMSS_CSIPHY_AHB2CRIF_CLK] = &mmss_csiphy_ahb2crif_clk.clkr, + [MMSS_MDSS_AHB_CLK] = &mmss_mdss_ahb_clk.clkr, + [MMSS_MDSS_AXI_CLK] = &mmss_mdss_axi_clk.clkr, + [MMSS_MDSS_BYTE0_CLK] = &mmss_mdss_byte0_clk.clkr, + [MMSS_MDSS_BYTE0_INTF_CLK] = &mmss_mdss_byte0_intf_clk.clkr, + [MMSS_MDSS_BYTE0_INTF_DIV_CLK] = &mmss_mdss_byte0_intf_div_clk.clkr, + [MMSS_MDSS_BYTE1_CLK] = &mmss_mdss_byte1_clk.clkr, + [MMSS_MDSS_BYTE1_INTF_CLK] = &mmss_mdss_byte1_intf_clk.clkr, + [MMSS_MDSS_DP_AUX_CLK] = &mmss_mdss_dp_aux_clk.clkr, + [MMSS_MDSS_DP_CRYPTO_CLK] = &mmss_mdss_dp_crypto_clk.clkr, + [MMSS_MDSS_DP_GTC_CLK] = &mmss_mdss_dp_gtc_clk.clkr, + [MMSS_MDSS_DP_LINK_CLK] = &mmss_mdss_dp_link_clk.clkr, + [MMSS_MDSS_DP_LINK_INTF_CLK] = &mmss_mdss_dp_link_intf_clk.clkr, + [MMSS_MDSS_DP_PIXEL_CLK] = &mmss_mdss_dp_pixel_clk.clkr, + [MMSS_MDSS_ESC0_CLK] = &mmss_mdss_esc0_clk.clkr, + [MMSS_MDSS_ESC1_CLK] = &mmss_mdss_esc1_clk.clkr, + [MMSS_MDSS_HDMI_DP_AHB_CLK] = &mmss_mdss_hdmi_dp_ahb_clk.clkr, + [MMSS_MDSS_MDP_CLK] = &mmss_mdss_mdp_clk.clkr, + [MMSS_MDSS_PCLK0_CLK] = &mmss_mdss_pclk0_clk.clkr, + [MMSS_MDSS_PCLK1_CLK] = &mmss_mdss_pclk1_clk.clkr, + [MMSS_MDSS_ROT_CLK] = &mmss_mdss_rot_clk.clkr, + [MMSS_MDSS_VSYNC_CLK] = &mmss_mdss_vsync_clk.clkr, + [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, + [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr, + [MMSS_MNOC_AHB_CLK] = &mmss_mnoc_ahb_clk.clkr, + [MMSS_SNOC_DVM_AXI_CLK] = &mmss_snoc_dvm_axi_clk.clkr, + [MMSS_VIDEO_AHB_CLK] = &mmss_video_ahb_clk.clkr, + [MMSS_VIDEO_AXI_CLK] = &mmss_video_axi_clk.clkr, + [MMSS_VIDEO_CORE_CLK] = &mmss_video_core_clk.clkr, + [MMSS_VIDEO_SUBCORE0_CLK] = &mmss_video_subcore0_clk.clkr, + [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, + [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr, + [ROT_CLK_SRC] = &rot_clk_src.clkr, + [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, + [VFE1_CLK_SRC] = &vfe1_clk_src.clkr, + [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr, + [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, +}; + +static const struct qcom_reset_map mmcc_660_resets[] = { + [CAMSS_MICRO_BCR] = { 0x3490 }, +}; + +static const struct regmap_config mmcc_660_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x10004, + .fast_io = true, +}; + +static const struct qcom_cc_desc mmcc_660_desc = { + .config = &mmcc_660_regmap_config, + .clks = mmcc_660_clocks, + .num_clks = ARRAY_SIZE(mmcc_660_clocks), + .hwclks = mmcc_sdm660_hws, + .num_hwclks = ARRAY_SIZE(mmcc_sdm660_hws), + .resets = mmcc_660_resets, + .num_resets = ARRAY_SIZE(mmcc_660_resets), +}; + +static const struct of_device_id mmcc_660_match_table[] = { + { .compatible = "qcom,mmcc-sdm660" }, + { } +}; +MODULE_DEVICE_TABLE(of, mmcc_660_match_table); + +static int mmcc_660_probe(struct platform_device *pdev) +{ + int ret = 0; + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &mmcc_660_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* PLLs connected on Mx rails of MMSS_CC */ + vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx_mmss"); + if (IS_ERR(vdd_mx.regulator[0])) { + if (!(PTR_ERR(vdd_mx.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_mx_mmss regulator\n"); + return PTR_ERR(vdd_mx.regulator[0]); + } + + vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig_mmss"); + if (IS_ERR(vdd_dig.regulator[0])) { + if (!(PTR_ERR(vdd_dig.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_dig regulator\n"); + return PTR_ERR(vdd_dig.regulator[0]); + } + + /* MMPLL10 connected to the Analog Rail */ + vdda.regulator[0] = devm_regulator_get(&pdev->dev, "vdda"); + if (IS_ERR(vdda.regulator[0])) { + if (!(PTR_ERR(vdda.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdda regulator\n"); + return PTR_ERR(vdda.regulator[0]); + } + + clk_alpha_pll_configure(&mmpll3_pll_out_main, regmap, &mmpll3_config); + clk_alpha_pll_configure(&mmpll4_pll_out_main, regmap, &mmpll4_config); + clk_alpha_pll_configure(&mmpll5_pll_out_main, regmap, &mmpll5_config); + clk_alpha_pll_configure(&mmpll7_pll_out_main, regmap, &mmpll7_config); + clk_alpha_pll_configure(&mmpll8_pll_out_main, regmap, &mmpll8_config); + clk_alpha_pll_configure(&mmpll10_pll_out_main, regmap, &mmpll10_config); + + ret = qcom_cc_really_probe(pdev, &mmcc_660_desc, regmap); + if (ret) { + dev_err(&pdev->dev, "Failed to register MMSS clocks\n"); + return ret; + } + + dev_info(&pdev->dev, "Registered MMSS clocks\n"); + + return ret; +} + +static struct platform_driver mmcc_660_driver = { + .probe = mmcc_660_probe, + .driver = { + .name = "mmcc-sdm660", + .of_match_table = mmcc_660_match_table, + }, +}; + +static int __init mmcc_660_init(void) +{ + return platform_driver_register(&mmcc_660_driver); +} +core_initcall_sync(mmcc_660_init); + +static void __exit mmcc_660_exit(void) +{ + platform_driver_unregister(&mmcc_660_driver); +} +module_exit(mmcc_660_exit); diff --git a/drivers/clk/qcom/vdd-level-660.h b/drivers/clk/qcom/vdd-level-660.h new file mode 100644 index 000000000000..f98a96033ea9 --- /dev/null +++ b/drivers/clk/qcom/vdd-level-660.h @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_660_H +#define __DRIVERS_CLK_QCOM_VDD_LEVEL_660_H + +#include +#include + +#define VDD_DIG_FMAX_MAP1(l1, f1) \ + .vdd_class = &vdd_dig, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + }, \ + .num_rate_max = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \ + .vdd_class = &vdd_dig, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + }, \ + .num_rate_max = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \ + .vdd_class = &vdd_dig, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + [VDD_DIG_##l3] = (f3), \ + }, \ + .num_rate_max = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP4(l1, f1, l2, f2, l3, f3, l4, f4) \ + .vdd_class = &vdd_dig, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + [VDD_DIG_##l3] = (f3), \ + [VDD_DIG_##l4] = (f4), \ + }, \ + .num_rate_max = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP5(l1, f1, l2, f2, l3, f3, l4, f4, l5, f5) \ + .vdd_class = &vdd_dig, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + [VDD_DIG_##l3] = (f3), \ + [VDD_DIG_##l4] = (f4), \ + [VDD_DIG_##l5] = (f5), \ + }, \ + .num_rate_max = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP6(l1, f1, l2, f2, l3, f3, l4, f4, l5, f5, l6, f6) \ + .vdd_class = &vdd_dig, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + [VDD_DIG_##l3] = (f3), \ + [VDD_DIG_##l4] = (f4), \ + [VDD_DIG_##l5] = (f5), \ + [VDD_DIG_##l6] = (f6), \ + }, \ + .num_rate_max = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP7(l1, f1, l2, f2, l3, f3, l4, f4, l5, f5, l6, f6, \ + l7, f7) \ + .vdd_class = &vdd_dig, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + [VDD_DIG_##l3] = (f3), \ + [VDD_DIG_##l4] = (f4), \ + [VDD_DIG_##l5] = (f5), \ + [VDD_DIG_##l6] = (f6), \ + [VDD_DIG_##l7] = (f7), \ + }, \ + .num_rate_max = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP1_AO(l1, f1) \ + .vdd_class = &vdd_dig_ao, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + }, \ + .num_rate_max = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP3_AO(l1, f1, l2, f2, l3, f3) \ + .vdd_class = &vdd_dig_ao, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + [VDD_DIG_##l3] = (f3), \ + }, \ + .num_rate_max = VDD_DIG_NUM + +#define VDD_GPU_PLL_FMAX_MAP1(l1, f1) \ + .vdd_class = &vdd_mx, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + }, \ + .num_rate_max = VDD_DIG_NUM + +#define VDD_MMSS_PLL_DIG_FMAX_MAP1(l1, f1) \ + .vdd_class = &vdd_mx, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + }, \ + .num_rate_max = VDD_DIG_NUM + +#define VDD_MMSS_PLL_DIG_FMAX_MAP2(l1, f1, l2, f2) \ + .vdd_class = &vdd_mx, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + }, \ + .num_rate_max = VDD_DIG_NUM + +enum vdd_dig_levels { + VDD_DIG_NONE, + VDD_DIG_MIN, /* MIN SVS */ + VDD_DIG_LOWER, /* SVS2 */ + VDD_DIG_LOW, /* SVS */ + VDD_DIG_LOW_L1, /* SVSL1 */ + VDD_DIG_NOMINAL, /* NOM */ + VDD_DIG_NOMINAL_L1, /* NOM */ + VDD_DIG_HIGH, /* TURBO */ + VDD_DIG_NUM +}; + +static int vdd_corner[] = { + RPM_REGULATOR_LEVEL_NONE, /* VDD_DIG_NONE */ + RPM_REGULATOR_LEVEL_MIN_SVS, /* VDD_DIG_MIN */ + RPM_REGULATOR_LEVEL_LOW_SVS, /* VDD_DIG_LOWER */ + RPM_REGULATOR_LEVEL_SVS, /* VDD_DIG_LOW */ + RPM_REGULATOR_LEVEL_SVS_PLUS, /* VDD_DIG_LOW_L1 */ + RPM_REGULATOR_LEVEL_NOM, /* VDD_DIG_NOMINAL */ + RPM_REGULATOR_LEVEL_NOM_PLUS, /* VDD_DIG_NOMINAL */ + RPM_REGULATOR_LEVEL_TURBO, /* VDD_DIG_HIGH */ +}; + +#endif diff --git a/drivers/clk/qcom/vdd-level-falcon.h b/drivers/clk/qcom/vdd-level-falcon.h deleted file mode 100644 index 75567dbe2329..000000000000 --- a/drivers/clk/qcom/vdd-level-falcon.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_FALCON_H -#define __DRIVERS_CLK_QCOM_VDD_LEVEL_FALCON_H - -#include -#include - -#define VDD_DIG_FMAX_MAP1(l1, f1) \ - .vdd_class = &vdd_dig, \ - .rate_max = (unsigned long[VDD_DIG_NUM]) { \ - [VDD_DIG_##l1] = (f1), \ - }, \ - .num_rate_max = VDD_DIG_NUM - -#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \ - .vdd_class = &vdd_dig, \ - .rate_max = (unsigned long[VDD_DIG_NUM]) { \ - [VDD_DIG_##l1] = (f1), \ - [VDD_DIG_##l2] = (f2), \ - }, \ - .num_rate_max = VDD_DIG_NUM - -#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \ - .vdd_class = &vdd_dig, \ - .rate_max = (unsigned long[VDD_DIG_NUM]) { \ - [VDD_DIG_##l1] = (f1), \ - [VDD_DIG_##l2] = (f2), \ - [VDD_DIG_##l3] = (f3), \ - }, \ - .num_rate_max = VDD_DIG_NUM - -#define VDD_DIG_FMAX_MAP4(l1, f1, l2, f2, l3, f3, l4, f4) \ - .vdd_class = &vdd_dig, \ - .rate_max = (unsigned long[VDD_DIG_NUM]) { \ - [VDD_DIG_##l1] = (f1), \ - [VDD_DIG_##l2] = (f2), \ - [VDD_DIG_##l3] = (f3), \ - [VDD_DIG_##l4] = (f4), \ - }, \ - .num_rate_max = VDD_DIG_NUM - -#define VDD_DIG_FMAX_MAP5(l1, f1, l2, f2, l3, f3, l4, f4, l5, f5) \ - .vdd_class = &vdd_dig, \ - .rate_max = (unsigned long[VDD_DIG_NUM]) { \ - [VDD_DIG_##l1] = (f1), \ - [VDD_DIG_##l2] = (f2), \ - [VDD_DIG_##l3] = (f3), \ - [VDD_DIG_##l4] = (f4), \ - [VDD_DIG_##l5] = (f5), \ - }, \ - .num_rate_max = VDD_DIG_NUM - -#define VDD_DIG_FMAX_MAP6(l1, f1, l2, f2, l3, f3, l4, f4, l5, f5, l6, f6) \ - .vdd_class = &vdd_dig, \ - .rate_max = (unsigned long[VDD_DIG_NUM]) { \ - [VDD_DIG_##l1] = (f1), \ - [VDD_DIG_##l2] = (f2), \ - [VDD_DIG_##l3] = (f3), \ - [VDD_DIG_##l4] = (f4), \ - [VDD_DIG_##l5] = (f5), \ - [VDD_DIG_##l6] = (f6), \ - }, \ - .num_rate_max = VDD_DIG_NUM - -#define VDD_DIG_FMAX_MAP7(l1, f1, l2, f2, l3, f3, l4, f4, l5, f5, l6, f6, \ - l7, f7) \ - .vdd_class = &vdd_dig, \ - .rate_max = (unsigned long[VDD_DIG_NUM]) { \ - [VDD_DIG_##l1] = (f1), \ - [VDD_DIG_##l2] = (f2), \ - [VDD_DIG_##l3] = (f3), \ - [VDD_DIG_##l4] = (f4), \ - [VDD_DIG_##l5] = (f5), \ - [VDD_DIG_##l6] = (f6), \ - [VDD_DIG_##l7] = (f7), \ - }, \ - .num_rate_max = VDD_DIG_NUM - -#define VDD_DIG_FMAX_MAP1_AO(l1, f1) \ - .vdd_class = &vdd_dig_ao, \ - .rate_max = (unsigned long[VDD_DIG_NUM]) { \ - [VDD_DIG_##l1] = (f1), \ - }, \ - .num_rate_max = VDD_DIG_NUM - -#define VDD_DIG_FMAX_MAP3_AO(l1, f1, l2, f2, l3, f3) \ - .vdd_class = &vdd_dig_ao, \ - .rate_max = (unsigned long[VDD_DIG_NUM]) { \ - [VDD_DIG_##l1] = (f1), \ - [VDD_DIG_##l2] = (f2), \ - [VDD_DIG_##l3] = (f3), \ - }, \ - .num_rate_max = VDD_DIG_NUM - -#define VDD_GPU_PLL_FMAX_MAP1(l1, f1) \ - .vdd_class = &vdd_mx, \ - .rate_max = (unsigned long[VDD_DIG_NUM]) { \ - [VDD_DIG_##l1] = (f1), \ - }, \ - .num_rate_max = VDD_DIG_NUM - -#define VDD_MMSS_PLL_DIG_FMAX_MAP1(l1, f1) \ - .vdd_class = &vdd_mx, \ - .rate_max = (unsigned long[VDD_DIG_NUM]) { \ - [VDD_DIG_##l1] = (f1), \ - }, \ - .num_rate_max = VDD_DIG_NUM - -#define VDD_MMSS_PLL_DIG_FMAX_MAP2(l1, f1, l2, f2) \ - .vdd_class = &vdd_mx, \ - .rate_max = (unsigned long[VDD_DIG_NUM]) { \ - [VDD_DIG_##l1] = (f1), \ - [VDD_DIG_##l2] = (f2), \ - }, \ - .num_rate_max = VDD_DIG_NUM - -enum vdd_dig_levels { - VDD_DIG_NONE, - VDD_DIG_MIN, /* MIN SVS */ - VDD_DIG_LOWER, /* SVS2 */ - VDD_DIG_LOW, /* SVS */ - VDD_DIG_LOW_L1, /* SVSL1 */ - VDD_DIG_NOMINAL, /* NOM */ - VDD_DIG_NOMINAL_L1, /* NOM */ - VDD_DIG_HIGH, /* TURBO */ - VDD_DIG_NUM -}; - -static int vdd_corner[] = { - RPM_REGULATOR_LEVEL_NONE, /* VDD_DIG_NONE */ - RPM_REGULATOR_LEVEL_MIN_SVS, /* VDD_DIG_MIN */ - RPM_REGULATOR_LEVEL_LOW_SVS, /* VDD_DIG_LOWER */ - RPM_REGULATOR_LEVEL_SVS, /* VDD_DIG_LOW */ - RPM_REGULATOR_LEVEL_SVS_PLUS, /* VDD_DIG_LOW_L1 */ - RPM_REGULATOR_LEVEL_NOM, /* VDD_DIG_NOMINAL */ - RPM_REGULATOR_LEVEL_NOM_PLUS, /* VDD_DIG_NOMINAL */ - RPM_REGULATOR_LEVEL_TURBO, /* VDD_DIG_HIGH */ -}; - -#endif diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 11d88df37d31..d45df18a7019 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -372,18 +372,18 @@ config CRYPTO_DEV_QCRYPTO config CRYPTO_DEV_QCOM_MSM_QCE tristate "Qualcomm Crypto Engine (QCE) module" - select CRYPTO_DEV_QCE50 if ARCH_APQ8084 || ARCH_MSM8916 || ARCH_MSM8994 || ARCH_MSM8996 || ARCH_MSM8992 || ARCH_MSMTITANIUM || ARCH_MSM8909 || ARCH_MSM8998 || ARCH_MSMFALCON || ARCH_MSMTRITON + select CRYPTO_DEV_QCE50 if ARCH_APQ8084 || ARCH_MSM8916 || ARCH_MSM8994 || ARCH_MSM8996 || ARCH_MSM8992 || ARCH_MSMTITANIUM || ARCH_MSM8909 || ARCH_MSM8998 || ARCH_SDM660 || ARCH_MSMTRITON default n help This driver supports Qualcomm Crypto Engine in MSM7x30, MSM8660 MSM8x55, MSM8960, MSM9615, MSM8916, MSM8994, MSM8996, FSM9900, - MSMTITANINUM, APQ8084, MSM8998, MSMFALCON and MSMTRITON. + MSMTITANINUM, APQ8084, MSM8998, SDM660 and MSMTRITON. To compile this driver as a module, choose M here: the For MSM7x30 MSM8660 and MSM8x55 the module is called qce For MSM8960, APQ8064 and MSM9615 the module is called qce40 For MSM8974, MSM8916, MSM8994, MSM8996, MSM8992, MSMTITANIUM, - APQ8084, MSM8998, MSMFALCON and MSMTRITON the module is called qce50. + APQ8084, MSM8998, SDM660 and MSMTRITON the module is called qce50. config CRYPTO_DEV_QCEDEV tristate "QCEDEV Interface to CE module" @@ -391,7 +391,7 @@ config CRYPTO_DEV_QCEDEV help This driver supports Qualcomm QCEDEV Crypto in MSM7x30, MSM8660, MSM8960, MSM9615, APQ8064, MSM8974, MSM8916, MSM8994, MSM8996, - APQ8084, MSM8998, MSMFALCON, MSMTRITON. This exposes the + APQ8084, MSM8998, SDM660, MSMTRITON. This exposes the interface to the QCE hardware accelerator via IOCTLs. To compile this driver as a module, choose M here: the diff --git a/drivers/leds/leds-qpnp-flash-v2.c b/drivers/leds/leds-qpnp-flash-v2.c index 674ca6161af9..aa59677c4b6a 100644 --- a/drivers/leds/leds-qpnp-flash-v2.c +++ b/drivers/leds/leds-qpnp-flash-v2.c @@ -1733,7 +1733,7 @@ static int qpnp_flash_led_parse_common_dt(struct qpnp_flash_led *led, led->pdata->thermal_hysteresis = -EINVAL; rc = of_property_read_u32(node, "qcom,thermal-hysteresis", &val); if (!rc) { - if (led->pdata->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) + if (led->pdata->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) val = THERMAL_HYST_TEMP_TO_VAL(val, 20); else val = THERMAL_HYST_TEMP_TO_VAL(val, 15); diff --git a/drivers/leds/leds-qpnp-wled.c b/drivers/leds/leds-qpnp-wled.c index 56750ac8e9e2..718badb16ea1 100644 --- a/drivers/leds/leds-qpnp-wled.c +++ b/drivers/leds/leds-qpnp-wled.c @@ -479,7 +479,7 @@ static int qpnp_wled_swire_avdd_config(struct qpnp_wled *wled) u8 val; if (wled->pmic_rev_id->pmic_subtype != PMI8998_SUBTYPE && - wled->pmic_rev_id->pmic_subtype != PM2FALCON_SUBTYPE) + wled->pmic_rev_id->pmic_subtype != PM660L_SUBTYPE) return 0; if (!wled->disp_type_amoled || wled->avdd_mode_spmi) @@ -1103,11 +1103,11 @@ static bool is_avdd_trim_adjustment_required(struct qpnp_wled *wled) u8 reg = 0; /* - * AVDD trim adjustment is not required for pmi8998/pm2falcon and not + * AVDD trim adjustment is not required for pmi8998/pm660l and not * supported for pmi8994. */ if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE || + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE || wled->pmic_rev_id->pmic_subtype == PMI8994_SUBTYPE) return false; @@ -1133,7 +1133,7 @@ static int qpnp_wled_gm_config(struct qpnp_wled *wled) /* Configure the LOOP COMP GM register */ if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) { + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) { if (wled->loop_auto_gm_en) reg |= QPNP_WLED_VLOOP_COMP_AUTO_GM_EN; @@ -1179,7 +1179,7 @@ static int qpnp_wled_ovp_config(struct qpnp_wled *wled) return 0; if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) ovp_table = qpnp_wled_ovp_thresholds_pmi8998; else ovp_table = qpnp_wled_ovp_thresholds_pmi8994; @@ -1264,10 +1264,10 @@ static int qpnp_wled_avdd_mode_config(struct qpnp_wled *wled) /* * At present, configuring the mode to SPMI/SWIRE for controlling - * AVDD voltage is available only in pmi8998/pm2falcon. + * AVDD voltage is available only in pmi8998/pm660l. */ if (wled->pmic_rev_id->pmic_subtype != PMI8998_SUBTYPE && - wled->pmic_rev_id->pmic_subtype != PM2FALCON_SUBTYPE) + wled->pmic_rev_id->pmic_subtype != PM660L_SUBTYPE) return 0; /* AMOLED_VOUT should be configured for AMOLED */ @@ -1313,7 +1313,7 @@ static int qpnp_wled_ilim_config(struct qpnp_wled *wled) wled->ilim_ma = PMI8994_WLED_ILIM_MIN_MA; if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) { + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) { ilim_table = qpnp_wled_ilim_settings_pmi8998; if (wled->ilim_ma > PMI8998_WLED_ILIM_MAX_MA) wled->ilim_ma = PMI8998_WLED_ILIM_MAX_MA; @@ -1352,7 +1352,7 @@ static int qpnp_wled_vref_config(struct qpnp_wled *wled) u8 reg = 0; if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) vref_setting = vref_setting_pmi8998; else vref_setting = vref_setting_pmi8994; @@ -1420,7 +1420,7 @@ static int qpnp_wled_config(struct qpnp_wled *wled) /* Configure auto PFM mode for LCD mode only */ if ((wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) && !wled->disp_type_amoled) { reg = 0; reg |= wled->lcd_auto_pfm_thresh; @@ -1563,7 +1563,7 @@ static int qpnp_wled_config(struct qpnp_wled *wled) reg = QPNP_WLED_SINK_TEST5_DIG; } else { reg = QPNP_WLED_SINK_TEST5_HYB; - if (wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) + if (wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) reg |= QPNP_WLED_SINK_TEST5_HVG_PULL_STR_BIT; } @@ -1816,7 +1816,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled) if (wled->disp_type_amoled) { if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) wled->loop_ea_gm = QPNP_WLED_LOOP_GM_DFLT_AMOLED_PMI8998; else @@ -1836,7 +1836,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled) } if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) { + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) { wled->loop_auto_gm_en = of_property_read_bool(pdev->dev.of_node, "qcom,loop-auto-gm-en"); @@ -1852,7 +1852,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled) } if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) { + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) { if (wled->pmic_rev_id->rev4 == PMI8998_V2P0_REV4) wled->lcd_auto_pfm_en = false; @@ -1905,7 +1905,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled) } if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) wled->vref_uv = vref_setting_pmi8998.default_uv; else wled->vref_uv = vref_setting_pmi8994.default_uv; @@ -1929,7 +1929,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled) } if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) wled->ovp_mv = 29600; else wled->ovp_mv = 29500; @@ -1943,7 +1943,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled) } if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) { + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) { if (wled->disp_type_amoled) wled->ilim_ma = PMI8998_AMOLED_DFLT_ILIM_MA; else diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 223339ff119d..e1ef353aa1e1 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -46,7 +46,7 @@ obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-20nm.o obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-14nm.o obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-v3.o obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qrbtc-v2.o -obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-v3-falcon.o +obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-v3-660.o obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o obj-$(CONFIG_PHY_BRCMSTB_SATA) += phy-brcmstb-sata.o obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o diff --git a/drivers/phy/phy-qcom-ufs-qmp-v3-660.c b/drivers/phy/phy-qcom-ufs-qmp-v3-660.c new file mode 100644 index 000000000000..a0cb7d0896d1 --- /dev/null +++ b/drivers/phy/phy-qcom-ufs-qmp-v3-660.c @@ -0,0 +1,260 @@ +/* + * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "phy-qcom-ufs-qmp-v3-660.h" + +#define UFS_PHY_NAME "ufs_phy_qmp_v3_660" + +static +int ufs_qcom_phy_qmp_v3_660_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy, + bool is_rate_B) +{ + int err; + int tbl_size_A, tbl_size_B; + struct ufs_qcom_phy_calibration *tbl_A, *tbl_B; + u8 major = ufs_qcom_phy->host_ctrl_rev_major; + u16 minor = ufs_qcom_phy->host_ctrl_rev_minor; + u16 step = ufs_qcom_phy->host_ctrl_rev_step; + + tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B); + tbl_B = phy_cal_table_rate_B; + + if ((major == 0x3) && (minor == 0x001) && (step == 0x001)) { + tbl_A = phy_cal_table_rate_A_3_1_1; + tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_3_1_1); + } else { + dev_err(ufs_qcom_phy->dev, + "%s: Unknown UFS-PHY version (major 0x%x minor 0x%x step 0x%x), no calibration values\n", + __func__, major, minor, step); + err = -ENODEV; + goto out; + } + + err = ufs_qcom_phy_calibrate(ufs_qcom_phy, + tbl_A, tbl_size_A, + tbl_B, tbl_size_B, + is_rate_B); + + if (err) + dev_err(ufs_qcom_phy->dev, + "%s: ufs_qcom_phy_calibrate() failed %d\n", + __func__, err); + +out: + return err; +} + +static int ufs_qcom_phy_qmp_v3_660_init(struct phy *generic_phy) +{ + struct ufs_qcom_phy_qmp_v3_660 *phy = phy_get_drvdata(generic_phy); + struct ufs_qcom_phy *phy_common = &phy->common_cfg; + int err; + + err = ufs_qcom_phy_init_clks(generic_phy, phy_common); + if (err) { + dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_clks() failed %d\n", + __func__, err); + goto out; + } + + err = ufs_qcom_phy_init_vregulators(generic_phy, phy_common); + if (err) { + dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_vregulators() failed %d\n", + __func__, err); + goto out; + } + +out: + return err; +} + +static +void ufs_qcom_phy_qmp_v3_660_power_control(struct ufs_qcom_phy *phy, + bool power_ctrl) +{ + if (!power_ctrl) { + /* apply analog power collapse */ + writel_relaxed(0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL); + /* + * Make sure that PHY knows its analog rail is going to be + * powered OFF. + */ + mb(); + } else { + /* bring PHY out of analog power collapse */ + writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL); + + /* + * Before any transactions involving PHY, ensure PHY knows + * that it's analog rail is powered ON. + */ + mb(); + } +} + +static inline +void ufs_qcom_phy_qmp_v3_660_set_tx_lane_enable(struct ufs_qcom_phy *phy, + u32 val) +{ + /* + * v3 PHY does not have TX_LANE_ENABLE register. + * Implement this function so as not to propagate error to caller. + */ +} + +static +void ufs_qcom_phy_qmp_v3_660_ctrl_rx_linecfg(struct ufs_qcom_phy *phy, + bool ctrl) +{ + u32 temp; + + temp = readl_relaxed(phy->mmio + UFS_PHY_LINECFG_DISABLE); + + if (ctrl) /* enable RX LineCfg */ + temp &= ~UFS_PHY_RX_LINECFG_DISABLE_BIT; + else /* disable RX LineCfg */ + temp |= UFS_PHY_RX_LINECFG_DISABLE_BIT; + + writel_relaxed(temp, phy->mmio + UFS_PHY_LINECFG_DISABLE); + /* Make sure that RX LineCfg config applied before we return */ + mb(); +} + +static inline void ufs_qcom_phy_qmp_v3_660_start_serdes( + struct ufs_qcom_phy *phy) +{ + u32 tmp; + + tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START); + tmp &= ~MASK_SERDES_START; + tmp |= (1 << OFFSET_SERDES_START); + writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START); + /* Ensure register value is committed */ + mb(); +} + +static int ufs_qcom_phy_qmp_v3_660_is_pcs_ready( + struct ufs_qcom_phy *phy_common) +{ + int err = 0; + u32 val; + + err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS, + val, (val & MASK_PCS_READY), 10, 1000000); + if (err) + dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n", + __func__, err); + return err; +} + +static void ufs_qcom_phy_qmp_v3_660_dbg_register_dump( + struct ufs_qcom_phy *phy) +{ + ufs_qcom_phy_dump_regs(phy, COM_BASE, COM_SIZE, + "PHY QSERDES COM Registers "); + ufs_qcom_phy_dump_regs(phy, PHY_BASE, PHY_SIZE, + "PHY Registers "); + ufs_qcom_phy_dump_regs(phy, RX_BASE, RX_SIZE, + "PHY RX0 Registers "); + ufs_qcom_phy_dump_regs(phy, TX_BASE, TX_SIZE, + "PHY TX0 Registers "); +} + +struct phy_ops ufs_qcom_phy_qmp_v3_660_phy_ops = { + .init = ufs_qcom_phy_qmp_v3_660_init, + .exit = ufs_qcom_phy_exit, + .power_on = ufs_qcom_phy_power_on, + .power_off = ufs_qcom_phy_power_off, + .owner = THIS_MODULE, +}; + +struct ufs_qcom_phy_specific_ops phy_v3_660_ops = { + .calibrate_phy = ufs_qcom_phy_qmp_v3_660_phy_calibrate, + .start_serdes = ufs_qcom_phy_qmp_v3_660_start_serdes, + .is_physical_coding_sublayer_ready = + ufs_qcom_phy_qmp_v3_660_is_pcs_ready, + .set_tx_lane_enable = ufs_qcom_phy_qmp_v3_660_set_tx_lane_enable, + .ctrl_rx_linecfg = ufs_qcom_phy_qmp_v3_660_ctrl_rx_linecfg, + .power_control = ufs_qcom_phy_qmp_v3_660_power_control, + .dbg_register_dump = ufs_qcom_phy_qmp_v3_660_dbg_register_dump, +}; + +static int ufs_qcom_phy_qmp_v3_660_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct phy *generic_phy; + struct ufs_qcom_phy_qmp_v3_660 *phy; + int err = 0; + + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); + if (!phy) { + err = -ENOMEM; + goto out; + } + + generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg, + &ufs_qcom_phy_qmp_v3_660_phy_ops, + &phy_v3_660_ops); + + if (!generic_phy) { + dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n", + __func__); + err = -EIO; + goto out; + } + + phy_set_drvdata(generic_phy, phy); + + strlcpy(phy->common_cfg.name, UFS_PHY_NAME, + sizeof(phy->common_cfg.name)); + +out: + return err; +} + +static int ufs_qcom_phy_qmp_v3_660_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct phy *generic_phy = to_phy(dev); + struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy); + int err = 0; + + err = ufs_qcom_phy_remove(generic_phy, ufs_qcom_phy); + if (err) + dev_err(dev, "%s: ufs_qcom_phy_remove failed = %d\n", + __func__, err); + + return err; +} + +static const struct of_device_id ufs_qcom_phy_qmp_v3_660_of_match[] = { + {.compatible = "qcom,ufs-phy-qmp-v3-660"}, + {}, +}; +MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_v3_660_of_match); + +static struct platform_driver ufs_qcom_phy_qmp_v3_660_driver = { + .probe = ufs_qcom_phy_qmp_v3_660_probe, + .remove = ufs_qcom_phy_qmp_v3_660_remove, + .driver = { + .of_match_table = ufs_qcom_phy_qmp_v3_660_of_match, + .name = "ufs_qcom_phy_qmp_v3_660", + .owner = THIS_MODULE, + }, +}; + +module_platform_driver(ufs_qcom_phy_qmp_v3_660_driver); + +MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP v3 660"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/phy/phy-qcom-ufs-qmp-v3-660.h b/drivers/phy/phy-qcom-ufs-qmp-v3-660.h new file mode 100644 index 000000000000..8d0183d87e20 --- /dev/null +++ b/drivers/phy/phy-qcom-ufs-qmp-v3-660.h @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef UFS_QCOM_PHY_QMP_V3_660_H_ +#define UFS_QCOM_PHY_QMP_V3_660_H_ + +#include "phy-qcom-ufs-i.h" + +/* QCOM UFS PHY control registers */ +#define COM_BASE 0x000 +#define COM_OFF(x) (COM_BASE + x) +#define COM_SIZE 0x1C0 + +#define TX_BASE 0x400 +#define TX_OFF(x) (TX_BASE + x) +#define TX_SIZE 0x128 + +#define RX_BASE 0x600 +#define RX_OFF(x) (RX_BASE + x) +#define RX_SIZE 0x1FC + +#define PHY_BASE 0xC00 +#define PHY_OFF(x) (PHY_BASE + x) +#define PHY_SIZE 0x1B4 + +/* UFS PHY QSERDES COM registers */ +#define QSERDES_COM_ATB_SEL1 COM_OFF(0x00) +#define QSERDES_COM_ATB_SEL2 COM_OFF(0x04) +#define QSERDES_COM_FREQ_UPDATE COM_OFF(0x08) +#define QSERDES_COM_BG_TIMER COM_OFF(0x0C) +#define QSERDES_COM_SSC_EN_CENTER COM_OFF(0x10) +#define QSERDES_COM_SSC_ADJ_PER1 COM_OFF(0x14) +#define QSERDES_COM_SSC_ADJ_PER2 COM_OFF(0x18) +#define QSERDES_COM_SSC_PER1 COM_OFF(0x1C) +#define QSERDES_COM_SSC_PER2 COM_OFF(0x20) +#define QSERDES_COM_SSC_STEP_SIZE1 COM_OFF(0x24) +#define QSERDES_COM_SSC_STEP_SIZE2 COM_OFF(0x28) +#define QSERDES_COM_POST_DIV COM_OFF(0x2C) +#define QSERDES_COM_POST_DIV_MUX COM_OFF(0x30) +#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN COM_OFF(0x34) +#define QSERDES_COM_CLK_ENABLE1 COM_OFF(0x38) +#define QSERDES_COM_SYS_CLK_CTRL COM_OFF(0x3C) +#define QSERDES_COM_SYSCLK_BUF_ENABLE COM_OFF(0x40) +#define QSERDES_COM_PLL_EN COM_OFF(0x44) +#define QSERDES_COM_PLL_IVCO COM_OFF(0x48) +#define QSERDES_COM_LOCK_CMP1_MODE0 COM_OFF(0X4C) +#define QSERDES_COM_LOCK_CMP2_MODE0 COM_OFF(0X50) +#define QSERDES_COM_LOCK_CMP3_MODE0 COM_OFF(0X54) +#define QSERDES_COM_LOCK_CMP1_MODE1 COM_OFF(0X58) +#define QSERDES_COM_LOCK_CMP2_MODE1 COM_OFF(0X5C) +#define QSERDES_COM_LOCK_CMP3_MODE1 COM_OFF(0X60) +#define QSERDES_COM_CMD_RSVD0 COM_OFF(0x64) +#define QSERDES_COM_EP_CLOCK_DETECT_CTRL COM_OFF(0x68) +#define QSERDES_COM_SYSCLK_DET_COMP_STATUS COM_OFF(0x6C) +#define QSERDES_COM_BG_TRIM COM_OFF(0x70) +#define QSERDES_COM_CLK_EP_DIV COM_OFF(0x74) +#define QSERDES_COM_CP_CTRL_MODE0 COM_OFF(0x78) +#define QSERDES_COM_CP_CTRL_MODE1 COM_OFF(0x7C) +#define QSERDES_COM_CMN_RSVD1 COM_OFF(0x80) +#define QSERDES_COM_PLL_RCTRL_MODE0 COM_OFF(0x84) +#define QSERDES_COM_PLL_RCTRL_MODE1 COM_OFF(0x88) +#define QSERDES_COM_CMN_RSVD2 COM_OFF(0x8C) +#define QSERDES_COM_PLL_CCTRL_MODE0 COM_OFF(0x90) +#define QSERDES_COM_PLL_CCTRL_MODE1 COM_OFF(0x94) +#define QSERDES_COM_CMN_RSVD3 COM_OFF(0x98) +#define QSERDES_COM_PLL_CNTRL COM_OFF(0x9C) +#define QSERDES_COM_PHASE_SEL_CTRL COM_OFF(0xA0) +#define QSERDES_COM_PHASE_SEL_DC COM_OFF(0xA4) +#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM COM_OFF(0xA8) +#define QSERDES_COM_SYSCLK_EN_SEL COM_OFF(0xAC) +#define QSERDES_COM_CML_SYSCLK_SEL COM_OFF(0xB0) +#define QSERDES_COM_RESETSM_CNTRL COM_OFF(0xB4) +#define QSERDES_COM_RESETSM_CNTRL2 COM_OFF(0xB8) +#define QSERDES_COM_RESTRIM_CTRL COM_OFF(0xBC) +#define QSERDES_COM_RESTRIM_CTRL2 COM_OFF(0xC0) +#define QSERDES_COM_LOCK_CMP_EN COM_OFF(0xC8) +#define QSERDES_COM_LOCK_CMP_CFG COM_OFF(0xCC) +#define QSERDES_COM_DEC_START_MODE0 COM_OFF(0xD0) +#define QSERDES_COM_DEC_START_MODE1 COM_OFF(0xD4) +#define QSERDES_COM_VCOCAL_DEADMAN_CTRL COM_OFF(0xD8) +#define QSERDES_COM_DIV_FRAC_START1_MODE0 COM_OFF(0xDC) +#define QSERDES_COM_DIV_FRAC_START2_MODE0 COM_OFF(0xE0) +#define QSERDES_COM_DIV_FRAC_START3_MODE0 COM_OFF(0xE4) +#define QSERDES_COM_DIV_FRAC_START1_MODE1 COM_OFF(0xE8) +#define QSERDES_COM_DIV_FRAC_START2_MODE1 COM_OFF(0xEC) +#define QSERDES_COM_DIV_FRAC_START3_MODE1 COM_OFF(0xF0) +#define QSERDES_COM_VCO_TUNE_MINVAL1 COM_OFF(0xF4) +#define QSERDES_COM_VCO_TUNE_MINVAL2 COM_OFF(0xF8) +#define QSERDES_COM_CMN_RSVD4 COM_OFF(0xFC) +#define QSERDES_COM_INTEGLOOP_INITVAL COM_OFF(0x100) +#define QSERDES_COM_INTEGLOOP_EN COM_OFF(0x104) +#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 COM_OFF(0x108) +#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 COM_OFF(0x10C) +#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 COM_OFF(0x110) +#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 COM_OFF(0x114) +#define QSERDES_COM_VCO_TUNE_MAXVAL1 COM_OFF(0x118) +#define QSERDES_COM_VCO_TUNE_MAXVAL2 COM_OFF(0x11C) +#define QSERDES_COM_RES_TRIM_CONTROL2 COM_OFF(0x120) +#define QSERDES_COM_VCO_TUNE_CTRL COM_OFF(0x124) +#define QSERDES_COM_VCO_TUNE_MAP COM_OFF(0x128) +#define QSERDES_COM_VCO_TUNE1_MODE0 COM_OFF(0x12C) +#define QSERDES_COM_VCO_TUNE2_MODE0 COM_OFF(0x130) +#define QSERDES_COM_VCO_TUNE1_MODE1 COM_OFF(0x134) +#define QSERDES_COM_VCO_TUNE2_MODE1 COM_OFF(0x138) +#define QSERDES_COM_VCO_TUNE_INITVAL1 COM_OFF(0x13C) +#define QSERDES_COM_VCO_TUNE_INITVAL2 COM_OFF(0x140) +#define QSERDES_COM_VCO_TUNE_TIMER1 COM_OFF(0x144) +#define QSERDES_COM_VCO_TUNE_TIMER2 COM_OFF(0x148) +#define QSERDES_COM_SAR COM_OFF(0x14C) +#define QSERDES_COM_SAR_CLK COM_OFF(0x150) +#define QSERDES_COM_SAR_CODE_OUT_STATUS COM_OFF(0x154) +#define QSERDES_COM_SAR_CODE_READY_STATUS COM_OFF(0x158) +#define QSERDES_COM_CMN_STATUS COM_OFF(0x15C) +#define QSERDES_COM_RESET_SM_STATUS COM_OFF(0x160) +#define QSERDES_COM_RESTRIM_CODE_STATUS COM_OFF(0x164) +#define QSERDES_COM_PLLCAL_CODE1_STATUS COM_OFF(0x168) +#define QSERDES_COM_PLLCAL_CODE2_STATUS COM_OFF(0x16C) +#define QSERDES_COM_BG_CTRL COM_OFF(0x170) +#define QSERDES_COM_CLK_SELECT COM_OFF(0x174) +#define QSERDES_COM_HSCLK_SEL COM_OFF(0x178) +#define QSERDES_COM_INTEGLOOP_BINCODE_STATUS COM_OFF(0x17C) +#define QSERDES_COM_PLL_ANALOG COM_OFF(0x180) +#define QSERDES_COM_CORECLK_DIV COM_OFF(0x184) +#define QSERDES_COM_SW_RESET COM_OFF(0x188) +#define QSERDES_COM_CORE_CLK_EN COM_OFF(0x18C) +#define QSERDES_COM_C_READY_STATUS COM_OFF(0x190) +#define QSERDES_COM_CMN_CONFIG COM_OFF(0x194) +#define QSERDES_COM_CMN_RATE_OVERRIDE COM_OFF(0x198) +#define QSERDES_COM_SVS_MODE_CLK_SEL COM_OFF(0x19C) +#define QSERDES_COM_DEBUG_BUS0 COM_OFF(0x1A0) +#define QSERDES_COM_DEBUG_BUS1 COM_OFF(0x1A4) +#define QSERDES_COM_DEBUG_BUS2 COM_OFF(0x1A8) +#define QSERDES_COM_DEBUG_BUS3 COM_OFF(0x1AC) +#define QSERDES_COM_DEBUG_BUS_SEL COM_OFF(0x1B0) +#define QSERDES_COM_CMN_MISC1 COM_OFF(0x1B4) +#define QSERDES_COM_CORECLK_DIV_MODE1 COM_OFF(0x1BC) +#define QSERDES_COM_CMN_RSVD5 COM_OFF(0x1C0) + +/* UFS PHY registers */ +#define UFS_PHY_PHY_START PHY_OFF(0x00) +#define UFS_PHY_POWER_DOWN_CONTROL PHY_OFF(0x04) +#define UFS_PHY_TX_LARGE_AMP_DRV_LVL PHY_OFF(0x34) +#define UFS_PHY_TX_SMALL_AMP_DRV_LVL PHY_OFF(0x3C) +#define UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP PHY_OFF(0xCC) +#define UFS_PHY_LINECFG_DISABLE PHY_OFF(0x138) +#define UFS_PHY_RX_SYM_RESYNC_CTRL PHY_OFF(0x13C) +#define UFS_PHY_RX_SIGDET_CTRL2 PHY_OFF(0x148) +#define UFS_PHY_RX_PWM_GEAR_BAND PHY_OFF(0x154) +#define UFS_PHY_PCS_READY_STATUS PHY_OFF(0x168) + +/* UFS PHY TX registers */ +#define QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN TX_OFF(0x68) +#define QSERDES_TX_LANE_MODE TX_OFF(0x94) + +/* UFS PHY RX registers */ +#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF RX_OFF(0x30) +#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER RX_OFF(0x34) +#define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH RX_OFF(0x38) +#define QSERDES_RX_UCDR_SVS_SO_GAIN RX_OFF(0x3C) +#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN RX_OFF(0x40) +#define QSERDES_RX_UCDR_SO_SATURATION_ENABLE RX_OFF(0x48) +#define QSERDES_RX_RX_TERM_BW RX_OFF(0x90) +#define QSERDES_RX_RX_EQ_GAIN1_LSB RX_OFF(0xC4) +#define QSERDES_RX_RX_EQ_GAIN1_MSB RX_OFF(0xC8) +#define QSERDES_RX_RX_EQ_GAIN2_LSB RX_OFF(0xCC) +#define QSERDES_RX_RX_EQ_GAIN2_MSB RX_OFF(0xD0) +#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 RX_OFF(0xD8) +#define QSERDES_RX_SIGDET_CNTRL RX_OFF(0x114) +#define QSERDES_RX_SIGDET_LVL RX_OFF(0x118) +#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL RX_OFF(0x11C) +#define QSERDES_RX_RX_INTERFACE_MODE RX_OFF(0x12C) + + +#define UFS_PHY_RX_LINECFG_DISABLE_BIT BIT(1) + +/* + * This structure represents the v3 660 specific phy. + * common_cfg MUST remain the first field in this structure + * in case extra fields are added. This way, when calling + * get_ufs_qcom_phy() of generic phy, we can extract the + * common phy structure (struct ufs_qcom_phy) out of it + * regardless of the relevant specific phy. + */ +struct ufs_qcom_phy_qmp_v3_660 { + struct ufs_qcom_phy common_cfg; +}; + +static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_3_1_1[] = { + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG, 0x0e), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0x14), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CLK_SELECT, 0x30), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x02), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TIMER, 0x0a), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV, 0x0a), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_CTRL, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x20), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_EN, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_CFG, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x04), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x0b), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x0b), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN, 0x45), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE, 0x06), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_LVL, 0x24), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL, 0x0F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_INTERFACE_MODE, 0x40), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_BW, 0x5B), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D), + + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TRIM, 0x0F), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_PWM_GEAR_BAND, 0x15), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SO_SATURATION_ENABLE, 0x4B), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL1, 0xFF), + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6c), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0A), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYM_RESYNC_CTRL, 0x03), +}; + +static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = { + UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x44), +}; + +#endif diff --git a/drivers/phy/phy-qcom-ufs-qmp-v3-falcon.c b/drivers/phy/phy-qcom-ufs-qmp-v3-falcon.c deleted file mode 100644 index e88c00e01e0b..000000000000 --- a/drivers/phy/phy-qcom-ufs-qmp-v3-falcon.c +++ /dev/null @@ -1,260 +0,0 @@ -/* - * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include "phy-qcom-ufs-qmp-v3-falcon.h" - -#define UFS_PHY_NAME "ufs_phy_qmp_v3_falcon" - -static -int ufs_qcom_phy_qmp_v3_falcon_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy, - bool is_rate_B) -{ - int err; - int tbl_size_A, tbl_size_B; - struct ufs_qcom_phy_calibration *tbl_A, *tbl_B; - u8 major = ufs_qcom_phy->host_ctrl_rev_major; - u16 minor = ufs_qcom_phy->host_ctrl_rev_minor; - u16 step = ufs_qcom_phy->host_ctrl_rev_step; - - tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B); - tbl_B = phy_cal_table_rate_B; - - if ((major == 0x3) && (minor == 0x001) && (step == 0x001)) { - tbl_A = phy_cal_table_rate_A_3_1_1; - tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_3_1_1); - } else { - dev_err(ufs_qcom_phy->dev, - "%s: Unknown UFS-PHY version (major 0x%x minor 0x%x step 0x%x), no calibration values\n", - __func__, major, minor, step); - err = -ENODEV; - goto out; - } - - err = ufs_qcom_phy_calibrate(ufs_qcom_phy, - tbl_A, tbl_size_A, - tbl_B, tbl_size_B, - is_rate_B); - - if (err) - dev_err(ufs_qcom_phy->dev, - "%s: ufs_qcom_phy_calibrate() failed %d\n", - __func__, err); - -out: - return err; -} - -static int ufs_qcom_phy_qmp_v3_falcon_init(struct phy *generic_phy) -{ - struct ufs_qcom_phy_qmp_v3_falcon *phy = phy_get_drvdata(generic_phy); - struct ufs_qcom_phy *phy_common = &phy->common_cfg; - int err; - - err = ufs_qcom_phy_init_clks(generic_phy, phy_common); - if (err) { - dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_clks() failed %d\n", - __func__, err); - goto out; - } - - err = ufs_qcom_phy_init_vregulators(generic_phy, phy_common); - if (err) { - dev_err(phy_common->dev, "%s: ufs_qcom_phy_init_vregulators() failed %d\n", - __func__, err); - goto out; - } - -out: - return err; -} - -static -void ufs_qcom_phy_qmp_v3_falcon_power_control(struct ufs_qcom_phy *phy, - bool power_ctrl) -{ - if (!power_ctrl) { - /* apply analog power collapse */ - writel_relaxed(0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL); - /* - * Make sure that PHY knows its analog rail is going to be - * powered OFF. - */ - mb(); - } else { - /* bring PHY out of analog power collapse */ - writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL); - - /* - * Before any transactions involving PHY, ensure PHY knows - * that it's analog rail is powered ON. - */ - mb(); - } -} - -static inline -void ufs_qcom_phy_qmp_v3_falcon_set_tx_lane_enable(struct ufs_qcom_phy *phy, - u32 val) -{ - /* - * v3 PHY does not have TX_LANE_ENABLE register. - * Implement this function so as not to propagate error to caller. - */ -} - -static -void ufs_qcom_phy_qmp_v3_falcon_ctrl_rx_linecfg(struct ufs_qcom_phy *phy, - bool ctrl) -{ - u32 temp; - - temp = readl_relaxed(phy->mmio + UFS_PHY_LINECFG_DISABLE); - - if (ctrl) /* enable RX LineCfg */ - temp &= ~UFS_PHY_RX_LINECFG_DISABLE_BIT; - else /* disable RX LineCfg */ - temp |= UFS_PHY_RX_LINECFG_DISABLE_BIT; - - writel_relaxed(temp, phy->mmio + UFS_PHY_LINECFG_DISABLE); - /* Make sure that RX LineCfg config applied before we return */ - mb(); -} - -static inline void ufs_qcom_phy_qmp_v3_falcon_start_serdes( - struct ufs_qcom_phy *phy) -{ - u32 tmp; - - tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START); - tmp &= ~MASK_SERDES_START; - tmp |= (1 << OFFSET_SERDES_START); - writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START); - /* Ensure register value is committed */ - mb(); -} - -static int ufs_qcom_phy_qmp_v3_falcon_is_pcs_ready( - struct ufs_qcom_phy *phy_common) -{ - int err = 0; - u32 val; - - err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS, - val, (val & MASK_PCS_READY), 10, 1000000); - if (err) - dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n", - __func__, err); - return err; -} - -static void ufs_qcom_phy_qmp_v3_falcon_dbg_register_dump( - struct ufs_qcom_phy *phy) -{ - ufs_qcom_phy_dump_regs(phy, COM_BASE, COM_SIZE, - "PHY QSERDES COM Registers "); - ufs_qcom_phy_dump_regs(phy, PHY_BASE, PHY_SIZE, - "PHY Registers "); - ufs_qcom_phy_dump_regs(phy, RX_BASE, RX_SIZE, - "PHY RX0 Registers "); - ufs_qcom_phy_dump_regs(phy, TX_BASE, TX_SIZE, - "PHY TX0 Registers "); -} - -struct phy_ops ufs_qcom_phy_qmp_v3_falcon_phy_ops = { - .init = ufs_qcom_phy_qmp_v3_falcon_init, - .exit = ufs_qcom_phy_exit, - .power_on = ufs_qcom_phy_power_on, - .power_off = ufs_qcom_phy_power_off, - .owner = THIS_MODULE, -}; - -struct ufs_qcom_phy_specific_ops phy_v3_falcon_ops = { - .calibrate_phy = ufs_qcom_phy_qmp_v3_falcon_phy_calibrate, - .start_serdes = ufs_qcom_phy_qmp_v3_falcon_start_serdes, - .is_physical_coding_sublayer_ready = - ufs_qcom_phy_qmp_v3_falcon_is_pcs_ready, - .set_tx_lane_enable = ufs_qcom_phy_qmp_v3_falcon_set_tx_lane_enable, - .ctrl_rx_linecfg = ufs_qcom_phy_qmp_v3_falcon_ctrl_rx_linecfg, - .power_control = ufs_qcom_phy_qmp_v3_falcon_power_control, - .dbg_register_dump = ufs_qcom_phy_qmp_v3_falcon_dbg_register_dump, -}; - -static int ufs_qcom_phy_qmp_v3_falcon_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct phy *generic_phy; - struct ufs_qcom_phy_qmp_v3_falcon *phy; - int err = 0; - - phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); - if (!phy) { - err = -ENOMEM; - goto out; - } - - generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg, - &ufs_qcom_phy_qmp_v3_falcon_phy_ops, - &phy_v3_falcon_ops); - - if (!generic_phy) { - dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n", - __func__); - err = -EIO; - goto out; - } - - phy_set_drvdata(generic_phy, phy); - - strlcpy(phy->common_cfg.name, UFS_PHY_NAME, - sizeof(phy->common_cfg.name)); - -out: - return err; -} - -static int ufs_qcom_phy_qmp_v3_falcon_remove(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct phy *generic_phy = to_phy(dev); - struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy); - int err = 0; - - err = ufs_qcom_phy_remove(generic_phy, ufs_qcom_phy); - if (err) - dev_err(dev, "%s: ufs_qcom_phy_remove failed = %d\n", - __func__, err); - - return err; -} - -static const struct of_device_id ufs_qcom_phy_qmp_v3_falcon_of_match[] = { - {.compatible = "qcom,ufs-phy-qmp-v3-falcon"}, - {}, -}; -MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_v3_falcon_of_match); - -static struct platform_driver ufs_qcom_phy_qmp_v3_falcon_driver = { - .probe = ufs_qcom_phy_qmp_v3_falcon_probe, - .remove = ufs_qcom_phy_qmp_v3_falcon_remove, - .driver = { - .of_match_table = ufs_qcom_phy_qmp_v3_falcon_of_match, - .name = "ufs_qcom_phy_qmp_v3_falcon", - .owner = THIS_MODULE, - }, -}; - -module_platform_driver(ufs_qcom_phy_qmp_v3_falcon_driver); - -MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP v3 falcon"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/phy/phy-qcom-ufs-qmp-v3-falcon.h b/drivers/phy/phy-qcom-ufs-qmp-v3-falcon.h deleted file mode 100644 index e64601cc6b22..000000000000 --- a/drivers/phy/phy-qcom-ufs-qmp-v3-falcon.h +++ /dev/null @@ -1,283 +0,0 @@ -/* - * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef UFS_QCOM_PHY_QMP_V3_FALCON_H_ -#define UFS_QCOM_PHY_QMP_V3_FALCON_H_ - -#include "phy-qcom-ufs-i.h" - -/* QCOM UFS PHY control registers */ -#define COM_BASE 0x000 -#define COM_OFF(x) (COM_BASE + x) -#define COM_SIZE 0x1C0 - -#define TX_BASE 0x400 -#define TX_OFF(x) (TX_BASE + x) -#define TX_SIZE 0x128 - -#define RX_BASE 0x600 -#define RX_OFF(x) (RX_BASE + x) -#define RX_SIZE 0x1FC - -#define PHY_BASE 0xC00 -#define PHY_OFF(x) (PHY_BASE + x) -#define PHY_SIZE 0x1B4 - -/* UFS PHY QSERDES COM registers */ -#define QSERDES_COM_ATB_SEL1 COM_OFF(0x00) -#define QSERDES_COM_ATB_SEL2 COM_OFF(0x04) -#define QSERDES_COM_FREQ_UPDATE COM_OFF(0x08) -#define QSERDES_COM_BG_TIMER COM_OFF(0x0C) -#define QSERDES_COM_SSC_EN_CENTER COM_OFF(0x10) -#define QSERDES_COM_SSC_ADJ_PER1 COM_OFF(0x14) -#define QSERDES_COM_SSC_ADJ_PER2 COM_OFF(0x18) -#define QSERDES_COM_SSC_PER1 COM_OFF(0x1C) -#define QSERDES_COM_SSC_PER2 COM_OFF(0x20) -#define QSERDES_COM_SSC_STEP_SIZE1 COM_OFF(0x24) -#define QSERDES_COM_SSC_STEP_SIZE2 COM_OFF(0x28) -#define QSERDES_COM_POST_DIV COM_OFF(0x2C) -#define QSERDES_COM_POST_DIV_MUX COM_OFF(0x30) -#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN COM_OFF(0x34) -#define QSERDES_COM_CLK_ENABLE1 COM_OFF(0x38) -#define QSERDES_COM_SYS_CLK_CTRL COM_OFF(0x3C) -#define QSERDES_COM_SYSCLK_BUF_ENABLE COM_OFF(0x40) -#define QSERDES_COM_PLL_EN COM_OFF(0x44) -#define QSERDES_COM_PLL_IVCO COM_OFF(0x48) -#define QSERDES_COM_LOCK_CMP1_MODE0 COM_OFF(0X4C) -#define QSERDES_COM_LOCK_CMP2_MODE0 COM_OFF(0X50) -#define QSERDES_COM_LOCK_CMP3_MODE0 COM_OFF(0X54) -#define QSERDES_COM_LOCK_CMP1_MODE1 COM_OFF(0X58) -#define QSERDES_COM_LOCK_CMP2_MODE1 COM_OFF(0X5C) -#define QSERDES_COM_LOCK_CMP3_MODE1 COM_OFF(0X60) -#define QSERDES_COM_CMD_RSVD0 COM_OFF(0x64) -#define QSERDES_COM_EP_CLOCK_DETECT_CTRL COM_OFF(0x68) -#define QSERDES_COM_SYSCLK_DET_COMP_STATUS COM_OFF(0x6C) -#define QSERDES_COM_BG_TRIM COM_OFF(0x70) -#define QSERDES_COM_CLK_EP_DIV COM_OFF(0x74) -#define QSERDES_COM_CP_CTRL_MODE0 COM_OFF(0x78) -#define QSERDES_COM_CP_CTRL_MODE1 COM_OFF(0x7C) -#define QSERDES_COM_CMN_RSVD1 COM_OFF(0x80) -#define QSERDES_COM_PLL_RCTRL_MODE0 COM_OFF(0x84) -#define QSERDES_COM_PLL_RCTRL_MODE1 COM_OFF(0x88) -#define QSERDES_COM_CMN_RSVD2 COM_OFF(0x8C) -#define QSERDES_COM_PLL_CCTRL_MODE0 COM_OFF(0x90) -#define QSERDES_COM_PLL_CCTRL_MODE1 COM_OFF(0x94) -#define QSERDES_COM_CMN_RSVD3 COM_OFF(0x98) -#define QSERDES_COM_PLL_CNTRL COM_OFF(0x9C) -#define QSERDES_COM_PHASE_SEL_CTRL COM_OFF(0xA0) -#define QSERDES_COM_PHASE_SEL_DC COM_OFF(0xA4) -#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM COM_OFF(0xA8) -#define QSERDES_COM_SYSCLK_EN_SEL COM_OFF(0xAC) -#define QSERDES_COM_CML_SYSCLK_SEL COM_OFF(0xB0) -#define QSERDES_COM_RESETSM_CNTRL COM_OFF(0xB4) -#define QSERDES_COM_RESETSM_CNTRL2 COM_OFF(0xB8) -#define QSERDES_COM_RESTRIM_CTRL COM_OFF(0xBC) -#define QSERDES_COM_RESTRIM_CTRL2 COM_OFF(0xC0) -#define QSERDES_COM_LOCK_CMP_EN COM_OFF(0xC8) -#define QSERDES_COM_LOCK_CMP_CFG COM_OFF(0xCC) -#define QSERDES_COM_DEC_START_MODE0 COM_OFF(0xD0) -#define QSERDES_COM_DEC_START_MODE1 COM_OFF(0xD4) -#define QSERDES_COM_VCOCAL_DEADMAN_CTRL COM_OFF(0xD8) -#define QSERDES_COM_DIV_FRAC_START1_MODE0 COM_OFF(0xDC) -#define QSERDES_COM_DIV_FRAC_START2_MODE0 COM_OFF(0xE0) -#define QSERDES_COM_DIV_FRAC_START3_MODE0 COM_OFF(0xE4) -#define QSERDES_COM_DIV_FRAC_START1_MODE1 COM_OFF(0xE8) -#define QSERDES_COM_DIV_FRAC_START2_MODE1 COM_OFF(0xEC) -#define QSERDES_COM_DIV_FRAC_START3_MODE1 COM_OFF(0xF0) -#define QSERDES_COM_VCO_TUNE_MINVAL1 COM_OFF(0xF4) -#define QSERDES_COM_VCO_TUNE_MINVAL2 COM_OFF(0xF8) -#define QSERDES_COM_CMN_RSVD4 COM_OFF(0xFC) -#define QSERDES_COM_INTEGLOOP_INITVAL COM_OFF(0x100) -#define QSERDES_COM_INTEGLOOP_EN COM_OFF(0x104) -#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 COM_OFF(0x108) -#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 COM_OFF(0x10C) -#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 COM_OFF(0x110) -#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 COM_OFF(0x114) -#define QSERDES_COM_VCO_TUNE_MAXVAL1 COM_OFF(0x118) -#define QSERDES_COM_VCO_TUNE_MAXVAL2 COM_OFF(0x11C) -#define QSERDES_COM_RES_TRIM_CONTROL2 COM_OFF(0x120) -#define QSERDES_COM_VCO_TUNE_CTRL COM_OFF(0x124) -#define QSERDES_COM_VCO_TUNE_MAP COM_OFF(0x128) -#define QSERDES_COM_VCO_TUNE1_MODE0 COM_OFF(0x12C) -#define QSERDES_COM_VCO_TUNE2_MODE0 COM_OFF(0x130) -#define QSERDES_COM_VCO_TUNE1_MODE1 COM_OFF(0x134) -#define QSERDES_COM_VCO_TUNE2_MODE1 COM_OFF(0x138) -#define QSERDES_COM_VCO_TUNE_INITVAL1 COM_OFF(0x13C) -#define QSERDES_COM_VCO_TUNE_INITVAL2 COM_OFF(0x140) -#define QSERDES_COM_VCO_TUNE_TIMER1 COM_OFF(0x144) -#define QSERDES_COM_VCO_TUNE_TIMER2 COM_OFF(0x148) -#define QSERDES_COM_SAR COM_OFF(0x14C) -#define QSERDES_COM_SAR_CLK COM_OFF(0x150) -#define QSERDES_COM_SAR_CODE_OUT_STATUS COM_OFF(0x154) -#define QSERDES_COM_SAR_CODE_READY_STATUS COM_OFF(0x158) -#define QSERDES_COM_CMN_STATUS COM_OFF(0x15C) -#define QSERDES_COM_RESET_SM_STATUS COM_OFF(0x160) -#define QSERDES_COM_RESTRIM_CODE_STATUS COM_OFF(0x164) -#define QSERDES_COM_PLLCAL_CODE1_STATUS COM_OFF(0x168) -#define QSERDES_COM_PLLCAL_CODE2_STATUS COM_OFF(0x16C) -#define QSERDES_COM_BG_CTRL COM_OFF(0x170) -#define QSERDES_COM_CLK_SELECT COM_OFF(0x174) -#define QSERDES_COM_HSCLK_SEL COM_OFF(0x178) -#define QSERDES_COM_INTEGLOOP_BINCODE_STATUS COM_OFF(0x17C) -#define QSERDES_COM_PLL_ANALOG COM_OFF(0x180) -#define QSERDES_COM_CORECLK_DIV COM_OFF(0x184) -#define QSERDES_COM_SW_RESET COM_OFF(0x188) -#define QSERDES_COM_CORE_CLK_EN COM_OFF(0x18C) -#define QSERDES_COM_C_READY_STATUS COM_OFF(0x190) -#define QSERDES_COM_CMN_CONFIG COM_OFF(0x194) -#define QSERDES_COM_CMN_RATE_OVERRIDE COM_OFF(0x198) -#define QSERDES_COM_SVS_MODE_CLK_SEL COM_OFF(0x19C) -#define QSERDES_COM_DEBUG_BUS0 COM_OFF(0x1A0) -#define QSERDES_COM_DEBUG_BUS1 COM_OFF(0x1A4) -#define QSERDES_COM_DEBUG_BUS2 COM_OFF(0x1A8) -#define QSERDES_COM_DEBUG_BUS3 COM_OFF(0x1AC) -#define QSERDES_COM_DEBUG_BUS_SEL COM_OFF(0x1B0) -#define QSERDES_COM_CMN_MISC1 COM_OFF(0x1B4) -#define QSERDES_COM_CORECLK_DIV_MODE1 COM_OFF(0x1BC) -#define QSERDES_COM_CMN_RSVD5 COM_OFF(0x1C0) - -/* UFS PHY registers */ -#define UFS_PHY_PHY_START PHY_OFF(0x00) -#define UFS_PHY_POWER_DOWN_CONTROL PHY_OFF(0x04) -#define UFS_PHY_TX_LARGE_AMP_DRV_LVL PHY_OFF(0x34) -#define UFS_PHY_TX_SMALL_AMP_DRV_LVL PHY_OFF(0x3C) -#define UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP PHY_OFF(0xCC) -#define UFS_PHY_LINECFG_DISABLE PHY_OFF(0x138) -#define UFS_PHY_RX_SYM_RESYNC_CTRL PHY_OFF(0x13C) -#define UFS_PHY_RX_SIGDET_CTRL2 PHY_OFF(0x148) -#define UFS_PHY_RX_PWM_GEAR_BAND PHY_OFF(0x154) -#define UFS_PHY_PCS_READY_STATUS PHY_OFF(0x168) - -/* UFS PHY TX registers */ -#define QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN TX_OFF(0x68) -#define QSERDES_TX_LANE_MODE TX_OFF(0x94) - -/* UFS PHY RX registers */ -#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF RX_OFF(0x30) -#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER RX_OFF(0x34) -#define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH RX_OFF(0x38) -#define QSERDES_RX_UCDR_SVS_SO_GAIN RX_OFF(0x3C) -#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN RX_OFF(0x40) -#define QSERDES_RX_UCDR_SO_SATURATION_ENABLE RX_OFF(0x48) -#define QSERDES_RX_RX_TERM_BW RX_OFF(0x90) -#define QSERDES_RX_RX_EQ_GAIN1_LSB RX_OFF(0xC4) -#define QSERDES_RX_RX_EQ_GAIN1_MSB RX_OFF(0xC8) -#define QSERDES_RX_RX_EQ_GAIN2_LSB RX_OFF(0xCC) -#define QSERDES_RX_RX_EQ_GAIN2_MSB RX_OFF(0xD0) -#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 RX_OFF(0xD8) -#define QSERDES_RX_SIGDET_CNTRL RX_OFF(0x114) -#define QSERDES_RX_SIGDET_LVL RX_OFF(0x118) -#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL RX_OFF(0x11C) -#define QSERDES_RX_RX_INTERFACE_MODE RX_OFF(0x12C) - - -#define UFS_PHY_RX_LINECFG_DISABLE_BIT BIT(1) - -/* - * This structure represents the v3 falcon specific phy. - * common_cfg MUST remain the first field in this structure - * in case extra fields are added. This way, when calling - * get_ufs_qcom_phy() of generic phy, we can extract the - * common phy structure (struct ufs_qcom_phy) out of it - * regardless of the relevant specific phy. - */ -struct ufs_qcom_phy_qmp_v3_falcon { - struct ufs_qcom_phy common_cfg; -}; - -static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_3_1_1[] = { - UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG, 0x0e), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0x14), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CLK_SELECT, 0x30), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x02), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TIMER, 0x0a), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV, 0x0a), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_CTRL, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x20), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_EN, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_CFG, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x04), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x0b), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x0b), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), - - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN, 0x45), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE, 0x06), - - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_LVL, 0x24), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL, 0x0F), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_INTERFACE_MODE, 0x40), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_BW, 0x5B), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D), - - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TRIM, 0x0F), - UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_PWM_GEAR_BAND, 0x15), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SO_SATURATION_ENABLE, 0x4B), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL1, 0xFF), - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), - UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6c), - UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0A), - UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02), - UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), - UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYM_RESYNC_CTRL, 0x03), -}; - -static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = { - UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x44), -}; - -#endif diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 68546eec7f61..3f9f58f57393 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -112,13 +112,13 @@ config PINCTRL_MSM8996 This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm MSM8996 platform. -config PINCTRL_MSMFALCON - tristate "Qualcomm MSMFALCON pin controller driver" +config PINCTRL_SDM660 + tristate "Qualcomm SDM660 pin controller driver" depends on GPIOLIB && OF select PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the - Qualcomm TLMM block found in the Qualcomm MSMFALCON platform. + Qualcomm TLMM block found in the Qualcomm SDM660 platform. config PINCTRL_WCD tristate "Qualcomm Technologies, Inc WCD pin controller driver" diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index fa228c7243e2..502b91f455d7 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -14,6 +14,6 @@ obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o obj-$(CONFIG_PINCTRL_MSM8996) += pinctrl-msm8996.o obj-$(CONFIG_PINCTRL_MSM8998) += pinctrl-msm8998.o -obj-$(CONFIG_PINCTRL_MSMFALCON) += pinctrl-msmfalcon.o +obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o obj-$(CONFIG_PINCTRL_WCD) += pinctrl-wcd.o obj-$(CONFIG_PINCTRL_LPI) += pinctrl-lpi.o diff --git a/drivers/pinctrl/qcom/pinctrl-msmfalcon.c b/drivers/pinctrl/qcom/pinctrl-msmfalcon.c deleted file mode 100644 index 91bbce2ce1d1..000000000000 --- a/drivers/pinctrl/qcom/pinctrl-msmfalcon.c +++ /dev/null @@ -1,1722 +0,0 @@ -/* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#include "pinctrl-msm.h" - -#define FUNCTION(fname) \ - [msm_mux_##fname] = { \ - .name = #fname, \ - .groups = fname##_groups, \ - .ngroups = ARRAY_SIZE(fname##_groups), \ - } - -#define NORTH 0x00900000 -#define CENTER 0x00500000 -#define SOUTH 0x00100000 -#define REG_SIZE 0x1000 -#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ - { \ - .name = "gpio" #id, \ - .pins = gpio##id##_pins, \ - .npins = (unsigned)ARRAY_SIZE(gpio##id##_pins), \ - .funcs = (int[]){ \ - msm_mux_gpio, /* gpio mode */ \ - msm_mux_##f1, \ - msm_mux_##f2, \ - msm_mux_##f3, \ - msm_mux_##f4, \ - msm_mux_##f5, \ - msm_mux_##f6, \ - msm_mux_##f7, \ - msm_mux_##f8, \ - msm_mux_##f9 \ - }, \ - .nfuncs = 10, \ - .ctl_reg = base + REG_SIZE * id, \ - .io_reg = base + 0x4 + REG_SIZE * id, \ - .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \ - .intr_status_reg = base + 0xc + REG_SIZE * id, \ - .intr_target_reg = base + 0x8 + REG_SIZE * id, \ - .mux_bit = 2, \ - .pull_bit = 0, \ - .drv_bit = 6, \ - .oe_bit = 9, \ - .in_bit = 0, \ - .out_bit = 1, \ - .intr_enable_bit = 0, \ - .intr_status_bit = 0, \ - .intr_target_bit = 5, \ - .intr_target_kpss_val = 3, \ - .intr_raw_status_bit = 4, \ - .intr_polarity_bit = 1, \ - .intr_detection_bit = 2, \ - .intr_detection_width = 2, \ - } - -#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ - { \ - .name = #pg_name, \ - .pins = pg_name##_pins, \ - .npins = (unsigned)ARRAY_SIZE(pg_name##_pins), \ - .ctl_reg = ctl, \ - .io_reg = 0, \ - .intr_cfg_reg = 0, \ - .intr_status_reg = 0, \ - .intr_target_reg = 0, \ - .mux_bit = -1, \ - .pull_bit = pull, \ - .drv_bit = drv, \ - .oe_bit = -1, \ - .in_bit = -1, \ - .out_bit = -1, \ - .intr_enable_bit = -1, \ - .intr_status_bit = -1, \ - .intr_target_bit = -1, \ - .intr_raw_status_bit = -1, \ - .intr_polarity_bit = -1, \ - .intr_detection_bit = -1, \ - .intr_detection_width = -1, \ - } -static const struct pinctrl_pin_desc msmfalcon_pins[] = { - PINCTRL_PIN(0, "GPIO_0"), - PINCTRL_PIN(1, "GPIO_1"), - PINCTRL_PIN(2, "GPIO_2"), - PINCTRL_PIN(3, "GPIO_3"), - PINCTRL_PIN(4, "GPIO_4"), - PINCTRL_PIN(5, "GPIO_5"), - PINCTRL_PIN(6, "GPIO_6"), - PINCTRL_PIN(7, "GPIO_7"), - PINCTRL_PIN(8, "GPIO_8"), - PINCTRL_PIN(9, "GPIO_9"), - PINCTRL_PIN(10, "GPIO_10"), - PINCTRL_PIN(11, "GPIO_11"), - PINCTRL_PIN(12, "GPIO_12"), - PINCTRL_PIN(13, "GPIO_13"), - PINCTRL_PIN(14, "GPIO_14"), - PINCTRL_PIN(15, "GPIO_15"), - PINCTRL_PIN(16, "GPIO_16"), - PINCTRL_PIN(17, "GPIO_17"), - PINCTRL_PIN(18, "GPIO_18"), - PINCTRL_PIN(19, "GPIO_19"), - PINCTRL_PIN(20, "GPIO_20"), - PINCTRL_PIN(21, "GPIO_21"), - PINCTRL_PIN(22, "GPIO_22"), - PINCTRL_PIN(23, "GPIO_23"), - PINCTRL_PIN(24, "GPIO_24"), - PINCTRL_PIN(25, "GPIO_25"), - PINCTRL_PIN(26, "GPIO_26"), - PINCTRL_PIN(27, "GPIO_27"), - PINCTRL_PIN(28, "GPIO_28"), - PINCTRL_PIN(29, "GPIO_29"), - PINCTRL_PIN(30, "GPIO_30"), - PINCTRL_PIN(31, "GPIO_31"), - PINCTRL_PIN(32, "GPIO_32"), - PINCTRL_PIN(33, "GPIO_33"), - PINCTRL_PIN(34, "GPIO_34"), - PINCTRL_PIN(35, "GPIO_35"), - PINCTRL_PIN(36, "GPIO_36"), - PINCTRL_PIN(37, "GPIO_37"), - PINCTRL_PIN(38, "GPIO_38"), - PINCTRL_PIN(39, "GPIO_39"), - PINCTRL_PIN(40, "GPIO_40"), - PINCTRL_PIN(41, "GPIO_41"), - PINCTRL_PIN(42, "GPIO_42"), - PINCTRL_PIN(43, "GPIO_43"), - PINCTRL_PIN(44, "GPIO_44"), - PINCTRL_PIN(45, "GPIO_45"), - PINCTRL_PIN(46, "GPIO_46"), - PINCTRL_PIN(47, "GPIO_47"), - PINCTRL_PIN(48, "GPIO_48"), - PINCTRL_PIN(49, "GPIO_49"), - PINCTRL_PIN(50, "GPIO_50"), - PINCTRL_PIN(51, "GPIO_51"), - PINCTRL_PIN(52, "GPIO_52"), - PINCTRL_PIN(53, "GPIO_53"), - PINCTRL_PIN(54, "GPIO_54"), - PINCTRL_PIN(55, "GPIO_55"), - PINCTRL_PIN(56, "GPIO_56"), - PINCTRL_PIN(57, "GPIO_57"), - PINCTRL_PIN(58, "GPIO_58"), - PINCTRL_PIN(59, "GPIO_59"), - PINCTRL_PIN(60, "GPIO_60"), - PINCTRL_PIN(61, "GPIO_61"), - PINCTRL_PIN(62, "GPIO_62"), - PINCTRL_PIN(63, "GPIO_63"), - PINCTRL_PIN(64, "GPIO_64"), - PINCTRL_PIN(65, "GPIO_65"), - PINCTRL_PIN(66, "GPIO_66"), - PINCTRL_PIN(67, "GPIO_67"), - PINCTRL_PIN(68, "GPIO_68"), - PINCTRL_PIN(69, "GPIO_69"), - PINCTRL_PIN(70, "GPIO_70"), - PINCTRL_PIN(71, "GPIO_71"), - PINCTRL_PIN(72, "GPIO_72"), - PINCTRL_PIN(73, "GPIO_73"), - PINCTRL_PIN(74, "GPIO_74"), - PINCTRL_PIN(75, "GPIO_75"), - PINCTRL_PIN(76, "GPIO_76"), - PINCTRL_PIN(77, "GPIO_77"), - PINCTRL_PIN(78, "GPIO_78"), - PINCTRL_PIN(79, "GPIO_79"), - PINCTRL_PIN(80, "GPIO_80"), - PINCTRL_PIN(81, "GPIO_81"), - PINCTRL_PIN(82, "GPIO_82"), - PINCTRL_PIN(83, "GPIO_83"), - PINCTRL_PIN(84, "GPIO_84"), - PINCTRL_PIN(85, "GPIO_85"), - PINCTRL_PIN(86, "GPIO_86"), - PINCTRL_PIN(87, "GPIO_87"), - PINCTRL_PIN(88, "GPIO_88"), - PINCTRL_PIN(89, "GPIO_89"), - PINCTRL_PIN(90, "GPIO_90"), - PINCTRL_PIN(91, "GPIO_91"), - PINCTRL_PIN(92, "GPIO_92"), - PINCTRL_PIN(93, "GPIO_93"), - PINCTRL_PIN(94, "GPIO_94"), - PINCTRL_PIN(95, "GPIO_95"), - PINCTRL_PIN(96, "GPIO_96"), - PINCTRL_PIN(97, "GPIO_97"), - PINCTRL_PIN(98, "GPIO_98"), - PINCTRL_PIN(99, "GPIO_99"), - PINCTRL_PIN(100, "GPIO_100"), - PINCTRL_PIN(101, "GPIO_101"), - PINCTRL_PIN(102, "GPIO_102"), - PINCTRL_PIN(103, "GPIO_103"), - PINCTRL_PIN(104, "GPIO_104"), - PINCTRL_PIN(105, "GPIO_105"), - PINCTRL_PIN(106, "GPIO_106"), - PINCTRL_PIN(107, "GPIO_107"), - PINCTRL_PIN(108, "GPIO_108"), - PINCTRL_PIN(109, "GPIO_109"), - PINCTRL_PIN(110, "GPIO_110"), - PINCTRL_PIN(111, "GPIO_111"), - PINCTRL_PIN(112, "GPIO_112"), - PINCTRL_PIN(113, "GPIO_113"), - PINCTRL_PIN(114, "SDC1_CLK"), - PINCTRL_PIN(115, "SDC1_CMD"), - PINCTRL_PIN(116, "SDC1_DATA"), - PINCTRL_PIN(117, "SDC2_CLK"), - PINCTRL_PIN(118, "SDC2_CMD"), - PINCTRL_PIN(119, "SDC2_DATA"), - PINCTRL_PIN(120, "SDC1_RCLK"), -}; - -#define DECLARE_MSM_GPIO_PINS(pin) \ - static const unsigned int gpio##pin##_pins[] = { pin } -DECLARE_MSM_GPIO_PINS(0); -DECLARE_MSM_GPIO_PINS(1); -DECLARE_MSM_GPIO_PINS(2); -DECLARE_MSM_GPIO_PINS(3); -DECLARE_MSM_GPIO_PINS(4); -DECLARE_MSM_GPIO_PINS(5); -DECLARE_MSM_GPIO_PINS(6); -DECLARE_MSM_GPIO_PINS(7); -DECLARE_MSM_GPIO_PINS(8); -DECLARE_MSM_GPIO_PINS(9); -DECLARE_MSM_GPIO_PINS(10); -DECLARE_MSM_GPIO_PINS(11); -DECLARE_MSM_GPIO_PINS(12); -DECLARE_MSM_GPIO_PINS(13); -DECLARE_MSM_GPIO_PINS(14); -DECLARE_MSM_GPIO_PINS(15); -DECLARE_MSM_GPIO_PINS(16); -DECLARE_MSM_GPIO_PINS(17); -DECLARE_MSM_GPIO_PINS(18); -DECLARE_MSM_GPIO_PINS(19); -DECLARE_MSM_GPIO_PINS(20); -DECLARE_MSM_GPIO_PINS(21); -DECLARE_MSM_GPIO_PINS(22); -DECLARE_MSM_GPIO_PINS(23); -DECLARE_MSM_GPIO_PINS(24); -DECLARE_MSM_GPIO_PINS(25); -DECLARE_MSM_GPIO_PINS(26); -DECLARE_MSM_GPIO_PINS(27); -DECLARE_MSM_GPIO_PINS(28); -DECLARE_MSM_GPIO_PINS(29); -DECLARE_MSM_GPIO_PINS(30); -DECLARE_MSM_GPIO_PINS(31); -DECLARE_MSM_GPIO_PINS(32); -DECLARE_MSM_GPIO_PINS(33); -DECLARE_MSM_GPIO_PINS(34); -DECLARE_MSM_GPIO_PINS(35); -DECLARE_MSM_GPIO_PINS(36); -DECLARE_MSM_GPIO_PINS(37); -DECLARE_MSM_GPIO_PINS(38); -DECLARE_MSM_GPIO_PINS(39); -DECLARE_MSM_GPIO_PINS(40); -DECLARE_MSM_GPIO_PINS(41); -DECLARE_MSM_GPIO_PINS(42); -DECLARE_MSM_GPIO_PINS(43); -DECLARE_MSM_GPIO_PINS(44); -DECLARE_MSM_GPIO_PINS(45); -DECLARE_MSM_GPIO_PINS(46); -DECLARE_MSM_GPIO_PINS(47); -DECLARE_MSM_GPIO_PINS(48); -DECLARE_MSM_GPIO_PINS(49); -DECLARE_MSM_GPIO_PINS(50); -DECLARE_MSM_GPIO_PINS(51); -DECLARE_MSM_GPIO_PINS(52); -DECLARE_MSM_GPIO_PINS(53); -DECLARE_MSM_GPIO_PINS(54); -DECLARE_MSM_GPIO_PINS(55); -DECLARE_MSM_GPIO_PINS(56); -DECLARE_MSM_GPIO_PINS(57); -DECLARE_MSM_GPIO_PINS(58); -DECLARE_MSM_GPIO_PINS(59); -DECLARE_MSM_GPIO_PINS(60); -DECLARE_MSM_GPIO_PINS(61); -DECLARE_MSM_GPIO_PINS(62); -DECLARE_MSM_GPIO_PINS(63); -DECLARE_MSM_GPIO_PINS(64); -DECLARE_MSM_GPIO_PINS(65); -DECLARE_MSM_GPIO_PINS(66); -DECLARE_MSM_GPIO_PINS(67); -DECLARE_MSM_GPIO_PINS(68); -DECLARE_MSM_GPIO_PINS(69); -DECLARE_MSM_GPIO_PINS(70); -DECLARE_MSM_GPIO_PINS(71); -DECLARE_MSM_GPIO_PINS(72); -DECLARE_MSM_GPIO_PINS(73); -DECLARE_MSM_GPIO_PINS(74); -DECLARE_MSM_GPIO_PINS(75); -DECLARE_MSM_GPIO_PINS(76); -DECLARE_MSM_GPIO_PINS(77); -DECLARE_MSM_GPIO_PINS(78); -DECLARE_MSM_GPIO_PINS(79); -DECLARE_MSM_GPIO_PINS(80); -DECLARE_MSM_GPIO_PINS(81); -DECLARE_MSM_GPIO_PINS(82); -DECLARE_MSM_GPIO_PINS(83); -DECLARE_MSM_GPIO_PINS(84); -DECLARE_MSM_GPIO_PINS(85); -DECLARE_MSM_GPIO_PINS(86); -DECLARE_MSM_GPIO_PINS(87); -DECLARE_MSM_GPIO_PINS(88); -DECLARE_MSM_GPIO_PINS(89); -DECLARE_MSM_GPIO_PINS(90); -DECLARE_MSM_GPIO_PINS(91); -DECLARE_MSM_GPIO_PINS(92); -DECLARE_MSM_GPIO_PINS(93); -DECLARE_MSM_GPIO_PINS(94); -DECLARE_MSM_GPIO_PINS(95); -DECLARE_MSM_GPIO_PINS(96); -DECLARE_MSM_GPIO_PINS(97); -DECLARE_MSM_GPIO_PINS(98); -DECLARE_MSM_GPIO_PINS(99); -DECLARE_MSM_GPIO_PINS(100); -DECLARE_MSM_GPIO_PINS(101); -DECLARE_MSM_GPIO_PINS(102); -DECLARE_MSM_GPIO_PINS(103); -DECLARE_MSM_GPIO_PINS(104); -DECLARE_MSM_GPIO_PINS(105); -DECLARE_MSM_GPIO_PINS(106); -DECLARE_MSM_GPIO_PINS(107); -DECLARE_MSM_GPIO_PINS(108); -DECLARE_MSM_GPIO_PINS(109); -DECLARE_MSM_GPIO_PINS(110); -DECLARE_MSM_GPIO_PINS(111); -DECLARE_MSM_GPIO_PINS(112); -DECLARE_MSM_GPIO_PINS(113); - -static const unsigned int sdc1_clk_pins[] = { 114 }; -static const unsigned int sdc1_cmd_pins[] = { 115 }; -static const unsigned int sdc1_data_pins[] = { 116 }; -static const unsigned int sdc2_clk_pins[] = { 117 }; -static const unsigned int sdc2_cmd_pins[] = { 118 }; -static const unsigned int sdc2_data_pins[] = { 119 }; -static const unsigned int sdc1_rclk_pins[] = { 120 }; - -enum msmfalcon_functions { - msm_mux_blsp_spi1, - msm_mux_gpio, - msm_mux_blsp_uim1, - msm_mux_tgu_ch0, - msm_mux_qdss_gpio4, - msm_mux_atest_gpsadc1, - msm_mux_blsp_uart1, - msm_mux_SMB_STAT, - msm_mux_phase_flag14, - msm_mux_blsp_i2c2, - msm_mux_phase_flag31, - msm_mux_blsp_spi3, - msm_mux_blsp_spi3_cs1, - msm_mux_blsp_spi3_cs2, - msm_mux_wlan1_adc1, - msm_mux_atest_usb13, - msm_mux_tgu_ch1, - msm_mux_qdss_gpio5, - msm_mux_atest_gpsadc0, - msm_mux_blsp_i2c1, - msm_mux_ddr_bist, - msm_mux_atest_tsens2, - msm_mux_atest_usb1, - msm_mux_blsp_spi2, - msm_mux_blsp_uim2, - msm_mux_phase_flag3, - msm_mux_bimc_dte1, - msm_mux_wlan1_adc0, - msm_mux_atest_usb12, - msm_mux_bimc_dte0, - msm_mux_blsp_i2c3, - msm_mux_wlan2_adc1, - msm_mux_atest_usb11, - msm_mux_dbg_out, - msm_mux_wlan2_adc0, - msm_mux_atest_usb10, - msm_mux_RCM_MARKER, - msm_mux_blsp_spi4, - msm_mux_pri_mi2s, - msm_mux_phase_flag26, - msm_mux_qdss_cti0_a, - msm_mux_qdss_cti0_b, - msm_mux_qdss_cti1_a, - msm_mux_qdss_cti1_b, - msm_mux_DP_HOT, - msm_mux_pri_mi2s_ws, - msm_mux_phase_flag27, - msm_mux_blsp_i2c4, - msm_mux_phase_flag28, - msm_mux_blsp_uart5, - msm_mux_blsp_spi5, - msm_mux_blsp_uim5, - msm_mux_phase_flag5, - msm_mux_blsp_i2c5, - msm_mux_blsp_spi6, - msm_mux_blsp_uart2, - msm_mux_blsp_uim6, - msm_mux_phase_flag11, - msm_mux_vsense_data0, - msm_mux_blsp_i2c6, - msm_mux_phase_flag12, - msm_mux_vsense_data1, - msm_mux_phase_flag13, - msm_mux_vsense_mode, - msm_mux_blsp_spi7, - msm_mux_blsp_uart6_a, - msm_mux_blsp_uart6_b, - msm_mux_sec_mi2s, - msm_mux_sndwire_clk, - msm_mux_phase_flag17, - msm_mux_vsense_clkout, - msm_mux_sndwire_data, - msm_mux_phase_flag18, - msm_mux_WSA_SPKR, - msm_mux_blsp_i2c7, - msm_mux_phase_flag19, - msm_mux_vfr_1, - msm_mux_phase_flag20, - msm_mux_NFC_INT, - msm_mux_blsp_spi8_cs1, - msm_mux_blsp_spi8_cs2, - msm_mux_m_voc, - msm_mux_phase_flag21, - msm_mux_NFC_EN, - msm_mux_phase_flag22, - msm_mux_NFC_DWL, - msm_mux_blsp_i2c8_a, - msm_mux_blsp_i2c8_b, - msm_mux_phase_flag23, - msm_mux_NFC_ESE, - msm_mux_pwr_modem, - msm_mux_phase_flag24, - msm_mux_qdss_gpio, - msm_mux_cam_mclk, - msm_mux_pwr_nav, - msm_mux_qdss_gpio0, - msm_mux_qspi_data0, - msm_mux_pwr_crypto, - msm_mux_qdss_gpio1, - msm_mux_qspi_data1, - msm_mux_agera_pll, - msm_mux_qdss_gpio2, - msm_mux_qspi_data2, - msm_mux_jitter_bist, - msm_mux_qdss_gpio3, - msm_mux_qdss_gpio7, - msm_mux_FL_R3LED, - msm_mux_CCI_TIMER0, - msm_mux_FL_STROBE, - msm_mux_CCI_TIMER1, - msm_mux_CAM_LDO1, - msm_mux_mdss_vsync0, - msm_mux_mdss_vsync1, - msm_mux_mdss_vsync2, - msm_mux_mdss_vsync3, - msm_mux_qdss_gpio9, - msm_mux_CAM_IRQ, - msm_mux_atest_usb2, - msm_mux_cci_i2c, - msm_mux_pll_bypassnl, - msm_mux_atest_tsens, - msm_mux_atest_usb21, - msm_mux_pll_reset, - msm_mux_atest_usb23, - msm_mux_qdss_gpio6, - msm_mux_CCI_TIMER3, - msm_mux_CCI_ASYNC, - msm_mux_qspi_cs, - msm_mux_qdss_gpio10, - msm_mux_CAM3_STANDBY, - msm_mux_CCI_TIMER4, - msm_mux_qdss_gpio11, - msm_mux_CAM_LDO2, - msm_mux_cci_async, - msm_mux_qdss_gpio12, - msm_mux_CAM0_RST, - msm_mux_qdss_gpio13, - msm_mux_CAM1_RST, - msm_mux_qspi_clk, - msm_mux_phase_flag30, - msm_mux_qdss_gpio14, - msm_mux_qspi_resetn, - msm_mux_phase_flag1, - msm_mux_qdss_gpio15, - msm_mux_CAM0_STANDBY, - msm_mux_phase_flag2, - msm_mux_CAM1_STANDBY, - msm_mux_phase_flag9, - msm_mux_CAM2_STANDBY, - msm_mux_qspi_data3, - msm_mux_phase_flag15, - msm_mux_qdss_gpio8, - msm_mux_CAM3_RST, - msm_mux_CCI_TIMER2, - msm_mux_phase_flag16, - msm_mux_LCD0_RESET, - msm_mux_phase_flag6, - msm_mux_SD_CARD, - msm_mux_phase_flag29, - msm_mux_DP_EN, - msm_mux_phase_flag25, - msm_mux_USBC_ORIENTATION, - msm_mux_phase_flag10, - msm_mux_atest_usb20, - msm_mux_gcc_gp1, - msm_mux_phase_flag4, - msm_mux_atest_usb22, - msm_mux_USB_PHY, - msm_mux_gcc_gp2, - msm_mux_atest_char, - msm_mux_mdp_vsync, - msm_mux_gcc_gp3, - msm_mux_atest_char3, - msm_mux_FORCE_TOUCH, - msm_mux_cri_trng0, - msm_mux_atest_char2, - msm_mux_cri_trng1, - msm_mux_atest_char1, - msm_mux_AUDIO_USBC, - msm_mux_audio_ref, - msm_mux_MDP_VSYNC, - msm_mux_cri_trng, - msm_mux_atest_char0, - msm_mux_US_EURO, - msm_mux_LCD_BACKLIGHT, - msm_mux_blsp_spi8_a, - msm_mux_blsp_spi8_b, - msm_mux_sp_cmu, - msm_mux_nav_pps_a, - msm_mux_nav_pps_b, - msm_mux_nav_pps_c, - msm_mux_gps_tx_a, - msm_mux_gps_tx_b, - msm_mux_gps_tx_c, - msm_mux_adsp_ext, - msm_mux_TS_RESET, - msm_mux_ssc_irq, - msm_mux_isense_dbg, - msm_mux_phase_flag0, - msm_mux_phase_flag7, - msm_mux_phase_flag8, - msm_mux_tsense_pwm1, - msm_mux_tsense_pwm2, - msm_mux_SENSOR_RST, - msm_mux_WMSS_RESETN, - msm_mux_HAPTICS_PWM, - msm_mux_GPS_eLNA, - msm_mux_mss_lte, - msm_mux_uim2_data, - msm_mux_uim2_clk, - msm_mux_uim2_reset, - msm_mux_uim2_present, - msm_mux_uim1_data, - msm_mux_uim1_clk, - msm_mux_uim1_reset, - msm_mux_uim1_present, - msm_mux_uim_batt, - msm_mux_pa_indicator, - msm_mux_ldo_en, - msm_mux_ldo_update, - msm_mux_qlink_request, - msm_mux_qlink_enable, - msm_mux_prng_rosc, - msm_mux_LCD_PWR, - msm_mux_NA, -}; - -static const char * const blsp_spi1_groups[] = { - "gpio0", "gpio1", "gpio2", "gpio3", "gpio46", -}; -static const char * const gpio_groups[] = { - "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", - "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", - "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", - "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", - "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", - "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", - "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", - "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", - "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", - "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", - "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", - "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", - "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", - "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", - "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", - "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", - "gpio111", "gpio112", "gpio113", -}; -static const char * const blsp_uim1_groups[] = { - "gpio0", "gpio1", -}; -static const char * const tgu_ch0_groups[] = { - "gpio0", -}; -static const char * const qdss_gpio4_groups[] = { - "gpio0", "gpio36", -}; -static const char * const atest_gpsadc1_groups[] = { - "gpio0", -}; -static const char * const blsp_uart1_groups[] = { - "gpio0", "gpio1", "gpio2", "gpio3", -}; -static const char * const SMB_STAT_groups[] = { - "gpio5", -}; -static const char * const phase_flag14_groups[] = { - "gpio5", -}; -static const char * const blsp_i2c2_groups[] = { - "gpio6", "gpio7", -}; -static const char * const phase_flag31_groups[] = { - "gpio6", -}; -static const char * const blsp_spi3_groups[] = { - "gpio8", "gpio9", "gpio10", "gpio11", -}; -static const char * const blsp_spi3_cs1_groups[] = { - "gpio30", -}; -static const char * const blsp_spi3_cs2_groups[] = { - "gpio65", -}; -static const char * const wlan1_adc1_groups[] = { - "gpio8", -}; -static const char * const atest_usb13_groups[] = { - "gpio8", -}; -static const char * const tgu_ch1_groups[] = { - "gpio1", -}; -static const char * const qdss_gpio5_groups[] = { - "gpio1", "gpio37", -}; -static const char * const atest_gpsadc0_groups[] = { - "gpio1", -}; -static const char * const blsp_i2c1_groups[] = { - "gpio2", "gpio3", -}; -static const char * const ddr_bist_groups[] = { - "gpio3", "gpio8", "gpio9", "gpio10", -}; -static const char * const atest_tsens2_groups[] = { - "gpio3", -}; -static const char * const atest_usb1_groups[] = { - "gpio3", -}; -static const char * const blsp_spi2_groups[] = { - "gpio4", "gpio5", "gpio6", "gpio7", -}; -static const char * const blsp_uim2_groups[] = { - "gpio4", "gpio5", -}; -static const char * const phase_flag3_groups[] = { - "gpio4", -}; -static const char * const bimc_dte1_groups[] = { - "gpio8", "gpio10", -}; -static const char * const wlan1_adc0_groups[] = { - "gpio9", -}; -static const char * const atest_usb12_groups[] = { - "gpio9", -}; -static const char * const bimc_dte0_groups[] = { - "gpio9", "gpio11", -}; -static const char * const blsp_i2c3_groups[] = { - "gpio10", "gpio11", -}; -static const char * const wlan2_adc1_groups[] = { - "gpio10", -}; -static const char * const atest_usb11_groups[] = { - "gpio10", -}; -static const char * const dbg_out_groups[] = { - "gpio11", -}; -static const char * const wlan2_adc0_groups[] = { - "gpio11", -}; -static const char * const atest_usb10_groups[] = { - "gpio11", -}; -static const char * const RCM_MARKER_groups[] = { - "gpio12", "gpio13", -}; -static const char * const blsp_spi4_groups[] = { - "gpio12", "gpio13", "gpio14", "gpio15", -}; -static const char * const pri_mi2s_groups[] = { - "gpio12", "gpio14", "gpio15", "gpio61", -}; -static const char * const phase_flag26_groups[] = { - "gpio12", -}; -static const char * const qdss_cti0_a_groups[] = { - "gpio49", "gpio50", -}; -static const char * const qdss_cti0_b_groups[] = { - "gpio13", "gpio21", -}; -static const char * const qdss_cti1_a_groups[] = { - "gpio53", "gpio55", -}; -static const char * const qdss_cti1_b_groups[] = { - "gpio12", "gpio66", -}; -static const char * const DP_HOT_groups[] = { - "gpio13", -}; -static const char * const pri_mi2s_ws_groups[] = { - "gpio13", -}; -static const char * const phase_flag27_groups[] = { - "gpio13", -}; -static const char * const blsp_i2c4_groups[] = { - "gpio14", "gpio15", -}; -static const char * const phase_flag28_groups[] = { - "gpio14", -}; -static const char * const blsp_uart5_groups[] = { - "gpio16", "gpio17", "gpio18", "gpio19", -}; -static const char * const blsp_spi5_groups[] = { - "gpio16", "gpio17", "gpio18", "gpio19", -}; -static const char * const blsp_uim5_groups[] = { - "gpio16", "gpio17", -}; -static const char * const phase_flag5_groups[] = { - "gpio17", -}; -static const char * const blsp_i2c5_groups[] = { - "gpio18", "gpio19", -}; -static const char * const blsp_spi6_groups[] = { - "gpio49", "gpio52", "gpio22", "gpio23", -}; -static const char * const blsp_uart2_groups[] = { - "gpio4", "gpio5", "gpio6", "gpio7", -}; -static const char * const blsp_uim6_groups[] = { - "gpio20", "gpio21", -}; -static const char * const phase_flag11_groups[] = { - "gpio21", -}; -static const char * const vsense_data0_groups[] = { - "gpio21", -}; -static const char * const blsp_i2c6_groups[] = { - "gpio22", "gpio23", -}; -static const char * const phase_flag12_groups[] = { - "gpio22", -}; -static const char * const vsense_data1_groups[] = { - "gpio22", -}; -static const char * const phase_flag13_groups[] = { - "gpio23", -}; -static const char * const vsense_mode_groups[] = { - "gpio23", -}; -static const char * const blsp_spi7_groups[] = { - "gpio24", "gpio25", "gpio26", "gpio27", -}; -static const char * const blsp_uart6_a_groups[] = { - "gpio24", "gpio25", "gpio26", "gpio27", -}; -static const char * const blsp_uart6_b_groups[] = { - "gpio28", "gpio29", "gpio30", "gpio31", -}; -static const char * const sec_mi2s_groups[] = { - "gpio24", "gpio25", "gpio26", "gpio27", "gpio62", -}; -static const char * const sndwire_clk_groups[] = { - "gpio24", -}; -static const char * const phase_flag17_groups[] = { - "gpio24", -}; -static const char * const vsense_clkout_groups[] = { - "gpio24", -}; -static const char * const sndwire_data_groups[] = { - "gpio25", -}; -static const char * const phase_flag18_groups[] = { - "gpio25", -}; -static const char * const WSA_SPKR_groups[] = { - "gpio26", "gpio27", -}; -static const char * const blsp_i2c7_groups[] = { - "gpio26", "gpio27", -}; -static const char * const phase_flag19_groups[] = { - "gpio26", -}; -static const char * const vfr_1_groups[] = { - "gpio27", -}; -static const char * const phase_flag20_groups[] = { - "gpio27", -}; -static const char * const NFC_INT_groups[] = { - "gpio28", -}; -static const char * const blsp_spi8_a_groups[] = { - "gpio28", "gpio29", "gpio30", "gpio31", -}; -static const char * const blsp_spi8_b_groups[] = { - "gpio40", "gpio41", "gpio44", "gpio52", -}; -static const char * const m_voc_groups[] = { - "gpio28", -}; -static const char * const phase_flag21_groups[] = { - "gpio28", -}; -static const char * const NFC_EN_groups[] = { - "gpio29", -}; -static const char * const phase_flag22_groups[] = { - "gpio29", -}; -static const char * const NFC_DWL_groups[] = { - "gpio30", -}; -static const char * const blsp_i2c8_a_groups[] = { - "gpio30", "gpio31", -}; -static const char * const blsp_i2c8_b_groups[] = { - "gpio44", "gpio52", -}; -static const char * const phase_flag23_groups[] = { - "gpio30", -}; -static const char * const NFC_ESE_groups[] = { - "gpio31", -}; -static const char * const pwr_modem_groups[] = { - "gpio31", -}; -static const char * const phase_flag24_groups[] = { - "gpio31", -}; -static const char * const qdss_gpio_groups[] = { - "gpio31", "gpio52", "gpio68", "gpio69", -}; -static const char * const cam_mclk_groups[] = { - "gpio32", "gpio33", "gpio34", "gpio35", -}; -static const char * const pwr_nav_groups[] = { - "gpio32", -}; -static const char * const qdss_gpio0_groups[] = { - "gpio32", "gpio67", -}; -static const char * const qspi_data0_groups[] = { - "gpio33", -}; -static const char * const pwr_crypto_groups[] = { - "gpio33", -}; -static const char * const qdss_gpio1_groups[] = { - "gpio33", "gpio63", -}; -static const char * const qspi_data1_groups[] = { - "gpio34", -}; -static const char * const agera_pll_groups[] = { - "gpio34", "gpio36", -}; -static const char * const qdss_gpio2_groups[] = { - "gpio34", "gpio64", -}; -static const char * const qspi_data2_groups[] = { - "gpio35", -}; -static const char * const jitter_bist_groups[] = { - "gpio35", -}; -static const char * const qdss_gpio3_groups[] = { - "gpio35", "gpio56", -}; -static const char * const qdss_gpio7_groups[] = { - "gpio39", "gpio71", -}; -static const char * const FL_R3LED_groups[] = { - "gpio40", -}; -static const char * const CCI_TIMER0_groups[] = { - "gpio40", -}; -static const char * const FL_STROBE_groups[] = { - "gpio41", -}; -static const char * const CCI_TIMER1_groups[] = { - "gpio41", -}; -static const char * const CAM_LDO1_groups[] = { - "gpio42", -}; -static const char * const mdss_vsync0_groups[] = { - "gpio42", -}; -static const char * const mdss_vsync1_groups[] = { - "gpio42", -}; -static const char * const mdss_vsync2_groups[] = { - "gpio42", -}; -static const char * const mdss_vsync3_groups[] = { - "gpio42", -}; -static const char * const qdss_gpio9_groups[] = { - "gpio42", "gpio76", -}; -static const char * const CAM_IRQ_groups[] = { - "gpio43", -}; -static const char * const atest_usb2_groups[] = { - "gpio35", -}; -static const char * const cci_i2c_groups[] = { - "gpio36", "gpio37", "gpio38", "gpio39", -}; -static const char * const pll_bypassnl_groups[] = { - "gpio36", -}; -static const char * const atest_tsens_groups[] = { - "gpio36", -}; -static const char * const atest_usb21_groups[] = { - "gpio36", -}; -static const char * const pll_reset_groups[] = { - "gpio37", -}; -static const char * const atest_usb23_groups[] = { - "gpio37", -}; -static const char * const qdss_gpio6_groups[] = { - "gpio38", "gpio70", -}; -static const char * const CCI_TIMER3_groups[] = { - "gpio43", -}; -static const char * const CCI_ASYNC_groups[] = { - "gpio43", "gpio44", -}; -static const char * const qspi_cs_groups[] = { - "gpio43", "gpio50", -}; -static const char * const qdss_gpio10_groups[] = { - "gpio43", "gpio77", -}; -static const char * const CAM3_STANDBY_groups[] = { - "gpio44", -}; -static const char * const CCI_TIMER4_groups[] = { - "gpio44", -}; -static const char * const qdss_gpio11_groups[] = { - "gpio44", "gpio79", -}; -static const char * const CAM_LDO2_groups[] = { - "gpio45", -}; -static const char * const cci_async_groups[] = { - "gpio45", -}; -static const char * const qdss_gpio12_groups[] = { - "gpio45", "gpio80", -}; -static const char * const CAM0_RST_groups[] = { - "gpio46", -}; -static const char * const qdss_gpio13_groups[] = { - "gpio46", "gpio78", -}; -static const char * const CAM1_RST_groups[] = { - "gpio47", -}; -static const char * const qspi_clk_groups[] = { - "gpio47", -}; -static const char * const phase_flag30_groups[] = { - "gpio47", -}; -static const char * const qdss_gpio14_groups[] = { - "gpio47", "gpio72", -}; -static const char * const qspi_resetn_groups[] = { - "gpio48", -}; -static const char * const phase_flag1_groups[] = { - "gpio48", -}; -static const char * const qdss_gpio15_groups[] = { - "gpio48", "gpio73", -}; -static const char * const CAM0_STANDBY_groups[] = { - "gpio49", -}; -static const char * const phase_flag2_groups[] = { - "gpio49", -}; -static const char * const CAM1_STANDBY_groups[] = { - "gpio50", -}; -static const char * const phase_flag9_groups[] = { - "gpio50", -}; -static const char * const CAM2_STANDBY_groups[] = { - "gpio51", -}; -static const char * const qspi_data3_groups[] = { - "gpio51", -}; -static const char * const phase_flag15_groups[] = { - "gpio51", -}; -static const char * const qdss_gpio8_groups[] = { - "gpio51", "gpio75", -}; -static const char * const CAM3_RST_groups[] = { - "gpio52", -}; -static const char * const CCI_TIMER2_groups[] = { - "gpio52", -}; -static const char * const phase_flag16_groups[] = { - "gpio52", -}; -static const char * const LCD0_RESET_groups[] = { - "gpio53", -}; -static const char * const phase_flag6_groups[] = { - "gpio53", -}; -static const char * const SD_CARD_groups[] = { - "gpio54", -}; -static const char * const phase_flag29_groups[] = { - "gpio54", -}; -static const char * const DP_EN_groups[] = { - "gpio55", -}; -static const char * const phase_flag25_groups[] = { - "gpio55", -}; -static const char * const USBC_ORIENTATION_groups[] = { - "gpio56", -}; -static const char * const phase_flag10_groups[] = { - "gpio56", -}; -static const char * const atest_usb20_groups[] = { - "gpio56", -}; -static const char * const gcc_gp1_groups[] = { - "gpio57", "gpio78", -}; -static const char * const phase_flag4_groups[] = { - "gpio57", -}; -static const char * const atest_usb22_groups[] = { - "gpio57", -}; -static const char * const USB_PHY_groups[] = { - "gpio58", -}; -static const char * const gcc_gp2_groups[] = { - "gpio58", "gpio81", -}; -static const char * const atest_char_groups[] = { - "gpio58", -}; -static const char * const mdp_vsync_groups[] = { - "gpio59", "gpio74", -}; -static const char * const gcc_gp3_groups[] = { - "gpio59", "gpio82", -}; -static const char * const atest_char3_groups[] = { - "gpio59", -}; -static const char * const FORCE_TOUCH_groups[] = { - "gpio60", "gpio73", -}; -static const char * const cri_trng0_groups[] = { - "gpio60", -}; -static const char * const atest_char2_groups[] = { - "gpio60", -}; -static const char * const cri_trng1_groups[] = { - "gpio61", -}; -static const char * const atest_char1_groups[] = { - "gpio61", -}; -static const char * const AUDIO_USBC_groups[] = { - "gpio62", -}; -static const char * const audio_ref_groups[] = { - "gpio62", -}; -static const char * const MDP_VSYNC_groups[] = { - "gpio62", -}; -static const char * const cri_trng_groups[] = { - "gpio62", -}; -static const char * const atest_char0_groups[] = { - "gpio62", -}; -static const char * const US_EURO_groups[] = { - "gpio63", -}; -static const char * const LCD_BACKLIGHT_groups[] = { - "gpio64", -}; -static const char * const blsp_spi8_cs1_groups[] = { - "gpio64", -}; -static const char * const blsp_spi8_cs2_groups[] = { - "gpio76", -}; -static const char * const sp_cmu_groups[] = { - "gpio64", -}; -static const char * const nav_pps_a_groups[] = { - "gpio65", -}; -static const char * const nav_pps_b_groups[] = { - "gpio98", -}; -static const char * const nav_pps_c_groups[] = { - "gpio80", -}; -static const char * const gps_tx_a_groups[] = { - "gpio65", -}; -static const char * const gps_tx_b_groups[] = { - "gpio98", -}; -static const char * const gps_tx_c_groups[] = { - "gpio80", -}; -static const char * const adsp_ext_groups[] = { - "gpio65", -}; -static const char * const TS_RESET_groups[] = { - "gpio66", -}; -static const char * const ssc_irq_groups[] = { - "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72", "gpio74", - "gpio75", "gpio76", -}; -static const char * const isense_dbg_groups[] = { - "gpio68", -}; -static const char * const phase_flag0_groups[] = { - "gpio68", -}; -static const char * const phase_flag7_groups[] = { - "gpio69", -}; -static const char * const phase_flag8_groups[] = { - "gpio70", -}; -static const char * const tsense_pwm1_groups[] = { - "gpio71", -}; -static const char * const tsense_pwm2_groups[] = { - "gpio71", -}; -static const char * const SENSOR_RST_groups[] = { - "gpio77", -}; -static const char * const WMSS_RESETN_groups[] = { - "gpio78", -}; -static const char * const HAPTICS_PWM_groups[] = { - "gpio79", -}; -static const char * const GPS_eLNA_groups[] = { - "gpio80", -}; -static const char * const mss_lte_groups[] = { - "gpio81", "gpio82", -}; -static const char * const uim2_data_groups[] = { - "gpio83", -}; -static const char * const uim2_clk_groups[] = { - "gpio84", -}; -static const char * const uim2_reset_groups[] = { - "gpio85", -}; -static const char * const uim2_present_groups[] = { - "gpio86", -}; -static const char * const uim1_data_groups[] = { - "gpio87", -}; -static const char * const uim1_clk_groups[] = { - "gpio88", -}; -static const char * const uim1_reset_groups[] = { - "gpio89", -}; -static const char * const uim1_present_groups[] = { - "gpio90", -}; -static const char * const uim_batt_groups[] = { - "gpio91", -}; -static const char * const pa_indicator_groups[] = { - "gpio92", -}; -static const char * const ldo_en_groups[] = { - "gpio97", -}; -static const char * const ldo_update_groups[] = { - "gpio98", -}; -static const char * const qlink_request_groups[] = { - "gpio99", -}; -static const char * const qlink_enable_groups[] = { - "gpio100", -}; -static const char * const prng_rosc_groups[] = { - "gpio102", -}; -static const char * const LCD_PWR_groups[] = { - "gpio113", -}; - -static const struct msm_function msmfalcon_functions[] = { - FUNCTION(blsp_spi1), - FUNCTION(gpio), - FUNCTION(blsp_uim1), - FUNCTION(tgu_ch0), - FUNCTION(qdss_gpio4), - FUNCTION(atest_gpsadc1), - FUNCTION(blsp_uart1), - FUNCTION(SMB_STAT), - FUNCTION(phase_flag14), - FUNCTION(blsp_i2c2), - FUNCTION(phase_flag31), - FUNCTION(blsp_spi3), - FUNCTION(blsp_spi3_cs1), - FUNCTION(blsp_spi3_cs2), - FUNCTION(wlan1_adc1), - FUNCTION(atest_usb13), - FUNCTION(tgu_ch1), - FUNCTION(qdss_gpio5), - FUNCTION(atest_gpsadc0), - FUNCTION(blsp_i2c1), - FUNCTION(ddr_bist), - FUNCTION(atest_tsens2), - FUNCTION(atest_usb1), - FUNCTION(blsp_spi2), - FUNCTION(blsp_uim2), - FUNCTION(phase_flag3), - FUNCTION(bimc_dte1), - FUNCTION(wlan1_adc0), - FUNCTION(atest_usb12), - FUNCTION(bimc_dte0), - FUNCTION(blsp_i2c3), - FUNCTION(wlan2_adc1), - FUNCTION(atest_usb11), - FUNCTION(dbg_out), - FUNCTION(wlan2_adc0), - FUNCTION(atest_usb10), - FUNCTION(RCM_MARKER), - FUNCTION(blsp_spi4), - FUNCTION(pri_mi2s), - FUNCTION(phase_flag26), - FUNCTION(qdss_cti0_a), - FUNCTION(qdss_cti0_b), - FUNCTION(qdss_cti1_a), - FUNCTION(qdss_cti1_b), - FUNCTION(DP_HOT), - FUNCTION(pri_mi2s_ws), - FUNCTION(phase_flag27), - FUNCTION(blsp_i2c4), - FUNCTION(phase_flag28), - FUNCTION(blsp_uart5), - FUNCTION(blsp_spi5), - FUNCTION(blsp_uim5), - FUNCTION(phase_flag5), - FUNCTION(blsp_i2c5), - FUNCTION(blsp_spi6), - FUNCTION(blsp_uart2), - FUNCTION(blsp_uim6), - FUNCTION(phase_flag11), - FUNCTION(vsense_data0), - FUNCTION(blsp_i2c6), - FUNCTION(phase_flag12), - FUNCTION(vsense_data1), - FUNCTION(phase_flag13), - FUNCTION(vsense_mode), - FUNCTION(blsp_spi7), - FUNCTION(blsp_uart6_a), - FUNCTION(blsp_uart6_b), - FUNCTION(sec_mi2s), - FUNCTION(sndwire_clk), - FUNCTION(phase_flag17), - FUNCTION(vsense_clkout), - FUNCTION(sndwire_data), - FUNCTION(phase_flag18), - FUNCTION(WSA_SPKR), - FUNCTION(blsp_i2c7), - FUNCTION(phase_flag19), - FUNCTION(vfr_1), - FUNCTION(phase_flag20), - FUNCTION(NFC_INT), - FUNCTION(blsp_spi8_cs1), - FUNCTION(blsp_spi8_cs2), - FUNCTION(m_voc), - FUNCTION(phase_flag21), - FUNCTION(NFC_EN), - FUNCTION(phase_flag22), - FUNCTION(NFC_DWL), - FUNCTION(blsp_i2c8_a), - FUNCTION(blsp_i2c8_b), - FUNCTION(phase_flag23), - FUNCTION(NFC_ESE), - FUNCTION(pwr_modem), - FUNCTION(phase_flag24), - FUNCTION(qdss_gpio), - FUNCTION(cam_mclk), - FUNCTION(pwr_nav), - FUNCTION(qdss_gpio0), - FUNCTION(qspi_data0), - FUNCTION(pwr_crypto), - FUNCTION(qdss_gpio1), - FUNCTION(qspi_data1), - FUNCTION(agera_pll), - FUNCTION(qdss_gpio2), - FUNCTION(qspi_data2), - FUNCTION(jitter_bist), - FUNCTION(qdss_gpio3), - FUNCTION(qdss_gpio7), - FUNCTION(FL_R3LED), - FUNCTION(CCI_TIMER0), - FUNCTION(FL_STROBE), - FUNCTION(CCI_TIMER1), - FUNCTION(CAM_LDO1), - FUNCTION(mdss_vsync0), - FUNCTION(mdss_vsync1), - FUNCTION(mdss_vsync2), - FUNCTION(mdss_vsync3), - FUNCTION(qdss_gpio9), - FUNCTION(CAM_IRQ), - FUNCTION(atest_usb2), - FUNCTION(cci_i2c), - FUNCTION(pll_bypassnl), - FUNCTION(atest_tsens), - FUNCTION(atest_usb21), - FUNCTION(pll_reset), - FUNCTION(atest_usb23), - FUNCTION(qdss_gpio6), - FUNCTION(CCI_TIMER3), - FUNCTION(CCI_ASYNC), - FUNCTION(qspi_cs), - FUNCTION(qdss_gpio10), - FUNCTION(CAM3_STANDBY), - FUNCTION(CCI_TIMER4), - FUNCTION(qdss_gpio11), - FUNCTION(CAM_LDO2), - FUNCTION(cci_async), - FUNCTION(qdss_gpio12), - FUNCTION(CAM0_RST), - FUNCTION(qdss_gpio13), - FUNCTION(CAM1_RST), - FUNCTION(qspi_clk), - FUNCTION(phase_flag30), - FUNCTION(qdss_gpio14), - FUNCTION(qspi_resetn), - FUNCTION(phase_flag1), - FUNCTION(qdss_gpio15), - FUNCTION(CAM0_STANDBY), - FUNCTION(phase_flag2), - FUNCTION(CAM1_STANDBY), - FUNCTION(phase_flag9), - FUNCTION(CAM2_STANDBY), - FUNCTION(qspi_data3), - FUNCTION(phase_flag15), - FUNCTION(qdss_gpio8), - FUNCTION(CAM3_RST), - FUNCTION(CCI_TIMER2), - FUNCTION(phase_flag16), - FUNCTION(LCD0_RESET), - FUNCTION(phase_flag6), - FUNCTION(SD_CARD), - FUNCTION(phase_flag29), - FUNCTION(DP_EN), - FUNCTION(phase_flag25), - FUNCTION(USBC_ORIENTATION), - FUNCTION(phase_flag10), - FUNCTION(atest_usb20), - FUNCTION(gcc_gp1), - FUNCTION(phase_flag4), - FUNCTION(atest_usb22), - FUNCTION(USB_PHY), - FUNCTION(gcc_gp2), - FUNCTION(atest_char), - FUNCTION(mdp_vsync), - FUNCTION(gcc_gp3), - FUNCTION(atest_char3), - FUNCTION(FORCE_TOUCH), - FUNCTION(cri_trng0), - FUNCTION(atest_char2), - FUNCTION(cri_trng1), - FUNCTION(atest_char1), - FUNCTION(AUDIO_USBC), - FUNCTION(audio_ref), - FUNCTION(MDP_VSYNC), - FUNCTION(cri_trng), - FUNCTION(atest_char0), - FUNCTION(US_EURO), - FUNCTION(LCD_BACKLIGHT), - FUNCTION(blsp_spi8_a), - FUNCTION(blsp_spi8_b), - FUNCTION(sp_cmu), - FUNCTION(nav_pps_a), - FUNCTION(nav_pps_b), - FUNCTION(nav_pps_c), - FUNCTION(gps_tx_a), - FUNCTION(gps_tx_b), - FUNCTION(gps_tx_c), - FUNCTION(adsp_ext), - FUNCTION(TS_RESET), - FUNCTION(ssc_irq), - FUNCTION(isense_dbg), - FUNCTION(phase_flag0), - FUNCTION(phase_flag7), - FUNCTION(phase_flag8), - FUNCTION(tsense_pwm1), - FUNCTION(tsense_pwm2), - FUNCTION(SENSOR_RST), - FUNCTION(WMSS_RESETN), - FUNCTION(HAPTICS_PWM), - FUNCTION(GPS_eLNA), - FUNCTION(mss_lte), - FUNCTION(uim2_data), - FUNCTION(uim2_clk), - FUNCTION(uim2_reset), - FUNCTION(uim2_present), - FUNCTION(uim1_data), - FUNCTION(uim1_clk), - FUNCTION(uim1_reset), - FUNCTION(uim1_present), - FUNCTION(uim_batt), - FUNCTION(pa_indicator), - FUNCTION(ldo_en), - FUNCTION(ldo_update), - FUNCTION(qlink_request), - FUNCTION(qlink_enable), - FUNCTION(prng_rosc), - FUNCTION(LCD_PWR), -}; - -static const struct msm_pingroup msmfalcon_groups[] = { - PINGROUP(0, SOUTH, blsp_spi1, blsp_uart1, blsp_uim1, tgu_ch0, NA, NA, - qdss_gpio4, atest_gpsadc1, NA), - PINGROUP(1, SOUTH, blsp_spi1, blsp_uart1, blsp_uim1, tgu_ch1, NA, NA, - qdss_gpio5, atest_gpsadc0, NA), - PINGROUP(2, SOUTH, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA, - NA, NA), - PINGROUP(3, SOUTH, blsp_spi1, blsp_uart1, blsp_i2c1, ddr_bist, NA, NA, - atest_tsens2, atest_usb1, NA), - PINGROUP(4, NORTH, blsp_spi2, blsp_uim2, blsp_uart2, phase_flag3, NA, - NA, NA, NA, NA), - PINGROUP(5, SOUTH, blsp_spi2, blsp_uim2, blsp_uart2, phase_flag14, NA, - NA, NA, NA, NA), - PINGROUP(6, SOUTH, blsp_spi2, blsp_i2c2, blsp_uart2, phase_flag31, NA, - NA, NA, NA, NA), - PINGROUP(7, SOUTH, blsp_spi2, blsp_i2c2, blsp_uart2, NA, NA, NA, NA, - NA, NA), - PINGROUP(8, NORTH, blsp_spi3, ddr_bist, NA, NA, NA, wlan1_adc1, - atest_usb13, bimc_dte1, NA), - PINGROUP(9, NORTH, blsp_spi3, ddr_bist, NA, NA, NA, wlan1_adc0, - atest_usb12, bimc_dte0, NA), - PINGROUP(10, NORTH, blsp_spi3, blsp_i2c3, ddr_bist, NA, NA, wlan2_adc1, - atest_usb11, bimc_dte1, NA), - PINGROUP(11, NORTH, blsp_spi3, blsp_i2c3, NA, dbg_out, wlan2_adc0, - atest_usb10, bimc_dte0, NA, NA), - PINGROUP(12, NORTH, blsp_spi4, pri_mi2s, NA, phase_flag26, qdss_cti1_b, - NA, NA, NA, NA), - PINGROUP(13, NORTH, blsp_spi4, DP_HOT, pri_mi2s_ws, NA, NA, - phase_flag27, qdss_cti0_b, NA, NA), - PINGROUP(14, NORTH, blsp_spi4, blsp_i2c4, pri_mi2s, NA, phase_flag28, - NA, NA, NA, NA), - PINGROUP(15, NORTH, blsp_spi4, blsp_i2c4, pri_mi2s, NA, NA, NA, NA, NA, - NA), - PINGROUP(16, CENTER, blsp_uart5, blsp_spi5, blsp_uim5, NA, NA, NA, NA, - NA, NA), - PINGROUP(17, CENTER, blsp_uart5, blsp_spi5, blsp_uim5, NA, phase_flag5, - NA, NA, NA, NA), - PINGROUP(18, CENTER, blsp_uart5, blsp_spi5, blsp_i2c5, NA, NA, NA, NA, - NA, NA), - PINGROUP(19, CENTER, blsp_uart5, blsp_spi5, blsp_i2c5, NA, NA, NA, NA, - NA, NA), - PINGROUP(20, SOUTH, NA, NA, blsp_uim6, NA, NA, NA, NA, - NA, NA), - PINGROUP(21, SOUTH, NA, NA, blsp_uim6, NA, phase_flag11, - qdss_cti0_b, vsense_data0, NA, NA), - PINGROUP(22, CENTER, blsp_spi6, NA, blsp_i2c6, NA, - phase_flag12, vsense_data1, NA, NA, NA), - PINGROUP(23, CENTER, blsp_spi6, NA, blsp_i2c6, NA, - phase_flag13, vsense_mode, NA, NA, NA), - PINGROUP(24, NORTH, blsp_spi7, blsp_uart6_a, sec_mi2s, sndwire_clk, NA, - NA, phase_flag17, vsense_clkout, NA), - PINGROUP(25, NORTH, blsp_spi7, blsp_uart6_a, sec_mi2s, sndwire_data, NA, - NA, phase_flag18, NA, NA), - PINGROUP(26, NORTH, blsp_spi7, blsp_uart6_a, blsp_i2c7, sec_mi2s, NA, - phase_flag19, NA, NA, NA), - PINGROUP(27, NORTH, blsp_spi7, blsp_uart6_a, blsp_i2c7, vfr_1, sec_mi2s, - NA, phase_flag20, NA, NA), - PINGROUP(28, CENTER, blsp_spi8_a, blsp_uart6_b, m_voc, NA, phase_flag21, - NA, NA, NA, NA), - PINGROUP(29, CENTER, blsp_spi8_a, blsp_uart6_b, NA, NA, phase_flag22, - NA, NA, NA, NA), - PINGROUP(30, CENTER, blsp_spi8_a, blsp_uart6_b, blsp_i2c8_a, - blsp_spi3_cs1, NA, phase_flag23, NA, NA, NA), - PINGROUP(31, CENTER, blsp_spi8_a, blsp_uart6_b, blsp_i2c8_a, pwr_modem, - NA, phase_flag24, qdss_gpio, NA, NA), - PINGROUP(32, SOUTH, cam_mclk, pwr_nav, NA, NA, qdss_gpio0, NA, NA, NA, - NA), - PINGROUP(33, SOUTH, cam_mclk, qspi_data0, pwr_crypto, NA, NA, - qdss_gpio1, NA, NA, NA), - PINGROUP(34, SOUTH, cam_mclk, qspi_data1, agera_pll, NA, NA, - qdss_gpio2, NA, NA, NA), - PINGROUP(35, SOUTH, cam_mclk, qspi_data2, jitter_bist, NA, NA, - qdss_gpio3, NA, atest_usb2, NA), - PINGROUP(36, SOUTH, cci_i2c, pll_bypassnl, agera_pll, NA, NA, - qdss_gpio4, atest_tsens, atest_usb21, NA), - PINGROUP(37, SOUTH, cci_i2c, pll_reset, NA, NA, qdss_gpio5, - atest_usb23, NA, NA, NA), - PINGROUP(38, SOUTH, cci_i2c, NA, NA, qdss_gpio6, NA, NA, NA, NA, NA), - PINGROUP(39, SOUTH, cci_i2c, NA, NA, qdss_gpio7, NA, NA, NA, NA, NA), - PINGROUP(40, SOUTH, CCI_TIMER0, NA, blsp_spi8_b, NA, NA, NA, NA, NA, - NA), - PINGROUP(41, SOUTH, CCI_TIMER1, NA, blsp_spi8_b, NA, NA, NA, NA, NA, - NA), - PINGROUP(42, SOUTH, mdss_vsync0, mdss_vsync1, mdss_vsync2, mdss_vsync3, - NA, NA, qdss_gpio9, NA, NA), - PINGROUP(43, SOUTH, CCI_TIMER3, CCI_ASYNC, qspi_cs, NA, NA, - qdss_gpio10, NA, NA, NA), - PINGROUP(44, SOUTH, CCI_TIMER4, CCI_ASYNC, blsp_spi8_b, blsp_i2c8_b, NA, - NA, qdss_gpio11, NA, NA), - PINGROUP(45, SOUTH, cci_async, NA, NA, qdss_gpio12, NA, NA, NA, NA, NA), - PINGROUP(46, SOUTH, blsp_spi1, NA, NA, qdss_gpio13, NA, NA, NA, NA, NA), - PINGROUP(47, SOUTH, qspi_clk, NA, phase_flag30, qdss_gpio14, NA, NA, - NA, NA, NA), - PINGROUP(48, SOUTH, NA, phase_flag1, qdss_gpio15, NA, NA, NA, NA, NA, - NA), - PINGROUP(49, SOUTH, blsp_spi6, phase_flag2, qdss_cti0_a, NA, NA, NA, - NA, NA, NA), - PINGROUP(50, SOUTH, qspi_cs, NA, phase_flag9, qdss_cti0_a, NA, NA, NA, - NA, NA), - PINGROUP(51, SOUTH, qspi_data3, NA, phase_flag15, qdss_gpio8, NA, NA, - NA, NA, NA), - PINGROUP(52, SOUTH, CCI_TIMER2, blsp_spi8_b, blsp_i2c8_b, blsp_spi6, - phase_flag16, qdss_gpio, NA, NA, NA), - PINGROUP(53, NORTH, NA, phase_flag6, qdss_cti1_a, NA, NA, NA, NA, NA, - NA), - PINGROUP(54, NORTH, NA, NA, phase_flag29, NA, NA, NA, NA, NA, NA), - PINGROUP(55, SOUTH, NA, phase_flag25, qdss_cti1_a, NA, NA, NA, NA, NA, - NA), - PINGROUP(56, SOUTH, NA, phase_flag10, qdss_gpio3, NA, atest_usb20, NA, - NA, NA, NA), - PINGROUP(57, SOUTH, gcc_gp1, NA, phase_flag4, atest_usb22, NA, NA, NA, - NA, NA), - PINGROUP(58, SOUTH, USB_PHY, gcc_gp2, NA, NA, atest_char, NA, NA, NA, - NA), - PINGROUP(59, NORTH, mdp_vsync, gcc_gp3, NA, NA, atest_char3, NA, NA, - NA, NA), - PINGROUP(60, NORTH, cri_trng0, NA, NA, atest_char2, NA, NA, NA, NA, NA), - PINGROUP(61, NORTH, pri_mi2s, cri_trng1, NA, NA, atest_char1, NA, NA, - NA, NA), - PINGROUP(62, NORTH, sec_mi2s, audio_ref, MDP_VSYNC, cri_trng, NA, NA, - atest_char0, NA, NA), - PINGROUP(63, NORTH, NA, NA, NA, qdss_gpio1, NA, NA, NA, NA, NA), - PINGROUP(64, SOUTH, blsp_spi8_cs1, sp_cmu, NA, NA, qdss_gpio2, NA, NA, - NA, NA), - PINGROUP(65, SOUTH, NA, nav_pps_a, nav_pps_a, gps_tx_a, blsp_spi3_cs2, - adsp_ext, NA, NA, NA), - PINGROUP(66, NORTH, NA, NA, qdss_cti1_b, NA, NA, NA, NA, NA, NA), - PINGROUP(67, NORTH, NA, NA, qdss_gpio0, NA, NA, NA, NA, NA, NA), - PINGROUP(68, NORTH, isense_dbg, NA, phase_flag0, qdss_gpio, NA, NA, NA, - NA, NA), - PINGROUP(69, NORTH, NA, phase_flag7, qdss_gpio, NA, NA, NA, NA, NA, NA), - PINGROUP(70, NORTH, NA, phase_flag8, qdss_gpio6, NA, NA, NA, NA, NA, - NA), - PINGROUP(71, NORTH, NA, NA, qdss_gpio7, tsense_pwm1, tsense_pwm2, NA, - NA, NA, NA), - PINGROUP(72, NORTH, NA, qdss_gpio14, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(73, NORTH, NA, NA, qdss_gpio15, NA, NA, NA, NA, NA, NA), - PINGROUP(74, NORTH, mdp_vsync, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(75, NORTH, NA, NA, qdss_gpio8, NA, NA, NA, NA, NA, NA), - PINGROUP(76, NORTH, blsp_spi8_cs2, NA, NA, NA, qdss_gpio9, NA, NA, NA, - NA), - PINGROUP(77, NORTH, NA, NA, qdss_gpio10, NA, NA, NA, NA, NA, NA), - PINGROUP(78, NORTH, gcc_gp1, NA, qdss_gpio13, NA, NA, NA, NA, NA, NA), - PINGROUP(79, SOUTH, NA, NA, qdss_gpio11, NA, NA, NA, NA, NA, NA), - PINGROUP(80, SOUTH, nav_pps_b, nav_pps_b, gps_tx_c, NA, NA, qdss_gpio12, - NA, NA, NA), - PINGROUP(81, CENTER, mss_lte, gcc_gp2, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(82, CENTER, mss_lte, gcc_gp3, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(83, SOUTH, uim2_data, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(84, SOUTH, uim2_clk, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(85, SOUTH, uim2_reset, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(86, SOUTH, uim2_present, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(87, SOUTH, uim1_data, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(88, SOUTH, uim1_clk, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(89, SOUTH, uim1_reset, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(90, SOUTH, uim1_present, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(91, SOUTH, uim_batt, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(92, SOUTH, NA, NA, pa_indicator, NA, NA, NA, NA, NA, NA), - PINGROUP(93, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(94, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(95, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(96, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(97, SOUTH, NA, ldo_en, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(98, SOUTH, NA, nav_pps_c, nav_pps_c, gps_tx_b, ldo_update, NA, - NA, NA, NA), - PINGROUP(99, SOUTH, qlink_request, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(100, SOUTH, qlink_enable, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(101, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(102, SOUTH, NA, prng_rosc, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(103, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(104, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(105, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(106, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(107, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(108, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(109, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(110, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(111, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(112, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - PINGROUP(113, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), - SDC_QDSD_PINGROUP(sdc1_clk, 0x99a000, 13, 6), - SDC_QDSD_PINGROUP(sdc1_cmd, 0x99a000, 11, 3), - SDC_QDSD_PINGROUP(sdc1_data, 0x99a000, 9, 0), - SDC_QDSD_PINGROUP(sdc2_clk, 0x99b000, 14, 6), - SDC_QDSD_PINGROUP(sdc2_cmd, 0x99b000, 11, 3), - SDC_QDSD_PINGROUP(sdc2_data, 0x99b000, 9, 0), - SDC_QDSD_PINGROUP(sdc1_rclk, 0x99a000, 15, 0), -}; - -static const struct msm_pinctrl_soc_data msmfalcon_pinctrl = { - .pins = msmfalcon_pins, - .npins = ARRAY_SIZE(msmfalcon_pins), - .functions = msmfalcon_functions, - .nfunctions = ARRAY_SIZE(msmfalcon_functions), - .groups = msmfalcon_groups, - .ngroups = ARRAY_SIZE(msmfalcon_groups), - .ngpios = 114, -}; - -static int msmfalcon_pinctrl_probe(struct platform_device *pdev) -{ - return msm_pinctrl_probe(pdev, &msmfalcon_pinctrl); -} - -static const struct of_device_id msmfalcon_pinctrl_of_match[] = { - { .compatible = "qcom,msmfalcon-pinctrl", }, - { }, -}; - -static struct platform_driver msmfalcon_pinctrl_driver = { - .driver = { - .name = "msmfalcon-pinctrl", - .owner = THIS_MODULE, - .of_match_table = msmfalcon_pinctrl_of_match, - }, - .probe = msmfalcon_pinctrl_probe, - .remove = msm_pinctrl_remove, -}; - -static int __init msmfalcon_pinctrl_init(void) -{ - return platform_driver_register(&msmfalcon_pinctrl_driver); -} -arch_initcall(msmfalcon_pinctrl_init); - -static void __exit msmfalcon_pinctrl_exit(void) -{ - platform_driver_unregister(&msmfalcon_pinctrl_driver); -} -module_exit(msmfalcon_pinctrl_exit); - -MODULE_DESCRIPTION("QTI msmfalcon pinctrl driver"); -MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msmfalcon_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660.c b/drivers/pinctrl/qcom/pinctrl-sdm660.c new file mode 100644 index 000000000000..4dbb4cae2fae --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sdm660.c @@ -0,0 +1,1722 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define NORTH 0x00900000 +#define CENTER 0x00500000 +#define SOUTH 0x00100000 +#define REG_SIZE 0x1000 +#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned)ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = base + REG_SIZE * id, \ + .io_reg = base + 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \ + .intr_status_reg = base + 0xc + REG_SIZE * id, \ + .intr_target_reg = base + 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc sdm660_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "SDC1_CLK"), + PINCTRL_PIN(115, "SDC1_CMD"), + PINCTRL_PIN(116, "SDC1_DATA"), + PINCTRL_PIN(117, "SDC2_CLK"), + PINCTRL_PIN(118, "SDC2_CMD"), + PINCTRL_PIN(119, "SDC2_DATA"), + PINCTRL_PIN(120, "SDC1_RCLK"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); + +static const unsigned int sdc1_clk_pins[] = { 114 }; +static const unsigned int sdc1_cmd_pins[] = { 115 }; +static const unsigned int sdc1_data_pins[] = { 116 }; +static const unsigned int sdc2_clk_pins[] = { 117 }; +static const unsigned int sdc2_cmd_pins[] = { 118 }; +static const unsigned int sdc2_data_pins[] = { 119 }; +static const unsigned int sdc1_rclk_pins[] = { 120 }; + +enum sdm660_functions { + msm_mux_blsp_spi1, + msm_mux_gpio, + msm_mux_blsp_uim1, + msm_mux_tgu_ch0, + msm_mux_qdss_gpio4, + msm_mux_atest_gpsadc1, + msm_mux_blsp_uart1, + msm_mux_SMB_STAT, + msm_mux_phase_flag14, + msm_mux_blsp_i2c2, + msm_mux_phase_flag31, + msm_mux_blsp_spi3, + msm_mux_blsp_spi3_cs1, + msm_mux_blsp_spi3_cs2, + msm_mux_wlan1_adc1, + msm_mux_atest_usb13, + msm_mux_tgu_ch1, + msm_mux_qdss_gpio5, + msm_mux_atest_gpsadc0, + msm_mux_blsp_i2c1, + msm_mux_ddr_bist, + msm_mux_atest_tsens2, + msm_mux_atest_usb1, + msm_mux_blsp_spi2, + msm_mux_blsp_uim2, + msm_mux_phase_flag3, + msm_mux_bimc_dte1, + msm_mux_wlan1_adc0, + msm_mux_atest_usb12, + msm_mux_bimc_dte0, + msm_mux_blsp_i2c3, + msm_mux_wlan2_adc1, + msm_mux_atest_usb11, + msm_mux_dbg_out, + msm_mux_wlan2_adc0, + msm_mux_atest_usb10, + msm_mux_RCM_MARKER, + msm_mux_blsp_spi4, + msm_mux_pri_mi2s, + msm_mux_phase_flag26, + msm_mux_qdss_cti0_a, + msm_mux_qdss_cti0_b, + msm_mux_qdss_cti1_a, + msm_mux_qdss_cti1_b, + msm_mux_DP_HOT, + msm_mux_pri_mi2s_ws, + msm_mux_phase_flag27, + msm_mux_blsp_i2c4, + msm_mux_phase_flag28, + msm_mux_blsp_uart5, + msm_mux_blsp_spi5, + msm_mux_blsp_uim5, + msm_mux_phase_flag5, + msm_mux_blsp_i2c5, + msm_mux_blsp_spi6, + msm_mux_blsp_uart2, + msm_mux_blsp_uim6, + msm_mux_phase_flag11, + msm_mux_vsense_data0, + msm_mux_blsp_i2c6, + msm_mux_phase_flag12, + msm_mux_vsense_data1, + msm_mux_phase_flag13, + msm_mux_vsense_mode, + msm_mux_blsp_spi7, + msm_mux_blsp_uart6_a, + msm_mux_blsp_uart6_b, + msm_mux_sec_mi2s, + msm_mux_sndwire_clk, + msm_mux_phase_flag17, + msm_mux_vsense_clkout, + msm_mux_sndwire_data, + msm_mux_phase_flag18, + msm_mux_WSA_SPKR, + msm_mux_blsp_i2c7, + msm_mux_phase_flag19, + msm_mux_vfr_1, + msm_mux_phase_flag20, + msm_mux_NFC_INT, + msm_mux_blsp_spi8_cs1, + msm_mux_blsp_spi8_cs2, + msm_mux_m_voc, + msm_mux_phase_flag21, + msm_mux_NFC_EN, + msm_mux_phase_flag22, + msm_mux_NFC_DWL, + msm_mux_blsp_i2c8_a, + msm_mux_blsp_i2c8_b, + msm_mux_phase_flag23, + msm_mux_NFC_ESE, + msm_mux_pwr_modem, + msm_mux_phase_flag24, + msm_mux_qdss_gpio, + msm_mux_cam_mclk, + msm_mux_pwr_nav, + msm_mux_qdss_gpio0, + msm_mux_qspi_data0, + msm_mux_pwr_crypto, + msm_mux_qdss_gpio1, + msm_mux_qspi_data1, + msm_mux_agera_pll, + msm_mux_qdss_gpio2, + msm_mux_qspi_data2, + msm_mux_jitter_bist, + msm_mux_qdss_gpio3, + msm_mux_qdss_gpio7, + msm_mux_FL_R3LED, + msm_mux_CCI_TIMER0, + msm_mux_FL_STROBE, + msm_mux_CCI_TIMER1, + msm_mux_CAM_LDO1, + msm_mux_mdss_vsync0, + msm_mux_mdss_vsync1, + msm_mux_mdss_vsync2, + msm_mux_mdss_vsync3, + msm_mux_qdss_gpio9, + msm_mux_CAM_IRQ, + msm_mux_atest_usb2, + msm_mux_cci_i2c, + msm_mux_pll_bypassnl, + msm_mux_atest_tsens, + msm_mux_atest_usb21, + msm_mux_pll_reset, + msm_mux_atest_usb23, + msm_mux_qdss_gpio6, + msm_mux_CCI_TIMER3, + msm_mux_CCI_ASYNC, + msm_mux_qspi_cs, + msm_mux_qdss_gpio10, + msm_mux_CAM3_STANDBY, + msm_mux_CCI_TIMER4, + msm_mux_qdss_gpio11, + msm_mux_CAM_LDO2, + msm_mux_cci_async, + msm_mux_qdss_gpio12, + msm_mux_CAM0_RST, + msm_mux_qdss_gpio13, + msm_mux_CAM1_RST, + msm_mux_qspi_clk, + msm_mux_phase_flag30, + msm_mux_qdss_gpio14, + msm_mux_qspi_resetn, + msm_mux_phase_flag1, + msm_mux_qdss_gpio15, + msm_mux_CAM0_STANDBY, + msm_mux_phase_flag2, + msm_mux_CAM1_STANDBY, + msm_mux_phase_flag9, + msm_mux_CAM2_STANDBY, + msm_mux_qspi_data3, + msm_mux_phase_flag15, + msm_mux_qdss_gpio8, + msm_mux_CAM3_RST, + msm_mux_CCI_TIMER2, + msm_mux_phase_flag16, + msm_mux_LCD0_RESET, + msm_mux_phase_flag6, + msm_mux_SD_CARD, + msm_mux_phase_flag29, + msm_mux_DP_EN, + msm_mux_phase_flag25, + msm_mux_USBC_ORIENTATION, + msm_mux_phase_flag10, + msm_mux_atest_usb20, + msm_mux_gcc_gp1, + msm_mux_phase_flag4, + msm_mux_atest_usb22, + msm_mux_USB_PHY, + msm_mux_gcc_gp2, + msm_mux_atest_char, + msm_mux_mdp_vsync, + msm_mux_gcc_gp3, + msm_mux_atest_char3, + msm_mux_FORCE_TOUCH, + msm_mux_cri_trng0, + msm_mux_atest_char2, + msm_mux_cri_trng1, + msm_mux_atest_char1, + msm_mux_AUDIO_USBC, + msm_mux_audio_ref, + msm_mux_MDP_VSYNC, + msm_mux_cri_trng, + msm_mux_atest_char0, + msm_mux_US_EURO, + msm_mux_LCD_BACKLIGHT, + msm_mux_blsp_spi8_a, + msm_mux_blsp_spi8_b, + msm_mux_sp_cmu, + msm_mux_nav_pps_a, + msm_mux_nav_pps_b, + msm_mux_nav_pps_c, + msm_mux_gps_tx_a, + msm_mux_gps_tx_b, + msm_mux_gps_tx_c, + msm_mux_adsp_ext, + msm_mux_TS_RESET, + msm_mux_ssc_irq, + msm_mux_isense_dbg, + msm_mux_phase_flag0, + msm_mux_phase_flag7, + msm_mux_phase_flag8, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_SENSOR_RST, + msm_mux_WMSS_RESETN, + msm_mux_HAPTICS_PWM, + msm_mux_GPS_eLNA, + msm_mux_mss_lte, + msm_mux_uim2_data, + msm_mux_uim2_clk, + msm_mux_uim2_reset, + msm_mux_uim2_present, + msm_mux_uim1_data, + msm_mux_uim1_clk, + msm_mux_uim1_reset, + msm_mux_uim1_present, + msm_mux_uim_batt, + msm_mux_pa_indicator, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_qlink_request, + msm_mux_qlink_enable, + msm_mux_prng_rosc, + msm_mux_LCD_PWR, + msm_mux_NA, +}; + +static const char * const blsp_spi1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio46", +}; +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", +}; +static const char * const blsp_uim1_groups[] = { + "gpio0", "gpio1", +}; +static const char * const tgu_ch0_groups[] = { + "gpio0", +}; +static const char * const qdss_gpio4_groups[] = { + "gpio0", "gpio36", +}; +static const char * const atest_gpsadc1_groups[] = { + "gpio0", +}; +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const SMB_STAT_groups[] = { + "gpio5", +}; +static const char * const phase_flag14_groups[] = { + "gpio5", +}; +static const char * const blsp_i2c2_groups[] = { + "gpio6", "gpio7", +}; +static const char * const phase_flag31_groups[] = { + "gpio6", +}; +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const blsp_spi3_cs1_groups[] = { + "gpio30", +}; +static const char * const blsp_spi3_cs2_groups[] = { + "gpio65", +}; +static const char * const wlan1_adc1_groups[] = { + "gpio8", +}; +static const char * const atest_usb13_groups[] = { + "gpio8", +}; +static const char * const tgu_ch1_groups[] = { + "gpio1", +}; +static const char * const qdss_gpio5_groups[] = { + "gpio1", "gpio37", +}; +static const char * const atest_gpsadc0_groups[] = { + "gpio1", +}; +static const char * const blsp_i2c1_groups[] = { + "gpio2", "gpio3", +}; +static const char * const ddr_bist_groups[] = { + "gpio3", "gpio8", "gpio9", "gpio10", +}; +static const char * const atest_tsens2_groups[] = { + "gpio3", +}; +static const char * const atest_usb1_groups[] = { + "gpio3", +}; +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const blsp_uim2_groups[] = { + "gpio4", "gpio5", +}; +static const char * const phase_flag3_groups[] = { + "gpio4", +}; +static const char * const bimc_dte1_groups[] = { + "gpio8", "gpio10", +}; +static const char * const wlan1_adc0_groups[] = { + "gpio9", +}; +static const char * const atest_usb12_groups[] = { + "gpio9", +}; +static const char * const bimc_dte0_groups[] = { + "gpio9", "gpio11", +}; +static const char * const blsp_i2c3_groups[] = { + "gpio10", "gpio11", +}; +static const char * const wlan2_adc1_groups[] = { + "gpio10", +}; +static const char * const atest_usb11_groups[] = { + "gpio10", +}; +static const char * const dbg_out_groups[] = { + "gpio11", +}; +static const char * const wlan2_adc0_groups[] = { + "gpio11", +}; +static const char * const atest_usb10_groups[] = { + "gpio11", +}; +static const char * const RCM_MARKER_groups[] = { + "gpio12", "gpio13", +}; +static const char * const blsp_spi4_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; +static const char * const pri_mi2s_groups[] = { + "gpio12", "gpio14", "gpio15", "gpio61", +}; +static const char * const phase_flag26_groups[] = { + "gpio12", +}; +static const char * const qdss_cti0_a_groups[] = { + "gpio49", "gpio50", +}; +static const char * const qdss_cti0_b_groups[] = { + "gpio13", "gpio21", +}; +static const char * const qdss_cti1_a_groups[] = { + "gpio53", "gpio55", +}; +static const char * const qdss_cti1_b_groups[] = { + "gpio12", "gpio66", +}; +static const char * const DP_HOT_groups[] = { + "gpio13", +}; +static const char * const pri_mi2s_ws_groups[] = { + "gpio13", +}; +static const char * const phase_flag27_groups[] = { + "gpio13", +}; +static const char * const blsp_i2c4_groups[] = { + "gpio14", "gpio15", +}; +static const char * const phase_flag28_groups[] = { + "gpio14", +}; +static const char * const blsp_uart5_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char * const blsp_spi5_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char * const blsp_uim5_groups[] = { + "gpio16", "gpio17", +}; +static const char * const phase_flag5_groups[] = { + "gpio17", +}; +static const char * const blsp_i2c5_groups[] = { + "gpio18", "gpio19", +}; +static const char * const blsp_spi6_groups[] = { + "gpio49", "gpio52", "gpio22", "gpio23", +}; +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const blsp_uim6_groups[] = { + "gpio20", "gpio21", +}; +static const char * const phase_flag11_groups[] = { + "gpio21", +}; +static const char * const vsense_data0_groups[] = { + "gpio21", +}; +static const char * const blsp_i2c6_groups[] = { + "gpio22", "gpio23", +}; +static const char * const phase_flag12_groups[] = { + "gpio22", +}; +static const char * const vsense_data1_groups[] = { + "gpio22", +}; +static const char * const phase_flag13_groups[] = { + "gpio23", +}; +static const char * const vsense_mode_groups[] = { + "gpio23", +}; +static const char * const blsp_spi7_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; +static const char * const blsp_uart6_a_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; +static const char * const blsp_uart6_b_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", +}; +static const char * const sec_mi2s_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", "gpio62", +}; +static const char * const sndwire_clk_groups[] = { + "gpio24", +}; +static const char * const phase_flag17_groups[] = { + "gpio24", +}; +static const char * const vsense_clkout_groups[] = { + "gpio24", +}; +static const char * const sndwire_data_groups[] = { + "gpio25", +}; +static const char * const phase_flag18_groups[] = { + "gpio25", +}; +static const char * const WSA_SPKR_groups[] = { + "gpio26", "gpio27", +}; +static const char * const blsp_i2c7_groups[] = { + "gpio26", "gpio27", +}; +static const char * const phase_flag19_groups[] = { + "gpio26", +}; +static const char * const vfr_1_groups[] = { + "gpio27", +}; +static const char * const phase_flag20_groups[] = { + "gpio27", +}; +static const char * const NFC_INT_groups[] = { + "gpio28", +}; +static const char * const blsp_spi8_a_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", +}; +static const char * const blsp_spi8_b_groups[] = { + "gpio40", "gpio41", "gpio44", "gpio52", +}; +static const char * const m_voc_groups[] = { + "gpio28", +}; +static const char * const phase_flag21_groups[] = { + "gpio28", +}; +static const char * const NFC_EN_groups[] = { + "gpio29", +}; +static const char * const phase_flag22_groups[] = { + "gpio29", +}; +static const char * const NFC_DWL_groups[] = { + "gpio30", +}; +static const char * const blsp_i2c8_a_groups[] = { + "gpio30", "gpio31", +}; +static const char * const blsp_i2c8_b_groups[] = { + "gpio44", "gpio52", +}; +static const char * const phase_flag23_groups[] = { + "gpio30", +}; +static const char * const NFC_ESE_groups[] = { + "gpio31", +}; +static const char * const pwr_modem_groups[] = { + "gpio31", +}; +static const char * const phase_flag24_groups[] = { + "gpio31", +}; +static const char * const qdss_gpio_groups[] = { + "gpio31", "gpio52", "gpio68", "gpio69", +}; +static const char * const cam_mclk_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; +static const char * const pwr_nav_groups[] = { + "gpio32", +}; +static const char * const qdss_gpio0_groups[] = { + "gpio32", "gpio67", +}; +static const char * const qspi_data0_groups[] = { + "gpio33", +}; +static const char * const pwr_crypto_groups[] = { + "gpio33", +}; +static const char * const qdss_gpio1_groups[] = { + "gpio33", "gpio63", +}; +static const char * const qspi_data1_groups[] = { + "gpio34", +}; +static const char * const agera_pll_groups[] = { + "gpio34", "gpio36", +}; +static const char * const qdss_gpio2_groups[] = { + "gpio34", "gpio64", +}; +static const char * const qspi_data2_groups[] = { + "gpio35", +}; +static const char * const jitter_bist_groups[] = { + "gpio35", +}; +static const char * const qdss_gpio3_groups[] = { + "gpio35", "gpio56", +}; +static const char * const qdss_gpio7_groups[] = { + "gpio39", "gpio71", +}; +static const char * const FL_R3LED_groups[] = { + "gpio40", +}; +static const char * const CCI_TIMER0_groups[] = { + "gpio40", +}; +static const char * const FL_STROBE_groups[] = { + "gpio41", +}; +static const char * const CCI_TIMER1_groups[] = { + "gpio41", +}; +static const char * const CAM_LDO1_groups[] = { + "gpio42", +}; +static const char * const mdss_vsync0_groups[] = { + "gpio42", +}; +static const char * const mdss_vsync1_groups[] = { + "gpio42", +}; +static const char * const mdss_vsync2_groups[] = { + "gpio42", +}; +static const char * const mdss_vsync3_groups[] = { + "gpio42", +}; +static const char * const qdss_gpio9_groups[] = { + "gpio42", "gpio76", +}; +static const char * const CAM_IRQ_groups[] = { + "gpio43", +}; +static const char * const atest_usb2_groups[] = { + "gpio35", +}; +static const char * const cci_i2c_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio36", +}; +static const char * const atest_tsens_groups[] = { + "gpio36", +}; +static const char * const atest_usb21_groups[] = { + "gpio36", +}; +static const char * const pll_reset_groups[] = { + "gpio37", +}; +static const char * const atest_usb23_groups[] = { + "gpio37", +}; +static const char * const qdss_gpio6_groups[] = { + "gpio38", "gpio70", +}; +static const char * const CCI_TIMER3_groups[] = { + "gpio43", +}; +static const char * const CCI_ASYNC_groups[] = { + "gpio43", "gpio44", +}; +static const char * const qspi_cs_groups[] = { + "gpio43", "gpio50", +}; +static const char * const qdss_gpio10_groups[] = { + "gpio43", "gpio77", +}; +static const char * const CAM3_STANDBY_groups[] = { + "gpio44", +}; +static const char * const CCI_TIMER4_groups[] = { + "gpio44", +}; +static const char * const qdss_gpio11_groups[] = { + "gpio44", "gpio79", +}; +static const char * const CAM_LDO2_groups[] = { + "gpio45", +}; +static const char * const cci_async_groups[] = { + "gpio45", +}; +static const char * const qdss_gpio12_groups[] = { + "gpio45", "gpio80", +}; +static const char * const CAM0_RST_groups[] = { + "gpio46", +}; +static const char * const qdss_gpio13_groups[] = { + "gpio46", "gpio78", +}; +static const char * const CAM1_RST_groups[] = { + "gpio47", +}; +static const char * const qspi_clk_groups[] = { + "gpio47", +}; +static const char * const phase_flag30_groups[] = { + "gpio47", +}; +static const char * const qdss_gpio14_groups[] = { + "gpio47", "gpio72", +}; +static const char * const qspi_resetn_groups[] = { + "gpio48", +}; +static const char * const phase_flag1_groups[] = { + "gpio48", +}; +static const char * const qdss_gpio15_groups[] = { + "gpio48", "gpio73", +}; +static const char * const CAM0_STANDBY_groups[] = { + "gpio49", +}; +static const char * const phase_flag2_groups[] = { + "gpio49", +}; +static const char * const CAM1_STANDBY_groups[] = { + "gpio50", +}; +static const char * const phase_flag9_groups[] = { + "gpio50", +}; +static const char * const CAM2_STANDBY_groups[] = { + "gpio51", +}; +static const char * const qspi_data3_groups[] = { + "gpio51", +}; +static const char * const phase_flag15_groups[] = { + "gpio51", +}; +static const char * const qdss_gpio8_groups[] = { + "gpio51", "gpio75", +}; +static const char * const CAM3_RST_groups[] = { + "gpio52", +}; +static const char * const CCI_TIMER2_groups[] = { + "gpio52", +}; +static const char * const phase_flag16_groups[] = { + "gpio52", +}; +static const char * const LCD0_RESET_groups[] = { + "gpio53", +}; +static const char * const phase_flag6_groups[] = { + "gpio53", +}; +static const char * const SD_CARD_groups[] = { + "gpio54", +}; +static const char * const phase_flag29_groups[] = { + "gpio54", +}; +static const char * const DP_EN_groups[] = { + "gpio55", +}; +static const char * const phase_flag25_groups[] = { + "gpio55", +}; +static const char * const USBC_ORIENTATION_groups[] = { + "gpio56", +}; +static const char * const phase_flag10_groups[] = { + "gpio56", +}; +static const char * const atest_usb20_groups[] = { + "gpio56", +}; +static const char * const gcc_gp1_groups[] = { + "gpio57", "gpio78", +}; +static const char * const phase_flag4_groups[] = { + "gpio57", +}; +static const char * const atest_usb22_groups[] = { + "gpio57", +}; +static const char * const USB_PHY_groups[] = { + "gpio58", +}; +static const char * const gcc_gp2_groups[] = { + "gpio58", "gpio81", +}; +static const char * const atest_char_groups[] = { + "gpio58", +}; +static const char * const mdp_vsync_groups[] = { + "gpio59", "gpio74", +}; +static const char * const gcc_gp3_groups[] = { + "gpio59", "gpio82", +}; +static const char * const atest_char3_groups[] = { + "gpio59", +}; +static const char * const FORCE_TOUCH_groups[] = { + "gpio60", "gpio73", +}; +static const char * const cri_trng0_groups[] = { + "gpio60", +}; +static const char * const atest_char2_groups[] = { + "gpio60", +}; +static const char * const cri_trng1_groups[] = { + "gpio61", +}; +static const char * const atest_char1_groups[] = { + "gpio61", +}; +static const char * const AUDIO_USBC_groups[] = { + "gpio62", +}; +static const char * const audio_ref_groups[] = { + "gpio62", +}; +static const char * const MDP_VSYNC_groups[] = { + "gpio62", +}; +static const char * const cri_trng_groups[] = { + "gpio62", +}; +static const char * const atest_char0_groups[] = { + "gpio62", +}; +static const char * const US_EURO_groups[] = { + "gpio63", +}; +static const char * const LCD_BACKLIGHT_groups[] = { + "gpio64", +}; +static const char * const blsp_spi8_cs1_groups[] = { + "gpio64", +}; +static const char * const blsp_spi8_cs2_groups[] = { + "gpio76", +}; +static const char * const sp_cmu_groups[] = { + "gpio64", +}; +static const char * const nav_pps_a_groups[] = { + "gpio65", +}; +static const char * const nav_pps_b_groups[] = { + "gpio98", +}; +static const char * const nav_pps_c_groups[] = { + "gpio80", +}; +static const char * const gps_tx_a_groups[] = { + "gpio65", +}; +static const char * const gps_tx_b_groups[] = { + "gpio98", +}; +static const char * const gps_tx_c_groups[] = { + "gpio80", +}; +static const char * const adsp_ext_groups[] = { + "gpio65", +}; +static const char * const TS_RESET_groups[] = { + "gpio66", +}; +static const char * const ssc_irq_groups[] = { + "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72", "gpio74", + "gpio75", "gpio76", +}; +static const char * const isense_dbg_groups[] = { + "gpio68", +}; +static const char * const phase_flag0_groups[] = { + "gpio68", +}; +static const char * const phase_flag7_groups[] = { + "gpio69", +}; +static const char * const phase_flag8_groups[] = { + "gpio70", +}; +static const char * const tsense_pwm1_groups[] = { + "gpio71", +}; +static const char * const tsense_pwm2_groups[] = { + "gpio71", +}; +static const char * const SENSOR_RST_groups[] = { + "gpio77", +}; +static const char * const WMSS_RESETN_groups[] = { + "gpio78", +}; +static const char * const HAPTICS_PWM_groups[] = { + "gpio79", +}; +static const char * const GPS_eLNA_groups[] = { + "gpio80", +}; +static const char * const mss_lte_groups[] = { + "gpio81", "gpio82", +}; +static const char * const uim2_data_groups[] = { + "gpio83", +}; +static const char * const uim2_clk_groups[] = { + "gpio84", +}; +static const char * const uim2_reset_groups[] = { + "gpio85", +}; +static const char * const uim2_present_groups[] = { + "gpio86", +}; +static const char * const uim1_data_groups[] = { + "gpio87", +}; +static const char * const uim1_clk_groups[] = { + "gpio88", +}; +static const char * const uim1_reset_groups[] = { + "gpio89", +}; +static const char * const uim1_present_groups[] = { + "gpio90", +}; +static const char * const uim_batt_groups[] = { + "gpio91", +}; +static const char * const pa_indicator_groups[] = { + "gpio92", +}; +static const char * const ldo_en_groups[] = { + "gpio97", +}; +static const char * const ldo_update_groups[] = { + "gpio98", +}; +static const char * const qlink_request_groups[] = { + "gpio99", +}; +static const char * const qlink_enable_groups[] = { + "gpio100", +}; +static const char * const prng_rosc_groups[] = { + "gpio102", +}; +static const char * const LCD_PWR_groups[] = { + "gpio113", +}; + +static const struct msm_function sdm660_functions[] = { + FUNCTION(blsp_spi1), + FUNCTION(gpio), + FUNCTION(blsp_uim1), + FUNCTION(tgu_ch0), + FUNCTION(qdss_gpio4), + FUNCTION(atest_gpsadc1), + FUNCTION(blsp_uart1), + FUNCTION(SMB_STAT), + FUNCTION(phase_flag14), + FUNCTION(blsp_i2c2), + FUNCTION(phase_flag31), + FUNCTION(blsp_spi3), + FUNCTION(blsp_spi3_cs1), + FUNCTION(blsp_spi3_cs2), + FUNCTION(wlan1_adc1), + FUNCTION(atest_usb13), + FUNCTION(tgu_ch1), + FUNCTION(qdss_gpio5), + FUNCTION(atest_gpsadc0), + FUNCTION(blsp_i2c1), + FUNCTION(ddr_bist), + FUNCTION(atest_tsens2), + FUNCTION(atest_usb1), + FUNCTION(blsp_spi2), + FUNCTION(blsp_uim2), + FUNCTION(phase_flag3), + FUNCTION(bimc_dte1), + FUNCTION(wlan1_adc0), + FUNCTION(atest_usb12), + FUNCTION(bimc_dte0), + FUNCTION(blsp_i2c3), + FUNCTION(wlan2_adc1), + FUNCTION(atest_usb11), + FUNCTION(dbg_out), + FUNCTION(wlan2_adc0), + FUNCTION(atest_usb10), + FUNCTION(RCM_MARKER), + FUNCTION(blsp_spi4), + FUNCTION(pri_mi2s), + FUNCTION(phase_flag26), + FUNCTION(qdss_cti0_a), + FUNCTION(qdss_cti0_b), + FUNCTION(qdss_cti1_a), + FUNCTION(qdss_cti1_b), + FUNCTION(DP_HOT), + FUNCTION(pri_mi2s_ws), + FUNCTION(phase_flag27), + FUNCTION(blsp_i2c4), + FUNCTION(phase_flag28), + FUNCTION(blsp_uart5), + FUNCTION(blsp_spi5), + FUNCTION(blsp_uim5), + FUNCTION(phase_flag5), + FUNCTION(blsp_i2c5), + FUNCTION(blsp_spi6), + FUNCTION(blsp_uart2), + FUNCTION(blsp_uim6), + FUNCTION(phase_flag11), + FUNCTION(vsense_data0), + FUNCTION(blsp_i2c6), + FUNCTION(phase_flag12), + FUNCTION(vsense_data1), + FUNCTION(phase_flag13), + FUNCTION(vsense_mode), + FUNCTION(blsp_spi7), + FUNCTION(blsp_uart6_a), + FUNCTION(blsp_uart6_b), + FUNCTION(sec_mi2s), + FUNCTION(sndwire_clk), + FUNCTION(phase_flag17), + FUNCTION(vsense_clkout), + FUNCTION(sndwire_data), + FUNCTION(phase_flag18), + FUNCTION(WSA_SPKR), + FUNCTION(blsp_i2c7), + FUNCTION(phase_flag19), + FUNCTION(vfr_1), + FUNCTION(phase_flag20), + FUNCTION(NFC_INT), + FUNCTION(blsp_spi8_cs1), + FUNCTION(blsp_spi8_cs2), + FUNCTION(m_voc), + FUNCTION(phase_flag21), + FUNCTION(NFC_EN), + FUNCTION(phase_flag22), + FUNCTION(NFC_DWL), + FUNCTION(blsp_i2c8_a), + FUNCTION(blsp_i2c8_b), + FUNCTION(phase_flag23), + FUNCTION(NFC_ESE), + FUNCTION(pwr_modem), + FUNCTION(phase_flag24), + FUNCTION(qdss_gpio), + FUNCTION(cam_mclk), + FUNCTION(pwr_nav), + FUNCTION(qdss_gpio0), + FUNCTION(qspi_data0), + FUNCTION(pwr_crypto), + FUNCTION(qdss_gpio1), + FUNCTION(qspi_data1), + FUNCTION(agera_pll), + FUNCTION(qdss_gpio2), + FUNCTION(qspi_data2), + FUNCTION(jitter_bist), + FUNCTION(qdss_gpio3), + FUNCTION(qdss_gpio7), + FUNCTION(FL_R3LED), + FUNCTION(CCI_TIMER0), + FUNCTION(FL_STROBE), + FUNCTION(CCI_TIMER1), + FUNCTION(CAM_LDO1), + FUNCTION(mdss_vsync0), + FUNCTION(mdss_vsync1), + FUNCTION(mdss_vsync2), + FUNCTION(mdss_vsync3), + FUNCTION(qdss_gpio9), + FUNCTION(CAM_IRQ), + FUNCTION(atest_usb2), + FUNCTION(cci_i2c), + FUNCTION(pll_bypassnl), + FUNCTION(atest_tsens), + FUNCTION(atest_usb21), + FUNCTION(pll_reset), + FUNCTION(atest_usb23), + FUNCTION(qdss_gpio6), + FUNCTION(CCI_TIMER3), + FUNCTION(CCI_ASYNC), + FUNCTION(qspi_cs), + FUNCTION(qdss_gpio10), + FUNCTION(CAM3_STANDBY), + FUNCTION(CCI_TIMER4), + FUNCTION(qdss_gpio11), + FUNCTION(CAM_LDO2), + FUNCTION(cci_async), + FUNCTION(qdss_gpio12), + FUNCTION(CAM0_RST), + FUNCTION(qdss_gpio13), + FUNCTION(CAM1_RST), + FUNCTION(qspi_clk), + FUNCTION(phase_flag30), + FUNCTION(qdss_gpio14), + FUNCTION(qspi_resetn), + FUNCTION(phase_flag1), + FUNCTION(qdss_gpio15), + FUNCTION(CAM0_STANDBY), + FUNCTION(phase_flag2), + FUNCTION(CAM1_STANDBY), + FUNCTION(phase_flag9), + FUNCTION(CAM2_STANDBY), + FUNCTION(qspi_data3), + FUNCTION(phase_flag15), + FUNCTION(qdss_gpio8), + FUNCTION(CAM3_RST), + FUNCTION(CCI_TIMER2), + FUNCTION(phase_flag16), + FUNCTION(LCD0_RESET), + FUNCTION(phase_flag6), + FUNCTION(SD_CARD), + FUNCTION(phase_flag29), + FUNCTION(DP_EN), + FUNCTION(phase_flag25), + FUNCTION(USBC_ORIENTATION), + FUNCTION(phase_flag10), + FUNCTION(atest_usb20), + FUNCTION(gcc_gp1), + FUNCTION(phase_flag4), + FUNCTION(atest_usb22), + FUNCTION(USB_PHY), + FUNCTION(gcc_gp2), + FUNCTION(atest_char), + FUNCTION(mdp_vsync), + FUNCTION(gcc_gp3), + FUNCTION(atest_char3), + FUNCTION(FORCE_TOUCH), + FUNCTION(cri_trng0), + FUNCTION(atest_char2), + FUNCTION(cri_trng1), + FUNCTION(atest_char1), + FUNCTION(AUDIO_USBC), + FUNCTION(audio_ref), + FUNCTION(MDP_VSYNC), + FUNCTION(cri_trng), + FUNCTION(atest_char0), + FUNCTION(US_EURO), + FUNCTION(LCD_BACKLIGHT), + FUNCTION(blsp_spi8_a), + FUNCTION(blsp_spi8_b), + FUNCTION(sp_cmu), + FUNCTION(nav_pps_a), + FUNCTION(nav_pps_b), + FUNCTION(nav_pps_c), + FUNCTION(gps_tx_a), + FUNCTION(gps_tx_b), + FUNCTION(gps_tx_c), + FUNCTION(adsp_ext), + FUNCTION(TS_RESET), + FUNCTION(ssc_irq), + FUNCTION(isense_dbg), + FUNCTION(phase_flag0), + FUNCTION(phase_flag7), + FUNCTION(phase_flag8), + FUNCTION(tsense_pwm1), + FUNCTION(tsense_pwm2), + FUNCTION(SENSOR_RST), + FUNCTION(WMSS_RESETN), + FUNCTION(HAPTICS_PWM), + FUNCTION(GPS_eLNA), + FUNCTION(mss_lte), + FUNCTION(uim2_data), + FUNCTION(uim2_clk), + FUNCTION(uim2_reset), + FUNCTION(uim2_present), + FUNCTION(uim1_data), + FUNCTION(uim1_clk), + FUNCTION(uim1_reset), + FUNCTION(uim1_present), + FUNCTION(uim_batt), + FUNCTION(pa_indicator), + FUNCTION(ldo_en), + FUNCTION(ldo_update), + FUNCTION(qlink_request), + FUNCTION(qlink_enable), + FUNCTION(prng_rosc), + FUNCTION(LCD_PWR), +}; + +static const struct msm_pingroup sdm660_groups[] = { + PINGROUP(0, SOUTH, blsp_spi1, blsp_uart1, blsp_uim1, tgu_ch0, NA, NA, + qdss_gpio4, atest_gpsadc1, NA), + PINGROUP(1, SOUTH, blsp_spi1, blsp_uart1, blsp_uim1, tgu_ch1, NA, NA, + qdss_gpio5, atest_gpsadc0, NA), + PINGROUP(2, SOUTH, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA, + NA, NA), + PINGROUP(3, SOUTH, blsp_spi1, blsp_uart1, blsp_i2c1, ddr_bist, NA, NA, + atest_tsens2, atest_usb1, NA), + PINGROUP(4, NORTH, blsp_spi2, blsp_uim2, blsp_uart2, phase_flag3, NA, + NA, NA, NA, NA), + PINGROUP(5, SOUTH, blsp_spi2, blsp_uim2, blsp_uart2, phase_flag14, NA, + NA, NA, NA, NA), + PINGROUP(6, SOUTH, blsp_spi2, blsp_i2c2, blsp_uart2, phase_flag31, NA, + NA, NA, NA, NA), + PINGROUP(7, SOUTH, blsp_spi2, blsp_i2c2, blsp_uart2, NA, NA, NA, NA, + NA, NA), + PINGROUP(8, NORTH, blsp_spi3, ddr_bist, NA, NA, NA, wlan1_adc1, + atest_usb13, bimc_dte1, NA), + PINGROUP(9, NORTH, blsp_spi3, ddr_bist, NA, NA, NA, wlan1_adc0, + atest_usb12, bimc_dte0, NA), + PINGROUP(10, NORTH, blsp_spi3, blsp_i2c3, ddr_bist, NA, NA, wlan2_adc1, + atest_usb11, bimc_dte1, NA), + PINGROUP(11, NORTH, blsp_spi3, blsp_i2c3, NA, dbg_out, wlan2_adc0, + atest_usb10, bimc_dte0, NA, NA), + PINGROUP(12, NORTH, blsp_spi4, pri_mi2s, NA, phase_flag26, qdss_cti1_b, + NA, NA, NA, NA), + PINGROUP(13, NORTH, blsp_spi4, DP_HOT, pri_mi2s_ws, NA, NA, + phase_flag27, qdss_cti0_b, NA, NA), + PINGROUP(14, NORTH, blsp_spi4, blsp_i2c4, pri_mi2s, NA, phase_flag28, + NA, NA, NA, NA), + PINGROUP(15, NORTH, blsp_spi4, blsp_i2c4, pri_mi2s, NA, NA, NA, NA, NA, + NA), + PINGROUP(16, CENTER, blsp_uart5, blsp_spi5, blsp_uim5, NA, NA, NA, NA, + NA, NA), + PINGROUP(17, CENTER, blsp_uart5, blsp_spi5, blsp_uim5, NA, phase_flag5, + NA, NA, NA, NA), + PINGROUP(18, CENTER, blsp_uart5, blsp_spi5, blsp_i2c5, NA, NA, NA, NA, + NA, NA), + PINGROUP(19, CENTER, blsp_uart5, blsp_spi5, blsp_i2c5, NA, NA, NA, NA, + NA, NA), + PINGROUP(20, SOUTH, NA, NA, blsp_uim6, NA, NA, NA, NA, + NA, NA), + PINGROUP(21, SOUTH, NA, NA, blsp_uim6, NA, phase_flag11, + qdss_cti0_b, vsense_data0, NA, NA), + PINGROUP(22, CENTER, blsp_spi6, NA, blsp_i2c6, NA, + phase_flag12, vsense_data1, NA, NA, NA), + PINGROUP(23, CENTER, blsp_spi6, NA, blsp_i2c6, NA, + phase_flag13, vsense_mode, NA, NA, NA), + PINGROUP(24, NORTH, blsp_spi7, blsp_uart6_a, sec_mi2s, sndwire_clk, NA, + NA, phase_flag17, vsense_clkout, NA), + PINGROUP(25, NORTH, blsp_spi7, blsp_uart6_a, sec_mi2s, sndwire_data, NA, + NA, phase_flag18, NA, NA), + PINGROUP(26, NORTH, blsp_spi7, blsp_uart6_a, blsp_i2c7, sec_mi2s, NA, + phase_flag19, NA, NA, NA), + PINGROUP(27, NORTH, blsp_spi7, blsp_uart6_a, blsp_i2c7, vfr_1, sec_mi2s, + NA, phase_flag20, NA, NA), + PINGROUP(28, CENTER, blsp_spi8_a, blsp_uart6_b, m_voc, NA, phase_flag21, + NA, NA, NA, NA), + PINGROUP(29, CENTER, blsp_spi8_a, blsp_uart6_b, NA, NA, phase_flag22, + NA, NA, NA, NA), + PINGROUP(30, CENTER, blsp_spi8_a, blsp_uart6_b, blsp_i2c8_a, + blsp_spi3_cs1, NA, phase_flag23, NA, NA, NA), + PINGROUP(31, CENTER, blsp_spi8_a, blsp_uart6_b, blsp_i2c8_a, pwr_modem, + NA, phase_flag24, qdss_gpio, NA, NA), + PINGROUP(32, SOUTH, cam_mclk, pwr_nav, NA, NA, qdss_gpio0, NA, NA, NA, + NA), + PINGROUP(33, SOUTH, cam_mclk, qspi_data0, pwr_crypto, NA, NA, + qdss_gpio1, NA, NA, NA), + PINGROUP(34, SOUTH, cam_mclk, qspi_data1, agera_pll, NA, NA, + qdss_gpio2, NA, NA, NA), + PINGROUP(35, SOUTH, cam_mclk, qspi_data2, jitter_bist, NA, NA, + qdss_gpio3, NA, atest_usb2, NA), + PINGROUP(36, SOUTH, cci_i2c, pll_bypassnl, agera_pll, NA, NA, + qdss_gpio4, atest_tsens, atest_usb21, NA), + PINGROUP(37, SOUTH, cci_i2c, pll_reset, NA, NA, qdss_gpio5, + atest_usb23, NA, NA, NA), + PINGROUP(38, SOUTH, cci_i2c, NA, NA, qdss_gpio6, NA, NA, NA, NA, NA), + PINGROUP(39, SOUTH, cci_i2c, NA, NA, qdss_gpio7, NA, NA, NA, NA, NA), + PINGROUP(40, SOUTH, CCI_TIMER0, NA, blsp_spi8_b, NA, NA, NA, NA, NA, + NA), + PINGROUP(41, SOUTH, CCI_TIMER1, NA, blsp_spi8_b, NA, NA, NA, NA, NA, + NA), + PINGROUP(42, SOUTH, mdss_vsync0, mdss_vsync1, mdss_vsync2, mdss_vsync3, + NA, NA, qdss_gpio9, NA, NA), + PINGROUP(43, SOUTH, CCI_TIMER3, CCI_ASYNC, qspi_cs, NA, NA, + qdss_gpio10, NA, NA, NA), + PINGROUP(44, SOUTH, CCI_TIMER4, CCI_ASYNC, blsp_spi8_b, blsp_i2c8_b, NA, + NA, qdss_gpio11, NA, NA), + PINGROUP(45, SOUTH, cci_async, NA, NA, qdss_gpio12, NA, NA, NA, NA, NA), + PINGROUP(46, SOUTH, blsp_spi1, NA, NA, qdss_gpio13, NA, NA, NA, NA, NA), + PINGROUP(47, SOUTH, qspi_clk, NA, phase_flag30, qdss_gpio14, NA, NA, + NA, NA, NA), + PINGROUP(48, SOUTH, NA, phase_flag1, qdss_gpio15, NA, NA, NA, NA, NA, + NA), + PINGROUP(49, SOUTH, blsp_spi6, phase_flag2, qdss_cti0_a, NA, NA, NA, + NA, NA, NA), + PINGROUP(50, SOUTH, qspi_cs, NA, phase_flag9, qdss_cti0_a, NA, NA, NA, + NA, NA), + PINGROUP(51, SOUTH, qspi_data3, NA, phase_flag15, qdss_gpio8, NA, NA, + NA, NA, NA), + PINGROUP(52, SOUTH, CCI_TIMER2, blsp_spi8_b, blsp_i2c8_b, blsp_spi6, + phase_flag16, qdss_gpio, NA, NA, NA), + PINGROUP(53, NORTH, NA, phase_flag6, qdss_cti1_a, NA, NA, NA, NA, NA, + NA), + PINGROUP(54, NORTH, NA, NA, phase_flag29, NA, NA, NA, NA, NA, NA), + PINGROUP(55, SOUTH, NA, phase_flag25, qdss_cti1_a, NA, NA, NA, NA, NA, + NA), + PINGROUP(56, SOUTH, NA, phase_flag10, qdss_gpio3, NA, atest_usb20, NA, + NA, NA, NA), + PINGROUP(57, SOUTH, gcc_gp1, NA, phase_flag4, atest_usb22, NA, NA, NA, + NA, NA), + PINGROUP(58, SOUTH, USB_PHY, gcc_gp2, NA, NA, atest_char, NA, NA, NA, + NA), + PINGROUP(59, NORTH, mdp_vsync, gcc_gp3, NA, NA, atest_char3, NA, NA, + NA, NA), + PINGROUP(60, NORTH, cri_trng0, NA, NA, atest_char2, NA, NA, NA, NA, NA), + PINGROUP(61, NORTH, pri_mi2s, cri_trng1, NA, NA, atest_char1, NA, NA, + NA, NA), + PINGROUP(62, NORTH, sec_mi2s, audio_ref, MDP_VSYNC, cri_trng, NA, NA, + atest_char0, NA, NA), + PINGROUP(63, NORTH, NA, NA, NA, qdss_gpio1, NA, NA, NA, NA, NA), + PINGROUP(64, SOUTH, blsp_spi8_cs1, sp_cmu, NA, NA, qdss_gpio2, NA, NA, + NA, NA), + PINGROUP(65, SOUTH, NA, nav_pps_a, nav_pps_a, gps_tx_a, blsp_spi3_cs2, + adsp_ext, NA, NA, NA), + PINGROUP(66, NORTH, NA, NA, qdss_cti1_b, NA, NA, NA, NA, NA, NA), + PINGROUP(67, NORTH, NA, NA, qdss_gpio0, NA, NA, NA, NA, NA, NA), + PINGROUP(68, NORTH, isense_dbg, NA, phase_flag0, qdss_gpio, NA, NA, NA, + NA, NA), + PINGROUP(69, NORTH, NA, phase_flag7, qdss_gpio, NA, NA, NA, NA, NA, NA), + PINGROUP(70, NORTH, NA, phase_flag8, qdss_gpio6, NA, NA, NA, NA, NA, + NA), + PINGROUP(71, NORTH, NA, NA, qdss_gpio7, tsense_pwm1, tsense_pwm2, NA, + NA, NA, NA), + PINGROUP(72, NORTH, NA, qdss_gpio14, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(73, NORTH, NA, NA, qdss_gpio15, NA, NA, NA, NA, NA, NA), + PINGROUP(74, NORTH, mdp_vsync, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(75, NORTH, NA, NA, qdss_gpio8, NA, NA, NA, NA, NA, NA), + PINGROUP(76, NORTH, blsp_spi8_cs2, NA, NA, NA, qdss_gpio9, NA, NA, NA, + NA), + PINGROUP(77, NORTH, NA, NA, qdss_gpio10, NA, NA, NA, NA, NA, NA), + PINGROUP(78, NORTH, gcc_gp1, NA, qdss_gpio13, NA, NA, NA, NA, NA, NA), + PINGROUP(79, SOUTH, NA, NA, qdss_gpio11, NA, NA, NA, NA, NA, NA), + PINGROUP(80, SOUTH, nav_pps_b, nav_pps_b, gps_tx_c, NA, NA, qdss_gpio12, + NA, NA, NA), + PINGROUP(81, CENTER, mss_lte, gcc_gp2, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(82, CENTER, mss_lte, gcc_gp3, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(83, SOUTH, uim2_data, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(84, SOUTH, uim2_clk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(85, SOUTH, uim2_reset, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(86, SOUTH, uim2_present, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(87, SOUTH, uim1_data, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(88, SOUTH, uim1_clk, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(89, SOUTH, uim1_reset, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(90, SOUTH, uim1_present, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(91, SOUTH, uim_batt, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(92, SOUTH, NA, NA, pa_indicator, NA, NA, NA, NA, NA, NA), + PINGROUP(93, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(94, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(95, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(96, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(97, SOUTH, NA, ldo_en, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(98, SOUTH, NA, nav_pps_c, nav_pps_c, gps_tx_b, ldo_update, NA, + NA, NA, NA), + PINGROUP(99, SOUTH, qlink_request, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(100, SOUTH, qlink_enable, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(101, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(102, SOUTH, NA, prng_rosc, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(103, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(104, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(105, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(106, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(107, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(108, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(109, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(110, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(111, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(112, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(113, SOUTH, NA, NA, NA, NA, NA, NA, NA, NA, NA), + SDC_QDSD_PINGROUP(sdc1_clk, 0x99a000, 13, 6), + SDC_QDSD_PINGROUP(sdc1_cmd, 0x99a000, 11, 3), + SDC_QDSD_PINGROUP(sdc1_data, 0x99a000, 9, 0), + SDC_QDSD_PINGROUP(sdc2_clk, 0x99b000, 14, 6), + SDC_QDSD_PINGROUP(sdc2_cmd, 0x99b000, 11, 3), + SDC_QDSD_PINGROUP(sdc2_data, 0x99b000, 9, 0), + SDC_QDSD_PINGROUP(sdc1_rclk, 0x99a000, 15, 0), +}; + +static const struct msm_pinctrl_soc_data sdm660_pinctrl = { + .pins = sdm660_pins, + .npins = ARRAY_SIZE(sdm660_pins), + .functions = sdm660_functions, + .nfunctions = ARRAY_SIZE(sdm660_functions), + .groups = sdm660_groups, + .ngroups = ARRAY_SIZE(sdm660_groups), + .ngpios = 114, +}; + +static int sdm660_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sdm660_pinctrl); +} + +static const struct of_device_id sdm660_pinctrl_of_match[] = { + { .compatible = "qcom,sdm660-pinctrl", }, + { }, +}; + +static struct platform_driver sdm660_pinctrl_driver = { + .driver = { + .name = "sdm660-pinctrl", + .owner = THIS_MODULE, + .of_match_table = sdm660_pinctrl_of_match, + }, + .probe = sdm660_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sdm660_pinctrl_init(void) +{ + return platform_driver_register(&sdm660_pinctrl_driver); +} +arch_initcall(sdm660_pinctrl_init); + +static void __exit sdm660_pinctrl_exit(void) +{ + platform_driver_unregister(&sdm660_pinctrl_driver); +} +module_exit(sdm660_pinctrl_exit); + +MODULE_DESCRIPTION("QTI sdm660 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sdm660_pinctrl_of_match); diff --git a/drivers/platform/msm/qpnp-revid.c b/drivers/platform/msm/qpnp-revid.c index cfc8093fa3dd..6b5db58f856a 100644 --- a/drivers/platform/msm/qpnp-revid.c +++ b/drivers/platform/msm/qpnp-revid.c @@ -56,8 +56,8 @@ static const char *const pmic_names[] = { [PMI8998_SUBTYPE] = "PMI8998", [PM8005_SUBTYPE] = "PM8005", [PM8937_SUBTYPE] = "PM8937", - [PM2FALCON_SUBTYPE] = "PM2FALCON", - [PMFALCON_SUBTYPE] = "PMFALCON", + [PM660L_SUBTYPE] = "PM660L", + [PM660_SUBTYPE] = "PM660", [PMI8937_SUBTYPE] = "PMI8937", }; diff --git a/drivers/power/qcom-charger/qpnp-fg-gen3.c b/drivers/power/qcom-charger/qpnp-fg-gen3.c index 7c1ece431beb..edd9b9ff28cf 100644 --- a/drivers/power/qcom-charger/qpnp-fg-gen3.c +++ b/drivers/power/qcom-charger/qpnp-fg-gen3.c @@ -3157,7 +3157,7 @@ static int fg_parse_dt(struct fg_chip *chip) return -EINVAL; } break; - case PMFALCON_SUBTYPE: + case PM660_SUBTYPE: chip->sp = pmi8998_v2_sram_params; chip->alg_flags = pmi8998_v2_alg_flags; break; diff --git a/drivers/power/qcom-charger/qpnp-smb2.c b/drivers/power/qcom-charger/qpnp-smb2.c index 90e3689086a6..463cbb7cb8ba 100644 --- a/drivers/power/qcom-charger/qpnp-smb2.c +++ b/drivers/power/qcom-charger/qpnp-smb2.c @@ -1453,7 +1453,7 @@ static int smb2_setup_wa_flags(struct smb2 *chip) if (pmic_rev_id->rev4 == PMI8998_V2P0_REV4) /* PMI rev 2.0 */ chg->wa_flags |= TYPEC_CC2_REMOVAL_WA_BIT; break; - case PMFALCON_SUBTYPE: + case PM660_SUBTYPE: chip->chg.wa_flags |= BOOST_BACK_WA; break; default: diff --git a/drivers/regulator/cpr4-mmss-ldo-regulator.c b/drivers/regulator/cpr4-mmss-ldo-regulator.c index 9fa5c309b02a..69c11a9e5da2 100644 --- a/drivers/regulator/cpr4-mmss-ldo-regulator.c +++ b/drivers/regulator/cpr4-mmss-ldo-regulator.c @@ -36,10 +36,10 @@ #include "cpr3-regulator.h" -#define MSMFALCON_MMSS_FUSE_CORNERS 6 +#define SDM660_MMSS_FUSE_CORNERS 6 /** - * struct cpr4_msmfalcon_mmss_fuses - MMSS specific fuse data for MSMFALCON + * struct cpr4_sdm660_mmss_fuses - MMSS specific fuse data for SDM660 * @init_voltage: Initial (i.e. open-loop) voltage fuse parameter value * for each fuse corner (raw, not converted to a voltage) * @offset_voltage: The closed-loop voltage margin adjustment fuse parameter @@ -55,19 +55,19 @@ * * This struct holds the values for all of the fuses read from memory. */ -struct cpr4_msmfalcon_mmss_fuses { - u64 init_voltage[MSMFALCON_MMSS_FUSE_CORNERS]; - u64 offset_voltage[MSMFALCON_MMSS_FUSE_CORNERS]; +struct cpr4_sdm660_mmss_fuses { + u64 init_voltage[SDM660_MMSS_FUSE_CORNERS]; + u64 offset_voltage[SDM660_MMSS_FUSE_CORNERS]; u64 cpr_fusing_rev; - u64 ldo_enable[MSMFALCON_MMSS_FUSE_CORNERS]; + u64 ldo_enable[SDM660_MMSS_FUSE_CORNERS]; u64 ldo_cpr_cl_enable; }; /* Fuse combos 0 - 7 map to CPR fusing revision 0 - 7 */ -#define CPR4_MSMFALCON_MMSS_FUSE_COMBO_COUNT 8 +#define CPR4_SDM660_MMSS_FUSE_COMBO_COUNT 8 /* - * MSMFALCON MMSS fuse parameter locations: + * SDM660 MMSS fuse parameter locations: * * Structs are organized with the following dimensions: * Outer: 0 to 3 for fuse corners from lowest to highest corner @@ -79,7 +79,7 @@ struct cpr4_msmfalcon_mmss_fuses { * a given parameter may correspond to different fuse rows. */ static const struct cpr3_fuse_param -msmfalcon_mmss_init_voltage_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = { +sdm660_mmss_init_voltage_param[SDM660_MMSS_FUSE_CORNERS][2] = { {{65, 39, 43}, {} }, {{65, 39, 43}, {} }, {{65, 34, 38}, {} }, @@ -88,13 +88,13 @@ msmfalcon_mmss_init_voltage_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = { {{65, 24, 28}, {} }, }; -static const struct cpr3_fuse_param msmfalcon_cpr_fusing_rev_param[] = { +static const struct cpr3_fuse_param sdm660_cpr_fusing_rev_param[] = { {71, 34, 36}, {}, }; static const struct cpr3_fuse_param -msmfalcon_mmss_offset_voltage_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = { +sdm660_mmss_offset_voltage_param[SDM660_MMSS_FUSE_CORNERS][2] = { {{} }, {{} }, {{} }, @@ -104,7 +104,7 @@ msmfalcon_mmss_offset_voltage_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = { }; static const struct cpr3_fuse_param -msmfalcon_mmss_ldo_enable_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = { +sdm660_mmss_ldo_enable_param[SDM660_MMSS_FUSE_CORNERS][2] = { {{73, 62, 62}, {} }, {{73, 61, 61}, {} }, {{73, 60, 60}, {} }, @@ -113,15 +113,15 @@ msmfalcon_mmss_ldo_enable_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = { {{73, 57, 57}, {} }, }; -static const struct cpr3_fuse_param msmfalcon_ldo_cpr_cl_enable_param[] = { +static const struct cpr3_fuse_param sdm660_ldo_cpr_cl_enable_param[] = { {71, 38, 38}, {}, }; -/* Additional MSMFALCON specific data: */ +/* Additional SDM660 specific data: */ /* Open loop voltage fuse reference voltages in microvolts */ -static const int msmfalcon_mmss_fuse_ref_volt[MSMFALCON_MMSS_FUSE_CORNERS] = { +static const int sdm660_mmss_fuse_ref_volt[SDM660_MMSS_FUSE_CORNERS] = { 584000, 644000, 724000, @@ -130,36 +130,36 @@ static const int msmfalcon_mmss_fuse_ref_volt[MSMFALCON_MMSS_FUSE_CORNERS] = { 924000, }; -#define MSMFALCON_MMSS_FUSE_STEP_VOLT 10000 -#define MSMFALCON_MMSS_OFFSET_FUSE_STEP_VOLT 10000 -#define MSMFALCON_MMSS_VOLTAGE_FUSE_SIZE 5 +#define SDM660_MMSS_FUSE_STEP_VOLT 10000 +#define SDM660_MMSS_OFFSET_FUSE_STEP_VOLT 10000 +#define SDM660_MMSS_VOLTAGE_FUSE_SIZE 5 -#define MSMFALCON_MMSS_CPR_SENSOR_COUNT 11 +#define SDM660_MMSS_CPR_SENSOR_COUNT 11 -#define MSMFALCON_MMSS_CPR_CLOCK_RATE 19200000 +#define SDM660_MMSS_CPR_CLOCK_RATE 19200000 /** - * cpr4_msmfalcon_mmss_read_fuse_data() - load MMSS specific fuse parameter + * cpr4_sdm660_mmss_read_fuse_data() - load MMSS specific fuse parameter * values * @vreg: Pointer to the CPR3 regulator * - * This function allocates a cpr4_msmfalcon_mmss_fuses struct, fills it with + * This function allocates a cpr4_sdm660_mmss_fuses struct, fills it with * values read out of hardware fuses, and finally copies common fuse values * into the regulator struct. * * Return: 0 on success, errno on failure */ -static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg) +static int cpr4_sdm660_mmss_read_fuse_data(struct cpr3_regulator *vreg) { void __iomem *base = vreg->thread->ctrl->fuse_base; - struct cpr4_msmfalcon_mmss_fuses *fuse; + struct cpr4_sdm660_mmss_fuses *fuse; int i, rc; fuse = devm_kzalloc(vreg->thread->ctrl->dev, sizeof(*fuse), GFP_KERNEL); if (!fuse) return -ENOMEM; - rc = cpr3_read_fuse_param(base, msmfalcon_cpr_fusing_rev_param, + rc = cpr3_read_fuse_param(base, sdm660_cpr_fusing_rev_param, &fuse->cpr_fusing_rev); if (rc) { cpr3_err(vreg, "Unable to read CPR fusing revision fuse, rc=%d\n", @@ -168,7 +168,7 @@ static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg) } cpr3_info(vreg, "CPR fusing revision = %llu\n", fuse->cpr_fusing_rev); - rc = cpr3_read_fuse_param(base, msmfalcon_ldo_cpr_cl_enable_param, + rc = cpr3_read_fuse_param(base, sdm660_ldo_cpr_cl_enable_param, &fuse->ldo_cpr_cl_enable); if (rc) { cpr3_err(vreg, "Unable to read ldo cpr closed-loop enable fuse, rc=%d\n", @@ -176,9 +176,9 @@ static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg) return rc; } - for (i = 0; i < MSMFALCON_MMSS_FUSE_CORNERS; i++) { + for (i = 0; i < SDM660_MMSS_FUSE_CORNERS; i++) { rc = cpr3_read_fuse_param(base, - msmfalcon_mmss_init_voltage_param[i], + sdm660_mmss_init_voltage_param[i], &fuse->init_voltage[i]); if (rc) { cpr3_err(vreg, "Unable to read fuse-corner %d initial voltage fuse, rc=%d\n", @@ -187,7 +187,7 @@ static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg) } rc = cpr3_read_fuse_param(base, - msmfalcon_mmss_offset_voltage_param[i], + sdm660_mmss_offset_voltage_param[i], &fuse->offset_voltage[i]); if (rc) { cpr3_err(vreg, "Unable to read fuse-corner %d offset voltage fuse, rc=%d\n", @@ -196,7 +196,7 @@ static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg) } rc = cpr3_read_fuse_param(base, - msmfalcon_mmss_ldo_enable_param[i], + sdm660_mmss_ldo_enable_param[i], &fuse->ldo_enable[i]); if (rc) { cpr3_err(vreg, "Unable to read fuse-corner %d ldo enable fuse, rc=%d\n", @@ -206,31 +206,31 @@ static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg) } vreg->fuse_combo = fuse->cpr_fusing_rev; - if (vreg->fuse_combo >= CPR4_MSMFALCON_MMSS_FUSE_COMBO_COUNT) { + if (vreg->fuse_combo >= CPR4_SDM660_MMSS_FUSE_COMBO_COUNT) { cpr3_err(vreg, "invalid CPR fuse combo = %d found, not in range 0 - %d\n", vreg->fuse_combo, - CPR4_MSMFALCON_MMSS_FUSE_COMBO_COUNT - 1); + CPR4_SDM660_MMSS_FUSE_COMBO_COUNT - 1); return -EINVAL; } vreg->cpr_rev_fuse = fuse->cpr_fusing_rev; - vreg->fuse_corner_count = MSMFALCON_MMSS_FUSE_CORNERS; + vreg->fuse_corner_count = SDM660_MMSS_FUSE_CORNERS; vreg->platform_fuses = fuse; return 0; } /** - * cpr3_msmfalcon_mmss_calculate_open_loop_voltages() - calculate the open-loop + * cpr3_sdm660_mmss_calculate_open_loop_voltages() - calculate the open-loop * voltage for each corner of a CPR3 regulator * @vreg: Pointer to the CPR3 regulator * * Return: 0 on success, errno on failure */ -static int cpr4_msmfalcon_mmss_calculate_open_loop_voltages( +static int cpr4_sdm660_mmss_calculate_open_loop_voltages( struct cpr3_regulator *vreg) { - struct cpr4_msmfalcon_mmss_fuses *fuse = vreg->platform_fuses; + struct cpr4_sdm660_mmss_fuses *fuse = vreg->platform_fuses; int i, rc = 0; const int *ref_volt; int *fuse_volt; @@ -240,11 +240,11 @@ static int cpr4_msmfalcon_mmss_calculate_open_loop_voltages( if (!fuse_volt) return -ENOMEM; - ref_volt = msmfalcon_mmss_fuse_ref_volt; + ref_volt = sdm660_mmss_fuse_ref_volt; for (i = 0; i < vreg->fuse_corner_count; i++) { fuse_volt[i] = cpr3_convert_open_loop_voltage_fuse(ref_volt[i], - MSMFALCON_MMSS_FUSE_STEP_VOLT, fuse->init_voltage[i], - MSMFALCON_MMSS_VOLTAGE_FUSE_SIZE); + SDM660_MMSS_FUSE_STEP_VOLT, fuse->init_voltage[i], + SDM660_MMSS_VOLTAGE_FUSE_SIZE); cpr3_info(vreg, "fuse_corner[%d] open-loop=%7d uV\n", i, fuse_volt[i]); } @@ -298,7 +298,7 @@ done: */ static int cpr4_mmss_parse_ldo_mode_data(struct cpr3_regulator *vreg) { - struct cpr4_msmfalcon_mmss_fuses *fuse = vreg->platform_fuses; + struct cpr4_sdm660_mmss_fuses *fuse = vreg->platform_fuses; int i, rc = 0; u32 *ldo_allowed; char *prop_str = "qcom,cpr-corner-allow-ldo-mode"; @@ -341,7 +341,7 @@ done: */ static int cpr4_mmss_parse_corner_operating_mode(struct cpr3_regulator *vreg) { - struct cpr4_msmfalcon_mmss_fuses *fuse = vreg->platform_fuses; + struct cpr4_sdm660_mmss_fuses *fuse = vreg->platform_fuses; int i, rc = 0; u32 *use_closed_loop; char *prop_str = "qcom,cpr-corner-allow-closed-loop"; @@ -476,7 +476,7 @@ static int cpr4_mmss_init_thread(struct cpr3_thread *thread) vreg->ldo_regulator_bypass = BHS_MODE; vreg->ldo_type = CPR3_LDO300; - rc = cpr4_msmfalcon_mmss_read_fuse_data(vreg); + rc = cpr4_sdm660_mmss_read_fuse_data(vreg); if (rc) { cpr3_err(vreg, "unable to read CPR fuse data, rc=%d\n", rc); return rc; @@ -489,7 +489,7 @@ static int cpr4_mmss_init_thread(struct cpr3_thread *thread) return rc; } - rc = cpr4_msmfalcon_mmss_calculate_open_loop_voltages(vreg); + rc = cpr4_sdm660_mmss_calculate_open_loop_voltages(vreg); if (rc) { cpr3_err(vreg, "unable to calculate open-loop voltages, rc=%d\n", rc); @@ -548,7 +548,7 @@ static int cpr4_mmss_init_controller(struct cpr3_controller *ctrl) return rc; } - ctrl->sensor_count = MSMFALCON_MMSS_CPR_SENSOR_COUNT; + ctrl->sensor_count = SDM660_MMSS_CPR_SENSOR_COUNT; /* * MMSS only has one thread (0) so the zeroed array does not need @@ -559,7 +559,7 @@ static int cpr4_mmss_init_controller(struct cpr3_controller *ctrl) if (!ctrl->sensor_owner) return -ENOMEM; - ctrl->cpr_clock_rate = MSMFALCON_MMSS_CPR_CLOCK_RATE; + ctrl->cpr_clock_rate = SDM660_MMSS_CPR_CLOCK_RATE; ctrl->ctrl_type = CPR_CTRL_TYPE_CPR4; ctrl->support_ldo300_vreg = true; @@ -572,7 +572,7 @@ static int cpr4_mmss_init_controller(struct cpr3_controller *ctrl) &ctrl->step_quot_fixed); ctrl->use_dynamic_step_quot = !ctrl->step_quot_fixed; - /* iface_clk is optional for msmfalcon */ + /* iface_clk is optional for sdm660 */ ctrl->iface_clk = NULL; ctrl->bus_clk = devm_clk_get(ctrl->dev, "bus_clk"); if (IS_ERR(ctrl->bus_clk)) { @@ -688,7 +688,7 @@ static int cpr4_mmss_regulator_resume(struct platform_device *pdev) /* Data corresponds to the SoC revision */ static const struct of_device_id cpr4_mmss_regulator_match_table[] = { { - .compatible = "qcom,cpr4-msmfalcon-mmss-ldo-regulator", + .compatible = "qcom,cpr4-sdm660-mmss-ldo-regulator", .data = (void *)NULL, }, }; diff --git a/drivers/regulator/msm_gfx_ldo.c b/drivers/regulator/msm_gfx_ldo.c index d2f743b8089a..265ca9ed5258 100644 --- a/drivers/regulator/msm_gfx_ldo.c +++ b/drivers/regulator/msm_gfx_ldo.c @@ -152,7 +152,7 @@ static struct ldo_config msm8953_ldo_config[] = { {LDO_MAX_OFFSET, LDO_MAX_OFFSET}, }; -static struct ldo_config msmfalcon_ldo_config[] = { +static struct ldo_config sdm660_ldo_config[] = { {LDO_ATEST_REG, 0x00000080}, {LDO_CFG0_REG, 0x0100A600}, {LDO_CFG1_REG, 0x000000A0}, @@ -185,7 +185,7 @@ static const int msm8953_fuse_ref_volt[MSM8953_LDO_FUSE_CORNERS] = { enum { MSM8953_SOC_ID, - MSMFALCON_SOC_ID, + SDM660_SOC_ID, }; static int convert_open_loop_voltage_fuse(int ref_volt, int step_volt, @@ -1516,8 +1516,8 @@ static const struct of_device_id msm_gfx_ldo_match_table[] = { .data = (void *)(uintptr_t)MSM8953_SOC_ID, }, { - .compatible = "qcom,msmfalcon-gfx-ldo", - .data = (void *)(uintptr_t)MSMFALCON_SOC_ID, + .compatible = "qcom,sdm660-gfx-ldo", + .data = (void *)(uintptr_t)SDM660_SOC_ID, }, {} }; @@ -1572,8 +1572,8 @@ static int msm_gfx_ldo_probe(struct platform_device *pdev) return rc; } break; - case MSMFALCON_SOC_ID: - ldo_vreg->ldo_init_config = msmfalcon_ldo_config; + case SDM660_SOC_ID: + ldo_vreg->ldo_init_config = sdm660_ldo_config; ldo_vreg->ops_type = VOLTAGE; init_data->constraints.valid_ops_mask |= REGULATOR_CHANGE_BYPASS; diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index bd58fcfe3061..ff5eca31323c 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -535,9 +535,9 @@ static struct msm_soc_info cpu_of_id[] = { /* Hamster ID */ [306] = {MSM_CPU_HAMSTER, "MSMHAMSTER"}, - /* falcon ID */ - [317] = {MSM_CPU_FALCON, "MSMFALCON"}, - [324] = {MSM_CPU_FALCON, "APQFALCON"}, + /* 660 ID */ + [317] = {MSM_CPU_660, "SDM660"}, + [324] = {MSM_CPU_660, "SDA660"}, /* triton ID */ [318] = {MSM_CPU_TRITON, "MSMTRITON"}, @@ -1208,13 +1208,13 @@ static void * __init setup_dummy_socinfo(void) dummy_socinfo.id = 306; strlcpy(dummy_socinfo.build_id, "msmhamster - ", sizeof(dummy_socinfo.build_id)); - } else if (early_machine_is_msmfalcon()) { + } else if (early_machine_is_sdm660()) { dummy_socinfo.id = 317; - strlcpy(dummy_socinfo.build_id, "msmfalcon - ", + strlcpy(dummy_socinfo.build_id, "sdm660 - ", sizeof(dummy_socinfo.build_id)); - } else if (early_machine_is_apqfalcon()) { + } else if (early_machine_is_sda660()) { dummy_socinfo.id = 324; - strlcpy(dummy_socinfo.build_id, "apqfalcon - ", + strlcpy(dummy_socinfo.build_id, "sda660 - ", sizeof(dummy_socinfo.build_id)); } else if (early_machine_is_msmtriton()) { dummy_socinfo.id = 318; diff --git a/drivers/thermal/msm-tsens.c b/drivers/thermal/msm-tsens.c index 243b3229f53e..07a1fad03c31 100644 --- a/drivers/thermal/msm-tsens.c +++ b/drivers/thermal/msm-tsens.c @@ -937,7 +937,7 @@ static struct of_device_id tsens_match[] = { { .compatible = "qcom,msmhamster-tsens", .data = (void *)TSENS_CALIB_FUSE_MAP_NONE, }, - { .compatible = "qcom,msmfalcon-tsens", + { .compatible = "qcom,sdm660-tsens", .data = (void *)TSENS_CALIB_FUSE_MAP_NONE, }, { .compatible = "qcom,msmtriton-tsens", @@ -5507,7 +5507,7 @@ static int get_device_tree_data(struct platform_device *pdev, (!strcmp(id->compatible, "qcom,msm8998-tsens"))) tmdev->tsens_type = TSENS_TYPE3; else if (!strcmp(id->compatible, "qcom,msmtitanium-tsens") || - (!strcmp(id->compatible, "qcom,msmfalcon-tsens") || + (!strcmp(id->compatible, "qcom,sdm660-tsens") || (!strcmp(id->compatible, "qcom,msmtriton-tsens") || (!strcmp(id->compatible, "qcom,msmhamster-tsens"))))) { tmdev->tsens_type = TSENS_TYPE3; @@ -5530,7 +5530,7 @@ static int get_device_tree_data(struct platform_device *pdev, (!strcmp(id->compatible, "qcom,msm8937-tsens")) || (!strcmp(id->compatible, "qcom,msmtitanium-tsens")) || (!strcmp(id->compatible, "qcom,msm8998-tsens")) || - (!strcmp(id->compatible, "qcom,msmfalcon-tsens") || + (!strcmp(id->compatible, "qcom,sdm660-tsens") || (!strcmp(id->compatible, "qcom,msmtriton-tsens") || (!strcmp(id->compatible, "qcom,msmhamster-tsens"))))) tmdev->tsens_valid_status_check = true; @@ -5547,7 +5547,7 @@ static int get_device_tree_data(struct platform_device *pdev, if (!strcmp(id->compatible, "qcom,msm8996-tsens") || (!strcmp(id->compatible, "qcom,msm8998-tsens")) || (!strcmp(id->compatible, "qcom,msmhamster-tsens")) || - (!strcmp(id->compatible, "qcom,msmfalcon-tsens") || + (!strcmp(id->compatible, "qcom,sdm660-tsens") || (!strcmp(id->compatible, "qcom,msmtriton-tsens") || (!strcmp(id->compatible, "qcom,msmtitanium-tsens"))))) { tmdev->tsens_critical_irq = diff --git a/include/dt-bindings/clock/qcom,gcc-msmfalcon.h b/include/dt-bindings/clock/qcom,gcc-msmfalcon.h deleted file mode 100644 index aa76fbad5083..000000000000 --- a/include/dt-bindings/clock/qcom,gcc-msmfalcon.h +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_GCC_FALCON_H -#define _DT_BINDINGS_CLK_MSM_GCC_FALCON_H - -/* Hardware/Dummy/Voter clocks */ -#define GCC_XO 0 -#define GCC_GPLL0_EARLY_DIV 1 -#define GCC_GPLL1_EARLY_DIV 2 -#define GCC_CE1_AHB_M_CLK 3 -#define GCC_CE1_AXI_M_CLK 4 - -/* RCGs and Branches */ -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 10 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 11 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 12 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 13 -#define BLSP1_QUP3_I2C_APPS_CLK_SRC 14 -#define BLSP1_QUP3_SPI_APPS_CLK_SRC 15 -#define BLSP1_QUP4_I2C_APPS_CLK_SRC 16 -#define BLSP1_QUP4_SPI_APPS_CLK_SRC 17 -#define BLSP1_UART1_APPS_CLK_SRC 18 -#define BLSP1_UART2_APPS_CLK_SRC 19 -#define BLSP2_QUP1_I2C_APPS_CLK_SRC 20 -#define BLSP2_QUP1_SPI_APPS_CLK_SRC 21 -#define BLSP2_QUP2_I2C_APPS_CLK_SRC 22 -#define BLSP2_QUP2_SPI_APPS_CLK_SRC 23 -#define BLSP2_QUP3_I2C_APPS_CLK_SRC 24 -#define BLSP2_QUP3_SPI_APPS_CLK_SRC 25 -#define BLSP2_QUP4_I2C_APPS_CLK_SRC 26 -#define BLSP2_QUP4_SPI_APPS_CLK_SRC 27 -#define BLSP2_UART1_APPS_CLK_SRC 28 -#define BLSP2_UART2_APPS_CLK_SRC 29 -#define GCC_AGGRE2_UFS_AXI_CLK 30 -#define GCC_AGGRE2_USB3_AXI_CLK 31 -#define GCC_BIMC_GFX_CLK 32 -#define GCC_BIMC_HMSS_AXI_CLK 33 -#define GCC_BIMC_MSS_Q6_AXI_CLK 34 -#define GCC_BLSP1_AHB_CLK 35 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 36 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 37 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 38 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 39 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 40 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 41 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 42 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 43 -#define GCC_BLSP1_UART1_APPS_CLK 44 -#define GCC_BLSP1_UART2_APPS_CLK 45 -#define GCC_BLSP2_AHB_CLK 46 -#define GCC_BLSP2_QUP1_I2C_APPS_CLK 47 -#define GCC_BLSP2_QUP1_SPI_APPS_CLK 48 -#define GCC_BLSP2_QUP2_I2C_APPS_CLK 49 -#define GCC_BLSP2_QUP2_SPI_APPS_CLK 50 -#define GCC_BLSP2_QUP3_I2C_APPS_CLK 51 -#define GCC_BLSP2_QUP3_SPI_APPS_CLK 52 -#define GCC_BLSP2_QUP4_I2C_APPS_CLK 53 -#define GCC_BLSP2_QUP4_SPI_APPS_CLK 54 -#define GCC_BLSP2_UART1_APPS_CLK 55 -#define GCC_BLSP2_UART2_APPS_CLK 56 -#define GCC_BOOT_ROM_AHB_CLK 57 -#define GCC_CFG_NOC_USB2_AXI_CLK 58 -#define GCC_CFG_NOC_USB3_AXI_CLK 59 -#define GCC_DCC_AHB_CLK 60 -#define GCC_GP1_CLK 61 -#define GCC_GP2_CLK 62 -#define GCC_GP3_CLK 63 -#define GCC_GPU_BIMC_GFX_CLK 64 -#define GCC_GPU_BIMC_GFX_SRC_CLK 65 -#define GCC_GPU_CFG_AHB_CLK 66 -#define GCC_GPU_GPLL0_CLK 67 -#define GCC_GPU_GPLL0_DIV_CLK 68 -#define GCC_GPU_SNOC_DVM_GFX_CLK 69 -#define GCC_HMSS_AHB_CLK 70 -#define GCC_HMSS_DVM_BUS_CLK 71 -#define GCC_HMSS_RBCPR_CLK 72 -#define GCC_MMSS_GPLL0_CLK 73 -#define GCC_MMSS_GPLL0_DIV_CLK 74 -#define GCC_MMSS_NOC_CFG_AHB_CLK 75 -#define GCC_MMSS_SYS_NOC_AXI_CLK 76 -#define GCC_MSS_CFG_AHB_CLK 77 -#define GCC_MSS_GPLL0_DIV_CLK 78 -#define GCC_MSS_MNOC_BIMC_AXI_CLK 79 -#define GCC_MSS_Q6_BIMC_AXI_CLK 80 -#define GCC_MSS_SNOC_AXI_CLK 81 -#define GCC_PDM2_CLK 82 -#define GCC_PDM_AHB_CLK 83 -#define GCC_PRNG_AHB_CLK 84 -#define GCC_QSPI_AHB_CLK 85 -#define GCC_QSPI_SER_CLK 86 -#define GCC_RX0_USB2_CLKREF_CLK 87 -#define GCC_RX1_USB2_CLKREF_CLK 88 -#define GCC_RX2_QLINK_CLKREF_CLK 89 -#define GCC_SDCC1_AHB_CLK 90 -#define GCC_SDCC1_APPS_CLK 91 -#define GCC_SDCC1_ICE_CORE_CLK 92 -#define GCC_SDCC2_AHB_CLK 93 -#define GCC_SDCC2_APPS_CLK 94 -#define GCC_UFS_AHB_CLK 95 -#define GCC_UFS_AXI_CLK 96 -#define GCC_UFS_CLKREF_CLK 97 -#define GCC_UFS_ICE_CORE_CLK 98 -#define GCC_UFS_PHY_AUX_CLK 99 -#define GCC_UFS_RX_SYMBOL_0_CLK 100 -#define GCC_UFS_RX_SYMBOL_1_CLK 101 -#define GCC_UFS_TX_SYMBOL_0_CLK 102 -#define GCC_UFS_UNIPRO_CORE_CLK 103 -#define GCC_USB20_MASTER_CLK 104 -#define GCC_USB20_MOCK_UTMI_CLK 105 -#define GCC_USB20_SLEEP_CLK 106 -#define GCC_USB30_MASTER_CLK 107 -#define GCC_USB30_MOCK_UTMI_CLK 108 -#define GCC_USB30_SLEEP_CLK 109 -#define GCC_USB3_CLKREF_CLK 110 -#define GCC_USB3_PHY_AUX_CLK 111 -#define GCC_USB3_PHY_PIPE_CLK 112 -#define GCC_USB_PHY_CFG_AHB2PHY_CLK 113 -#define GP1_CLK_SRC 114 -#define GP2_CLK_SRC 115 -#define GP3_CLK_SRC 116 -#define GPLL0 117 -#define GPLL0_OUT_AUX 118 -#define GPLL0_OUT_AUX2 119 -#define GPLL0_OUT_EARLY 120 -#define GPLL0_OUT_MAIN 121 -#define GPLL0_OUT_TEST 122 -#define GPLL1 123 -#define GPLL1_OUT_AUX 124 -#define GPLL1_OUT_AUX2 125 -#define GPLL1_OUT_EARLY 126 -#define GPLL1_OUT_MAIN 127 -#define GPLL1_OUT_TEST 128 -#define GPLL2 129 -#define GPLL2_OUT_AUX 130 -#define GPLL2_OUT_AUX2 131 -#define GPLL2_OUT_EARLY 132 -#define GPLL2_OUT_MAIN 133 -#define GPLL2_OUT_TEST 134 -#define GPLL3 135 -#define GPLL3_OUT_AUX 136 -#define GPLL3_OUT_AUX2 137 -#define GPLL3_OUT_EARLY 138 -#define GPLL3_OUT_MAIN 139 -#define GPLL3_OUT_TEST 140 -#define GPLL4 141 -#define GPLL4_OUT_AUX 142 -#define GPLL4_OUT_AUX2 143 -#define GPLL4_OUT_EARLY 144 -#define GPLL4_OUT_MAIN 145 -#define GPLL4_OUT_TEST 146 -#define GPLL5 147 -#define GPLL5_OUT_AUX 148 -#define GPLL5_OUT_AUX2 149 -#define GPLL5_OUT_EARLY 150 -#define GPLL5_OUT_MAIN 151 -#define GPLL5_OUT_TEST 152 -#define GPLL6 153 -#define GPLL6_OUT_AUX 154 -#define GPLL6_OUT_AUX2 155 -#define GPLL6_OUT_EARLY 156 -#define GPLL6_OUT_MAIN 157 -#define GPLL6_OUT_TEST 158 -#define HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 159 -#define HMSS_AHB_CLK_SRC 160 -#define HMSS_GPLL0_CLK_SRC 161 -#define HMSS_GPLL4_CLK_SRC 162 -#define HMSS_RBCPR_CLK_SRC 163 -#define PDM2_CLK_SRC 164 -#define QSPI_SER_CLK_SRC 165 -#define SDCC1_APPS_CLK_SRC 166 -#define SDCC1_ICE_CORE_CLK_SRC 167 -#define SDCC2_APPS_CLK_SRC 168 -#define UFS_AXI_CLK_SRC 169 -#define UFS_ICE_CORE_CLK_SRC 170 -#define UFS_PHY_AUX_CLK_SRC 171 -#define UFS_UNIPRO_CORE_CLK_SRC 172 -#define USB20_MASTER_CLK_SRC 173 -#define USB20_MOCK_UTMI_CLK_SRC 174 -#define USB30_MASTER_CLK_SRC 175 -#define USB30_MOCK_UTMI_CLK_SRC 176 -#define USB3_PHY_AUX_CLK_SRC 177 -#define GPLL0_OUT_MSSCC 178 -#define GCC_UFS_AXI_HW_CTL_CLK 179 -#define GCC_UFS_ICE_CORE_HW_CTL_CLK 180 -#define GCC_UFS_PHY_AUX_HW_CTL_CLK 181 -#define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 182 -#define HLOS1_VOTE_TURING_ADSP_SMMU_CLK 183 -#define HLOS2_VOTE_TURING_ADSP_SMMU_CLK 184 - -/* Block resets */ -#define GCC_QUSB2PHY_PRIM_BCR 0 -#define GCC_QUSB2PHY_SEC_BCR 1 -#define GCC_UFS_BCR 2 -#define GCC_USB3_DP_PHY_BCR 3 -#define GCC_USB3_PHY_BCR 4 -#define GCC_USB3PHY_PHY_BCR 5 -#define GCC_USB_20_BCR 6 -#define GCC_USB_30_BCR 7 -#define GCC_USB_PHY_CFG_AHB2PHY_BCR 8 - -#endif diff --git a/include/dt-bindings/clock/qcom,gcc-sdm660.h b/include/dt-bindings/clock/qcom,gcc-sdm660.h new file mode 100644 index 000000000000..4bf87f6c08bf --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sdm660.h @@ -0,0 +1,212 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_GCC_660_H +#define _DT_BINDINGS_CLK_MSM_GCC_660_H + +/* Hardware/Dummy/Voter clocks */ +#define GCC_XO 0 +#define GCC_GPLL0_EARLY_DIV 1 +#define GCC_GPLL1_EARLY_DIV 2 +#define GCC_CE1_AHB_M_CLK 3 +#define GCC_CE1_AXI_M_CLK 4 + +/* RCGs and Branches */ +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 10 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 11 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 12 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 13 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 14 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 15 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 16 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 17 +#define BLSP1_UART1_APPS_CLK_SRC 18 +#define BLSP1_UART2_APPS_CLK_SRC 19 +#define BLSP2_QUP1_I2C_APPS_CLK_SRC 20 +#define BLSP2_QUP1_SPI_APPS_CLK_SRC 21 +#define BLSP2_QUP2_I2C_APPS_CLK_SRC 22 +#define BLSP2_QUP2_SPI_APPS_CLK_SRC 23 +#define BLSP2_QUP3_I2C_APPS_CLK_SRC 24 +#define BLSP2_QUP3_SPI_APPS_CLK_SRC 25 +#define BLSP2_QUP4_I2C_APPS_CLK_SRC 26 +#define BLSP2_QUP4_SPI_APPS_CLK_SRC 27 +#define BLSP2_UART1_APPS_CLK_SRC 28 +#define BLSP2_UART2_APPS_CLK_SRC 29 +#define GCC_AGGRE2_UFS_AXI_CLK 30 +#define GCC_AGGRE2_USB3_AXI_CLK 31 +#define GCC_BIMC_GFX_CLK 32 +#define GCC_BIMC_HMSS_AXI_CLK 33 +#define GCC_BIMC_MSS_Q6_AXI_CLK 34 +#define GCC_BLSP1_AHB_CLK 35 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 36 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 37 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 38 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 39 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 40 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 41 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 42 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 43 +#define GCC_BLSP1_UART1_APPS_CLK 44 +#define GCC_BLSP1_UART2_APPS_CLK 45 +#define GCC_BLSP2_AHB_CLK 46 +#define GCC_BLSP2_QUP1_I2C_APPS_CLK 47 +#define GCC_BLSP2_QUP1_SPI_APPS_CLK 48 +#define GCC_BLSP2_QUP2_I2C_APPS_CLK 49 +#define GCC_BLSP2_QUP2_SPI_APPS_CLK 50 +#define GCC_BLSP2_QUP3_I2C_APPS_CLK 51 +#define GCC_BLSP2_QUP3_SPI_APPS_CLK 52 +#define GCC_BLSP2_QUP4_I2C_APPS_CLK 53 +#define GCC_BLSP2_QUP4_SPI_APPS_CLK 54 +#define GCC_BLSP2_UART1_APPS_CLK 55 +#define GCC_BLSP2_UART2_APPS_CLK 56 +#define GCC_BOOT_ROM_AHB_CLK 57 +#define GCC_CFG_NOC_USB2_AXI_CLK 58 +#define GCC_CFG_NOC_USB3_AXI_CLK 59 +#define GCC_DCC_AHB_CLK 60 +#define GCC_GP1_CLK 61 +#define GCC_GP2_CLK 62 +#define GCC_GP3_CLK 63 +#define GCC_GPU_BIMC_GFX_CLK 64 +#define GCC_GPU_BIMC_GFX_SRC_CLK 65 +#define GCC_GPU_CFG_AHB_CLK 66 +#define GCC_GPU_GPLL0_CLK 67 +#define GCC_GPU_GPLL0_DIV_CLK 68 +#define GCC_GPU_SNOC_DVM_GFX_CLK 69 +#define GCC_HMSS_AHB_CLK 70 +#define GCC_HMSS_DVM_BUS_CLK 71 +#define GCC_HMSS_RBCPR_CLK 72 +#define GCC_MMSS_GPLL0_CLK 73 +#define GCC_MMSS_GPLL0_DIV_CLK 74 +#define GCC_MMSS_NOC_CFG_AHB_CLK 75 +#define GCC_MMSS_SYS_NOC_AXI_CLK 76 +#define GCC_MSS_CFG_AHB_CLK 77 +#define GCC_MSS_GPLL0_DIV_CLK 78 +#define GCC_MSS_MNOC_BIMC_AXI_CLK 79 +#define GCC_MSS_Q6_BIMC_AXI_CLK 80 +#define GCC_MSS_SNOC_AXI_CLK 81 +#define GCC_PDM2_CLK 82 +#define GCC_PDM_AHB_CLK 83 +#define GCC_PRNG_AHB_CLK 84 +#define GCC_QSPI_AHB_CLK 85 +#define GCC_QSPI_SER_CLK 86 +#define GCC_RX0_USB2_CLKREF_CLK 87 +#define GCC_RX1_USB2_CLKREF_CLK 88 +#define GCC_RX2_QLINK_CLKREF_CLK 89 +#define GCC_SDCC1_AHB_CLK 90 +#define GCC_SDCC1_APPS_CLK 91 +#define GCC_SDCC1_ICE_CORE_CLK 92 +#define GCC_SDCC2_AHB_CLK 93 +#define GCC_SDCC2_APPS_CLK 94 +#define GCC_UFS_AHB_CLK 95 +#define GCC_UFS_AXI_CLK 96 +#define GCC_UFS_CLKREF_CLK 97 +#define GCC_UFS_ICE_CORE_CLK 98 +#define GCC_UFS_PHY_AUX_CLK 99 +#define GCC_UFS_RX_SYMBOL_0_CLK 100 +#define GCC_UFS_RX_SYMBOL_1_CLK 101 +#define GCC_UFS_TX_SYMBOL_0_CLK 102 +#define GCC_UFS_UNIPRO_CORE_CLK 103 +#define GCC_USB20_MASTER_CLK 104 +#define GCC_USB20_MOCK_UTMI_CLK 105 +#define GCC_USB20_SLEEP_CLK 106 +#define GCC_USB30_MASTER_CLK 107 +#define GCC_USB30_MOCK_UTMI_CLK 108 +#define GCC_USB30_SLEEP_CLK 109 +#define GCC_USB3_CLKREF_CLK 110 +#define GCC_USB3_PHY_AUX_CLK 111 +#define GCC_USB3_PHY_PIPE_CLK 112 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 113 +#define GP1_CLK_SRC 114 +#define GP2_CLK_SRC 115 +#define GP3_CLK_SRC 116 +#define GPLL0 117 +#define GPLL0_OUT_AUX 118 +#define GPLL0_OUT_AUX2 119 +#define GPLL0_OUT_EARLY 120 +#define GPLL0_OUT_MAIN 121 +#define GPLL0_OUT_TEST 122 +#define GPLL1 123 +#define GPLL1_OUT_AUX 124 +#define GPLL1_OUT_AUX2 125 +#define GPLL1_OUT_EARLY 126 +#define GPLL1_OUT_MAIN 127 +#define GPLL1_OUT_TEST 128 +#define GPLL2 129 +#define GPLL2_OUT_AUX 130 +#define GPLL2_OUT_AUX2 131 +#define GPLL2_OUT_EARLY 132 +#define GPLL2_OUT_MAIN 133 +#define GPLL2_OUT_TEST 134 +#define GPLL3 135 +#define GPLL3_OUT_AUX 136 +#define GPLL3_OUT_AUX2 137 +#define GPLL3_OUT_EARLY 138 +#define GPLL3_OUT_MAIN 139 +#define GPLL3_OUT_TEST 140 +#define GPLL4 141 +#define GPLL4_OUT_AUX 142 +#define GPLL4_OUT_AUX2 143 +#define GPLL4_OUT_EARLY 144 +#define GPLL4_OUT_MAIN 145 +#define GPLL4_OUT_TEST 146 +#define GPLL5 147 +#define GPLL5_OUT_AUX 148 +#define GPLL5_OUT_AUX2 149 +#define GPLL5_OUT_EARLY 150 +#define GPLL5_OUT_MAIN 151 +#define GPLL5_OUT_TEST 152 +#define GPLL6 153 +#define GPLL6_OUT_AUX 154 +#define GPLL6_OUT_AUX2 155 +#define GPLL6_OUT_EARLY 156 +#define GPLL6_OUT_MAIN 157 +#define GPLL6_OUT_TEST 158 +#define HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 159 +#define HMSS_AHB_CLK_SRC 160 +#define HMSS_GPLL0_CLK_SRC 161 +#define HMSS_GPLL4_CLK_SRC 162 +#define HMSS_RBCPR_CLK_SRC 163 +#define PDM2_CLK_SRC 164 +#define QSPI_SER_CLK_SRC 165 +#define SDCC1_APPS_CLK_SRC 166 +#define SDCC1_ICE_CORE_CLK_SRC 167 +#define SDCC2_APPS_CLK_SRC 168 +#define UFS_AXI_CLK_SRC 169 +#define UFS_ICE_CORE_CLK_SRC 170 +#define UFS_PHY_AUX_CLK_SRC 171 +#define UFS_UNIPRO_CORE_CLK_SRC 172 +#define USB20_MASTER_CLK_SRC 173 +#define USB20_MOCK_UTMI_CLK_SRC 174 +#define USB30_MASTER_CLK_SRC 175 +#define USB30_MOCK_UTMI_CLK_SRC 176 +#define USB3_PHY_AUX_CLK_SRC 177 +#define GPLL0_OUT_MSSCC 178 +#define GCC_UFS_AXI_HW_CTL_CLK 179 +#define GCC_UFS_ICE_CORE_HW_CTL_CLK 180 +#define GCC_UFS_PHY_AUX_HW_CTL_CLK 181 +#define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 182 +#define HLOS1_VOTE_TURING_ADSP_SMMU_CLK 183 +#define HLOS2_VOTE_TURING_ADSP_SMMU_CLK 184 + +/* Block resets */ +#define GCC_QUSB2PHY_PRIM_BCR 0 +#define GCC_QUSB2PHY_SEC_BCR 1 +#define GCC_UFS_BCR 2 +#define GCC_USB3_DP_PHY_BCR 3 +#define GCC_USB3_PHY_BCR 4 +#define GCC_USB3PHY_PHY_BCR 5 +#define GCC_USB_20_BCR 6 +#define GCC_USB_30_BCR 7 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 8 + +#endif diff --git a/include/dt-bindings/clock/qcom,gpu-msmfalcon.h b/include/dt-bindings/clock/qcom,gpu-msmfalcon.h deleted file mode 100644 index 2ef1e34db3a1..000000000000 --- a/include/dt-bindings/clock/qcom,gpu-msmfalcon.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_GPU_FALCON_H -#define _DT_BINDINGS_CLK_MSM_GPU_FALCON_H - -#define GFX3D_CLK_SRC 0 -#define GPU_PLL0_PLL 1 -#define GPU_PLL0_PLL_OUT_AUX 2 -#define GPU_PLL0_PLL_OUT_AUX2 3 -#define GPU_PLL0_PLL_OUT_EARLY 4 -#define GPU_PLL0_PLL_OUT_MAIN 5 -#define GPU_PLL0_PLL_OUT_TEST 6 -#define GPU_PLL1_PLL 7 -#define GPU_PLL1_PLL_OUT_AUX 8 -#define GPU_PLL1_PLL_OUT_AUX2 9 -#define GPU_PLL1_PLL_OUT_EARLY 10 -#define GPU_PLL1_PLL_OUT_MAIN 11 -#define GPU_PLL1_PLL_OUT_TEST 12 -#define GPUCC_CXO_CLK 13 -#define GPUCC_GFX3D_CLK 14 -#define GPUCC_RBBMTIMER_CLK 15 -#define GPUCC_RBCPR_CLK 16 -#define RBBMTIMER_CLK_SRC 17 -#define RBCPR_CLK_SRC 18 - -#define GPU_CX_GDSC 0 -#define GPU_GX_GDSC 1 - -#define GPUCC_GPU_CX_BCR 0 -#define GPUCC_GPU_GX_BCR 1 -#define GPUCC_RBCPR_BCR 2 -#define GPUCC_SPDM_BCR 3 - -#endif diff --git a/include/dt-bindings/clock/qcom,gpu-sdm660.h b/include/dt-bindings/clock/qcom,gpu-sdm660.h new file mode 100644 index 000000000000..80b49d3420e3 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpu-sdm660.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_GPU_660_H +#define _DT_BINDINGS_CLK_MSM_GPU_660_H + +#define GFX3D_CLK_SRC 0 +#define GPU_PLL0_PLL 1 +#define GPU_PLL0_PLL_OUT_AUX 2 +#define GPU_PLL0_PLL_OUT_AUX2 3 +#define GPU_PLL0_PLL_OUT_EARLY 4 +#define GPU_PLL0_PLL_OUT_MAIN 5 +#define GPU_PLL0_PLL_OUT_TEST 6 +#define GPU_PLL1_PLL 7 +#define GPU_PLL1_PLL_OUT_AUX 8 +#define GPU_PLL1_PLL_OUT_AUX2 9 +#define GPU_PLL1_PLL_OUT_EARLY 10 +#define GPU_PLL1_PLL_OUT_MAIN 11 +#define GPU_PLL1_PLL_OUT_TEST 12 +#define GPUCC_CXO_CLK 13 +#define GPUCC_GFX3D_CLK 14 +#define GPUCC_RBBMTIMER_CLK 15 +#define GPUCC_RBCPR_CLK 16 +#define RBBMTIMER_CLK_SRC 17 +#define RBCPR_CLK_SRC 18 + +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#define GPUCC_GPU_CX_BCR 0 +#define GPUCC_GPU_GX_BCR 1 +#define GPUCC_RBCPR_BCR 2 +#define GPUCC_SPDM_BCR 3 + +#endif diff --git a/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h b/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h deleted file mode 100644 index 91309b4616a6..000000000000 --- a/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h +++ /dev/null @@ -1,218 +0,0 @@ -/* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_CLK_MSM_MMCC_FALCON_H -#define _DT_BINDINGS_CLK_MSM_MMCC_FALCON_H - -#define MMSS_CAMSS_JPEG0_VOTE_CLK 0 -#define MMSS_CAMSS_JPEG0_DMA_VOTE_CLK 1 - -#define AHB_CLK_SRC 5 -#define BYTE0_CLK_SRC 6 -#define BYTE1_CLK_SRC 7 -#define CAMSS_GP0_CLK_SRC 8 -#define CAMSS_GP1_CLK_SRC 9 -#define CCI_CLK_SRC 10 -#define CPP_CLK_SRC 11 -#define CSI0_CLK_SRC 12 -#define CSI0PHYTIMER_CLK_SRC 13 -#define CSI1_CLK_SRC 14 -#define CSI1PHYTIMER_CLK_SRC 15 -#define CSI2_CLK_SRC 16 -#define CSI2PHYTIMER_CLK_SRC 17 -#define CSI3_CLK_SRC 18 -#define CSIPHY_CLK_SRC 19 -#define DP_AUX_CLK_SRC 20 -#define DP_CRYPTO_CLK_SRC 21 -#define DP_GTC_CLK_SRC 22 -#define DP_LINK_CLK_SRC 23 -#define DP_PIXEL_CLK_SRC 24 -#define ESC0_CLK_SRC 25 -#define ESC1_CLK_SRC 26 -#define JPEG0_CLK_SRC 27 -#define MCLK0_CLK_SRC 28 -#define MCLK1_CLK_SRC 29 -#define MCLK2_CLK_SRC 30 -#define MCLK3_CLK_SRC 31 -#define MDP_CLK_SRC 32 -#define MMPLL0_PLL 33 -#define MMPLL0_PLL_OUT_AUX 34 -#define MMPLL0_PLL_OUT_AUX2 35 -#define MMPLL0_PLL_OUT_EARLY 36 -#define MMPLL0_PLL_OUT_MAIN 37 -#define MMPLL0_PLL_OUT_TEST 38 -#define MMPLL10_PLL 39 -#define MMPLL10_PLL_OUT_AUX 40 -#define MMPLL10_PLL_OUT_AUX2 41 -#define MMPLL10_PLL_OUT_EARLY 42 -#define MMPLL10_PLL_OUT_MAIN 43 -#define MMPLL10_PLL_OUT_TEST 44 -#define MMPLL1_PLL 45 -#define MMPLL1_PLL_OUT_AUX 46 -#define MMPLL1_PLL_OUT_AUX2 47 -#define MMPLL1_PLL_OUT_EARLY 48 -#define MMPLL1_PLL_OUT_MAIN 49 -#define MMPLL1_PLL_OUT_TEST 50 -#define MMPLL3_PLL 51 -#define MMPLL3_PLL_OUT_AUX 52 -#define MMPLL3_PLL_OUT_AUX2 53 -#define MMPLL3_PLL_OUT_EARLY 54 -#define MMPLL3_PLL_OUT_MAIN 55 -#define MMPLL3_PLL_OUT_TEST 56 -#define MMPLL4_PLL 57 -#define MMPLL4_PLL_OUT_AUX 58 -#define MMPLL4_PLL_OUT_AUX2 59 -#define MMPLL4_PLL_OUT_EARLY 60 -#define MMPLL4_PLL_OUT_MAIN 61 -#define MMPLL4_PLL_OUT_TEST 62 -#define MMPLL5_PLL 63 -#define MMPLL5_PLL_OUT_AUX 64 -#define MMPLL5_PLL_OUT_AUX2 65 -#define MMPLL5_PLL_OUT_EARLY 66 -#define MMPLL5_PLL_OUT_MAIN 67 -#define MMPLL5_PLL_OUT_TEST 68 -#define MMPLL6_PLL 69 -#define MMPLL6_PLL_OUT_AUX 70 -#define MMPLL6_PLL_OUT_AUX2 71 -#define MMPLL6_PLL_OUT_EARLY 72 -#define MMPLL6_PLL_OUT_MAIN 73 -#define MMPLL6_PLL_OUT_TEST 74 -#define MMPLL7_PLL 75 -#define MMPLL7_PLL_OUT_AUX 76 -#define MMPLL7_PLL_OUT_AUX2 77 -#define MMPLL7_PLL_OUT_EARLY 78 -#define MMPLL7_PLL_OUT_MAIN 79 -#define MMPLL7_PLL_OUT_TEST 80 -#define MMPLL8_PLL 81 -#define MMPLL8_PLL_OUT_AUX 82 -#define MMPLL8_PLL_OUT_AUX2 83 -#define MMPLL8_PLL_OUT_EARLY 84 -#define MMPLL8_PLL_OUT_MAIN 85 -#define MMPLL8_PLL_OUT_TEST 86 -#define MMSS_BIMC_SMMU_AHB_CLK 87 -#define MMSS_BIMC_SMMU_AXI_CLK 88 -#define MMSS_CAMSS_AHB_CLK 89 -#define MMSS_CAMSS_CCI_AHB_CLK 90 -#define MMSS_CAMSS_CCI_CLK 91 -#define MMSS_CAMSS_CPHY_CSID0_CLK 92 -#define MMSS_CAMSS_CPHY_CSID1_CLK 93 -#define MMSS_CAMSS_CPHY_CSID2_CLK 94 -#define MMSS_CAMSS_CPHY_CSID3_CLK 95 -#define MMSS_CAMSS_CPP_AHB_CLK 96 -#define MMSS_CAMSS_CPP_AXI_CLK 97 -#define MMSS_CAMSS_CPP_CLK 98 -#define MMSS_CAMSS_CPP_VBIF_AHB_CLK 99 -#define MMSS_CAMSS_CSI0_AHB_CLK 100 -#define MMSS_CAMSS_CSI0_CLK 101 -#define MMSS_CAMSS_CSI0PHYTIMER_CLK 102 -#define MMSS_CAMSS_CSI0PIX_CLK 103 -#define MMSS_CAMSS_CSI0RDI_CLK 104 -#define MMSS_CAMSS_CSI1_AHB_CLK 105 -#define MMSS_CAMSS_CSI1_CLK 106 -#define MMSS_CAMSS_CSI1PHYTIMER_CLK 107 -#define MMSS_CAMSS_CSI1PIX_CLK 108 -#define MMSS_CAMSS_CSI1RDI_CLK 109 -#define MMSS_CAMSS_CSI2_AHB_CLK 110 -#define MMSS_CAMSS_CSI2_CLK 111 -#define MMSS_CAMSS_CSI2PHYTIMER_CLK 112 -#define MMSS_CAMSS_CSI2PIX_CLK 113 -#define MMSS_CAMSS_CSI2RDI_CLK 114 -#define MMSS_CAMSS_CSI3_AHB_CLK 115 -#define MMSS_CAMSS_CSI3_CLK 116 -#define MMSS_CAMSS_CSI3PIX_CLK 117 -#define MMSS_CAMSS_CSI3RDI_CLK 118 -#define MMSS_CAMSS_CSI_VFE0_CLK 119 -#define MMSS_CAMSS_CSI_VFE1_CLK 120 -#define MMSS_CAMSS_CSIPHY0_CLK 121 -#define MMSS_CAMSS_CSIPHY1_CLK 122 -#define MMSS_CAMSS_CSIPHY2_CLK 123 -#define MMSS_CAMSS_GP0_CLK 124 -#define MMSS_CAMSS_GP1_CLK 125 -#define MMSS_CAMSS_ISPIF_AHB_CLK 126 -#define MMSS_CAMSS_JPEG0_CLK 127 -#define MMSS_CAMSS_JPEG_AHB_CLK 128 -#define MMSS_CAMSS_JPEG_AXI_CLK 129 -#define MMSS_CAMSS_MCLK0_CLK 130 -#define MMSS_CAMSS_MCLK1_CLK 131 -#define MMSS_CAMSS_MCLK2_CLK 132 -#define MMSS_CAMSS_MCLK3_CLK 133 -#define MMSS_CAMSS_MICRO_AHB_CLK 134 -#define MMSS_CAMSS_TOP_AHB_CLK 135 -#define MMSS_CAMSS_VFE0_AHB_CLK 136 -#define MMSS_CAMSS_VFE0_CLK 137 -#define MMSS_CAMSS_VFE0_STREAM_CLK 138 -#define MMSS_CAMSS_VFE1_AHB_CLK 139 -#define MMSS_CAMSS_VFE1_CLK 140 -#define MMSS_CAMSS_VFE1_STREAM_CLK 141 -#define MMSS_CAMSS_VFE_VBIF_AHB_CLK 142 -#define MMSS_CAMSS_VFE_VBIF_AXI_CLK 143 -#define MMSS_CSIPHY_AHB2CRIF_CLK 144 -#define MMSS_CXO_CLK 145 -#define MMSS_MDSS_AHB_CLK 146 -#define MMSS_MDSS_AXI_CLK 147 -#define MMSS_MDSS_BYTE0_CLK 148 -#define MMSS_MDSS_BYTE0_INTF_CLK 149 -#define MMSS_MDSS_BYTE0_INTF_DIV_CLK 150 -#define MMSS_MDSS_BYTE1_CLK 151 -#define MMSS_MDSS_BYTE1_INTF_CLK 152 -#define MMSS_MDSS_DP_AUX_CLK 153 -#define MMSS_MDSS_DP_CRYPTO_CLK 154 -#define MMSS_MDSS_DP_GTC_CLK 155 -#define MMSS_MDSS_DP_LINK_CLK 156 -#define MMSS_MDSS_DP_LINK_INTF_CLK 157 -#define MMSS_MDSS_DP_PIXEL_CLK 158 -#define MMSS_MDSS_ESC0_CLK 159 -#define MMSS_MDSS_ESC1_CLK 160 -#define MMSS_MDSS_HDMI_DP_AHB_CLK 161 -#define MMSS_MDSS_MDP_CLK 162 -#define MMSS_MDSS_PCLK0_CLK 163 -#define MMSS_MDSS_PCLK1_CLK 164 -#define MMSS_MDSS_ROT_CLK 165 -#define MMSS_MDSS_VSYNC_CLK 166 -#define MMSS_MISC_AHB_CLK 167 -#define MMSS_MISC_CXO_CLK 168 -#define MMSS_MNOC_AHB_CLK 169 -#define MMSS_SNOC_DVM_AXI_CLK 170 -#define MMSS_THROTTLE_CAMSS_AHB_CLK 171 -#define MMSS_THROTTLE_CAMSS_AXI_CLK 172 -#define MMSS_THROTTLE_CAMSS_CXO_CLK 173 -#define MMSS_THROTTLE_MDSS_AHB_CLK 174 -#define MMSS_THROTTLE_MDSS_AXI_CLK 175 -#define MMSS_THROTTLE_MDSS_CXO_CLK 176 -#define MMSS_THROTTLE_VIDEO_AHB_CLK 177 -#define MMSS_THROTTLE_VIDEO_AXI_CLK 178 -#define MMSS_THROTTLE_VIDEO_CXO_CLK 179 -#define MMSS_VIDEO_AHB_CLK 180 -#define MMSS_VIDEO_AXI_CLK 181 -#define MMSS_VIDEO_CORE_CLK 182 -#define MMSS_VIDEO_SUBCORE0_CLK 183 -#define PCLK0_CLK_SRC 184 -#define PCLK1_CLK_SRC 185 -#define ROT_CLK_SRC 186 -#define VFE0_CLK_SRC 187 -#define VFE1_CLK_SRC 188 -#define VIDEO_CORE_CLK_SRC 189 -#define VSYNC_CLK_SRC 190 - -#define BIMC_SMMU_GDSC 0 -#define CAMSS_CPP_GDSC 1 -#define CAMSS_TOP_GDSC 2 -#define CAMSS_VFE0_GDSC 3 -#define CAMSS_VFE1_GDSC 4 -#define MDSS_GDSC 5 -#define VIDEO_SUBCORE0_GDSC 6 -#define VIDEO_TOP_GDSC 7 - -#define CAMSS_MICRO_BCR 0 - -#endif diff --git a/include/dt-bindings/clock/qcom,mmcc-sdm660.h b/include/dt-bindings/clock/qcom,mmcc-sdm660.h new file mode 100644 index 000000000000..cc7c0033d6ea --- /dev/null +++ b/include/dt-bindings/clock/qcom,mmcc-sdm660.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_MMCC_660_H +#define _DT_BINDINGS_CLK_MSM_MMCC_660_H + +#define MMSS_CAMSS_JPEG0_VOTE_CLK 0 +#define MMSS_CAMSS_JPEG0_DMA_VOTE_CLK 1 + +#define AHB_CLK_SRC 5 +#define BYTE0_CLK_SRC 6 +#define BYTE1_CLK_SRC 7 +#define CAMSS_GP0_CLK_SRC 8 +#define CAMSS_GP1_CLK_SRC 9 +#define CCI_CLK_SRC 10 +#define CPP_CLK_SRC 11 +#define CSI0_CLK_SRC 12 +#define CSI0PHYTIMER_CLK_SRC 13 +#define CSI1_CLK_SRC 14 +#define CSI1PHYTIMER_CLK_SRC 15 +#define CSI2_CLK_SRC 16 +#define CSI2PHYTIMER_CLK_SRC 17 +#define CSI3_CLK_SRC 18 +#define CSIPHY_CLK_SRC 19 +#define DP_AUX_CLK_SRC 20 +#define DP_CRYPTO_CLK_SRC 21 +#define DP_GTC_CLK_SRC 22 +#define DP_LINK_CLK_SRC 23 +#define DP_PIXEL_CLK_SRC 24 +#define ESC0_CLK_SRC 25 +#define ESC1_CLK_SRC 26 +#define JPEG0_CLK_SRC 27 +#define MCLK0_CLK_SRC 28 +#define MCLK1_CLK_SRC 29 +#define MCLK2_CLK_SRC 30 +#define MCLK3_CLK_SRC 31 +#define MDP_CLK_SRC 32 +#define MMPLL0_PLL 33 +#define MMPLL0_PLL_OUT_AUX 34 +#define MMPLL0_PLL_OUT_AUX2 35 +#define MMPLL0_PLL_OUT_EARLY 36 +#define MMPLL0_PLL_OUT_MAIN 37 +#define MMPLL0_PLL_OUT_TEST 38 +#define MMPLL10_PLL 39 +#define MMPLL10_PLL_OUT_AUX 40 +#define MMPLL10_PLL_OUT_AUX2 41 +#define MMPLL10_PLL_OUT_EARLY 42 +#define MMPLL10_PLL_OUT_MAIN 43 +#define MMPLL10_PLL_OUT_TEST 44 +#define MMPLL1_PLL 45 +#define MMPLL1_PLL_OUT_AUX 46 +#define MMPLL1_PLL_OUT_AUX2 47 +#define MMPLL1_PLL_OUT_EARLY 48 +#define MMPLL1_PLL_OUT_MAIN 49 +#define MMPLL1_PLL_OUT_TEST 50 +#define MMPLL3_PLL 51 +#define MMPLL3_PLL_OUT_AUX 52 +#define MMPLL3_PLL_OUT_AUX2 53 +#define MMPLL3_PLL_OUT_EARLY 54 +#define MMPLL3_PLL_OUT_MAIN 55 +#define MMPLL3_PLL_OUT_TEST 56 +#define MMPLL4_PLL 57 +#define MMPLL4_PLL_OUT_AUX 58 +#define MMPLL4_PLL_OUT_AUX2 59 +#define MMPLL4_PLL_OUT_EARLY 60 +#define MMPLL4_PLL_OUT_MAIN 61 +#define MMPLL4_PLL_OUT_TEST 62 +#define MMPLL5_PLL 63 +#define MMPLL5_PLL_OUT_AUX 64 +#define MMPLL5_PLL_OUT_AUX2 65 +#define MMPLL5_PLL_OUT_EARLY 66 +#define MMPLL5_PLL_OUT_MAIN 67 +#define MMPLL5_PLL_OUT_TEST 68 +#define MMPLL6_PLL 69 +#define MMPLL6_PLL_OUT_AUX 70 +#define MMPLL6_PLL_OUT_AUX2 71 +#define MMPLL6_PLL_OUT_EARLY 72 +#define MMPLL6_PLL_OUT_MAIN 73 +#define MMPLL6_PLL_OUT_TEST 74 +#define MMPLL7_PLL 75 +#define MMPLL7_PLL_OUT_AUX 76 +#define MMPLL7_PLL_OUT_AUX2 77 +#define MMPLL7_PLL_OUT_EARLY 78 +#define MMPLL7_PLL_OUT_MAIN 79 +#define MMPLL7_PLL_OUT_TEST 80 +#define MMPLL8_PLL 81 +#define MMPLL8_PLL_OUT_AUX 82 +#define MMPLL8_PLL_OUT_AUX2 83 +#define MMPLL8_PLL_OUT_EARLY 84 +#define MMPLL8_PLL_OUT_MAIN 85 +#define MMPLL8_PLL_OUT_TEST 86 +#define MMSS_BIMC_SMMU_AHB_CLK 87 +#define MMSS_BIMC_SMMU_AXI_CLK 88 +#define MMSS_CAMSS_AHB_CLK 89 +#define MMSS_CAMSS_CCI_AHB_CLK 90 +#define MMSS_CAMSS_CCI_CLK 91 +#define MMSS_CAMSS_CPHY_CSID0_CLK 92 +#define MMSS_CAMSS_CPHY_CSID1_CLK 93 +#define MMSS_CAMSS_CPHY_CSID2_CLK 94 +#define MMSS_CAMSS_CPHY_CSID3_CLK 95 +#define MMSS_CAMSS_CPP_AHB_CLK 96 +#define MMSS_CAMSS_CPP_AXI_CLK 97 +#define MMSS_CAMSS_CPP_CLK 98 +#define MMSS_CAMSS_CPP_VBIF_AHB_CLK 99 +#define MMSS_CAMSS_CSI0_AHB_CLK 100 +#define MMSS_CAMSS_CSI0_CLK 101 +#define MMSS_CAMSS_CSI0PHYTIMER_CLK 102 +#define MMSS_CAMSS_CSI0PIX_CLK 103 +#define MMSS_CAMSS_CSI0RDI_CLK 104 +#define MMSS_CAMSS_CSI1_AHB_CLK 105 +#define MMSS_CAMSS_CSI1_CLK 106 +#define MMSS_CAMSS_CSI1PHYTIMER_CLK 107 +#define MMSS_CAMSS_CSI1PIX_CLK 108 +#define MMSS_CAMSS_CSI1RDI_CLK 109 +#define MMSS_CAMSS_CSI2_AHB_CLK 110 +#define MMSS_CAMSS_CSI2_CLK 111 +#define MMSS_CAMSS_CSI2PHYTIMER_CLK 112 +#define MMSS_CAMSS_CSI2PIX_CLK 113 +#define MMSS_CAMSS_CSI2RDI_CLK 114 +#define MMSS_CAMSS_CSI3_AHB_CLK 115 +#define MMSS_CAMSS_CSI3_CLK 116 +#define MMSS_CAMSS_CSI3PIX_CLK 117 +#define MMSS_CAMSS_CSI3RDI_CLK 118 +#define MMSS_CAMSS_CSI_VFE0_CLK 119 +#define MMSS_CAMSS_CSI_VFE1_CLK 120 +#define MMSS_CAMSS_CSIPHY0_CLK 121 +#define MMSS_CAMSS_CSIPHY1_CLK 122 +#define MMSS_CAMSS_CSIPHY2_CLK 123 +#define MMSS_CAMSS_GP0_CLK 124 +#define MMSS_CAMSS_GP1_CLK 125 +#define MMSS_CAMSS_ISPIF_AHB_CLK 126 +#define MMSS_CAMSS_JPEG0_CLK 127 +#define MMSS_CAMSS_JPEG_AHB_CLK 128 +#define MMSS_CAMSS_JPEG_AXI_CLK 129 +#define MMSS_CAMSS_MCLK0_CLK 130 +#define MMSS_CAMSS_MCLK1_CLK 131 +#define MMSS_CAMSS_MCLK2_CLK 132 +#define MMSS_CAMSS_MCLK3_CLK 133 +#define MMSS_CAMSS_MICRO_AHB_CLK 134 +#define MMSS_CAMSS_TOP_AHB_CLK 135 +#define MMSS_CAMSS_VFE0_AHB_CLK 136 +#define MMSS_CAMSS_VFE0_CLK 137 +#define MMSS_CAMSS_VFE0_STREAM_CLK 138 +#define MMSS_CAMSS_VFE1_AHB_CLK 139 +#define MMSS_CAMSS_VFE1_CLK 140 +#define MMSS_CAMSS_VFE1_STREAM_CLK 141 +#define MMSS_CAMSS_VFE_VBIF_AHB_CLK 142 +#define MMSS_CAMSS_VFE_VBIF_AXI_CLK 143 +#define MMSS_CSIPHY_AHB2CRIF_CLK 144 +#define MMSS_CXO_CLK 145 +#define MMSS_MDSS_AHB_CLK 146 +#define MMSS_MDSS_AXI_CLK 147 +#define MMSS_MDSS_BYTE0_CLK 148 +#define MMSS_MDSS_BYTE0_INTF_CLK 149 +#define MMSS_MDSS_BYTE0_INTF_DIV_CLK 150 +#define MMSS_MDSS_BYTE1_CLK 151 +#define MMSS_MDSS_BYTE1_INTF_CLK 152 +#define MMSS_MDSS_DP_AUX_CLK 153 +#define MMSS_MDSS_DP_CRYPTO_CLK 154 +#define MMSS_MDSS_DP_GTC_CLK 155 +#define MMSS_MDSS_DP_LINK_CLK 156 +#define MMSS_MDSS_DP_LINK_INTF_CLK 157 +#define MMSS_MDSS_DP_PIXEL_CLK 158 +#define MMSS_MDSS_ESC0_CLK 159 +#define MMSS_MDSS_ESC1_CLK 160 +#define MMSS_MDSS_HDMI_DP_AHB_CLK 161 +#define MMSS_MDSS_MDP_CLK 162 +#define MMSS_MDSS_PCLK0_CLK 163 +#define MMSS_MDSS_PCLK1_CLK 164 +#define MMSS_MDSS_ROT_CLK 165 +#define MMSS_MDSS_VSYNC_CLK 166 +#define MMSS_MISC_AHB_CLK 167 +#define MMSS_MISC_CXO_CLK 168 +#define MMSS_MNOC_AHB_CLK 169 +#define MMSS_SNOC_DVM_AXI_CLK 170 +#define MMSS_THROTTLE_CAMSS_AHB_CLK 171 +#define MMSS_THROTTLE_CAMSS_AXI_CLK 172 +#define MMSS_THROTTLE_CAMSS_CXO_CLK 173 +#define MMSS_THROTTLE_MDSS_AHB_CLK 174 +#define MMSS_THROTTLE_MDSS_AXI_CLK 175 +#define MMSS_THROTTLE_MDSS_CXO_CLK 176 +#define MMSS_THROTTLE_VIDEO_AHB_CLK 177 +#define MMSS_THROTTLE_VIDEO_AXI_CLK 178 +#define MMSS_THROTTLE_VIDEO_CXO_CLK 179 +#define MMSS_VIDEO_AHB_CLK 180 +#define MMSS_VIDEO_AXI_CLK 181 +#define MMSS_VIDEO_CORE_CLK 182 +#define MMSS_VIDEO_SUBCORE0_CLK 183 +#define PCLK0_CLK_SRC 184 +#define PCLK1_CLK_SRC 185 +#define ROT_CLK_SRC 186 +#define VFE0_CLK_SRC 187 +#define VFE1_CLK_SRC 188 +#define VIDEO_CORE_CLK_SRC 189 +#define VSYNC_CLK_SRC 190 + +#define BIMC_SMMU_GDSC 0 +#define CAMSS_CPP_GDSC 1 +#define CAMSS_TOP_GDSC 2 +#define CAMSS_VFE0_GDSC 3 +#define CAMSS_VFE1_GDSC 4 +#define MDSS_GDSC 5 +#define VIDEO_SUBCORE0_GDSC 6 +#define VIDEO_TOP_GDSC 7 + +#define CAMSS_MICRO_BCR 0 + +#endif diff --git a/include/linux/qpnp/qpnp-revid.h b/include/linux/qpnp/qpnp-revid.h index 8d9bbfd67992..4023e3a683d3 100644 --- a/include/linux/qpnp/qpnp-revid.h +++ b/include/linux/qpnp/qpnp-revid.h @@ -177,9 +177,9 @@ /* PMI8998 */ #define PMI8998_SUBTYPE 0x15 -/* PMFALCON */ -#define PM2FALCON_SUBTYPE 0x1A -#define PMFALCON_SUBTYPE 0x1B +/* PM660 */ +#define PM660L_SUBTYPE 0x1A +#define PM660_SUBTYPE 0x1B #define PMI8998_V1P0_REV1 0x00 #define PMI8998_V1P0_REV2 0x00 diff --git a/include/soc/qcom/socinfo.h b/include/soc/qcom/socinfo.h index 3e5f7be53204..7cb8b0364596 100644 --- a/include/soc/qcom/socinfo.h +++ b/include/soc/qcom/socinfo.h @@ -94,10 +94,10 @@ of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,apq8998") #define early_machine_is_msmhamster() \ of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msmhamster") -#define early_machine_is_msmfalcon() \ - of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msmfalcon") -#define early_machine_is_apqfalcon() \ - of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,apqfalcon") +#define early_machine_is_sdm660() \ + of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,sdm660") +#define early_machine_is_sda660() \ + of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,sda660") #define early_machine_is_msmtriton() \ of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msmtriton") #else @@ -136,8 +136,8 @@ #define early_machine_is_msm8998() 0 #define early_machine_is_apq8998() 0 #define early_machine_is_msmhamster() 0 -#define early_machine_is_msmfalcon() 0 -#define early_machine_is_apqfalcon() 0 +#define early_machine_is_sdm660() 0 +#define early_machine_is_sda660() 0 #define early_machine_is_msmtriton() 0 #endif @@ -197,7 +197,7 @@ enum msm_cpu { MSM_CPU_8929, MSM_CPU_8998, MSM_CPU_HAMSTER, - MSM_CPU_FALCON, + MSM_CPU_660, MSM_CPU_TRITON, }; diff --git a/include/uapi/linux/msm_mdp.h b/include/uapi/linux/msm_mdp.h index 4df3845c159c..fca2a3c2d494 100644 --- a/include/uapi/linux/msm_mdp.h +++ b/include/uapi/linux/msm_mdp.h @@ -118,7 +118,7 @@ #define MDSS_MDP_HW_REV_116 MDSS_MDP_REV(1, 16, 0) /* msmtitanium */ #define MDSS_MDP_HW_REV_300 MDSS_MDP_REV(3, 0, 0) /* msm8998 */ #define MDSS_MDP_HW_REV_301 MDSS_MDP_REV(3, 0, 1) /* msm8998 v1.0 */ -#define MDSS_MDP_HW_REV_320 MDSS_MDP_REV(3, 2, 0) /* msmfalcon */ +#define MDSS_MDP_HW_REV_320 MDSS_MDP_REV(3, 2, 0) /* sdm660 */ enum { NOTIFY_UPDATE_INIT, diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 26a5356fb30e..8d623d01425b 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -765,11 +765,11 @@ config SND_SOC_WCD_CPE config AUDIO_EXT_CLK tristate - default y if SND_SOC_WCD9335=y || SND_SOC_WCD9330=y || SND_SOC_MSMFALCON_CDC=y + default y if SND_SOC_WCD9335=y || SND_SOC_WCD9330=y || SND_SOC_SDM660_CDC=y config SND_SOC_WCD_MBHC tristate - default y if (SND_SOC_MSM8909_WCD=y || SND_SOC_MSMFALCON_CDC=y || SND_SOC_WCD9335=y) && SND_SOC_MDMCALIFORNIUM!=y + default y if (SND_SOC_MSM8909_WCD=y || SND_SOC_SDM660_CDC=y || SND_SOC_WCD9335=y) && SND_SOC_MDMCALIFORNIUM!=y config SND_SOC_WCD_DSP_MGR tristate @@ -994,7 +994,7 @@ config SND_SOC_MSM_HDMI_CODEC_RX HDMI audio drivers should be built only if the platform supports hdmi panel. -source "sound/soc/codecs/msmfalcon_cdc/Kconfig" +source "sound/soc/codecs/sdm660_cdc/Kconfig" source "sound/soc/codecs/msm_sdw/Kconfig" endmenu diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 9dcdc517b9ea..5305cc6071e8 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -425,5 +425,5 @@ obj-$(CONFIG_SND_SOC_MSM_STUB) += snd-soc-msm-stub.o # Amp obj-$(CONFIG_SND_SOC_MAX9877) += snd-soc-max9877.o obj-$(CONFIG_SND_SOC_TPA6130A2) += snd-soc-tpa6130a2.o -obj-y += msmfalcon_cdc/ +obj-y += sdm660_cdc/ obj-y += msm_sdw/ diff --git a/sound/soc/codecs/msmfalcon_cdc/Kconfig b/sound/soc/codecs/msmfalcon_cdc/Kconfig deleted file mode 100644 index dc461a619781..000000000000 --- a/sound/soc/codecs/msmfalcon_cdc/Kconfig +++ /dev/null @@ -1,3 +0,0 @@ - -config SND_SOC_MSMFALCON_CDC - tristate "MSM Internal PMIC based codec" diff --git a/sound/soc/codecs/msmfalcon_cdc/Makefile b/sound/soc/codecs/msmfalcon_cdc/Makefile deleted file mode 100644 index 814308d9f5b0..000000000000 --- a/sound/soc/codecs/msmfalcon_cdc/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -snd-soc-msmfalcon-cdc-objs := msm-analog-cdc.o msm-digital-cdc.o msmfalcon-regmap.o -obj-$(CONFIG_SND_SOC_MSMFALCON_CDC) += snd-soc-msmfalcon-cdc.o msmfalcon-cdc-irq.o diff --git a/sound/soc/codecs/msmfalcon_cdc/msm-analog-cdc.c b/sound/soc/codecs/msmfalcon_cdc/msm-analog-cdc.c deleted file mode 100644 index 33c5e103dfe7..000000000000 --- a/sound/soc/codecs/msmfalcon_cdc/msm-analog-cdc.c +++ /dev/null @@ -1,4645 +0,0 @@ -/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "msm-analog-cdc.h" -#include "msmfalcon-cdc-irq.h" -#include "msmfalcon-cdc-registers.h" -#include "msm-cdc-common.h" -#include "../../msm/msmfalcon-common.h" -#include "../wcd-mbhc-v2.h" - -#define DRV_NAME "pmic_analog_codec" -#define MSMFALCON_CDC_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ - SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\ - SNDRV_PCM_RATE_48000) -#define MSMFALCON_CDC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ - SNDRV_PCM_FMTBIT_S24_LE) -#define MSM_DIG_CDC_STRING_LEN 80 -#define MSM_ANLG_CDC_VERSION_ENTRY_SIZE 32 - -#define CODEC_DT_MAX_PROP_SIZE 40 -#define MAX_ON_DEMAND_SUPPLY_NAME_LENGTH 64 -#define BUS_DOWN 1 - -/* - *50 Milliseconds sufficient for DSP bring up in the modem - * after Sub System Restart - */ -#define ADSP_STATE_READY_TIMEOUT_MS 50 - -enum { - BOOST_SWITCH = 0, - BOOST_ALWAYS, - BYPASS_ALWAYS, - BOOST_ON_FOREVER, -}; - -#define EAR_PMD 0 -#define EAR_PMU 1 -#define SPK_PMD 2 -#define SPK_PMU 3 - -#define MICBIAS_DEFAULT_VAL 1800000 -#define MICBIAS_MIN_VAL 1600000 -#define MICBIAS_STEP_SIZE 50000 - -#define DEFAULT_BOOST_VOLTAGE 5000 -#define MIN_BOOST_VOLTAGE 4000 -#define MAX_BOOST_VOLTAGE 5550 -#define BOOST_VOLTAGE_STEP 50 - -#define MSMFALCON_CDC_MBHC_BTN_COARSE_ADJ 100 /* in mV */ -#define MSMFALCON_CDC_MBHC_BTN_FINE_ADJ 12 /* in mV */ - -#define VOLTAGE_CONVERTER(value, min_value, step_size)\ - ((value - min_value)/step_size) - -enum { - RX_MIX1_INP_SEL_ZERO = 0, - RX_MIX1_INP_SEL_IIR1, - RX_MIX1_INP_SEL_IIR2, - RX_MIX1_INP_SEL_RX1, - RX_MIX1_INP_SEL_RX2, - RX_MIX1_INP_SEL_RX3, -}; - -static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); -static struct snd_soc_dai_driver msm_anlg_cdc_i2s_dai[]; -/* By default enable the internal speaker boost */ -static bool spkr_boost_en = true; -static bool initial_boot = true; - -static char on_demand_supply_name[][MAX_ON_DEMAND_SUPPLY_NAME_LENGTH] = { - "cdc-vdd-mic-bias", -}; - -static struct wcd_mbhc_register - wcd_mbhc_registers[WCD_MBHC_REG_FUNC_MAX] = { - WCD_MBHC_REGISTER("WCD_MBHC_L_DET_EN", - MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1, 0x80, 7, 0), - WCD_MBHC_REGISTER("WCD_MBHC_GND_DET_EN", - MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1, 0x40, 6, 0), - WCD_MBHC_REGISTER("WCD_MBHC_MECH_DETECTION_TYPE", - MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1, 0x20, 5, 0), - WCD_MBHC_REGISTER("WCD_MBHC_MIC_CLAMP_CTL", - MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1, 0x18, 3, 0), - WCD_MBHC_REGISTER("WCD_MBHC_ELECT_DETECTION_TYPE", - MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0x01, 0, 0), - WCD_MBHC_REGISTER("WCD_MBHC_HS_L_DET_PULL_UP_CTRL", - MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0xC0, 6, 0), - WCD_MBHC_REGISTER("WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL", - MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0x20, 5, 0), - WCD_MBHC_REGISTER("WCD_MBHC_HPHL_PLUG_TYPE", - MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0x10, 4, 0), - WCD_MBHC_REGISTER("WCD_MBHC_GND_PLUG_TYPE", - MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0x08, 3, 0), - WCD_MBHC_REGISTER("WCD_MBHC_SW_HPH_LP_100K_TO_GND", - MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0x01, 0, 0), - WCD_MBHC_REGISTER("WCD_MBHC_ELECT_SCHMT_ISRC", - MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0x06, 1, 0), - WCD_MBHC_REGISTER("WCD_MBHC_FSM_EN", - MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, 0x80, 7, 0), - WCD_MBHC_REGISTER("WCD_MBHC_INSREM_DBNC", - MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER, 0xF0, 4, 0), - WCD_MBHC_REGISTER("WCD_MBHC_BTN_DBNC", - MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER, 0x0C, 2, 0), - WCD_MBHC_REGISTER("WCD_MBHC_HS_VREF", - MSM89XX_PMIC_ANALOG_MBHC_BTN3_CTL, 0x03, 0, 0), - WCD_MBHC_REGISTER("WCD_MBHC_HS_COMP_RESULT", - MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT, 0x01, - 0, 0), - WCD_MBHC_REGISTER("WCD_MBHC_MIC_SCHMT_RESULT", - MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT, 0x02, - 1, 0), - WCD_MBHC_REGISTER("WCD_MBHC_HPHL_SCHMT_RESULT", - MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT, 0x08, - 3, 0), - WCD_MBHC_REGISTER("WCD_MBHC_HPHR_SCHMT_RESULT", - MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT, 0x04, - 2, 0), - WCD_MBHC_REGISTER("WCD_MBHC_OCP_FSM_EN", - MSM89XX_PMIC_ANALOG_RX_COM_OCP_CTL, 0x10, 4, 0), - WCD_MBHC_REGISTER("WCD_MBHC_BTN_RESULT", - MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT, 0xFF, 0, 0), - WCD_MBHC_REGISTER("WCD_MBHC_BTN_ISRC_CTL", - MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, 0x70, 4, 0), - WCD_MBHC_REGISTER("WCD_MBHC_ELECT_RESULT", - MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT, 0xFF, - 0, 0), - WCD_MBHC_REGISTER("WCD_MBHC_MICB_CTRL", - MSM89XX_PMIC_ANALOG_MICB_2_EN, 0xC0, 6, 0), - WCD_MBHC_REGISTER("WCD_MBHC_HPH_CNP_WG_TIME", - MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME, 0xFC, 2, 0), - WCD_MBHC_REGISTER("WCD_MBHC_HPHR_PA_EN", - MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, 0x10, 4, 0), - WCD_MBHC_REGISTER("WCD_MBHC_HPHL_PA_EN", - MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, 0x20, 5, 0), - WCD_MBHC_REGISTER("WCD_MBHC_HPH_PA_EN", - MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, 0x30, 4, 0), - WCD_MBHC_REGISTER("WCD_MBHC_SWCH_LEVEL_REMOVE", - MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT, - 0x10, 4, 0), - WCD_MBHC_REGISTER("WCD_MBHC_PULLDOWN_CTRL", - MSM89XX_PMIC_ANALOG_MICB_2_EN, 0x20, 5, 0), - WCD_MBHC_REGISTER("WCD_MBHC_ANC_DET_EN", 0, 0, 0, 0), - WCD_MBHC_REGISTER("WCD_MBHC_FSM_STATUS", 0, 0, 0, 0), - WCD_MBHC_REGISTER("WCD_MBHC_MUX_CTL", 0, 0, 0, 0), -}; - -/* Multiply gain_adj and offset by 1000 and 100 to avoid float arithmetic */ -static const struct wcd_imped_i_ref imped_i_ref[] = { - {I_h4_UA, 8, 800, 9000, 10000}, - {I_pt5_UA, 10, 100, 990, 4600}, - {I_14_UA, 17, 14, 1050, 700}, - {I_l4_UA, 10, 4, 1165, 110}, - {I_1_UA, 0, 1, 1200, 65}, -}; - -static const struct wcd_mbhc_intr intr_ids = { - .mbhc_sw_intr = MSM89XX_IRQ_MBHC_HS_DET, - .mbhc_btn_press_intr = MSM89XX_IRQ_MBHC_PRESS, - .mbhc_btn_release_intr = MSM89XX_IRQ_MBHC_RELEASE, - .mbhc_hs_ins_intr = MSM89XX_IRQ_MBHC_INSREM_DET1, - .mbhc_hs_rem_intr = MSM89XX_IRQ_MBHC_INSREM_DET, - .hph_left_ocp = MSM89XX_IRQ_HPHL_OCP, - .hph_right_ocp = MSM89XX_IRQ_HPHR_OCP, -}; - -static int msm_anlg_cdc_dt_parse_vreg_info(struct device *dev, - struct msmfalcon_cdc_regulator *vreg, - const char *vreg_name, - bool ondemand); -static struct msmfalcon_cdc_pdata *msm_anlg_cdc_populate_dt_pdata( - struct device *dev); -static int msm_anlg_cdc_enable_ext_mb_source(struct wcd_mbhc *wcd_mbhc, - bool turn_on); -static void msm_anlg_cdc_trim_btn_reg(struct snd_soc_codec *codec); -static void msm_anlg_cdc_set_micb_v(struct snd_soc_codec *codec); -static void msm_anlg_cdc_set_boost_v(struct snd_soc_codec *codec); -static void msm_anlg_cdc_set_auto_zeroing(struct snd_soc_codec *codec, - bool enable); -static void msm_anlg_cdc_configure_cap(struct snd_soc_codec *codec, - bool micbias1, bool micbias2); -static bool msm_anlg_cdc_use_mb(struct snd_soc_codec *codec); - -static int get_codec_version(struct msmfalcon_cdc_priv *msmfalcon_cdc) -{ - if (msmfalcon_cdc->codec_version == DRAX_CDC) - return DRAX_CDC; - else if (msmfalcon_cdc->codec_version == DIANGU) - return DIANGU; - else if (msmfalcon_cdc->codec_version == CAJON_2_0) - return CAJON_2_0; - else if (msmfalcon_cdc->codec_version == CAJON) - return CAJON; - else if (msmfalcon_cdc->codec_version == CONGA) - return CONGA; - else if (msmfalcon_cdc->pmic_rev == TOMBAK_2_0) - return TOMBAK_2_0; - else if (msmfalcon_cdc->pmic_rev == TOMBAK_1_0) - return TOMBAK_1_0; - - pr_err("%s: unsupported codec version\n", __func__); - return UNSUPPORTED; -} - -static void wcd_mbhc_meas_imped(struct snd_soc_codec *codec, - s16 *impedance_l, s16 *impedance_r) -{ - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - if ((msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_BOTH) || - (msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_HPHL)) { - /* Enable ZDET_L_MEAS_EN */ - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, - 0x08, 0x08); - /* Wait for 2ms for measurement to complete */ - usleep_range(2000, 2100); - /* Read Left impedance value from Result1 */ - *impedance_l = snd_soc_read(codec, - MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT); - /* Enable ZDET_R_MEAS_EN */ - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, - 0x08, 0x00); - } - if ((msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_BOTH) || - (msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_HPHR)) { - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, - 0x04, 0x04); - /* Wait for 2ms for measurement to complete */ - usleep_range(2000, 2100); - /* Read Right impedance value from Result1 */ - *impedance_r = snd_soc_read(codec, - MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, - 0x04, 0x00); - } -} - -static void msm_anlg_cdc_set_ref_current(struct snd_soc_codec *codec, - enum wcd_curr_ref curr_ref) -{ - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - dev_dbg(codec->dev, "%s: curr_ref: %d\n", __func__, curr_ref); - - if (get_codec_version(msmfalcon_cdc) < CAJON) - dev_dbg(codec->dev, "%s: Setting ref current not required\n", - __func__); - - msmfalcon_cdc->imped_i_ref = imped_i_ref[curr_ref]; - - switch (curr_ref) { - case I_h4_UA: - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MICB_2_EN, - 0x07, 0x01); - break; - case I_pt5_UA: - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MICB_2_EN, - 0x07, 0x04); - break; - case I_14_UA: - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MICB_2_EN, - 0x07, 0x03); - break; - case I_l4_UA: - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MICB_2_EN, - 0x07, 0x01); - break; - case I_1_UA: - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MICB_2_EN, - 0x07, 0x00); - break; - default: - pr_debug("%s: No ref current set\n", __func__); - break; - } -} - -static bool msm_anlg_cdc_adj_ref_current(struct snd_soc_codec *codec, - s16 *impedance_l, s16 *impedance_r) -{ - int i = 2; - s16 compare_imp = 0; - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - if (msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_HPHR) - compare_imp = *impedance_r; - else - compare_imp = *impedance_l; - - if (get_codec_version(msmfalcon_cdc) < CAJON) { - dev_dbg(codec->dev, - "%s: Reference current adjustment not required\n", - __func__); - return false; - } - - while (compare_imp < imped_i_ref[i].min_val) { - msm_anlg_cdc_set_ref_current(codec, imped_i_ref[++i].curr_ref); - wcd_mbhc_meas_imped(codec, impedance_l, impedance_r); - compare_imp = (msmfalcon_cdc->imped_det_pin == - WCD_MBHC_DET_HPHR) ? *impedance_r : *impedance_l; - if (i >= I_1_UA) - break; - } - return true; -} - -void msm_anlg_cdc_spk_ext_pa_cb( - int (*codec_spk_ext_pa)(struct snd_soc_codec *codec, - int enable), struct snd_soc_codec *codec) -{ - struct msmfalcon_cdc_priv *msmfalcon_cdc; - - if (!codec) { - pr_err("%s: NULL codec pointer!\n", __func__); - return; - } - - msmfalcon_cdc = snd_soc_codec_get_drvdata(codec); - - dev_dbg(codec->dev, "%s: Enter\n", __func__); - msmfalcon_cdc->codec_spk_ext_pa_cb = codec_spk_ext_pa; -} - -static void msm_anlg_cdc_compute_impedance(struct snd_soc_codec *codec, s16 l, - s16 r, uint32_t *zl, uint32_t *zr, - bool high) -{ - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - uint32_t rl = 0, rr = 0; - struct wcd_imped_i_ref R = msmfalcon_cdc->imped_i_ref; - int codec_ver = get_codec_version(msmfalcon_cdc); - - switch (codec_ver) { - case TOMBAK_1_0: - case TOMBAK_2_0: - case CONGA: - if (high) { - dev_dbg(codec->dev, - "%s: This plug has high range impedance\n", - __func__); - rl = (uint32_t)(((100 * (l * 400 - 200))/96) - 230); - rr = (uint32_t)(((100 * (r * 400 - 200))/96) - 230); - } else { - dev_dbg(codec->dev, - "%s: This plug has low range impedance\n", - __func__); - rl = (uint32_t)(((1000 * (l * 2 - 1))/1165) - (13/10)); - rr = (uint32_t)(((1000 * (r * 2 - 1))/1165) - (13/10)); - } - break; - case CAJON: - case CAJON_2_0: - case DIANGU: - case DRAX_CDC: - if (msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_HPHL) { - rr = (uint32_t)(((DEFAULT_MULTIPLIER * (10 * r - 5)) - - (DEFAULT_OFFSET * DEFAULT_GAIN))/DEFAULT_GAIN); - rl = (uint32_t)(((10000 * (R.multiplier * (10 * l - 5))) - - R.offset * R.gain_adj)/(R.gain_adj * 100)); - } else if (msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_HPHR) { - rr = (uint32_t)(((10000 * (R.multiplier * (10 * r - 5))) - - R.offset * R.gain_adj)/(R.gain_adj * 100)); - rl = (uint32_t)(((DEFAULT_MULTIPLIER * (10 * l - 5))- - (DEFAULT_OFFSET * DEFAULT_GAIN))/DEFAULT_GAIN); - } else if (msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_NONE) { - rr = (uint32_t)(((DEFAULT_MULTIPLIER * (10 * r - 5)) - - (DEFAULT_OFFSET * DEFAULT_GAIN))/DEFAULT_GAIN); - rl = (uint32_t)(((DEFAULT_MULTIPLIER * (10 * l - 5))- - (DEFAULT_OFFSET * DEFAULT_GAIN))/DEFAULT_GAIN); - } else { - rr = (uint32_t)(((10000 * (R.multiplier * (10 * r - 5))) - - R.offset * R.gain_adj)/(R.gain_adj * 100)); - rl = (uint32_t)(((10000 * (R.multiplier * (10 * l - 5))) - - R.offset * R.gain_adj)/(R.gain_adj * 100)); - } - break; - default: - dev_dbg(codec->dev, "%s: No codec mentioned\n", __func__); - break; - } - *zl = rl; - *zr = rr; -} - -static struct firmware_cal *msm_anlg_cdc_get_hwdep_fw_cal( - struct wcd_mbhc *wcd_mbhc, - enum wcd_cal_type type) -{ - struct msmfalcon_cdc_priv *msmfalcon_cdc; - struct firmware_cal *hwdep_cal; - struct snd_soc_codec *codec = wcd_mbhc->codec; - - if (!codec) { - pr_err("%s: NULL codec pointer\n", __func__); - return NULL; - } - msmfalcon_cdc = snd_soc_codec_get_drvdata(codec); - hwdep_cal = wcdcal_get_fw_cal(msmfalcon_cdc->fw_data, type); - if (!hwdep_cal) { - dev_err(codec->dev, "%s: cal not sent by %d\n", - __func__, type); - return NULL; - } - return hwdep_cal; -} - -static void wcd9xxx_spmi_irq_control(struct snd_soc_codec *codec, - int irq, bool enable) -{ - if (enable) - wcd9xxx_spmi_enable_irq(irq); - else - wcd9xxx_spmi_disable_irq(irq); -} - -static void msm_anlg_cdc_mbhc_clk_setup(struct snd_soc_codec *codec, - bool enable) -{ - if (enable) - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, - 0x08, 0x08); - else - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, - 0x08, 0x00); -} - -static int msm_anlg_cdc_mbhc_map_btn_code_to_num(struct snd_soc_codec *codec) -{ - int btn_code; - int btn; - - btn_code = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT); - - switch (btn_code) { - case 0: - btn = 0; - break; - case 1: - btn = 1; - break; - case 3: - btn = 2; - break; - case 7: - btn = 3; - break; - case 15: - btn = 4; - break; - default: - btn = -EINVAL; - break; - }; - - return btn; -} - -static bool msm_anlg_cdc_spmi_lock_sleep(struct wcd_mbhc *mbhc, bool lock) -{ - if (lock) - return wcd9xxx_spmi_lock_sleep(); - wcd9xxx_spmi_unlock_sleep(); - return 0; -} - -static bool msm_anlg_cdc_micb_en_status(struct wcd_mbhc *mbhc, int micb_num) -{ - if (micb_num == MIC_BIAS_1) - return (snd_soc_read(mbhc->codec, - MSM89XX_PMIC_ANALOG_MICB_1_EN) & - 0x80); - if (micb_num == MIC_BIAS_2) - return (snd_soc_read(mbhc->codec, - MSM89XX_PMIC_ANALOG_MICB_2_EN) & - 0x80); - return false; -} - -static void msm_anlg_cdc_enable_master_bias(struct snd_soc_codec *codec, - bool enable) -{ - if (enable) - snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL, - 0x30, 0x30); - else - snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL, - 0x30, 0x00); -} - -static void msm_anlg_cdc_mbhc_common_micb_ctrl(struct snd_soc_codec *codec, - int event, bool enable) -{ - u16 reg; - u8 mask; - u8 val; - - switch (event) { - case MBHC_COMMON_MICB_PRECHARGE: - reg = MSM89XX_PMIC_ANALOG_MICB_1_CTL; - mask = 0x60; - val = (enable ? 0x60 : 0x00); - break; - case MBHC_COMMON_MICB_SET_VAL: - reg = MSM89XX_PMIC_ANALOG_MICB_1_VAL; - mask = 0xFF; - val = (enable ? 0xC0 : 0x00); - break; - case MBHC_COMMON_MICB_TAIL_CURR: - reg = MSM89XX_PMIC_ANALOG_MICB_1_EN; - mask = 0x04; - val = (enable ? 0x04 : 0x00); - break; - default: - dev_err(codec->dev, - "%s: Invalid event received\n", __func__); - return; - }; - snd_soc_update_bits(codec, reg, mask, val); -} - -static void msm_anlg_cdc_mbhc_internal_micbias_ctrl(struct snd_soc_codec *codec, - int micbias_num, - bool enable) -{ - if (micbias_num == 1) { - if (enable) - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MICB_1_INT_RBIAS, - 0x10, 0x10); - else - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MICB_1_INT_RBIAS, - 0x10, 0x00); - } -} - -static bool msm_anlg_cdc_mbhc_hph_pa_on_status(struct snd_soc_codec *codec) -{ - return (snd_soc_read(codec, MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN) & - 0x30) ? true : false; -} - -static void msm_anlg_cdc_mbhc_program_btn_thr(struct snd_soc_codec *codec, - s16 *btn_low, s16 *btn_high, - int num_btn, bool is_micbias) -{ - int i; - u32 course, fine, reg_val; - u16 reg_addr = MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL; - s16 *btn_voltage; - - btn_voltage = ((is_micbias) ? btn_high : btn_low); - - for (i = 0; i < num_btn; i++) { - course = (btn_voltage[i] / MSMFALCON_CDC_MBHC_BTN_COARSE_ADJ); - fine = ((btn_voltage[i] % MSMFALCON_CDC_MBHC_BTN_COARSE_ADJ) / - MSMFALCON_CDC_MBHC_BTN_FINE_ADJ); - - reg_val = (course << 5) | (fine << 2); - snd_soc_update_bits(codec, reg_addr, 0xFC, reg_val); - dev_dbg(codec->dev, - "%s: course: %d fine: %d reg_addr: %x reg_val: %x\n", - __func__, course, fine, reg_addr, reg_val); - reg_addr++; - } -} - -static void msm_anlg_cdc_mbhc_calc_impedance(struct wcd_mbhc *mbhc, - uint32_t *zl, uint32_t *zr) -{ - struct snd_soc_codec *codec = mbhc->codec; - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - s16 impedance_l, impedance_r; - s16 impedance_l_fixed; - s16 reg0, reg1, reg2, reg3, reg4; - bool high = false; - bool min_range_used = false; - - WCD_MBHC_RSC_ASSERT_LOCKED(mbhc); - reg0 = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER); - reg1 = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_MBHC_BTN2_ZDETH_CTL); - reg2 = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2); - reg3 = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_MICB_2_EN); - reg4 = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL); - - msmfalcon_cdc->imped_det_pin = WCD_MBHC_DET_BOTH; - mbhc->hph_type = WCD_MBHC_HPH_NONE; - - /* disable FSM and micbias and enable pullup*/ - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, - 0x80, 0x00); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MICB_2_EN, - 0xA5, 0x25); - /* - * Enable legacy electrical detection current sources - * and disable fast ramp and enable manual switching - * of extra capacitance - */ - dev_dbg(codec->dev, "%s: Setup for impedance det\n", __func__); - - msm_anlg_cdc_set_ref_current(codec, I_h4_UA); - - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, - 0x06, 0x02); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER, - 0x02, 0x02); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_BTN2_ZDETH_CTL, - 0x02, 0x00); - - dev_dbg(codec->dev, "%s: Start performing impedance detection\n", - __func__); - - wcd_mbhc_meas_imped(codec, &impedance_l, &impedance_r); - - if (impedance_l > 2 || impedance_r > 2) { - high = true; - if (!mbhc->mbhc_cfg->mono_stero_detection) { - /* Set ZDET_CHG to 0 to discharge ramp */ - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, - 0x02, 0x00); - /* wait 40ms for the discharge ramp to complete */ - usleep_range(40000, 40100); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL, - 0x03, 0x00); - msmfalcon_cdc->imped_det_pin = (impedance_l > 2 && - impedance_r > 2) ? - WCD_MBHC_DET_NONE : - ((impedance_l > 2) ? - WCD_MBHC_DET_HPHR : - WCD_MBHC_DET_HPHL); - if (msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_NONE) - goto exit; - } else { - if (get_codec_version(msmfalcon_cdc) >= CAJON) { - if (impedance_l == 63 && impedance_r == 63) { - dev_dbg(codec->dev, - "%s: HPHL and HPHR are floating\n", - __func__); - msmfalcon_cdc->imped_det_pin = - WCD_MBHC_DET_NONE; - mbhc->hph_type = WCD_MBHC_HPH_NONE; - } else if (impedance_l == 63 - && impedance_r < 63) { - dev_dbg(codec->dev, - "%s: Mono HS with HPHL floating\n", - __func__); - msmfalcon_cdc->imped_det_pin = - WCD_MBHC_DET_HPHR; - mbhc->hph_type = WCD_MBHC_HPH_MONO; - } else if (impedance_r == 63 && - impedance_l < 63) { - dev_dbg(codec->dev, - "%s: Mono HS with HPHR floating\n", - __func__); - msmfalcon_cdc->imped_det_pin = - WCD_MBHC_DET_HPHL; - mbhc->hph_type = WCD_MBHC_HPH_MONO; - } else if (impedance_l > 3 && impedance_r > 3 && - (impedance_l == impedance_r)) { - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, - 0x06, 0x06); - wcd_mbhc_meas_imped(codec, &impedance_l, - &impedance_r); - if (impedance_r == impedance_l) - dev_dbg(codec->dev, - "%s: Mono Headset\n", - __func__); - msmfalcon_cdc->imped_det_pin = - WCD_MBHC_DET_NONE; - mbhc->hph_type = - WCD_MBHC_HPH_MONO; - } else { - dev_dbg(codec->dev, - "%s: STEREO headset is found\n", - __func__); - msmfalcon_cdc->imped_det_pin = - WCD_MBHC_DET_BOTH; - mbhc->hph_type = WCD_MBHC_HPH_STEREO; - } - } - } - } - - msm_anlg_cdc_set_ref_current(codec, I_pt5_UA); - msm_anlg_cdc_set_ref_current(codec, I_14_UA); - - /* Enable RAMP_L , RAMP_R & ZDET_CHG*/ - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL, - 0x03, 0x03); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, - 0x02, 0x02); - /* wait for 50msec for the HW to apply ramp on HPHL and HPHR */ - usleep_range(50000, 50100); - /* Enable ZDET_DISCHG_CAP_CTL to add extra capacitance */ - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, - 0x01, 0x01); - /* wait for 5msec for the voltage to get stable */ - usleep_range(5000, 5100); - - wcd_mbhc_meas_imped(codec, &impedance_l, &impedance_r); - - min_range_used = msm_anlg_cdc_adj_ref_current(codec, - &impedance_l, &impedance_r); - if (!mbhc->mbhc_cfg->mono_stero_detection) { - /* Set ZDET_CHG to 0 to discharge ramp */ - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, - 0x02, 0x00); - /* wait for 40msec for the capacitor to discharge */ - usleep_range(40000, 40100); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL, - 0x03, 0x00); - goto exit; - } - - /* we are setting ref current to the minimun range or the measured - * value larger than the minimum value, so min_range_used is true. - * If the headset is mono headset with either HPHL or HPHR floating - * then we have already done the mono stereo detection and do not - * need to continue further. - */ - - if (!min_range_used || - msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_HPHL || - msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_HPHR) - goto exit; - - - /* Disable Set ZDET_CONN_RAMP_L and enable ZDET_CONN_FIXED_L */ - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL, - 0x02, 0x00); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_BTN1_ZDETM_CTL, - 0x02, 0x02); - /* Set ZDET_CHG to 0 */ - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, - 0x02, 0x00); - /* wait for 40msec for the capacitor to discharge */ - usleep_range(40000, 40100); - - /* Set ZDET_CONN_RAMP_R to 0 */ - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL, - 0x01, 0x00); - /* Enable ZDET_L_MEAS_EN */ - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, - 0x08, 0x08); - /* wait for 2msec for the HW to compute left inpedance value */ - usleep_range(2000, 2100); - /* Read Left impedance value from Result1 */ - impedance_l_fixed = snd_soc_read(codec, - MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT); - /* Disable ZDET_L_MEAS_EN */ - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, - 0x08, 0x00); - /* - * Assume impedance_l is L1, impedance_l_fixed is L2. - * If the following condition is met, we can take this - * headset as mono one with impedance of L2. - * Otherwise, take it as stereo with impedance of L1. - * Condition: - * abs[(L2-0.5L1)/(L2+0.5L1)] < abs [(L2-L1)/(L2+L1)] - */ - if ((abs(impedance_l_fixed - impedance_l/2) * - (impedance_l_fixed + impedance_l)) >= - (abs(impedance_l_fixed - impedance_l) * - (impedance_l_fixed + impedance_l/2))) { - dev_dbg(codec->dev, - "%s: STEREO plug type detected\n", - __func__); - mbhc->hph_type = WCD_MBHC_HPH_STEREO; - } else { - dev_dbg(codec->dev, - "%s: MONO plug type detected\n", - __func__); - mbhc->hph_type = WCD_MBHC_HPH_MONO; - impedance_l = impedance_l_fixed; - } - /* Enable ZDET_CHG */ - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, - 0x02, 0x02); - /* wait for 10msec for the capacitor to charge */ - usleep_range(10000, 10100); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL, - 0x02, 0x02); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_BTN1_ZDETM_CTL, - 0x02, 0x00); - /* Set ZDET_CHG to 0 to discharge HPHL */ - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, - 0x02, 0x00); - /* wait for 40msec for the capacitor to discharge */ - usleep_range(40000, 40100); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL, - 0x02, 0x00); - -exit: - snd_soc_write(codec, MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, reg4); - snd_soc_write(codec, MSM89XX_PMIC_ANALOG_MICB_2_EN, reg3); - snd_soc_write(codec, MSM89XX_PMIC_ANALOG_MBHC_BTN2_ZDETH_CTL, reg1); - snd_soc_write(codec, MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER, reg0); - snd_soc_write(codec, MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, reg2); - msm_anlg_cdc_compute_impedance(codec, impedance_l, impedance_r, - zl, zr, high); - - dev_dbg(codec->dev, "%s: RL %d ohm, RR %d ohm\n", __func__, *zl, *zr); - dev_dbg(codec->dev, "%s: Impedance detection completed\n", __func__); -} - -static int msm_anlg_cdc_dig_register_notifier(void *handle, - struct notifier_block *nblock, - bool enable) -{ - struct msmfalcon_cdc *handle_cdc = handle; - - if (enable) - return blocking_notifier_chain_register(&handle_cdc->notifier, - nblock); - return blocking_notifier_chain_unregister(&handle_cdc->notifier, - nblock); -} - -static int msm_anlg_cdc_mbhc_register_notifier(struct wcd_mbhc *wcd_mbhc, - struct notifier_block *nblock, - bool enable) -{ - struct snd_soc_codec *codec = wcd_mbhc->codec; - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - if (enable) - return blocking_notifier_chain_register( - &msmfalcon_cdc->notifier, - nblock); - - return blocking_notifier_chain_unregister(&msmfalcon_cdc->notifier, - nblock); -} - -static int msm_anlg_cdc_request_irq(struct snd_soc_codec *codec, - int irq, irq_handler_t handler, - const char *name, void *data) -{ - return wcd9xxx_spmi_request_irq(irq, handler, name, data); -} - -static int msm_anlg_cdc_free_irq(struct snd_soc_codec *codec, - int irq, void *data) -{ - return wcd9xxx_spmi_free_irq(irq, data); -} - -static const struct wcd_mbhc_cb mbhc_cb = { - .enable_mb_source = msm_anlg_cdc_enable_ext_mb_source, - .trim_btn_reg = msm_anlg_cdc_trim_btn_reg, - .compute_impedance = msm_anlg_cdc_mbhc_calc_impedance, - .set_micbias_value = msm_anlg_cdc_set_micb_v, - .set_auto_zeroing = msm_anlg_cdc_set_auto_zeroing, - .get_hwdep_fw_cal = msm_anlg_cdc_get_hwdep_fw_cal, - .set_cap_mode = msm_anlg_cdc_configure_cap, - .register_notifier = msm_anlg_cdc_mbhc_register_notifier, - .request_irq = msm_anlg_cdc_request_irq, - .irq_control = wcd9xxx_spmi_irq_control, - .free_irq = msm_anlg_cdc_free_irq, - .clk_setup = msm_anlg_cdc_mbhc_clk_setup, - .map_btn_code_to_num = msm_anlg_cdc_mbhc_map_btn_code_to_num, - .lock_sleep = msm_anlg_cdc_spmi_lock_sleep, - .micbias_enable_status = msm_anlg_cdc_micb_en_status, - .mbhc_bias = msm_anlg_cdc_enable_master_bias, - .mbhc_common_micb_ctrl = msm_anlg_cdc_mbhc_common_micb_ctrl, - .micb_internal = msm_anlg_cdc_mbhc_internal_micbias_ctrl, - .hph_pa_on_status = msm_anlg_cdc_mbhc_hph_pa_on_status, - .set_btn_thr = msm_anlg_cdc_mbhc_program_btn_thr, - .extn_use_mb = msm_anlg_cdc_use_mb, -}; - -static const uint32_t wcd_imped_val[] = {4, 8, 12, 13, 16, - 20, 24, 28, 32, - 36, 40, 44, 48}; - -static void msm_anlg_cdc_dig_notifier_call(struct snd_soc_codec *codec, - const enum dig_cdc_notify_event event) -{ - struct msmfalcon_cdc *msmfalcon_cdc = codec->control_data; - - pr_debug("%s: notifier call event %d\n", __func__, event); - blocking_notifier_call_chain(&msmfalcon_cdc->notifier, - event, NULL); -} - -static void msm_anlg_cdc_notifier_call(struct snd_soc_codec *codec, - const enum wcd_notify_event event) -{ - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - dev_dbg(codec->dev, "%s: notifier call event %d\n", __func__, event); - blocking_notifier_call_chain(&msmfalcon_cdc->notifier, event, - &msmfalcon_cdc->mbhc); -} - -static void msm_anlg_cdc_boost_on(struct snd_soc_codec *codec) -{ - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x0F, 0x0F); - snd_soc_write(codec, MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0xA5); - snd_soc_write(codec, MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3, 0x0F); - snd_soc_write(codec, MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL, 0x30); - if (get_codec_version(msmfalcon_cdc) < CAJON_2_0) - snd_soc_write(codec, MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0x82); - else - snd_soc_write(codec, MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0xA2); - snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, - 0x69, 0x69); - snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG, - 0x01, 0x01); - snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SLOPE_COMP_IP_ZERO, - 0x88, 0x88); - snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, - 0x03, 0x03); - snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL, - 0xE1, 0xE1); - if (get_codec_version(msmfalcon_cdc) < CAJON_2_0) { - snd_soc_update_bits(codec, MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, - 0x20, 0x20); - /* Wait for 1ms after clock ctl enable */ - usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS); - snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_BOOST_EN_CTL, - 0xDF, 0xDF); - usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS); - } else { - snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_BOOST_EN_CTL, - 0x40, 0x00); - snd_soc_update_bits(codec, MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, - 0x20, 0x20); - snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_BOOST_EN_CTL, - 0x80, 0x80); - /* Wait for 500us after BOOST_EN to happen */ - usleep_range(500, 510); - snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_BOOST_EN_CTL, - 0x40, 0x40); - /* Wait for 500us after BOOST pulse_skip */ - usleep_range(500, 510); - } -} - -static void msm_anlg_cdc_boost_off(struct snd_soc_codec *codec) -{ - snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_BOOST_EN_CTL, - 0xDF, 0x5F); - snd_soc_update_bits(codec, MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, - 0x20, 0x00); -} - -static void msm_anlg_cdc_bypass_on(struct snd_soc_codec *codec) -{ - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - if (get_codec_version(msmfalcon_cdc) < CAJON_2_0) { - snd_soc_write(codec, - MSM89XX_PMIC_ANALOG_SEC_ACCESS, - 0xA5); - snd_soc_write(codec, - MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3, - 0x07); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_BYPASS_MODE, - 0x02, 0x02); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_BYPASS_MODE, - 0x01, 0x00); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_BYPASS_MODE, - 0x40, 0x40); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_BYPASS_MODE, - 0x80, 0x80); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_BOOST_EN_CTL, - 0xDF, 0xDF); - } else { - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, - 0x20, 0x20); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_BYPASS_MODE, - 0x20, 0x20); - } -} - -static void msm_anlg_cdc_bypass_off(struct snd_soc_codec *codec) -{ - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - if (get_codec_version(msmfalcon_cdc) < CAJON_2_0) { - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_BOOST_EN_CTL, - 0x80, 0x00); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_BYPASS_MODE, - 0x80, 0x00); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_BYPASS_MODE, - 0x02, 0x00); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_BYPASS_MODE, - 0x40, 0x00); - } else { - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_BYPASS_MODE, - 0x20, 0x00); - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, - 0x20, 0x00); - } -} - -static void msm_anlg_cdc_boost_mode_sequence(struct snd_soc_codec *codec, - int flag) -{ - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - if (flag == EAR_PMU) { - switch (msmfalcon_cdc->boost_option) { - case BOOST_SWITCH: - if (msmfalcon_cdc->ear_pa_boost_set) { - msm_anlg_cdc_boost_off(codec); - msm_anlg_cdc_bypass_on(codec); - } - break; - case BOOST_ALWAYS: - msm_anlg_cdc_boost_on(codec); - break; - case BYPASS_ALWAYS: - msm_anlg_cdc_bypass_on(codec); - break; - case BOOST_ON_FOREVER: - msm_anlg_cdc_boost_on(codec); - break; - default: - dev_err(codec->dev, - "%s: invalid boost option: %d\n", __func__, - msmfalcon_cdc->boost_option); - break; - } - } else if (flag == EAR_PMD) { - switch (msmfalcon_cdc->boost_option) { - case BOOST_SWITCH: - if (msmfalcon_cdc->ear_pa_boost_set) - msm_anlg_cdc_bypass_off(codec); - break; - case BOOST_ALWAYS: - msm_anlg_cdc_boost_off(codec); - /* 80ms for EAR boost to settle down */ - msleep(80); - break; - case BYPASS_ALWAYS: - /* nothing to do as bypass on always */ - break; - case BOOST_ON_FOREVER: - /* nothing to do as boost on forever */ - break; - default: - dev_err(codec->dev, - "%s: invalid boost option: %d\n", __func__, - msmfalcon_cdc->boost_option); - break; - } - } else if (flag == SPK_PMU) { - switch (msmfalcon_cdc->boost_option) { - case BOOST_SWITCH: - if (msmfalcon_cdc->spk_boost_set) { - msm_anlg_cdc_bypass_off(codec); - msm_anlg_cdc_boost_on(codec); - } - break; - case BOOST_ALWAYS: - msm_anlg_cdc_boost_on(codec); - break; - case BYPASS_ALWAYS: - msm_anlg_cdc_bypass_on(codec); - break; - case BOOST_ON_FOREVER: - msm_anlg_cdc_boost_on(codec); - break; - default: - dev_err(codec->dev, - "%s: invalid boost option: %d\n", __func__, - msmfalcon_cdc->boost_option); - break; - } - } else if (flag == SPK_PMD) { - switch (msmfalcon_cdc->boost_option) { - case BOOST_SWITCH: - if (msmfalcon_cdc->spk_boost_set) { - msm_anlg_cdc_boost_off(codec); - /* - * Add 40 ms sleep for the spk - * boost to settle down - */ - msleep(40); - } - break; - case BOOST_ALWAYS: - msm_anlg_cdc_boost_off(codec); - /* - * Add 40 ms sleep for the spk - * boost to settle down - */ - msleep(40); - break; - case BYPASS_ALWAYS: - /* nothing to do as bypass on always */ - break; - case BOOST_ON_FOREVER: - /* nothing to do as boost on forever */ - break; - default: - dev_err(codec->dev, - "%s: invalid boost option: %d\n", __func__, - msmfalcon_cdc->boost_option); - break; - } - } -} - -static int msm_anlg_cdc_dt_parse_vreg_info(struct device *dev, - struct msmfalcon_cdc_regulator *vreg, const char *vreg_name, - bool ondemand) -{ - int len, ret = 0; - const __be32 *prop; - char prop_name[CODEC_DT_MAX_PROP_SIZE]; - struct device_node *regnode = NULL; - u32 prop_val; - - snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE, "%s-supply", - vreg_name); - regnode = of_parse_phandle(dev->of_node, prop_name, 0); - - if (!regnode) { - dev_err(dev, "Looking up %s property in node %s failed\n", - prop_name, dev->of_node->full_name); - return -ENODEV; - } - - dev_dbg(dev, "Looking up %s property in node %s\n", - prop_name, dev->of_node->full_name); - - vreg->name = vreg_name; - vreg->ondemand = ondemand; - - snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE, - "qcom,%s-voltage", vreg_name); - prop = of_get_property(dev->of_node, prop_name, &len); - - if (!prop || (len != (2 * sizeof(__be32)))) { - dev_err(dev, "%s %s property\n", - prop ? "invalid format" : "no", prop_name); - return -EINVAL; - } - vreg->min_uv = be32_to_cpup(&prop[0]); - vreg->max_uv = be32_to_cpup(&prop[1]); - - snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE, - "qcom,%s-current", vreg_name); - - ret = of_property_read_u32(dev->of_node, prop_name, &prop_val); - if (ret) { - dev_err(dev, "Looking up %s property in node %s failed", - prop_name, dev->of_node->full_name); - return -EFAULT; - } - vreg->optimum_ua = prop_val; - - dev_dbg(dev, "%s: vol=[%d %d]uV, curr=[%d]uA, ond %d\n\n", vreg->name, - vreg->min_uv, vreg->max_uv, vreg->optimum_ua, vreg->ondemand); - return 0; -} - -static void msm_anlg_cdc_dt_parse_boost_info(struct snd_soc_codec *codec) -{ - struct msmfalcon_cdc_priv *msmfalcon_cdc_priv = - snd_soc_codec_get_drvdata(codec); - const char *prop_name = "qcom,cdc-boost-voltage"; - int boost_voltage, ret; - - ret = of_property_read_u32(codec->dev->of_node, prop_name, - &boost_voltage); - if (ret) { - dev_dbg(codec->dev, "Looking up %s property in node %s failed\n", - prop_name, codec->dev->of_node->full_name); - boost_voltage = DEFAULT_BOOST_VOLTAGE; - } - if (boost_voltage < MIN_BOOST_VOLTAGE || - boost_voltage > MAX_BOOST_VOLTAGE) { - dev_err(codec->dev, - "Incorrect boost voltage. Reverting to default\n"); - boost_voltage = DEFAULT_BOOST_VOLTAGE; - } - - msmfalcon_cdc_priv->boost_voltage = - VOLTAGE_CONVERTER(boost_voltage, MIN_BOOST_VOLTAGE, - BOOST_VOLTAGE_STEP); - dev_dbg(codec->dev, "Boost voltage value is: %d\n", - boost_voltage); -} - -static void msm_anlg_cdc_dt_parse_micbias_info(struct device *dev, - struct wcd_micbias_setting *micbias) -{ - const char *prop_name = "qcom,cdc-micbias-cfilt-mv"; - int ret; - - ret = of_property_read_u32(dev->of_node, prop_name, - &micbias->cfilt1_mv); - if (ret) { - dev_dbg(dev, "Looking up %s property in node %s failed", - prop_name, dev->of_node->full_name); - micbias->cfilt1_mv = MICBIAS_DEFAULT_VAL; - } -} - -static struct msmfalcon_cdc_pdata *msm_anlg_cdc_populate_dt_pdata( - struct device *dev) -{ - struct msmfalcon_cdc_pdata *pdata; - int ret, static_cnt, ond_cnt, idx, i; - const char *name = NULL; - const char *static_prop_name = "qcom,cdc-static-supplies"; - const char *ond_prop_name = "qcom,cdc-on-demand-supplies"; - - pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); - if (!pdata) - return NULL; - - static_cnt = of_property_count_strings(dev->of_node, static_prop_name); - if (IS_ERR_VALUE(static_cnt)) { - dev_err(dev, "%s: Failed to get static supplies %d\n", __func__, - static_cnt); - ret = -EINVAL; - goto err; - } - - /* On-demand supply list is an optional property */ - ond_cnt = of_property_count_strings(dev->of_node, ond_prop_name); - if (IS_ERR_VALUE(ond_cnt)) - ond_cnt = 0; - - WARN_ON(static_cnt <= 0 || ond_cnt < 0); - if ((static_cnt + ond_cnt) > ARRAY_SIZE(pdata->regulator)) { - dev_err(dev, "%s: Num of supplies %u > max supported %zd\n", - __func__, (static_cnt + ond_cnt), - ARRAY_SIZE(pdata->regulator)); - ret = -EINVAL; - goto err; - } - - for (idx = 0; idx < static_cnt; idx++) { - ret = of_property_read_string_index(dev->of_node, - static_prop_name, idx, - &name); - if (ret) { - dev_err(dev, "%s: of read string %s idx %d error %d\n", - __func__, static_prop_name, idx, ret); - goto err; - } - - dev_dbg(dev, "%s: Found static cdc supply %s\n", __func__, - name); - ret = msm_anlg_cdc_dt_parse_vreg_info(dev, - &pdata->regulator[idx], - name, false); - if (ret) { - dev_err(dev, "%s:err parsing vreg for %s idx %d\n", - __func__, name, idx); - goto err; - } - } - - for (i = 0; i < ond_cnt; i++, idx++) { - ret = of_property_read_string_index(dev->of_node, ond_prop_name, - i, &name); - if (ret) { - dev_err(dev, "%s: err parsing on_demand for %s idx %d\n", - __func__, ond_prop_name, i); - goto err; - } - - dev_dbg(dev, "%s: Found on-demand cdc supply %s\n", __func__, - name); - ret = msm_anlg_cdc_dt_parse_vreg_info(dev, - &pdata->regulator[idx], - name, true); - if (ret) { - dev_err(dev, "%s: err parsing vreg on_demand for %s idx %d\n", - __func__, name, idx); - goto err; - } - } - msm_anlg_cdc_dt_parse_micbias_info(dev, &pdata->micbias); - - return pdata; -err: - devm_kfree(dev, pdata); - dev_err(dev, "%s: Failed to populate DT data ret = %d\n", - __func__, ret); - return NULL; -} - -static int msm_anlg_cdc_codec_enable_on_demand_supply( - struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, int event) -{ - int ret = 0; - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - struct on_demand_supply *supply; - - if (w->shift >= ON_DEMAND_SUPPLIES_MAX) { - dev_err(codec->dev, "%s: error index > MAX Demand supplies", - __func__); - ret = -EINVAL; - goto out; - } - dev_dbg(codec->dev, "%s: supply: %s event: %d ref: %d\n", - __func__, on_demand_supply_name[w->shift], event, - atomic_read(&msmfalcon_cdc->on_demand_list[w->shift].ref)); - - supply = &msmfalcon_cdc->on_demand_list[w->shift]; - WARN_ONCE(!supply->supply, "%s isn't defined\n", - on_demand_supply_name[w->shift]); - if (!supply->supply) { - dev_err(codec->dev, "%s: err supply not present ond for %d", - __func__, w->shift); - goto out; - } - switch (event) { - case SND_SOC_DAPM_PRE_PMU: - if (atomic_inc_return(&supply->ref) == 1) - ret = regulator_enable(supply->supply); - if (ret) - dev_err(codec->dev, "%s: Failed to enable %s\n", - __func__, - on_demand_supply_name[w->shift]); - break; - case SND_SOC_DAPM_POST_PMD: - if (atomic_read(&supply->ref) == 0) { - dev_dbg(codec->dev, "%s: %s supply has been disabled.\n", - __func__, on_demand_supply_name[w->shift]); - goto out; - } - if (atomic_dec_return(&supply->ref) == 0) - ret = regulator_disable(supply->supply); - if (ret) - dev_err(codec->dev, "%s: Failed to disable %s\n", - __func__, - on_demand_supply_name[w->shift]); - break; - default: - break; - } -out: - return ret; -} - -static int msm_anlg_cdc_codec_enable_clock_block(struct snd_soc_codec *codec, - int enable) -{ - struct msm_asoc_mach_data *pdata = NULL; - - pdata = snd_soc_card_get_drvdata(codec->component.card); - if (enable) { - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL, 0x30, 0x30); - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x80, 0x80); - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL, 0x0C, 0x0C); - msm_anlg_cdc_dig_notifier_call(codec, DIG_CDC_EVENT_CLK_ON); - } else { - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL, 0x0C, 0x00); - msm_anlg_cdc_dig_notifier_call(codec, DIG_CDC_EVENT_CLK_OFF); - } - return 0; -} - -static int msm_anlg_cdc_codec_enable_charge_pump(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, - int event) -{ - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - dev_dbg(codec->dev, "%s: event = %d\n", __func__, event); - switch (event) { - case SND_SOC_DAPM_PRE_PMU: - msm_anlg_cdc_codec_enable_clock_block(codec, 1); - if (!(strcmp(w->name, "EAR CP"))) { - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, - 0x80, 0x80); - msm_anlg_cdc_boost_mode_sequence(codec, EAR_PMU); - } else if (get_codec_version(msmfalcon_cdc) >= DIANGU) { - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, - 0x80, 0x80); - } else { - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, - 0xC0, 0xC0); - } - break; - case SND_SOC_DAPM_POST_PMU: - /* Wait for 1ms post powerup of chargepump */ - usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS); - break; - case SND_SOC_DAPM_POST_PMD: - /* Wait for 1ms post powerdown of chargepump */ - usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS); - if (!(strcmp(w->name, "EAR CP"))) { - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, - 0x80, 0x00); - if (msmfalcon_cdc->boost_option != BOOST_ALWAYS) { - dev_dbg(codec->dev, - "%s: boost_option:%d, tear down ear\n", - __func__, msmfalcon_cdc->boost_option); - msm_anlg_cdc_boost_mode_sequence(codec, - EAR_PMD); - } - /* - * Reset pa select bit from ear to hph after ear pa - * is disabled and HPH DAC disable to reduce ear - * turn off pop and avoid HPH pop in concurrency - */ - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_EAR_CTL, 0x80, 0x00); - } else { - if (get_codec_version(msmfalcon_cdc) < DIANGU) - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, - 0x40, 0x00); - if (msmfalcon_cdc->rx_bias_count == 0) - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, - 0x80, 0x00); - dev_dbg(codec->dev, "%s: rx_bias_count = %d\n", - __func__, msmfalcon_cdc->rx_bias_count); - } - break; - } - return 0; -} - -static int msm_anlg_cdc_ear_pa_boost_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - ucontrol->value.integer.value[0] = - (msmfalcon_cdc->ear_pa_boost_set ? 1 : 0); - dev_dbg(codec->dev, "%s: msmfalcon_cdc->ear_pa_boost_set = %d\n", - __func__, msmfalcon_cdc->ear_pa_boost_set); - return 0; -} - -static int msm_anlg_cdc_ear_pa_boost_set(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", - __func__, ucontrol->value.integer.value[0]); - msmfalcon_cdc->ear_pa_boost_set = - (ucontrol->value.integer.value[0] ? true : false); - return 0; -} - -static int msm_anlg_cdc_loopback_mode_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msm_asoc_mach_data *pdata = NULL; - - pdata = snd_soc_card_get_drvdata(codec->component.card); - dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", - __func__, ucontrol->value.integer.value[0]); - - return pdata->lb_mode; -} - -static int msm_anlg_cdc_loopback_mode_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msm_asoc_mach_data *pdata = NULL; - - pdata = snd_soc_card_get_drvdata(codec->component.card); - dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", - __func__, ucontrol->value.integer.value[0]); - - switch (ucontrol->value.integer.value[0]) { - case 0: - pdata->lb_mode = false; - break; - case 1: - pdata->lb_mode = true; - break; - default: - return -EINVAL; - } - - return 0; -} - -static int msm_anlg_cdc_pa_gain_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - u8 ear_pa_gain; - struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - if (get_codec_version(msmfalcon_cdc) >= DIANGU) { - ear_pa_gain = snd_soc_read(codec, - MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC); - ear_pa_gain = (ear_pa_gain >> 1) & 0x3; - - if (ear_pa_gain == 0x00) { - ucontrol->value.integer.value[0] = 3; - } else if (ear_pa_gain == 0x01) { - ucontrol->value.integer.value[1] = 2; - } else if (ear_pa_gain == 0x02) { - ucontrol->value.integer.value[2] = 1; - } else if (ear_pa_gain == 0x03) { - ucontrol->value.integer.value[3] = 0; - } else { - dev_err(codec->dev, - "%s: ERROR: Unsupported Ear Gain = 0x%x\n", - __func__, ear_pa_gain); - return -EINVAL; - } - } else { - ear_pa_gain = snd_soc_read(codec, - MSM89XX_PMIC_ANALOG_RX_EAR_CTL); - ear_pa_gain = (ear_pa_gain >> 5) & 0x1; - if (ear_pa_gain == 0x00) { - ucontrol->value.integer.value[0] = 0; - } else if (ear_pa_gain == 0x01) { - ucontrol->value.integer.value[0] = 3; - } else { - dev_err(codec->dev, - "%s: ERROR: Unsupported Ear Gain = 0x%x\n", - __func__, ear_pa_gain); - return -EINVAL; - } - } - ucontrol->value.integer.value[0] = ear_pa_gain; - dev_dbg(codec->dev, "%s: ear_pa_gain = 0x%x\n", __func__, ear_pa_gain); - return 0; -} - -static int msm_anlg_cdc_pa_gain_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - u8 ear_pa_gain; - struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", - __func__, ucontrol->value.integer.value[0]); - - if (get_codec_version(msmfalcon_cdc) >= DIANGU) { - switch (ucontrol->value.integer.value[0]) { - case 0: - ear_pa_gain = 0x06; - break; - case 1: - ear_pa_gain = 0x04; - break; - case 2: - ear_pa_gain = 0x02; - break; - case 3: - ear_pa_gain = 0x00; - break; - default: - return -EINVAL; - } - snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, - 0x06, ear_pa_gain); - } else { - switch (ucontrol->value.integer.value[0]) { - case 0: - ear_pa_gain = 0x00; - break; - case 3: - ear_pa_gain = 0x20; - break; - case 1: - case 2: - default: - return -EINVAL; - } - snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_EAR_CTL, - 0x20, ear_pa_gain); - } - return 0; -} - -static int msm_anlg_cdc_hph_mode_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - if (msmfalcon_cdc->hph_mode == NORMAL_MODE) { - ucontrol->value.integer.value[0] = 0; - } else if (msmfalcon_cdc->hph_mode == HD2_MODE) { - ucontrol->value.integer.value[0] = 1; - } else { - dev_err(codec->dev, "%s: ERROR: Default HPH Mode= %d\n", - __func__, msmfalcon_cdc->hph_mode); - } - - dev_dbg(codec->dev, "%s: msmfalcon_cdc->hph_mode = %d\n", __func__, - msmfalcon_cdc->hph_mode); - return 0; -} - -static int msm_anlg_cdc_hph_mode_set(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", - __func__, ucontrol->value.integer.value[0]); - - switch (ucontrol->value.integer.value[0]) { - case 0: - msmfalcon_cdc->hph_mode = NORMAL_MODE; - break; - case 1: - if (get_codec_version(msmfalcon_cdc) >= DIANGU) - msmfalcon_cdc->hph_mode = HD2_MODE; - break; - default: - msmfalcon_cdc->hph_mode = NORMAL_MODE; - break; - } - dev_dbg(codec->dev, "%s: msmfalcon_cdc->hph_mode_set = %d\n", - __func__, msmfalcon_cdc->hph_mode); - return 0; -} - -static int msm_anlg_cdc_boost_option_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - if (msmfalcon_cdc->boost_option == BOOST_SWITCH) { - ucontrol->value.integer.value[0] = 0; - } else if (msmfalcon_cdc->boost_option == BOOST_ALWAYS) { - ucontrol->value.integer.value[0] = 1; - } else if (msmfalcon_cdc->boost_option == BYPASS_ALWAYS) { - ucontrol->value.integer.value[0] = 2; - } else if (msmfalcon_cdc->boost_option == BOOST_ON_FOREVER) { - ucontrol->value.integer.value[0] = 3; - } else { - dev_err(codec->dev, "%s: ERROR: Unsupported Boost option= %d\n", - __func__, msmfalcon_cdc->boost_option); - return -EINVAL; - } - - dev_dbg(codec->dev, "%s: msmfalcon_cdc->boost_option = %d\n", __func__, - msmfalcon_cdc->boost_option); - return 0; -} - -static int msm_anlg_cdc_boost_option_set(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", - __func__, ucontrol->value.integer.value[0]); - - switch (ucontrol->value.integer.value[0]) { - case 0: - msmfalcon_cdc->boost_option = BOOST_SWITCH; - break; - case 1: - msmfalcon_cdc->boost_option = BOOST_ALWAYS; - break; - case 2: - msmfalcon_cdc->boost_option = BYPASS_ALWAYS; - msm_anlg_cdc_bypass_on(codec); - break; - case 3: - msmfalcon_cdc->boost_option = BOOST_ON_FOREVER; - msm_anlg_cdc_boost_on(codec); - break; - default: - pr_err("%s: invalid boost option: %d\n", __func__, - msmfalcon_cdc->boost_option); - return -EINVAL; - } - dev_dbg(codec->dev, "%s: msmfalcon_cdc->boost_option_set = %d\n", - __func__, msmfalcon_cdc->boost_option); - return 0; -} - -static int msm_anlg_cdc_spk_boost_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - if (msmfalcon_cdc->spk_boost_set == false) { - ucontrol->value.integer.value[0] = 0; - } else if (msmfalcon_cdc->spk_boost_set == true) { - ucontrol->value.integer.value[0] = 1; - } else { - dev_err(codec->dev, "%s: ERROR: Unsupported Speaker Boost = %d\n", - __func__, msmfalcon_cdc->spk_boost_set); - return -EINVAL; - } - - dev_dbg(codec->dev, "%s: msmfalcon_cdc->spk_boost_set = %d\n", __func__, - msmfalcon_cdc->spk_boost_set); - return 0; -} - -static int msm_anlg_cdc_spk_boost_set(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", - __func__, ucontrol->value.integer.value[0]); - - switch (ucontrol->value.integer.value[0]) { - case 0: - msmfalcon_cdc->spk_boost_set = false; - break; - case 1: - msmfalcon_cdc->spk_boost_set = true; - break; - default: - return -EINVAL; - } - dev_dbg(codec->dev, "%s: msmfalcon_cdc->spk_boost_set = %d\n", - __func__, msmfalcon_cdc->spk_boost_set); - return 0; -} - -static int msm_anlg_cdc_ext_spk_boost_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - if (msmfalcon_cdc->ext_spk_boost_set == false) - ucontrol->value.integer.value[0] = 0; - else - ucontrol->value.integer.value[0] = 1; - - dev_dbg(codec->dev, "%s: msmfalcon_cdc->ext_spk_boost_set = %d\n", - __func__, msmfalcon_cdc->ext_spk_boost_set); - return 0; -} - -static int msm_anlg_cdc_ext_spk_boost_set(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", - __func__, ucontrol->value.integer.value[0]); - - switch (ucontrol->value.integer.value[0]) { - case 0: - msmfalcon_cdc->ext_spk_boost_set = false; - break; - case 1: - msmfalcon_cdc->ext_spk_boost_set = true; - break; - default: - return -EINVAL; - } - dev_dbg(codec->dev, "%s: msmfalcon_cdc->spk_boost_set = %d\n", - __func__, msmfalcon_cdc->spk_boost_set); - return 0; -} - - -static const char * const msm_anlg_cdc_loopback_mode_ctrl_text[] = { - "DISABLE", "ENABLE"}; -static const struct soc_enum msm_anlg_cdc_loopback_mode_ctl_enum[] = { - SOC_ENUM_SINGLE_EXT(2, msm_anlg_cdc_loopback_mode_ctrl_text), -}; - -static const char * const msm_anlg_cdc_ear_pa_boost_ctrl_text[] = { - "DISABLE", "ENABLE"}; -static const struct soc_enum msm_anlg_cdc_ear_pa_boost_ctl_enum[] = { - SOC_ENUM_SINGLE_EXT(2, msm_anlg_cdc_ear_pa_boost_ctrl_text), -}; - -static const char * const msm_anlg_cdc_ear_pa_gain_text[] = { - "POS_1P5_DB", "POS_3_DB", "POS_4P5_DB", "POS_6_DB"}; -static const struct soc_enum msm_anlg_cdc_ear_pa_gain_enum[] = { - SOC_ENUM_SINGLE_EXT(4, msm_anlg_cdc_ear_pa_gain_text), -}; - -static const char * const msm_anlg_cdc_boost_option_ctrl_text[] = { - "BOOST_SWITCH", "BOOST_ALWAYS", "BYPASS_ALWAYS", - "BOOST_ON_FOREVER"}; -static const struct soc_enum msm_anlg_cdc_boost_option_ctl_enum[] = { - SOC_ENUM_SINGLE_EXT(4, msm_anlg_cdc_boost_option_ctrl_text), -}; -static const char * const msm_anlg_cdc_spk_boost_ctrl_text[] = { - "DISABLE", "ENABLE"}; -static const struct soc_enum msm_anlg_cdc_spk_boost_ctl_enum[] = { - SOC_ENUM_SINGLE_EXT(2, msm_anlg_cdc_spk_boost_ctrl_text), -}; - -static const char * const msm_anlg_cdc_ext_spk_boost_ctrl_text[] = { - "DISABLE", "ENABLE"}; -static const struct soc_enum msm_anlg_cdc_ext_spk_boost_ctl_enum[] = { - SOC_ENUM_SINGLE_EXT(2, msm_anlg_cdc_ext_spk_boost_ctrl_text), -}; - -static const char * const msm_anlg_cdc_hph_mode_ctrl_text[] = { - "NORMAL", "HD2"}; -static const struct soc_enum msm_anlg_cdc_hph_mode_ctl_enum[] = { - SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(msm_anlg_cdc_hph_mode_ctrl_text), - msm_anlg_cdc_hph_mode_ctrl_text), -}; - -/*cut of frequency for high pass filter*/ -static const char * const cf_text[] = { - "MIN_3DB_4Hz", "MIN_3DB_75Hz", "MIN_3DB_150Hz" -}; - - -static const struct snd_kcontrol_new msm_anlg_cdc_snd_controls[] = { - - SOC_ENUM_EXT("RX HPH Mode", msm_anlg_cdc_hph_mode_ctl_enum[0], - msm_anlg_cdc_hph_mode_get, msm_anlg_cdc_hph_mode_set), - - SOC_ENUM_EXT("Boost Option", msm_anlg_cdc_boost_option_ctl_enum[0], - msm_anlg_cdc_boost_option_get, msm_anlg_cdc_boost_option_set), - - SOC_ENUM_EXT("EAR PA Boost", msm_anlg_cdc_ear_pa_boost_ctl_enum[0], - msm_anlg_cdc_ear_pa_boost_get, msm_anlg_cdc_ear_pa_boost_set), - - SOC_ENUM_EXT("EAR PA Gain", msm_anlg_cdc_ear_pa_gain_enum[0], - msm_anlg_cdc_pa_gain_get, msm_anlg_cdc_pa_gain_put), - - SOC_ENUM_EXT("Speaker Boost", msm_anlg_cdc_spk_boost_ctl_enum[0], - msm_anlg_cdc_spk_boost_get, msm_anlg_cdc_spk_boost_set), - - SOC_ENUM_EXT("Ext Spk Boost", msm_anlg_cdc_ext_spk_boost_ctl_enum[0], - msm_anlg_cdc_ext_spk_boost_get, msm_anlg_cdc_ext_spk_boost_set), - - SOC_ENUM_EXT("LOOPBACK Mode", msm_anlg_cdc_loopback_mode_ctl_enum[0], - msm_anlg_cdc_loopback_mode_get, msm_anlg_cdc_loopback_mode_put), - SOC_SINGLE_TLV("ADC1 Volume", MSM89XX_PMIC_ANALOG_TX_1_EN, 3, - 8, 0, analog_gain), - SOC_SINGLE_TLV("ADC2 Volume", MSM89XX_PMIC_ANALOG_TX_2_EN, 3, - 8, 0, analog_gain), - SOC_SINGLE_TLV("ADC3 Volume", MSM89XX_PMIC_ANALOG_TX_3_EN, 3, - 8, 0, analog_gain), - - -}; - -static int tombak_hph_impedance_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ret; - uint32_t zl, zr; - bool hphr; - struct soc_multi_mixer_control *mc; - struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *priv = snd_soc_codec_get_drvdata(codec); - - mc = (struct soc_multi_mixer_control *)(kcontrol->private_value); - - hphr = mc->shift; - ret = wcd_mbhc_get_impedance(&priv->mbhc, &zl, &zr); - if (ret) - dev_dbg(codec->dev, "%s: Failed to get mbhc imped", __func__); - dev_dbg(codec->dev, "%s: zl %u, zr %u\n", __func__, zl, zr); - ucontrol->value.integer.value[0] = hphr ? zr : zl; - - return 0; -} - -static const struct snd_kcontrol_new impedance_detect_controls[] = { - SOC_SINGLE_EXT("HPHL Impedance", 0, 0, UINT_MAX, 0, - tombak_hph_impedance_get, NULL), - SOC_SINGLE_EXT("HPHR Impedance", 0, 1, UINT_MAX, 0, - tombak_hph_impedance_get, NULL), -}; - -static int tombak_get_hph_type(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *priv = snd_soc_codec_get_drvdata(codec); - struct wcd_mbhc *mbhc; - - if (!priv) { - dev_err(codec->dev, - "%s: msmfalcon_cdc-wcd private data is NULL\n", - __func__); - return -EINVAL; - } - - mbhc = &priv->mbhc; - if (!mbhc) { - dev_err(codec->dev, "%s: mbhc not initialized\n", __func__); - return -EINVAL; - } - - ucontrol->value.integer.value[0] = (u32) mbhc->hph_type; - dev_dbg(codec->dev, "%s: hph_type = %u\n", __func__, mbhc->hph_type); - - return 0; -} - -static const struct snd_kcontrol_new hph_type_detect_controls[] = { - SOC_SINGLE_EXT("HPH Type", 0, 0, UINT_MAX, 0, - tombak_get_hph_type, NULL), -}; - -static const char * const rdac2_mux_text[] = { - "ZERO", "RX2", "RX1" -}; - -static const struct soc_enum rdac2_mux_enum = - SOC_ENUM_SINGLE(MSM89XX_PMIC_DIGITAL_CDC_CONN_HPHR_DAC_CTL, - 0, 3, rdac2_mux_text); - -static const char * const adc2_mux_text[] = { - "ZERO", "INP2", "INP3" -}; - -static const char * const ext_spk_text[] = { - "Off", "On" -}; - -static const char * const wsa_spk_text[] = { - "ZERO", "WSA" -}; - - - -static const char * const iir_inp1_text[] = { - "ZERO", "DEC1", "DEC2", "RX1", "RX2", "RX3" -}; - -static const struct soc_enum adc2_enum = - SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, - ARRAY_SIZE(adc2_mux_text), adc2_mux_text); - -static const struct soc_enum ext_spk_enum = - SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, - ARRAY_SIZE(ext_spk_text), ext_spk_text); - -static const struct soc_enum wsa_spk_enum = - SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, - ARRAY_SIZE(wsa_spk_text), wsa_spk_text); - - - -static const struct snd_kcontrol_new ext_spk_mux = - SOC_DAPM_ENUM("Ext Spk Switch Mux", ext_spk_enum); - - - -static const struct snd_kcontrol_new tx_adc2_mux = - SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum); - - -static const struct snd_kcontrol_new rdac2_mux = - SOC_DAPM_ENUM("RDAC2 MUX Mux", rdac2_mux_enum); - -static const char * const ear_text[] = { - "ZERO", "Switch", -}; - -static const struct soc_enum ear_enum = - SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(ear_text), ear_text); - -static const struct snd_kcontrol_new ear_pa_mux[] = { - SOC_DAPM_ENUM("EAR_S", ear_enum) -}; - -static const struct snd_kcontrol_new wsa_spk_mux[] = { - SOC_DAPM_ENUM("WSA Spk Switch", wsa_spk_enum) -}; - - - -static const char * const hph_text[] = { - "ZERO", "Switch", -}; - -static const struct soc_enum hph_enum = - SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(hph_text), hph_text); - -static const struct snd_kcontrol_new hphl_mux[] = { - SOC_DAPM_ENUM("HPHL", hph_enum) -}; - -static const struct snd_kcontrol_new hphr_mux[] = { - SOC_DAPM_ENUM("HPHR", hph_enum) -}; - -static const struct snd_kcontrol_new spkr_mux[] = { - SOC_DAPM_ENUM("SPK", hph_enum) -}; - -static const char * const lo_text[] = { - "ZERO", "Switch", -}; - -static const struct soc_enum lo_enum = - SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(hph_text), hph_text); - -static const struct snd_kcontrol_new lo_mux[] = { - SOC_DAPM_ENUM("LINE_OUT", lo_enum) -}; - -static void msm_anlg_cdc_codec_enable_adc_block(struct snd_soc_codec *codec, - int enable) -{ - struct msmfalcon_cdc_priv *wcd8x16 = snd_soc_codec_get_drvdata(codec); - - dev_dbg(codec->dev, "%s %d\n", __func__, enable); - - if (enable) { - wcd8x16->adc_count++; - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, - 0x20, 0x20); - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, - 0x10, 0x10); - } else { - wcd8x16->adc_count--; - if (!wcd8x16->adc_count) { - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, - 0x10, 0x00); - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, - 0x20, 0x0); - } - } -} - -static int msm_anlg_cdc_codec_enable_adc(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, - int event) -{ - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - u16 adc_reg; - u8 init_bit_shift; - - dev_dbg(codec->dev, "%s %d\n", __func__, event); - - adc_reg = MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_2; - - if (w->reg == MSM89XX_PMIC_ANALOG_TX_1_EN) - init_bit_shift = 5; - else if ((w->reg == MSM89XX_PMIC_ANALOG_TX_2_EN) || - (w->reg == MSM89XX_PMIC_ANALOG_TX_3_EN)) - init_bit_shift = 4; - else { - dev_err(codec->dev, "%s: Error, invalid adc register\n", - __func__); - return -EINVAL; - } - - switch (event) { - case SND_SOC_DAPM_PRE_PMU: - msm_anlg_cdc_codec_enable_adc_block(codec, 1); - if (w->reg == MSM89XX_PMIC_ANALOG_TX_2_EN) - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MICB_1_CTL, 0x02, 0x02); - /* - * Add delay of 10 ms to give sufficient time for the voltage - * to shoot up and settle so that the txfe init does not - * happen when the input voltage is changing too much. - */ - usleep_range(10000, 10010); - snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift, - 1 << init_bit_shift); - if (w->reg == MSM89XX_PMIC_ANALOG_TX_1_EN) - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_CONN_TX1_CTL, - 0x03, 0x00); - else if ((w->reg == MSM89XX_PMIC_ANALOG_TX_2_EN) || - (w->reg == MSM89XX_PMIC_ANALOG_TX_3_EN)) - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_CONN_TX2_CTL, - 0x03, 0x00); - /* Wait for 1ms to allow txfe settling time */ - usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS); - break; - case SND_SOC_DAPM_POST_PMU: - /* - * Add delay of 12 ms before deasserting the init - * to reduce the tx pop - */ - usleep_range(12000, 12010); - snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift, 0x00); - /* Wait for 1ms to allow txfe settling time post powerup */ - usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS); - break; - case SND_SOC_DAPM_POST_PMD: - msm_anlg_cdc_codec_enable_adc_block(codec, 0); - if (w->reg == MSM89XX_PMIC_ANALOG_TX_2_EN) - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MICB_1_CTL, 0x02, 0x00); - if (w->reg == MSM89XX_PMIC_ANALOG_TX_1_EN) - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_CONN_TX1_CTL, - 0x03, 0x02); - else if ((w->reg == MSM89XX_PMIC_ANALOG_TX_2_EN) || - (w->reg == MSM89XX_PMIC_ANALOG_TX_3_EN)) - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_CONN_TX2_CTL, - 0x03, 0x02); - - break; - } - return 0; -} - -static int msm_anlg_cdc_codec_enable_spk_pa(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, - int event) -{ - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - dev_dbg(codec->dev, "%s %d %s\n", __func__, event, w->name); - switch (event) { - case SND_SOC_DAPM_PRE_PMU: - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, 0x01, 0x01); - switch (msmfalcon_cdc->boost_option) { - case BOOST_SWITCH: - if (!msmfalcon_cdc->spk_boost_set) - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, - 0x10, 0x10); - break; - case BOOST_ALWAYS: - case BOOST_ON_FOREVER: - break; - case BYPASS_ALWAYS: - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, - 0x10, 0x10); - break; - default: - dev_err(codec->dev, - "%s: invalid boost option: %d\n", __func__, - msmfalcon_cdc->boost_option); - break; - } - /* Wait for 1ms after SPK_DAC CTL setting */ - usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, 0xE0, 0xE0); - if (get_codec_version(msmfalcon_cdc) != TOMBAK_1_0) - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_EAR_CTL, 0x01, 0x01); - break; - case SND_SOC_DAPM_POST_PMU: - /* Wait for 1ms after SPK_VBAT_LDO Enable */ - usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS); - switch (msmfalcon_cdc->boost_option) { - case BOOST_SWITCH: - if (msmfalcon_cdc->spk_boost_set) - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, - 0xEF, 0xEF); - else - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, - 0x10, 0x00); - break; - case BOOST_ALWAYS: - case BOOST_ON_FOREVER: - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, - 0xEF, 0xEF); - break; - case BYPASS_ALWAYS: - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x10, 0x00); - break; - default: - dev_err(codec->dev, - "%s: invalid boost option: %d\n", __func__, - msmfalcon_cdc->boost_option); - break; - } - msm_anlg_cdc_dig_notifier_call(codec, - DIG_CDC_EVENT_RX3_MUTE_OFF); - snd_soc_update_bits(codec, w->reg, 0x80, 0x80); - break; - case SND_SOC_DAPM_PRE_PMD: - msm_anlg_cdc_dig_notifier_call(codec, - DIG_CDC_EVENT_RX3_MUTE_ON); - /* - * Add 1 ms sleep for the mute to take effect - */ - usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x10, 0x10); - if (get_codec_version(msmfalcon_cdc) < CAJON_2_0) - msm_anlg_cdc_boost_mode_sequence(codec, SPK_PMD); - snd_soc_update_bits(codec, w->reg, 0x80, 0x00); - switch (msmfalcon_cdc->boost_option) { - case BOOST_SWITCH: - if (msmfalcon_cdc->spk_boost_set) - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, - 0xEF, 0x69); - break; - case BOOST_ALWAYS: - case BOOST_ON_FOREVER: - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, - 0xEF, 0x69); - break; - case BYPASS_ALWAYS: - break; - default: - dev_err(codec->dev, - "%s: invalid boost option: %d\n", __func__, - msmfalcon_cdc->boost_option); - break; - } - break; - case SND_SOC_DAPM_POST_PMD: - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, 0xE0, 0x00); - /* Wait for 1ms to allow setting time for spkr path disable */ - usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, 0x01, 0x00); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x10, 0x00); - if (get_codec_version(msmfalcon_cdc) != TOMBAK_1_0) - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_EAR_CTL, 0x01, 0x00); - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00); - if (get_codec_version(msmfalcon_cdc) >= CAJON_2_0) - msm_anlg_cdc_boost_mode_sequence(codec, SPK_PMD); - break; - } - return 0; -} - -static int msm_anlg_cdc_codec_enable_dig_clk(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, - int event) -{ - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - struct msm_asoc_mach_data *pdata = NULL; - - pdata = snd_soc_card_get_drvdata(codec->component.card); - - dev_dbg(codec->dev, "%s event %d w->name %s\n", __func__, - event, w->name); - switch (event) { - case SND_SOC_DAPM_PRE_PMU: - msm_anlg_cdc_codec_enable_clock_block(codec, 1); - snd_soc_update_bits(codec, w->reg, 0x80, 0x80); - break; - case SND_SOC_DAPM_POST_PMD: - if (msmfalcon_cdc->rx_bias_count == 0) - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, - 0x80, 0x00); - } - return 0; -} - - - -static bool msm_anlg_cdc_use_mb(struct snd_soc_codec *codec) -{ - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - if (get_codec_version(msmfalcon_cdc) < CAJON) - return true; - else - return false; -} - -static void msm_anlg_cdc_set_auto_zeroing(struct snd_soc_codec *codec, - bool enable) -{ - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - if (get_codec_version(msmfalcon_cdc) < CONGA) { - if (enable) - /* - * Set autozeroing for special headset detection and - * buttons to work. - */ - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MICB_2_EN, - 0x18, 0x10); - else - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MICB_2_EN, - 0x18, 0x00); - - } else { - dev_dbg(codec->dev, - "%s: Auto Zeroing is not required from CONGA\n", - __func__); - } -} - -static void msm_anlg_cdc_trim_btn_reg(struct snd_soc_codec *codec) -{ - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - if (get_codec_version(msmfalcon_cdc) == TOMBAK_1_0) { - pr_debug("%s: This device needs to be trimmed\n", __func__); - /* - * Calculate the trim value for each device used - * till is comes in production by hardware team - */ - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_SEC_ACCESS, - 0xA5, 0xA5); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_TRIM_CTRL2, - 0xFF, 0x30); - } else { - dev_dbg(codec->dev, "%s: This device is trimmed at ATE\n", - __func__); - } -} - -static int msm_anlg_cdc_enable_ext_mb_source(struct wcd_mbhc *wcd_mbhc, - bool turn_on) -{ - int ret = 0; - static int count; - struct snd_soc_codec *codec = wcd_mbhc->codec; - struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); - - dev_dbg(codec->dev, "%s turn_on: %d count: %d\n", __func__, turn_on, - count); - if (turn_on) { - if (!count) { - ret = snd_soc_dapm_force_enable_pin(dapm, - "MICBIAS_REGULATOR"); - snd_soc_dapm_sync(dapm); - } - count++; - } else { - if (count > 0) - count--; - if (!count) { - ret = snd_soc_dapm_disable_pin(dapm, - "MICBIAS_REGULATOR"); - snd_soc_dapm_sync(dapm); - } - } - - if (ret) - dev_err(codec->dev, "%s: Failed to %s external micbias source\n", - __func__, turn_on ? "enable" : "disabled"); - else - dev_dbg(codec->dev, "%s: %s external micbias source\n", - __func__, turn_on ? "Enabled" : "Disabled"); - - return ret; -} - -static int msm_anlg_cdc_codec_enable_micbias(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, - int event) -{ - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - u16 micb_int_reg; - char *internal1_text = "Internal1"; - char *internal2_text = "Internal2"; - char *internal3_text = "Internal3"; - char *external2_text = "External2"; - char *external_text = "External"; - bool micbias2; - - dev_dbg(codec->dev, "%s %d\n", __func__, event); - switch (w->reg) { - case MSM89XX_PMIC_ANALOG_MICB_1_EN: - case MSM89XX_PMIC_ANALOG_MICB_2_EN: - micb_int_reg = MSM89XX_PMIC_ANALOG_MICB_1_INT_RBIAS; - break; - default: - dev_err(codec->dev, - "%s: Error, invalid micbias register 0x%x\n", - __func__, w->reg); - return -EINVAL; - } - - micbias2 = (snd_soc_read(codec, MSM89XX_PMIC_ANALOG_MICB_2_EN) & 0x80); - switch (event) { - case SND_SOC_DAPM_PRE_PMU: - if (strnstr(w->name, internal1_text, strlen(w->name))) { - if (get_codec_version(msmfalcon_cdc) >= CAJON) - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2, - 0x02, 0x02); - snd_soc_update_bits(codec, micb_int_reg, 0x80, 0x80); - } else if (strnstr(w->name, internal2_text, strlen(w->name))) { - snd_soc_update_bits(codec, micb_int_reg, 0x10, 0x10); - snd_soc_update_bits(codec, w->reg, 0x60, 0x00); - } else if (strnstr(w->name, internal3_text, strlen(w->name))) { - snd_soc_update_bits(codec, micb_int_reg, 0x2, 0x2); - /* - * update MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2 - * for external bias only, not for external2. - */ - } else if (!strnstr(w->name, external2_text, strlen(w->name)) && - strnstr(w->name, external_text, - strlen(w->name))) { - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2, - 0x02, 0x02); - } - if (!strnstr(w->name, external_text, strlen(w->name))) - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MICB_1_EN, 0x05, 0x04); - if (w->reg == MSM89XX_PMIC_ANALOG_MICB_1_EN) - msm_anlg_cdc_configure_cap(codec, true, micbias2); - - break; - case SND_SOC_DAPM_POST_PMU: - if (get_codec_version(msmfalcon_cdc) <= TOMBAK_2_0) - /* - * Wait for 20ms post micbias enable - * for version < tombak 2.0. - */ - usleep_range(20000, 20100); - if (strnstr(w->name, internal1_text, strlen(w->name))) { - snd_soc_update_bits(codec, micb_int_reg, 0x40, 0x40); - } else if (strnstr(w->name, internal2_text, strlen(w->name))) { - snd_soc_update_bits(codec, micb_int_reg, 0x08, 0x08); - msm_anlg_cdc_notifier_call(codec, - WCD_EVENT_POST_MICBIAS_2_ON); - } else if (strnstr(w->name, internal3_text, 30)) { - snd_soc_update_bits(codec, micb_int_reg, 0x01, 0x01); - } else if (strnstr(w->name, external2_text, strlen(w->name))) { - msm_anlg_cdc_notifier_call(codec, - WCD_EVENT_POST_MICBIAS_2_ON); - } - break; - case SND_SOC_DAPM_POST_PMD: - if (strnstr(w->name, internal1_text, strlen(w->name))) { - snd_soc_update_bits(codec, micb_int_reg, 0xC0, 0x40); - } else if (strnstr(w->name, internal2_text, strlen(w->name))) { - msm_anlg_cdc_notifier_call(codec, - WCD_EVENT_POST_MICBIAS_2_OFF); - } else if (strnstr(w->name, internal3_text, 30)) { - snd_soc_update_bits(codec, micb_int_reg, 0x2, 0x0); - } else if (strnstr(w->name, external2_text, strlen(w->name))) { - /* - * send micbias turn off event to mbhc driver and then - * break, as no need to set MICB_1_EN register. - */ - msm_anlg_cdc_notifier_call(codec, - WCD_EVENT_POST_MICBIAS_2_OFF); - break; - } - if (w->reg == MSM89XX_PMIC_ANALOG_MICB_1_EN) - msm_anlg_cdc_configure_cap(codec, false, micbias2); - break; - } - return 0; -} - -static void update_clkdiv(void *handle, int val) -{ - struct msmfalcon_cdc *handle_cdc = handle; - struct snd_soc_codec *codec = handle_cdc->codec; - - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_TX_1_2_TXFE_CLKDIV, - 0xFF, val); -} - -static int get_cdc_version(void *handle) -{ - struct msmfalcon_cdc *handle_cdc = handle; - struct snd_soc_codec *codec = handle_cdc->codec; - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - return get_codec_version(msmfalcon_cdc); -} - -static int msmfalcon_wcd_codec_enable_vdd_spkr(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, - int event) -{ - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - int ret = 0; - - if (!msmfalcon_cdc->ext_spk_boost_set) { - dev_dbg(codec->dev, "%s: ext_boost not supported/disabled\n", - __func__); - return 0; - } - dev_dbg(codec->dev, "%s: %s %d\n", __func__, w->name, event); - switch (event) { - case SND_SOC_DAPM_PRE_PMU: - if (msmfalcon_cdc->spkdrv_reg) { - ret = regulator_enable(msmfalcon_cdc->spkdrv_reg); - if (ret) - dev_err(codec->dev, - "%s Failed to enable spkdrv reg %s\n", - __func__, MSM89XX_VDD_SPKDRV_NAME); - } - break; - case SND_SOC_DAPM_POST_PMD: - if (msmfalcon_cdc->spkdrv_reg) { - ret = regulator_disable(msmfalcon_cdc->spkdrv_reg); - if (ret) - dev_err(codec->dev, - "%s: Failed to disable spkdrv_reg %s\n", - __func__, MSM89XX_VDD_SPKDRV_NAME); - } - break; - } - return 0; -} - - -/* The register address is the same as other codec so it can use resmgr */ -static int msm_anlg_cdc_codec_enable_rx_bias(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, - int event) -{ - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - dev_dbg(codec->dev, "%s %d\n", __func__, event); - - switch (event) { - case SND_SOC_DAPM_PRE_PMU: - msmfalcon_cdc->rx_bias_count++; - if (msmfalcon_cdc->rx_bias_count == 1) { - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, - 0x80, 0x80); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, - 0x01, 0x01); - } - break; - case SND_SOC_DAPM_POST_PMD: - msmfalcon_cdc->rx_bias_count--; - if (msmfalcon_cdc->rx_bias_count == 0) { - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, - 0x01, 0x00); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, - 0x80, 0x00); - } - break; - } - dev_dbg(codec->dev, "%s rx_bias_count = %d\n", - __func__, msmfalcon_cdc->rx_bias_count); - return 0; -} - -static uint32_t wcd_get_impedance_value(uint32_t imped) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(wcd_imped_val) - 1; i++) { - if (imped >= wcd_imped_val[i] && - imped < wcd_imped_val[i + 1]) - break; - } - - pr_debug("%s: selected impedance value = %d\n", - __func__, wcd_imped_val[i]); - return wcd_imped_val[i]; -} - -static void wcd_imped_config(struct snd_soc_codec *codec, - uint32_t imped, bool set_gain) -{ - uint32_t value; - int codec_version; - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - value = wcd_get_impedance_value(imped); - - if (value < wcd_imped_val[0]) { - dev_dbg(codec->dev, - "%s, detected impedance is less than 4 Ohm\n", - __func__); - return; - } - - codec_version = get_codec_version(msmfalcon_cdc); - - if (set_gain) { - switch (codec_version) { - case TOMBAK_1_0: - case TOMBAK_2_0: - case CONGA: - /* - * For 32Ohm load and higher loads, Set 0x19E - * bit 5 to 1 (POS_0_DB_DI). For loads lower - * than 32Ohm (such as 16Ohm load), Set 0x19E - * bit 5 to 0 (POS_M4P5_DB_DI) - */ - if (value >= 32) - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_EAR_CTL, - 0x20, 0x20); - else - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_EAR_CTL, - 0x20, 0x00); - break; - case CAJON: - case CAJON_2_0: - case DIANGU: - case DRAX_CDC: - if (value >= 13) { - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_EAR_CTL, - 0x20, 0x20); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_NCP_VCTRL, - 0x07, 0x07); - } else { - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_EAR_CTL, - 0x20, 0x00); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_NCP_VCTRL, - 0x07, 0x04); - } - break; - } - } else { - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_EAR_CTL, - 0x20, 0x00); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_NCP_VCTRL, - 0x07, 0x04); - } - - dev_dbg(codec->dev, "%s: Exit\n", __func__); -} - -static int msm_anlg_cdc_hphl_dac_event(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, - int event) -{ - uint32_t impedl, impedr; - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - int ret; - - dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event); - ret = wcd_mbhc_get_impedance(&msmfalcon_cdc->mbhc, - &impedl, &impedr); - - switch (event) { - case SND_SOC_DAPM_PRE_PMU: - if (get_codec_version(msmfalcon_cdc) > CAJON) - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, - 0x08, 0x08); - if (get_codec_version(msmfalcon_cdc) == CAJON || - get_codec_version(msmfalcon_cdc) == CAJON_2_0) { - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST, - 0x80, 0x80); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST, - 0x80, 0x80); - } - if (get_codec_version(msmfalcon_cdc) > CAJON) - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, - 0x08, 0x00); - if (msmfalcon_cdc->hph_mode == HD2_MODE) - msm_anlg_cdc_dig_notifier_call(codec, - DIG_CDC_EVENT_PRE_RX1_INT_ON); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL, 0x02, 0x02); - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01); - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02); - if (!ret) - wcd_imped_config(codec, impedl, true); - else - dev_dbg(codec->dev, "Failed to get mbhc impedance %d\n", - ret); - break; - case SND_SOC_DAPM_POST_PMU: - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL, 0x02, 0x00); - break; - case SND_SOC_DAPM_POST_PMD: - wcd_imped_config(codec, impedl, false); - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00); - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x00); - if (msmfalcon_cdc->hph_mode == HD2_MODE) - msm_anlg_cdc_dig_notifier_call(codec, - DIG_CDC_EVENT_POST_RX1_INT_OFF); - break; - } - return 0; -} - -static int msm_anlg_cdc_lo_dac_event(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, - int event) -{ - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - - dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event); - - switch (event) { - case SND_SOC_DAPM_PRE_PMU: - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL, 0x20, 0x20); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL, 0x80, 0x80); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x08, 0x08); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x40, 0x40); - break; - case SND_SOC_DAPM_POST_PMU: - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x80, 0x80); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x08, 0x00); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL, 0x40, 0x40); - break; - case SND_SOC_DAPM_POST_PMD: - /* Wait for 20ms before powerdown of lineout_dac */ - usleep_range(20000, 20100); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x80, 0x00); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x40, 0x00); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x08, 0x00); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL, 0x80, 0x00); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL, 0x40, 0x00); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL, 0x20, 0x00); - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00); - break; - } - return 0; -} - -static int msm_anlg_cdc_hphr_dac_event(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, - int event) -{ - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event); - - switch (event) { - case SND_SOC_DAPM_PRE_PMU: - if (msmfalcon_cdc->hph_mode == HD2_MODE) - msm_anlg_cdc_dig_notifier_call(codec, - DIG_CDC_EVENT_PRE_RX2_INT_ON); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL, 0x02, 0x02); - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02); - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01); - break; - case SND_SOC_DAPM_POST_PMU: - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL, 0x02, 0x00); - break; - case SND_SOC_DAPM_POST_PMD: - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00); - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x00); - if (msmfalcon_cdc->hph_mode == HD2_MODE) - msm_anlg_cdc_dig_notifier_call(codec, - DIG_CDC_EVENT_POST_RX2_INT_OFF); - break; - } - return 0; -} - -static int msm_anlg_cdc_hph_pa_event(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, - int event) -{ - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - dev_dbg(codec->dev, "%s: %s event = %d\n", __func__, w->name, event); - - switch (event) { - case SND_SOC_DAPM_PRE_PMU: - if (w->shift == 5) - msm_anlg_cdc_notifier_call(codec, - WCD_EVENT_PRE_HPHL_PA_ON); - else if (w->shift == 4) - msm_anlg_cdc_notifier_call(codec, - WCD_EVENT_PRE_HPHR_PA_ON); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_NCP_FBCTRL, 0x20, 0x20); - break; - - case SND_SOC_DAPM_POST_PMU: - /* Wait for 7ms to allow setting time for HPH_PA Enable */ - usleep_range(7000, 7100); - if (w->shift == 5) { - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST, 0x04, 0x04); - msm_anlg_cdc_dig_notifier_call(codec, - DIG_CDC_EVENT_RX1_MUTE_OFF); - } else if (w->shift == 4) { - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST, 0x04, 0x04); - msm_anlg_cdc_dig_notifier_call(codec, - DIG_CDC_EVENT_RX2_MUTE_OFF); - } - break; - - case SND_SOC_DAPM_PRE_PMD: - if (w->shift == 5) { - msm_anlg_cdc_dig_notifier_call(codec, - DIG_CDC_EVENT_RX1_MUTE_ON); - /* Wait for 20ms after HPHL RX digital mute */ - msleep(20); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST, 0x04, 0x00); - msm_anlg_cdc_notifier_call(codec, - WCD_EVENT_PRE_HPHL_PA_OFF); - } else if (w->shift == 4) { - msm_anlg_cdc_dig_notifier_call(codec, - DIG_CDC_EVENT_RX2_MUTE_ON); - /* Wait for 20ms after HPHR RX digital mute */ - msleep(20); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST, 0x04, 0x00); - msm_anlg_cdc_notifier_call(codec, - WCD_EVENT_PRE_HPHR_PA_OFF); - } - if (get_codec_version(msmfalcon_cdc) >= CAJON) { - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_CNP, - 0xF0, 0x30); - } - break; - case SND_SOC_DAPM_POST_PMD: - if (w->shift == 5) { - clear_bit(WCD_MBHC_HPHL_PA_OFF_ACK, - &msmfalcon_cdc->mbhc.hph_pa_dac_state); - msm_anlg_cdc_notifier_call(codec, - WCD_EVENT_POST_HPHL_PA_OFF); - } else if (w->shift == 4) { - clear_bit(WCD_MBHC_HPHR_PA_OFF_ACK, - &msmfalcon_cdc->mbhc.hph_pa_dac_state); - msm_anlg_cdc_notifier_call(codec, - WCD_EVENT_POST_HPHR_PA_OFF); - } - /* Wait for 15ms after HPH RX teardown */ - usleep_range(15000, 15100); - break; - } - return 0; -} - -static const struct snd_soc_dapm_route audio_map[] = { - /* RDAC Connections */ - {"HPHR DAC", NULL, "RDAC2 MUX"}, - {"RDAC2 MUX", "RX1", "PDM_IN_RX1"}, - {"RDAC2 MUX", "RX2", "PDM_IN_RX2"}, - - /* WSA */ - {"WSA_SPK OUT", NULL, "WSA Spk Switch"}, - {"WSA Spk Switch", "WSA", "EAR PA"}, - - /* Earpiece (RX MIX1) */ - {"EAR", NULL, "EAR_S"}, - {"EAR_S", "Switch", "EAR PA"}, - {"EAR PA", NULL, "RX_BIAS"}, - {"EAR PA", NULL, "HPHL DAC"}, - {"EAR PA", NULL, "HPHR DAC"}, - {"EAR PA", NULL, "EAR CP"}, - - /* Headset (RX MIX1 and RX MIX2) */ - {"HEADPHONE", NULL, "HPHL PA"}, - {"HEADPHONE", NULL, "HPHR PA"}, - - {"Ext Spk", NULL, "Ext Spk Switch"}, - {"Ext Spk Switch", "On", "HPHL PA"}, - {"Ext Spk Switch", "On", "HPHR PA"}, - - {"HPHL PA", NULL, "HPHL"}, - {"HPHR PA", NULL, "HPHR"}, - {"HPHL", "Switch", "HPHL DAC"}, - {"HPHR", "Switch", "HPHR DAC"}, - {"HPHL PA", NULL, "CP"}, - {"HPHL PA", NULL, "RX_BIAS"}, - {"HPHR PA", NULL, "CP"}, - {"HPHR PA", NULL, "RX_BIAS"}, - {"HPHL DAC", NULL, "PDM_IN_RX1"}, - - {"SPK_OUT", NULL, "SPK PA"}, - {"SPK PA", NULL, "SPK_RX_BIAS"}, - {"SPK PA", NULL, "SPK"}, - {"SPK", "Switch", "SPK DAC"}, - {"SPK DAC", NULL, "PDM_IN_RX3"}, - {"SPK DAC", NULL, "VDD_SPKDRV"}, - - /* lineout */ - {"LINEOUT", NULL, "LINEOUT PA"}, - {"LINEOUT PA", NULL, "SPK_RX_BIAS"}, - {"LINEOUT PA", NULL, "LINE_OUT"}, - {"LINE_OUT", "Switch", "LINEOUT DAC"}, - {"LINEOUT DAC", NULL, "PDM_IN_RX3"}, - - /* lineout to WSA */ - {"WSA_SPK OUT", NULL, "LINEOUT PA"}, - - {"PDM_IN_RX1", NULL, "RX1 CLK"}, - {"PDM_IN_RX2", NULL, "RX2 CLK"}, - {"PDM_IN_RX3", NULL, "RX3 CLK"}, - - {"ADC1_OUT", NULL, "ADC1"}, - {"ADC2_OUT", NULL, "ADC2"}, - {"ADC3_OUT", NULL, "ADC3"}, - - /* ADC Connections */ - {"ADC2", NULL, "ADC2 MUX"}, - {"ADC3", NULL, "ADC2 MUX"}, - {"ADC2 MUX", "INP2", "ADC2_INP2"}, - {"ADC2 MUX", "INP3", "ADC2_INP3"}, - - {"ADC1", NULL, "AMIC1"}, - {"ADC2_INP2", NULL, "AMIC2"}, - {"ADC2_INP3", NULL, "AMIC3"}, - - {"MIC BIAS Internal1", NULL, "INT_LDO_H"}, - {"MIC BIAS Internal2", NULL, "INT_LDO_H"}, - {"MIC BIAS External", NULL, "INT_LDO_H"}, - {"MIC BIAS External2", NULL, "INT_LDO_H"}, - {"MIC BIAS Internal1", NULL, "MICBIAS_REGULATOR"}, - {"MIC BIAS Internal2", NULL, "MICBIAS_REGULATOR"}, - {"MIC BIAS External", NULL, "MICBIAS_REGULATOR"}, - {"MIC BIAS External2", NULL, "MICBIAS_REGULATOR"}, -}; - -static int msm_anlg_cdc_startup(struct snd_pcm_substream *substream, - struct snd_soc_dai *dai) -{ - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(dai->codec); - - dev_dbg(dai->codec->dev, "%s(): substream = %s stream = %d\n", - __func__, - substream->name, substream->stream); - /* - * If status_mask is BUS_DOWN it means SSR is not complete. - * So return error. - */ - if (test_bit(BUS_DOWN, &msmfalcon_cdc->status_mask)) { - dev_err(dai->codec->dev, "Error, Device is not up post SSR\n"); - return -EINVAL; - } - return 0; -} - -static void msm_anlg_cdc_shutdown(struct snd_pcm_substream *substream, - struct snd_soc_dai *dai) -{ - dev_dbg(dai->codec->dev, - "%s(): substream = %s stream = %d\n", __func__, - substream->name, substream->stream); -} - -int msm_anlg_cdc_mclk_enable(struct snd_soc_codec *codec, - int mclk_enable, bool dapm) -{ - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - dev_dbg(codec->dev, "%s: mclk_enable = %u, dapm = %d\n", - __func__, mclk_enable, dapm); - if (mclk_enable) { - msmfalcon_cdc->int_mclk0_enabled = true; - msm_anlg_cdc_codec_enable_clock_block(codec, 1); - } else { - if (!msmfalcon_cdc->int_mclk0_enabled) { - dev_err(codec->dev, "Error, MCLK already diabled\n"); - return -EINVAL; - } - msmfalcon_cdc->int_mclk0_enabled = false; - msm_anlg_cdc_codec_enable_clock_block(codec, 0); - } - return 0; -} - -static int msm_anlg_cdc_set_dai_sysclk(struct snd_soc_dai *dai, - int clk_id, unsigned int freq, int dir) -{ - dev_dbg(dai->codec->dev, "%s\n", __func__); - return 0; -} - -static int msm_anlg_cdc_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) -{ - dev_dbg(dai->codec->dev, "%s\n", __func__); - return 0; -} - -static int msm_anlg_cdc_set_channel_map(struct snd_soc_dai *dai, - unsigned int tx_num, unsigned int *tx_slot, - unsigned int rx_num, unsigned int *rx_slot) - -{ - dev_dbg(dai->codec->dev, "%s\n", __func__); - return 0; -} - -static int msm_anlg_cdc_get_channel_map(struct snd_soc_dai *dai, - unsigned int *tx_num, unsigned int *tx_slot, - unsigned int *rx_num, unsigned int *rx_slot) - -{ - dev_dbg(dai->codec->dev, "%s\n", __func__); - return 0; -} - -static struct snd_soc_dai_ops msm_anlg_cdc_dai_ops = { - .startup = msm_anlg_cdc_startup, - .shutdown = msm_anlg_cdc_shutdown, - .set_sysclk = msm_anlg_cdc_set_dai_sysclk, - .set_fmt = msm_anlg_cdc_set_dai_fmt, - .set_channel_map = msm_anlg_cdc_set_channel_map, - .get_channel_map = msm_anlg_cdc_get_channel_map, -}; - -static struct snd_soc_dai_driver msm_anlg_cdc_i2s_dai[] = { - { - .name = "msm_anlg_cdc_i2s_rx1", - .id = AIF1_PB, - .playback = { - .stream_name = "Playback", - .rates = MSMFALCON_CDC_RATES, - .formats = MSMFALCON_CDC_FORMATS, - .rate_max = 192000, - .rate_min = 8000, - .channels_min = 1, - .channels_max = 3, - }, - .ops = &msm_anlg_cdc_dai_ops, - }, - { - .name = "msm_anlg_cdc_i2s_tx1", - .id = AIF1_CAP, - .capture = { - .stream_name = "Record", - .rates = MSMFALCON_CDC_RATES, - .formats = MSMFALCON_CDC_FORMATS, - .rate_max = 48000, - .rate_min = 8000, - .channels_min = 1, - .channels_max = 4, - }, - .ops = &msm_anlg_cdc_dai_ops, - }, - { - .name = "msm_anlg_cdc_i2s_tx2", - .id = AIF3_SVA, - .capture = { - .stream_name = "RecordSVA", - .rates = MSMFALCON_CDC_RATES, - .formats = MSMFALCON_CDC_FORMATS, - .rate_max = 48000, - .rate_min = 8000, - .channels_min = 1, - .channels_max = 2, - }, - .ops = &msm_anlg_cdc_dai_ops, - }, - { - .name = "msm_anlg_vifeedback", - .id = AIF2_VIFEED, - .capture = { - .stream_name = "VIfeed", - .rates = MSMFALCON_CDC_RATES, - .formats = MSMFALCON_CDC_FORMATS, - .rate_max = 48000, - .rate_min = 48000, - .channels_min = 2, - .channels_max = 2, - }, - .ops = &msm_anlg_cdc_dai_ops, - }, -}; - - -static int msm_anlg_cdc_codec_enable_lo_pa(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, - int event) -{ - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - - dev_dbg(codec->dev, "%s: %d %s\n", __func__, event, w->name); - switch (event) { - case SND_SOC_DAPM_POST_PMU: - msm_anlg_cdc_dig_notifier_call(codec, - DIG_CDC_EVENT_RX3_MUTE_OFF); - break; - case SND_SOC_DAPM_POST_PMD: - msm_anlg_cdc_dig_notifier_call(codec, - DIG_CDC_EVENT_RX3_MUTE_ON); - break; - } - - return 0; -} - -static int msm_anlg_cdc_codec_enable_spk_ext_pa(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, - int event) -{ - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - dev_dbg(codec->dev, "%s: %s event = %d\n", __func__, w->name, event); - switch (event) { - case SND_SOC_DAPM_POST_PMU: - dev_dbg(codec->dev, - "%s: enable external speaker PA\n", __func__); - if (msmfalcon_cdc->codec_spk_ext_pa_cb) - msmfalcon_cdc->codec_spk_ext_pa_cb(codec, 1); - break; - case SND_SOC_DAPM_PRE_PMD: - dev_dbg(codec->dev, - "%s: enable external speaker PA\n", __func__); - if (msmfalcon_cdc->codec_spk_ext_pa_cb) - msmfalcon_cdc->codec_spk_ext_pa_cb(codec, 0); - break; - } - return 0; -} - -static int msm_anlg_cdc_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, - int event) -{ - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - switch (event) { - case SND_SOC_DAPM_PRE_PMU: - dev_dbg(codec->dev, - "%s: Sleeping 20ms after select EAR PA\n", - __func__); - snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_EAR_CTL, - 0x80, 0x80); - if (get_codec_version(msmfalcon_cdc) < CONGA) - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME, 0xFF, 0x2A); - if (get_codec_version(msmfalcon_cdc) >= DIANGU) { - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, 0x08, 0x00); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST, 0x04, 0x04); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST, 0x04, 0x04); - } - break; - case SND_SOC_DAPM_POST_PMU: - dev_dbg(codec->dev, - "%s: Sleeping 20ms after enabling EAR PA\n", - __func__); - snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_EAR_CTL, - 0x40, 0x40); - /* Wait for 7ms after EAR PA enable */ - usleep_range(7000, 7100); - msm_anlg_cdc_dig_notifier_call(codec, - DIG_CDC_EVENT_RX1_MUTE_OFF); - break; - case SND_SOC_DAPM_PRE_PMD: - msm_anlg_cdc_dig_notifier_call(codec, - DIG_CDC_EVENT_RX1_MUTE_ON); - /* Wait for 20ms for RX digital mute to take effect */ - msleep(20); - if (msmfalcon_cdc->boost_option == BOOST_ALWAYS) { - dev_dbg(codec->dev, - "%s: boost_option:%d, tear down ear\n", - __func__, msmfalcon_cdc->boost_option); - msm_anlg_cdc_boost_mode_sequence(codec, EAR_PMD); - } - if (get_codec_version(msmfalcon_cdc) >= DIANGU) { - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST, 0x04, 0x0); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST, 0x04, 0x0); - } - break; - case SND_SOC_DAPM_POST_PMD: - dev_dbg(codec->dev, - "%s: Sleeping 7ms after disabling EAR PA\n", - __func__); - snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_EAR_CTL, - 0x40, 0x00); - /* Wait for 7ms after EAR PA teardown */ - usleep_range(7000, 7100); - if (get_codec_version(msmfalcon_cdc) < CONGA) - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME, 0xFF, 0x16); - if (get_codec_version(msmfalcon_cdc) >= DIANGU) - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, 0x08, 0x08); - break; - } - return 0; -} - -static const struct snd_soc_dapm_widget msm_anlg_cdc_dapm_widgets[] = { - SND_SOC_DAPM_PGA_E("EAR PA", SND_SOC_NOPM, - 0, 0, NULL, 0, msm_anlg_cdc_codec_enable_ear_pa, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_PGA_E("HPHL PA", MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, - 5, 0, NULL, 0, - msm_anlg_cdc_hph_pa_event, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD | - SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_PGA_E("HPHR PA", MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, - 4, 0, NULL, 0, - msm_anlg_cdc_hph_pa_event, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD | - SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_PGA_E("SPK PA", SND_SOC_NOPM, - 0, 0, NULL, 0, msm_anlg_cdc_codec_enable_spk_pa, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_PGA_E("LINEOUT PA", MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL, - 5, 0, NULL, 0, msm_anlg_cdc_codec_enable_lo_pa, - SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_MUX("EAR_S", SND_SOC_NOPM, 0, 0, ear_pa_mux), - SND_SOC_DAPM_MUX("SPK", SND_SOC_NOPM, 0, 0, spkr_mux), - SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, hphl_mux), - SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, hphr_mux), - SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux), - SND_SOC_DAPM_MUX("WSA Spk Switch", SND_SOC_NOPM, 0, 0, wsa_spk_mux), - SND_SOC_DAPM_MUX("Ext Spk Switch", SND_SOC_NOPM, 0, 0, &ext_spk_mux), - SND_SOC_DAPM_MUX("LINE_OUT", SND_SOC_NOPM, 0, 0, lo_mux), - SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), - - SND_SOC_DAPM_MIXER_E("HPHL DAC", - MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL, - 0, msm_anlg_cdc_hphl_dac_event, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MIXER_E("HPHR DAC", - MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL, - 0, msm_anlg_cdc_hphr_dac_event, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), - SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), - - SND_SOC_DAPM_DAC("SPK DAC", NULL, MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, - 7, 0), - SND_SOC_DAPM_DAC_E("LINEOUT DAC", NULL, - SND_SOC_NOPM, 0, 0, msm_anlg_cdc_lo_dac_event, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_SPK("Ext Spk", msm_anlg_cdc_codec_enable_spk_ext_pa), - - SND_SOC_DAPM_SUPPLY("RX1 CLK", MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, - 0, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("RX2 CLK", MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, - 1, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("RX3 CLK", MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, - 2, 0, msm_anlg_cdc_codec_enable_dig_clk, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_SUPPLY("CP", MSM89XX_PMIC_ANALOG_NCP_EN, 0, 0, - msm_anlg_cdc_codec_enable_charge_pump, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_SUPPLY("EAR CP", MSM89XX_PMIC_ANALOG_NCP_EN, 4, 0, - msm_anlg_cdc_codec_enable_charge_pump, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_SUPPLY_S("RX_BIAS", 1, SND_SOC_NOPM, - 0, 0, msm_anlg_cdc_codec_enable_rx_bias, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_SUPPLY_S("SPK_RX_BIAS", 1, SND_SOC_NOPM, 0, 0, - msm_anlg_cdc_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_SUPPLY("VDD_SPKDRV", SND_SOC_NOPM, 0, 0, - msmfalcon_wcd_codec_enable_vdd_spkr, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("MICBIAS_REGULATOR", SND_SOC_NOPM, - ON_DEMAND_MICBIAS, 0, - msm_anlg_cdc_codec_enable_on_demand_supply, - SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_MICBIAS_E("MIC BIAS Internal1", - MSM89XX_PMIC_ANALOG_MICB_1_EN, 7, 0, - msm_anlg_cdc_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MICBIAS_E("MIC BIAS Internal2", - MSM89XX_PMIC_ANALOG_MICB_2_EN, 7, 0, - msm_anlg_cdc_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MICBIAS_E("MIC BIAS Internal3", - MSM89XX_PMIC_ANALOG_MICB_1_EN, 7, 0, - msm_anlg_cdc_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_ADC_E("ADC1", NULL, MSM89XX_PMIC_ANALOG_TX_1_EN, 7, 0, - msm_anlg_cdc_codec_enable_adc, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_ADC_E("ADC2_INP2", - NULL, MSM89XX_PMIC_ANALOG_TX_2_EN, 7, 0, - msm_anlg_cdc_codec_enable_adc, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_ADC_E("ADC2_INP3", - NULL, MSM89XX_PMIC_ANALOG_TX_3_EN, 7, 0, - msm_anlg_cdc_codec_enable_adc, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_MICBIAS_E("MIC BIAS External", - MSM89XX_PMIC_ANALOG_MICB_1_EN, 7, 0, - msm_anlg_cdc_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MICBIAS_E("MIC BIAS External2", - MSM89XX_PMIC_ANALOG_MICB_2_EN, 7, 0, - msm_anlg_cdc_codec_enable_micbias, SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_INPUT("AMIC1"), - SND_SOC_DAPM_INPUT("AMIC2"), - SND_SOC_DAPM_INPUT("AMIC3"), - SND_SOC_DAPM_INPUT("PDM_IN_RX1"), - SND_SOC_DAPM_INPUT("PDM_IN_RX2"), - SND_SOC_DAPM_INPUT("PDM_IN_RX3"), - - SND_SOC_DAPM_OUTPUT("EAR"), - SND_SOC_DAPM_OUTPUT("WSA_SPK OUT"), - SND_SOC_DAPM_OUTPUT("HEADPHONE"), - SND_SOC_DAPM_OUTPUT("SPK_OUT"), - SND_SOC_DAPM_OUTPUT("LINEOUT"), - SND_SOC_DAPM_OUTPUT("ADC1_OUT"), - SND_SOC_DAPM_OUTPUT("ADC2_OUT"), - SND_SOC_DAPM_OUTPUT("ADC3_OUT"), -}; - -static const struct msmfalcon_cdc_reg_mask_val msm_anlg_cdc_reg_defaults[] = { - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x03), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0x82), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL, 0xE1), -}; - -static const struct msmfalcon_cdc_reg_mask_val - msm_anlg_cdc_reg_defaults_2_0[] = { - MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_SEC_ACCESS, 0xA5), - MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x0F), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS, 0x4F), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_NCP_FBCTRL, 0x28), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, 0x69), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG, 0x01), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_BOOST_EN_CTL, 0x5F), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SLOPE_COMP_IP_ZERO, 0x88), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0xA5), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3, 0x0F), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0x82), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x03), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL, 0xE1), - MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x80), -}; - -static const struct msmfalcon_cdc_reg_mask_val conga_wcd_reg_defaults[] = { - MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_SEC_ACCESS, 0xA5), - MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x0F), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0xA5), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3, 0x0F), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS, 0x4C), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_NCP_FBCTRL, 0x28), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, 0x69), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG, 0x01), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_PERPH_SUBTYPE, 0x0A), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x03), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL, 0xE1), - MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x80), -}; - -static const struct msmfalcon_cdc_reg_mask_val cajon_wcd_reg_defaults[] = { - MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_SEC_ACCESS, 0xA5), - MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x0F), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0xA5), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3, 0x0F), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS, 0x4C), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0x82), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_NCP_FBCTRL, 0xA8), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_NCP_VCTRL, 0xA4), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_ANA_BIAS_SET, 0x41), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, 0x69), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG, 0x01), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL, 0xE1), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x03), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_PA, 0xFA), - MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x80), -}; - -static const struct msmfalcon_cdc_reg_mask_val cajon2p0_wcd_reg_defaults[] = { - MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_SEC_ACCESS, 0xA5), - MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x0F), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0xA5), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3, 0x0F), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS, 0x4C), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0xA2), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_NCP_FBCTRL, 0xA8), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_NCP_VCTRL, 0xA4), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_ANA_BIAS_SET, 0x41), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, 0x69), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG, 0x01), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL, 0xE1), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x03), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_RX_EAR_STATUS, 0x10), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_BYPASS_MODE, 0x18), - MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_PA, 0xFA), - MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x80), -}; - -static void msm_anlg_cdc_update_reg_defaults(struct snd_soc_codec *codec) -{ - u32 i, version; - struct msmfalcon_cdc_priv *msmfalcon_cdc = - snd_soc_codec_get_drvdata(codec); - - version = get_codec_version(msmfalcon_cdc); - if (version == TOMBAK_1_0) { - for (i = 0; i < ARRAY_SIZE(msm_anlg_cdc_reg_defaults); i++) - snd_soc_write(codec, msm_anlg_cdc_reg_defaults[i].reg, - msm_anlg_cdc_reg_defaults[i].val); - } else if (version == TOMBAK_2_0) { - for (i = 0; i < ARRAY_SIZE(msm_anlg_cdc_reg_defaults_2_0); i++) - snd_soc_write(codec, - msm_anlg_cdc_reg_defaults_2_0[i].reg, - msm_anlg_cdc_reg_defaults_2_0[i].val); - } else if (version == CONGA) { - for (i = 0; i < ARRAY_SIZE(conga_wcd_reg_defaults); i++) - snd_soc_write(codec, - conga_wcd_reg_defaults[i].reg, - conga_wcd_reg_defaults[i].val); - } else if (version == CAJON) { - for (i = 0; i < ARRAY_SIZE(cajon_wcd_reg_defaults); i++) - snd_soc_write(codec, - cajon_wcd_reg_defaults[i].reg, - cajon_wcd_reg_defaults[i].val); - } else if (version == CAJON_2_0 || version == DIANGU - || version == DRAX_CDC) { - for (i = 0; i < ARRAY_SIZE(cajon2p0_wcd_reg_defaults); i++) - snd_soc_write(codec, - cajon2p0_wcd_reg_defaults[i].reg, - cajon2p0_wcd_reg_defaults[i].val); - } -} - -static const struct msmfalcon_cdc_reg_mask_val - msm_anlg_cdc_codec_reg_init_val[] = { - - /* Initialize current threshold to 350MA - * number of wait and run cycles to 4096 - */ - {MSM89XX_PMIC_ANALOG_RX_COM_OCP_CTL, 0xFF, 0x12}, - {MSM89XX_PMIC_ANALOG_RX_COM_OCP_COUNT, 0xFF, 0xFF}, -}; - -static void msm_anlg_cdc_codec_init_cache(struct snd_soc_codec *codec) -{ - u32 i; - - regcache_cache_only(codec->component.regmap, true); - /* update cache with POR values */ - for (i = 0; i < ARRAY_SIZE(msm89xx_pmic_cdc_defaults); i++) - snd_soc_write(codec, msm89xx_pmic_cdc_defaults[i].reg, - msm89xx_pmic_cdc_defaults[i].def); - regcache_cache_only(codec->component.regmap, false); -} - -static void msm_anlg_cdc_codec_init_reg(struct snd_soc_codec *codec) -{ - u32 i; - - for (i = 0; i < ARRAY_SIZE(msm_anlg_cdc_codec_reg_init_val); i++) - snd_soc_update_bits(codec, - msm_anlg_cdc_codec_reg_init_val[i].reg, - msm_anlg_cdc_codec_reg_init_val[i].mask, - msm_anlg_cdc_codec_reg_init_val[i].val); -} - -static int msm_anlg_cdc_bringup(struct snd_soc_codec *codec) -{ - snd_soc_write(codec, - MSM89XX_PMIC_DIGITAL_SEC_ACCESS, - 0xA5); - snd_soc_write(codec, MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL4, 0x01); - snd_soc_write(codec, - MSM89XX_PMIC_ANALOG_SEC_ACCESS, - 0xA5); - snd_soc_write(codec, MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL4, 0x01); - snd_soc_write(codec, - MSM89XX_PMIC_DIGITAL_SEC_ACCESS, - 0xA5); - snd_soc_write(codec, MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL4, 0x00); - snd_soc_write(codec, - MSM89XX_PMIC_ANALOG_SEC_ACCESS, - 0xA5); - snd_soc_write(codec, MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL4, 0x00); - return 0; -} - -static struct regulator *msm_anlg_cdc_find_regulator( - const struct msmfalcon_cdc *msmfalcon_cdc, - const char *name) -{ - int i; - - for (i = 0; i < msmfalcon_cdc->num_of_supplies; i++) { - if (msmfalcon_cdc->supplies[i].supply && - !strcmp(msmfalcon_cdc->supplies[i].supply, name)) - return msmfalcon_cdc->supplies[i].consumer; - } - - dev_err(msmfalcon_cdc->dev, "Error: regulator not found:%s\n" - , name); - return NULL; -} - -static int msm_anlg_cdc_device_down(struct snd_soc_codec *codec) -{ - struct msm_asoc_mach_data *pdata = NULL; - struct msmfalcon_cdc_priv *msmfalcon_cdc_priv = - snd_soc_codec_get_drvdata(codec); - unsigned int tx_1_en; - unsigned int tx_2_en; - - pdata = snd_soc_card_get_drvdata(codec->component.card); - dev_dbg(codec->dev, "%s: device down!\n", __func__); - - tx_1_en = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_TX_1_EN); - tx_2_en = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_TX_2_EN); - tx_1_en = tx_1_en & 0x7f; - tx_2_en = tx_2_en & 0x7f; - snd_soc_write(codec, - MSM89XX_PMIC_ANALOG_TX_1_EN, tx_1_en); - snd_soc_write(codec, - MSM89XX_PMIC_ANALOG_TX_2_EN, tx_2_en); - if (msmfalcon_cdc_priv->boost_option == BOOST_ON_FOREVER) { - if ((snd_soc_read(codec, MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL) - & 0x80) == 0) { - msm_anlg_cdc_dig_notifier_call(codec, - DIG_CDC_EVENT_CLK_ON); - snd_soc_write(codec, - MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL, 0x30); - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x80, 0x80); - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL, - 0x0C, 0x0C); - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, - 0x84, 0x84); - snd_soc_update_bits(codec, - MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, - 0x10, 0x10); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, - 0x1F, 0x1F); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, - 0x90, 0x90); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_RX_EAR_CTL, - 0xFF, 0xFF); - /* Wait for 20us for boost settings to take effect */ - usleep_range(20, 21); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, - 0xFF, 0xFF); - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, - 0xE9, 0xE9); - } - } - msm_anlg_cdc_boost_off(codec); - msmfalcon_cdc_priv->hph_mode = NORMAL_MODE; - - /* 40ms to allow boost to discharge */ - msleep(40); - /* Disable PA to avoid pop during codec bring up */ - snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, - 0x30, 0x00); - snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, - 0x80, 0x00); - snd_soc_write(codec, - MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL, 0x20); - snd_soc_write(codec, - MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL, 0x20); - snd_soc_write(codec, - MSM89XX_PMIC_ANALOG_RX_EAR_CTL, 0x12); - snd_soc_write(codec, - MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x93); - - msm_anlg_cdc_bringup(codec); - atomic_set(&pdata->int_mclk0_enabled, false); - msm_anlg_cdc_dig_notifier_call(codec, DIG_CDC_EVENT_SSR_DOWN); - set_bit(BUS_DOWN, &msmfalcon_cdc_priv->status_mask); - snd_soc_card_change_online_state(codec->component.card, 0); - return 0; -} - -static int msm_anlg_cdc_device_up(struct snd_soc_codec *codec) -{ - struct msmfalcon_cdc_priv *msmfalcon_cdc_priv = - snd_soc_codec_get_drvdata(codec); - int ret = 0; - - dev_dbg(codec->dev, "%s: device up!\n", __func__); - - msm_anlg_cdc_dig_notifier_call(codec, DIG_CDC_EVENT_SSR_UP); - clear_bit(BUS_DOWN, &msmfalcon_cdc_priv->status_mask); - snd_soc_card_change_online_state(codec->component.card, 1); - /* delay is required to make sure sound card state updated */ - usleep_range(5000, 5100); - - msm_anlg_cdc_codec_init_reg(codec); - msm_anlg_cdc_update_reg_defaults(codec); - - regcache_mark_dirty(codec->component.regmap); - regcache_sync_region(codec->component.regmap, - MSM89XX_PMIC_DIGITAL_REVISION1, - MSM89XX_PMIC_CDC_MAX_REGISTER); - - snd_soc_write(codec, MSM89XX_PMIC_DIGITAL_INT_EN_SET, - MSM89XX_PMIC_DIGITAL_INT_EN_SET__POR); - snd_soc_write(codec, MSM89XX_PMIC_DIGITAL_INT_EN_CLR, - MSM89XX_PMIC_DIGITAL_INT_EN_CLR__POR); - - msm_anlg_cdc_set_boost_v(codec); - msm_anlg_cdc_set_micb_v(codec); - if (msmfalcon_cdc_priv->boost_option == BOOST_ON_FOREVER) - msm_anlg_cdc_boost_on(codec); - else if (msmfalcon_cdc_priv->boost_option == BYPASS_ALWAYS) - msm_anlg_cdc_bypass_on(codec); - - msm_anlg_cdc_configure_cap(codec, false, false); - wcd_mbhc_stop(&msmfalcon_cdc_priv->mbhc); - wcd_mbhc_deinit(&msmfalcon_cdc_priv->mbhc); - ret = wcd_mbhc_init(&msmfalcon_cdc_priv->mbhc, codec, &mbhc_cb, - &intr_ids, wcd_mbhc_registers, true); - if (ret) - dev_err(codec->dev, "%s: mbhc initialization failed\n", - __func__); - else - wcd_mbhc_start(&msmfalcon_cdc_priv->mbhc, - msmfalcon_cdc_priv->mbhc.mbhc_cfg); - - return 0; -} - -static int msmfalcon_cdc_notifier_service_cb(struct notifier_block *nb, - unsigned long opcode, void *ptr) -{ - struct snd_soc_codec *codec; - struct msmfalcon_cdc_priv *msmfalcon_cdc_priv = - container_of(nb, struct msmfalcon_cdc_priv, - audio_ssr_nb); - bool adsp_ready = false; - bool timedout; - unsigned long timeout; - - codec = msmfalcon_cdc_priv->codec; - dev_dbg(codec->dev, "%s: Service opcode 0x%lx\n", __func__, opcode); - - switch (opcode) { - case AUDIO_NOTIFIER_SERVICE_DOWN: - dev_dbg(codec->dev, - "ADSP is about to power down. teardown/reset codec\n"); - msm_anlg_cdc_device_down(codec); - break; - case AUDIO_NOTIFIER_SERVICE_UP: - if (initial_boot) { - initial_boot = false; - break; - } - dev_dbg(codec->dev, - "ADSP is about to power up. bring up codec\n"); - - if (!q6core_is_adsp_ready()) { - dev_dbg(codec->dev, - "ADSP isn't ready\n"); - timeout = jiffies + - msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS); - while (!(timedout = time_after(jiffies, timeout))) { - if (!q6core_is_adsp_ready()) { - dev_dbg(codec->dev, - "ADSP isn't ready\n"); - } else { - dev_dbg(codec->dev, - "ADSP is ready\n"); - adsp_ready = true; - goto powerup; - } - } - } else { - adsp_ready = true; - dev_dbg(codec->dev, "%s: DSP is ready\n", __func__); - } -powerup: - if (adsp_ready) - msm_anlg_cdc_device_up(codec); - break; - default: - break; - } - return NOTIFY_OK; -} - -int msm_anlg_cdc_hs_detect(struct snd_soc_codec *codec, - struct wcd_mbhc_config *mbhc_cfg) -{ - struct msmfalcon_cdc_priv *msmfalcon_cdc_priv = - snd_soc_codec_get_drvdata(codec); - - return wcd_mbhc_start(&msmfalcon_cdc_priv->mbhc, mbhc_cfg); -} -EXPORT_SYMBOL(msm_anlg_cdc_hs_detect); - -void msm_anlg_cdc_hs_detect_exit(struct snd_soc_codec *codec) -{ - struct msmfalcon_cdc_priv *msmfalcon_cdc_priv = - snd_soc_codec_get_drvdata(codec); - - wcd_mbhc_stop(&msmfalcon_cdc_priv->mbhc); -} -EXPORT_SYMBOL(msm_anlg_cdc_hs_detect_exit); - -void msm_anlg_cdc_update_int_spk_boost(bool enable) -{ - pr_debug("%s: enable = %d\n", __func__, enable); - spkr_boost_en = enable; -} -EXPORT_SYMBOL(msm_anlg_cdc_update_int_spk_boost); - -static void msm_anlg_cdc_set_micb_v(struct snd_soc_codec *codec) -{ - - struct msmfalcon_cdc *msmfalcon_cdc = codec->control_data; - struct msmfalcon_cdc_pdata *pdata = msmfalcon_cdc->dev->platform_data; - u8 reg_val; - - reg_val = VOLTAGE_CONVERTER(pdata->micbias.cfilt1_mv, MICBIAS_MIN_VAL, - MICBIAS_STEP_SIZE); - dev_dbg(codec->dev, "cfilt1_mv %d reg_val %x\n", - (u32)pdata->micbias.cfilt1_mv, reg_val); - snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_MICB_1_VAL, - 0xF8, (reg_val << 3)); -} - -static void msm_anlg_cdc_set_boost_v(struct snd_soc_codec *codec) -{ - struct msmfalcon_cdc_priv *msmfalcon_cdc_priv = - snd_soc_codec_get_drvdata(codec); - - snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_OUTPUT_VOLTAGE, - 0x1F, msmfalcon_cdc_priv->boost_voltage); -} - -static void msm_anlg_cdc_configure_cap(struct snd_soc_codec *codec, - bool micbias1, bool micbias2) -{ - - struct msm_asoc_mach_data *pdata = NULL; - - pdata = snd_soc_card_get_drvdata(codec->component.card); - - pr_debug("\n %s: micbias1 %x micbias2 = %d\n", __func__, micbias1, - micbias2); - if (micbias1 && micbias2) { - if ((pdata->micbias1_cap_mode - == MICBIAS_EXT_BYP_CAP) || - (pdata->micbias2_cap_mode - == MICBIAS_EXT_BYP_CAP)) - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MICB_1_EN, - 0x40, (MICBIAS_EXT_BYP_CAP << 6)); - else - snd_soc_update_bits(codec, - MSM89XX_PMIC_ANALOG_MICB_1_EN, - 0x40, (MICBIAS_NO_EXT_BYP_CAP << 6)); - } else if (micbias2) { - snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_MICB_1_EN, - 0x40, (pdata->micbias2_cap_mode << 6)); - } else if (micbias1) { - snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_MICB_1_EN, - 0x40, (pdata->micbias1_cap_mode << 6)); - } else { - snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_MICB_1_EN, - 0x40, 0x00); - } -} - -static ssize_t msm_anlg_codec_version_read(struct snd_info_entry *entry, - void *file_private_data, - struct file *file, - char __user *buf, size_t count, - loff_t pos) -{ - struct msmfalcon_cdc_priv *msmfalcon_cdc_priv; - char buffer[MSM_ANLG_CDC_VERSION_ENTRY_SIZE]; - int len = 0; - - msmfalcon_cdc_priv = (struct msmfalcon_cdc_priv *) entry->private_data; - if (!msmfalcon_cdc_priv) { - pr_err("%s: msmfalcon_cdc_priv is null\n", __func__); - return -EINVAL; - } - - switch (get_codec_version(msmfalcon_cdc_priv)) { - case DRAX_CDC: - len = snprintf(buffer, sizeof(buffer), "DRAX_CDC_1_0\n"); - break; - default: - len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n"); - } - - return simple_read_from_buffer(buf, count, &pos, buffer, len); -} - -static struct snd_info_entry_ops msm_anlg_codec_info_ops = { - .read = msm_anlg_codec_version_read, -}; - -/* - * msm_anlg_codec_info_create_codec_entry - creates pmic_analog module - * @codec_root: The parent directory - * @codec: Codec instance - * - * Creates pmic_analog module and version entry under the given - * parent directory. - * - * Return: 0 on success or negative error code on failure. - */ -int msm_anlg_codec_info_create_codec_entry(struct snd_info_entry *codec_root, - struct snd_soc_codec *codec) -{ - struct snd_info_entry *version_entry; - struct msmfalcon_cdc_priv *msmfalcon_cdc_priv; - struct snd_soc_card *card; - - if (!codec_root || !codec) - return -EINVAL; - - msmfalcon_cdc_priv = snd_soc_codec_get_drvdata(codec); - card = codec->component.card; - msmfalcon_cdc_priv->entry = snd_register_module_info(codec_root->module, - "pmic_analog", - codec_root); - if (!msmfalcon_cdc_priv->entry) { - dev_dbg(codec->dev, "%s: failed to create pmic_analog entry\n", - __func__); - return -ENOMEM; - } - - version_entry = snd_info_create_card_entry(card->snd_card, - "version", - msmfalcon_cdc_priv->entry); - if (!version_entry) { - dev_dbg(codec->dev, "%s: failed to create pmic_analog version entry\n", - __func__); - return -ENOMEM; - } - - version_entry->private_data = msmfalcon_cdc_priv; - version_entry->size = MSM_ANLG_CDC_VERSION_ENTRY_SIZE; - version_entry->content = SNDRV_INFO_CONTENT_DATA; - version_entry->c.ops = &msm_anlg_codec_info_ops; - - if (snd_info_register(version_entry) < 0) { - snd_info_free_entry(version_entry); - return -ENOMEM; - } - msmfalcon_cdc_priv->version_entry = version_entry; - return 0; -} -EXPORT_SYMBOL(msm_anlg_codec_info_create_codec_entry); - -static int msm_anlg_cdc_soc_probe(struct snd_soc_codec *codec) -{ - struct msmfalcon_cdc_priv *msmfalcon_cdc_priv; - struct msmfalcon_cdc *handle_cdc; - int ret; - - msmfalcon_cdc_priv = devm_kzalloc(codec->dev, - sizeof(struct msmfalcon_cdc_priv), - GFP_KERNEL); - if (!msmfalcon_cdc_priv) - return -ENOMEM; - - codec->control_data = dev_get_drvdata(codec->dev); - snd_soc_codec_set_drvdata(codec, msmfalcon_cdc_priv); - msmfalcon_cdc_priv->codec = codec; - handle_cdc = codec->control_data; - handle_cdc->codec = codec; - - /* codec resmgr module init */ - msmfalcon_cdc_priv->spkdrv_reg = - msm_anlg_cdc_find_regulator(codec->control_data, - MSM89XX_VDD_SPKDRV_NAME); - msmfalcon_cdc_priv->pmic_rev = - snd_soc_read(codec, - MSM89XX_PMIC_DIGITAL_REVISION1); - msmfalcon_cdc_priv->codec_version = - snd_soc_read(codec, - MSM89XX_PMIC_DIGITAL_PERPH_SUBTYPE); - msmfalcon_cdc_priv->analog_major_rev = - snd_soc_read(codec, - MSM89XX_PMIC_ANALOG_REVISION4); - - if (msmfalcon_cdc_priv->codec_version == CONGA) { - dev_dbg(codec->dev, "%s :Conga REV: %d\n", __func__, - msmfalcon_cdc_priv->codec_version); - msmfalcon_cdc_priv->ext_spk_boost_set = true; - } else { - dev_dbg(codec->dev, "%s :PMIC REV: %d\n", __func__, - msmfalcon_cdc_priv->pmic_rev); - if (msmfalcon_cdc_priv->pmic_rev == TOMBAK_1_0 && - msmfalcon_cdc_priv->codec_version == CAJON_2_0) { - if (msmfalcon_cdc_priv->analog_major_rev == 0x02) { - msmfalcon_cdc_priv->codec_version = DRAX_CDC; - dev_dbg(codec->dev, - "%s : Drax codec detected\n", __func__); - } else { - msmfalcon_cdc_priv->codec_version = DIANGU; - dev_dbg(codec->dev, "%s : Diangu detected\n", - __func__); - } - } else if (msmfalcon_cdc_priv->pmic_rev == TOMBAK_1_0 && - (snd_soc_read(codec, MSM89XX_PMIC_ANALOG_NCP_FBCTRL) - & 0x80)) { - msmfalcon_cdc_priv->codec_version = CAJON; - dev_dbg(codec->dev, "%s : Cajon detected\n", __func__); - } else if (msmfalcon_cdc_priv->pmic_rev == TOMBAK_2_0 && - (snd_soc_read(codec, MSM89XX_PMIC_ANALOG_NCP_FBCTRL) - & 0x80)) { - msmfalcon_cdc_priv->codec_version = CAJON_2_0; - dev_dbg(codec->dev, "%s : Cajon 2.0 detected\n", - __func__); - } - } - /* - * set to default boost option BOOST_SWITCH, user mixer path can change - * it to BOOST_ALWAYS or BOOST_BYPASS based on solution chosen. - */ - msmfalcon_cdc_priv->boost_option = BOOST_SWITCH; - msmfalcon_cdc_priv->hph_mode = NORMAL_MODE; - - msm_anlg_cdc_dt_parse_boost_info(codec); - msm_anlg_cdc_set_boost_v(codec); - - snd_soc_add_codec_controls(codec, impedance_detect_controls, - ARRAY_SIZE(impedance_detect_controls)); - snd_soc_add_codec_controls(codec, hph_type_detect_controls, - ARRAY_SIZE(hph_type_detect_controls)); - - msm_anlg_cdc_bringup(codec); - msm_anlg_cdc_codec_init_cache(codec); - msm_anlg_cdc_codec_init_reg(codec); - msm_anlg_cdc_update_reg_defaults(codec); - - wcd9xxx_spmi_set_codec(codec); - - msmfalcon_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].supply = - msm_anlg_cdc_find_regulator( - codec->control_data, - on_demand_supply_name[ON_DEMAND_MICBIAS]); - atomic_set(&msmfalcon_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].ref, - 0); - - BLOCKING_INIT_NOTIFIER_HEAD(&msmfalcon_cdc_priv->notifier); - - msmfalcon_cdc_priv->fw_data = devm_kzalloc(codec->dev, - sizeof(*(msmfalcon_cdc_priv->fw_data)), - GFP_KERNEL); - if (!msmfalcon_cdc_priv->fw_data) - return -ENOMEM; - - set_bit(WCD9XXX_MBHC_CAL, msmfalcon_cdc_priv->fw_data->cal_bit); - ret = wcd_cal_create_hwdep(msmfalcon_cdc_priv->fw_data, - WCD9XXX_CODEC_HWDEP_NODE, codec); - if (ret < 0) { - dev_err(codec->dev, "%s hwdep failed %d\n", __func__, ret); - return ret; - } - - wcd_mbhc_init(&msmfalcon_cdc_priv->mbhc, codec, &mbhc_cb, &intr_ids, - wcd_mbhc_registers, true); - - msmfalcon_cdc_priv->int_mclk0_enabled = false; - /*Update speaker boost configuration*/ - msmfalcon_cdc_priv->spk_boost_set = spkr_boost_en; - pr_debug("%s: speaker boost configured = %d\n", - __func__, msmfalcon_cdc_priv->spk_boost_set); - - /* Set initial MICBIAS voltage level */ - msm_anlg_cdc_set_micb_v(codec); - - /* Set initial cap mode */ - msm_anlg_cdc_configure_cap(codec, false, false); - msmfalcon_cdc_priv->audio_ssr_nb.notifier_call = - msmfalcon_cdc_notifier_service_cb; - ret = audio_notifier_register("pmic_analog_cdc", - AUDIO_NOTIFIER_ADSP_DOMAIN, - &msmfalcon_cdc_priv->audio_ssr_nb); - if (ret < 0) { - pr_err("%s: Audio notifier register failed ret = %d\n", - __func__, ret); - wcd_mbhc_deinit(&msmfalcon_cdc_priv->mbhc); - return ret; - } - return 0; -} - -static int msm_anlg_cdc_soc_remove(struct snd_soc_codec *codec) -{ - struct msmfalcon_cdc_priv *msmfalcon_cdc_priv = - snd_soc_codec_get_drvdata(codec); - - msmfalcon_cdc_priv->spkdrv_reg = NULL; - msmfalcon_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].supply = NULL; - atomic_set(&msmfalcon_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].ref, - 0); - wcd_mbhc_deinit(&msmfalcon_cdc_priv->mbhc); - - return 0; -} - -static int msm_anlg_cdc_enable_static_supplies_to_optimum( - struct msmfalcon_cdc *msmfalcon_cdc, - struct msmfalcon_cdc_pdata *pdata) -{ - int i; - int ret = 0; - - for (i = 0; i < msmfalcon_cdc->num_of_supplies; i++) { - if (pdata->regulator[i].ondemand) - continue; - if (regulator_count_voltages( - msmfalcon_cdc->supplies[i].consumer) <= 0) - continue; - - ret = regulator_set_voltage( - msmfalcon_cdc->supplies[i].consumer, - pdata->regulator[i].min_uv, - pdata->regulator[i].max_uv); - if (ret) { - dev_err(msmfalcon_cdc->dev, - "Setting volt failed for regulator %s err %d\n", - msmfalcon_cdc->supplies[i].supply, ret); - } - - ret = regulator_set_load(msmfalcon_cdc->supplies[i].consumer, - pdata->regulator[i].optimum_ua); - dev_dbg(msmfalcon_cdc->dev, "Regulator %s set optimum mode\n", - msmfalcon_cdc->supplies[i].supply); - } - - return ret; -} - -static int msm_anlg_cdc_disable_static_supplies_to_optimum( - struct msmfalcon_cdc *msmfalcon_cdc, - struct msmfalcon_cdc_pdata *pdata) -{ - int i; - int ret = 0; - - for (i = 0; i < msmfalcon_cdc->num_of_supplies; i++) { - if (pdata->regulator[i].ondemand) - continue; - if (regulator_count_voltages( - msmfalcon_cdc->supplies[i].consumer) <= 0) - continue; - regulator_set_voltage(msmfalcon_cdc->supplies[i].consumer, 0, - pdata->regulator[i].max_uv); - regulator_set_load(msmfalcon_cdc->supplies[i].consumer, 0); - dev_dbg(msmfalcon_cdc->dev, "Regulator %s set optimum mode\n", - msmfalcon_cdc->supplies[i].supply); - } - - return ret; -} - -static int msm_anlg_cdc_suspend(struct snd_soc_codec *codec) -{ - struct msm_asoc_mach_data *pdata = NULL; - struct msmfalcon_cdc *msmfalcon_cdc = codec->control_data; - struct msmfalcon_cdc_pdata *msmfalcon_cdc_pdata = - msmfalcon_cdc->dev->platform_data; - - pdata = snd_soc_card_get_drvdata(codec->component.card); - pr_debug("%s: mclk cnt = %d, mclk_enabled = %d\n", - __func__, atomic_read(&pdata->int_mclk0_rsc_ref), - atomic_read(&pdata->int_mclk0_enabled)); - if (atomic_read(&pdata->int_mclk0_enabled) == true) { - cancel_delayed_work_sync(&pdata->disable_int_mclk0_work); - mutex_lock(&pdata->cdc_int_mclk0_mutex); - pdata->digital_cdc_core_clk.enable = 0; - afe_set_lpass_clock_v2(AFE_PORT_ID_INT0_MI2S_RX, - &pdata->digital_cdc_core_clk); - atomic_set(&pdata->int_mclk0_enabled, false); - mutex_unlock(&pdata->cdc_int_mclk0_mutex); - } - msm_anlg_cdc_disable_static_supplies_to_optimum(msmfalcon_cdc, - msmfalcon_cdc_pdata); - return 0; -} - -static int msm_anlg_cdc_resume(struct snd_soc_codec *codec) -{ - struct msm_asoc_mach_data *pdata = NULL; - struct msmfalcon_cdc *msmfalcon_cdc = codec->control_data; - struct msmfalcon_cdc_pdata *msmfalcon_cdc_pdata = - msmfalcon_cdc->dev->platform_data; - - pdata = snd_soc_card_get_drvdata(codec->component.card); - msm_anlg_cdc_enable_static_supplies_to_optimum(msmfalcon_cdc, - msmfalcon_cdc_pdata); - return 0; -} - -static struct regmap *msm_anlg_get_regmap(struct device *dev) -{ - return dev_get_regmap(dev->parent, NULL); -} - -static struct snd_soc_codec_driver soc_codec_dev_msmfalcon_cdc = { - .probe = msm_anlg_cdc_soc_probe, - .remove = msm_anlg_cdc_soc_remove, - .suspend = msm_anlg_cdc_suspend, - .resume = msm_anlg_cdc_resume, - .reg_word_size = 1, - .controls = msm_anlg_cdc_snd_controls, - .num_controls = ARRAY_SIZE(msm_anlg_cdc_snd_controls), - .dapm_widgets = msm_anlg_cdc_dapm_widgets, - .num_dapm_widgets = ARRAY_SIZE(msm_anlg_cdc_dapm_widgets), - .dapm_routes = audio_map, - .num_dapm_routes = ARRAY_SIZE(audio_map), - .get_regmap = msm_anlg_get_regmap, -}; - -static int msm_anlg_cdc_init_supplies(struct msmfalcon_cdc *msmfalcon_cdc, - struct msmfalcon_cdc_pdata *pdata) -{ - int ret; - int i; - - msmfalcon_cdc->supplies = devm_kzalloc(msmfalcon_cdc->dev, - sizeof(struct regulator_bulk_data) * - ARRAY_SIZE(pdata->regulator), - GFP_KERNEL); - if (!msmfalcon_cdc->supplies) { - ret = -ENOMEM; - goto err; - } - - msmfalcon_cdc->num_of_supplies = 0; - if (ARRAY_SIZE(pdata->regulator) > MAX_REGULATOR) { - dev_err(msmfalcon_cdc->dev, "%s: Array Size out of bound\n", - __func__); - ret = -EINVAL; - goto err; - } - - for (i = 0; i < ARRAY_SIZE(pdata->regulator); i++) { - if (pdata->regulator[i].name) { - msmfalcon_cdc->supplies[i].supply = - pdata->regulator[i].name; - msmfalcon_cdc->num_of_supplies++; - } - } - - ret = devm_regulator_bulk_get(msmfalcon_cdc->dev, - msmfalcon_cdc->num_of_supplies, - msmfalcon_cdc->supplies); - if (ret != 0) { - dev_err(msmfalcon_cdc->dev, - "Failed to get supplies: err = %d\n", - ret); - goto err_supplies; - } - - for (i = 0; i < msmfalcon_cdc->num_of_supplies; i++) { - if (regulator_count_voltages( - msmfalcon_cdc->supplies[i].consumer) <= 0) - continue; - ret = regulator_set_voltage(msmfalcon_cdc->supplies[i].consumer, - pdata->regulator[i].min_uv, - pdata->regulator[i].max_uv); - if (ret) { - dev_err(msmfalcon_cdc->dev, - "Setting regulator voltage failed for regulator %s err = %d\n", - msmfalcon_cdc->supplies[i].supply, ret); - goto err_supplies; - } - ret = regulator_set_load(msmfalcon_cdc->supplies[i].consumer, - pdata->regulator[i].optimum_ua); - if (ret < 0) { - dev_err(msmfalcon_cdc->dev, - "Setting regulator optimum mode failed for regulator %s err = %d\n", - msmfalcon_cdc->supplies[i].supply, ret); - goto err_supplies; - } else { - ret = 0; - } - } - - return ret; - -err_supplies: - kfree(msmfalcon_cdc->supplies); -err: - return ret; -} - -static int msm_anlg_cdc_enable_static_supplies( - struct msmfalcon_cdc *msmfalcon_cdc, - struct msmfalcon_cdc_pdata *pdata) -{ - int i; - int ret = 0; - - for (i = 0; i < msmfalcon_cdc->num_of_supplies; i++) { - if (pdata->regulator[i].ondemand) - continue; - ret = regulator_enable(msmfalcon_cdc->supplies[i].consumer); - if (ret) { - dev_err(msmfalcon_cdc->dev, "Failed to enable %s\n", - msmfalcon_cdc->supplies[i].supply); - break; - } - dev_dbg(msmfalcon_cdc->dev, "Enabled regulator %s\n", - msmfalcon_cdc->supplies[i].supply); - } - - while (ret && --i) - if (!pdata->regulator[i].ondemand) - regulator_disable(msmfalcon_cdc->supplies[i].consumer); - return ret; -} - -static void msm_anlg_cdc_disable_supplies(struct msmfalcon_cdc *msmfalcon_cdc, - struct msmfalcon_cdc_pdata *pdata) -{ - int i; - - regulator_bulk_disable(msmfalcon_cdc->num_of_supplies, - msmfalcon_cdc->supplies); - for (i = 0; i < msmfalcon_cdc->num_of_supplies; i++) { - if (regulator_count_voltages( - msmfalcon_cdc->supplies[i].consumer) <= 0) - continue; - regulator_set_voltage(msmfalcon_cdc->supplies[i].consumer, 0, - pdata->regulator[i].max_uv); - regulator_set_load(msmfalcon_cdc->supplies[i].consumer, 0); - } - regulator_bulk_free(msmfalcon_cdc->num_of_supplies, - msmfalcon_cdc->supplies); - kfree(msmfalcon_cdc->supplies); -} - -static const struct of_device_id msmfalcon_codec_of_match[] = { - { .compatible = "qcom,pmic-analog-codec", }, - {}, -}; - -static void msm_anlg_add_child_devices(struct work_struct *work) -{ - struct msmfalcon_cdc *pdata; - struct platform_device *pdev; - struct device_node *node; - struct msm_dig_ctrl_data *dig_ctrl_data = NULL, *temp; - int ret, ctrl_num = 0; - struct msm_dig_ctrl_platform_data *platdata; - char plat_dev_name[MSM_DIG_CDC_STRING_LEN]; - - pdata = container_of(work, struct msmfalcon_cdc, - msm_anlg_add_child_devices_work); - if (!pdata) { - pr_err("%s: Memory for pdata does not exist\n", - __func__); - return; - } - if (!pdata->dev->of_node) { - dev_err(pdata->dev, - "%s: DT node for pdata does not exist\n", __func__); - return; - } - - platdata = &pdata->dig_plat_data; - - for_each_child_of_node(pdata->dev->of_node, node) { - if (!strcmp(node->name, "msm-dig-codec")) - strlcpy(plat_dev_name, "msm_digital_codec", - (MSM_DIG_CDC_STRING_LEN - 1)); - else - continue; - - pdev = platform_device_alloc(plat_dev_name, -1); - if (!pdev) { - dev_err(pdata->dev, "%s: pdev memory alloc failed\n", - __func__); - ret = -ENOMEM; - goto err; - } - pdev->dev.parent = pdata->dev; - pdev->dev.of_node = node; - - if (!strcmp(node->name, "msm-dig-codec")) { - ret = platform_device_add_data(pdev, platdata, - sizeof(*platdata)); - if (ret) { - dev_err(&pdev->dev, - "%s: cannot add plat data ctrl:%d\n", - __func__, ctrl_num); - goto fail_pdev_add; - } - } - - ret = platform_device_add(pdev); - if (ret) { - dev_err(&pdev->dev, - "%s: Cannot add platform device\n", - __func__); - goto fail_pdev_add; - } - - if (!strcmp(node->name, "msm-dig-codec")) { - temp = krealloc(dig_ctrl_data, - (ctrl_num + 1) * sizeof( - struct msm_dig_ctrl_data), - GFP_KERNEL); - if (!temp) { - dev_err(&pdev->dev, "out of memory\n"); - ret = -ENOMEM; - goto err; - } - dig_ctrl_data = temp; - dig_ctrl_data[ctrl_num].dig_pdev = pdev; - ctrl_num++; - dev_dbg(&pdev->dev, - "%s: Added digital codec device(s)\n", - __func__); - pdata->dig_ctrl_data = dig_ctrl_data; - } - } - - return; -fail_pdev_add: - platform_device_put(pdev); -err: - return; -} - -static int msm_anlg_cdc_probe(struct platform_device *pdev) -{ - int ret = 0; - struct msmfalcon_cdc *msmfalcon_cdc = NULL; - struct msmfalcon_cdc_pdata *pdata; - int adsp_state; - - adsp_state = apr_get_subsys_state(); - if (adsp_state != APR_SUBSYS_LOADED) { - dev_err(&pdev->dev, "Adsp is not loaded yet %d\n", - adsp_state); - return -EPROBE_DEFER; - } - device_init_wakeup(&pdev->dev, true); - - if (pdev->dev.of_node) { - dev_dbg(&pdev->dev, "%s:Platform data from device tree\n", - __func__); - pdata = msm_anlg_cdc_populate_dt_pdata(&pdev->dev); - pdev->dev.platform_data = pdata; - } else { - dev_dbg(&pdev->dev, "%s:Platform data from board file\n", - __func__); - pdata = pdev->dev.platform_data; - } - if (pdata == NULL) { - dev_err(&pdev->dev, "%s:Platform data failed to populate\n", - __func__); - goto rtn; - } - msmfalcon_cdc = devm_kzalloc(&pdev->dev, sizeof(struct msmfalcon_cdc), - GFP_KERNEL); - if (msmfalcon_cdc == NULL) { - ret = -ENOMEM; - goto rtn; - } - - msmfalcon_cdc->dev = &pdev->dev; - ret = msm_anlg_cdc_init_supplies(msmfalcon_cdc, pdata); - if (ret) { - dev_err(&pdev->dev, "%s: Fail to enable Codec supplies\n", - __func__); - goto rtn; - } - ret = msm_anlg_cdc_enable_static_supplies(msmfalcon_cdc, pdata); - if (ret) { - dev_err(&pdev->dev, - "%s: Fail to enable Codec pre-reset supplies\n", - __func__); - goto rtn; - } - /* Allow supplies to be ready */ - usleep_range(5, 6); - - dev_set_drvdata(&pdev->dev, msmfalcon_cdc); - if (wcd9xxx_spmi_irq_init()) { - dev_err(&pdev->dev, - "%s: irq initialization failed\n", __func__); - } else { - dev_dbg(&pdev->dev, - "%s: irq initialization passed\n", __func__); - } - - ret = snd_soc_register_codec(&pdev->dev, - &soc_codec_dev_msmfalcon_cdc, - msm_anlg_cdc_i2s_dai, - ARRAY_SIZE(msm_anlg_cdc_i2s_dai)); - if (ret) { - dev_err(&pdev->dev, - "%s:snd_soc_register_codec failed with error %d\n", - __func__, ret); - goto err_supplies; - } - msmfalcon_cdc->dig_plat_data.handle = (void *) msmfalcon_cdc; - msmfalcon_cdc->dig_plat_data.update_clkdiv = update_clkdiv; - msmfalcon_cdc->dig_plat_data.get_cdc_version = get_cdc_version; - msmfalcon_cdc->dig_plat_data.register_notifier = - msm_anlg_cdc_dig_register_notifier; - INIT_WORK(&msmfalcon_cdc->msm_anlg_add_child_devices_work, - msm_anlg_add_child_devices); - schedule_work(&msmfalcon_cdc->msm_anlg_add_child_devices_work); - - return ret; -err_supplies: - msm_anlg_cdc_disable_supplies(msmfalcon_cdc, pdata); -rtn: - return ret; -} - -static int msm_anlg_cdc_remove(struct platform_device *pdev) -{ - struct msmfalcon_cdc *msmfalcon_cdc = dev_get_drvdata(&pdev->dev); - struct msmfalcon_cdc_pdata *pdata = msmfalcon_cdc->dev->platform_data; - - snd_soc_unregister_codec(&pdev->dev); - msm_anlg_cdc_disable_supplies(msmfalcon_cdc, pdata); - return 0; -} - -static struct platform_driver msm_anlg_codec_driver = { - .driver = { - .owner = THIS_MODULE, - .name = DRV_NAME, - .of_match_table = of_match_ptr(msmfalcon_codec_of_match) - }, - .probe = msm_anlg_cdc_probe, - .remove = msm_anlg_cdc_remove, -}; -module_platform_driver(msm_anlg_codec_driver); - -MODULE_DESCRIPTION("MSM Audio Analog codec driver"); -MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/codecs/msmfalcon_cdc/msm-analog-cdc.h b/sound/soc/codecs/msmfalcon_cdc/msm-analog-cdc.h deleted file mode 100644 index 112b544b7de8..000000000000 --- a/sound/soc/codecs/msmfalcon_cdc/msm-analog-cdc.h +++ /dev/null @@ -1,240 +0,0 @@ -/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef MSM_ANALOG_CDC_H -#define MSM_ANALOG_CDC_H - -#include -#include -#include -#include "../wcd-mbhc-v2.h" -#include "../wcdcal-hwdep.h" -#include "msmfalcon-cdc-registers.h" - -#define MICBIAS_EXT_BYP_CAP 0x00 -#define MICBIAS_NO_EXT_BYP_CAP 0x01 - -#define MSM89XX_NUM_IRQ_REGS 2 -#define MAX_REGULATOR 7 -#define MSM89XX_REG_VAL(reg, val) {reg, 0, val} - -#define MSM89XX_VDD_SPKDRV_NAME "cdc-vdd-spkdrv" - -#define DEFAULT_MULTIPLIER 800 -#define DEFAULT_GAIN 9 -#define DEFAULT_OFFSET 100 - -extern const u8 msm89xx_pmic_cdc_reg_readable[MSM89XX_PMIC_CDC_CACHE_SIZE]; -extern const u8 msm89xx_cdc_core_reg_readable[MSM89XX_CDC_CORE_CACHE_SIZE]; -extern struct regmap_config msm89xx_cdc_core_regmap_config; -extern struct regmap_config msm89xx_pmic_cdc_regmap_config; - -enum wcd_curr_ref { - I_h4_UA = 0, - I_pt5_UA, - I_14_UA, - I_l4_UA, - I_1_UA, -}; - -enum wcd_mbhc_imp_det_pin { - WCD_MBHC_DET_NONE = 0, - WCD_MBHC_DET_HPHL, - WCD_MBHC_DET_HPHR, - WCD_MBHC_DET_BOTH, -}; - - -/* Each micbias can be assigned to one of three cfilters - * Vbatt_min >= .15V + ldoh_v - * ldoh_v >= .15v + cfiltx_mv - * If ldoh_v = 1.95 160 mv < cfiltx_mv < 1800 mv - * If ldoh_v = 2.35 200 mv < cfiltx_mv < 2200 mv - * If ldoh_v = 2.75 240 mv < cfiltx_mv < 2600 mv - * If ldoh_v = 2.85 250 mv < cfiltx_mv < 2700 mv - */ - -struct wcd_micbias_setting { - u8 ldoh_v; - u32 cfilt1_mv; /* in mv */ - u32 cfilt2_mv; /* in mv */ - u32 cfilt3_mv; /* in mv */ - /* Different WCD9xxx series codecs may not - * have 4 mic biases. If a codec has fewer - * mic biases, some of these properties will - * not be used. - */ - u8 bias1_cfilt_sel; - u8 bias2_cfilt_sel; - u8 bias3_cfilt_sel; - u8 bias4_cfilt_sel; - u8 bias1_cap_mode; - u8 bias2_cap_mode; - u8 bias3_cap_mode; - u8 bias4_cap_mode; - bool bias2_is_headset_only; -}; - -enum msmfalcon_cdc_pid_current { - MSM89XX_PID_MIC_2P5_UA, - MSM89XX_PID_MIC_5_UA, - MSM89XX_PID_MIC_10_UA, - MSM89XX_PID_MIC_20_UA, -}; - -struct msmfalcon_cdc_reg_mask_val { - u16 reg; - u8 mask; - u8 val; -}; - -enum { - /* INTR_REG 0 - Digital Periph */ - MSM89XX_IRQ_SPKR_CNP = 0, - MSM89XX_IRQ_SPKR_CLIP, - MSM89XX_IRQ_SPKR_OCP, - MSM89XX_IRQ_MBHC_INSREM_DET1, - MSM89XX_IRQ_MBHC_RELEASE, - MSM89XX_IRQ_MBHC_PRESS, - MSM89XX_IRQ_MBHC_INSREM_DET, - MSM89XX_IRQ_MBHC_HS_DET, - /* INTR_REG 1 - Analog Periph */ - MSM89XX_IRQ_EAR_OCP, - MSM89XX_IRQ_HPHR_OCP, - MSM89XX_IRQ_HPHL_OCP, - MSM89XX_IRQ_EAR_CNP, - MSM89XX_IRQ_HPHR_CNP, - MSM89XX_IRQ_HPHL_CNP, - MSM89XX_NUM_IRQS, -}; - -enum { - ON_DEMAND_MICBIAS = 0, - ON_DEMAND_SPKDRV, - ON_DEMAND_SUPPLIES_MAX, -}; - -/* - * The delay list is per codec HW specification. - * Please add delay in the list in the future instead - * of magic number - */ -enum { - CODEC_DELAY_1_MS = 1000, - CODEC_DELAY_1_1_MS = 1100, -}; - -struct msmfalcon_cdc_regulator { - const char *name; - int min_uv; - int max_uv; - int optimum_ua; - bool ondemand; - struct regulator *regulator; -}; - -struct on_demand_supply { - struct regulator *supply; - atomic_t ref; -}; - -struct wcd_imped_i_ref { - enum wcd_curr_ref curr_ref; - int min_val; - int multiplier; - int gain_adj; - int offset; -}; - -enum msmfalcon_cdc_micbias_num { - MSM89XX_MICBIAS1 = 0, -}; - -/* Hold instance to digital codec platform device */ -struct msm_dig_ctrl_data { - struct platform_device *dig_pdev; -}; - -struct msm_dig_ctrl_platform_data { - void *handle; - void (*update_clkdiv)(void *handle, int val); - int (*get_cdc_version)(void *handle); - int (*register_notifier)(void *handle, - struct notifier_block *nblock, - bool enable); -}; - -struct msmfalcon_cdc { - struct device *dev; - u32 num_of_supplies; - struct regulator_bulk_data *supplies; - struct snd_soc_codec *codec; - struct work_struct msm_anlg_add_child_devices_work; - struct msm_dig_ctrl_platform_data dig_plat_data; - /* digital codec data structure */ - struct msm_dig_ctrl_data *dig_ctrl_data; - struct blocking_notifier_head notifier; -}; - -struct msmfalcon_cdc_pdata { - struct wcd_micbias_setting micbias; - struct msmfalcon_cdc_regulator regulator[MAX_REGULATOR]; -}; - -struct msmfalcon_cdc_priv { - struct snd_soc_codec *codec; - u16 pmic_rev; - u16 codec_version; - u16 analog_major_rev; - u32 boost_voltage; - u32 adc_count; - u32 rx_bias_count; - bool int_mclk0_enabled; - u16 boost_option; - /* mode to select hd2 */ - u32 hph_mode; - /* compander used for each rx chain */ - bool spk_boost_set; - bool ear_pa_boost_set; - bool ext_spk_boost_set; - struct on_demand_supply on_demand_list[ON_DEMAND_SUPPLIES_MAX]; - struct regulator *spkdrv_reg; - struct blocking_notifier_head notifier; - /* mbhc module */ - struct wcd_mbhc mbhc; - /* cal info for codec */ - struct fw_info *fw_data; - struct notifier_block audio_ssr_nb; - int (*codec_spk_ext_pa_cb)(struct snd_soc_codec *codec, int enable); - unsigned long status_mask; - struct wcd_imped_i_ref imped_i_ref; - enum wcd_mbhc_imp_det_pin imped_det_pin; - /* Entry for version info */ - struct snd_info_entry *entry; - struct snd_info_entry *version_entry; -}; - -extern int msm_anlg_cdc_mclk_enable(struct snd_soc_codec *codec, - int mclk_enable, bool dapm); - -extern int msm_anlg_cdc_hs_detect(struct snd_soc_codec *codec, - struct wcd_mbhc_config *mbhc_cfg); - -extern void msm_anlg_cdc_hs_detect_exit(struct snd_soc_codec *codec); - -extern void msmfalcon_cdc_update_int_spk_boost(bool enable); - -extern void msm_anlg_cdc_spk_ext_pa_cb( - int (*codec_spk_ext_pa)(struct snd_soc_codec *codec, - int enable), struct snd_soc_codec *codec); -int msm_anlg_codec_info_create_codec_entry(struct snd_info_entry *codec_root, - struct snd_soc_codec *codec); -#endif diff --git a/sound/soc/codecs/msmfalcon_cdc/msm-cdc-common.h b/sound/soc/codecs/msmfalcon_cdc/msm-cdc-common.h deleted file mode 100644 index 9f2e9355197b..000000000000 --- a/sound/soc/codecs/msmfalcon_cdc/msm-cdc-common.h +++ /dev/null @@ -1,66 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include "msmfalcon-cdc-registers.h" - -extern struct reg_default - msm89xx_cdc_core_defaults[MSM89XX_CDC_CORE_CACHE_SIZE]; -extern struct reg_default - msm89xx_pmic_cdc_defaults[MSM89XX_PMIC_CDC_CACHE_SIZE]; - -bool msm89xx_cdc_core_readable_reg(struct device *dev, unsigned int reg); -bool msm89xx_cdc_core_volatile_reg(struct device *dev, unsigned int reg); - -enum { - AIF1_PB = 0, - AIF1_CAP, - AIF2_VIFEED, - AIF3_SVA, - NUM_CODEC_DAIS, -}; - -enum codec_versions { - TOMBAK_1_0, - TOMBAK_2_0, - CONGA, - CAJON, - CAJON_2_0, - DIANGU, - DRAX_CDC, - UNSUPPORTED, -}; - -/* Support different hph modes */ -enum { - NORMAL_MODE = 0, - HD2_MODE, -}; - -enum dig_cdc_notify_event { - DIG_CDC_EVENT_INVALID, - DIG_CDC_EVENT_CLK_ON, - DIG_CDC_EVENT_CLK_OFF, - DIG_CDC_EVENT_RX1_MUTE_ON, - DIG_CDC_EVENT_RX1_MUTE_OFF, - DIG_CDC_EVENT_RX2_MUTE_ON, - DIG_CDC_EVENT_RX2_MUTE_OFF, - DIG_CDC_EVENT_RX3_MUTE_ON, - DIG_CDC_EVENT_RX3_MUTE_OFF, - DIG_CDC_EVENT_PRE_RX1_INT_ON, - DIG_CDC_EVENT_PRE_RX2_INT_ON, - DIG_CDC_EVENT_POST_RX1_INT_OFF, - DIG_CDC_EVENT_POST_RX2_INT_OFF, - DIG_CDC_EVENT_SSR_DOWN, - DIG_CDC_EVENT_SSR_UP, - DIG_CDC_EVENT_LAST, -}; diff --git a/sound/soc/codecs/msmfalcon_cdc/msm-digital-cdc.c b/sound/soc/codecs/msmfalcon_cdc/msm-digital-cdc.c deleted file mode 100644 index d036b82654f0..000000000000 --- a/sound/soc/codecs/msmfalcon_cdc/msm-digital-cdc.c +++ /dev/null @@ -1,2039 +0,0 @@ -/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "msmfalcon-cdc-registers.h" -#include "msm-digital-cdc.h" -#include "msm-cdc-common.h" -#include "../../msm/msmfalcon-common.h" - -#define DRV_NAME "msm_digital_codec" -#define MCLK_RATE_9P6MHZ 9600000 -#define MCLK_RATE_12P288MHZ 12288000 -#define TX_MUX_CTL_CUT_OFF_FREQ_MASK 0x30 -#define CF_MIN_3DB_4HZ 0x0 -#define CF_MIN_3DB_75HZ 0x1 -#define CF_MIN_3DB_150HZ 0x2 - -#define MSM_DIG_CDC_VERSION_ENTRY_SIZE 32 - -static unsigned long rx_digital_gain_reg[] = { - MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL, - MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL, - MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL, -}; - -static unsigned long tx_digital_gain_reg[] = { - MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN, - MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN, -}; - -static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0); - -struct snd_soc_codec *registered_digcodec; -struct hpf_work tx_hpf_work[NUM_DECIMATORS]; - -/* Codec supports 2 IIR filters */ -enum { - IIR1 = 0, - IIR2, - IIR_MAX, -}; - -static int msm_digcdc_clock_control(bool flag) -{ - int ret = -EINVAL; - struct msm_asoc_mach_data *pdata = NULL; - - pdata = snd_soc_card_get_drvdata(registered_digcodec->component.card); - - if (flag) { - if (atomic_read(&pdata->int_mclk0_enabled) == false) { - pdata->digital_cdc_core_clk.enable = 1; - ret = afe_set_lpass_clock_v2( - AFE_PORT_ID_PRIMARY_MI2S_RX, - &pdata->digital_cdc_core_clk); - if (ret < 0) { - pr_err("%s:failed to enable the MCLK\n", - __func__); - return ret; - } - pr_debug("enabled digital codec core clk\n"); - atomic_set(&pdata->int_mclk0_enabled, true); - schedule_delayed_work(&pdata->disable_int_mclk0_work, - 50); - } - } else { - dev_dbg(registered_digcodec->dev, - "disable MCLK, workq to disable set already\n"); - } - return 0; -} - -static void enable_digital_callback(void *flag) -{ - msm_digcdc_clock_control(true); -} - -static void disable_digital_callback(void *flag) -{ - pr_debug("disable mclk happens in workq\n"); -} - -static int msm_dig_cdc_put_dec_enum(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_dapm_widget_list *wlist = - dapm_kcontrol_get_wlist(kcontrol); - struct snd_soc_dapm_widget *w = wlist->widgets[0]; - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; - unsigned int dec_mux, decimator; - char *dec_name = NULL; - char *widget_name = NULL; - char *temp; - u16 tx_mux_ctl_reg; - u8 adc_dmic_sel = 0x0; - int ret = 0; - char *dec_num; - - if (ucontrol->value.enumerated.item[0] > e->items) { - dev_err(codec->dev, "%s: Invalid enum value: %d\n", - __func__, ucontrol->value.enumerated.item[0]); - return -EINVAL; - } - dec_mux = ucontrol->value.enumerated.item[0]; - - widget_name = kstrndup(w->name, 15, GFP_KERNEL); - if (!widget_name) { - dev_err(codec->dev, "%s: failed to copy string\n", - __func__); - return -ENOMEM; - } - temp = widget_name; - - dec_name = strsep(&widget_name, " "); - widget_name = temp; - if (!dec_name) { - dev_err(codec->dev, "%s: Invalid decimator = %s\n", - __func__, w->name); - ret = -EINVAL; - goto out; - } - - dec_num = strpbrk(dec_name, "12345"); - if (dec_num == NULL) { - dev_err(codec->dev, "%s: Invalid DEC selected\n", __func__); - ret = -EINVAL; - goto out; - } - - ret = kstrtouint(dec_num, 10, &decimator); - if (ret < 0) { - dev_err(codec->dev, "%s: Invalid decimator = %s\n", - __func__, dec_name); - ret = -EINVAL; - goto out; - } - - dev_dbg(w->dapm->dev, "%s(): widget = %s decimator = %u dec_mux = %u\n" - , __func__, w->name, decimator, dec_mux); - - switch (decimator) { - case 1: - case 2: - case 3: - case 4: - case 5: - if ((dec_mux == 4) || (dec_mux == 5) || - (dec_mux == 6) || (dec_mux == 7)) - adc_dmic_sel = 0x1; - else - adc_dmic_sel = 0x0; - break; - default: - dev_err(codec->dev, "%s: Invalid Decimator = %u\n", - __func__, decimator); - ret = -EINVAL; - goto out; - } - - tx_mux_ctl_reg = - MSM89XX_CDC_CORE_TX1_MUX_CTL + 32 * (decimator - 1); - - snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x1, adc_dmic_sel); - - ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol); - -out: - kfree(widget_name); - return ret; -} - - -static int msm_dig_cdc_codec_config_compander(struct snd_soc_codec *codec, - int interp_n, int event) -{ - struct msm_dig_priv *dig_cdc = snd_soc_codec_get_drvdata(codec); - - dev_dbg(codec->dev, "%s: event %d shift %d, enabled %d\n", - __func__, event, interp_n, - dig_cdc->comp_enabled[interp_n]); - - /* compander is not enabled */ - if (!dig_cdc->comp_enabled[interp_n]) - return 0; - - switch (dig_cdc->comp_enabled[interp_n]) { - case COMPANDER_1: - if (SND_SOC_DAPM_EVENT_ON(event)) { - /* Enable Compander Clock */ - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_COMP0_B2_CTL, 0x0F, 0x09); - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_CLK_RX_B2_CTL, 0x01, 0x01); - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_COMP0_B1_CTL, - 1 << interp_n, 1 << interp_n); - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_COMP0_B3_CTL, 0xFF, 0x01); - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_COMP0_B2_CTL, 0xF0, 0x50); - /* add sleep for compander to settle */ - usleep_range(1000, 1100); - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_COMP0_B3_CTL, 0xFF, 0x28); - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_COMP0_B2_CTL, 0xF0, 0xB0); - - /* Enable Compander GPIO */ - if (dig_cdc->codec_hph_comp_gpio) - dig_cdc->codec_hph_comp_gpio(1, codec); - } else if (SND_SOC_DAPM_EVENT_OFF(event)) { - /* Disable Compander GPIO */ - if (dig_cdc->codec_hph_comp_gpio) - dig_cdc->codec_hph_comp_gpio(0, codec); - - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_COMP0_B2_CTL, 0x0F, 0x05); - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_COMP0_B1_CTL, - 1 << interp_n, 0); - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_CLK_RX_B2_CTL, 0x01, 0x00); - } - break; - default: - dev_dbg(codec->dev, "%s: Invalid compander %d\n", __func__, - dig_cdc->comp_enabled[interp_n]); - break; - }; - - return 0; -} - -/** - * msm_dig_cdc_hph_comp_cb - registers callback to codec by machine driver. - * - * @codec_hph_comp_gpio: function pointer to set comp gpio at machine driver - * @codec: codec pointer - * - */ -void msm_dig_cdc_hph_comp_cb( - int (*codec_hph_comp_gpio)(bool enable, struct snd_soc_codec *codec), - struct snd_soc_codec *codec) -{ - struct msm_dig_priv *dig_cdc = snd_soc_codec_get_drvdata(codec); - - pr_debug("%s: Enter\n", __func__); - dig_cdc->codec_hph_comp_gpio = codec_hph_comp_gpio; -} -EXPORT_SYMBOL(msm_dig_cdc_hph_comp_cb); - -static int msm_dig_cdc_codec_enable_interpolator(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, - int event) -{ - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msm_dig *msm_dig_cdc = dev_get_drvdata(codec->dev); - - dev_dbg(codec->dev, "%s %d %s\n", __func__, event, w->name); - - if (w->shift >= MSM89XX_RX_MAX || w->shift < 0) { - dev_err(codec->dev, "%s: wrong RX index: %d\n", - __func__, w->shift); - return -EINVAL; - } - switch (event) { - case SND_SOC_DAPM_POST_PMU: - msm_dig_cdc_codec_config_compander(codec, w->shift, event); - /* apply the digital gain after the interpolator is enabled*/ - if ((w->shift) < ARRAY_SIZE(rx_digital_gain_reg)) - snd_soc_write(codec, - rx_digital_gain_reg[w->shift], - snd_soc_read(codec, - rx_digital_gain_reg[w->shift]) - ); - break; - case SND_SOC_DAPM_POST_PMD: - msm_dig_cdc_codec_config_compander(codec, w->shift, event); - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_CLK_RX_RESET_CTL, - 1 << w->shift, 1 << w->shift); - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_CLK_RX_RESET_CTL, - 1 << w->shift, 0x0); - /* - * disable the mute enabled during the PMD of this device - */ - if ((w->shift == 0) && - (msm_dig_cdc->mute_mask & HPHL_PA_DISABLE)) { - pr_debug("disabling HPHL mute\n"); - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_RX1_B6_CTL, 0x01, 0x00); - msm_dig_cdc->mute_mask &= ~(HPHL_PA_DISABLE); - } else if ((w->shift == 1) && - (msm_dig_cdc->mute_mask & HPHR_PA_DISABLE)) { - pr_debug("disabling HPHR mute\n"); - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_RX2_B6_CTL, 0x01, 0x00); - msm_dig_cdc->mute_mask &= ~(HPHR_PA_DISABLE); - } else if ((w->shift == 2) && - (msm_dig_cdc->mute_mask & SPKR_PA_DISABLE)) { - pr_debug("disabling SPKR mute\n"); - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_RX3_B6_CTL, 0x01, 0x00); - msm_dig_cdc->mute_mask &= ~(SPKR_PA_DISABLE); - } - } - return 0; -} - -static int msm_dig_cdc_codec_enable_rx_chain(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, - int event) -{ - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - - switch (event) { - case SND_SOC_DAPM_POST_PMD: - snd_soc_update_bits(codec, w->reg, - 1 << w->shift, 0x00); - break; - } - return 0; -} - -static int msm_dig_cdc_get_iir_enable_audio_mixer( - struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - int iir_idx = ((struct soc_multi_mixer_control *) - kcontrol->private_value)->reg; - int band_idx = ((struct soc_multi_mixer_control *) - kcontrol->private_value)->shift; - - ucontrol->value.integer.value[0] = - (snd_soc_read(codec, - (MSM89XX_CDC_CORE_IIR1_CTL + 64 * iir_idx)) & - (1 << band_idx)) != 0; - - dev_dbg(codec->dev, "%s: IIR #%d band #%d enable %d\n", __func__, - iir_idx, band_idx, - (uint32_t)ucontrol->value.integer.value[0]); - return 0; -} - -static int msm_dig_cdc_put_iir_enable_audio_mixer( - struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - int iir_idx = ((struct soc_multi_mixer_control *) - kcontrol->private_value)->reg; - int band_idx = ((struct soc_multi_mixer_control *) - kcontrol->private_value)->shift; - int value = ucontrol->value.integer.value[0]; - - /* Mask first 5 bits, 6-8 are reserved */ - snd_soc_update_bits(codec, - (MSM89XX_CDC_CORE_IIR1_CTL + 64 * iir_idx), - (1 << band_idx), (value << band_idx)); - - dev_dbg(codec->dev, "%s: IIR #%d band #%d enable %d\n", __func__, - iir_idx, band_idx, - ((snd_soc_read(codec, - (MSM89XX_CDC_CORE_IIR1_CTL + 64 * iir_idx)) & - (1 << band_idx)) != 0)); - - return 0; -} - -static uint32_t get_iir_band_coeff(struct snd_soc_codec *codec, - int iir_idx, int band_idx, - int coeff_idx) -{ - uint32_t value = 0; - - /* Address does not automatically update if reading */ - snd_soc_write(codec, - (MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL + 64 * iir_idx), - ((band_idx * BAND_MAX + coeff_idx) - * sizeof(uint32_t)) & 0x7F); - - value |= snd_soc_read(codec, - (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx)); - - snd_soc_write(codec, - (MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL + 64 * iir_idx), - ((band_idx * BAND_MAX + coeff_idx) - * sizeof(uint32_t) + 1) & 0x7F); - - value |= (snd_soc_read(codec, - (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx)) << 8); - - snd_soc_write(codec, - (MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL + 64 * iir_idx), - ((band_idx * BAND_MAX + coeff_idx) - * sizeof(uint32_t) + 2) & 0x7F); - - value |= (snd_soc_read(codec, - (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx)) << 16); - - snd_soc_write(codec, - (MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL + 64 * iir_idx), - ((band_idx * BAND_MAX + coeff_idx) - * sizeof(uint32_t) + 3) & 0x7F); - - /* Mask bits top 2 bits since they are reserved */ - value |= ((snd_soc_read(codec, (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL - + 64 * iir_idx)) & 0x3f) << 24); - - return value; - -} - -static void set_iir_band_coeff(struct snd_soc_codec *codec, - int iir_idx, int band_idx, - uint32_t value) -{ - snd_soc_write(codec, - (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx), - (value & 0xFF)); - - snd_soc_write(codec, - (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx), - (value >> 8) & 0xFF); - - snd_soc_write(codec, - (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx), - (value >> 16) & 0xFF); - - /* Mask top 2 bits, 7-8 are reserved */ - snd_soc_write(codec, - (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx), - (value >> 24) & 0x3F); - -} - -static int msm_dig_cdc_get_iir_band_audio_mixer( - struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - int iir_idx = ((struct soc_multi_mixer_control *) - kcontrol->private_value)->reg; - int band_idx = ((struct soc_multi_mixer_control *) - kcontrol->private_value)->shift; - - ucontrol->value.integer.value[0] = - get_iir_band_coeff(codec, iir_idx, band_idx, 0); - ucontrol->value.integer.value[1] = - get_iir_band_coeff(codec, iir_idx, band_idx, 1); - ucontrol->value.integer.value[2] = - get_iir_band_coeff(codec, iir_idx, band_idx, 2); - ucontrol->value.integer.value[3] = - get_iir_band_coeff(codec, iir_idx, band_idx, 3); - ucontrol->value.integer.value[4] = - get_iir_band_coeff(codec, iir_idx, band_idx, 4); - - dev_dbg(codec->dev, "%s: IIR #%d band #%d b0 = 0x%x\n" - "%s: IIR #%d band #%d b1 = 0x%x\n" - "%s: IIR #%d band #%d b2 = 0x%x\n" - "%s: IIR #%d band #%d a1 = 0x%x\n" - "%s: IIR #%d band #%d a2 = 0x%x\n", - __func__, iir_idx, band_idx, - (uint32_t)ucontrol->value.integer.value[0], - __func__, iir_idx, band_idx, - (uint32_t)ucontrol->value.integer.value[1], - __func__, iir_idx, band_idx, - (uint32_t)ucontrol->value.integer.value[2], - __func__, iir_idx, band_idx, - (uint32_t)ucontrol->value.integer.value[3], - __func__, iir_idx, band_idx, - (uint32_t)ucontrol->value.integer.value[4]); - return 0; -} - -static int msm_dig_cdc_put_iir_band_audio_mixer( - struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - int iir_idx = ((struct soc_multi_mixer_control *) - kcontrol->private_value)->reg; - int band_idx = ((struct soc_multi_mixer_control *) - kcontrol->private_value)->shift; - - /* Mask top bit it is reserved */ - /* Updates addr automatically for each B2 write */ - snd_soc_write(codec, - (MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL + 64 * iir_idx), - (band_idx * BAND_MAX * sizeof(uint32_t)) & 0x7F); - - - set_iir_band_coeff(codec, iir_idx, band_idx, - ucontrol->value.integer.value[0]); - set_iir_band_coeff(codec, iir_idx, band_idx, - ucontrol->value.integer.value[1]); - set_iir_band_coeff(codec, iir_idx, band_idx, - ucontrol->value.integer.value[2]); - set_iir_band_coeff(codec, iir_idx, band_idx, - ucontrol->value.integer.value[3]); - set_iir_band_coeff(codec, iir_idx, band_idx, - ucontrol->value.integer.value[4]); - - dev_dbg(codec->dev, "%s: IIR #%d band #%d b0 = 0x%x\n" - "%s: IIR #%d band #%d b1 = 0x%x\n" - "%s: IIR #%d band #%d b2 = 0x%x\n" - "%s: IIR #%d band #%d a1 = 0x%x\n" - "%s: IIR #%d band #%d a2 = 0x%x\n", - __func__, iir_idx, band_idx, - get_iir_band_coeff(codec, iir_idx, band_idx, 0), - __func__, iir_idx, band_idx, - get_iir_band_coeff(codec, iir_idx, band_idx, 1), - __func__, iir_idx, band_idx, - get_iir_band_coeff(codec, iir_idx, band_idx, 2), - __func__, iir_idx, band_idx, - get_iir_band_coeff(codec, iir_idx, band_idx, 3), - __func__, iir_idx, band_idx, - get_iir_band_coeff(codec, iir_idx, band_idx, 4)); - return 0; -} - -static void tx_hpf_corner_freq_callback(struct work_struct *work) -{ - struct delayed_work *hpf_delayed_work; - struct hpf_work *hpf_work; - struct snd_soc_codec *codec; - struct msm_dig *msm_dig_cdc; - u16 tx_mux_ctl_reg; - u8 hpf_cut_of_freq; - - hpf_delayed_work = to_delayed_work(work); - hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork); - codec = hpf_work->dig_cdc->codec; - msm_dig_cdc = codec->control_data; - hpf_cut_of_freq = hpf_work->tx_hpf_cut_of_freq; - - tx_mux_ctl_reg = MSM89XX_CDC_CORE_TX1_MUX_CTL + - (hpf_work->decimator - 1) * 32; - - dev_dbg(codec->dev, "%s(): decimator %u hpf_cut_of_freq 0x%x\n", - __func__, hpf_work->decimator, (unsigned int)hpf_cut_of_freq); - msm_dig_cdc->update_clkdiv(msm_dig_cdc->handle, 0x51); - - snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x30, hpf_cut_of_freq << 4); -} - -static int msm_dig_cdc_codec_set_iir_gain(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, int event) -{ - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - int value = 0, reg; - - switch (event) { - case SND_SOC_DAPM_POST_PMU: - if (w->shift == 0) - reg = MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL; - else if (w->shift == 1) - reg = MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL; - else - goto ret; - value = snd_soc_read(codec, reg); - snd_soc_write(codec, reg, value); - break; - default: - pr_err("%s: event = %d not expected\n", __func__, event); - } -ret: - return 0; -} - -static int msm_dig_cdc_compander_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msm_dig_priv *dig_cdc = snd_soc_codec_get_drvdata(codec); - int comp_idx = ((struct soc_multi_mixer_control *) - kcontrol->private_value)->reg; - int rx_idx = ((struct soc_multi_mixer_control *) - kcontrol->private_value)->shift; - - dev_dbg(codec->dev, "%s: msm_dig_cdc->comp[%d]_enabled[%d] = %d\n", - __func__, comp_idx, rx_idx, - dig_cdc->comp_enabled[rx_idx]); - - ucontrol->value.integer.value[0] = dig_cdc->comp_enabled[rx_idx]; - - dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", - __func__, ucontrol->value.integer.value[0]); - - return 0; -} - -static int msm_dig_cdc_compander_set(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msm_dig_priv *dig_cdc = snd_soc_codec_get_drvdata(codec); - int comp_idx = ((struct soc_multi_mixer_control *) - kcontrol->private_value)->reg; - int rx_idx = ((struct soc_multi_mixer_control *) - kcontrol->private_value)->shift; - int value = ucontrol->value.integer.value[0]; - - dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", - __func__, ucontrol->value.integer.value[0]); - - if (dig_cdc->version >= DIANGU) { - if (!value) - dig_cdc->comp_enabled[rx_idx] = 0; - else - dig_cdc->comp_enabled[rx_idx] = comp_idx; - } - - dev_dbg(codec->dev, "%s: msm_dig_cdc->comp[%d]_enabled[%d] = %d\n", - __func__, comp_idx, rx_idx, - dig_cdc->comp_enabled[rx_idx]); - - return 0; -} - -static const struct snd_kcontrol_new compander_kcontrols[] = { - SOC_SINGLE_EXT("COMP0 RX1", COMPANDER_1, MSM89XX_RX1, 1, 0, - msm_dig_cdc_compander_get, msm_dig_cdc_compander_set), - - SOC_SINGLE_EXT("COMP0 RX2", COMPANDER_1, MSM89XX_RX2, 1, 0, - msm_dig_cdc_compander_get, msm_dig_cdc_compander_set), - -}; - -static int msm_dig_cdc_set_interpolator_rate(struct snd_soc_dai *dai, - u8 rx_fs_rate_reg_val, - u32 sample_rate) -{ - snd_soc_update_bits(dai->codec, - MSM89XX_CDC_CORE_RX1_B5_CTL, 0xF0, rx_fs_rate_reg_val); - snd_soc_update_bits(dai->codec, - MSM89XX_CDC_CORE_RX2_B5_CTL, 0xF0, rx_fs_rate_reg_val); - return 0; -} - -static int msm_dig_cdc_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params, - struct snd_soc_dai *dai) -{ - u8 tx_fs_rate, rx_fs_rate, rx_clk_fs_rate; - int ret; - - dev_dbg(dai->codec->dev, - "%s: dai_name = %s DAI-ID %x rate %d num_ch %d format %d\n", - __func__, dai->name, dai->id, params_rate(params), - params_channels(params), params_format(params)); - - switch (params_rate(params)) { - case 8000: - tx_fs_rate = 0x00; - rx_fs_rate = 0x00; - rx_clk_fs_rate = 0x00; - break; - case 16000: - tx_fs_rate = 0x20; - rx_fs_rate = 0x20; - rx_clk_fs_rate = 0x01; - break; - case 32000: - tx_fs_rate = 0x40; - rx_fs_rate = 0x40; - rx_clk_fs_rate = 0x02; - break; - case 44100: - case 48000: - tx_fs_rate = 0x60; - rx_fs_rate = 0x60; - rx_clk_fs_rate = 0x03; - break; - case 96000: - tx_fs_rate = 0x80; - rx_fs_rate = 0x80; - rx_clk_fs_rate = 0x04; - break; - case 192000: - tx_fs_rate = 0xA0; - rx_fs_rate = 0xA0; - rx_clk_fs_rate = 0x05; - break; - default: - dev_err(dai->codec->dev, - "%s: Invalid sampling rate %d\n", __func__, - params_rate(params)); - return -EINVAL; - } - - snd_soc_update_bits(dai->codec, - MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 0x0F, rx_clk_fs_rate); - - switch (substream->stream) { - case SNDRV_PCM_STREAM_CAPTURE: - break; - case SNDRV_PCM_STREAM_PLAYBACK: - ret = msm_dig_cdc_set_interpolator_rate(dai, rx_fs_rate, - params_rate(params)); - if (ret < 0) { - dev_err(dai->codec->dev, - "%s: set decimator rate failed %d\n", __func__, - ret); - return ret; - } - break; - default: - dev_err(dai->codec->dev, - "%s: Invalid stream type %d\n", __func__, - substream->stream); - return -EINVAL; - } - switch (params_format(params)) { - case SNDRV_PCM_FORMAT_S16_LE: - snd_soc_update_bits(dai->codec, - MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 0x20, 0x20); - break; - case SNDRV_PCM_FORMAT_S24_LE: - snd_soc_update_bits(dai->codec, - MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 0x20, 0x00); - break; - default: - dev_err(dai->codec->dev, "%s: wrong format selected\n", - __func__); - return -EINVAL; - } - return 0; -} - -static int msm_dig_cdc_codec_enable_dmic(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, - int event) -{ - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msm_dig_priv *dig_cdc = snd_soc_codec_get_drvdata(codec); - u8 dmic_clk_en; - u16 dmic_clk_reg; - s32 *dmic_clk_cnt; - unsigned int dmic; - int ret; - char *dmic_num = strpbrk(w->name, "1234"); - - if (dmic_num == NULL) { - dev_err(codec->dev, "%s: Invalid DMIC\n", __func__); - return -EINVAL; - } - - ret = kstrtouint(dmic_num, 10, &dmic); - if (ret < 0) { - dev_err(codec->dev, - "%s: Invalid DMIC line on the codec\n", __func__); - return -EINVAL; - } - - switch (dmic) { - case 1: - case 2: - dmic_clk_en = 0x01; - dmic_clk_cnt = &(dig_cdc->dmic_1_2_clk_cnt); - dmic_clk_reg = MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL; - dev_dbg(codec->dev, - "%s() event %d DMIC%d dmic_1_2_clk_cnt %d\n", - __func__, event, dmic, *dmic_clk_cnt); - break; - case 3: - case 4: - dmic_clk_en = 0x01; - dmic_clk_cnt = &(dig_cdc->dmic_3_4_clk_cnt); - dmic_clk_reg = MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL; - dev_dbg(codec->dev, - "%s() event %d DMIC%d dmic_3_4_clk_cnt %d\n", - __func__, event, dmic, *dmic_clk_cnt); - break; - default: - dev_err(codec->dev, "%s: Invalid DMIC Selection\n", __func__); - return -EINVAL; - } - - switch (event) { - case SND_SOC_DAPM_PRE_PMU: - (*dmic_clk_cnt)++; - if (*dmic_clk_cnt == 1) { - snd_soc_update_bits(codec, dmic_clk_reg, - 0x0E, 0x02); - snd_soc_update_bits(codec, dmic_clk_reg, - dmic_clk_en, dmic_clk_en); - } - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_TX1_DMIC_CTL + (dmic - 1) * 0x20, - 0x07, 0x01); - break; - case SND_SOC_DAPM_POST_PMD: - (*dmic_clk_cnt)--; - if (*dmic_clk_cnt == 0) - snd_soc_update_bits(codec, dmic_clk_reg, - dmic_clk_en, 0); - break; - } - return 0; -} - -static int msm_dig_cdc_codec_enable_dec(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, - int event) -{ - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msm_asoc_mach_data *pdata = NULL; - unsigned int decimator; - struct msm_dig_priv *dig_cdc = snd_soc_codec_get_drvdata(codec); - struct msm_dig *msm_dig_cdc = codec->control_data; - char *dec_name = NULL; - char *widget_name = NULL; - char *temp; - int ret = 0, i; - u16 dec_reset_reg, tx_vol_ctl_reg, tx_mux_ctl_reg; - u8 dec_hpf_cut_of_freq; - int offset; - char *dec_num; - - pdata = snd_soc_card_get_drvdata(codec->component.card); - dev_dbg(codec->dev, "%s %d\n", __func__, event); - - widget_name = kstrndup(w->name, 15, GFP_KERNEL); - if (!widget_name) - return -ENOMEM; - temp = widget_name; - - dec_name = strsep(&widget_name, " "); - widget_name = temp; - if (!dec_name) { - dev_err(codec->dev, - "%s: Invalid decimator = %s\n", __func__, w->name); - ret = -EINVAL; - goto out; - } - - dec_num = strpbrk(dec_name, "12345"); - if (dec_num == NULL) { - dev_err(codec->dev, "%s: Invalid Decimator\n", __func__); - ret = -EINVAL; - goto out; - } - - ret = kstrtouint(dec_num, 10, &decimator); - if (ret < 0) { - dev_err(codec->dev, - "%s: Invalid decimator = %s\n", __func__, dec_name); - ret = -EINVAL; - goto out; - } - - dev_dbg(codec->dev, - "%s(): widget = %s dec_name = %s decimator = %u\n", __func__, - w->name, dec_name, decimator); - - if (w->reg == MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL) { - dec_reset_reg = MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL; - offset = 0; - } else { - dev_err(codec->dev, "%s: Error, incorrect dec\n", __func__); - ret = -EINVAL; - goto out; - } - - tx_vol_ctl_reg = MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG + - 32 * (decimator - 1); - tx_mux_ctl_reg = MSM89XX_CDC_CORE_TX1_MUX_CTL + - 32 * (decimator - 1); - - switch (event) { - case SND_SOC_DAPM_PRE_PMU: - /* Enableable TX digital mute */ - snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x01); - for (i = 0; i < NUM_DECIMATORS; i++) { - if (decimator == i + 1) - dig_cdc->dec_active[i] = true; - } - - dec_hpf_cut_of_freq = snd_soc_read(codec, tx_mux_ctl_reg); - - dec_hpf_cut_of_freq = (dec_hpf_cut_of_freq & 0x30) >> 4; - - tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq = - dec_hpf_cut_of_freq; - - if (dec_hpf_cut_of_freq != CF_MIN_3DB_150HZ) { - - /* set cut of freq to CF_MIN_3DB_150HZ (0x1); */ - snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x30, - CF_MIN_3DB_150HZ << 4); - } - msm_dig_cdc->update_clkdiv(msm_dig_cdc->handle, 0x42); - break; - case SND_SOC_DAPM_POST_PMU: - /* enable HPF */ - snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x08, 0x00); - - if (tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq != - CF_MIN_3DB_150HZ) { - - schedule_delayed_work(&tx_hpf_work[decimator - 1].dwork, - msecs_to_jiffies(300)); - } - /* apply the digital gain after the decimator is enabled*/ - if ((w->shift) < ARRAY_SIZE(tx_digital_gain_reg)) - snd_soc_write(codec, - tx_digital_gain_reg[w->shift + offset], - snd_soc_read(codec, - tx_digital_gain_reg[w->shift + offset]) - ); - if (pdata->lb_mode) { - pr_debug("%s: loopback mode unmute the DEC\n", - __func__); - snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x00); - } - snd_soc_update_bits(codec, tx_vol_ctl_reg, - 0x01, 0x00); - - break; - case SND_SOC_DAPM_PRE_PMD: - snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x01); - msleep(20); - snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x08, 0x08); - cancel_delayed_work_sync(&tx_hpf_work[decimator - 1].dwork); - break; - case SND_SOC_DAPM_POST_PMD: - snd_soc_update_bits(codec, dec_reset_reg, 1 << w->shift, - 1 << w->shift); - snd_soc_update_bits(codec, dec_reset_reg, 1 << w->shift, 0x0); - snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x08, 0x08); - snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x30, - (tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq) << 4); - snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x00); - for (i = 0; i < NUM_DECIMATORS; i++) { - if (decimator == i + 1) - dig_cdc->dec_active[i] = false; - } - break; - } -out: - kfree(widget_name); - return ret; -} - -static int msm_dig_cdc_event_notify(struct notifier_block *block, - unsigned long val, - void *data) -{ - enum dig_cdc_notify_event event = (enum dig_cdc_notify_event)val; - struct snd_soc_codec *codec = registered_digcodec; - struct msm_dig *msm_dig_cdc = codec->control_data; - struct msm_asoc_mach_data *pdata = NULL; - - pdata = snd_soc_card_get_drvdata(codec->component.card); - - switch (event) { - case DIG_CDC_EVENT_CLK_ON: - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_CLK_PDM_CTL, 0x03, 0x03); - if (pdata->mclk_freq == MCLK_RATE_12P288MHZ || - pdata->native_clk_set) - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_TOP_CTL, 0x01, 0x00); - else if (pdata->mclk_freq == MCLK_RATE_9P6MHZ) - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_TOP_CTL, 0x01, 0x01); - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_CLK_MCLK_CTL, 0x01, 0x01); - break; - case DIG_CDC_EVENT_CLK_OFF: - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_CLK_PDM_CTL, 0x03, 0x00); - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_CLK_MCLK_CTL, 0x01, 0x00); - break; - case DIG_CDC_EVENT_RX1_MUTE_ON: - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_RX1_B6_CTL, 0x01, 0x01); - msm_dig_cdc->mute_mask |= HPHL_PA_DISABLE; - break; - case DIG_CDC_EVENT_RX1_MUTE_OFF: - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_RX1_B6_CTL, 0x01, 0x00); - msm_dig_cdc->mute_mask &= (~HPHL_PA_DISABLE); - break; - case DIG_CDC_EVENT_RX2_MUTE_ON: - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_RX2_B6_CTL, 0x01, 0x01); - msm_dig_cdc->mute_mask |= HPHR_PA_DISABLE; - break; - case DIG_CDC_EVENT_RX2_MUTE_OFF: - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_RX2_B6_CTL, 0x01, 0x00); - msm_dig_cdc->mute_mask &= (~HPHR_PA_DISABLE); - break; - case DIG_CDC_EVENT_RX3_MUTE_ON: - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_RX3_B6_CTL, 0x01, 0x01); - msm_dig_cdc->mute_mask |= SPKR_PA_DISABLE; - break; - case DIG_CDC_EVENT_RX3_MUTE_OFF: - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_RX3_B6_CTL, 0x01, 0x00); - msm_dig_cdc->mute_mask &= (~SPKR_PA_DISABLE); - break; - case DIG_CDC_EVENT_PRE_RX1_INT_ON: - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_RX1_B3_CTL, 0x1C, 0x14); - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_RX1_B4_CTL, 0x18, 0x10); - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_RX1_B3_CTL, 0x80, 0x80); - break; - case DIG_CDC_EVENT_PRE_RX2_INT_ON: - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_RX2_B3_CTL, 0x1C, 0x14); - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_RX2_B4_CTL, 0x18, 0x10); - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_RX2_B3_CTL, 0x80, 0x80); - break; - case DIG_CDC_EVENT_POST_RX1_INT_OFF: - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_RX1_B3_CTL, 0x1C, 0x00); - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_RX1_B4_CTL, 0x18, 0xFF); - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_RX1_B3_CTL, 0x80, 0x00); - break; - case DIG_CDC_EVENT_POST_RX2_INT_OFF: - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_RX2_B3_CTL, 0x1C, 0x00); - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_RX2_B4_CTL, 0x18, 0xFF); - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_RX2_B3_CTL, 0x80, 0x00); - break; - case DIG_CDC_EVENT_SSR_DOWN: - regcache_cache_only(msm_dig_cdc->regmap, true); - break; - case DIG_CDC_EVENT_SSR_UP: - regcache_cache_only(msm_dig_cdc->regmap, false); - regcache_mark_dirty(msm_dig_cdc->regmap); - regcache_sync(msm_dig_cdc->regmap); - break; - case DIG_CDC_EVENT_INVALID: - default: - break; - } - return 0; -} - -static ssize_t msm_dig_codec_version_read(struct snd_info_entry *entry, - void *file_private_data, - struct file *file, - char __user *buf, size_t count, - loff_t pos) -{ - struct msm_dig_priv *msm_dig; - char buffer[MSM_DIG_CDC_VERSION_ENTRY_SIZE]; - int len = 0; - - msm_dig = (struct msm_dig_priv *) entry->private_data; - if (!msm_dig) { - pr_err("%s: msm_dig priv is null\n", __func__); - return -EINVAL; - } - - switch (msm_dig->version) { - case DRAX_CDC: - len = snprintf(buffer, sizeof(buffer), "DRAX_CDC_1_0\n"); - break; - default: - len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n"); - } - - return simple_read_from_buffer(buf, count, &pos, buffer, len); -} - -static struct snd_info_entry_ops msm_dig_codec_info_ops = { - .read = msm_dig_codec_version_read, -}; - -/* - * msm_dig_codec_info_create_codec_entry - creates msm_dig module - * @codec_root: The parent directory - * @codec: Codec instance - * - * Creates msm_dig module and version entry under the given - * parent directory. - * - * Return: 0 on success or negative error code on failure. - */ -int msm_dig_codec_info_create_codec_entry(struct snd_info_entry *codec_root, - struct snd_soc_codec *codec) -{ - struct snd_info_entry *version_entry; - struct msm_dig_priv *msm_dig; - struct snd_soc_card *card; - - if (!codec_root || !codec) - return -EINVAL; - - msm_dig = snd_soc_codec_get_drvdata(codec); - card = codec->component.card; - msm_dig->entry = snd_register_module_info(codec_root->module, - "msm_digital", - codec_root); - if (!msm_dig->entry) { - dev_dbg(codec->dev, "%s: failed to create msm_digital entry\n", - __func__); - return -ENOMEM; - } - - version_entry = snd_info_create_card_entry(card->snd_card, - "version", - msm_dig->entry); - if (!version_entry) { - dev_dbg(codec->dev, "%s: failed to create msm_digital version entry\n", - __func__); - return -ENOMEM; - } - - version_entry->private_data = msm_dig; - version_entry->size = MSM_DIG_CDC_VERSION_ENTRY_SIZE; - version_entry->content = SNDRV_INFO_CONTENT_DATA; - version_entry->c.ops = &msm_dig_codec_info_ops; - - if (snd_info_register(version_entry) < 0) { - snd_info_free_entry(version_entry); - return -ENOMEM; - } - msm_dig->version_entry = version_entry; - return 0; -} -EXPORT_SYMBOL(msm_dig_codec_info_create_codec_entry); - -static int msm_dig_cdc_soc_probe(struct snd_soc_codec *codec) -{ - struct msm_dig_priv *dig_cdc = NULL; - struct msm_dig *msm_dig_cdc = dev_get_drvdata(codec->dev); - int i, ret; - - dig_cdc = devm_kzalloc(codec->dev, sizeof(struct msm_dig_priv), - GFP_KERNEL); - if (!dig_cdc) - return -ENOMEM; - snd_soc_codec_set_drvdata(codec, dig_cdc); - dig_cdc->codec = codec; - codec->control_data = msm_dig_cdc; - - snd_soc_add_codec_controls(codec, compander_kcontrols, - ARRAY_SIZE(compander_kcontrols)); - - for (i = 0; i < NUM_DECIMATORS; i++) { - tx_hpf_work[i].dig_cdc = dig_cdc; - tx_hpf_work[i].decimator = i + 1; - INIT_DELAYED_WORK(&tx_hpf_work[i].dwork, - tx_hpf_corner_freq_callback); - } - - for (i = 0; i < MSM89XX_RX_MAX; i++) - dig_cdc->comp_enabled[i] = COMPANDER_NONE; - - /* Register event notifier */ - msm_dig_cdc->nblock.notifier_call = msm_dig_cdc_event_notify; - if (msm_dig_cdc->register_notifier) { - ret = msm_dig_cdc->register_notifier(msm_dig_cdc->handle, - &msm_dig_cdc->nblock, - true); - if (ret) { - pr_err("%s: Failed to register notifier %d\n", - __func__, ret); - return ret; - } - } - if (msm_dig_cdc->get_cdc_version) - dig_cdc->version = msm_dig_cdc->get_cdc_version( - msm_dig_cdc->handle); - registered_digcodec = codec; - return 0; -} - -static int msm_dig_cdc_soc_remove(struct snd_soc_codec *codec) -{ - struct msm_dig *msm_dig_cdc = dev_get_drvdata(codec->dev); - - if (msm_dig_cdc->register_notifier) - msm_dig_cdc->register_notifier(msm_dig_cdc->handle, - &msm_dig_cdc->nblock, - false); - iounmap(msm_dig_cdc->dig_base); - return 0; -} - -static const struct snd_soc_dapm_route audio_dig_map[] = { - {"RX_I2S_CLK", NULL, "CDC_CONN"}, - {"I2S RX1", NULL, "RX_I2S_CLK"}, - {"I2S RX2", NULL, "RX_I2S_CLK"}, - {"I2S RX3", NULL, "RX_I2S_CLK"}, - - {"I2S TX1", NULL, "TX_I2S_CLK"}, - {"I2S TX2", NULL, "TX_I2S_CLK"}, - {"I2S TX3", NULL, "TX_I2S_CLK"}, - {"I2S TX4", NULL, "TX_I2S_CLK"}, - {"I2S TX5", NULL, "TX_I2S_CLK"}, - {"I2S TX6", NULL, "TX_I2S_CLK"}, - - {"I2S TX1", NULL, "DEC1 MUX"}, - {"I2S TX2", NULL, "DEC2 MUX"}, - {"I2S TX3", NULL, "DEC3 MUX"}, - {"I2S TX4", NULL, "DEC4 MUX"}, - {"I2S TX5", NULL, "DEC3 MUX"}, - {"I2S TX6", NULL, "DEC4 MUX"}, - {"I2S TX6", NULL, "DEC5 MUX"}, - - {"PDM_OUT_RX1", NULL, "RX1 CHAIN"}, - {"PDM_OUT_RX2", NULL, "RX2 CHAIN"}, - {"PDM_OUT_RX3", NULL, "RX3 CHAIN"}, - - {"RX1 CHAIN", NULL, "RX1 MIX2"}, - {"RX2 CHAIN", NULL, "RX2 MIX2"}, - {"RX3 CHAIN", NULL, "RX3 MIX1"}, - - {"RX1 MIX1", NULL, "RX1 MIX1 INP1"}, - {"RX1 MIX1", NULL, "RX1 MIX1 INP2"}, - {"RX1 MIX1", NULL, "RX1 MIX1 INP3"}, - {"RX2 MIX1", NULL, "RX2 MIX1 INP1"}, - {"RX2 MIX1", NULL, "RX2 MIX1 INP2"}, - {"RX3 MIX1", NULL, "RX3 MIX1 INP1"}, - {"RX3 MIX1", NULL, "RX3 MIX1 INP2"}, - {"RX1 MIX2", NULL, "RX1 MIX1"}, - {"RX1 MIX2", NULL, "RX1 MIX2 INP1"}, - {"RX2 MIX2", NULL, "RX2 MIX1"}, - {"RX2 MIX2", NULL, "RX2 MIX2 INP1"}, - - {"RX1 MIX1 INP1", "RX1", "I2S RX1"}, - {"RX1 MIX1 INP1", "RX2", "I2S RX2"}, - {"RX1 MIX1 INP1", "RX3", "I2S RX3"}, - {"RX1 MIX1 INP1", "IIR1", "IIR1"}, - {"RX1 MIX1 INP1", "IIR2", "IIR2"}, - {"RX1 MIX1 INP2", "RX1", "I2S RX1"}, - {"RX1 MIX1 INP2", "RX2", "I2S RX2"}, - {"RX1 MIX1 INP2", "RX3", "I2S RX3"}, - {"RX1 MIX1 INP2", "IIR1", "IIR1"}, - {"RX1 MIX1 INP2", "IIR2", "IIR2"}, - {"RX1 MIX1 INP3", "RX1", "I2S RX1"}, - {"RX1 MIX1 INP3", "RX2", "I2S RX2"}, - {"RX1 MIX1 INP3", "RX3", "I2S RX3"}, - - {"RX2 MIX1 INP1", "RX1", "I2S RX1"}, - {"RX2 MIX1 INP1", "RX2", "I2S RX2"}, - {"RX2 MIX1 INP1", "RX3", "I2S RX3"}, - {"RX2 MIX1 INP1", "IIR1", "IIR1"}, - {"RX2 MIX1 INP1", "IIR2", "IIR2"}, - {"RX2 MIX1 INP2", "RX1", "I2S RX1"}, - {"RX2 MIX1 INP2", "RX2", "I2S RX2"}, - {"RX2 MIX1 INP2", "RX3", "I2S RX3"}, - {"RX2 MIX1 INP2", "IIR1", "IIR1"}, - {"RX2 MIX1 INP2", "IIR2", "IIR2"}, - - {"RX3 MIX1 INP1", "RX1", "I2S RX1"}, - {"RX3 MIX1 INP1", "RX2", "I2S RX2"}, - {"RX3 MIX1 INP1", "RX3", "I2S RX3"}, - {"RX3 MIX1 INP1", "IIR1", "IIR1"}, - {"RX3 MIX1 INP1", "IIR2", "IIR2"}, - {"RX3 MIX1 INP2", "RX1", "I2S RX1"}, - {"RX3 MIX1 INP2", "RX2", "I2S RX2"}, - {"RX3 MIX1 INP2", "RX3", "I2S RX3"}, - {"RX3 MIX1 INP2", "IIR1", "IIR1"}, - {"RX3 MIX1 INP2", "IIR2", "IIR2"}, - - {"RX1 MIX2 INP1", "IIR1", "IIR1"}, - {"RX2 MIX2 INP1", "IIR1", "IIR1"}, - {"RX1 MIX2 INP1", "IIR2", "IIR2"}, - {"RX2 MIX2 INP1", "IIR2", "IIR2"}, - - /* Decimator Inputs */ - {"DEC1 MUX", "DMIC1", "DMIC1"}, - {"DEC1 MUX", "DMIC2", "DMIC2"}, - {"DEC1 MUX", "DMIC3", "DMIC3"}, - {"DEC1 MUX", "DMIC4", "DMIC4"}, - {"DEC1 MUX", "ADC1", "ADC1_IN"}, - {"DEC1 MUX", "ADC2", "ADC2_IN"}, - {"DEC1 MUX", "ADC3", "ADC3_IN"}, - {"DEC1 MUX", NULL, "CDC_CONN"}, - - {"DEC2 MUX", "DMIC1", "DMIC1"}, - {"DEC2 MUX", "DMIC2", "DMIC2"}, - {"DEC2 MUX", "DMIC3", "DMIC3"}, - {"DEC2 MUX", "DMIC4", "DMIC4"}, - {"DEC2 MUX", "ADC1", "ADC1_IN"}, - {"DEC2 MUX", "ADC2", "ADC2_IN"}, - {"DEC2 MUX", "ADC3", "ADC3_IN"}, - {"DEC2 MUX", NULL, "CDC_CONN"}, - - {"DEC3 MUX", "DMIC1", "DMIC1"}, - {"DEC3 MUX", "DMIC2", "DMIC2"}, - {"DEC3 MUX", "DMIC3", "DMIC3"}, - {"DEC3 MUX", "DMIC4", "DMIC4"}, - {"DEC3 MUX", "ADC1", "ADC1_IN"}, - {"DEC3 MUX", "ADC2", "ADC2_IN"}, - {"DEC3 MUX", "ADC3", "ADC3_IN"}, - {"DEC3 MUX", NULL, "CDC_CONN"}, - - {"DEC4 MUX", "DMIC1", "DMIC1"}, - {"DEC4 MUX", "DMIC2", "DMIC2"}, - {"DEC4 MUX", "DMIC3", "DMIC3"}, - {"DEC4 MUX", "DMIC4", "DMIC4"}, - {"DEC4 MUX", "ADC1", "ADC1_IN"}, - {"DEC4 MUX", "ADC2", "ADC2_IN"}, - {"DEC4 MUX", "ADC3", "ADC3_IN"}, - {"DEC4 MUX", NULL, "CDC_CONN"}, - - {"DEC5 MUX", "DMIC1", "DMIC1"}, - {"DEC5 MUX", "DMIC2", "DMIC2"}, - {"DEC5 MUX", "DMIC3", "DMIC3"}, - {"DEC5 MUX", "DMIC4", "DMIC4"}, - {"DEC5 MUX", "ADC1", "ADC1_IN"}, - {"DEC5 MUX", "ADC2", "ADC2_IN"}, - {"DEC5 MUX", "ADC3", "ADC3_IN"}, - {"DEC5 MUX", NULL, "CDC_CONN"}, - - {"IIR1", NULL, "IIR1 INP1 MUX"}, - {"IIR1 INP1 MUX", "DEC1", "DEC1 MUX"}, - {"IIR1 INP1 MUX", "DEC2", "DEC2 MUX"}, - {"IIR1 INP1 MUX", "DEC3", "DEC3 MUX"}, - {"IIR1 INP1 MUX", "DEC4", "DEC4 MUX"}, - {"IIR2", NULL, "IIR2 INP1 MUX"}, - {"IIR2 INP1 MUX", "DEC1", "DEC1 MUX"}, - {"IIR2 INP1 MUX", "DEC2", "DEC2 MUX"}, - {"IIR1 INP1 MUX", "DEC3", "DEC3 MUX"}, - {"IIR1 INP1 MUX", "DEC4", "DEC4 MUX"}, -}; - -static const char * const rx_mix1_text[] = { - "ZERO", "IIR1", "IIR2", "RX1", "RX2", "RX3" -}; - -static const char * const rx_mix2_text[] = { - "ZERO", "IIR1", "IIR2" -}; - -static const char * const dec_mux_text[] = { - "ZERO", "ADC1", "ADC2", "ADC3", "DMIC1", "DMIC2", "DMIC3", "DMIC4" -}; - -static const char * const iir_inp1_text[] = { - "ZERO", "DEC1", "DEC2", "RX1", "RX2", "RX3", "DEC3", "DEC4" -}; -/* RX1 MIX1 */ -static const struct soc_enum rx_mix1_inp1_chain_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX1_B1_CTL, - 0, 6, rx_mix1_text); - -static const struct soc_enum rx_mix1_inp2_chain_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX1_B1_CTL, - 3, 6, rx_mix1_text); - -static const struct soc_enum rx_mix1_inp3_chain_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX1_B2_CTL, - 0, 6, rx_mix1_text); - -/* RX1 MIX2 */ -static const struct soc_enum rx_mix2_inp1_chain_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX1_B3_CTL, - 0, 3, rx_mix2_text); - -/* RX2 MIX1 */ -static const struct soc_enum rx2_mix1_inp1_chain_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX2_B1_CTL, - 0, 6, rx_mix1_text); - -static const struct soc_enum rx2_mix1_inp2_chain_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX2_B1_CTL, - 3, 6, rx_mix1_text); - -static const struct soc_enum rx2_mix1_inp3_chain_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX2_B1_CTL, - 0, 6, rx_mix1_text); - -/* RX2 MIX2 */ -static const struct soc_enum rx2_mix2_inp1_chain_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX2_B3_CTL, - 0, 3, rx_mix2_text); - -/* RX3 MIX1 */ -static const struct soc_enum rx3_mix1_inp1_chain_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX3_B1_CTL, - 0, 6, rx_mix1_text); - -static const struct soc_enum rx3_mix1_inp2_chain_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX3_B1_CTL, - 3, 6, rx_mix1_text); - -static const struct soc_enum rx3_mix1_inp3_chain_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX3_B1_CTL, - 0, 6, rx_mix1_text); - -/* DEC */ -static const struct soc_enum dec1_mux_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_TX_B1_CTL, - 0, 8, dec_mux_text); - -static const struct soc_enum dec2_mux_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_TX_B1_CTL, - 3, 8, dec_mux_text); - -static const struct soc_enum dec3_mux_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_TX_B2_CTL, - 0, 8, dec_mux_text); - -static const struct soc_enum dec4_mux_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_TX_B2_CTL, - 3, 8, dec_mux_text); - -static const struct soc_enum decsva_mux_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_TX_B3_CTL, - 0, 8, dec_mux_text); - -static const struct soc_enum iir1_inp1_mux_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL, - 0, 8, iir_inp1_text); - -static const struct soc_enum iir2_inp1_mux_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL, - 0, 8, iir_inp1_text); - -/*cut of frequency for high pass filter*/ -static const char * const cf_text[] = { - "MIN_3DB_4Hz", "MIN_3DB_75Hz", "MIN_3DB_150Hz" -}; - -static const struct soc_enum cf_rxmix1_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_RX1_B4_CTL, 0, 3, cf_text); - -static const struct soc_enum cf_rxmix2_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_RX2_B4_CTL, 0, 3, cf_text); - -static const struct soc_enum cf_rxmix3_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_RX3_B4_CTL, 0, 3, cf_text); - -static const struct snd_kcontrol_new rx3_mix1_inp1_mux = - SOC_DAPM_ENUM("RX3 MIX1 INP1 Mux", rx3_mix1_inp1_chain_enum); - -#define MSM89XX_DEC_ENUM(xname, xenum) \ -{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ - .info = snd_soc_info_enum_double, \ - .get = snd_soc_dapm_get_enum_double, \ - .put = msm_dig_cdc_put_dec_enum, \ - .private_value = (unsigned long)&xenum } - -static const struct snd_kcontrol_new dec1_mux = - MSM89XX_DEC_ENUM("DEC1 MUX Mux", dec1_mux_enum); - -static const struct snd_kcontrol_new dec2_mux = - MSM89XX_DEC_ENUM("DEC2 MUX Mux", dec2_mux_enum); - -static const struct snd_kcontrol_new dec3_mux = - MSM89XX_DEC_ENUM("DEC3 MUX Mux", dec3_mux_enum); - -static const struct snd_kcontrol_new dec4_mux = - MSM89XX_DEC_ENUM("DEC4 MUX Mux", dec4_mux_enum); - -static const struct snd_kcontrol_new decsva_mux = - MSM89XX_DEC_ENUM("DEC5 MUX Mux", decsva_mux_enum); - -static const struct snd_kcontrol_new iir1_inp1_mux = - SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum); - -static const struct snd_kcontrol_new iir2_inp1_mux = - SOC_DAPM_ENUM("IIR2 INP1 Mux", iir2_inp1_mux_enum); - -static const struct snd_kcontrol_new rx_mix1_inp1_mux = - SOC_DAPM_ENUM("RX1 MIX1 INP1 Mux", rx_mix1_inp1_chain_enum); - -static const struct snd_kcontrol_new rx_mix1_inp2_mux = - SOC_DAPM_ENUM("RX1 MIX1 INP2 Mux", rx_mix1_inp2_chain_enum); - -static const struct snd_kcontrol_new rx_mix1_inp3_mux = - SOC_DAPM_ENUM("RX1 MIX1 INP3 Mux", rx_mix1_inp3_chain_enum); - -static const struct snd_kcontrol_new rx2_mix1_inp1_mux = - SOC_DAPM_ENUM("RX2 MIX1 INP1 Mux", rx2_mix1_inp1_chain_enum); - -static const struct snd_kcontrol_new rx2_mix1_inp2_mux = - SOC_DAPM_ENUM("RX2 MIX1 INP2 Mux", rx2_mix1_inp2_chain_enum); - -static const struct snd_kcontrol_new rx2_mix1_inp3_mux = - SOC_DAPM_ENUM("RX2 MIX1 INP3 Mux", rx2_mix1_inp3_chain_enum); - -static const struct snd_kcontrol_new rx3_mix1_inp2_mux = - SOC_DAPM_ENUM("RX3 MIX1 INP2 Mux", rx3_mix1_inp2_chain_enum); - -static const struct snd_kcontrol_new rx3_mix1_inp3_mux = - SOC_DAPM_ENUM("RX3 MIX1 INP3 Mux", rx3_mix1_inp3_chain_enum); - -static const struct snd_kcontrol_new rx1_mix2_inp1_mux = - SOC_DAPM_ENUM("RX1 MIX2 INP1 Mux", rx_mix2_inp1_chain_enum); - -static const struct snd_kcontrol_new rx2_mix2_inp1_mux = - SOC_DAPM_ENUM("RX2 MIX2 INP1 Mux", rx2_mix2_inp1_chain_enum); - -static const struct snd_soc_dapm_widget msm_dig_dapm_widgets[] = { - SND_SOC_DAPM_AIF_IN("I2S RX1", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), - SND_SOC_DAPM_AIF_IN("I2S RX2", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), - SND_SOC_DAPM_AIF_IN("I2S RX3", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), - - SND_SOC_DAPM_AIF_OUT("I2S TX1", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), - SND_SOC_DAPM_AIF_OUT("I2S TX2", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), - SND_SOC_DAPM_AIF_OUT("I2S TX3", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), - SND_SOC_DAPM_AIF_OUT("I2S TX4", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), - SND_SOC_DAPM_AIF_OUT("I2S TX5", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), - SND_SOC_DAPM_AIF_OUT("I2S TX6", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), - - SND_SOC_DAPM_MIXER_E("RX1 MIX2", MSM89XX_CDC_CORE_CLK_RX_B1_CTL, - MSM89XX_RX1, 0, NULL, 0, - msm_dig_cdc_codec_enable_interpolator, - SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MIXER_E("RX2 MIX2", MSM89XX_CDC_CORE_CLK_RX_B1_CTL, - MSM89XX_RX2, 0, NULL, 0, - msm_dig_cdc_codec_enable_interpolator, - SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MIXER_E("RX3 MIX1", MSM89XX_CDC_CORE_CLK_RX_B1_CTL, - MSM89XX_RX3, 0, NULL, 0, - msm_dig_cdc_codec_enable_interpolator, - SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_MIXER("RX1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), - SND_SOC_DAPM_MIXER("RX2 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), - - SND_SOC_DAPM_MIXER_E("RX1 CHAIN", MSM89XX_CDC_CORE_RX1_B6_CTL, - MSM89XX_RX1, 0, NULL, 0, - msm_dig_cdc_codec_enable_rx_chain, - SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MIXER_E("RX2 CHAIN", MSM89XX_CDC_CORE_RX2_B6_CTL, - MSM89XX_RX2, 0, NULL, 0, - msm_dig_cdc_codec_enable_rx_chain, SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MIXER_E("RX3 CHAIN", MSM89XX_CDC_CORE_RX3_B6_CTL, - MSM89XX_RX3, 0, NULL, 0, - msm_dig_cdc_codec_enable_rx_chain, SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_MUX("RX1 MIX1 INP1", SND_SOC_NOPM, 0, 0, - &rx_mix1_inp1_mux), - SND_SOC_DAPM_MUX("RX1 MIX1 INP2", SND_SOC_NOPM, 0, 0, - &rx_mix1_inp2_mux), - SND_SOC_DAPM_MUX("RX1 MIX1 INP3", SND_SOC_NOPM, 0, 0, - &rx_mix1_inp3_mux), - - SND_SOC_DAPM_MUX("RX2 MIX1 INP1", SND_SOC_NOPM, 0, 0, - &rx2_mix1_inp1_mux), - SND_SOC_DAPM_MUX("RX2 MIX1 INP2", SND_SOC_NOPM, 0, 0, - &rx2_mix1_inp2_mux), - SND_SOC_DAPM_MUX("RX2 MIX1 INP3", SND_SOC_NOPM, 0, 0, - &rx2_mix1_inp3_mux), - - SND_SOC_DAPM_MUX("RX3 MIX1 INP1", SND_SOC_NOPM, 0, 0, - &rx3_mix1_inp1_mux), - SND_SOC_DAPM_MUX("RX3 MIX1 INP2", SND_SOC_NOPM, 0, 0, - &rx3_mix1_inp2_mux), - SND_SOC_DAPM_MUX("RX3 MIX1 INP3", SND_SOC_NOPM, 0, 0, - &rx3_mix1_inp3_mux), - - SND_SOC_DAPM_MUX("RX1 MIX2 INP1", SND_SOC_NOPM, 0, 0, - &rx1_mix2_inp1_mux), - SND_SOC_DAPM_MUX("RX2 MIX2 INP1", SND_SOC_NOPM, 0, 0, - &rx2_mix2_inp1_mux), - - SND_SOC_DAPM_SUPPLY_S("CDC_CONN", -2, MSM89XX_CDC_CORE_CLK_OTHR_CTL, - 2, 0, NULL, 0), - - SND_SOC_DAPM_MUX_E("DEC1 MUX", - MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 0, 0, - &dec1_mux, msm_dig_cdc_codec_enable_dec, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_MUX_E("DEC2 MUX", - MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 1, 0, - &dec2_mux, msm_dig_cdc_codec_enable_dec, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_MUX_E("DEC3 MUX", - MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 2, 0, - &dec3_mux, msm_dig_cdc_codec_enable_dec, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_MUX_E("DEC4 MUX", - MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 3, 0, - &dec4_mux, msm_dig_cdc_codec_enable_dec, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_MUX_E("DEC5 MUX", - MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 4, 0, - &decsva_mux, msm_dig_cdc_codec_enable_dec, - SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | - SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), - - /* Sidetone */ - SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux), - SND_SOC_DAPM_PGA_E("IIR1", MSM89XX_CDC_CORE_CLK_SD_CTL, 0, 0, NULL, 0, - msm_dig_cdc_codec_set_iir_gain, SND_SOC_DAPM_POST_PMU), - - SND_SOC_DAPM_MUX("IIR2 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir2_inp1_mux), - SND_SOC_DAPM_PGA_E("IIR2", MSM89XX_CDC_CORE_CLK_SD_CTL, 1, 0, NULL, 0, - msm_dig_cdc_codec_set_iir_gain, SND_SOC_DAPM_POST_PMU), - - SND_SOC_DAPM_SUPPLY("RX_I2S_CLK", - MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 4, 0, NULL, 0), - SND_SOC_DAPM_SUPPLY("TX_I2S_CLK", - MSM89XX_CDC_CORE_CLK_TX_I2S_CTL, 4, 0, NULL, 0), - - /* Digital Mic Inputs */ - SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, - msm_dig_cdc_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0, - msm_dig_cdc_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0, - msm_dig_cdc_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0, - msm_dig_cdc_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | - SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_INPUT("ADC1_IN"), - SND_SOC_DAPM_INPUT("ADC2_IN"), - SND_SOC_DAPM_INPUT("ADC3_IN"), - SND_SOC_DAPM_OUTPUT("PDM_OUT_RX1"), - SND_SOC_DAPM_OUTPUT("PDM_OUT_RX2"), - SND_SOC_DAPM_OUTPUT("PDM_OUT_RX3"), -}; - -static const struct soc_enum cf_dec1_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX1_MUX_CTL, 4, 3, cf_text); - -static const struct soc_enum cf_dec2_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX2_MUX_CTL, 4, 3, cf_text); - -static const struct soc_enum cf_dec3_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX3_MUX_CTL, 4, 3, cf_text); - -static const struct soc_enum cf_dec4_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX4_MUX_CTL, 4, 3, cf_text); - -static const struct soc_enum cf_decsva_enum = - SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX5_MUX_CTL, 4, 3, cf_text); - -static const struct snd_kcontrol_new msm_dig_snd_controls[] = { - SOC_SINGLE_SX_TLV("DEC1 Volume", - MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN, - 0, -84, 40, digital_gain), - SOC_SINGLE_SX_TLV("DEC2 Volume", - MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN, - 0, -84, 40, digital_gain), - SOC_SINGLE_SX_TLV("DEC3 Volume", - MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN, - 0, -84, 40, digital_gain), - SOC_SINGLE_SX_TLV("DEC4 Volume", - MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN, - 0, -84, 40, digital_gain), - SOC_SINGLE_SX_TLV("DEC5 Volume", - MSM89XX_CDC_CORE_TX5_VOL_CTL_GAIN, - 0, -84, 40, digital_gain), - - SOC_SINGLE_SX_TLV("IIR1 INP1 Volume", - MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL, - 0, -84, 40, digital_gain), - SOC_SINGLE_SX_TLV("IIR1 INP2 Volume", - MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL, - 0, -84, 40, digital_gain), - SOC_SINGLE_SX_TLV("IIR1 INP3 Volume", - MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL, - 0, -84, 40, digital_gain), - SOC_SINGLE_SX_TLV("IIR1 INP4 Volume", - MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL, - 0, -84, 40, digital_gain), - SOC_SINGLE_SX_TLV("IIR2 INP1 Volume", - MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL, - 0, -84, 40, digital_gain), - - SOC_SINGLE_SX_TLV("RX1 Digital Volume", - MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL, - 0, -84, 40, digital_gain), - SOC_SINGLE_SX_TLV("RX2 Digital Volume", - MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL, - 0, -84, 40, digital_gain), - SOC_SINGLE_SX_TLV("RX3 Digital Volume", - MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL, - 0, -84, 40, digital_gain), - - SOC_SINGLE_EXT("IIR1 Enable Band1", IIR1, BAND1, 1, 0, - msm_dig_cdc_get_iir_enable_audio_mixer, - msm_dig_cdc_put_iir_enable_audio_mixer), - SOC_SINGLE_EXT("IIR1 Enable Band2", IIR1, BAND2, 1, 0, - msm_dig_cdc_get_iir_enable_audio_mixer, - msm_dig_cdc_put_iir_enable_audio_mixer), - SOC_SINGLE_EXT("IIR1 Enable Band3", IIR1, BAND3, 1, 0, - msm_dig_cdc_get_iir_enable_audio_mixer, - msm_dig_cdc_put_iir_enable_audio_mixer), - SOC_SINGLE_EXT("IIR1 Enable Band4", IIR1, BAND4, 1, 0, - msm_dig_cdc_get_iir_enable_audio_mixer, - msm_dig_cdc_put_iir_enable_audio_mixer), - SOC_SINGLE_EXT("IIR1 Enable Band5", IIR1, BAND5, 1, 0, - msm_dig_cdc_get_iir_enable_audio_mixer, - msm_dig_cdc_put_iir_enable_audio_mixer), - - SOC_SINGLE_EXT("IIR2 Enable Band1", IIR2, BAND1, 1, 0, - msm_dig_cdc_get_iir_enable_audio_mixer, - msm_dig_cdc_put_iir_enable_audio_mixer), - SOC_SINGLE_EXT("IIR2 Enable Band2", IIR2, BAND2, 1, 0, - msm_dig_cdc_get_iir_enable_audio_mixer, - msm_dig_cdc_put_iir_enable_audio_mixer), - SOC_SINGLE_EXT("IIR2 Enable Band3", IIR2, BAND3, 1, 0, - msm_dig_cdc_get_iir_enable_audio_mixer, - msm_dig_cdc_put_iir_enable_audio_mixer), - SOC_SINGLE_EXT("IIR2 Enable Band4", IIR2, BAND4, 1, 0, - msm_dig_cdc_get_iir_enable_audio_mixer, - msm_dig_cdc_put_iir_enable_audio_mixer), - SOC_SINGLE_EXT("IIR2 Enable Band5", IIR2, BAND5, 1, 0, - msm_dig_cdc_get_iir_enable_audio_mixer, - msm_dig_cdc_put_iir_enable_audio_mixer), - - SOC_SINGLE_MULTI_EXT("IIR1 Band1", IIR1, BAND1, 255, 0, 5, - msm_dig_cdc_get_iir_band_audio_mixer, - msm_dig_cdc_put_iir_band_audio_mixer), - SOC_SINGLE_MULTI_EXT("IIR1 Band2", IIR1, BAND2, 255, 0, 5, - msm_dig_cdc_get_iir_band_audio_mixer, - msm_dig_cdc_put_iir_band_audio_mixer), - SOC_SINGLE_MULTI_EXT("IIR1 Band3", IIR1, BAND3, 255, 0, 5, - msm_dig_cdc_get_iir_band_audio_mixer, - msm_dig_cdc_put_iir_band_audio_mixer), - SOC_SINGLE_MULTI_EXT("IIR1 Band4", IIR1, BAND4, 255, 0, 5, - msm_dig_cdc_get_iir_band_audio_mixer, - msm_dig_cdc_put_iir_band_audio_mixer), - SOC_SINGLE_MULTI_EXT("IIR1 Band5", IIR1, BAND5, 255, 0, 5, - msm_dig_cdc_get_iir_band_audio_mixer, - msm_dig_cdc_put_iir_band_audio_mixer), - - SOC_SINGLE_MULTI_EXT("IIR2 Band1", IIR2, BAND1, 255, 0, 5, - msm_dig_cdc_get_iir_band_audio_mixer, - msm_dig_cdc_put_iir_band_audio_mixer), - SOC_SINGLE_MULTI_EXT("IIR2 Band2", IIR2, BAND2, 255, 0, 5, - msm_dig_cdc_get_iir_band_audio_mixer, - msm_dig_cdc_put_iir_band_audio_mixer), - SOC_SINGLE_MULTI_EXT("IIR2 Band3", IIR2, BAND3, 255, 0, 5, - msm_dig_cdc_get_iir_band_audio_mixer, - msm_dig_cdc_put_iir_band_audio_mixer), - SOC_SINGLE_MULTI_EXT("IIR2 Band4", IIR2, BAND4, 255, 0, 5, - msm_dig_cdc_get_iir_band_audio_mixer, - msm_dig_cdc_put_iir_band_audio_mixer), - SOC_SINGLE_MULTI_EXT("IIR2 Band5", IIR2, BAND5, 255, 0, 5, - msm_dig_cdc_get_iir_band_audio_mixer, - msm_dig_cdc_put_iir_band_audio_mixer), - - SOC_SINGLE("RX1 HPF Switch", - MSM89XX_CDC_CORE_RX1_B5_CTL, 2, 1, 0), - SOC_SINGLE("RX2 HPF Switch", - MSM89XX_CDC_CORE_RX2_B5_CTL, 2, 1, 0), - SOC_SINGLE("RX3 HPF Switch", - MSM89XX_CDC_CORE_RX3_B5_CTL, 2, 1, 0), - - SOC_ENUM("RX1 HPF cut off", cf_rxmix1_enum), - SOC_ENUM("RX2 HPF cut off", cf_rxmix2_enum), - SOC_ENUM("RX3 HPF cut off", cf_rxmix3_enum), - - SOC_ENUM("TX1 HPF cut off", cf_dec1_enum), - SOC_ENUM("TX2 HPF cut off", cf_dec2_enum), - SOC_ENUM("TX3 HPF cut off", cf_dec3_enum), - SOC_ENUM("TX4 HPF cut off", cf_dec4_enum), - SOC_ENUM("TX5 HPF cut off", cf_decsva_enum), - SOC_SINGLE("TX1 HPF Switch", - MSM89XX_CDC_CORE_TX1_MUX_CTL, 3, 1, 0), - SOC_SINGLE("TX2 HPF Switch", - MSM89XX_CDC_CORE_TX2_MUX_CTL, 3, 1, 0), - SOC_SINGLE("TX3 HPF Switch", - MSM89XX_CDC_CORE_TX3_MUX_CTL, 3, 1, 0), - SOC_SINGLE("TX4 HPF Switch", - MSM89XX_CDC_CORE_TX4_MUX_CTL, 3, 1, 0), - SOC_SINGLE("TX5 HPF Switch", - MSM89XX_CDC_CORE_TX5_MUX_CTL, 3, 1, 0), -}; - -static int msm_dig_cdc_digital_mute(struct snd_soc_dai *dai, int mute) -{ - struct snd_soc_codec *codec = NULL; - u16 tx_vol_ctl_reg = 0; - u8 decimator = 0, i; - struct msm_dig_priv *dig_cdc; - - pr_debug("%s: Digital Mute val = %d\n", __func__, mute); - - if (!dai || !dai->codec) { - pr_err("%s: Invalid params\n", __func__); - return -EINVAL; - } - codec = dai->codec; - dig_cdc = snd_soc_codec_get_drvdata(codec); - - if (dai->id == AIF1_PB) { - dev_dbg(codec->dev, "%s: Not capture use case skip\n", - __func__); - return 0; - } - - mute = (mute) ? 1 : 0; - if (!mute) { - /* - * 15 ms is an emperical value for the mute time - * that was arrived by checking the pop level - * to be inaudible - */ - usleep_range(15000, 15010); - } - - if (dai->id == AIF3_SVA) { - snd_soc_update_bits(codec, - MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG, 0x01, mute); - goto ret; - } - for (i = 0; i < (NUM_DECIMATORS - 1); i++) { - if (dig_cdc->dec_active[i]) - decimator = i + 1; - if (decimator && decimator < NUM_DECIMATORS) { - /* mute/unmute decimators corresponding to Tx DAI's */ - tx_vol_ctl_reg = - MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG + - 32 * (decimator - 1); - snd_soc_update_bits(codec, tx_vol_ctl_reg, - 0x01, mute); - } - decimator = 0; - } -ret: - return 0; -} - -static struct snd_soc_dai_ops msm_dig_dai_ops = { - .hw_params = msm_dig_cdc_hw_params, - .digital_mute = msm_dig_cdc_digital_mute, -}; - - -static struct snd_soc_dai_driver msm_codec_dais[] = { - { - .name = "msm_dig_cdc_dai_rx1", - .id = AIF1_PB, - .playback = { /* Support maximum range */ - .stream_name = "AIF1 Playback", - .channels_min = 1, - .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_48000, - .formats = SNDRV_PCM_FMTBIT_S16_LE, - }, - .ops = &msm_dig_dai_ops, - }, - { - .name = "msm_dig_cdc_dai_tx1", - .id = AIF1_CAP, - .capture = { /* Support maximum range */ - .stream_name = "AIF1 Capture", - .channels_min = 1, - .channels_max = 4, - .rates = SNDRV_PCM_RATE_8000_48000, - .formats = SNDRV_PCM_FMTBIT_S16_LE, - }, - .ops = &msm_dig_dai_ops, - }, - { - .name = "msm_dig_cdc_dai_tx2", - .id = AIF3_SVA, - .capture = { /* Support maximum range */ - .stream_name = "AIF2 Capture", - .channels_min = 1, - .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_48000, - .formats = SNDRV_PCM_FMTBIT_S16_LE, - }, - .ops = &msm_dig_dai_ops, - }, - { - .name = "msm_dig_cdc_dai_vifeed", - .id = AIF2_VIFEED, - .capture = { /* Support maximum range */ - .stream_name = "AIF2 Capture", - .channels_min = 1, - .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_48000, - .formats = SNDRV_PCM_FMTBIT_S16_LE, - }, - .ops = &msm_dig_dai_ops, - }, -}; - -static struct regmap *msm_digital_get_regmap(struct device *dev) -{ - struct msm_dig *msm_dig_cdc = dev_get_drvdata(dev); - - return msm_dig_cdc->regmap; -} - -static struct snd_soc_codec_driver soc_msm_dig_codec = { - .probe = msm_dig_cdc_soc_probe, - .remove = msm_dig_cdc_soc_remove, - .controls = msm_dig_snd_controls, - .num_controls = ARRAY_SIZE(msm_dig_snd_controls), - .dapm_widgets = msm_dig_dapm_widgets, - .num_dapm_widgets = ARRAY_SIZE(msm_dig_dapm_widgets), - .dapm_routes = audio_dig_map, - .num_dapm_routes = ARRAY_SIZE(audio_dig_map), - .get_regmap = msm_digital_get_regmap, -}; - -const struct regmap_config msm_digital_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .lock = enable_digital_callback, - .unlock = disable_digital_callback, - .cache_type = REGCACHE_FLAT, - .reg_defaults = msm89xx_cdc_core_defaults, - .num_reg_defaults = MSM89XX_CDC_CORE_MAX_REGISTER, - .readable_reg = msm89xx_cdc_core_readable_reg, - .volatile_reg = msm89xx_cdc_core_volatile_reg, - .reg_format_endian = REGMAP_ENDIAN_NATIVE, - .val_format_endian = REGMAP_ENDIAN_NATIVE, - .max_register = MSM89XX_CDC_CORE_MAX_REGISTER, -}; - -static int msm_dig_cdc_probe(struct platform_device *pdev) -{ - int ret; - u32 dig_cdc_addr; - struct msm_dig *msm_dig_cdc; - struct dig_ctrl_platform_data *pdata; - - msm_dig_cdc = devm_kzalloc(&pdev->dev, sizeof(struct msm_dig), - GFP_KERNEL); - if (!msm_dig_cdc) - return -ENOMEM; - pdata = dev_get_platdata(&pdev->dev); - if (!pdata) { - dev_err(&pdev->dev, "%s: pdata from parent is NULL\n", - __func__); - ret = -EINVAL; - goto rtn; - } - dev_set_drvdata(&pdev->dev, msm_dig_cdc); - - ret = of_property_read_u32(pdev->dev.of_node, "reg", - &dig_cdc_addr); - if (ret) { - dev_err(&pdev->dev, "%s: could not find %s entry in dt\n", - __func__, "reg"); - return ret; - } - - msm_dig_cdc->dig_base = ioremap(dig_cdc_addr, - MSM89XX_CDC_CORE_MAX_REGISTER); - if (msm_dig_cdc->dig_base == NULL) { - dev_err(&pdev->dev, "%s ioremap failed\n", __func__); - return -ENOMEM; - } - msm_dig_cdc->regmap = - devm_regmap_init_mmio_clk(&pdev->dev, NULL, - msm_dig_cdc->dig_base, &msm_digital_regmap_config); - - msm_dig_cdc->update_clkdiv = pdata->update_clkdiv; - msm_dig_cdc->get_cdc_version = pdata->get_cdc_version; - msm_dig_cdc->handle = pdata->handle; - msm_dig_cdc->register_notifier = pdata->register_notifier; - - snd_soc_register_codec(&pdev->dev, &soc_msm_dig_codec, - msm_codec_dais, ARRAY_SIZE(msm_codec_dais)); - dev_dbg(&pdev->dev, "%s: registered DIG CODEC 0x%x\n", - __func__, dig_cdc_addr); -rtn: - return ret; -} - -static int msm_dig_cdc_remove(struct platform_device *pdev) -{ - snd_soc_unregister_codec(&pdev->dev); - return 0; -} - -static const struct of_device_id msm_dig_cdc_of_match[] = { - {.compatible = "qcom,msm-digital-codec"}, - {}, -}; - -static struct platform_driver msm_digcodec_driver = { - .driver = { - .owner = THIS_MODULE, - .name = DRV_NAME, - .of_match_table = msm_dig_cdc_of_match, - }, - .probe = msm_dig_cdc_probe, - .remove = msm_dig_cdc_remove, -}; -module_platform_driver(msm_digcodec_driver); - -MODULE_DESCRIPTION("MSM Audio Digital codec driver"); -MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/codecs/msmfalcon_cdc/msm-digital-cdc.h b/sound/soc/codecs/msmfalcon_cdc/msm-digital-cdc.h deleted file mode 100644 index 4cb82cd421b0..000000000000 --- a/sound/soc/codecs/msmfalcon_cdc/msm-digital-cdc.h +++ /dev/null @@ -1,93 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef MSM_DIGITAL_CDC_H -#define MSM_DIGITAL_CDC_H - -#define HPHL_PA_DISABLE (0x01 << 1) -#define HPHR_PA_DISABLE (0x01 << 2) -#define SPKR_PA_DISABLE (0x01 << 3) - -#define NUM_DECIMATORS 5 -/* Codec supports 1 compander */ -enum { - COMPANDER_NONE = 0, - COMPANDER_1, /* HPHL/R */ - COMPANDER_MAX, -}; - -/* Number of output I2S port */ -enum { - MSM89XX_RX1 = 0, - MSM89XX_RX2, - MSM89XX_RX3, - MSM89XX_RX_MAX, -}; - -struct msm_dig_priv { - struct snd_soc_codec *codec; - u32 comp_enabled[MSM89XX_RX_MAX]; - int (*codec_hph_comp_gpio)(bool enable, struct snd_soc_codec *codec); - s32 dmic_1_2_clk_cnt; - s32 dmic_3_4_clk_cnt; - bool dec_active[NUM_DECIMATORS]; - int version; - /* Entry for version info */ - struct snd_info_entry *entry; - struct snd_info_entry *version_entry; -}; - -struct msm_dig { - char __iomem *dig_base; - struct regmap *regmap; - struct notifier_block nblock; - u32 mute_mask; - void *handle; - void (*update_clkdiv)(void *handle, int val); - int (*get_cdc_version)(void *handle); - int (*register_notifier)(void *handle, - struct notifier_block *nblock, - bool enable); -}; - -struct dig_ctrl_platform_data { - void *handle; - void (*update_clkdiv)(void *handle, int val); - int (*get_cdc_version)(void *handle); - int (*register_notifier)(void *handle, - struct notifier_block *nblock, - bool enable); -}; - -struct hpf_work { - struct msm_dig_priv *dig_cdc; - u32 decimator; - u8 tx_hpf_cut_of_freq; - struct delayed_work dwork; -}; - -/* Codec supports 5 bands */ -enum { - BAND1 = 0, - BAND2, - BAND3, - BAND4, - BAND5, - BAND_MAX, -}; - -extern void msm_dig_cdc_hph_comp_cb( - int (*codec_hph_comp_gpio)( - bool enable, struct snd_soc_codec *codec), - struct snd_soc_codec *codec); -int msm_dig_codec_info_create_codec_entry(struct snd_info_entry *codec_root, - struct snd_soc_codec *codec); -#endif diff --git a/sound/soc/codecs/msmfalcon_cdc/msmfalcon-cdc-irq.c b/sound/soc/codecs/msmfalcon_cdc/msmfalcon-cdc-irq.c deleted file mode 100644 index 5ba2dac1ec20..000000000000 --- a/sound/soc/codecs/msmfalcon_cdc/msmfalcon-cdc-irq.c +++ /dev/null @@ -1,441 +0,0 @@ -/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "msm-analog-cdc.h" -#include "msmfalcon-cdc-irq.h" -#include "msmfalcon-cdc-registers.h" - -#define MAX_NUM_IRQS 14 -#define NUM_IRQ_REGS 2 -#define WCD9XXX_SYSTEM_RESUME_TIMEOUT_MS 700 - -#define BYTE_BIT_MASK(nr) (1UL << ((nr) % BITS_PER_BYTE)) -#define BIT_BYTE(nr) ((nr) / BITS_PER_BYTE) - -static irqreturn_t wcd9xxx_spmi_irq_handler(int linux_irq, void *data); - -char *irq_names[MAX_NUM_IRQS] = { - "spk_cnp_int", - "spk_clip_int", - "spk_ocp_int", - "ins_rem_det1", - "but_rel_det", - "but_press_det", - "ins_rem_det", - "mbhc_int", - "ear_ocp_int", - "hphr_ocp_int", - "hphl_ocp_det", - "ear_cnp_int", - "hphr_cnp_int", - "hphl_cnp_int" -}; - -int order[MAX_NUM_IRQS] = { - MSM89XX_IRQ_SPKR_CNP, - MSM89XX_IRQ_SPKR_CLIP, - MSM89XX_IRQ_SPKR_OCP, - MSM89XX_IRQ_MBHC_INSREM_DET1, - MSM89XX_IRQ_MBHC_RELEASE, - MSM89XX_IRQ_MBHC_PRESS, - MSM89XX_IRQ_MBHC_INSREM_DET, - MSM89XX_IRQ_MBHC_HS_DET, - MSM89XX_IRQ_EAR_OCP, - MSM89XX_IRQ_HPHR_OCP, - MSM89XX_IRQ_HPHL_OCP, - MSM89XX_IRQ_EAR_CNP, - MSM89XX_IRQ_HPHR_CNP, - MSM89XX_IRQ_HPHL_CNP, -}; - -enum wcd9xxx_spmi_pm_state { - WCD9XXX_PM_SLEEPABLE, - WCD9XXX_PM_AWAKE, - WCD9XXX_PM_ASLEEP, -}; - -struct wcd9xxx_spmi_map { - uint8_t handled[NUM_IRQ_REGS]; - uint8_t mask[NUM_IRQ_REGS]; - int linuxirq[MAX_NUM_IRQS]; - irq_handler_t handler[MAX_NUM_IRQS]; - struct spmi_device *spmi[NUM_IRQ_REGS]; - struct snd_soc_codec *codec; - - enum wcd9xxx_spmi_pm_state pm_state; - struct mutex pm_lock; - /* pm_wq notifies change of pm_state */ - wait_queue_head_t pm_wq; - struct pm_qos_request pm_qos_req; - int wlock_holders; -}; - -struct wcd9xxx_spmi_map map; - -void wcd9xxx_spmi_enable_irq(int irq) -{ - pr_debug("%s: irqno =%d\n", __func__, irq); - if ((irq >= 0) && (irq <= 7)) { - snd_soc_update_bits(map.codec, - MSM89XX_PMIC_DIGITAL_INT_EN_CLR, - (0x01 << irq), 0x00); - snd_soc_update_bits(map.codec, - MSM89XX_PMIC_DIGITAL_INT_EN_SET, - (0x01 << irq), (0x01 << irq)); - } - if ((irq > 7) && (irq <= 15)) { - snd_soc_update_bits(map.codec, - MSM89XX_PMIC_ANALOG_INT_EN_CLR, - (0x01 << (irq - 8)), 0x00); - snd_soc_update_bits(map.codec, - MSM89XX_PMIC_ANALOG_INT_EN_SET, - (0x01 << (irq - 8)), (0x01 << (irq - 8))); - } - - if (!(map.mask[BIT_BYTE(irq)] & (BYTE_BIT_MASK(irq)))) - return; - - map.mask[BIT_BYTE(irq)] &= - ~(BYTE_BIT_MASK(irq)); - - enable_irq(map.linuxirq[irq]); -} - -void wcd9xxx_spmi_disable_irq(int irq) -{ - pr_debug("%s: irqno =%d\n", __func__, irq); - if ((irq >= 0) && (irq <= 7)) { - snd_soc_update_bits(map.codec, - MSM89XX_PMIC_DIGITAL_INT_EN_SET, - (0x01 << (irq)), 0x00); - snd_soc_update_bits(map.codec, - MSM89XX_PMIC_DIGITAL_INT_EN_CLR, - (0x01 << irq), (0x01 << irq)); - } - - if ((irq > 7) && (irq <= 15)) { - snd_soc_update_bits(map.codec, - MSM89XX_PMIC_ANALOG_INT_EN_SET, - (0x01 << (irq - 8)), 0x00); - snd_soc_update_bits(map.codec, - MSM89XX_PMIC_ANALOG_INT_EN_CLR, - (0x01 << (irq - 8)), (0x01 << (irq - 8))); - } - - if (map.mask[BIT_BYTE(irq)] & (BYTE_BIT_MASK(irq))) - return; - - map.mask[BIT_BYTE(irq)] |= - (BYTE_BIT_MASK(irq)); - - disable_irq_nosync(map.linuxirq[irq]); -} - -int wcd9xxx_spmi_request_irq(int irq, irq_handler_t handler, - const char *name, void *priv) -{ - int rc; - unsigned long irq_flags; - - if (strcmp(name, "mbhc sw intr")) - irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | - IRQF_ONESHOT; - else - irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | - IRQF_ONESHOT | IRQF_NO_SUSPEND; - pr_debug("%s: name:%s irq_flags = %lx\n", __func__, name, irq_flags); - - rc = devm_request_threaded_irq(&map.spmi[BIT_BYTE(irq)]->dev, - map.linuxirq[irq], NULL, - wcd9xxx_spmi_irq_handler, - irq_flags, - name, priv); - if (rc < 0) { - dev_err(&map.spmi[BIT_BYTE(irq)]->dev, - "Can't request %d IRQ\n", irq); - return rc; - } - - dev_dbg(&map.spmi[BIT_BYTE(irq)]->dev, - "irq %d linuxIRQ: %d\n", irq, map.linuxirq[irq]); - map.mask[BIT_BYTE(irq)] &= ~BYTE_BIT_MASK(irq); - map.handler[irq] = handler; - enable_irq_wake(map.linuxirq[irq]); - return 0; -} - -int wcd9xxx_spmi_free_irq(int irq, void *priv) -{ - devm_free_irq(&map.spmi[BIT_BYTE(irq)]->dev, map.linuxirq[irq], - priv); - map.mask[BIT_BYTE(irq)] |= BYTE_BIT_MASK(irq); - return 0; -} - -static int get_irq_bit(int linux_irq) -{ - int i = 0; - - for (; i < MAX_NUM_IRQS; i++) - if (map.linuxirq[i] == linux_irq) - return i; - - return i; -} - -static int get_order_irq(int i) -{ - return order[i]; -} - -static irqreturn_t wcd9xxx_spmi_irq_handler(int linux_irq, void *data) -{ - int irq, i, j; - unsigned long status[NUM_IRQ_REGS] = {0}; - - if (unlikely(wcd9xxx_spmi_lock_sleep() == false)) { - pr_err("Failed to hold suspend\n"); - return IRQ_NONE; - } - - irq = get_irq_bit(linux_irq); - if (irq == MAX_NUM_IRQS) - return IRQ_HANDLED; - - status[BIT_BYTE(irq)] |= BYTE_BIT_MASK(irq); - for (i = 0; i < NUM_IRQ_REGS; i++) { - status[i] |= snd_soc_read(map.codec, - BIT_BYTE(irq) * 0x100 + - MSM89XX_PMIC_DIGITAL_INT_LATCHED_STS); - status[i] &= ~map.mask[i]; - } - for (i = 0; i < MAX_NUM_IRQS; i++) { - j = get_order_irq(i); - if ((status[BIT_BYTE(j)] & BYTE_BIT_MASK(j)) && - ((map.handled[BIT_BYTE(j)] & - BYTE_BIT_MASK(j)) == 0)) { - map.handler[j](irq, data); - map.handled[BIT_BYTE(j)] |= - BYTE_BIT_MASK(j); - } - } - map.handled[BIT_BYTE(irq)] &= ~BYTE_BIT_MASK(irq); - wcd9xxx_spmi_unlock_sleep(); - - return IRQ_HANDLED; -} - -enum wcd9xxx_spmi_pm_state wcd9xxx_spmi_pm_cmpxchg( - enum wcd9xxx_spmi_pm_state o, - enum wcd9xxx_spmi_pm_state n) -{ - enum wcd9xxx_spmi_pm_state old; - - mutex_lock(&map.pm_lock); - old = map.pm_state; - if (old == o) - map.pm_state = n; - pr_debug("%s: map.pm_state = %d\n", __func__, map.pm_state); - mutex_unlock(&map.pm_lock); - return old; -} -EXPORT_SYMBOL(wcd9xxx_spmi_pm_cmpxchg); - -int wcd9xxx_spmi_suspend(pm_message_t pmesg) -{ - int ret = 0; - - pr_debug("%s: enter\n", __func__); - /* - * pm_qos_update_request() can be called after this suspend chain call - * started. thus suspend can be called while lock is being held - */ - mutex_lock(&map.pm_lock); - if (map.pm_state == WCD9XXX_PM_SLEEPABLE) { - pr_debug("%s: suspending system, state %d, wlock %d\n", - __func__, map.pm_state, - map.wlock_holders); - map.pm_state = WCD9XXX_PM_ASLEEP; - } else if (map.pm_state == WCD9XXX_PM_AWAKE) { - /* - * unlock to wait for pm_state == WCD9XXX_PM_SLEEPABLE - * then set to WCD9XXX_PM_ASLEEP - */ - pr_debug("%s: waiting to suspend system, state %d, wlock %d\n", - __func__, map.pm_state, - map.wlock_holders); - mutex_unlock(&map.pm_lock); - if (!(wait_event_timeout(map.pm_wq, - wcd9xxx_spmi_pm_cmpxchg( - WCD9XXX_PM_SLEEPABLE, - WCD9XXX_PM_ASLEEP) == - WCD9XXX_PM_SLEEPABLE, - HZ))) { - pr_debug("%s: suspend failed state %d, wlock %d\n", - __func__, map.pm_state, - map.wlock_holders); - ret = -EBUSY; - } else { - pr_debug("%s: done, state %d, wlock %d\n", __func__, - map.pm_state, - map.wlock_holders); - } - mutex_lock(&map.pm_lock); - } else if (map.pm_state == WCD9XXX_PM_ASLEEP) { - pr_warn("%s: system is already suspended, state %d, wlock %dn", - __func__, map.pm_state, - map.wlock_holders); - } - mutex_unlock(&map.pm_lock); - - return ret; -} -EXPORT_SYMBOL(wcd9xxx_spmi_suspend); - -int wcd9xxx_spmi_resume(void) -{ - int ret = 0; - - pr_debug("%s: enter\n", __func__); - mutex_lock(&map.pm_lock); - if (map.pm_state == WCD9XXX_PM_ASLEEP) { - pr_debug("%s: resuming system, state %d, wlock %d\n", __func__, - map.pm_state, - map.wlock_holders); - map.pm_state = WCD9XXX_PM_SLEEPABLE; - } else { - pr_warn("%s: system is already awake, state %d wlock %d\n", - __func__, map.pm_state, - map.wlock_holders); - } - mutex_unlock(&map.pm_lock); - wake_up_all(&map.pm_wq); - - return ret; -} -EXPORT_SYMBOL(wcd9xxx_spmi_resume); - -bool wcd9xxx_spmi_lock_sleep(void) -{ - /* - * wcd9xxx_spmi_{lock/unlock}_sleep will be called by - * wcd9xxx_spmi_irq_thread - * and its subroutines only motly. - * but btn0_lpress_fn is not wcd9xxx_spmi_irq_thread's subroutine and - * It can race with wcd9xxx_spmi_irq_thread. - * So need to embrace wlock_holders with mutex. - */ - mutex_lock(&map.pm_lock); - if (map.wlock_holders++ == 0) { - pr_debug("%s: holding wake lock\n", __func__); - pm_qos_update_request(&map.pm_qos_req, - msm_cpuidle_get_deep_idle_latency()); - pm_stay_awake(&map.spmi[0]->dev); - } - mutex_unlock(&map.pm_lock); - pr_debug("%s: wake lock counter %d\n", __func__, - map.wlock_holders); - pr_debug("%s: map.pm_state = %d\n", __func__, map.pm_state); - - if (!wait_event_timeout(map.pm_wq, - ((wcd9xxx_spmi_pm_cmpxchg( - WCD9XXX_PM_SLEEPABLE, - WCD9XXX_PM_AWAKE)) == - WCD9XXX_PM_SLEEPABLE || - (wcd9xxx_spmi_pm_cmpxchg( - WCD9XXX_PM_SLEEPABLE, - WCD9XXX_PM_AWAKE) == - WCD9XXX_PM_AWAKE)), - msecs_to_jiffies( - WCD9XXX_SYSTEM_RESUME_TIMEOUT_MS))) { - pr_warn("%s: system didn't resume within %dms, s %d, w %d\n", - __func__, - WCD9XXX_SYSTEM_RESUME_TIMEOUT_MS, map.pm_state, - map.wlock_holders); - wcd9xxx_spmi_unlock_sleep(); - return false; - } - wake_up_all(&map.pm_wq); - pr_debug("%s: leaving pm_state = %d\n", __func__, map.pm_state); - return true; -} -EXPORT_SYMBOL(wcd9xxx_spmi_lock_sleep); - -void wcd9xxx_spmi_unlock_sleep(void) -{ - mutex_lock(&map.pm_lock); - if (--map.wlock_holders == 0) { - pr_debug("%s: releasing wake lock pm_state %d -> %d\n", - __func__, map.pm_state, WCD9XXX_PM_SLEEPABLE); - /* - * if wcd9xxx_spmi_lock_sleep failed, pm_state would be still - * WCD9XXX_PM_ASLEEP, don't overwrite - */ - if (likely(map.pm_state == WCD9XXX_PM_AWAKE)) - map.pm_state = WCD9XXX_PM_SLEEPABLE; - pm_qos_update_request(&map.pm_qos_req, - PM_QOS_DEFAULT_VALUE); - pm_relax(&map.spmi[0]->dev); - } - mutex_unlock(&map.pm_lock); - pr_debug("%s: wake lock counter %d\n", __func__, - map.wlock_holders); - pr_debug("%s: map.pm_state = %d\n", __func__, map.pm_state); - wake_up_all(&map.pm_wq); -} -EXPORT_SYMBOL(wcd9xxx_spmi_unlock_sleep); - -void wcd9xxx_spmi_set_codec(struct snd_soc_codec *codec) -{ - map.codec = codec; -} - -void wcd9xxx_spmi_set_dev(struct spmi_device *spmi, int i) -{ - if (i < NUM_IRQ_REGS) - map.spmi[i] = spmi; -} - -int wcd9xxx_spmi_irq_init(void) -{ - int i = 0; - - for (; i < MAX_NUM_IRQS; i++) - map.mask[BIT_BYTE(i)] |= BYTE_BIT_MASK(i); - mutex_init(&map.pm_lock); - map.wlock_holders = 0; - map.pm_state = WCD9XXX_PM_SLEEPABLE; - init_waitqueue_head(&map.pm_wq); - pm_qos_add_request(&map.pm_qos_req, - PM_QOS_CPU_DMA_LATENCY, - PM_QOS_DEFAULT_VALUE); - - return 0; -} - -MODULE_DESCRIPTION("MSM8x16 SPMI IRQ driver"); -MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/codecs/msmfalcon_cdc/msmfalcon-cdc-irq.h b/sound/soc/codecs/msmfalcon_cdc/msmfalcon-cdc-irq.h deleted file mode 100644 index 659e52cc2a5e..000000000000 --- a/sound/soc/codecs/msmfalcon_cdc/msmfalcon-cdc-irq.h +++ /dev/null @@ -1,34 +0,0 @@ -/* Copyright (c) 2015, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef __WCD9XXX_SPMI_IRQ_H__ -#define __WCD9XXX_SPMI_IRQ_H__ - -#include -#include -#include -#include -#include - -extern void wcd9xxx_spmi_enable_irq(int irq); -extern void wcd9xxx_spmi_disable_irq(int irq); -extern int wcd9xxx_spmi_request_irq(int irq, irq_handler_t handler, - const char *name, void *priv); -extern int wcd9xxx_spmi_free_irq(int irq, void *priv); -extern void wcd9xxx_spmi_set_codec(struct snd_soc_codec *codec); -extern void wcd9xxx_spmi_set_dev(struct spmi_device *spmi, int i); -extern int wcd9xxx_spmi_irq_init(void); -extern int wcd9xxx_spmi_suspend(pm_message_t); -extern int wcd9xxx_spmi_resume(void); -bool wcd9xxx_spmi_lock_sleep(void); -void wcd9xxx_spmi_unlock_sleep(void); - -#endif diff --git a/sound/soc/codecs/msmfalcon_cdc/msmfalcon-cdc-registers.h b/sound/soc/codecs/msmfalcon_cdc/msmfalcon-cdc-registers.h deleted file mode 100644 index 34c3d3333d6e..000000000000 --- a/sound/soc/codecs/msmfalcon_cdc/msmfalcon-cdc-registers.h +++ /dev/null @@ -1,603 +0,0 @@ - /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef MSMFALCON_WCD_REGISTERS_H -#define MSMFALCON_WCD_REGISTERS_H - -#define CDC_DIG_BASE 0xF000 -#define CDC_ANA_BASE 0xF100 - -#define MSM89XX_PMIC_DIGITAL_REVISION1 (CDC_DIG_BASE+0x000) -#define MSM89XX_PMIC_DIGITAL_REVISION1__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_REVISION2 (CDC_DIG_BASE+0x001) -#define MSM89XX_PMIC_DIGITAL_REVISION2__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_PERPH_TYPE (CDC_DIG_BASE+0x004) -#define MSM89XX_PMIC_DIGITAL_PERPH_TYPE__POR (0x23) -#define MSM89XX_PMIC_DIGITAL_PERPH_SUBTYPE (CDC_DIG_BASE+0x005) -#define MSM89XX_PMIC_DIGITAL_PERPH_SUBTYPE__POR (0x01) -#define MSM89XX_PMIC_DIGITAL_INT_RT_STS (CDC_DIG_BASE+0x010) -#define MSM89XX_PMIC_DIGITAL_INT_RT_STS__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_INT_SET_TYPE (CDC_DIG_BASE+0x011) -#define MSM89XX_PMIC_DIGITAL_INT_SET_TYPE__POR (0xFF) -#define MSM89XX_PMIC_DIGITAL_INT_POLARITY_HIGH (CDC_DIG_BASE+0x012) -#define MSM89XX_PMIC_DIGITAL_INT_POLARITY_HIGH__POR (0xFF) -#define MSM89XX_PMIC_DIGITAL_INT_POLARITY_LOW (CDC_DIG_BASE+0x013) -#define MSM89XX_PMIC_DIGITAL_INT_POLARITY_LOW__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_INT_LATCHED_CLR (CDC_DIG_BASE+0x014) -#define MSM89XX_PMIC_DIGITAL_INT_LATCHED_CLR__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_INT_EN_SET (CDC_DIG_BASE+0x015) -#define MSM89XX_PMIC_DIGITAL_INT_EN_SET__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_INT_EN_CLR (CDC_DIG_BASE+0x016) -#define MSM89XX_PMIC_DIGITAL_INT_EN_CLR__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_INT_LATCHED_STS (CDC_DIG_BASE+0x018) -#define MSM89XX_PMIC_DIGITAL_INT_LATCHED_STS__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_INT_PENDING_STS (CDC_DIG_BASE+0x019) -#define MSM89XX_PMIC_DIGITAL_INT_PENDING_STS__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_INT_MID_SEL (CDC_DIG_BASE+0x01A) -#define MSM89XX_PMIC_DIGITAL_INT_MID_SEL__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_INT_PRIORITY (CDC_DIG_BASE+0x01B) -#define MSM89XX_PMIC_DIGITAL_INT_PRIORITY__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_GPIO_MODE (CDC_DIG_BASE+0x040) -#define MSM89XX_PMIC_DIGITAL_GPIO_MODE__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_PIN_CTL_OE (CDC_DIG_BASE+0x041) -#define MSM89XX_PMIC_DIGITAL_PIN_CTL_OE__POR (0x01) -#define MSM89XX_PMIC_DIGITAL_PIN_CTL_DATA (CDC_DIG_BASE+0x042) -#define MSM89XX_PMIC_DIGITAL_PIN_CTL_DATA__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_PIN_STATUS (CDC_DIG_BASE+0x043) -#define MSM89XX_PMIC_DIGITAL_PIN_STATUS__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_HDRIVE_CTL (CDC_DIG_BASE+0x044) -#define MSM89XX_PMIC_DIGITAL_HDRIVE_CTL__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_CDC_RST_CTL (CDC_DIG_BASE+0x046) -#define MSM89XX_PMIC_DIGITAL_CDC_RST_CTL__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL (CDC_DIG_BASE+0x048) -#define MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL (CDC_DIG_BASE+0x049) -#define MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL (CDC_DIG_BASE+0x04A) -#define MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_CDC_CONN_TX1_CTL (CDC_DIG_BASE+0x050) -#define MSM89XX_PMIC_DIGITAL_CDC_CONN_TX1_CTL__POR (0x02) -#define MSM89XX_PMIC_DIGITAL_CDC_CONN_TX2_CTL (CDC_DIG_BASE+0x051) -#define MSM89XX_PMIC_DIGITAL_CDC_CONN_TX2_CTL__POR (0x02) -#define MSM89XX_PMIC_DIGITAL_CDC_CONN_HPHR_DAC_CTL (CDC_DIG_BASE+0x052) -#define MSM89XX_PMIC_DIGITAL_CDC_CONN_HPHR_DAC_CTL__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX1_CTL (CDC_DIG_BASE+0x053) -#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX1_CTL__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX2_CTL (CDC_DIG_BASE+0x054) -#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX2_CTL__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX3_CTL (CDC_DIG_BASE+0x055) -#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX3_CTL__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX_LB_CTL (CDC_DIG_BASE+0x056) -#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX_LB_CTL__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL1 (CDC_DIG_BASE+0x058) -#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL1__POR (0x7C) -#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL2 (CDC_DIG_BASE+0x059) -#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL2__POR (0x7C) -#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL3 (CDC_DIG_BASE+0x05A) -#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL3__POR (0x7C) -#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA0 (CDC_DIG_BASE+0x05B) -#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA0__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA1 (CDC_DIG_BASE+0x05C) -#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA1__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA2 (CDC_DIG_BASE+0x05D) -#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA2__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA3 (CDC_DIG_BASE+0x05E) -#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA3__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_DIG_DEBUG_CTL (CDC_DIG_BASE+0x068) -#define MSM89XX_PMIC_DIGITAL_DIG_DEBUG_CTL__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_DIG_DEBUG_EN (CDC_DIG_BASE+0x069) -#define MSM89XX_PMIC_DIGITAL_DIG_DEBUG_EN__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_SPARE_0 (CDC_DIG_BASE+0x070) -#define MSM89XX_PMIC_DIGITAL_SPARE_0__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_SPARE_1 (CDC_DIG_BASE+0x071) -#define MSM89XX_PMIC_DIGITAL_SPARE_1__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_SPARE_2 (CDC_DIG_BASE+0x072) -#define MSM89XX_PMIC_DIGITAL_SPARE_2__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_SEC_ACCESS (CDC_DIG_BASE+0x0D0) -#define MSM89XX_PMIC_DIGITAL_SEC_ACCESS__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL1 (CDC_DIG_BASE+0x0D8) -#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL1__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL2 (CDC_DIG_BASE+0x0D9) -#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL2__POR (0x01) -#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3 (CDC_DIG_BASE+0x0DA) -#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3__POR (0x05) -#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL4 (CDC_DIG_BASE+0x0DB) -#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL4__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_INT_TEST1 (CDC_DIG_BASE+0x0E0) -#define MSM89XX_PMIC_DIGITAL_INT_TEST1__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_INT_TEST_VAL (CDC_DIG_BASE+0x0E1) -#define MSM89XX_PMIC_DIGITAL_INT_TEST_VAL__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_TRIM_NUM (CDC_DIG_BASE+0x0F0) -#define MSM89XX_PMIC_DIGITAL_TRIM_NUM__POR (0x00) -#define MSM89XX_PMIC_DIGITAL_TRIM_CTRL (CDC_DIG_BASE+0x0F1) -#define MSM89XX_PMIC_DIGITAL_TRIM_CTRL__POR (0x00) - -#define MSM89XX_PMIC_ANALOG_REVISION1 (CDC_ANA_BASE+0x00) -#define MSM89XX_PMIC_ANALOG_REVISION1__POR (0x00) -#define MSM89XX_PMIC_ANALOG_REVISION2 (CDC_ANA_BASE+0x01) -#define MSM89XX_PMIC_ANALOG_REVISION2__POR (0x00) -#define MSM89XX_PMIC_ANALOG_REVISION3 (CDC_ANA_BASE+0x02) -#define MSM89XX_PMIC_ANALOG_REVISION3__POR (0x00) -#define MSM89XX_PMIC_ANALOG_REVISION4 (CDC_ANA_BASE+0x03) -#define MSM89XX_PMIC_ANALOG_REVISION4__POR (0x00) -#define MSM89XX_PMIC_ANALOG_PERPH_TYPE (CDC_ANA_BASE+0x04) -#define MSM89XX_PMIC_ANALOG_PERPH_TYPE__POR (0x23) -#define MSM89XX_PMIC_ANALOG_PERPH_SUBTYPE (CDC_ANA_BASE+0x05) -#define MSM89XX_PMIC_ANALOG_PERPH_SUBTYPE__POR (0x09) -#define MSM89XX_PMIC_ANALOG_INT_RT_STS (CDC_ANA_BASE+0x10) -#define MSM89XX_PMIC_ANALOG_INT_RT_STS__POR (0x00) -#define MSM89XX_PMIC_ANALOG_INT_SET_TYPE (CDC_ANA_BASE+0x11) -#define MSM89XX_PMIC_ANALOG_INT_SET_TYPE__POR (0x3F) -#define MSM89XX_PMIC_ANALOG_INT_POLARITY_HIGH (CDC_ANA_BASE+0x12) -#define MSM89XX_PMIC_ANALOG_INT_POLARITY_HIGH__POR (0x3F) -#define MSM89XX_PMIC_ANALOG_INT_POLARITY_LOW (CDC_ANA_BASE+0x13) -#define MSM89XX_PMIC_ANALOG_INT_POLARITY_LOW__POR (0x00) -#define MSM89XX_PMIC_ANALOG_INT_LATCHED_CLR (CDC_ANA_BASE+0x14) -#define MSM89XX_PMIC_ANALOG_INT_LATCHED_CLR__POR (0x00) -#define MSM89XX_PMIC_ANALOG_INT_EN_SET (CDC_ANA_BASE+0x15) -#define MSM89XX_PMIC_ANALOG_INT_EN_SET__POR (0x00) -#define MSM89XX_PMIC_ANALOG_INT_EN_CLR (CDC_ANA_BASE+0x16) -#define MSM89XX_PMIC_ANALOG_INT_EN_CLR__POR (0x00) -#define MSM89XX_PMIC_ANALOG_INT_LATCHED_STS (CDC_ANA_BASE+0x18) -#define MSM89XX_PMIC_ANALOG_INT_LATCHED_STS__POR (0x00) -#define MSM89XX_PMIC_ANALOG_INT_PENDING_STS (CDC_ANA_BASE+0x19) -#define MSM89XX_PMIC_ANALOG_INT_PENDING_STS__POR (0x00) -#define MSM89XX_PMIC_ANALOG_INT_MID_SEL (CDC_ANA_BASE+0x1A) -#define MSM89XX_PMIC_ANALOG_INT_MID_SEL__POR (0x00) -#define MSM89XX_PMIC_ANALOG_INT_PRIORITY (CDC_ANA_BASE+0x1B) -#define MSM89XX_PMIC_ANALOG_INT_PRIORITY__POR (0x00) -#define MSM89XX_PMIC_ANALOG_MICB_1_EN (CDC_ANA_BASE+0x40) -#define MSM89XX_PMIC_ANALOG_MICB_1_EN__POR (0x00) -#define MSM89XX_PMIC_ANALOG_MICB_1_VAL (CDC_ANA_BASE+0x41) -#define MSM89XX_PMIC_ANALOG_MICB_1_VAL__POR (0x20) -#define MSM89XX_PMIC_ANALOG_MICB_1_CTL (CDC_ANA_BASE+0x42) -#define MSM89XX_PMIC_ANALOG_MICB_1_CTL__POR (0x00) -#define MSM89XX_PMIC_ANALOG_MICB_1_INT_RBIAS (CDC_ANA_BASE+0x43) -#define MSM89XX_PMIC_ANALOG_MICB_1_INT_RBIAS__POR (0x49) -#define MSM89XX_PMIC_ANALOG_MICB_2_EN (CDC_ANA_BASE+0x44) -#define MSM89XX_PMIC_ANALOG_MICB_2_EN__POR (0x20) -#define MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2 (CDC_ANA_BASE+0x45) -#define MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2__POR (0x00) -#define MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL (CDC_ANA_BASE+0x46) -#define MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL__POR (0x00) -#define MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1 (CDC_ANA_BASE+0x47) -#define MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1__POR (0x35) -#define MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2 (CDC_ANA_BASE+0x50) -#define MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2__POR (0x08) -#define MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL (CDC_ANA_BASE+0x51) -#define MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL__POR (0x00) -#define MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER (CDC_ANA_BASE+0x52) -#define MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER__POR (0x98) -#define MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL (CDC_ANA_BASE+0x53) -#define MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL__POR (0x00) -#define MSM89XX_PMIC_ANALOG_MBHC_BTN1_ZDETM_CTL (CDC_ANA_BASE+0x54) -#define MSM89XX_PMIC_ANALOG_MBHC_BTN1_ZDETM_CTL__POR (0x20) -#define MSM89XX_PMIC_ANALOG_MBHC_BTN2_ZDETH_CTL (CDC_ANA_BASE+0x55) -#define MSM89XX_PMIC_ANALOG_MBHC_BTN2_ZDETH_CTL__POR (0x40) -#define MSM89XX_PMIC_ANALOG_MBHC_BTN3_CTL (CDC_ANA_BASE+0x56) -#define MSM89XX_PMIC_ANALOG_MBHC_BTN3_CTL__POR (0x61) -#define MSM89XX_PMIC_ANALOG_MBHC_BTN4_CTL (CDC_ANA_BASE+0x57) -#define MSM89XX_PMIC_ANALOG_MBHC_BTN4_CTL__POR (0x80) -#define MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT (CDC_ANA_BASE+0x58) -#define MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT__POR (0x00) -#define MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT (CDC_ANA_BASE+0x59) -#define MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT__POR (0x00) -#define MSM89XX_PMIC_ANALOG_TX_1_EN (CDC_ANA_BASE+0x60) -#define MSM89XX_PMIC_ANALOG_TX_1_EN__POR (0x03) -#define MSM89XX_PMIC_ANALOG_TX_2_EN (CDC_ANA_BASE+0x61) -#define MSM89XX_PMIC_ANALOG_TX_2_EN__POR (0x03) -#define MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_1 (CDC_ANA_BASE+0x62) -#define MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_1__POR (0xBF) -#define MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_2 (CDC_ANA_BASE+0x63) -#define MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_2__POR (0x8C) -#define MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL (CDC_ANA_BASE+0x64) -#define MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL__POR (0x00) -#define MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS (CDC_ANA_BASE+0x65) -#define MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS__POR (0x6B) -#define MSM89XX_PMIC_ANALOG_TX_1_2_TXFE_CLKDIV (CDC_ANA_BASE+0x66) -#define MSM89XX_PMIC_ANALOG_TX_1_2_TXFE_CLKDIV__POR (0x51) -#define MSM89XX_PMIC_ANALOG_TX_3_EN (CDC_ANA_BASE+0x67) -#define MSM89XX_PMIC_ANALOG_TX_3_EN__POR (0x02) -#define MSM89XX_PMIC_ANALOG_NCP_EN (CDC_ANA_BASE+0x80) -#define MSM89XX_PMIC_ANALOG_NCP_EN__POR (0x26) -#define MSM89XX_PMIC_ANALOG_NCP_CLK (CDC_ANA_BASE+0x81) -#define MSM89XX_PMIC_ANALOG_NCP_CLK__POR (0x23) -#define MSM89XX_PMIC_ANALOG_NCP_DEGLITCH (CDC_ANA_BASE+0x82) -#define MSM89XX_PMIC_ANALOG_NCP_DEGLITCH__POR (0x5B) -#define MSM89XX_PMIC_ANALOG_NCP_FBCTRL (CDC_ANA_BASE+0x83) -#define MSM89XX_PMIC_ANALOG_NCP_FBCTRL__POR (0x08) -#define MSM89XX_PMIC_ANALOG_NCP_BIAS (CDC_ANA_BASE+0x84) -#define MSM89XX_PMIC_ANALOG_NCP_BIAS__POR (0x29) -#define MSM89XX_PMIC_ANALOG_NCP_VCTRL (CDC_ANA_BASE+0x85) -#define MSM89XX_PMIC_ANALOG_NCP_VCTRL__POR (0x24) -#define MSM89XX_PMIC_ANALOG_NCP_TEST (CDC_ANA_BASE+0x86) -#define MSM89XX_PMIC_ANALOG_NCP_TEST__POR (0x00) -#define MSM89XX_PMIC_ANALOG_NCP_CLIM_ADDR (CDC_ANA_BASE+0x87) -#define MSM89XX_PMIC_ANALOG_NCP_CLIM_ADDR__POR (0xD5) -#define MSM89XX_PMIC_ANALOG_RX_CLOCK_DIVIDER (CDC_ANA_BASE+0x90) -#define MSM89XX_PMIC_ANALOG_RX_CLOCK_DIVIDER__POR (0xE8) -#define MSM89XX_PMIC_ANALOG_RX_COM_OCP_CTL (CDC_ANA_BASE+0x91) -#define MSM89XX_PMIC_ANALOG_RX_COM_OCP_CTL__POR (0xCF) -#define MSM89XX_PMIC_ANALOG_RX_COM_OCP_COUNT (CDC_ANA_BASE+0x92) -#define MSM89XX_PMIC_ANALOG_RX_COM_OCP_COUNT__POR (0x6E) -#define MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC (CDC_ANA_BASE+0x93) -#define MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC__POR (0x18) -#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_PA (CDC_ANA_BASE+0x94) -#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_PA__POR (0x5A) -#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_LDO_OCP (CDC_ANA_BASE+0x95) -#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_LDO_OCP__POR (0x69) -#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_CNP (CDC_ANA_BASE+0x96) -#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_CNP__POR (0x29) -#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN (CDC_ANA_BASE+0x97) -#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN__POR (0x80) -#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_CTL (CDC_ANA_BASE+0x98) -#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_CTL__POR (0xDA) -#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME (CDC_ANA_BASE+0x99) -#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME__POR (0x16) -#define MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST (CDC_ANA_BASE+0x9A) -#define MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST__POR (0x00) -#define MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL (CDC_ANA_BASE+0x9B) -#define MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL__POR (0x20) -#define MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST (CDC_ANA_BASE+0x9C) -#define MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST__POR (0x00) -#define MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL (CDC_ANA_BASE+0x9D) -#define MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL__POR (0x20) -#define MSM89XX_PMIC_ANALOG_RX_EAR_CTL (CDC_ANA_BASE+0x9E) -#define MSM89XX_PMIC_ANALOG_RX_EAR_CTL___POR (0x12) -#define MSM89XX_PMIC_ANALOG_RX_ATEST (CDC_ANA_BASE+0x9F) -#define MSM89XX_PMIC_ANALOG_RX_ATEST__POR (0x00) -#define MSM89XX_PMIC_ANALOG_RX_HPH_STATUS (CDC_ANA_BASE+0xA0) -#define MSM89XX_PMIC_ANALOG_RX_HPH_STATUS__POR (0x0C) -#define MSM89XX_PMIC_ANALOG_RX_EAR_STATUS (CDC_ANA_BASE+0xA1) -#define MSM89XX_PMIC_ANALOG_RX_EAR_STATUS__POR (0x00) -#define MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL (CDC_ANA_BASE+0xAC) -#define MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL__POR (0x00) -#define MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL (CDC_ANA_BASE+0xAD) -#define MSM89XX_PMIC_ANALOG_RX_RX_LO_EN_CTL__POR (0x00) -#define MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL (CDC_ANA_BASE+0xB0) -#define MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL__POR (0x83) -#define MSM89XX_PMIC_ANALOG_SPKR_DRV_CLIP_DET (CDC_ANA_BASE+0xB1) -#define MSM89XX_PMIC_ANALOG_SPKR_DRV_CLIP_DET__POR (0x91) -#define MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL (CDC_ANA_BASE+0xB2) -#define MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL__POR (0x29) -#define MSM89XX_PMIC_ANALOG_SPKR_ANA_BIAS_SET (CDC_ANA_BASE+0xB3) -#define MSM89XX_PMIC_ANALOG_SPKR_ANA_BIAS_SET__POR (0x4D) -#define MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL (CDC_ANA_BASE+0xB4) -#define MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL__POR (0xE1) -#define MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL (CDC_ANA_BASE+0xB5) -#define MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL__POR (0x1E) -#define MSM89XX_PMIC_ANALOG_SPKR_DRV_MISC (CDC_ANA_BASE+0xB6) -#define MSM89XX_PMIC_ANALOG_SPKR_DRV_MISC__POR (0xCB) -#define MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG (CDC_ANA_BASE+0xB7) -#define MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG__POR (0x00) -#define MSM89XX_PMIC_ANALOG_CURRENT_LIMIT (CDC_ANA_BASE+0xC0) -#define MSM89XX_PMIC_ANALOG_CURRENT_LIMIT__POR (0x02) -#define MSM89XX_PMIC_ANALOG_OUTPUT_VOLTAGE (CDC_ANA_BASE+0xC1) -#define MSM89XX_PMIC_ANALOG_OUTPUT_VOLTAGE__POR (0x14) -#define MSM89XX_PMIC_ANALOG_BYPASS_MODE (CDC_ANA_BASE+0xC2) -#define MSM89XX_PMIC_ANALOG_BYPASS_MODE__POR (0x00) -#define MSM89XX_PMIC_ANALOG_BOOST_EN_CTL (CDC_ANA_BASE+0xC3) -#define MSM89XX_PMIC_ANALOG_BOOST_EN_CTL__POR (0x1F) -#define MSM89XX_PMIC_ANALOG_SLOPE_COMP_IP_ZERO (CDC_ANA_BASE+0xC4) -#define MSM89XX_PMIC_ANALOG_SLOPE_COMP_IP_ZERO__POR (0x8C) -#define MSM89XX_PMIC_ANALOG_RDSON_MAX_DUTY_CYCLE (CDC_ANA_BASE+0xC5) -#define MSM89XX_PMIC_ANALOG_RDSON_MAX_DUTY_CYCLE__POR (0xC0) -#define MSM89XX_PMIC_ANALOG_BOOST_TEST1_1 (CDC_ANA_BASE+0xC6) -#define MSM89XX_PMIC_ANALOG_BOOST_TEST1_1__POR (0x00) -#define MSM89XX_PMIC_ANALOG_BOOST_TEST_2 (CDC_ANA_BASE+0xC7) -#define MSM89XX_PMIC_ANALOG_BOOST_TEST_2__POR (0x00) -#define MSM89XX_PMIC_ANALOG_SPKR_SAR_STATUS (CDC_ANA_BASE+0xC8) -#define MSM89XX_PMIC_ANALOG_SPKR_SAR_STATUS__POR (0x00) -#define MSM89XX_PMIC_ANALOG_SPKR_DRV_STATUS (CDC_ANA_BASE+0xC9) -#define MSM89XX_PMIC_ANALOG_SPKR_DRV_STATUS__POR (0x00) -#define MSM89XX_PMIC_ANALOG_PBUS_ADD_CSR (CDC_ANA_BASE+0xCE) -#define MSM89XX_PMIC_ANALOG_PBUS_ADD_CSR__POR (0x00) -#define MSM89XX_PMIC_ANALOG_PBUS_ADD_SEL (CDC_ANA_BASE+0xCF) -#define MSM89XX_PMIC_ANALOG_PBUS_ADD_SEL__POR (0x00) -#define MSM89XX_PMIC_ANALOG_SEC_ACCESS (CDC_ANA_BASE+0xD0) -#define MSM89XX_PMIC_ANALOG_SEC_ACCESS__POR (0x00) -#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL1 (CDC_ANA_BASE+0xD8) -#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL1__POR (0x00) -#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL2 (CDC_ANA_BASE+0xD9) -#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL2__POR (0x01) -#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3 (CDC_ANA_BASE+0xDA) -#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3__POR (0x05) -#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL4 (CDC_ANA_BASE+0xDB) -#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL4__POR (0x00) -#define MSM89XX_PMIC_ANALOG_INT_TEST1 (CDC_ANA_BASE+0xE0) -#define MSM89XX_PMIC_ANALOG_INT_TEST1__POR (0x00) -#define MSM89XX_PMIC_ANALOG_INT_TEST_VAL (CDC_ANA_BASE+0xE1) -#define MSM89XX_PMIC_ANALOG_INT_TEST_VAL__POR (0x00) -#define MSM89XX_PMIC_ANALOG_TRIM_NUM (CDC_ANA_BASE+0xF0) -#define MSM89XX_PMIC_ANALOG_TRIM_NUM__POR (0x04) -#define MSM89XX_PMIC_ANALOG_TRIM_CTRL1 (CDC_ANA_BASE+0xF1) -#define MSM89XX_PMIC_ANALOG_TRIM_CTRL1__POR (0x00) -#define MSM89XX_PMIC_ANALOG_TRIM_CTRL2 (CDC_ANA_BASE+0xF2) -#define MSM89XX_PMIC_ANALOG_TRIM_CTRL2__POR (0x00) -#define MSM89XX_PMIC_ANALOG_TRIM_CTRL3 (CDC_ANA_BASE+0xF3) -#define MSM89XX_PMIC_ANALOG_TRIM_CTRL3__POR (0x00) -#define MSM89XX_PMIC_ANALOG_TRIM_CTRL4 (CDC_ANA_BASE+0xF4) -#define MSM89XX_PMIC_ANALOG_TRIM_CTRL4__POR (0x00) - -#define MSM89XX_PMIC_CDC_NUM_REGISTERS \ - (MSM89XX_PMIC_ANALOG_TRIM_CTRL4+1) -#define MSM89XX_PMIC_CDC_MAX_REGISTER \ - (MSM89XX_PMIC_CDC_NUM_REGISTERS-1) -#define MSM89XX_PMIC_CDC_CACHE_SIZE \ - MSM89XX_PMIC_CDC_NUM_REGISTERS - - -#define MSM89XX_CDC_CORE_CLK_RX_RESET_CTL (0x00) -#define MSM89XX_CDC_CORE_CLK_RX_RESET_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL (0x04) -#define MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL (0x08) -#define MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CLK_RX_I2S_CTL (0x0C) -#define MSM89XX_CDC_CORE_CLK_RX_I2S_CTL__POR (0x13) -#define MSM89XX_CDC_CORE_CLK_TX_I2S_CTL (0x10) -#define MSM89XX_CDC_CORE_CLK_TX_I2S_CTL__POR (0x13) -#define MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL (0x14) -#define MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL (0x18) -#define MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CLK_OTHR_CTL (0x1C) -#define MSM89XX_CDC_CORE_CLK_OTHR_CTL__POR (0x04) -#define MSM89XX_CDC_CORE_CLK_RX_B1_CTL (0x20) -#define MSM89XX_CDC_CORE_CLK_RX_B1_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CLK_MCLK_CTL (0x24) -#define MSM89XX_CDC_CORE_CLK_MCLK_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CLK_PDM_CTL (0x28) -#define MSM89XX_CDC_CORE_CLK_PDM_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CLK_SD_CTL (0x2C) -#define MSM89XX_CDC_CORE_CLK_SD_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL (0x30) -#define MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CLK_RX_B2_CTL (0x34) -#define MSM89XX_CDC_CORE_CLK_RX_B2_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CLK_TX2_I2S_CTL (0x38) -#define MSM89XX_CDC_CORE_CLK_TX2_I2S_CTL__POR (0x13) -#define MSM89XX_CDC_CORE_RX1_B1_CTL (0x40) -#define MSM89XX_CDC_CORE_RX1_B1_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_RX2_B1_CTL (0x60) -#define MSM89XX_CDC_CORE_RX2_B1_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_RX3_B1_CTL (0x80) -#define MSM89XX_CDC_CORE_RX3_B1_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_RX1_B2_CTL (0x44) -#define MSM89XX_CDC_CORE_RX1_B2_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_RX2_B2_CTL (0x64) -#define MSM89XX_CDC_CORE_RX2_B2_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_RX3_B2_CTL (0x84) -#define MSM89XX_CDC_CORE_RX3_B2_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_RX1_B3_CTL (0x48) -#define MSM89XX_CDC_CORE_RX1_B3_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_RX2_B3_CTL (0x68) -#define MSM89XX_CDC_CORE_RX2_B3_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_RX3_B3_CTL (0x88) -#define MSM89XX_CDC_CORE_RX3_B3_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_RX1_B4_CTL (0x4C) -#define MSM89XX_CDC_CORE_RX1_B4_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_RX2_B4_CTL (0x6C) -#define MSM89XX_CDC_CORE_RX2_B4_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_RX3_B4_CTL (0x8C) -#define MSM89XX_CDC_CORE_RX3_B4_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_RX1_B5_CTL (0x50) -#define MSM89XX_CDC_CORE_RX1_B5_CTL__POR (0x68) -#define MSM89XX_CDC_CORE_RX2_B5_CTL (0x70) -#define MSM89XX_CDC_CORE_RX2_B5_CTL__POR (0x68) -#define MSM89XX_CDC_CORE_RX3_B5_CTL (0x90) -#define MSM89XX_CDC_CORE_RX3_B5_CTL__POR (0x68) -#define MSM89XX_CDC_CORE_RX1_B6_CTL (0x54) -#define MSM89XX_CDC_CORE_RX1_B6_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_RX2_B6_CTL (0x74) -#define MSM89XX_CDC_CORE_RX2_B6_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_RX3_B6_CTL (0x94) -#define MSM89XX_CDC_CORE_RX3_B6_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL (0x58) -#define MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL (0x78) -#define MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL (0x98) -#define MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL (0x5C) -#define MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL (0x7C) -#define MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL (0x9C) -#define MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_TOP_GAIN_UPDATE (0xA0) -#define MSM89XX_CDC_CORE_TOP_GAIN_UPDATE__POR (0x00) -#define MSM89XX_CDC_CORE_TOP_CTL (0xA4) -#define MSM89XX_CDC_CORE_TOP_CTL__POR (0x01) -#define MSM89XX_CDC_CORE_COMP0_B1_CTL (0xB0) -#define MSM89XX_CDC_CORE_COMP0_B1_CTL__POR (0x30) -#define MSM89XX_CDC_CORE_COMP0_B2_CTL (0xB4) -#define MSM89XX_CDC_CORE_COMP0_B2_CTL__POR (0xB5) -#define MSM89XX_CDC_CORE_COMP0_B3_CTL (0xB8) -#define MSM89XX_CDC_CORE_COMP0_B3_CTL__POR (0x28) -#define MSM89XX_CDC_CORE_COMP0_B4_CTL (0xBC) -#define MSM89XX_CDC_CORE_COMP0_B4_CTL__POR (0x37) -#define MSM89XX_CDC_CORE_COMP0_B5_CTL (0xC0) -#define MSM89XX_CDC_CORE_COMP0_B5_CTL__POR (0x7F) -#define MSM89XX_CDC_CORE_COMP0_B6_CTL (0xC4) -#define MSM89XX_CDC_CORE_COMP0_B6_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_COMP0_SHUT_DOWN_STATUS (0xC8) -#define MSM89XX_CDC_CORE_COMP0_SHUT_DOWN_STATUS__POR (0x03) -#define MSM89XX_CDC_CORE_COMP0_FS_CFG (0xCC) -#define MSM89XX_CDC_CORE_COMP0_FS_CFG__POR (0x03) -#define MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL (0xD0) -#define MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL__POR (0x02) -#define MSM89XX_CDC_CORE_DEBUG_DESER1_CTL (0xE0) -#define MSM89XX_CDC_CORE_DEBUG_DESER1_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_DEBUG_DESER2_CTL (0xE4) -#define MSM89XX_CDC_CORE_DEBUG_DESER2_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG (0xE8) -#define MSM89XX_CDC_CORE_DEBUG_B1_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG (0xEC) -#define MSM89XX_CDC_CORE_DEBUG_B2_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG (0xF0) -#define MSM89XX_CDC_CORE_DEBUG_B3_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL (0x100) -#define MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL (0x140) -#define MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL (0x104) -#define MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL (0x144) -#define MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL (0x108) -#define MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL (0x148) -#define MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL (0x10C) -#define MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL (0x14C) -#define MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL (0x110) -#define MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL (0x150) -#define MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL (0x114) -#define MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL (0x154) -#define MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL (0x118) -#define MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL (0x158) -#define MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL (0x11C) -#define MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL (0x15C) -#define MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_IIR1_CTL (0x120) -#define MSM89XX_CDC_CORE_IIR1_CTL__POR (0x40) -#define MSM89XX_CDC_CORE_IIR2_CTL (0x160) -#define MSM89XX_CDC_CORE_IIR2_CTL__POR (0x40) -#define MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL (0x124) -#define MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL (0x164) -#define MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL (0x128) -#define MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL (0x168) -#define MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL (0x12C) -#define MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL (0x16C) -#define MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CONN_RX1_B1_CTL (0x180) -#define MSM89XX_CDC_CORE_CONN_RX1_B1_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CONN_RX1_B2_CTL (0x184) -#define MSM89XX_CDC_CORE_CONN_RX1_B2_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CONN_RX1_B3_CTL (0x188) -#define MSM89XX_CDC_CORE_CONN_RX1_B3_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CONN_RX2_B1_CTL (0x18C) -#define MSM89XX_CDC_CORE_CONN_RX2_B1_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CONN_RX2_B2_CTL (0x190) -#define MSM89XX_CDC_CORE_CONN_RX2_B2_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CONN_RX2_B3_CTL (0x194) -#define MSM89XX_CDC_CORE_CONN_RX2_B3_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CONN_RX3_B1_CTL (0x198) -#define MSM89XX_CDC_CORE_CONN_RX3_B1_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CONN_RX3_B2_CTL (0x19C) -#define MSM89XX_CDC_CORE_CONN_RX3_B2_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CONN_TX_B1_CTL (0x1A0) -#define MSM89XX_CDC_CORE_CONN_TX_B1_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CONN_TX_B2_CTL (0x1A4) -#define MSM89XX_CDC_CORE_CONN_TX_B2_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL (0x1A8) -#define MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL (0x1AC) -#define MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL (0x1B0) -#define MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL (0x1B4) -#define MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL (0x1B8) -#define MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL (0x1BC) -#define MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL (0x1C0) -#define MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL (0x1C4) -#define MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL (0x1C8) -#define MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_CONN_TX_B3_CTL (0x1CC) -#define MSM89XX_CDC_CORE_CONN_TX_B3_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_TX5_VOL_CTL_TIMER (0x1E0) -#define MSM89XX_CDC_CORE_TX5_VOL_CTL_TIMER__POR (0x00) -#define MSM89XX_CDC_CORE_TX5_VOL_CTL_GAIN (0x1E4) -#define MSM89XX_CDC_CORE_TX5_VOL_CTL_GAIN__POR (0x00) -#define MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG (0x1E8) -#define MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG__POR (0x00) -#define MSM89XX_CDC_CORE_TX5_MUX_CTL (0x1EC) -#define MSM89XX_CDC_CORE_TX5_MUX_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_TX5_CLK_FS_CTL (0x1F0) -#define MSM89XX_CDC_CORE_TX5_CLK_FS_CTL__POR (0x03) -#define MSM89XX_CDC_CORE_TX5_DMIC_CTL (0x1F4) -#define MSM89XX_CDC_CORE_TX5_DMIC_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER (0x280) -#define MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER__POR (0x00) -#define MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER (0x2A0) -#define MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER__POR (0x00) -#define MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER (0x2C0) -#define MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER__POR (0x00) -#define MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER (0x2E0) -#define MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER__POR (0x00) -#define MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN (0x284) -#define MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN__POR (0x00) -#define MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN (0x2A4) -#define MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN__POR (0x00) -#define MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN (0x2C4) -#define MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN__POR (0x00) -#define MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN (0x2E4) -#define MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN__POR (0x00) -#define MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG (0x288) -#define MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG__POR (0x00) -#define MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG (0x2A8) -#define MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG__POR (0x00) -#define MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG (0x2C8) -#define MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG__POR (0x00) -#define MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG (0x2E8) -#define MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG__POR (0x00) -#define MSM89XX_CDC_CORE_TX1_MUX_CTL (0x28C) -#define MSM89XX_CDC_CORE_TX1_MUX_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_TX2_MUX_CTL (0x2AC) -#define MSM89XX_CDC_CORE_TX2_MUX_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_TX3_MUX_CTL (0x2CC) -#define MSM89XX_CDC_CORE_TX3_MUX_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_TX4_MUX_CTL (0x2EC) -#define MSM89XX_CDC_CORE_TX4_MUX_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_TX1_CLK_FS_CTL (0x290) -#define MSM89XX_CDC_CORE_TX1_CLK_FS_CTL__POR (0x03) -#define MSM89XX_CDC_CORE_TX2_CLK_FS_CTL (0x2B0) -#define MSM89XX_CDC_CORE_TX2_CLK_FS_CTL__POR (0x03) -#define MSM89XX_CDC_CORE_TX3_CLK_FS_CTL (0x2D0) -#define MSM89XX_CDC_CORE_TX3_CLK_FS_CTL__POR (0x03) -#define MSM89XX_CDC_CORE_TX4_CLK_FS_CTL (0x2F0) -#define MSM89XX_CDC_CORE_TX4_CLK_FS_CTL__POR (0x03) -#define MSM89XX_CDC_CORE_TX1_DMIC_CTL (0x294) -#define MSM89XX_CDC_CORE_TX1_DMIC_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_TX2_DMIC_CTL (0x2B4) -#define MSM89XX_CDC_CORE_TX2_DMIC_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_TX3_DMIC_CTL (0x2D4) -#define MSM89XX_CDC_CORE_TX3_DMIC_CTL__POR (0x00) -#define MSM89XX_CDC_CORE_TX4_DMIC_CTL (0x2F4) -#define MSM89XX_CDC_CORE_TX4_DMIC_CTL__POR (0x00) - -#define MSM89XX_CDC_CORE_NUM_REGISTERS \ - (MSM89XX_CDC_CORE_TX4_DMIC_CTL+1) -#define MSM89XX_CDC_CORE_MAX_REGISTER \ - (MSM89XX_CDC_CORE_NUM_REGISTERS-1) -#define MSM89XX_CDC_CORE_CACHE_SIZE \ - MSM89XX_CDC_CORE_NUM_REGISTERS -#endif diff --git a/sound/soc/codecs/msmfalcon_cdc/msmfalcon-regmap.c b/sound/soc/codecs/msmfalcon_cdc/msmfalcon-regmap.c deleted file mode 100644 index 5001c8da9877..000000000000 --- a/sound/soc/codecs/msmfalcon_cdc/msmfalcon-regmap.c +++ /dev/null @@ -1,471 +0,0 @@ -/* - * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include "msmfalcon-cdc-registers.h" - -/* - * Default register reset values that are common across different versions - * are defined here. If a register reset value is changed based on version - * then remove it from this structure and add it in version specific - * structures. - */ -struct reg_default - msm89xx_cdc_core_defaults[MSM89XX_CDC_CORE_CACHE_SIZE] = { - {MSM89XX_CDC_CORE_CLK_RX_RESET_CTL, 0x00}, - {MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL, 0x00}, - {MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL, 0x00}, - {MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 0x13}, - {MSM89XX_CDC_CORE_CLK_TX_I2S_CTL, 0x13}, - {MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL, 0x00}, - {MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 0x00}, - {MSM89XX_CDC_CORE_CLK_OTHR_CTL, 0x04}, - {MSM89XX_CDC_CORE_CLK_RX_B1_CTL, 0x00}, - {MSM89XX_CDC_CORE_CLK_MCLK_CTL, 0x00}, - {MSM89XX_CDC_CORE_CLK_PDM_CTL, 0x00}, - {MSM89XX_CDC_CORE_CLK_SD_CTL, 0x00}, - {MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL, 0x00}, - {MSM89XX_CDC_CORE_CLK_RX_B2_CTL, 0x00}, - {MSM89XX_CDC_CORE_CLK_TX2_I2S_CTL, 0x13}, - {MSM89XX_CDC_CORE_RX1_B1_CTL, 0x00}, - {MSM89XX_CDC_CORE_RX2_B1_CTL, 0x00}, - {MSM89XX_CDC_CORE_RX3_B1_CTL, 0x00}, - {MSM89XX_CDC_CORE_RX1_B2_CTL, 0x00}, - {MSM89XX_CDC_CORE_RX2_B2_CTL, 0x00}, - {MSM89XX_CDC_CORE_RX3_B2_CTL, 0x00}, - {MSM89XX_CDC_CORE_RX1_B3_CTL, 0x00}, - {MSM89XX_CDC_CORE_RX2_B3_CTL, 0x00}, - {MSM89XX_CDC_CORE_RX3_B3_CTL, 0x00}, - {MSM89XX_CDC_CORE_RX1_B4_CTL, 0x00}, - {MSM89XX_CDC_CORE_RX2_B4_CTL, 0x00}, - {MSM89XX_CDC_CORE_RX3_B4_CTL, 0x00}, - {MSM89XX_CDC_CORE_RX1_B5_CTL, 0x68}, - {MSM89XX_CDC_CORE_RX2_B5_CTL, 0x68}, - {MSM89XX_CDC_CORE_RX3_B5_CTL, 0x68}, - {MSM89XX_CDC_CORE_RX1_B6_CTL, 0x00}, - {MSM89XX_CDC_CORE_RX2_B6_CTL, 0x00}, - {MSM89XX_CDC_CORE_RX3_B6_CTL, 0x00}, - {MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL, 0x00}, - {MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL, 0x00}, - {MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL, 0x00}, - {MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL, 0x00}, - {MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL, 0x00}, - {MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL, 0x00}, - {MSM89XX_CDC_CORE_TOP_GAIN_UPDATE, 0x00}, - {MSM89XX_CDC_CORE_TOP_CTL, 0x01}, - {MSM89XX_CDC_CORE_COMP0_B1_CTL, 0x30}, - {MSM89XX_CDC_CORE_COMP0_B2_CTL, 0xB5}, - {MSM89XX_CDC_CORE_COMP0_B3_CTL, 0x28}, - {MSM89XX_CDC_CORE_COMP0_B4_CTL, 0x37}, - {MSM89XX_CDC_CORE_COMP0_B5_CTL, 0x7F}, - {MSM89XX_CDC_CORE_COMP0_B6_CTL, 0x00}, - {MSM89XX_CDC_CORE_COMP0_SHUT_DOWN_STATUS, 0x03}, - {MSM89XX_CDC_CORE_COMP0_FS_CFG, 0x03}, - {MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL, 0x02}, - {MSM89XX_CDC_CORE_DEBUG_DESER1_CTL, 0x00}, - {MSM89XX_CDC_CORE_DEBUG_DESER2_CTL, 0x00}, - {MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG, 0x00}, - {MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG, 0x00}, - {MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG, 0x00}, - {MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL, 0x00}, - {MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL, 0x00}, - {MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL, 0x00}, - {MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL, 0x00}, - {MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL, 0x00}, - {MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL, 0x00}, - {MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL, 0x00}, - {MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL, 0x00}, - {MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL, 0x00}, - {MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL, 0x00}, - {MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL, 0x00}, - {MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL, 0x00}, - {MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL, 0x00}, - {MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL, 0x00}, - {MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL, 0x00}, - {MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL, 0x00}, - {MSM89XX_CDC_CORE_IIR1_CTL, 0x40}, - {MSM89XX_CDC_CORE_IIR2_CTL, 0x40}, - {MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL, 0x00}, - {MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL, 0x00}, - {MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL, 0x00}, - {MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL, 0x00}, - {MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL, 0x00}, - {MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL, 0x00}, - {MSM89XX_CDC_CORE_CONN_RX1_B1_CTL, 0x00}, - {MSM89XX_CDC_CORE_CONN_RX1_B2_CTL, 0x00}, - {MSM89XX_CDC_CORE_CONN_RX1_B3_CTL, 0x00}, - {MSM89XX_CDC_CORE_CONN_RX2_B1_CTL, 0x00}, - {MSM89XX_CDC_CORE_CONN_RX2_B2_CTL, 0x00}, - {MSM89XX_CDC_CORE_CONN_RX2_B3_CTL, 0x00}, - {MSM89XX_CDC_CORE_CONN_RX3_B1_CTL, 0x00}, - {MSM89XX_CDC_CORE_CONN_RX3_B2_CTL, 0x00}, - {MSM89XX_CDC_CORE_CONN_TX_B1_CTL, 0x00}, - {MSM89XX_CDC_CORE_CONN_TX_B2_CTL, 0x00}, - {MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL, 0x00}, - {MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL, 0x00}, - {MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL, 0x00}, - {MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL, 0x00}, - {MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL, 0x00}, - {MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL, 0x00}, - {MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL, 0x00}, - {MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL, 0x00}, - {MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL, 0x00}, - {MSM89XX_CDC_CORE_CONN_TX_B3_CTL, 0x00}, - {MSM89XX_CDC_CORE_TX5_VOL_CTL_TIMER, 0x00}, - {MSM89XX_CDC_CORE_TX5_VOL_CTL_GAIN, 0x00}, - {MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG, 0x00}, - {MSM89XX_CDC_CORE_TX5_MUX_CTL, 0x00}, - {MSM89XX_CDC_CORE_TX5_CLK_FS_CTL, 0x03}, - {MSM89XX_CDC_CORE_TX5_DMIC_CTL, 0x00}, - {MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER, 0x00}, - {MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER, 0x00}, - {MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER, 0x00}, - {MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER, 0x00}, - {MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN, 0x00}, - {MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN, 0x00}, - {MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN, 0x00}, - {MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN, 0x00}, - {MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG, 0x00}, - {MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG, 0x00}, - {MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG, 0x00}, - {MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG, 0x00}, - {MSM89XX_CDC_CORE_TX1_MUX_CTL, 0x00}, - {MSM89XX_CDC_CORE_TX2_MUX_CTL, 0x00}, - {MSM89XX_CDC_CORE_TX3_MUX_CTL, 0x00}, - {MSM89XX_CDC_CORE_TX4_MUX_CTL, 0x00}, - {MSM89XX_CDC_CORE_TX1_CLK_FS_CTL, 0x03}, - {MSM89XX_CDC_CORE_TX2_CLK_FS_CTL, 0x03}, - {MSM89XX_CDC_CORE_TX3_CLK_FS_CTL, 0x03}, - {MSM89XX_CDC_CORE_TX4_CLK_FS_CTL, 0x03}, - {MSM89XX_CDC_CORE_TX1_DMIC_CTL, 0x00}, - {MSM89XX_CDC_CORE_TX2_DMIC_CTL, 0x00}, - {MSM89XX_CDC_CORE_TX3_DMIC_CTL, 0x00}, - {MSM89XX_CDC_CORE_TX4_DMIC_CTL, 0x00}, -}; - -struct reg_default - msm89xx_pmic_cdc_defaults[MSM89XX_PMIC_CDC_CACHE_SIZE] = { - {MSM89XX_PMIC_DIGITAL_REVISION1, 0x00}, - {MSM89XX_PMIC_DIGITAL_REVISION2, 0x00}, - {MSM89XX_PMIC_DIGITAL_PERPH_TYPE, 0x23}, - {MSM89XX_PMIC_DIGITAL_PERPH_SUBTYPE, 0x01}, - {MSM89XX_PMIC_DIGITAL_INT_RT_STS, 0x00}, - {MSM89XX_PMIC_DIGITAL_INT_SET_TYPE, 0xFF}, - {MSM89XX_PMIC_DIGITAL_INT_POLARITY_HIGH, 0xFF}, - {MSM89XX_PMIC_DIGITAL_INT_POLARITY_LOW, 0x00}, - {MSM89XX_PMIC_DIGITAL_INT_LATCHED_CLR, 0x00}, - {MSM89XX_PMIC_DIGITAL_INT_EN_SET, 0x00}, - {MSM89XX_PMIC_DIGITAL_INT_EN_CLR, 0x00}, - {MSM89XX_PMIC_DIGITAL_INT_LATCHED_STS, 0x00}, - {MSM89XX_PMIC_DIGITAL_INT_PENDING_STS, 0x00}, - {MSM89XX_PMIC_DIGITAL_INT_MID_SEL, 0x00}, - {MSM89XX_PMIC_DIGITAL_INT_PRIORITY, 0x00}, - {MSM89XX_PMIC_DIGITAL_GPIO_MODE, 0x00}, - {MSM89XX_PMIC_DIGITAL_PIN_CTL_OE, 0x01}, - {MSM89XX_PMIC_DIGITAL_PIN_CTL_DATA, 0x00}, - {MSM89XX_PMIC_DIGITAL_PIN_STATUS, 0x00}, - {MSM89XX_PMIC_DIGITAL_HDRIVE_CTL, 0x00}, - {MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x00}, - {MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL, 0x00}, - {MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x00}, - {MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x00}, - {MSM89XX_PMIC_DIGITAL_CDC_CONN_TX1_CTL, 0x02}, - {MSM89XX_PMIC_DIGITAL_CDC_CONN_TX2_CTL, 0x02}, - {MSM89XX_PMIC_DIGITAL_CDC_CONN_HPHR_DAC_CTL, 0x00}, - {MSM89XX_PMIC_DIGITAL_CDC_CONN_RX1_CTL, 0x00}, - {MSM89XX_PMIC_DIGITAL_CDC_CONN_RX2_CTL, 0x00}, - {MSM89XX_PMIC_DIGITAL_CDC_CONN_RX3_CTL, 0x00}, - {MSM89XX_PMIC_DIGITAL_CDC_CONN_RX_LB_CTL, 0x00}, - {MSM89XX_PMIC_DIGITAL_CDC_RX_CTL1, 0x7C}, - {MSM89XX_PMIC_DIGITAL_CDC_RX_CTL2, 0x7C}, - {MSM89XX_PMIC_DIGITAL_CDC_RX_CTL3, 0x7C}, - {MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA0, 0x00}, - {MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA1, 0x00}, - {MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA2, 0x00}, - {MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA3, 0x00}, - {MSM89XX_PMIC_DIGITAL_DIG_DEBUG_CTL, 0x00}, - {MSM89XX_PMIC_DIGITAL_DIG_DEBUG_EN, 0x00}, - {MSM89XX_PMIC_DIGITAL_SPARE_0, 0x00}, - {MSM89XX_PMIC_DIGITAL_SPARE_1, 0x00}, - {MSM89XX_PMIC_DIGITAL_SPARE_2, 0x00}, - {MSM89XX_PMIC_DIGITAL_SEC_ACCESS, 0x00}, - {MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL1, 0x00}, - {MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL2, 0x02}, - {MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x05}, - {MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL4, 0x00}, - {MSM89XX_PMIC_DIGITAL_INT_TEST1, 0x00}, - {MSM89XX_PMIC_DIGITAL_INT_TEST_VAL, 0x00}, - {MSM89XX_PMIC_DIGITAL_TRIM_NUM, 0x00}, - {MSM89XX_PMIC_DIGITAL_TRIM_CTRL, 0x00}, - {MSM89XX_PMIC_ANALOG_REVISION1, 0x00}, - {MSM89XX_PMIC_ANALOG_REVISION2, 0x00}, - {MSM89XX_PMIC_ANALOG_REVISION3, 0x00}, - {MSM89XX_PMIC_ANALOG_REVISION4, 0x00}, - {MSM89XX_PMIC_ANALOG_PERPH_TYPE, 0x23}, - {MSM89XX_PMIC_ANALOG_PERPH_SUBTYPE, 0x09}, - {MSM89XX_PMIC_ANALOG_INT_RT_STS, 0x00}, - {MSM89XX_PMIC_ANALOG_INT_SET_TYPE, 0x3F}, - {MSM89XX_PMIC_ANALOG_INT_POLARITY_HIGH, 0x3F}, - {MSM89XX_PMIC_ANALOG_INT_POLARITY_LOW, 0x00}, - {MSM89XX_PMIC_ANALOG_INT_LATCHED_CLR, 0x00}, - {MSM89XX_PMIC_ANALOG_INT_EN_SET, 0x00}, - {MSM89XX_PMIC_ANALOG_INT_EN_CLR, 0x00}, - {MSM89XX_PMIC_ANALOG_INT_LATCHED_STS, 0x00}, - {MSM89XX_PMIC_ANALOG_INT_PENDING_STS, 0x00}, - {MSM89XX_PMIC_ANALOG_INT_MID_SEL, 0x00}, - {MSM89XX_PMIC_ANALOG_INT_PRIORITY, 0x00}, - {MSM89XX_PMIC_ANALOG_MICB_1_EN, 0x00}, - {MSM89XX_PMIC_ANALOG_MICB_1_VAL, 0x20}, - {MSM89XX_PMIC_ANALOG_MICB_1_CTL, 0x00}, - {MSM89XX_PMIC_ANALOG_MICB_1_INT_RBIAS, 0x49}, - {MSM89XX_PMIC_ANALOG_MICB_2_EN, 0x20}, - {MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2, 0x00}, - {MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL, 0x00}, - {MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1, 0x35}, - {MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0x08}, - {MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, 0x00}, - {MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER, 0x98}, - {MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL, 0x00}, - {MSM89XX_PMIC_ANALOG_MBHC_BTN1_ZDETM_CTL, 0x20}, - {MSM89XX_PMIC_ANALOG_MBHC_BTN2_ZDETH_CTL, 0x40}, - {MSM89XX_PMIC_ANALOG_MBHC_BTN3_CTL, 0x61}, - {MSM89XX_PMIC_ANALOG_MBHC_BTN4_CTL, 0x80}, - {MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT, 0x00}, - {MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT, 0x00}, - {MSM89XX_PMIC_ANALOG_TX_1_EN, 0x03}, - {MSM89XX_PMIC_ANALOG_TX_2_EN, 0x03}, - {MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_1, 0xBF}, - {MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_2, 0x8C}, - {MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL, 0x00}, - {MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS, 0x6B}, - {MSM89XX_PMIC_ANALOG_TX_1_2_TXFE_CLKDIV, 0x51}, - {MSM89XX_PMIC_ANALOG_TX_3_EN, 0x02}, - {MSM89XX_PMIC_ANALOG_NCP_EN, 0x26}, - {MSM89XX_PMIC_ANALOG_NCP_CLK, 0x23}, - {MSM89XX_PMIC_ANALOG_NCP_DEGLITCH, 0x5B}, - {MSM89XX_PMIC_ANALOG_NCP_FBCTRL, 0x08}, - {MSM89XX_PMIC_ANALOG_NCP_BIAS, 0x29}, - {MSM89XX_PMIC_ANALOG_NCP_VCTRL, 0x24}, - {MSM89XX_PMIC_ANALOG_NCP_TEST, 0x00}, - {MSM89XX_PMIC_ANALOG_NCP_CLIM_ADDR, 0xD5}, - {MSM89XX_PMIC_ANALOG_RX_CLOCK_DIVIDER, 0xE8}, - {MSM89XX_PMIC_ANALOG_RX_COM_OCP_CTL, 0xCF}, - {MSM89XX_PMIC_ANALOG_RX_COM_OCP_COUNT, 0x6E}, - {MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, 0x18}, - {MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_PA, 0x5A}, - {MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_LDO_OCP, 0x69}, - {MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_CNP, 0x29}, - {MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, 0x80}, - {MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_CTL, 0xDA}, - {MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME, 0x16}, - {MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST, 0x00}, - {MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL, 0x20}, - {MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST, 0x00}, - {MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL, 0x20}, - {MSM89XX_PMIC_ANALOG_RX_EAR_CTL, 0x12}, - {MSM89XX_PMIC_ANALOG_RX_ATEST, 0x00}, - {MSM89XX_PMIC_ANALOG_RX_HPH_STATUS, 0x0C}, - {MSM89XX_PMIC_ANALOG_RX_EAR_STATUS, 0x00}, - {MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x00}, - {MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL, 0x00}, - {MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x83}, - {MSM89XX_PMIC_ANALOG_SPKR_DRV_CLIP_DET, 0x91}, - {MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, 0x29}, - {MSM89XX_PMIC_ANALOG_SPKR_ANA_BIAS_SET, 0x4D}, - {MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL, 0xE1}, - {MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, 0x1E}, - {MSM89XX_PMIC_ANALOG_SPKR_DRV_MISC, 0xCB}, - {MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG, 0x00}, - {MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0x02}, - {MSM89XX_PMIC_ANALOG_OUTPUT_VOLTAGE, 0x14}, - {MSM89XX_PMIC_ANALOG_BYPASS_MODE, 0x00}, - {MSM89XX_PMIC_ANALOG_BOOST_EN_CTL, 0x1F}, - {MSM89XX_PMIC_ANALOG_SLOPE_COMP_IP_ZERO, 0x8C}, - {MSM89XX_PMIC_ANALOG_RDSON_MAX_DUTY_CYCLE, 0xC0}, - {MSM89XX_PMIC_ANALOG_BOOST_TEST1_1, 0x00}, - {MSM89XX_PMIC_ANALOG_BOOST_TEST_2, 0x00}, - {MSM89XX_PMIC_ANALOG_SPKR_SAR_STATUS, 0x00}, - {MSM89XX_PMIC_ANALOG_SPKR_DRV_STATUS, 0x00}, - {MSM89XX_PMIC_ANALOG_PBUS_ADD_CSR, 0x00}, - {MSM89XX_PMIC_ANALOG_PBUS_ADD_SEL, 0x00}, - {MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0x00}, - {MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL1, 0x00}, - {MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL2, 0x01}, - {MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3, 0x05}, - {MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL4, 0x00}, - {MSM89XX_PMIC_ANALOG_INT_TEST1, 0x00}, - {MSM89XX_PMIC_ANALOG_INT_TEST_VAL, 0x00}, - {MSM89XX_PMIC_ANALOG_TRIM_NUM, 0x04}, - {MSM89XX_PMIC_ANALOG_TRIM_CTRL1, 0x00}, - {MSM89XX_PMIC_ANALOG_TRIM_CTRL2, 0x00}, - {MSM89XX_PMIC_ANALOG_TRIM_CTRL3, 0x00}, - {MSM89XX_PMIC_ANALOG_TRIM_CTRL4, 0x00}, -}; - -static const u8 msm89xx_cdc_core_reg_readable[MSM89XX_CDC_CORE_CACHE_SIZE] = { - [MSM89XX_CDC_CORE_CLK_RX_RESET_CTL] = 1, - [MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL] = 1, - [MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL] = 1, - [MSM89XX_CDC_CORE_CLK_RX_I2S_CTL] = 1, - [MSM89XX_CDC_CORE_CLK_TX_I2S_CTL] = 1, - [MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL] = 1, - [MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL] = 1, - [MSM89XX_CDC_CORE_CLK_OTHR_CTL] = 1, - [MSM89XX_CDC_CORE_CLK_RX_B1_CTL] = 1, - [MSM89XX_CDC_CORE_CLK_MCLK_CTL] = 1, - [MSM89XX_CDC_CORE_CLK_PDM_CTL] = 1, - [MSM89XX_CDC_CORE_CLK_SD_CTL] = 1, - [MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL] = 1, - [MSM89XX_CDC_CORE_CLK_RX_B2_CTL] = 1, - [MSM89XX_CDC_CORE_CLK_TX2_I2S_CTL] = 1, - [MSM89XX_CDC_CORE_RX1_B1_CTL] = 1, - [MSM89XX_CDC_CORE_RX2_B1_CTL] = 1, - [MSM89XX_CDC_CORE_RX3_B1_CTL] = 1, - [MSM89XX_CDC_CORE_RX1_B2_CTL] = 1, - [MSM89XX_CDC_CORE_RX2_B2_CTL] = 1, - [MSM89XX_CDC_CORE_RX3_B2_CTL] = 1, - [MSM89XX_CDC_CORE_RX1_B3_CTL] = 1, - [MSM89XX_CDC_CORE_RX2_B3_CTL] = 1, - [MSM89XX_CDC_CORE_RX3_B3_CTL] = 1, - [MSM89XX_CDC_CORE_RX1_B4_CTL] = 1, - [MSM89XX_CDC_CORE_RX2_B4_CTL] = 1, - [MSM89XX_CDC_CORE_RX3_B4_CTL] = 1, - [MSM89XX_CDC_CORE_RX1_B5_CTL] = 1, - [MSM89XX_CDC_CORE_RX2_B5_CTL] = 1, - [MSM89XX_CDC_CORE_RX3_B5_CTL] = 1, - [MSM89XX_CDC_CORE_RX1_B6_CTL] = 1, - [MSM89XX_CDC_CORE_RX2_B6_CTL] = 1, - [MSM89XX_CDC_CORE_RX3_B6_CTL] = 1, - [MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL] = 1, - [MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL] = 1, - [MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL] = 1, - [MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL] = 1, - [MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL] = 1, - [MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL] = 1, - [MSM89XX_CDC_CORE_TOP_GAIN_UPDATE] = 1, - [MSM89XX_CDC_CORE_TOP_CTL] = 1, - [MSM89XX_CDC_CORE_COMP0_B1_CTL] = 1, - [MSM89XX_CDC_CORE_COMP0_B2_CTL] = 1, - [MSM89XX_CDC_CORE_COMP0_B3_CTL] = 1, - [MSM89XX_CDC_CORE_COMP0_B4_CTL] = 1, - [MSM89XX_CDC_CORE_COMP0_B5_CTL] = 1, - [MSM89XX_CDC_CORE_COMP0_B6_CTL] = 1, - [MSM89XX_CDC_CORE_COMP0_SHUT_DOWN_STATUS] = 1, - [MSM89XX_CDC_CORE_COMP0_FS_CFG] = 1, - [MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL] = 1, - [MSM89XX_CDC_CORE_DEBUG_DESER1_CTL] = 1, - [MSM89XX_CDC_CORE_DEBUG_DESER2_CTL] = 1, - [MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG] = 1, - [MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG] = 1, - [MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG] = 1, - [MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL] = 1, - [MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL] = 1, - [MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL] = 1, - [MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL] = 1, - [MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL] = 1, - [MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL] = 1, - [MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL] = 1, - [MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL] = 1, - [MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL] = 1, - [MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL] = 1, - [MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL] = 1, - [MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL] = 1, - [MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL] = 1, - [MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL] = 1, - [MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL] = 1, - [MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL] = 1, - [MSM89XX_CDC_CORE_IIR1_CTL] = 1, - [MSM89XX_CDC_CORE_IIR2_CTL] = 1, - [MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL] = 1, - [MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL] = 1, - [MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL] = 1, - [MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL] = 1, - [MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL] = 1, - [MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL] = 1, - [MSM89XX_CDC_CORE_CONN_RX1_B1_CTL] = 1, - [MSM89XX_CDC_CORE_CONN_RX1_B2_CTL] = 1, - [MSM89XX_CDC_CORE_CONN_RX1_B3_CTL] = 1, - [MSM89XX_CDC_CORE_CONN_RX2_B1_CTL] = 1, - [MSM89XX_CDC_CORE_CONN_RX2_B2_CTL] = 1, - [MSM89XX_CDC_CORE_CONN_RX2_B3_CTL] = 1, - [MSM89XX_CDC_CORE_CONN_RX3_B1_CTL] = 1, - [MSM89XX_CDC_CORE_CONN_RX3_B2_CTL] = 1, - [MSM89XX_CDC_CORE_CONN_TX_B1_CTL] = 1, - [MSM89XX_CDC_CORE_CONN_TX_B2_CTL] = 1, - [MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL] = 1, - [MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL] = 1, - [MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL] = 1, - [MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL] = 1, - [MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL] = 1, - [MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL] = 1, - [MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL] = 1, - [MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL] = 1, - [MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL] = 1, - [MSM89XX_CDC_CORE_CONN_TX_B3_CTL] = 1, - [MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER] = 1, - [MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER] = 1, - [MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER] = 1, - [MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER] = 1, - [MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN] = 1, - [MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN] = 1, - [MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN] = 1, - [MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN] = 1, - [MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG] = 1, - [MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG] = 1, - [MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG] = 1, - [MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG] = 1, - [MSM89XX_CDC_CORE_TX1_MUX_CTL] = 1, - [MSM89XX_CDC_CORE_TX2_MUX_CTL] = 1, - [MSM89XX_CDC_CORE_TX3_MUX_CTL] = 1, - [MSM89XX_CDC_CORE_TX4_MUX_CTL] = 1, - [MSM89XX_CDC_CORE_TX1_CLK_FS_CTL] = 1, - [MSM89XX_CDC_CORE_TX2_CLK_FS_CTL] = 1, - [MSM89XX_CDC_CORE_TX3_CLK_FS_CTL] = 1, - [MSM89XX_CDC_CORE_TX4_CLK_FS_CTL] = 1, - [MSM89XX_CDC_CORE_TX5_VOL_CTL_TIMER] = 1, - [MSM89XX_CDC_CORE_TX5_VOL_CTL_GAIN] = 1, - [MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG] = 1, - [MSM89XX_CDC_CORE_TX5_MUX_CTL] = 1, - [MSM89XX_CDC_CORE_TX5_CLK_FS_CTL] = 1, - [MSM89XX_CDC_CORE_TX5_DMIC_CTL] = 1, - [MSM89XX_CDC_CORE_TX1_DMIC_CTL] = 1, - [MSM89XX_CDC_CORE_TX2_DMIC_CTL] = 1, - [MSM89XX_CDC_CORE_TX3_DMIC_CTL] = 1, - [MSM89XX_CDC_CORE_TX4_DMIC_CTL] = 1, -}; - -bool msm89xx_cdc_core_readable_reg(struct device *dev, unsigned int reg) -{ - return msm89xx_cdc_core_reg_readable[reg]; -} - -bool msm89xx_cdc_core_volatile_reg(struct device *dev, unsigned int reg) -{ - switch (reg) { - case MSM89XX_CDC_CORE_RX1_B1_CTL: - case MSM89XX_CDC_CORE_RX2_B1_CTL: - case MSM89XX_CDC_CORE_RX3_B1_CTL: - case MSM89XX_CDC_CORE_RX1_B6_CTL: - case MSM89XX_CDC_CORE_RX2_B6_CTL: - case MSM89XX_CDC_CORE_RX3_B6_CTL: - case MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG: - case MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG: - case MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL: - case MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL: - case MSM89XX_CDC_CORE_CLK_MCLK_CTL: - case MSM89XX_CDC_CORE_CLK_PDM_CTL: - return true; - default: - return false; - } -} diff --git a/sound/soc/codecs/sdm660_cdc/Kconfig b/sound/soc/codecs/sdm660_cdc/Kconfig new file mode 100644 index 000000000000..d370da3d2ad5 --- /dev/null +++ b/sound/soc/codecs/sdm660_cdc/Kconfig @@ -0,0 +1,3 @@ + +config SND_SOC_SDM660_CDC + tristate "MSM Internal PMIC based codec" diff --git a/sound/soc/codecs/sdm660_cdc/Makefile b/sound/soc/codecs/sdm660_cdc/Makefile new file mode 100644 index 000000000000..d846fae26054 --- /dev/null +++ b/sound/soc/codecs/sdm660_cdc/Makefile @@ -0,0 +1,2 @@ +snd-soc-sdm660-cdc-objs := msm-analog-cdc.o msm-digital-cdc.o sdm660-regmap.o +obj-$(CONFIG_SND_SOC_SDM660_CDC) += snd-soc-sdm660-cdc.o sdm660-cdc-irq.o diff --git a/sound/soc/codecs/sdm660_cdc/msm-analog-cdc.c b/sound/soc/codecs/sdm660_cdc/msm-analog-cdc.c new file mode 100644 index 000000000000..cee4720bbe31 --- /dev/null +++ b/sound/soc/codecs/sdm660_cdc/msm-analog-cdc.c @@ -0,0 +1,4645 @@ +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "msm-analog-cdc.h" +#include "sdm660-cdc-irq.h" +#include "sdm660-cdc-registers.h" +#include "msm-cdc-common.h" +#include "../../msm/sdm660-common.h" +#include "../wcd-mbhc-v2.h" + +#define DRV_NAME "pmic_analog_codec" +#define SDM660_CDC_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ + SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\ + SNDRV_PCM_RATE_48000) +#define SDM660_CDC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ + SNDRV_PCM_FMTBIT_S24_LE) +#define MSM_DIG_CDC_STRING_LEN 80 +#define MSM_ANLG_CDC_VERSION_ENTRY_SIZE 32 + +#define CODEC_DT_MAX_PROP_SIZE 40 +#define MAX_ON_DEMAND_SUPPLY_NAME_LENGTH 64 +#define BUS_DOWN 1 + +/* + *50 Milliseconds sufficient for DSP bring up in the modem + * after Sub System Restart + */ +#define ADSP_STATE_READY_TIMEOUT_MS 50 + +enum { + BOOST_SWITCH = 0, + BOOST_ALWAYS, + BYPASS_ALWAYS, + BOOST_ON_FOREVER, +}; + +#define EAR_PMD 0 +#define EAR_PMU 1 +#define SPK_PMD 2 +#define SPK_PMU 3 + +#define MICBIAS_DEFAULT_VAL 1800000 +#define MICBIAS_MIN_VAL 1600000 +#define MICBIAS_STEP_SIZE 50000 + +#define DEFAULT_BOOST_VOLTAGE 5000 +#define MIN_BOOST_VOLTAGE 4000 +#define MAX_BOOST_VOLTAGE 5550 +#define BOOST_VOLTAGE_STEP 50 + +#define SDM660_CDC_MBHC_BTN_COARSE_ADJ 100 /* in mV */ +#define SDM660_CDC_MBHC_BTN_FINE_ADJ 12 /* in mV */ + +#define VOLTAGE_CONVERTER(value, min_value, step_size)\ + ((value - min_value)/step_size) + +enum { + RX_MIX1_INP_SEL_ZERO = 0, + RX_MIX1_INP_SEL_IIR1, + RX_MIX1_INP_SEL_IIR2, + RX_MIX1_INP_SEL_RX1, + RX_MIX1_INP_SEL_RX2, + RX_MIX1_INP_SEL_RX3, +}; + +static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); +static struct snd_soc_dai_driver msm_anlg_cdc_i2s_dai[]; +/* By default enable the internal speaker boost */ +static bool spkr_boost_en = true; +static bool initial_boot = true; + +static char on_demand_supply_name[][MAX_ON_DEMAND_SUPPLY_NAME_LENGTH] = { + "cdc-vdd-mic-bias", +}; + +static struct wcd_mbhc_register + wcd_mbhc_registers[WCD_MBHC_REG_FUNC_MAX] = { + WCD_MBHC_REGISTER("WCD_MBHC_L_DET_EN", + MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1, 0x80, 7, 0), + WCD_MBHC_REGISTER("WCD_MBHC_GND_DET_EN", + MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1, 0x40, 6, 0), + WCD_MBHC_REGISTER("WCD_MBHC_MECH_DETECTION_TYPE", + MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1, 0x20, 5, 0), + WCD_MBHC_REGISTER("WCD_MBHC_MIC_CLAMP_CTL", + MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1, 0x18, 3, 0), + WCD_MBHC_REGISTER("WCD_MBHC_ELECT_DETECTION_TYPE", + MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0x01, 0, 0), + WCD_MBHC_REGISTER("WCD_MBHC_HS_L_DET_PULL_UP_CTRL", + MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0xC0, 6, 0), + WCD_MBHC_REGISTER("WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL", + MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0x20, 5, 0), + WCD_MBHC_REGISTER("WCD_MBHC_HPHL_PLUG_TYPE", + MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0x10, 4, 0), + WCD_MBHC_REGISTER("WCD_MBHC_GND_PLUG_TYPE", + MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0x08, 3, 0), + WCD_MBHC_REGISTER("WCD_MBHC_SW_HPH_LP_100K_TO_GND", + MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0x01, 0, 0), + WCD_MBHC_REGISTER("WCD_MBHC_ELECT_SCHMT_ISRC", + MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0x06, 1, 0), + WCD_MBHC_REGISTER("WCD_MBHC_FSM_EN", + MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, 0x80, 7, 0), + WCD_MBHC_REGISTER("WCD_MBHC_INSREM_DBNC", + MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER, 0xF0, 4, 0), + WCD_MBHC_REGISTER("WCD_MBHC_BTN_DBNC", + MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER, 0x0C, 2, 0), + WCD_MBHC_REGISTER("WCD_MBHC_HS_VREF", + MSM89XX_PMIC_ANALOG_MBHC_BTN3_CTL, 0x03, 0, 0), + WCD_MBHC_REGISTER("WCD_MBHC_HS_COMP_RESULT", + MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT, 0x01, + 0, 0), + WCD_MBHC_REGISTER("WCD_MBHC_MIC_SCHMT_RESULT", + MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT, 0x02, + 1, 0), + WCD_MBHC_REGISTER("WCD_MBHC_HPHL_SCHMT_RESULT", + MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT, 0x08, + 3, 0), + WCD_MBHC_REGISTER("WCD_MBHC_HPHR_SCHMT_RESULT", + MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT, 0x04, + 2, 0), + WCD_MBHC_REGISTER("WCD_MBHC_OCP_FSM_EN", + MSM89XX_PMIC_ANALOG_RX_COM_OCP_CTL, 0x10, 4, 0), + WCD_MBHC_REGISTER("WCD_MBHC_BTN_RESULT", + MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT, 0xFF, 0, 0), + WCD_MBHC_REGISTER("WCD_MBHC_BTN_ISRC_CTL", + MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, 0x70, 4, 0), + WCD_MBHC_REGISTER("WCD_MBHC_ELECT_RESULT", + MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT, 0xFF, + 0, 0), + WCD_MBHC_REGISTER("WCD_MBHC_MICB_CTRL", + MSM89XX_PMIC_ANALOG_MICB_2_EN, 0xC0, 6, 0), + WCD_MBHC_REGISTER("WCD_MBHC_HPH_CNP_WG_TIME", + MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME, 0xFC, 2, 0), + WCD_MBHC_REGISTER("WCD_MBHC_HPHR_PA_EN", + MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, 0x10, 4, 0), + WCD_MBHC_REGISTER("WCD_MBHC_HPHL_PA_EN", + MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, 0x20, 5, 0), + WCD_MBHC_REGISTER("WCD_MBHC_HPH_PA_EN", + MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, 0x30, 4, 0), + WCD_MBHC_REGISTER("WCD_MBHC_SWCH_LEVEL_REMOVE", + MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT, + 0x10, 4, 0), + WCD_MBHC_REGISTER("WCD_MBHC_PULLDOWN_CTRL", + MSM89XX_PMIC_ANALOG_MICB_2_EN, 0x20, 5, 0), + WCD_MBHC_REGISTER("WCD_MBHC_ANC_DET_EN", 0, 0, 0, 0), + WCD_MBHC_REGISTER("WCD_MBHC_FSM_STATUS", 0, 0, 0, 0), + WCD_MBHC_REGISTER("WCD_MBHC_MUX_CTL", 0, 0, 0, 0), +}; + +/* Multiply gain_adj and offset by 1000 and 100 to avoid float arithmetic */ +static const struct wcd_imped_i_ref imped_i_ref[] = { + {I_h4_UA, 8, 800, 9000, 10000}, + {I_pt5_UA, 10, 100, 990, 4600}, + {I_14_UA, 17, 14, 1050, 700}, + {I_l4_UA, 10, 4, 1165, 110}, + {I_1_UA, 0, 1, 1200, 65}, +}; + +static const struct wcd_mbhc_intr intr_ids = { + .mbhc_sw_intr = MSM89XX_IRQ_MBHC_HS_DET, + .mbhc_btn_press_intr = MSM89XX_IRQ_MBHC_PRESS, + .mbhc_btn_release_intr = MSM89XX_IRQ_MBHC_RELEASE, + .mbhc_hs_ins_intr = MSM89XX_IRQ_MBHC_INSREM_DET1, + .mbhc_hs_rem_intr = MSM89XX_IRQ_MBHC_INSREM_DET, + .hph_left_ocp = MSM89XX_IRQ_HPHL_OCP, + .hph_right_ocp = MSM89XX_IRQ_HPHR_OCP, +}; + +static int msm_anlg_cdc_dt_parse_vreg_info(struct device *dev, + struct sdm660_cdc_regulator *vreg, + const char *vreg_name, + bool ondemand); +static struct sdm660_cdc_pdata *msm_anlg_cdc_populate_dt_pdata( + struct device *dev); +static int msm_anlg_cdc_enable_ext_mb_source(struct wcd_mbhc *wcd_mbhc, + bool turn_on); +static void msm_anlg_cdc_trim_btn_reg(struct snd_soc_codec *codec); +static void msm_anlg_cdc_set_micb_v(struct snd_soc_codec *codec); +static void msm_anlg_cdc_set_boost_v(struct snd_soc_codec *codec); +static void msm_anlg_cdc_set_auto_zeroing(struct snd_soc_codec *codec, + bool enable); +static void msm_anlg_cdc_configure_cap(struct snd_soc_codec *codec, + bool micbias1, bool micbias2); +static bool msm_anlg_cdc_use_mb(struct snd_soc_codec *codec); + +static int get_codec_version(struct sdm660_cdc_priv *sdm660_cdc) +{ + if (sdm660_cdc->codec_version == DRAX_CDC) + return DRAX_CDC; + else if (sdm660_cdc->codec_version == DIANGU) + return DIANGU; + else if (sdm660_cdc->codec_version == CAJON_2_0) + return CAJON_2_0; + else if (sdm660_cdc->codec_version == CAJON) + return CAJON; + else if (sdm660_cdc->codec_version == CONGA) + return CONGA; + else if (sdm660_cdc->pmic_rev == TOMBAK_2_0) + return TOMBAK_2_0; + else if (sdm660_cdc->pmic_rev == TOMBAK_1_0) + return TOMBAK_1_0; + + pr_err("%s: unsupported codec version\n", __func__); + return UNSUPPORTED; +} + +static void wcd_mbhc_meas_imped(struct snd_soc_codec *codec, + s16 *impedance_l, s16 *impedance_r) +{ + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + if ((sdm660_cdc->imped_det_pin == WCD_MBHC_DET_BOTH) || + (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHL)) { + /* Enable ZDET_L_MEAS_EN */ + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, + 0x08, 0x08); + /* Wait for 2ms for measurement to complete */ + usleep_range(2000, 2100); + /* Read Left impedance value from Result1 */ + *impedance_l = snd_soc_read(codec, + MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT); + /* Enable ZDET_R_MEAS_EN */ + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, + 0x08, 0x00); + } + if ((sdm660_cdc->imped_det_pin == WCD_MBHC_DET_BOTH) || + (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHR)) { + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, + 0x04, 0x04); + /* Wait for 2ms for measurement to complete */ + usleep_range(2000, 2100); + /* Read Right impedance value from Result1 */ + *impedance_r = snd_soc_read(codec, + MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, + 0x04, 0x00); + } +} + +static void msm_anlg_cdc_set_ref_current(struct snd_soc_codec *codec, + enum wcd_curr_ref curr_ref) +{ + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + dev_dbg(codec->dev, "%s: curr_ref: %d\n", __func__, curr_ref); + + if (get_codec_version(sdm660_cdc) < CAJON) + dev_dbg(codec->dev, "%s: Setting ref current not required\n", + __func__); + + sdm660_cdc->imped_i_ref = imped_i_ref[curr_ref]; + + switch (curr_ref) { + case I_h4_UA: + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MICB_2_EN, + 0x07, 0x01); + break; + case I_pt5_UA: + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MICB_2_EN, + 0x07, 0x04); + break; + case I_14_UA: + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MICB_2_EN, + 0x07, 0x03); + break; + case I_l4_UA: + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MICB_2_EN, + 0x07, 0x01); + break; + case I_1_UA: + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MICB_2_EN, + 0x07, 0x00); + break; + default: + pr_debug("%s: No ref current set\n", __func__); + break; + } +} + +static bool msm_anlg_cdc_adj_ref_current(struct snd_soc_codec *codec, + s16 *impedance_l, s16 *impedance_r) +{ + int i = 2; + s16 compare_imp = 0; + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + if (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHR) + compare_imp = *impedance_r; + else + compare_imp = *impedance_l; + + if (get_codec_version(sdm660_cdc) < CAJON) { + dev_dbg(codec->dev, + "%s: Reference current adjustment not required\n", + __func__); + return false; + } + + while (compare_imp < imped_i_ref[i].min_val) { + msm_anlg_cdc_set_ref_current(codec, imped_i_ref[++i].curr_ref); + wcd_mbhc_meas_imped(codec, impedance_l, impedance_r); + compare_imp = (sdm660_cdc->imped_det_pin == + WCD_MBHC_DET_HPHR) ? *impedance_r : *impedance_l; + if (i >= I_1_UA) + break; + } + return true; +} + +void msm_anlg_cdc_spk_ext_pa_cb( + int (*codec_spk_ext_pa)(struct snd_soc_codec *codec, + int enable), struct snd_soc_codec *codec) +{ + struct sdm660_cdc_priv *sdm660_cdc; + + if (!codec) { + pr_err("%s: NULL codec pointer!\n", __func__); + return; + } + + sdm660_cdc = snd_soc_codec_get_drvdata(codec); + + dev_dbg(codec->dev, "%s: Enter\n", __func__); + sdm660_cdc->codec_spk_ext_pa_cb = codec_spk_ext_pa; +} + +static void msm_anlg_cdc_compute_impedance(struct snd_soc_codec *codec, s16 l, + s16 r, uint32_t *zl, uint32_t *zr, + bool high) +{ + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + uint32_t rl = 0, rr = 0; + struct wcd_imped_i_ref R = sdm660_cdc->imped_i_ref; + int codec_ver = get_codec_version(sdm660_cdc); + + switch (codec_ver) { + case TOMBAK_1_0: + case TOMBAK_2_0: + case CONGA: + if (high) { + dev_dbg(codec->dev, + "%s: This plug has high range impedance\n", + __func__); + rl = (uint32_t)(((100 * (l * 400 - 200))/96) - 230); + rr = (uint32_t)(((100 * (r * 400 - 200))/96) - 230); + } else { + dev_dbg(codec->dev, + "%s: This plug has low range impedance\n", + __func__); + rl = (uint32_t)(((1000 * (l * 2 - 1))/1165) - (13/10)); + rr = (uint32_t)(((1000 * (r * 2 - 1))/1165) - (13/10)); + } + break; + case CAJON: + case CAJON_2_0: + case DIANGU: + case DRAX_CDC: + if (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHL) { + rr = (uint32_t)(((DEFAULT_MULTIPLIER * (10 * r - 5)) - + (DEFAULT_OFFSET * DEFAULT_GAIN))/DEFAULT_GAIN); + rl = (uint32_t)(((10000 * (R.multiplier * (10 * l - 5))) + - R.offset * R.gain_adj)/(R.gain_adj * 100)); + } else if (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHR) { + rr = (uint32_t)(((10000 * (R.multiplier * (10 * r - 5))) + - R.offset * R.gain_adj)/(R.gain_adj * 100)); + rl = (uint32_t)(((DEFAULT_MULTIPLIER * (10 * l - 5))- + (DEFAULT_OFFSET * DEFAULT_GAIN))/DEFAULT_GAIN); + } else if (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_NONE) { + rr = (uint32_t)(((DEFAULT_MULTIPLIER * (10 * r - 5)) - + (DEFAULT_OFFSET * DEFAULT_GAIN))/DEFAULT_GAIN); + rl = (uint32_t)(((DEFAULT_MULTIPLIER * (10 * l - 5))- + (DEFAULT_OFFSET * DEFAULT_GAIN))/DEFAULT_GAIN); + } else { + rr = (uint32_t)(((10000 * (R.multiplier * (10 * r - 5))) + - R.offset * R.gain_adj)/(R.gain_adj * 100)); + rl = (uint32_t)(((10000 * (R.multiplier * (10 * l - 5))) + - R.offset * R.gain_adj)/(R.gain_adj * 100)); + } + break; + default: + dev_dbg(codec->dev, "%s: No codec mentioned\n", __func__); + break; + } + *zl = rl; + *zr = rr; +} + +static struct firmware_cal *msm_anlg_cdc_get_hwdep_fw_cal( + struct wcd_mbhc *wcd_mbhc, + enum wcd_cal_type type) +{ + struct sdm660_cdc_priv *sdm660_cdc; + struct firmware_cal *hwdep_cal; + struct snd_soc_codec *codec = wcd_mbhc->codec; + + if (!codec) { + pr_err("%s: NULL codec pointer\n", __func__); + return NULL; + } + sdm660_cdc = snd_soc_codec_get_drvdata(codec); + hwdep_cal = wcdcal_get_fw_cal(sdm660_cdc->fw_data, type); + if (!hwdep_cal) { + dev_err(codec->dev, "%s: cal not sent by %d\n", + __func__, type); + return NULL; + } + return hwdep_cal; +} + +static void wcd9xxx_spmi_irq_control(struct snd_soc_codec *codec, + int irq, bool enable) +{ + if (enable) + wcd9xxx_spmi_enable_irq(irq); + else + wcd9xxx_spmi_disable_irq(irq); +} + +static void msm_anlg_cdc_mbhc_clk_setup(struct snd_soc_codec *codec, + bool enable) +{ + if (enable) + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, + 0x08, 0x08); + else + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, + 0x08, 0x00); +} + +static int msm_anlg_cdc_mbhc_map_btn_code_to_num(struct snd_soc_codec *codec) +{ + int btn_code; + int btn; + + btn_code = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT); + + switch (btn_code) { + case 0: + btn = 0; + break; + case 1: + btn = 1; + break; + case 3: + btn = 2; + break; + case 7: + btn = 3; + break; + case 15: + btn = 4; + break; + default: + btn = -EINVAL; + break; + }; + + return btn; +} + +static bool msm_anlg_cdc_spmi_lock_sleep(struct wcd_mbhc *mbhc, bool lock) +{ + if (lock) + return wcd9xxx_spmi_lock_sleep(); + wcd9xxx_spmi_unlock_sleep(); + return 0; +} + +static bool msm_anlg_cdc_micb_en_status(struct wcd_mbhc *mbhc, int micb_num) +{ + if (micb_num == MIC_BIAS_1) + return (snd_soc_read(mbhc->codec, + MSM89XX_PMIC_ANALOG_MICB_1_EN) & + 0x80); + if (micb_num == MIC_BIAS_2) + return (snd_soc_read(mbhc->codec, + MSM89XX_PMIC_ANALOG_MICB_2_EN) & + 0x80); + return false; +} + +static void msm_anlg_cdc_enable_master_bias(struct snd_soc_codec *codec, + bool enable) +{ + if (enable) + snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL, + 0x30, 0x30); + else + snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL, + 0x30, 0x00); +} + +static void msm_anlg_cdc_mbhc_common_micb_ctrl(struct snd_soc_codec *codec, + int event, bool enable) +{ + u16 reg; + u8 mask; + u8 val; + + switch (event) { + case MBHC_COMMON_MICB_PRECHARGE: + reg = MSM89XX_PMIC_ANALOG_MICB_1_CTL; + mask = 0x60; + val = (enable ? 0x60 : 0x00); + break; + case MBHC_COMMON_MICB_SET_VAL: + reg = MSM89XX_PMIC_ANALOG_MICB_1_VAL; + mask = 0xFF; + val = (enable ? 0xC0 : 0x00); + break; + case MBHC_COMMON_MICB_TAIL_CURR: + reg = MSM89XX_PMIC_ANALOG_MICB_1_EN; + mask = 0x04; + val = (enable ? 0x04 : 0x00); + break; + default: + dev_err(codec->dev, + "%s: Invalid event received\n", __func__); + return; + }; + snd_soc_update_bits(codec, reg, mask, val); +} + +static void msm_anlg_cdc_mbhc_internal_micbias_ctrl(struct snd_soc_codec *codec, + int micbias_num, + bool enable) +{ + if (micbias_num == 1) { + if (enable) + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MICB_1_INT_RBIAS, + 0x10, 0x10); + else + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MICB_1_INT_RBIAS, + 0x10, 0x00); + } +} + +static bool msm_anlg_cdc_mbhc_hph_pa_on_status(struct snd_soc_codec *codec) +{ + return (snd_soc_read(codec, MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN) & + 0x30) ? true : false; +} + +static void msm_anlg_cdc_mbhc_program_btn_thr(struct snd_soc_codec *codec, + s16 *btn_low, s16 *btn_high, + int num_btn, bool is_micbias) +{ + int i; + u32 course, fine, reg_val; + u16 reg_addr = MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL; + s16 *btn_voltage; + + btn_voltage = ((is_micbias) ? btn_high : btn_low); + + for (i = 0; i < num_btn; i++) { + course = (btn_voltage[i] / SDM660_CDC_MBHC_BTN_COARSE_ADJ); + fine = ((btn_voltage[i] % SDM660_CDC_MBHC_BTN_COARSE_ADJ) / + SDM660_CDC_MBHC_BTN_FINE_ADJ); + + reg_val = (course << 5) | (fine << 2); + snd_soc_update_bits(codec, reg_addr, 0xFC, reg_val); + dev_dbg(codec->dev, + "%s: course: %d fine: %d reg_addr: %x reg_val: %x\n", + __func__, course, fine, reg_addr, reg_val); + reg_addr++; + } +} + +static void msm_anlg_cdc_mbhc_calc_impedance(struct wcd_mbhc *mbhc, + uint32_t *zl, uint32_t *zr) +{ + struct snd_soc_codec *codec = mbhc->codec; + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + s16 impedance_l, impedance_r; + s16 impedance_l_fixed; + s16 reg0, reg1, reg2, reg3, reg4; + bool high = false; + bool min_range_used = false; + + WCD_MBHC_RSC_ASSERT_LOCKED(mbhc); + reg0 = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER); + reg1 = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_MBHC_BTN2_ZDETH_CTL); + reg2 = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2); + reg3 = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_MICB_2_EN); + reg4 = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL); + + sdm660_cdc->imped_det_pin = WCD_MBHC_DET_BOTH; + mbhc->hph_type = WCD_MBHC_HPH_NONE; + + /* disable FSM and micbias and enable pullup*/ + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, + 0x80, 0x00); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MICB_2_EN, + 0xA5, 0x25); + /* + * Enable legacy electrical detection current sources + * and disable fast ramp and enable manual switching + * of extra capacitance + */ + dev_dbg(codec->dev, "%s: Setup for impedance det\n", __func__); + + msm_anlg_cdc_set_ref_current(codec, I_h4_UA); + + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, + 0x06, 0x02); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER, + 0x02, 0x02); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_BTN2_ZDETH_CTL, + 0x02, 0x00); + + dev_dbg(codec->dev, "%s: Start performing impedance detection\n", + __func__); + + wcd_mbhc_meas_imped(codec, &impedance_l, &impedance_r); + + if (impedance_l > 2 || impedance_r > 2) { + high = true; + if (!mbhc->mbhc_cfg->mono_stero_detection) { + /* Set ZDET_CHG to 0 to discharge ramp */ + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, + 0x02, 0x00); + /* wait 40ms for the discharge ramp to complete */ + usleep_range(40000, 40100); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL, + 0x03, 0x00); + sdm660_cdc->imped_det_pin = (impedance_l > 2 && + impedance_r > 2) ? + WCD_MBHC_DET_NONE : + ((impedance_l > 2) ? + WCD_MBHC_DET_HPHR : + WCD_MBHC_DET_HPHL); + if (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_NONE) + goto exit; + } else { + if (get_codec_version(sdm660_cdc) >= CAJON) { + if (impedance_l == 63 && impedance_r == 63) { + dev_dbg(codec->dev, + "%s: HPHL and HPHR are floating\n", + __func__); + sdm660_cdc->imped_det_pin = + WCD_MBHC_DET_NONE; + mbhc->hph_type = WCD_MBHC_HPH_NONE; + } else if (impedance_l == 63 + && impedance_r < 63) { + dev_dbg(codec->dev, + "%s: Mono HS with HPHL floating\n", + __func__); + sdm660_cdc->imped_det_pin = + WCD_MBHC_DET_HPHR; + mbhc->hph_type = WCD_MBHC_HPH_MONO; + } else if (impedance_r == 63 && + impedance_l < 63) { + dev_dbg(codec->dev, + "%s: Mono HS with HPHR floating\n", + __func__); + sdm660_cdc->imped_det_pin = + WCD_MBHC_DET_HPHL; + mbhc->hph_type = WCD_MBHC_HPH_MONO; + } else if (impedance_l > 3 && impedance_r > 3 && + (impedance_l == impedance_r)) { + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, + 0x06, 0x06); + wcd_mbhc_meas_imped(codec, &impedance_l, + &impedance_r); + if (impedance_r == impedance_l) + dev_dbg(codec->dev, + "%s: Mono Headset\n", + __func__); + sdm660_cdc->imped_det_pin = + WCD_MBHC_DET_NONE; + mbhc->hph_type = + WCD_MBHC_HPH_MONO; + } else { + dev_dbg(codec->dev, + "%s: STEREO headset is found\n", + __func__); + sdm660_cdc->imped_det_pin = + WCD_MBHC_DET_BOTH; + mbhc->hph_type = WCD_MBHC_HPH_STEREO; + } + } + } + } + + msm_anlg_cdc_set_ref_current(codec, I_pt5_UA); + msm_anlg_cdc_set_ref_current(codec, I_14_UA); + + /* Enable RAMP_L , RAMP_R & ZDET_CHG*/ + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL, + 0x03, 0x03); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, + 0x02, 0x02); + /* wait for 50msec for the HW to apply ramp on HPHL and HPHR */ + usleep_range(50000, 50100); + /* Enable ZDET_DISCHG_CAP_CTL to add extra capacitance */ + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, + 0x01, 0x01); + /* wait for 5msec for the voltage to get stable */ + usleep_range(5000, 5100); + + wcd_mbhc_meas_imped(codec, &impedance_l, &impedance_r); + + min_range_used = msm_anlg_cdc_adj_ref_current(codec, + &impedance_l, &impedance_r); + if (!mbhc->mbhc_cfg->mono_stero_detection) { + /* Set ZDET_CHG to 0 to discharge ramp */ + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, + 0x02, 0x00); + /* wait for 40msec for the capacitor to discharge */ + usleep_range(40000, 40100); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL, + 0x03, 0x00); + goto exit; + } + + /* we are setting ref current to the minimun range or the measured + * value larger than the minimum value, so min_range_used is true. + * If the headset is mono headset with either HPHL or HPHR floating + * then we have already done the mono stereo detection and do not + * need to continue further. + */ + + if (!min_range_used || + sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHL || + sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHR) + goto exit; + + + /* Disable Set ZDET_CONN_RAMP_L and enable ZDET_CONN_FIXED_L */ + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL, + 0x02, 0x00); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_BTN1_ZDETM_CTL, + 0x02, 0x02); + /* Set ZDET_CHG to 0 */ + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, + 0x02, 0x00); + /* wait for 40msec for the capacitor to discharge */ + usleep_range(40000, 40100); + + /* Set ZDET_CONN_RAMP_R to 0 */ + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL, + 0x01, 0x00); + /* Enable ZDET_L_MEAS_EN */ + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, + 0x08, 0x08); + /* wait for 2msec for the HW to compute left inpedance value */ + usleep_range(2000, 2100); + /* Read Left impedance value from Result1 */ + impedance_l_fixed = snd_soc_read(codec, + MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT); + /* Disable ZDET_L_MEAS_EN */ + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, + 0x08, 0x00); + /* + * Assume impedance_l is L1, impedance_l_fixed is L2. + * If the following condition is met, we can take this + * headset as mono one with impedance of L2. + * Otherwise, take it as stereo with impedance of L1. + * Condition: + * abs[(L2-0.5L1)/(L2+0.5L1)] < abs [(L2-L1)/(L2+L1)] + */ + if ((abs(impedance_l_fixed - impedance_l/2) * + (impedance_l_fixed + impedance_l)) >= + (abs(impedance_l_fixed - impedance_l) * + (impedance_l_fixed + impedance_l/2))) { + dev_dbg(codec->dev, + "%s: STEREO plug type detected\n", + __func__); + mbhc->hph_type = WCD_MBHC_HPH_STEREO; + } else { + dev_dbg(codec->dev, + "%s: MONO plug type detected\n", + __func__); + mbhc->hph_type = WCD_MBHC_HPH_MONO; + impedance_l = impedance_l_fixed; + } + /* Enable ZDET_CHG */ + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, + 0x02, 0x02); + /* wait for 10msec for the capacitor to charge */ + usleep_range(10000, 10100); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL, + 0x02, 0x02); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_BTN1_ZDETM_CTL, + 0x02, 0x00); + /* Set ZDET_CHG to 0 to discharge HPHL */ + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, + 0x02, 0x00); + /* wait for 40msec for the capacitor to discharge */ + usleep_range(40000, 40100); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL, + 0x02, 0x00); + +exit: + snd_soc_write(codec, MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, reg4); + snd_soc_write(codec, MSM89XX_PMIC_ANALOG_MICB_2_EN, reg3); + snd_soc_write(codec, MSM89XX_PMIC_ANALOG_MBHC_BTN2_ZDETH_CTL, reg1); + snd_soc_write(codec, MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER, reg0); + snd_soc_write(codec, MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, reg2); + msm_anlg_cdc_compute_impedance(codec, impedance_l, impedance_r, + zl, zr, high); + + dev_dbg(codec->dev, "%s: RL %d ohm, RR %d ohm\n", __func__, *zl, *zr); + dev_dbg(codec->dev, "%s: Impedance detection completed\n", __func__); +} + +static int msm_anlg_cdc_dig_register_notifier(void *handle, + struct notifier_block *nblock, + bool enable) +{ + struct sdm660_cdc *handle_cdc = handle; + + if (enable) + return blocking_notifier_chain_register(&handle_cdc->notifier, + nblock); + return blocking_notifier_chain_unregister(&handle_cdc->notifier, + nblock); +} + +static int msm_anlg_cdc_mbhc_register_notifier(struct wcd_mbhc *wcd_mbhc, + struct notifier_block *nblock, + bool enable) +{ + struct snd_soc_codec *codec = wcd_mbhc->codec; + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + if (enable) + return blocking_notifier_chain_register( + &sdm660_cdc->notifier, + nblock); + + return blocking_notifier_chain_unregister(&sdm660_cdc->notifier, + nblock); +} + +static int msm_anlg_cdc_request_irq(struct snd_soc_codec *codec, + int irq, irq_handler_t handler, + const char *name, void *data) +{ + return wcd9xxx_spmi_request_irq(irq, handler, name, data); +} + +static int msm_anlg_cdc_free_irq(struct snd_soc_codec *codec, + int irq, void *data) +{ + return wcd9xxx_spmi_free_irq(irq, data); +} + +static const struct wcd_mbhc_cb mbhc_cb = { + .enable_mb_source = msm_anlg_cdc_enable_ext_mb_source, + .trim_btn_reg = msm_anlg_cdc_trim_btn_reg, + .compute_impedance = msm_anlg_cdc_mbhc_calc_impedance, + .set_micbias_value = msm_anlg_cdc_set_micb_v, + .set_auto_zeroing = msm_anlg_cdc_set_auto_zeroing, + .get_hwdep_fw_cal = msm_anlg_cdc_get_hwdep_fw_cal, + .set_cap_mode = msm_anlg_cdc_configure_cap, + .register_notifier = msm_anlg_cdc_mbhc_register_notifier, + .request_irq = msm_anlg_cdc_request_irq, + .irq_control = wcd9xxx_spmi_irq_control, + .free_irq = msm_anlg_cdc_free_irq, + .clk_setup = msm_anlg_cdc_mbhc_clk_setup, + .map_btn_code_to_num = msm_anlg_cdc_mbhc_map_btn_code_to_num, + .lock_sleep = msm_anlg_cdc_spmi_lock_sleep, + .micbias_enable_status = msm_anlg_cdc_micb_en_status, + .mbhc_bias = msm_anlg_cdc_enable_master_bias, + .mbhc_common_micb_ctrl = msm_anlg_cdc_mbhc_common_micb_ctrl, + .micb_internal = msm_anlg_cdc_mbhc_internal_micbias_ctrl, + .hph_pa_on_status = msm_anlg_cdc_mbhc_hph_pa_on_status, + .set_btn_thr = msm_anlg_cdc_mbhc_program_btn_thr, + .extn_use_mb = msm_anlg_cdc_use_mb, +}; + +static const uint32_t wcd_imped_val[] = {4, 8, 12, 13, 16, + 20, 24, 28, 32, + 36, 40, 44, 48}; + +static void msm_anlg_cdc_dig_notifier_call(struct snd_soc_codec *codec, + const enum dig_cdc_notify_event event) +{ + struct sdm660_cdc *sdm660_cdc = codec->control_data; + + pr_debug("%s: notifier call event %d\n", __func__, event); + blocking_notifier_call_chain(&sdm660_cdc->notifier, + event, NULL); +} + +static void msm_anlg_cdc_notifier_call(struct snd_soc_codec *codec, + const enum wcd_notify_event event) +{ + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + dev_dbg(codec->dev, "%s: notifier call event %d\n", __func__, event); + blocking_notifier_call_chain(&sdm660_cdc->notifier, event, + &sdm660_cdc->mbhc); +} + +static void msm_anlg_cdc_boost_on(struct snd_soc_codec *codec) +{ + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x0F, 0x0F); + snd_soc_write(codec, MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0xA5); + snd_soc_write(codec, MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3, 0x0F); + snd_soc_write(codec, MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL, 0x30); + if (get_codec_version(sdm660_cdc) < CAJON_2_0) + snd_soc_write(codec, MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0x82); + else + snd_soc_write(codec, MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0xA2); + snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, + 0x69, 0x69); + snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG, + 0x01, 0x01); + snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SLOPE_COMP_IP_ZERO, + 0x88, 0x88); + snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, + 0x03, 0x03); + snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL, + 0xE1, 0xE1); + if (get_codec_version(sdm660_cdc) < CAJON_2_0) { + snd_soc_update_bits(codec, MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, + 0x20, 0x20); + /* Wait for 1ms after clock ctl enable */ + usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS); + snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_BOOST_EN_CTL, + 0xDF, 0xDF); + usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS); + } else { + snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_BOOST_EN_CTL, + 0x40, 0x00); + snd_soc_update_bits(codec, MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, + 0x20, 0x20); + snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_BOOST_EN_CTL, + 0x80, 0x80); + /* Wait for 500us after BOOST_EN to happen */ + usleep_range(500, 510); + snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_BOOST_EN_CTL, + 0x40, 0x40); + /* Wait for 500us after BOOST pulse_skip */ + usleep_range(500, 510); + } +} + +static void msm_anlg_cdc_boost_off(struct snd_soc_codec *codec) +{ + snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_BOOST_EN_CTL, + 0xDF, 0x5F); + snd_soc_update_bits(codec, MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, + 0x20, 0x00); +} + +static void msm_anlg_cdc_bypass_on(struct snd_soc_codec *codec) +{ + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + if (get_codec_version(sdm660_cdc) < CAJON_2_0) { + snd_soc_write(codec, + MSM89XX_PMIC_ANALOG_SEC_ACCESS, + 0xA5); + snd_soc_write(codec, + MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3, + 0x07); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_BYPASS_MODE, + 0x02, 0x02); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_BYPASS_MODE, + 0x01, 0x00); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_BYPASS_MODE, + 0x40, 0x40); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_BYPASS_MODE, + 0x80, 0x80); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_BOOST_EN_CTL, + 0xDF, 0xDF); + } else { + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, + 0x20, 0x20); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_BYPASS_MODE, + 0x20, 0x20); + } +} + +static void msm_anlg_cdc_bypass_off(struct snd_soc_codec *codec) +{ + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + if (get_codec_version(sdm660_cdc) < CAJON_2_0) { + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_BOOST_EN_CTL, + 0x80, 0x00); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_BYPASS_MODE, + 0x80, 0x00); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_BYPASS_MODE, + 0x02, 0x00); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_BYPASS_MODE, + 0x40, 0x00); + } else { + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_BYPASS_MODE, + 0x20, 0x00); + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, + 0x20, 0x00); + } +} + +static void msm_anlg_cdc_boost_mode_sequence(struct snd_soc_codec *codec, + int flag) +{ + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + if (flag == EAR_PMU) { + switch (sdm660_cdc->boost_option) { + case BOOST_SWITCH: + if (sdm660_cdc->ear_pa_boost_set) { + msm_anlg_cdc_boost_off(codec); + msm_anlg_cdc_bypass_on(codec); + } + break; + case BOOST_ALWAYS: + msm_anlg_cdc_boost_on(codec); + break; + case BYPASS_ALWAYS: + msm_anlg_cdc_bypass_on(codec); + break; + case BOOST_ON_FOREVER: + msm_anlg_cdc_boost_on(codec); + break; + default: + dev_err(codec->dev, + "%s: invalid boost option: %d\n", __func__, + sdm660_cdc->boost_option); + break; + } + } else if (flag == EAR_PMD) { + switch (sdm660_cdc->boost_option) { + case BOOST_SWITCH: + if (sdm660_cdc->ear_pa_boost_set) + msm_anlg_cdc_bypass_off(codec); + break; + case BOOST_ALWAYS: + msm_anlg_cdc_boost_off(codec); + /* 80ms for EAR boost to settle down */ + msleep(80); + break; + case BYPASS_ALWAYS: + /* nothing to do as bypass on always */ + break; + case BOOST_ON_FOREVER: + /* nothing to do as boost on forever */ + break; + default: + dev_err(codec->dev, + "%s: invalid boost option: %d\n", __func__, + sdm660_cdc->boost_option); + break; + } + } else if (flag == SPK_PMU) { + switch (sdm660_cdc->boost_option) { + case BOOST_SWITCH: + if (sdm660_cdc->spk_boost_set) { + msm_anlg_cdc_bypass_off(codec); + msm_anlg_cdc_boost_on(codec); + } + break; + case BOOST_ALWAYS: + msm_anlg_cdc_boost_on(codec); + break; + case BYPASS_ALWAYS: + msm_anlg_cdc_bypass_on(codec); + break; + case BOOST_ON_FOREVER: + msm_anlg_cdc_boost_on(codec); + break; + default: + dev_err(codec->dev, + "%s: invalid boost option: %d\n", __func__, + sdm660_cdc->boost_option); + break; + } + } else if (flag == SPK_PMD) { + switch (sdm660_cdc->boost_option) { + case BOOST_SWITCH: + if (sdm660_cdc->spk_boost_set) { + msm_anlg_cdc_boost_off(codec); + /* + * Add 40 ms sleep for the spk + * boost to settle down + */ + msleep(40); + } + break; + case BOOST_ALWAYS: + msm_anlg_cdc_boost_off(codec); + /* + * Add 40 ms sleep for the spk + * boost to settle down + */ + msleep(40); + break; + case BYPASS_ALWAYS: + /* nothing to do as bypass on always */ + break; + case BOOST_ON_FOREVER: + /* nothing to do as boost on forever */ + break; + default: + dev_err(codec->dev, + "%s: invalid boost option: %d\n", __func__, + sdm660_cdc->boost_option); + break; + } + } +} + +static int msm_anlg_cdc_dt_parse_vreg_info(struct device *dev, + struct sdm660_cdc_regulator *vreg, const char *vreg_name, + bool ondemand) +{ + int len, ret = 0; + const __be32 *prop; + char prop_name[CODEC_DT_MAX_PROP_SIZE]; + struct device_node *regnode = NULL; + u32 prop_val; + + snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE, "%s-supply", + vreg_name); + regnode = of_parse_phandle(dev->of_node, prop_name, 0); + + if (!regnode) { + dev_err(dev, "Looking up %s property in node %s failed\n", + prop_name, dev->of_node->full_name); + return -ENODEV; + } + + dev_dbg(dev, "Looking up %s property in node %s\n", + prop_name, dev->of_node->full_name); + + vreg->name = vreg_name; + vreg->ondemand = ondemand; + + snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE, + "qcom,%s-voltage", vreg_name); + prop = of_get_property(dev->of_node, prop_name, &len); + + if (!prop || (len != (2 * sizeof(__be32)))) { + dev_err(dev, "%s %s property\n", + prop ? "invalid format" : "no", prop_name); + return -EINVAL; + } + vreg->min_uv = be32_to_cpup(&prop[0]); + vreg->max_uv = be32_to_cpup(&prop[1]); + + snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE, + "qcom,%s-current", vreg_name); + + ret = of_property_read_u32(dev->of_node, prop_name, &prop_val); + if (ret) { + dev_err(dev, "Looking up %s property in node %s failed", + prop_name, dev->of_node->full_name); + return -EFAULT; + } + vreg->optimum_ua = prop_val; + + dev_dbg(dev, "%s: vol=[%d %d]uV, curr=[%d]uA, ond %d\n\n", vreg->name, + vreg->min_uv, vreg->max_uv, vreg->optimum_ua, vreg->ondemand); + return 0; +} + +static void msm_anlg_cdc_dt_parse_boost_info(struct snd_soc_codec *codec) +{ + struct sdm660_cdc_priv *sdm660_cdc_priv = + snd_soc_codec_get_drvdata(codec); + const char *prop_name = "qcom,cdc-boost-voltage"; + int boost_voltage, ret; + + ret = of_property_read_u32(codec->dev->of_node, prop_name, + &boost_voltage); + if (ret) { + dev_dbg(codec->dev, "Looking up %s property in node %s failed\n", + prop_name, codec->dev->of_node->full_name); + boost_voltage = DEFAULT_BOOST_VOLTAGE; + } + if (boost_voltage < MIN_BOOST_VOLTAGE || + boost_voltage > MAX_BOOST_VOLTAGE) { + dev_err(codec->dev, + "Incorrect boost voltage. Reverting to default\n"); + boost_voltage = DEFAULT_BOOST_VOLTAGE; + } + + sdm660_cdc_priv->boost_voltage = + VOLTAGE_CONVERTER(boost_voltage, MIN_BOOST_VOLTAGE, + BOOST_VOLTAGE_STEP); + dev_dbg(codec->dev, "Boost voltage value is: %d\n", + boost_voltage); +} + +static void msm_anlg_cdc_dt_parse_micbias_info(struct device *dev, + struct wcd_micbias_setting *micbias) +{ + const char *prop_name = "qcom,cdc-micbias-cfilt-mv"; + int ret; + + ret = of_property_read_u32(dev->of_node, prop_name, + &micbias->cfilt1_mv); + if (ret) { + dev_dbg(dev, "Looking up %s property in node %s failed", + prop_name, dev->of_node->full_name); + micbias->cfilt1_mv = MICBIAS_DEFAULT_VAL; + } +} + +static struct sdm660_cdc_pdata *msm_anlg_cdc_populate_dt_pdata( + struct device *dev) +{ + struct sdm660_cdc_pdata *pdata; + int ret, static_cnt, ond_cnt, idx, i; + const char *name = NULL; + const char *static_prop_name = "qcom,cdc-static-supplies"; + const char *ond_prop_name = "qcom,cdc-on-demand-supplies"; + + pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return NULL; + + static_cnt = of_property_count_strings(dev->of_node, static_prop_name); + if (IS_ERR_VALUE(static_cnt)) { + dev_err(dev, "%s: Failed to get static supplies %d\n", __func__, + static_cnt); + ret = -EINVAL; + goto err; + } + + /* On-demand supply list is an optional property */ + ond_cnt = of_property_count_strings(dev->of_node, ond_prop_name); + if (IS_ERR_VALUE(ond_cnt)) + ond_cnt = 0; + + WARN_ON(static_cnt <= 0 || ond_cnt < 0); + if ((static_cnt + ond_cnt) > ARRAY_SIZE(pdata->regulator)) { + dev_err(dev, "%s: Num of supplies %u > max supported %zd\n", + __func__, (static_cnt + ond_cnt), + ARRAY_SIZE(pdata->regulator)); + ret = -EINVAL; + goto err; + } + + for (idx = 0; idx < static_cnt; idx++) { + ret = of_property_read_string_index(dev->of_node, + static_prop_name, idx, + &name); + if (ret) { + dev_err(dev, "%s: of read string %s idx %d error %d\n", + __func__, static_prop_name, idx, ret); + goto err; + } + + dev_dbg(dev, "%s: Found static cdc supply %s\n", __func__, + name); + ret = msm_anlg_cdc_dt_parse_vreg_info(dev, + &pdata->regulator[idx], + name, false); + if (ret) { + dev_err(dev, "%s:err parsing vreg for %s idx %d\n", + __func__, name, idx); + goto err; + } + } + + for (i = 0; i < ond_cnt; i++, idx++) { + ret = of_property_read_string_index(dev->of_node, ond_prop_name, + i, &name); + if (ret) { + dev_err(dev, "%s: err parsing on_demand for %s idx %d\n", + __func__, ond_prop_name, i); + goto err; + } + + dev_dbg(dev, "%s: Found on-demand cdc supply %s\n", __func__, + name); + ret = msm_anlg_cdc_dt_parse_vreg_info(dev, + &pdata->regulator[idx], + name, true); + if (ret) { + dev_err(dev, "%s: err parsing vreg on_demand for %s idx %d\n", + __func__, name, idx); + goto err; + } + } + msm_anlg_cdc_dt_parse_micbias_info(dev, &pdata->micbias); + + return pdata; +err: + devm_kfree(dev, pdata); + dev_err(dev, "%s: Failed to populate DT data ret = %d\n", + __func__, ret); + return NULL; +} + +static int msm_anlg_cdc_codec_enable_on_demand_supply( + struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + int ret = 0; + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + struct on_demand_supply *supply; + + if (w->shift >= ON_DEMAND_SUPPLIES_MAX) { + dev_err(codec->dev, "%s: error index > MAX Demand supplies", + __func__); + ret = -EINVAL; + goto out; + } + dev_dbg(codec->dev, "%s: supply: %s event: %d ref: %d\n", + __func__, on_demand_supply_name[w->shift], event, + atomic_read(&sdm660_cdc->on_demand_list[w->shift].ref)); + + supply = &sdm660_cdc->on_demand_list[w->shift]; + WARN_ONCE(!supply->supply, "%s isn't defined\n", + on_demand_supply_name[w->shift]); + if (!supply->supply) { + dev_err(codec->dev, "%s: err supply not present ond for %d", + __func__, w->shift); + goto out; + } + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + if (atomic_inc_return(&supply->ref) == 1) + ret = regulator_enable(supply->supply); + if (ret) + dev_err(codec->dev, "%s: Failed to enable %s\n", + __func__, + on_demand_supply_name[w->shift]); + break; + case SND_SOC_DAPM_POST_PMD: + if (atomic_read(&supply->ref) == 0) { + dev_dbg(codec->dev, "%s: %s supply has been disabled.\n", + __func__, on_demand_supply_name[w->shift]); + goto out; + } + if (atomic_dec_return(&supply->ref) == 0) + ret = regulator_disable(supply->supply); + if (ret) + dev_err(codec->dev, "%s: Failed to disable %s\n", + __func__, + on_demand_supply_name[w->shift]); + break; + default: + break; + } +out: + return ret; +} + +static int msm_anlg_cdc_codec_enable_clock_block(struct snd_soc_codec *codec, + int enable) +{ + struct msm_asoc_mach_data *pdata = NULL; + + pdata = snd_soc_card_get_drvdata(codec->component.card); + if (enable) { + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL, 0x30, 0x30); + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x80, 0x80); + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL, 0x0C, 0x0C); + msm_anlg_cdc_dig_notifier_call(codec, DIG_CDC_EVENT_CLK_ON); + } else { + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL, 0x0C, 0x00); + msm_anlg_cdc_dig_notifier_call(codec, DIG_CDC_EVENT_CLK_OFF); + } + return 0; +} + +static int msm_anlg_cdc_codec_enable_charge_pump(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + dev_dbg(codec->dev, "%s: event = %d\n", __func__, event); + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + msm_anlg_cdc_codec_enable_clock_block(codec, 1); + if (!(strcmp(w->name, "EAR CP"))) { + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, + 0x80, 0x80); + msm_anlg_cdc_boost_mode_sequence(codec, EAR_PMU); + } else if (get_codec_version(sdm660_cdc) >= DIANGU) { + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, + 0x80, 0x80); + } else { + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, + 0xC0, 0xC0); + } + break; + case SND_SOC_DAPM_POST_PMU: + /* Wait for 1ms post powerup of chargepump */ + usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS); + break; + case SND_SOC_DAPM_POST_PMD: + /* Wait for 1ms post powerdown of chargepump */ + usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS); + if (!(strcmp(w->name, "EAR CP"))) { + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, + 0x80, 0x00); + if (sdm660_cdc->boost_option != BOOST_ALWAYS) { + dev_dbg(codec->dev, + "%s: boost_option:%d, tear down ear\n", + __func__, sdm660_cdc->boost_option); + msm_anlg_cdc_boost_mode_sequence(codec, + EAR_PMD); + } + /* + * Reset pa select bit from ear to hph after ear pa + * is disabled and HPH DAC disable to reduce ear + * turn off pop and avoid HPH pop in concurrency + */ + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_EAR_CTL, 0x80, 0x00); + } else { + if (get_codec_version(sdm660_cdc) < DIANGU) + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, + 0x40, 0x00); + if (sdm660_cdc->rx_bias_count == 0) + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, + 0x80, 0x00); + dev_dbg(codec->dev, "%s: rx_bias_count = %d\n", + __func__, sdm660_cdc->rx_bias_count); + } + break; + } + return 0; +} + +static int msm_anlg_cdc_ear_pa_boost_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + ucontrol->value.integer.value[0] = + (sdm660_cdc->ear_pa_boost_set ? 1 : 0); + dev_dbg(codec->dev, "%s: sdm660_cdc->ear_pa_boost_set = %d\n", + __func__, sdm660_cdc->ear_pa_boost_set); + return 0; +} + +static int msm_anlg_cdc_ear_pa_boost_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", + __func__, ucontrol->value.integer.value[0]); + sdm660_cdc->ear_pa_boost_set = + (ucontrol->value.integer.value[0] ? true : false); + return 0; +} + +static int msm_anlg_cdc_loopback_mode_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct msm_asoc_mach_data *pdata = NULL; + + pdata = snd_soc_card_get_drvdata(codec->component.card); + dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", + __func__, ucontrol->value.integer.value[0]); + + return pdata->lb_mode; +} + +static int msm_anlg_cdc_loopback_mode_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct msm_asoc_mach_data *pdata = NULL; + + pdata = snd_soc_card_get_drvdata(codec->component.card); + dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", + __func__, ucontrol->value.integer.value[0]); + + switch (ucontrol->value.integer.value[0]) { + case 0: + pdata->lb_mode = false; + break; + case 1: + pdata->lb_mode = true; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int msm_anlg_cdc_pa_gain_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + u8 ear_pa_gain; + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + if (get_codec_version(sdm660_cdc) >= DIANGU) { + ear_pa_gain = snd_soc_read(codec, + MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC); + ear_pa_gain = (ear_pa_gain >> 1) & 0x3; + + if (ear_pa_gain == 0x00) { + ucontrol->value.integer.value[0] = 3; + } else if (ear_pa_gain == 0x01) { + ucontrol->value.integer.value[1] = 2; + } else if (ear_pa_gain == 0x02) { + ucontrol->value.integer.value[2] = 1; + } else if (ear_pa_gain == 0x03) { + ucontrol->value.integer.value[3] = 0; + } else { + dev_err(codec->dev, + "%s: ERROR: Unsupported Ear Gain = 0x%x\n", + __func__, ear_pa_gain); + return -EINVAL; + } + } else { + ear_pa_gain = snd_soc_read(codec, + MSM89XX_PMIC_ANALOG_RX_EAR_CTL); + ear_pa_gain = (ear_pa_gain >> 5) & 0x1; + if (ear_pa_gain == 0x00) { + ucontrol->value.integer.value[0] = 0; + } else if (ear_pa_gain == 0x01) { + ucontrol->value.integer.value[0] = 3; + } else { + dev_err(codec->dev, + "%s: ERROR: Unsupported Ear Gain = 0x%x\n", + __func__, ear_pa_gain); + return -EINVAL; + } + } + ucontrol->value.integer.value[0] = ear_pa_gain; + dev_dbg(codec->dev, "%s: ear_pa_gain = 0x%x\n", __func__, ear_pa_gain); + return 0; +} + +static int msm_anlg_cdc_pa_gain_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + u8 ear_pa_gain; + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", + __func__, ucontrol->value.integer.value[0]); + + if (get_codec_version(sdm660_cdc) >= DIANGU) { + switch (ucontrol->value.integer.value[0]) { + case 0: + ear_pa_gain = 0x06; + break; + case 1: + ear_pa_gain = 0x04; + break; + case 2: + ear_pa_gain = 0x02; + break; + case 3: + ear_pa_gain = 0x00; + break; + default: + return -EINVAL; + } + snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, + 0x06, ear_pa_gain); + } else { + switch (ucontrol->value.integer.value[0]) { + case 0: + ear_pa_gain = 0x00; + break; + case 3: + ear_pa_gain = 0x20; + break; + case 1: + case 2: + default: + return -EINVAL; + } + snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_EAR_CTL, + 0x20, ear_pa_gain); + } + return 0; +} + +static int msm_anlg_cdc_hph_mode_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + if (sdm660_cdc->hph_mode == NORMAL_MODE) { + ucontrol->value.integer.value[0] = 0; + } else if (sdm660_cdc->hph_mode == HD2_MODE) { + ucontrol->value.integer.value[0] = 1; + } else { + dev_err(codec->dev, "%s: ERROR: Default HPH Mode= %d\n", + __func__, sdm660_cdc->hph_mode); + } + + dev_dbg(codec->dev, "%s: sdm660_cdc->hph_mode = %d\n", __func__, + sdm660_cdc->hph_mode); + return 0; +} + +static int msm_anlg_cdc_hph_mode_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", + __func__, ucontrol->value.integer.value[0]); + + switch (ucontrol->value.integer.value[0]) { + case 0: + sdm660_cdc->hph_mode = NORMAL_MODE; + break; + case 1: + if (get_codec_version(sdm660_cdc) >= DIANGU) + sdm660_cdc->hph_mode = HD2_MODE; + break; + default: + sdm660_cdc->hph_mode = NORMAL_MODE; + break; + } + dev_dbg(codec->dev, "%s: sdm660_cdc->hph_mode_set = %d\n", + __func__, sdm660_cdc->hph_mode); + return 0; +} + +static int msm_anlg_cdc_boost_option_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + if (sdm660_cdc->boost_option == BOOST_SWITCH) { + ucontrol->value.integer.value[0] = 0; + } else if (sdm660_cdc->boost_option == BOOST_ALWAYS) { + ucontrol->value.integer.value[0] = 1; + } else if (sdm660_cdc->boost_option == BYPASS_ALWAYS) { + ucontrol->value.integer.value[0] = 2; + } else if (sdm660_cdc->boost_option == BOOST_ON_FOREVER) { + ucontrol->value.integer.value[0] = 3; + } else { + dev_err(codec->dev, "%s: ERROR: Unsupported Boost option= %d\n", + __func__, sdm660_cdc->boost_option); + return -EINVAL; + } + + dev_dbg(codec->dev, "%s: sdm660_cdc->boost_option = %d\n", __func__, + sdm660_cdc->boost_option); + return 0; +} + +static int msm_anlg_cdc_boost_option_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", + __func__, ucontrol->value.integer.value[0]); + + switch (ucontrol->value.integer.value[0]) { + case 0: + sdm660_cdc->boost_option = BOOST_SWITCH; + break; + case 1: + sdm660_cdc->boost_option = BOOST_ALWAYS; + break; + case 2: + sdm660_cdc->boost_option = BYPASS_ALWAYS; + msm_anlg_cdc_bypass_on(codec); + break; + case 3: + sdm660_cdc->boost_option = BOOST_ON_FOREVER; + msm_anlg_cdc_boost_on(codec); + break; + default: + pr_err("%s: invalid boost option: %d\n", __func__, + sdm660_cdc->boost_option); + return -EINVAL; + } + dev_dbg(codec->dev, "%s: sdm660_cdc->boost_option_set = %d\n", + __func__, sdm660_cdc->boost_option); + return 0; +} + +static int msm_anlg_cdc_spk_boost_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + if (sdm660_cdc->spk_boost_set == false) { + ucontrol->value.integer.value[0] = 0; + } else if (sdm660_cdc->spk_boost_set == true) { + ucontrol->value.integer.value[0] = 1; + } else { + dev_err(codec->dev, "%s: ERROR: Unsupported Speaker Boost = %d\n", + __func__, sdm660_cdc->spk_boost_set); + return -EINVAL; + } + + dev_dbg(codec->dev, "%s: sdm660_cdc->spk_boost_set = %d\n", __func__, + sdm660_cdc->spk_boost_set); + return 0; +} + +static int msm_anlg_cdc_spk_boost_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", + __func__, ucontrol->value.integer.value[0]); + + switch (ucontrol->value.integer.value[0]) { + case 0: + sdm660_cdc->spk_boost_set = false; + break; + case 1: + sdm660_cdc->spk_boost_set = true; + break; + default: + return -EINVAL; + } + dev_dbg(codec->dev, "%s: sdm660_cdc->spk_boost_set = %d\n", + __func__, sdm660_cdc->spk_boost_set); + return 0; +} + +static int msm_anlg_cdc_ext_spk_boost_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + if (sdm660_cdc->ext_spk_boost_set == false) + ucontrol->value.integer.value[0] = 0; + else + ucontrol->value.integer.value[0] = 1; + + dev_dbg(codec->dev, "%s: sdm660_cdc->ext_spk_boost_set = %d\n", + __func__, sdm660_cdc->ext_spk_boost_set); + return 0; +} + +static int msm_anlg_cdc_ext_spk_boost_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", + __func__, ucontrol->value.integer.value[0]); + + switch (ucontrol->value.integer.value[0]) { + case 0: + sdm660_cdc->ext_spk_boost_set = false; + break; + case 1: + sdm660_cdc->ext_spk_boost_set = true; + break; + default: + return -EINVAL; + } + dev_dbg(codec->dev, "%s: sdm660_cdc->spk_boost_set = %d\n", + __func__, sdm660_cdc->spk_boost_set); + return 0; +} + + +static const char * const msm_anlg_cdc_loopback_mode_ctrl_text[] = { + "DISABLE", "ENABLE"}; +static const struct soc_enum msm_anlg_cdc_loopback_mode_ctl_enum[] = { + SOC_ENUM_SINGLE_EXT(2, msm_anlg_cdc_loopback_mode_ctrl_text), +}; + +static const char * const msm_anlg_cdc_ear_pa_boost_ctrl_text[] = { + "DISABLE", "ENABLE"}; +static const struct soc_enum msm_anlg_cdc_ear_pa_boost_ctl_enum[] = { + SOC_ENUM_SINGLE_EXT(2, msm_anlg_cdc_ear_pa_boost_ctrl_text), +}; + +static const char * const msm_anlg_cdc_ear_pa_gain_text[] = { + "POS_1P5_DB", "POS_3_DB", "POS_4P5_DB", "POS_6_DB"}; +static const struct soc_enum msm_anlg_cdc_ear_pa_gain_enum[] = { + SOC_ENUM_SINGLE_EXT(4, msm_anlg_cdc_ear_pa_gain_text), +}; + +static const char * const msm_anlg_cdc_boost_option_ctrl_text[] = { + "BOOST_SWITCH", "BOOST_ALWAYS", "BYPASS_ALWAYS", + "BOOST_ON_FOREVER"}; +static const struct soc_enum msm_anlg_cdc_boost_option_ctl_enum[] = { + SOC_ENUM_SINGLE_EXT(4, msm_anlg_cdc_boost_option_ctrl_text), +}; +static const char * const msm_anlg_cdc_spk_boost_ctrl_text[] = { + "DISABLE", "ENABLE"}; +static const struct soc_enum msm_anlg_cdc_spk_boost_ctl_enum[] = { + SOC_ENUM_SINGLE_EXT(2, msm_anlg_cdc_spk_boost_ctrl_text), +}; + +static const char * const msm_anlg_cdc_ext_spk_boost_ctrl_text[] = { + "DISABLE", "ENABLE"}; +static const struct soc_enum msm_anlg_cdc_ext_spk_boost_ctl_enum[] = { + SOC_ENUM_SINGLE_EXT(2, msm_anlg_cdc_ext_spk_boost_ctrl_text), +}; + +static const char * const msm_anlg_cdc_hph_mode_ctrl_text[] = { + "NORMAL", "HD2"}; +static const struct soc_enum msm_anlg_cdc_hph_mode_ctl_enum[] = { + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(msm_anlg_cdc_hph_mode_ctrl_text), + msm_anlg_cdc_hph_mode_ctrl_text), +}; + +/*cut of frequency for high pass filter*/ +static const char * const cf_text[] = { + "MIN_3DB_4Hz", "MIN_3DB_75Hz", "MIN_3DB_150Hz" +}; + + +static const struct snd_kcontrol_new msm_anlg_cdc_snd_controls[] = { + + SOC_ENUM_EXT("RX HPH Mode", msm_anlg_cdc_hph_mode_ctl_enum[0], + msm_anlg_cdc_hph_mode_get, msm_anlg_cdc_hph_mode_set), + + SOC_ENUM_EXT("Boost Option", msm_anlg_cdc_boost_option_ctl_enum[0], + msm_anlg_cdc_boost_option_get, msm_anlg_cdc_boost_option_set), + + SOC_ENUM_EXT("EAR PA Boost", msm_anlg_cdc_ear_pa_boost_ctl_enum[0], + msm_anlg_cdc_ear_pa_boost_get, msm_anlg_cdc_ear_pa_boost_set), + + SOC_ENUM_EXT("EAR PA Gain", msm_anlg_cdc_ear_pa_gain_enum[0], + msm_anlg_cdc_pa_gain_get, msm_anlg_cdc_pa_gain_put), + + SOC_ENUM_EXT("Speaker Boost", msm_anlg_cdc_spk_boost_ctl_enum[0], + msm_anlg_cdc_spk_boost_get, msm_anlg_cdc_spk_boost_set), + + SOC_ENUM_EXT("Ext Spk Boost", msm_anlg_cdc_ext_spk_boost_ctl_enum[0], + msm_anlg_cdc_ext_spk_boost_get, msm_anlg_cdc_ext_spk_boost_set), + + SOC_ENUM_EXT("LOOPBACK Mode", msm_anlg_cdc_loopback_mode_ctl_enum[0], + msm_anlg_cdc_loopback_mode_get, msm_anlg_cdc_loopback_mode_put), + SOC_SINGLE_TLV("ADC1 Volume", MSM89XX_PMIC_ANALOG_TX_1_EN, 3, + 8, 0, analog_gain), + SOC_SINGLE_TLV("ADC2 Volume", MSM89XX_PMIC_ANALOG_TX_2_EN, 3, + 8, 0, analog_gain), + SOC_SINGLE_TLV("ADC3 Volume", MSM89XX_PMIC_ANALOG_TX_3_EN, 3, + 8, 0, analog_gain), + + +}; + +static int tombak_hph_impedance_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret; + uint32_t zl, zr; + bool hphr; + struct soc_multi_mixer_control *mc; + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct sdm660_cdc_priv *priv = snd_soc_codec_get_drvdata(codec); + + mc = (struct soc_multi_mixer_control *)(kcontrol->private_value); + + hphr = mc->shift; + ret = wcd_mbhc_get_impedance(&priv->mbhc, &zl, &zr); + if (ret) + dev_dbg(codec->dev, "%s: Failed to get mbhc imped", __func__); + dev_dbg(codec->dev, "%s: zl %u, zr %u\n", __func__, zl, zr); + ucontrol->value.integer.value[0] = hphr ? zr : zl; + + return 0; +} + +static const struct snd_kcontrol_new impedance_detect_controls[] = { + SOC_SINGLE_EXT("HPHL Impedance", 0, 0, UINT_MAX, 0, + tombak_hph_impedance_get, NULL), + SOC_SINGLE_EXT("HPHR Impedance", 0, 1, UINT_MAX, 0, + tombak_hph_impedance_get, NULL), +}; + +static int tombak_get_hph_type(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct sdm660_cdc_priv *priv = snd_soc_codec_get_drvdata(codec); + struct wcd_mbhc *mbhc; + + if (!priv) { + dev_err(codec->dev, + "%s: sdm660_cdc-wcd private data is NULL\n", + __func__); + return -EINVAL; + } + + mbhc = &priv->mbhc; + if (!mbhc) { + dev_err(codec->dev, "%s: mbhc not initialized\n", __func__); + return -EINVAL; + } + + ucontrol->value.integer.value[0] = (u32) mbhc->hph_type; + dev_dbg(codec->dev, "%s: hph_type = %u\n", __func__, mbhc->hph_type); + + return 0; +} + +static const struct snd_kcontrol_new hph_type_detect_controls[] = { + SOC_SINGLE_EXT("HPH Type", 0, 0, UINT_MAX, 0, + tombak_get_hph_type, NULL), +}; + +static const char * const rdac2_mux_text[] = { + "ZERO", "RX2", "RX1" +}; + +static const struct soc_enum rdac2_mux_enum = + SOC_ENUM_SINGLE(MSM89XX_PMIC_DIGITAL_CDC_CONN_HPHR_DAC_CTL, + 0, 3, rdac2_mux_text); + +static const char * const adc2_mux_text[] = { + "ZERO", "INP2", "INP3" +}; + +static const char * const ext_spk_text[] = { + "Off", "On" +}; + +static const char * const wsa_spk_text[] = { + "ZERO", "WSA" +}; + + + +static const char * const iir_inp1_text[] = { + "ZERO", "DEC1", "DEC2", "RX1", "RX2", "RX3" +}; + +static const struct soc_enum adc2_enum = + SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, + ARRAY_SIZE(adc2_mux_text), adc2_mux_text); + +static const struct soc_enum ext_spk_enum = + SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, + ARRAY_SIZE(ext_spk_text), ext_spk_text); + +static const struct soc_enum wsa_spk_enum = + SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, + ARRAY_SIZE(wsa_spk_text), wsa_spk_text); + + + +static const struct snd_kcontrol_new ext_spk_mux = + SOC_DAPM_ENUM("Ext Spk Switch Mux", ext_spk_enum); + + + +static const struct snd_kcontrol_new tx_adc2_mux = + SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum); + + +static const struct snd_kcontrol_new rdac2_mux = + SOC_DAPM_ENUM("RDAC2 MUX Mux", rdac2_mux_enum); + +static const char * const ear_text[] = { + "ZERO", "Switch", +}; + +static const struct soc_enum ear_enum = + SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(ear_text), ear_text); + +static const struct snd_kcontrol_new ear_pa_mux[] = { + SOC_DAPM_ENUM("EAR_S", ear_enum) +}; + +static const struct snd_kcontrol_new wsa_spk_mux[] = { + SOC_DAPM_ENUM("WSA Spk Switch", wsa_spk_enum) +}; + + + +static const char * const hph_text[] = { + "ZERO", "Switch", +}; + +static const struct soc_enum hph_enum = + SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(hph_text), hph_text); + +static const struct snd_kcontrol_new hphl_mux[] = { + SOC_DAPM_ENUM("HPHL", hph_enum) +}; + +static const struct snd_kcontrol_new hphr_mux[] = { + SOC_DAPM_ENUM("HPHR", hph_enum) +}; + +static const struct snd_kcontrol_new spkr_mux[] = { + SOC_DAPM_ENUM("SPK", hph_enum) +}; + +static const char * const lo_text[] = { + "ZERO", "Switch", +}; + +static const struct soc_enum lo_enum = + SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(hph_text), hph_text); + +static const struct snd_kcontrol_new lo_mux[] = { + SOC_DAPM_ENUM("LINE_OUT", lo_enum) +}; + +static void msm_anlg_cdc_codec_enable_adc_block(struct snd_soc_codec *codec, + int enable) +{ + struct sdm660_cdc_priv *wcd8x16 = snd_soc_codec_get_drvdata(codec); + + dev_dbg(codec->dev, "%s %d\n", __func__, enable); + + if (enable) { + wcd8x16->adc_count++; + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, + 0x20, 0x20); + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, + 0x10, 0x10); + } else { + wcd8x16->adc_count--; + if (!wcd8x16->adc_count) { + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, + 0x10, 0x00); + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, + 0x20, 0x0); + } + } +} + +static int msm_anlg_cdc_codec_enable_adc(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + u16 adc_reg; + u8 init_bit_shift; + + dev_dbg(codec->dev, "%s %d\n", __func__, event); + + adc_reg = MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_2; + + if (w->reg == MSM89XX_PMIC_ANALOG_TX_1_EN) + init_bit_shift = 5; + else if ((w->reg == MSM89XX_PMIC_ANALOG_TX_2_EN) || + (w->reg == MSM89XX_PMIC_ANALOG_TX_3_EN)) + init_bit_shift = 4; + else { + dev_err(codec->dev, "%s: Error, invalid adc register\n", + __func__); + return -EINVAL; + } + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + msm_anlg_cdc_codec_enable_adc_block(codec, 1); + if (w->reg == MSM89XX_PMIC_ANALOG_TX_2_EN) + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MICB_1_CTL, 0x02, 0x02); + /* + * Add delay of 10 ms to give sufficient time for the voltage + * to shoot up and settle so that the txfe init does not + * happen when the input voltage is changing too much. + */ + usleep_range(10000, 10010); + snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift, + 1 << init_bit_shift); + if (w->reg == MSM89XX_PMIC_ANALOG_TX_1_EN) + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_CONN_TX1_CTL, + 0x03, 0x00); + else if ((w->reg == MSM89XX_PMIC_ANALOG_TX_2_EN) || + (w->reg == MSM89XX_PMIC_ANALOG_TX_3_EN)) + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_CONN_TX2_CTL, + 0x03, 0x00); + /* Wait for 1ms to allow txfe settling time */ + usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS); + break; + case SND_SOC_DAPM_POST_PMU: + /* + * Add delay of 12 ms before deasserting the init + * to reduce the tx pop + */ + usleep_range(12000, 12010); + snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift, 0x00); + /* Wait for 1ms to allow txfe settling time post powerup */ + usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS); + break; + case SND_SOC_DAPM_POST_PMD: + msm_anlg_cdc_codec_enable_adc_block(codec, 0); + if (w->reg == MSM89XX_PMIC_ANALOG_TX_2_EN) + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MICB_1_CTL, 0x02, 0x00); + if (w->reg == MSM89XX_PMIC_ANALOG_TX_1_EN) + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_CONN_TX1_CTL, + 0x03, 0x02); + else if ((w->reg == MSM89XX_PMIC_ANALOG_TX_2_EN) || + (w->reg == MSM89XX_PMIC_ANALOG_TX_3_EN)) + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_CONN_TX2_CTL, + 0x03, 0x02); + + break; + } + return 0; +} + +static int msm_anlg_cdc_codec_enable_spk_pa(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + dev_dbg(codec->dev, "%s %d %s\n", __func__, event, w->name); + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, 0x01, 0x01); + switch (sdm660_cdc->boost_option) { + case BOOST_SWITCH: + if (!sdm660_cdc->spk_boost_set) + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, + 0x10, 0x10); + break; + case BOOST_ALWAYS: + case BOOST_ON_FOREVER: + break; + case BYPASS_ALWAYS: + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, + 0x10, 0x10); + break; + default: + dev_err(codec->dev, + "%s: invalid boost option: %d\n", __func__, + sdm660_cdc->boost_option); + break; + } + /* Wait for 1ms after SPK_DAC CTL setting */ + usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, 0xE0, 0xE0); + if (get_codec_version(sdm660_cdc) != TOMBAK_1_0) + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_EAR_CTL, 0x01, 0x01); + break; + case SND_SOC_DAPM_POST_PMU: + /* Wait for 1ms after SPK_VBAT_LDO Enable */ + usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS); + switch (sdm660_cdc->boost_option) { + case BOOST_SWITCH: + if (sdm660_cdc->spk_boost_set) + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, + 0xEF, 0xEF); + else + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, + 0x10, 0x00); + break; + case BOOST_ALWAYS: + case BOOST_ON_FOREVER: + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, + 0xEF, 0xEF); + break; + case BYPASS_ALWAYS: + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x10, 0x00); + break; + default: + dev_err(codec->dev, + "%s: invalid boost option: %d\n", __func__, + sdm660_cdc->boost_option); + break; + } + msm_anlg_cdc_dig_notifier_call(codec, + DIG_CDC_EVENT_RX3_MUTE_OFF); + snd_soc_update_bits(codec, w->reg, 0x80, 0x80); + break; + case SND_SOC_DAPM_PRE_PMD: + msm_anlg_cdc_dig_notifier_call(codec, + DIG_CDC_EVENT_RX3_MUTE_ON); + /* + * Add 1 ms sleep for the mute to take effect + */ + usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x10, 0x10); + if (get_codec_version(sdm660_cdc) < CAJON_2_0) + msm_anlg_cdc_boost_mode_sequence(codec, SPK_PMD); + snd_soc_update_bits(codec, w->reg, 0x80, 0x00); + switch (sdm660_cdc->boost_option) { + case BOOST_SWITCH: + if (sdm660_cdc->spk_boost_set) + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, + 0xEF, 0x69); + break; + case BOOST_ALWAYS: + case BOOST_ON_FOREVER: + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, + 0xEF, 0x69); + break; + case BYPASS_ALWAYS: + break; + default: + dev_err(codec->dev, + "%s: invalid boost option: %d\n", __func__, + sdm660_cdc->boost_option); + break; + } + break; + case SND_SOC_DAPM_POST_PMD: + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, 0xE0, 0x00); + /* Wait for 1ms to allow setting time for spkr path disable */ + usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, 0x01, 0x00); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x10, 0x00); + if (get_codec_version(sdm660_cdc) != TOMBAK_1_0) + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_EAR_CTL, 0x01, 0x00); + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00); + if (get_codec_version(sdm660_cdc) >= CAJON_2_0) + msm_anlg_cdc_boost_mode_sequence(codec, SPK_PMD); + break; + } + return 0; +} + +static int msm_anlg_cdc_codec_enable_dig_clk(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + struct msm_asoc_mach_data *pdata = NULL; + + pdata = snd_soc_card_get_drvdata(codec->component.card); + + dev_dbg(codec->dev, "%s event %d w->name %s\n", __func__, + event, w->name); + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + msm_anlg_cdc_codec_enable_clock_block(codec, 1); + snd_soc_update_bits(codec, w->reg, 0x80, 0x80); + break; + case SND_SOC_DAPM_POST_PMD: + if (sdm660_cdc->rx_bias_count == 0) + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, + 0x80, 0x00); + } + return 0; +} + + + +static bool msm_anlg_cdc_use_mb(struct snd_soc_codec *codec) +{ + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + if (get_codec_version(sdm660_cdc) < CAJON) + return true; + else + return false; +} + +static void msm_anlg_cdc_set_auto_zeroing(struct snd_soc_codec *codec, + bool enable) +{ + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + if (get_codec_version(sdm660_cdc) < CONGA) { + if (enable) + /* + * Set autozeroing for special headset detection and + * buttons to work. + */ + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MICB_2_EN, + 0x18, 0x10); + else + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MICB_2_EN, + 0x18, 0x00); + + } else { + dev_dbg(codec->dev, + "%s: Auto Zeroing is not required from CONGA\n", + __func__); + } +} + +static void msm_anlg_cdc_trim_btn_reg(struct snd_soc_codec *codec) +{ + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + if (get_codec_version(sdm660_cdc) == TOMBAK_1_0) { + pr_debug("%s: This device needs to be trimmed\n", __func__); + /* + * Calculate the trim value for each device used + * till is comes in production by hardware team + */ + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_SEC_ACCESS, + 0xA5, 0xA5); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_TRIM_CTRL2, + 0xFF, 0x30); + } else { + dev_dbg(codec->dev, "%s: This device is trimmed at ATE\n", + __func__); + } +} + +static int msm_anlg_cdc_enable_ext_mb_source(struct wcd_mbhc *wcd_mbhc, + bool turn_on) +{ + int ret = 0; + static int count; + struct snd_soc_codec *codec = wcd_mbhc->codec; + struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); + + dev_dbg(codec->dev, "%s turn_on: %d count: %d\n", __func__, turn_on, + count); + if (turn_on) { + if (!count) { + ret = snd_soc_dapm_force_enable_pin(dapm, + "MICBIAS_REGULATOR"); + snd_soc_dapm_sync(dapm); + } + count++; + } else { + if (count > 0) + count--; + if (!count) { + ret = snd_soc_dapm_disable_pin(dapm, + "MICBIAS_REGULATOR"); + snd_soc_dapm_sync(dapm); + } + } + + if (ret) + dev_err(codec->dev, "%s: Failed to %s external micbias source\n", + __func__, turn_on ? "enable" : "disabled"); + else + dev_dbg(codec->dev, "%s: %s external micbias source\n", + __func__, turn_on ? "Enabled" : "Disabled"); + + return ret; +} + +static int msm_anlg_cdc_codec_enable_micbias(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + u16 micb_int_reg; + char *internal1_text = "Internal1"; + char *internal2_text = "Internal2"; + char *internal3_text = "Internal3"; + char *external2_text = "External2"; + char *external_text = "External"; + bool micbias2; + + dev_dbg(codec->dev, "%s %d\n", __func__, event); + switch (w->reg) { + case MSM89XX_PMIC_ANALOG_MICB_1_EN: + case MSM89XX_PMIC_ANALOG_MICB_2_EN: + micb_int_reg = MSM89XX_PMIC_ANALOG_MICB_1_INT_RBIAS; + break; + default: + dev_err(codec->dev, + "%s: Error, invalid micbias register 0x%x\n", + __func__, w->reg); + return -EINVAL; + } + + micbias2 = (snd_soc_read(codec, MSM89XX_PMIC_ANALOG_MICB_2_EN) & 0x80); + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + if (strnstr(w->name, internal1_text, strlen(w->name))) { + if (get_codec_version(sdm660_cdc) >= CAJON) + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2, + 0x02, 0x02); + snd_soc_update_bits(codec, micb_int_reg, 0x80, 0x80); + } else if (strnstr(w->name, internal2_text, strlen(w->name))) { + snd_soc_update_bits(codec, micb_int_reg, 0x10, 0x10); + snd_soc_update_bits(codec, w->reg, 0x60, 0x00); + } else if (strnstr(w->name, internal3_text, strlen(w->name))) { + snd_soc_update_bits(codec, micb_int_reg, 0x2, 0x2); + /* + * update MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2 + * for external bias only, not for external2. + */ + } else if (!strnstr(w->name, external2_text, strlen(w->name)) && + strnstr(w->name, external_text, + strlen(w->name))) { + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2, + 0x02, 0x02); + } + if (!strnstr(w->name, external_text, strlen(w->name))) + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MICB_1_EN, 0x05, 0x04); + if (w->reg == MSM89XX_PMIC_ANALOG_MICB_1_EN) + msm_anlg_cdc_configure_cap(codec, true, micbias2); + + break; + case SND_SOC_DAPM_POST_PMU: + if (get_codec_version(sdm660_cdc) <= TOMBAK_2_0) + /* + * Wait for 20ms post micbias enable + * for version < tombak 2.0. + */ + usleep_range(20000, 20100); + if (strnstr(w->name, internal1_text, strlen(w->name))) { + snd_soc_update_bits(codec, micb_int_reg, 0x40, 0x40); + } else if (strnstr(w->name, internal2_text, strlen(w->name))) { + snd_soc_update_bits(codec, micb_int_reg, 0x08, 0x08); + msm_anlg_cdc_notifier_call(codec, + WCD_EVENT_POST_MICBIAS_2_ON); + } else if (strnstr(w->name, internal3_text, 30)) { + snd_soc_update_bits(codec, micb_int_reg, 0x01, 0x01); + } else if (strnstr(w->name, external2_text, strlen(w->name))) { + msm_anlg_cdc_notifier_call(codec, + WCD_EVENT_POST_MICBIAS_2_ON); + } + break; + case SND_SOC_DAPM_POST_PMD: + if (strnstr(w->name, internal1_text, strlen(w->name))) { + snd_soc_update_bits(codec, micb_int_reg, 0xC0, 0x40); + } else if (strnstr(w->name, internal2_text, strlen(w->name))) { + msm_anlg_cdc_notifier_call(codec, + WCD_EVENT_POST_MICBIAS_2_OFF); + } else if (strnstr(w->name, internal3_text, 30)) { + snd_soc_update_bits(codec, micb_int_reg, 0x2, 0x0); + } else if (strnstr(w->name, external2_text, strlen(w->name))) { + /* + * send micbias turn off event to mbhc driver and then + * break, as no need to set MICB_1_EN register. + */ + msm_anlg_cdc_notifier_call(codec, + WCD_EVENT_POST_MICBIAS_2_OFF); + break; + } + if (w->reg == MSM89XX_PMIC_ANALOG_MICB_1_EN) + msm_anlg_cdc_configure_cap(codec, false, micbias2); + break; + } + return 0; +} + +static void update_clkdiv(void *handle, int val) +{ + struct sdm660_cdc *handle_cdc = handle; + struct snd_soc_codec *codec = handle_cdc->codec; + + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_TX_1_2_TXFE_CLKDIV, + 0xFF, val); +} + +static int get_cdc_version(void *handle) +{ + struct sdm660_cdc *handle_cdc = handle; + struct snd_soc_codec *codec = handle_cdc->codec; + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + return get_codec_version(sdm660_cdc); +} + +static int sdm660_wcd_codec_enable_vdd_spkr(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + int ret = 0; + + if (!sdm660_cdc->ext_spk_boost_set) { + dev_dbg(codec->dev, "%s: ext_boost not supported/disabled\n", + __func__); + return 0; + } + dev_dbg(codec->dev, "%s: %s %d\n", __func__, w->name, event); + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + if (sdm660_cdc->spkdrv_reg) { + ret = regulator_enable(sdm660_cdc->spkdrv_reg); + if (ret) + dev_err(codec->dev, + "%s Failed to enable spkdrv reg %s\n", + __func__, MSM89XX_VDD_SPKDRV_NAME); + } + break; + case SND_SOC_DAPM_POST_PMD: + if (sdm660_cdc->spkdrv_reg) { + ret = regulator_disable(sdm660_cdc->spkdrv_reg); + if (ret) + dev_err(codec->dev, + "%s: Failed to disable spkdrv_reg %s\n", + __func__, MSM89XX_VDD_SPKDRV_NAME); + } + break; + } + return 0; +} + + +/* The register address is the same as other codec so it can use resmgr */ +static int msm_anlg_cdc_codec_enable_rx_bias(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + dev_dbg(codec->dev, "%s %d\n", __func__, event); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + sdm660_cdc->rx_bias_count++; + if (sdm660_cdc->rx_bias_count == 1) { + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, + 0x80, 0x80); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, + 0x01, 0x01); + } + break; + case SND_SOC_DAPM_POST_PMD: + sdm660_cdc->rx_bias_count--; + if (sdm660_cdc->rx_bias_count == 0) { + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, + 0x01, 0x00); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, + 0x80, 0x00); + } + break; + } + dev_dbg(codec->dev, "%s rx_bias_count = %d\n", + __func__, sdm660_cdc->rx_bias_count); + return 0; +} + +static uint32_t wcd_get_impedance_value(uint32_t imped) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(wcd_imped_val) - 1; i++) { + if (imped >= wcd_imped_val[i] && + imped < wcd_imped_val[i + 1]) + break; + } + + pr_debug("%s: selected impedance value = %d\n", + __func__, wcd_imped_val[i]); + return wcd_imped_val[i]; +} + +static void wcd_imped_config(struct snd_soc_codec *codec, + uint32_t imped, bool set_gain) +{ + uint32_t value; + int codec_version; + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + value = wcd_get_impedance_value(imped); + + if (value < wcd_imped_val[0]) { + dev_dbg(codec->dev, + "%s, detected impedance is less than 4 Ohm\n", + __func__); + return; + } + + codec_version = get_codec_version(sdm660_cdc); + + if (set_gain) { + switch (codec_version) { + case TOMBAK_1_0: + case TOMBAK_2_0: + case CONGA: + /* + * For 32Ohm load and higher loads, Set 0x19E + * bit 5 to 1 (POS_0_DB_DI). For loads lower + * than 32Ohm (such as 16Ohm load), Set 0x19E + * bit 5 to 0 (POS_M4P5_DB_DI) + */ + if (value >= 32) + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_EAR_CTL, + 0x20, 0x20); + else + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_EAR_CTL, + 0x20, 0x00); + break; + case CAJON: + case CAJON_2_0: + case DIANGU: + case DRAX_CDC: + if (value >= 13) { + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_EAR_CTL, + 0x20, 0x20); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_NCP_VCTRL, + 0x07, 0x07); + } else { + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_EAR_CTL, + 0x20, 0x00); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_NCP_VCTRL, + 0x07, 0x04); + } + break; + } + } else { + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_EAR_CTL, + 0x20, 0x00); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_NCP_VCTRL, + 0x07, 0x04); + } + + dev_dbg(codec->dev, "%s: Exit\n", __func__); +} + +static int msm_anlg_cdc_hphl_dac_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + uint32_t impedl, impedr; + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + int ret; + + dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event); + ret = wcd_mbhc_get_impedance(&sdm660_cdc->mbhc, + &impedl, &impedr); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + if (get_codec_version(sdm660_cdc) > CAJON) + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, + 0x08, 0x08); + if (get_codec_version(sdm660_cdc) == CAJON || + get_codec_version(sdm660_cdc) == CAJON_2_0) { + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST, + 0x80, 0x80); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST, + 0x80, 0x80); + } + if (get_codec_version(sdm660_cdc) > CAJON) + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, + 0x08, 0x00); + if (sdm660_cdc->hph_mode == HD2_MODE) + msm_anlg_cdc_dig_notifier_call(codec, + DIG_CDC_EVENT_PRE_RX1_INT_ON); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL, 0x02, 0x02); + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01); + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02); + if (!ret) + wcd_imped_config(codec, impedl, true); + else + dev_dbg(codec->dev, "Failed to get mbhc impedance %d\n", + ret); + break; + case SND_SOC_DAPM_POST_PMU: + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL, 0x02, 0x00); + break; + case SND_SOC_DAPM_POST_PMD: + wcd_imped_config(codec, impedl, false); + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00); + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x00); + if (sdm660_cdc->hph_mode == HD2_MODE) + msm_anlg_cdc_dig_notifier_call(codec, + DIG_CDC_EVENT_POST_RX1_INT_OFF); + break; + } + return 0; +} + +static int msm_anlg_cdc_lo_dac_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + + dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL, 0x20, 0x20); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL, 0x80, 0x80); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x08, 0x08); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x40, 0x40); + break; + case SND_SOC_DAPM_POST_PMU: + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x80, 0x80); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x08, 0x00); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL, 0x40, 0x40); + break; + case SND_SOC_DAPM_POST_PMD: + /* Wait for 20ms before powerdown of lineout_dac */ + usleep_range(20000, 20100); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x80, 0x00); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x40, 0x00); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x08, 0x00); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL, 0x80, 0x00); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL, 0x40, 0x00); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL, 0x20, 0x00); + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00); + break; + } + return 0; +} + +static int msm_anlg_cdc_hphr_dac_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + if (sdm660_cdc->hph_mode == HD2_MODE) + msm_anlg_cdc_dig_notifier_call(codec, + DIG_CDC_EVENT_PRE_RX2_INT_ON); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL, 0x02, 0x02); + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02); + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01); + break; + case SND_SOC_DAPM_POST_PMU: + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL, 0x02, 0x00); + break; + case SND_SOC_DAPM_POST_PMD: + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00); + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x00); + if (sdm660_cdc->hph_mode == HD2_MODE) + msm_anlg_cdc_dig_notifier_call(codec, + DIG_CDC_EVENT_POST_RX2_INT_OFF); + break; + } + return 0; +} + +static int msm_anlg_cdc_hph_pa_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + dev_dbg(codec->dev, "%s: %s event = %d\n", __func__, w->name, event); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + if (w->shift == 5) + msm_anlg_cdc_notifier_call(codec, + WCD_EVENT_PRE_HPHL_PA_ON); + else if (w->shift == 4) + msm_anlg_cdc_notifier_call(codec, + WCD_EVENT_PRE_HPHR_PA_ON); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_NCP_FBCTRL, 0x20, 0x20); + break; + + case SND_SOC_DAPM_POST_PMU: + /* Wait for 7ms to allow setting time for HPH_PA Enable */ + usleep_range(7000, 7100); + if (w->shift == 5) { + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST, 0x04, 0x04); + msm_anlg_cdc_dig_notifier_call(codec, + DIG_CDC_EVENT_RX1_MUTE_OFF); + } else if (w->shift == 4) { + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST, 0x04, 0x04); + msm_anlg_cdc_dig_notifier_call(codec, + DIG_CDC_EVENT_RX2_MUTE_OFF); + } + break; + + case SND_SOC_DAPM_PRE_PMD: + if (w->shift == 5) { + msm_anlg_cdc_dig_notifier_call(codec, + DIG_CDC_EVENT_RX1_MUTE_ON); + /* Wait for 20ms after HPHL RX digital mute */ + msleep(20); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST, 0x04, 0x00); + msm_anlg_cdc_notifier_call(codec, + WCD_EVENT_PRE_HPHL_PA_OFF); + } else if (w->shift == 4) { + msm_anlg_cdc_dig_notifier_call(codec, + DIG_CDC_EVENT_RX2_MUTE_ON); + /* Wait for 20ms after HPHR RX digital mute */ + msleep(20); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST, 0x04, 0x00); + msm_anlg_cdc_notifier_call(codec, + WCD_EVENT_PRE_HPHR_PA_OFF); + } + if (get_codec_version(sdm660_cdc) >= CAJON) { + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_CNP, + 0xF0, 0x30); + } + break; + case SND_SOC_DAPM_POST_PMD: + if (w->shift == 5) { + clear_bit(WCD_MBHC_HPHL_PA_OFF_ACK, + &sdm660_cdc->mbhc.hph_pa_dac_state); + msm_anlg_cdc_notifier_call(codec, + WCD_EVENT_POST_HPHL_PA_OFF); + } else if (w->shift == 4) { + clear_bit(WCD_MBHC_HPHR_PA_OFF_ACK, + &sdm660_cdc->mbhc.hph_pa_dac_state); + msm_anlg_cdc_notifier_call(codec, + WCD_EVENT_POST_HPHR_PA_OFF); + } + /* Wait for 15ms after HPH RX teardown */ + usleep_range(15000, 15100); + break; + } + return 0; +} + +static const struct snd_soc_dapm_route audio_map[] = { + /* RDAC Connections */ + {"HPHR DAC", NULL, "RDAC2 MUX"}, + {"RDAC2 MUX", "RX1", "PDM_IN_RX1"}, + {"RDAC2 MUX", "RX2", "PDM_IN_RX2"}, + + /* WSA */ + {"WSA_SPK OUT", NULL, "WSA Spk Switch"}, + {"WSA Spk Switch", "WSA", "EAR PA"}, + + /* Earpiece (RX MIX1) */ + {"EAR", NULL, "EAR_S"}, + {"EAR_S", "Switch", "EAR PA"}, + {"EAR PA", NULL, "RX_BIAS"}, + {"EAR PA", NULL, "HPHL DAC"}, + {"EAR PA", NULL, "HPHR DAC"}, + {"EAR PA", NULL, "EAR CP"}, + + /* Headset (RX MIX1 and RX MIX2) */ + {"HEADPHONE", NULL, "HPHL PA"}, + {"HEADPHONE", NULL, "HPHR PA"}, + + {"Ext Spk", NULL, "Ext Spk Switch"}, + {"Ext Spk Switch", "On", "HPHL PA"}, + {"Ext Spk Switch", "On", "HPHR PA"}, + + {"HPHL PA", NULL, "HPHL"}, + {"HPHR PA", NULL, "HPHR"}, + {"HPHL", "Switch", "HPHL DAC"}, + {"HPHR", "Switch", "HPHR DAC"}, + {"HPHL PA", NULL, "CP"}, + {"HPHL PA", NULL, "RX_BIAS"}, + {"HPHR PA", NULL, "CP"}, + {"HPHR PA", NULL, "RX_BIAS"}, + {"HPHL DAC", NULL, "PDM_IN_RX1"}, + + {"SPK_OUT", NULL, "SPK PA"}, + {"SPK PA", NULL, "SPK_RX_BIAS"}, + {"SPK PA", NULL, "SPK"}, + {"SPK", "Switch", "SPK DAC"}, + {"SPK DAC", NULL, "PDM_IN_RX3"}, + {"SPK DAC", NULL, "VDD_SPKDRV"}, + + /* lineout */ + {"LINEOUT", NULL, "LINEOUT PA"}, + {"LINEOUT PA", NULL, "SPK_RX_BIAS"}, + {"LINEOUT PA", NULL, "LINE_OUT"}, + {"LINE_OUT", "Switch", "LINEOUT DAC"}, + {"LINEOUT DAC", NULL, "PDM_IN_RX3"}, + + /* lineout to WSA */ + {"WSA_SPK OUT", NULL, "LINEOUT PA"}, + + {"PDM_IN_RX1", NULL, "RX1 CLK"}, + {"PDM_IN_RX2", NULL, "RX2 CLK"}, + {"PDM_IN_RX3", NULL, "RX3 CLK"}, + + {"ADC1_OUT", NULL, "ADC1"}, + {"ADC2_OUT", NULL, "ADC2"}, + {"ADC3_OUT", NULL, "ADC3"}, + + /* ADC Connections */ + {"ADC2", NULL, "ADC2 MUX"}, + {"ADC3", NULL, "ADC2 MUX"}, + {"ADC2 MUX", "INP2", "ADC2_INP2"}, + {"ADC2 MUX", "INP3", "ADC2_INP3"}, + + {"ADC1", NULL, "AMIC1"}, + {"ADC2_INP2", NULL, "AMIC2"}, + {"ADC2_INP3", NULL, "AMIC3"}, + + {"MIC BIAS Internal1", NULL, "INT_LDO_H"}, + {"MIC BIAS Internal2", NULL, "INT_LDO_H"}, + {"MIC BIAS External", NULL, "INT_LDO_H"}, + {"MIC BIAS External2", NULL, "INT_LDO_H"}, + {"MIC BIAS Internal1", NULL, "MICBIAS_REGULATOR"}, + {"MIC BIAS Internal2", NULL, "MICBIAS_REGULATOR"}, + {"MIC BIAS External", NULL, "MICBIAS_REGULATOR"}, + {"MIC BIAS External2", NULL, "MICBIAS_REGULATOR"}, +}; + +static int msm_anlg_cdc_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(dai->codec); + + dev_dbg(dai->codec->dev, "%s(): substream = %s stream = %d\n", + __func__, + substream->name, substream->stream); + /* + * If status_mask is BUS_DOWN it means SSR is not complete. + * So return error. + */ + if (test_bit(BUS_DOWN, &sdm660_cdc->status_mask)) { + dev_err(dai->codec->dev, "Error, Device is not up post SSR\n"); + return -EINVAL; + } + return 0; +} + +static void msm_anlg_cdc_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + dev_dbg(dai->codec->dev, + "%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); +} + +int msm_anlg_cdc_mclk_enable(struct snd_soc_codec *codec, + int mclk_enable, bool dapm) +{ + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + dev_dbg(codec->dev, "%s: mclk_enable = %u, dapm = %d\n", + __func__, mclk_enable, dapm); + if (mclk_enable) { + sdm660_cdc->int_mclk0_enabled = true; + msm_anlg_cdc_codec_enable_clock_block(codec, 1); + } else { + if (!sdm660_cdc->int_mclk0_enabled) { + dev_err(codec->dev, "Error, MCLK already diabled\n"); + return -EINVAL; + } + sdm660_cdc->int_mclk0_enabled = false; + msm_anlg_cdc_codec_enable_clock_block(codec, 0); + } + return 0; +} + +static int msm_anlg_cdc_set_dai_sysclk(struct snd_soc_dai *dai, + int clk_id, unsigned int freq, int dir) +{ + dev_dbg(dai->codec->dev, "%s\n", __func__); + return 0; +} + +static int msm_anlg_cdc_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ + dev_dbg(dai->codec->dev, "%s\n", __func__); + return 0; +} + +static int msm_anlg_cdc_set_channel_map(struct snd_soc_dai *dai, + unsigned int tx_num, unsigned int *tx_slot, + unsigned int rx_num, unsigned int *rx_slot) + +{ + dev_dbg(dai->codec->dev, "%s\n", __func__); + return 0; +} + +static int msm_anlg_cdc_get_channel_map(struct snd_soc_dai *dai, + unsigned int *tx_num, unsigned int *tx_slot, + unsigned int *rx_num, unsigned int *rx_slot) + +{ + dev_dbg(dai->codec->dev, "%s\n", __func__); + return 0; +} + +static struct snd_soc_dai_ops msm_anlg_cdc_dai_ops = { + .startup = msm_anlg_cdc_startup, + .shutdown = msm_anlg_cdc_shutdown, + .set_sysclk = msm_anlg_cdc_set_dai_sysclk, + .set_fmt = msm_anlg_cdc_set_dai_fmt, + .set_channel_map = msm_anlg_cdc_set_channel_map, + .get_channel_map = msm_anlg_cdc_get_channel_map, +}; + +static struct snd_soc_dai_driver msm_anlg_cdc_i2s_dai[] = { + { + .name = "msm_anlg_cdc_i2s_rx1", + .id = AIF1_PB, + .playback = { + .stream_name = "Playback", + .rates = SDM660_CDC_RATES, + .formats = SDM660_CDC_FORMATS, + .rate_max = 192000, + .rate_min = 8000, + .channels_min = 1, + .channels_max = 3, + }, + .ops = &msm_anlg_cdc_dai_ops, + }, + { + .name = "msm_anlg_cdc_i2s_tx1", + .id = AIF1_CAP, + .capture = { + .stream_name = "Record", + .rates = SDM660_CDC_RATES, + .formats = SDM660_CDC_FORMATS, + .rate_max = 48000, + .rate_min = 8000, + .channels_min = 1, + .channels_max = 4, + }, + .ops = &msm_anlg_cdc_dai_ops, + }, + { + .name = "msm_anlg_cdc_i2s_tx2", + .id = AIF3_SVA, + .capture = { + .stream_name = "RecordSVA", + .rates = SDM660_CDC_RATES, + .formats = SDM660_CDC_FORMATS, + .rate_max = 48000, + .rate_min = 8000, + .channels_min = 1, + .channels_max = 2, + }, + .ops = &msm_anlg_cdc_dai_ops, + }, + { + .name = "msm_anlg_vifeedback", + .id = AIF2_VIFEED, + .capture = { + .stream_name = "VIfeed", + .rates = SDM660_CDC_RATES, + .formats = SDM660_CDC_FORMATS, + .rate_max = 48000, + .rate_min = 48000, + .channels_min = 2, + .channels_max = 2, + }, + .ops = &msm_anlg_cdc_dai_ops, + }, +}; + + +static int msm_anlg_cdc_codec_enable_lo_pa(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + + dev_dbg(codec->dev, "%s: %d %s\n", __func__, event, w->name); + switch (event) { + case SND_SOC_DAPM_POST_PMU: + msm_anlg_cdc_dig_notifier_call(codec, + DIG_CDC_EVENT_RX3_MUTE_OFF); + break; + case SND_SOC_DAPM_POST_PMD: + msm_anlg_cdc_dig_notifier_call(codec, + DIG_CDC_EVENT_RX3_MUTE_ON); + break; + } + + return 0; +} + +static int msm_anlg_cdc_codec_enable_spk_ext_pa(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + dev_dbg(codec->dev, "%s: %s event = %d\n", __func__, w->name, event); + switch (event) { + case SND_SOC_DAPM_POST_PMU: + dev_dbg(codec->dev, + "%s: enable external speaker PA\n", __func__); + if (sdm660_cdc->codec_spk_ext_pa_cb) + sdm660_cdc->codec_spk_ext_pa_cb(codec, 1); + break; + case SND_SOC_DAPM_PRE_PMD: + dev_dbg(codec->dev, + "%s: enable external speaker PA\n", __func__); + if (sdm660_cdc->codec_spk_ext_pa_cb) + sdm660_cdc->codec_spk_ext_pa_cb(codec, 0); + break; + } + return 0; +} + +static int msm_anlg_cdc_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + dev_dbg(codec->dev, + "%s: Sleeping 20ms after select EAR PA\n", + __func__); + snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_EAR_CTL, + 0x80, 0x80); + if (get_codec_version(sdm660_cdc) < CONGA) + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME, 0xFF, 0x2A); + if (get_codec_version(sdm660_cdc) >= DIANGU) { + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, 0x08, 0x00); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST, 0x04, 0x04); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST, 0x04, 0x04); + } + break; + case SND_SOC_DAPM_POST_PMU: + dev_dbg(codec->dev, + "%s: Sleeping 20ms after enabling EAR PA\n", + __func__); + snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_EAR_CTL, + 0x40, 0x40); + /* Wait for 7ms after EAR PA enable */ + usleep_range(7000, 7100); + msm_anlg_cdc_dig_notifier_call(codec, + DIG_CDC_EVENT_RX1_MUTE_OFF); + break; + case SND_SOC_DAPM_PRE_PMD: + msm_anlg_cdc_dig_notifier_call(codec, + DIG_CDC_EVENT_RX1_MUTE_ON); + /* Wait for 20ms for RX digital mute to take effect */ + msleep(20); + if (sdm660_cdc->boost_option == BOOST_ALWAYS) { + dev_dbg(codec->dev, + "%s: boost_option:%d, tear down ear\n", + __func__, sdm660_cdc->boost_option); + msm_anlg_cdc_boost_mode_sequence(codec, EAR_PMD); + } + if (get_codec_version(sdm660_cdc) >= DIANGU) { + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST, 0x04, 0x0); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST, 0x04, 0x0); + } + break; + case SND_SOC_DAPM_POST_PMD: + dev_dbg(codec->dev, + "%s: Sleeping 7ms after disabling EAR PA\n", + __func__); + snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_EAR_CTL, + 0x40, 0x00); + /* Wait for 7ms after EAR PA teardown */ + usleep_range(7000, 7100); + if (get_codec_version(sdm660_cdc) < CONGA) + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME, 0xFF, 0x16); + if (get_codec_version(sdm660_cdc) >= DIANGU) + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, 0x08, 0x08); + break; + } + return 0; +} + +static const struct snd_soc_dapm_widget msm_anlg_cdc_dapm_widgets[] = { + SND_SOC_DAPM_PGA_E("EAR PA", SND_SOC_NOPM, + 0, 0, NULL, 0, msm_anlg_cdc_codec_enable_ear_pa, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_PGA_E("HPHL PA", MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, + 5, 0, NULL, 0, + msm_anlg_cdc_hph_pa_event, SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD | + SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_PGA_E("HPHR PA", MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, + 4, 0, NULL, 0, + msm_anlg_cdc_hph_pa_event, SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD | + SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_PGA_E("SPK PA", SND_SOC_NOPM, + 0, 0, NULL, 0, msm_anlg_cdc_codec_enable_spk_pa, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_PGA_E("LINEOUT PA", MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL, + 5, 0, NULL, 0, msm_anlg_cdc_codec_enable_lo_pa, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MUX("EAR_S", SND_SOC_NOPM, 0, 0, ear_pa_mux), + SND_SOC_DAPM_MUX("SPK", SND_SOC_NOPM, 0, 0, spkr_mux), + SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, hphl_mux), + SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, hphr_mux), + SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux), + SND_SOC_DAPM_MUX("WSA Spk Switch", SND_SOC_NOPM, 0, 0, wsa_spk_mux), + SND_SOC_DAPM_MUX("Ext Spk Switch", SND_SOC_NOPM, 0, 0, &ext_spk_mux), + SND_SOC_DAPM_MUX("LINE_OUT", SND_SOC_NOPM, 0, 0, lo_mux), + SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), + + SND_SOC_DAPM_MIXER_E("HPHL DAC", + MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL, + 0, msm_anlg_cdc_hphl_dac_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_MIXER_E("HPHR DAC", + MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL, + 0, msm_anlg_cdc_hphr_dac_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), + + SND_SOC_DAPM_DAC("SPK DAC", NULL, MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, + 7, 0), + SND_SOC_DAPM_DAC_E("LINEOUT DAC", NULL, + SND_SOC_NOPM, 0, 0, msm_anlg_cdc_lo_dac_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_SPK("Ext Spk", msm_anlg_cdc_codec_enable_spk_ext_pa), + + SND_SOC_DAPM_SUPPLY("RX1 CLK", MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, + 0, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("RX2 CLK", MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, + 1, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("RX3 CLK", MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, + 2, 0, msm_anlg_cdc_codec_enable_dig_clk, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY("CP", MSM89XX_PMIC_ANALOG_NCP_EN, 0, 0, + msm_anlg_cdc_codec_enable_charge_pump, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY("EAR CP", MSM89XX_PMIC_ANALOG_NCP_EN, 4, 0, + msm_anlg_cdc_codec_enable_charge_pump, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S("RX_BIAS", 1, SND_SOC_NOPM, + 0, 0, msm_anlg_cdc_codec_enable_rx_bias, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY_S("SPK_RX_BIAS", 1, SND_SOC_NOPM, 0, 0, + msm_anlg_cdc_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY("VDD_SPKDRV", SND_SOC_NOPM, 0, 0, + sdm660_wcd_codec_enable_vdd_spkr, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("MICBIAS_REGULATOR", SND_SOC_NOPM, + ON_DEMAND_MICBIAS, 0, + msm_anlg_cdc_codec_enable_on_demand_supply, + SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MICBIAS_E("MIC BIAS Internal1", + MSM89XX_PMIC_ANALOG_MICB_1_EN, 7, 0, + msm_anlg_cdc_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_MICBIAS_E("MIC BIAS Internal2", + MSM89XX_PMIC_ANALOG_MICB_2_EN, 7, 0, + msm_anlg_cdc_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_MICBIAS_E("MIC BIAS Internal3", + MSM89XX_PMIC_ANALOG_MICB_1_EN, 7, 0, + msm_anlg_cdc_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_ADC_E("ADC1", NULL, MSM89XX_PMIC_ANALOG_TX_1_EN, 7, 0, + msm_anlg_cdc_codec_enable_adc, SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_ADC_E("ADC2_INP2", + NULL, MSM89XX_PMIC_ANALOG_TX_2_EN, 7, 0, + msm_anlg_cdc_codec_enable_adc, SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_ADC_E("ADC2_INP3", + NULL, MSM89XX_PMIC_ANALOG_TX_3_EN, 7, 0, + msm_anlg_cdc_codec_enable_adc, SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MICBIAS_E("MIC BIAS External", + MSM89XX_PMIC_ANALOG_MICB_1_EN, 7, 0, + msm_anlg_cdc_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_MICBIAS_E("MIC BIAS External2", + MSM89XX_PMIC_ANALOG_MICB_2_EN, 7, 0, + msm_anlg_cdc_codec_enable_micbias, SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_INPUT("AMIC1"), + SND_SOC_DAPM_INPUT("AMIC2"), + SND_SOC_DAPM_INPUT("AMIC3"), + SND_SOC_DAPM_INPUT("PDM_IN_RX1"), + SND_SOC_DAPM_INPUT("PDM_IN_RX2"), + SND_SOC_DAPM_INPUT("PDM_IN_RX3"), + + SND_SOC_DAPM_OUTPUT("EAR"), + SND_SOC_DAPM_OUTPUT("WSA_SPK OUT"), + SND_SOC_DAPM_OUTPUT("HEADPHONE"), + SND_SOC_DAPM_OUTPUT("SPK_OUT"), + SND_SOC_DAPM_OUTPUT("LINEOUT"), + SND_SOC_DAPM_OUTPUT("ADC1_OUT"), + SND_SOC_DAPM_OUTPUT("ADC2_OUT"), + SND_SOC_DAPM_OUTPUT("ADC3_OUT"), +}; + +static const struct sdm660_cdc_reg_mask_val msm_anlg_cdc_reg_defaults[] = { + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x03), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0x82), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL, 0xE1), +}; + +static const struct sdm660_cdc_reg_mask_val + msm_anlg_cdc_reg_defaults_2_0[] = { + MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_SEC_ACCESS, 0xA5), + MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x0F), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS, 0x4F), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_NCP_FBCTRL, 0x28), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, 0x69), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG, 0x01), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_BOOST_EN_CTL, 0x5F), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SLOPE_COMP_IP_ZERO, 0x88), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0xA5), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3, 0x0F), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0x82), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x03), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL, 0xE1), + MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x80), +}; + +static const struct sdm660_cdc_reg_mask_val conga_wcd_reg_defaults[] = { + MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_SEC_ACCESS, 0xA5), + MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x0F), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0xA5), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3, 0x0F), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS, 0x4C), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_NCP_FBCTRL, 0x28), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, 0x69), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG, 0x01), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_PERPH_SUBTYPE, 0x0A), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x03), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL, 0xE1), + MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x80), +}; + +static const struct sdm660_cdc_reg_mask_val cajon_wcd_reg_defaults[] = { + MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_SEC_ACCESS, 0xA5), + MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x0F), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0xA5), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3, 0x0F), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS, 0x4C), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0x82), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_NCP_FBCTRL, 0xA8), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_NCP_VCTRL, 0xA4), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_ANA_BIAS_SET, 0x41), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, 0x69), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG, 0x01), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL, 0xE1), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x03), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_PA, 0xFA), + MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x80), +}; + +static const struct sdm660_cdc_reg_mask_val cajon2p0_wcd_reg_defaults[] = { + MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_SEC_ACCESS, 0xA5), + MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x0F), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0xA5), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3, 0x0F), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS, 0x4C), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0xA2), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_NCP_FBCTRL, 0xA8), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_NCP_VCTRL, 0xA4), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_ANA_BIAS_SET, 0x41), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, 0x69), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG, 0x01), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL, 0xE1), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x03), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_RX_EAR_STATUS, 0x10), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_BYPASS_MODE, 0x18), + MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_PA, 0xFA), + MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x80), +}; + +static void msm_anlg_cdc_update_reg_defaults(struct snd_soc_codec *codec) +{ + u32 i, version; + struct sdm660_cdc_priv *sdm660_cdc = + snd_soc_codec_get_drvdata(codec); + + version = get_codec_version(sdm660_cdc); + if (version == TOMBAK_1_0) { + for (i = 0; i < ARRAY_SIZE(msm_anlg_cdc_reg_defaults); i++) + snd_soc_write(codec, msm_anlg_cdc_reg_defaults[i].reg, + msm_anlg_cdc_reg_defaults[i].val); + } else if (version == TOMBAK_2_0) { + for (i = 0; i < ARRAY_SIZE(msm_anlg_cdc_reg_defaults_2_0); i++) + snd_soc_write(codec, + msm_anlg_cdc_reg_defaults_2_0[i].reg, + msm_anlg_cdc_reg_defaults_2_0[i].val); + } else if (version == CONGA) { + for (i = 0; i < ARRAY_SIZE(conga_wcd_reg_defaults); i++) + snd_soc_write(codec, + conga_wcd_reg_defaults[i].reg, + conga_wcd_reg_defaults[i].val); + } else if (version == CAJON) { + for (i = 0; i < ARRAY_SIZE(cajon_wcd_reg_defaults); i++) + snd_soc_write(codec, + cajon_wcd_reg_defaults[i].reg, + cajon_wcd_reg_defaults[i].val); + } else if (version == CAJON_2_0 || version == DIANGU + || version == DRAX_CDC) { + for (i = 0; i < ARRAY_SIZE(cajon2p0_wcd_reg_defaults); i++) + snd_soc_write(codec, + cajon2p0_wcd_reg_defaults[i].reg, + cajon2p0_wcd_reg_defaults[i].val); + } +} + +static const struct sdm660_cdc_reg_mask_val + msm_anlg_cdc_codec_reg_init_val[] = { + + /* Initialize current threshold to 350MA + * number of wait and run cycles to 4096 + */ + {MSM89XX_PMIC_ANALOG_RX_COM_OCP_CTL, 0xFF, 0x12}, + {MSM89XX_PMIC_ANALOG_RX_COM_OCP_COUNT, 0xFF, 0xFF}, +}; + +static void msm_anlg_cdc_codec_init_cache(struct snd_soc_codec *codec) +{ + u32 i; + + regcache_cache_only(codec->component.regmap, true); + /* update cache with POR values */ + for (i = 0; i < ARRAY_SIZE(msm89xx_pmic_cdc_defaults); i++) + snd_soc_write(codec, msm89xx_pmic_cdc_defaults[i].reg, + msm89xx_pmic_cdc_defaults[i].def); + regcache_cache_only(codec->component.regmap, false); +} + +static void msm_anlg_cdc_codec_init_reg(struct snd_soc_codec *codec) +{ + u32 i; + + for (i = 0; i < ARRAY_SIZE(msm_anlg_cdc_codec_reg_init_val); i++) + snd_soc_update_bits(codec, + msm_anlg_cdc_codec_reg_init_val[i].reg, + msm_anlg_cdc_codec_reg_init_val[i].mask, + msm_anlg_cdc_codec_reg_init_val[i].val); +} + +static int msm_anlg_cdc_bringup(struct snd_soc_codec *codec) +{ + snd_soc_write(codec, + MSM89XX_PMIC_DIGITAL_SEC_ACCESS, + 0xA5); + snd_soc_write(codec, MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL4, 0x01); + snd_soc_write(codec, + MSM89XX_PMIC_ANALOG_SEC_ACCESS, + 0xA5); + snd_soc_write(codec, MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL4, 0x01); + snd_soc_write(codec, + MSM89XX_PMIC_DIGITAL_SEC_ACCESS, + 0xA5); + snd_soc_write(codec, MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL4, 0x00); + snd_soc_write(codec, + MSM89XX_PMIC_ANALOG_SEC_ACCESS, + 0xA5); + snd_soc_write(codec, MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL4, 0x00); + return 0; +} + +static struct regulator *msm_anlg_cdc_find_regulator( + const struct sdm660_cdc *sdm660_cdc, + const char *name) +{ + int i; + + for (i = 0; i < sdm660_cdc->num_of_supplies; i++) { + if (sdm660_cdc->supplies[i].supply && + !strcmp(sdm660_cdc->supplies[i].supply, name)) + return sdm660_cdc->supplies[i].consumer; + } + + dev_err(sdm660_cdc->dev, "Error: regulator not found:%s\n" + , name); + return NULL; +} + +static int msm_anlg_cdc_device_down(struct snd_soc_codec *codec) +{ + struct msm_asoc_mach_data *pdata = NULL; + struct sdm660_cdc_priv *sdm660_cdc_priv = + snd_soc_codec_get_drvdata(codec); + unsigned int tx_1_en; + unsigned int tx_2_en; + + pdata = snd_soc_card_get_drvdata(codec->component.card); + dev_dbg(codec->dev, "%s: device down!\n", __func__); + + tx_1_en = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_TX_1_EN); + tx_2_en = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_TX_2_EN); + tx_1_en = tx_1_en & 0x7f; + tx_2_en = tx_2_en & 0x7f; + snd_soc_write(codec, + MSM89XX_PMIC_ANALOG_TX_1_EN, tx_1_en); + snd_soc_write(codec, + MSM89XX_PMIC_ANALOG_TX_2_EN, tx_2_en); + if (sdm660_cdc_priv->boost_option == BOOST_ON_FOREVER) { + if ((snd_soc_read(codec, MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL) + & 0x80) == 0) { + msm_anlg_cdc_dig_notifier_call(codec, + DIG_CDC_EVENT_CLK_ON); + snd_soc_write(codec, + MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL, 0x30); + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x80, 0x80); + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL, + 0x0C, 0x0C); + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, + 0x84, 0x84); + snd_soc_update_bits(codec, + MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, + 0x10, 0x10); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, + 0x1F, 0x1F); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, + 0x90, 0x90); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_RX_EAR_CTL, + 0xFF, 0xFF); + /* Wait for 20us for boost settings to take effect */ + usleep_range(20, 21); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, + 0xFF, 0xFF); + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, + 0xE9, 0xE9); + } + } + msm_anlg_cdc_boost_off(codec); + sdm660_cdc_priv->hph_mode = NORMAL_MODE; + + /* 40ms to allow boost to discharge */ + msleep(40); + /* Disable PA to avoid pop during codec bring up */ + snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, + 0x30, 0x00); + snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, + 0x80, 0x00); + snd_soc_write(codec, + MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL, 0x20); + snd_soc_write(codec, + MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL, 0x20); + snd_soc_write(codec, + MSM89XX_PMIC_ANALOG_RX_EAR_CTL, 0x12); + snd_soc_write(codec, + MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x93); + + msm_anlg_cdc_bringup(codec); + atomic_set(&pdata->int_mclk0_enabled, false); + msm_anlg_cdc_dig_notifier_call(codec, DIG_CDC_EVENT_SSR_DOWN); + set_bit(BUS_DOWN, &sdm660_cdc_priv->status_mask); + snd_soc_card_change_online_state(codec->component.card, 0); + return 0; +} + +static int msm_anlg_cdc_device_up(struct snd_soc_codec *codec) +{ + struct sdm660_cdc_priv *sdm660_cdc_priv = + snd_soc_codec_get_drvdata(codec); + int ret = 0; + + dev_dbg(codec->dev, "%s: device up!\n", __func__); + + msm_anlg_cdc_dig_notifier_call(codec, DIG_CDC_EVENT_SSR_UP); + clear_bit(BUS_DOWN, &sdm660_cdc_priv->status_mask); + snd_soc_card_change_online_state(codec->component.card, 1); + /* delay is required to make sure sound card state updated */ + usleep_range(5000, 5100); + + msm_anlg_cdc_codec_init_reg(codec); + msm_anlg_cdc_update_reg_defaults(codec); + + regcache_mark_dirty(codec->component.regmap); + regcache_sync_region(codec->component.regmap, + MSM89XX_PMIC_DIGITAL_REVISION1, + MSM89XX_PMIC_CDC_MAX_REGISTER); + + snd_soc_write(codec, MSM89XX_PMIC_DIGITAL_INT_EN_SET, + MSM89XX_PMIC_DIGITAL_INT_EN_SET__POR); + snd_soc_write(codec, MSM89XX_PMIC_DIGITAL_INT_EN_CLR, + MSM89XX_PMIC_DIGITAL_INT_EN_CLR__POR); + + msm_anlg_cdc_set_boost_v(codec); + msm_anlg_cdc_set_micb_v(codec); + if (sdm660_cdc_priv->boost_option == BOOST_ON_FOREVER) + msm_anlg_cdc_boost_on(codec); + else if (sdm660_cdc_priv->boost_option == BYPASS_ALWAYS) + msm_anlg_cdc_bypass_on(codec); + + msm_anlg_cdc_configure_cap(codec, false, false); + wcd_mbhc_stop(&sdm660_cdc_priv->mbhc); + wcd_mbhc_deinit(&sdm660_cdc_priv->mbhc); + ret = wcd_mbhc_init(&sdm660_cdc_priv->mbhc, codec, &mbhc_cb, + &intr_ids, wcd_mbhc_registers, true); + if (ret) + dev_err(codec->dev, "%s: mbhc initialization failed\n", + __func__); + else + wcd_mbhc_start(&sdm660_cdc_priv->mbhc, + sdm660_cdc_priv->mbhc.mbhc_cfg); + + return 0; +} + +static int sdm660_cdc_notifier_service_cb(struct notifier_block *nb, + unsigned long opcode, void *ptr) +{ + struct snd_soc_codec *codec; + struct sdm660_cdc_priv *sdm660_cdc_priv = + container_of(nb, struct sdm660_cdc_priv, + audio_ssr_nb); + bool adsp_ready = false; + bool timedout; + unsigned long timeout; + + codec = sdm660_cdc_priv->codec; + dev_dbg(codec->dev, "%s: Service opcode 0x%lx\n", __func__, opcode); + + switch (opcode) { + case AUDIO_NOTIFIER_SERVICE_DOWN: + dev_dbg(codec->dev, + "ADSP is about to power down. teardown/reset codec\n"); + msm_anlg_cdc_device_down(codec); + break; + case AUDIO_NOTIFIER_SERVICE_UP: + if (initial_boot) { + initial_boot = false; + break; + } + dev_dbg(codec->dev, + "ADSP is about to power up. bring up codec\n"); + + if (!q6core_is_adsp_ready()) { + dev_dbg(codec->dev, + "ADSP isn't ready\n"); + timeout = jiffies + + msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS); + while (!(timedout = time_after(jiffies, timeout))) { + if (!q6core_is_adsp_ready()) { + dev_dbg(codec->dev, + "ADSP isn't ready\n"); + } else { + dev_dbg(codec->dev, + "ADSP is ready\n"); + adsp_ready = true; + goto powerup; + } + } + } else { + adsp_ready = true; + dev_dbg(codec->dev, "%s: DSP is ready\n", __func__); + } +powerup: + if (adsp_ready) + msm_anlg_cdc_device_up(codec); + break; + default: + break; + } + return NOTIFY_OK; +} + +int msm_anlg_cdc_hs_detect(struct snd_soc_codec *codec, + struct wcd_mbhc_config *mbhc_cfg) +{ + struct sdm660_cdc_priv *sdm660_cdc_priv = + snd_soc_codec_get_drvdata(codec); + + return wcd_mbhc_start(&sdm660_cdc_priv->mbhc, mbhc_cfg); +} +EXPORT_SYMBOL(msm_anlg_cdc_hs_detect); + +void msm_anlg_cdc_hs_detect_exit(struct snd_soc_codec *codec) +{ + struct sdm660_cdc_priv *sdm660_cdc_priv = + snd_soc_codec_get_drvdata(codec); + + wcd_mbhc_stop(&sdm660_cdc_priv->mbhc); +} +EXPORT_SYMBOL(msm_anlg_cdc_hs_detect_exit); + +void msm_anlg_cdc_update_int_spk_boost(bool enable) +{ + pr_debug("%s: enable = %d\n", __func__, enable); + spkr_boost_en = enable; +} +EXPORT_SYMBOL(msm_anlg_cdc_update_int_spk_boost); + +static void msm_anlg_cdc_set_micb_v(struct snd_soc_codec *codec) +{ + + struct sdm660_cdc *sdm660_cdc = codec->control_data; + struct sdm660_cdc_pdata *pdata = sdm660_cdc->dev->platform_data; + u8 reg_val; + + reg_val = VOLTAGE_CONVERTER(pdata->micbias.cfilt1_mv, MICBIAS_MIN_VAL, + MICBIAS_STEP_SIZE); + dev_dbg(codec->dev, "cfilt1_mv %d reg_val %x\n", + (u32)pdata->micbias.cfilt1_mv, reg_val); + snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_MICB_1_VAL, + 0xF8, (reg_val << 3)); +} + +static void msm_anlg_cdc_set_boost_v(struct snd_soc_codec *codec) +{ + struct sdm660_cdc_priv *sdm660_cdc_priv = + snd_soc_codec_get_drvdata(codec); + + snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_OUTPUT_VOLTAGE, + 0x1F, sdm660_cdc_priv->boost_voltage); +} + +static void msm_anlg_cdc_configure_cap(struct snd_soc_codec *codec, + bool micbias1, bool micbias2) +{ + + struct msm_asoc_mach_data *pdata = NULL; + + pdata = snd_soc_card_get_drvdata(codec->component.card); + + pr_debug("\n %s: micbias1 %x micbias2 = %d\n", __func__, micbias1, + micbias2); + if (micbias1 && micbias2) { + if ((pdata->micbias1_cap_mode + == MICBIAS_EXT_BYP_CAP) || + (pdata->micbias2_cap_mode + == MICBIAS_EXT_BYP_CAP)) + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MICB_1_EN, + 0x40, (MICBIAS_EXT_BYP_CAP << 6)); + else + snd_soc_update_bits(codec, + MSM89XX_PMIC_ANALOG_MICB_1_EN, + 0x40, (MICBIAS_NO_EXT_BYP_CAP << 6)); + } else if (micbias2) { + snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_MICB_1_EN, + 0x40, (pdata->micbias2_cap_mode << 6)); + } else if (micbias1) { + snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_MICB_1_EN, + 0x40, (pdata->micbias1_cap_mode << 6)); + } else { + snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_MICB_1_EN, + 0x40, 0x00); + } +} + +static ssize_t msm_anlg_codec_version_read(struct snd_info_entry *entry, + void *file_private_data, + struct file *file, + char __user *buf, size_t count, + loff_t pos) +{ + struct sdm660_cdc_priv *sdm660_cdc_priv; + char buffer[MSM_ANLG_CDC_VERSION_ENTRY_SIZE]; + int len = 0; + + sdm660_cdc_priv = (struct sdm660_cdc_priv *) entry->private_data; + if (!sdm660_cdc_priv) { + pr_err("%s: sdm660_cdc_priv is null\n", __func__); + return -EINVAL; + } + + switch (get_codec_version(sdm660_cdc_priv)) { + case DRAX_CDC: + len = snprintf(buffer, sizeof(buffer), "DRAX_CDC_1_0\n"); + break; + default: + len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n"); + } + + return simple_read_from_buffer(buf, count, &pos, buffer, len); +} + +static struct snd_info_entry_ops msm_anlg_codec_info_ops = { + .read = msm_anlg_codec_version_read, +}; + +/* + * msm_anlg_codec_info_create_codec_entry - creates pmic_analog module + * @codec_root: The parent directory + * @codec: Codec instance + * + * Creates pmic_analog module and version entry under the given + * parent directory. + * + * Return: 0 on success or negative error code on failure. + */ +int msm_anlg_codec_info_create_codec_entry(struct snd_info_entry *codec_root, + struct snd_soc_codec *codec) +{ + struct snd_info_entry *version_entry; + struct sdm660_cdc_priv *sdm660_cdc_priv; + struct snd_soc_card *card; + + if (!codec_root || !codec) + return -EINVAL; + + sdm660_cdc_priv = snd_soc_codec_get_drvdata(codec); + card = codec->component.card; + sdm660_cdc_priv->entry = snd_register_module_info(codec_root->module, + "pmic_analog", + codec_root); + if (!sdm660_cdc_priv->entry) { + dev_dbg(codec->dev, "%s: failed to create pmic_analog entry\n", + __func__); + return -ENOMEM; + } + + version_entry = snd_info_create_card_entry(card->snd_card, + "version", + sdm660_cdc_priv->entry); + if (!version_entry) { + dev_dbg(codec->dev, "%s: failed to create pmic_analog version entry\n", + __func__); + return -ENOMEM; + } + + version_entry->private_data = sdm660_cdc_priv; + version_entry->size = MSM_ANLG_CDC_VERSION_ENTRY_SIZE; + version_entry->content = SNDRV_INFO_CONTENT_DATA; + version_entry->c.ops = &msm_anlg_codec_info_ops; + + if (snd_info_register(version_entry) < 0) { + snd_info_free_entry(version_entry); + return -ENOMEM; + } + sdm660_cdc_priv->version_entry = version_entry; + return 0; +} +EXPORT_SYMBOL(msm_anlg_codec_info_create_codec_entry); + +static int msm_anlg_cdc_soc_probe(struct snd_soc_codec *codec) +{ + struct sdm660_cdc_priv *sdm660_cdc_priv; + struct sdm660_cdc *handle_cdc; + int ret; + + sdm660_cdc_priv = devm_kzalloc(codec->dev, + sizeof(struct sdm660_cdc_priv), + GFP_KERNEL); + if (!sdm660_cdc_priv) + return -ENOMEM; + + codec->control_data = dev_get_drvdata(codec->dev); + snd_soc_codec_set_drvdata(codec, sdm660_cdc_priv); + sdm660_cdc_priv->codec = codec; + handle_cdc = codec->control_data; + handle_cdc->codec = codec; + + /* codec resmgr module init */ + sdm660_cdc_priv->spkdrv_reg = + msm_anlg_cdc_find_regulator(codec->control_data, + MSM89XX_VDD_SPKDRV_NAME); + sdm660_cdc_priv->pmic_rev = + snd_soc_read(codec, + MSM89XX_PMIC_DIGITAL_REVISION1); + sdm660_cdc_priv->codec_version = + snd_soc_read(codec, + MSM89XX_PMIC_DIGITAL_PERPH_SUBTYPE); + sdm660_cdc_priv->analog_major_rev = + snd_soc_read(codec, + MSM89XX_PMIC_ANALOG_REVISION4); + + if (sdm660_cdc_priv->codec_version == CONGA) { + dev_dbg(codec->dev, "%s :Conga REV: %d\n", __func__, + sdm660_cdc_priv->codec_version); + sdm660_cdc_priv->ext_spk_boost_set = true; + } else { + dev_dbg(codec->dev, "%s :PMIC REV: %d\n", __func__, + sdm660_cdc_priv->pmic_rev); + if (sdm660_cdc_priv->pmic_rev == TOMBAK_1_0 && + sdm660_cdc_priv->codec_version == CAJON_2_0) { + if (sdm660_cdc_priv->analog_major_rev == 0x02) { + sdm660_cdc_priv->codec_version = DRAX_CDC; + dev_dbg(codec->dev, + "%s : Drax codec detected\n", __func__); + } else { + sdm660_cdc_priv->codec_version = DIANGU; + dev_dbg(codec->dev, "%s : Diangu detected\n", + __func__); + } + } else if (sdm660_cdc_priv->pmic_rev == TOMBAK_1_0 && + (snd_soc_read(codec, MSM89XX_PMIC_ANALOG_NCP_FBCTRL) + & 0x80)) { + sdm660_cdc_priv->codec_version = CAJON; + dev_dbg(codec->dev, "%s : Cajon detected\n", __func__); + } else if (sdm660_cdc_priv->pmic_rev == TOMBAK_2_0 && + (snd_soc_read(codec, MSM89XX_PMIC_ANALOG_NCP_FBCTRL) + & 0x80)) { + sdm660_cdc_priv->codec_version = CAJON_2_0; + dev_dbg(codec->dev, "%s : Cajon 2.0 detected\n", + __func__); + } + } + /* + * set to default boost option BOOST_SWITCH, user mixer path can change + * it to BOOST_ALWAYS or BOOST_BYPASS based on solution chosen. + */ + sdm660_cdc_priv->boost_option = BOOST_SWITCH; + sdm660_cdc_priv->hph_mode = NORMAL_MODE; + + msm_anlg_cdc_dt_parse_boost_info(codec); + msm_anlg_cdc_set_boost_v(codec); + + snd_soc_add_codec_controls(codec, impedance_detect_controls, + ARRAY_SIZE(impedance_detect_controls)); + snd_soc_add_codec_controls(codec, hph_type_detect_controls, + ARRAY_SIZE(hph_type_detect_controls)); + + msm_anlg_cdc_bringup(codec); + msm_anlg_cdc_codec_init_cache(codec); + msm_anlg_cdc_codec_init_reg(codec); + msm_anlg_cdc_update_reg_defaults(codec); + + wcd9xxx_spmi_set_codec(codec); + + sdm660_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].supply = + msm_anlg_cdc_find_regulator( + codec->control_data, + on_demand_supply_name[ON_DEMAND_MICBIAS]); + atomic_set(&sdm660_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].ref, + 0); + + BLOCKING_INIT_NOTIFIER_HEAD(&sdm660_cdc_priv->notifier); + + sdm660_cdc_priv->fw_data = devm_kzalloc(codec->dev, + sizeof(*(sdm660_cdc_priv->fw_data)), + GFP_KERNEL); + if (!sdm660_cdc_priv->fw_data) + return -ENOMEM; + + set_bit(WCD9XXX_MBHC_CAL, sdm660_cdc_priv->fw_data->cal_bit); + ret = wcd_cal_create_hwdep(sdm660_cdc_priv->fw_data, + WCD9XXX_CODEC_HWDEP_NODE, codec); + if (ret < 0) { + dev_err(codec->dev, "%s hwdep failed %d\n", __func__, ret); + return ret; + } + + wcd_mbhc_init(&sdm660_cdc_priv->mbhc, codec, &mbhc_cb, &intr_ids, + wcd_mbhc_registers, true); + + sdm660_cdc_priv->int_mclk0_enabled = false; + /*Update speaker boost configuration*/ + sdm660_cdc_priv->spk_boost_set = spkr_boost_en; + pr_debug("%s: speaker boost configured = %d\n", + __func__, sdm660_cdc_priv->spk_boost_set); + + /* Set initial MICBIAS voltage level */ + msm_anlg_cdc_set_micb_v(codec); + + /* Set initial cap mode */ + msm_anlg_cdc_configure_cap(codec, false, false); + sdm660_cdc_priv->audio_ssr_nb.notifier_call = + sdm660_cdc_notifier_service_cb; + ret = audio_notifier_register("pmic_analog_cdc", + AUDIO_NOTIFIER_ADSP_DOMAIN, + &sdm660_cdc_priv->audio_ssr_nb); + if (ret < 0) { + pr_err("%s: Audio notifier register failed ret = %d\n", + __func__, ret); + wcd_mbhc_deinit(&sdm660_cdc_priv->mbhc); + return ret; + } + return 0; +} + +static int msm_anlg_cdc_soc_remove(struct snd_soc_codec *codec) +{ + struct sdm660_cdc_priv *sdm660_cdc_priv = + snd_soc_codec_get_drvdata(codec); + + sdm660_cdc_priv->spkdrv_reg = NULL; + sdm660_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].supply = NULL; + atomic_set(&sdm660_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].ref, + 0); + wcd_mbhc_deinit(&sdm660_cdc_priv->mbhc); + + return 0; +} + +static int msm_anlg_cdc_enable_static_supplies_to_optimum( + struct sdm660_cdc *sdm660_cdc, + struct sdm660_cdc_pdata *pdata) +{ + int i; + int ret = 0; + + for (i = 0; i < sdm660_cdc->num_of_supplies; i++) { + if (pdata->regulator[i].ondemand) + continue; + if (regulator_count_voltages( + sdm660_cdc->supplies[i].consumer) <= 0) + continue; + + ret = regulator_set_voltage( + sdm660_cdc->supplies[i].consumer, + pdata->regulator[i].min_uv, + pdata->regulator[i].max_uv); + if (ret) { + dev_err(sdm660_cdc->dev, + "Setting volt failed for regulator %s err %d\n", + sdm660_cdc->supplies[i].supply, ret); + } + + ret = regulator_set_load(sdm660_cdc->supplies[i].consumer, + pdata->regulator[i].optimum_ua); + dev_dbg(sdm660_cdc->dev, "Regulator %s set optimum mode\n", + sdm660_cdc->supplies[i].supply); + } + + return ret; +} + +static int msm_anlg_cdc_disable_static_supplies_to_optimum( + struct sdm660_cdc *sdm660_cdc, + struct sdm660_cdc_pdata *pdata) +{ + int i; + int ret = 0; + + for (i = 0; i < sdm660_cdc->num_of_supplies; i++) { + if (pdata->regulator[i].ondemand) + continue; + if (regulator_count_voltages( + sdm660_cdc->supplies[i].consumer) <= 0) + continue; + regulator_set_voltage(sdm660_cdc->supplies[i].consumer, 0, + pdata->regulator[i].max_uv); + regulator_set_load(sdm660_cdc->supplies[i].consumer, 0); + dev_dbg(sdm660_cdc->dev, "Regulator %s set optimum mode\n", + sdm660_cdc->supplies[i].supply); + } + + return ret; +} + +static int msm_anlg_cdc_suspend(struct snd_soc_codec *codec) +{ + struct msm_asoc_mach_data *pdata = NULL; + struct sdm660_cdc *sdm660_cdc = codec->control_data; + struct sdm660_cdc_pdata *sdm660_cdc_pdata = + sdm660_cdc->dev->platform_data; + + pdata = snd_soc_card_get_drvdata(codec->component.card); + pr_debug("%s: mclk cnt = %d, mclk_enabled = %d\n", + __func__, atomic_read(&pdata->int_mclk0_rsc_ref), + atomic_read(&pdata->int_mclk0_enabled)); + if (atomic_read(&pdata->int_mclk0_enabled) == true) { + cancel_delayed_work_sync(&pdata->disable_int_mclk0_work); + mutex_lock(&pdata->cdc_int_mclk0_mutex); + pdata->digital_cdc_core_clk.enable = 0; + afe_set_lpass_clock_v2(AFE_PORT_ID_INT0_MI2S_RX, + &pdata->digital_cdc_core_clk); + atomic_set(&pdata->int_mclk0_enabled, false); + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + } + msm_anlg_cdc_disable_static_supplies_to_optimum(sdm660_cdc, + sdm660_cdc_pdata); + return 0; +} + +static int msm_anlg_cdc_resume(struct snd_soc_codec *codec) +{ + struct msm_asoc_mach_data *pdata = NULL; + struct sdm660_cdc *sdm660_cdc = codec->control_data; + struct sdm660_cdc_pdata *sdm660_cdc_pdata = + sdm660_cdc->dev->platform_data; + + pdata = snd_soc_card_get_drvdata(codec->component.card); + msm_anlg_cdc_enable_static_supplies_to_optimum(sdm660_cdc, + sdm660_cdc_pdata); + return 0; +} + +static struct regmap *msm_anlg_get_regmap(struct device *dev) +{ + return dev_get_regmap(dev->parent, NULL); +} + +static struct snd_soc_codec_driver soc_codec_dev_sdm660_cdc = { + .probe = msm_anlg_cdc_soc_probe, + .remove = msm_anlg_cdc_soc_remove, + .suspend = msm_anlg_cdc_suspend, + .resume = msm_anlg_cdc_resume, + .reg_word_size = 1, + .controls = msm_anlg_cdc_snd_controls, + .num_controls = ARRAY_SIZE(msm_anlg_cdc_snd_controls), + .dapm_widgets = msm_anlg_cdc_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(msm_anlg_cdc_dapm_widgets), + .dapm_routes = audio_map, + .num_dapm_routes = ARRAY_SIZE(audio_map), + .get_regmap = msm_anlg_get_regmap, +}; + +static int msm_anlg_cdc_init_supplies(struct sdm660_cdc *sdm660_cdc, + struct sdm660_cdc_pdata *pdata) +{ + int ret; + int i; + + sdm660_cdc->supplies = devm_kzalloc(sdm660_cdc->dev, + sizeof(struct regulator_bulk_data) * + ARRAY_SIZE(pdata->regulator), + GFP_KERNEL); + if (!sdm660_cdc->supplies) { + ret = -ENOMEM; + goto err; + } + + sdm660_cdc->num_of_supplies = 0; + if (ARRAY_SIZE(pdata->regulator) > MAX_REGULATOR) { + dev_err(sdm660_cdc->dev, "%s: Array Size out of bound\n", + __func__); + ret = -EINVAL; + goto err; + } + + for (i = 0; i < ARRAY_SIZE(pdata->regulator); i++) { + if (pdata->regulator[i].name) { + sdm660_cdc->supplies[i].supply = + pdata->regulator[i].name; + sdm660_cdc->num_of_supplies++; + } + } + + ret = devm_regulator_bulk_get(sdm660_cdc->dev, + sdm660_cdc->num_of_supplies, + sdm660_cdc->supplies); + if (ret != 0) { + dev_err(sdm660_cdc->dev, + "Failed to get supplies: err = %d\n", + ret); + goto err_supplies; + } + + for (i = 0; i < sdm660_cdc->num_of_supplies; i++) { + if (regulator_count_voltages( + sdm660_cdc->supplies[i].consumer) <= 0) + continue; + ret = regulator_set_voltage(sdm660_cdc->supplies[i].consumer, + pdata->regulator[i].min_uv, + pdata->regulator[i].max_uv); + if (ret) { + dev_err(sdm660_cdc->dev, + "Setting regulator voltage failed for regulator %s err = %d\n", + sdm660_cdc->supplies[i].supply, ret); + goto err_supplies; + } + ret = regulator_set_load(sdm660_cdc->supplies[i].consumer, + pdata->regulator[i].optimum_ua); + if (ret < 0) { + dev_err(sdm660_cdc->dev, + "Setting regulator optimum mode failed for regulator %s err = %d\n", + sdm660_cdc->supplies[i].supply, ret); + goto err_supplies; + } else { + ret = 0; + } + } + + return ret; + +err_supplies: + kfree(sdm660_cdc->supplies); +err: + return ret; +} + +static int msm_anlg_cdc_enable_static_supplies( + struct sdm660_cdc *sdm660_cdc, + struct sdm660_cdc_pdata *pdata) +{ + int i; + int ret = 0; + + for (i = 0; i < sdm660_cdc->num_of_supplies; i++) { + if (pdata->regulator[i].ondemand) + continue; + ret = regulator_enable(sdm660_cdc->supplies[i].consumer); + if (ret) { + dev_err(sdm660_cdc->dev, "Failed to enable %s\n", + sdm660_cdc->supplies[i].supply); + break; + } + dev_dbg(sdm660_cdc->dev, "Enabled regulator %s\n", + sdm660_cdc->supplies[i].supply); + } + + while (ret && --i) + if (!pdata->regulator[i].ondemand) + regulator_disable(sdm660_cdc->supplies[i].consumer); + return ret; +} + +static void msm_anlg_cdc_disable_supplies(struct sdm660_cdc *sdm660_cdc, + struct sdm660_cdc_pdata *pdata) +{ + int i; + + regulator_bulk_disable(sdm660_cdc->num_of_supplies, + sdm660_cdc->supplies); + for (i = 0; i < sdm660_cdc->num_of_supplies; i++) { + if (regulator_count_voltages( + sdm660_cdc->supplies[i].consumer) <= 0) + continue; + regulator_set_voltage(sdm660_cdc->supplies[i].consumer, 0, + pdata->regulator[i].max_uv); + regulator_set_load(sdm660_cdc->supplies[i].consumer, 0); + } + regulator_bulk_free(sdm660_cdc->num_of_supplies, + sdm660_cdc->supplies); + kfree(sdm660_cdc->supplies); +} + +static const struct of_device_id sdm660_codec_of_match[] = { + { .compatible = "qcom,pmic-analog-codec", }, + {}, +}; + +static void msm_anlg_add_child_devices(struct work_struct *work) +{ + struct sdm660_cdc *pdata; + struct platform_device *pdev; + struct device_node *node; + struct msm_dig_ctrl_data *dig_ctrl_data = NULL, *temp; + int ret, ctrl_num = 0; + struct msm_dig_ctrl_platform_data *platdata; + char plat_dev_name[MSM_DIG_CDC_STRING_LEN]; + + pdata = container_of(work, struct sdm660_cdc, + msm_anlg_add_child_devices_work); + if (!pdata) { + pr_err("%s: Memory for pdata does not exist\n", + __func__); + return; + } + if (!pdata->dev->of_node) { + dev_err(pdata->dev, + "%s: DT node for pdata does not exist\n", __func__); + return; + } + + platdata = &pdata->dig_plat_data; + + for_each_child_of_node(pdata->dev->of_node, node) { + if (!strcmp(node->name, "msm-dig-codec")) + strlcpy(plat_dev_name, "msm_digital_codec", + (MSM_DIG_CDC_STRING_LEN - 1)); + else + continue; + + pdev = platform_device_alloc(plat_dev_name, -1); + if (!pdev) { + dev_err(pdata->dev, "%s: pdev memory alloc failed\n", + __func__); + ret = -ENOMEM; + goto err; + } + pdev->dev.parent = pdata->dev; + pdev->dev.of_node = node; + + if (!strcmp(node->name, "msm-dig-codec")) { + ret = platform_device_add_data(pdev, platdata, + sizeof(*platdata)); + if (ret) { + dev_err(&pdev->dev, + "%s: cannot add plat data ctrl:%d\n", + __func__, ctrl_num); + goto fail_pdev_add; + } + } + + ret = platform_device_add(pdev); + if (ret) { + dev_err(&pdev->dev, + "%s: Cannot add platform device\n", + __func__); + goto fail_pdev_add; + } + + if (!strcmp(node->name, "msm-dig-codec")) { + temp = krealloc(dig_ctrl_data, + (ctrl_num + 1) * sizeof( + struct msm_dig_ctrl_data), + GFP_KERNEL); + if (!temp) { + dev_err(&pdev->dev, "out of memory\n"); + ret = -ENOMEM; + goto err; + } + dig_ctrl_data = temp; + dig_ctrl_data[ctrl_num].dig_pdev = pdev; + ctrl_num++; + dev_dbg(&pdev->dev, + "%s: Added digital codec device(s)\n", + __func__); + pdata->dig_ctrl_data = dig_ctrl_data; + } + } + + return; +fail_pdev_add: + platform_device_put(pdev); +err: + return; +} + +static int msm_anlg_cdc_probe(struct platform_device *pdev) +{ + int ret = 0; + struct sdm660_cdc *sdm660_cdc = NULL; + struct sdm660_cdc_pdata *pdata; + int adsp_state; + + adsp_state = apr_get_subsys_state(); + if (adsp_state != APR_SUBSYS_LOADED) { + dev_err(&pdev->dev, "Adsp is not loaded yet %d\n", + adsp_state); + return -EPROBE_DEFER; + } + device_init_wakeup(&pdev->dev, true); + + if (pdev->dev.of_node) { + dev_dbg(&pdev->dev, "%s:Platform data from device tree\n", + __func__); + pdata = msm_anlg_cdc_populate_dt_pdata(&pdev->dev); + pdev->dev.platform_data = pdata; + } else { + dev_dbg(&pdev->dev, "%s:Platform data from board file\n", + __func__); + pdata = pdev->dev.platform_data; + } + if (pdata == NULL) { + dev_err(&pdev->dev, "%s:Platform data failed to populate\n", + __func__); + goto rtn; + } + sdm660_cdc = devm_kzalloc(&pdev->dev, sizeof(struct sdm660_cdc), + GFP_KERNEL); + if (sdm660_cdc == NULL) { + ret = -ENOMEM; + goto rtn; + } + + sdm660_cdc->dev = &pdev->dev; + ret = msm_anlg_cdc_init_supplies(sdm660_cdc, pdata); + if (ret) { + dev_err(&pdev->dev, "%s: Fail to enable Codec supplies\n", + __func__); + goto rtn; + } + ret = msm_anlg_cdc_enable_static_supplies(sdm660_cdc, pdata); + if (ret) { + dev_err(&pdev->dev, + "%s: Fail to enable Codec pre-reset supplies\n", + __func__); + goto rtn; + } + /* Allow supplies to be ready */ + usleep_range(5, 6); + + dev_set_drvdata(&pdev->dev, sdm660_cdc); + if (wcd9xxx_spmi_irq_init()) { + dev_err(&pdev->dev, + "%s: irq initialization failed\n", __func__); + } else { + dev_dbg(&pdev->dev, + "%s: irq initialization passed\n", __func__); + } + + ret = snd_soc_register_codec(&pdev->dev, + &soc_codec_dev_sdm660_cdc, + msm_anlg_cdc_i2s_dai, + ARRAY_SIZE(msm_anlg_cdc_i2s_dai)); + if (ret) { + dev_err(&pdev->dev, + "%s:snd_soc_register_codec failed with error %d\n", + __func__, ret); + goto err_supplies; + } + sdm660_cdc->dig_plat_data.handle = (void *) sdm660_cdc; + sdm660_cdc->dig_plat_data.update_clkdiv = update_clkdiv; + sdm660_cdc->dig_plat_data.get_cdc_version = get_cdc_version; + sdm660_cdc->dig_plat_data.register_notifier = + msm_anlg_cdc_dig_register_notifier; + INIT_WORK(&sdm660_cdc->msm_anlg_add_child_devices_work, + msm_anlg_add_child_devices); + schedule_work(&sdm660_cdc->msm_anlg_add_child_devices_work); + + return ret; +err_supplies: + msm_anlg_cdc_disable_supplies(sdm660_cdc, pdata); +rtn: + return ret; +} + +static int msm_anlg_cdc_remove(struct platform_device *pdev) +{ + struct sdm660_cdc *sdm660_cdc = dev_get_drvdata(&pdev->dev); + struct sdm660_cdc_pdata *pdata = sdm660_cdc->dev->platform_data; + + snd_soc_unregister_codec(&pdev->dev); + msm_anlg_cdc_disable_supplies(sdm660_cdc, pdata); + return 0; +} + +static struct platform_driver msm_anlg_codec_driver = { + .driver = { + .owner = THIS_MODULE, + .name = DRV_NAME, + .of_match_table = of_match_ptr(sdm660_codec_of_match) + }, + .probe = msm_anlg_cdc_probe, + .remove = msm_anlg_cdc_remove, +}; +module_platform_driver(msm_anlg_codec_driver); + +MODULE_DESCRIPTION("MSM Audio Analog codec driver"); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/codecs/sdm660_cdc/msm-analog-cdc.h b/sound/soc/codecs/sdm660_cdc/msm-analog-cdc.h new file mode 100644 index 000000000000..e0626d3be971 --- /dev/null +++ b/sound/soc/codecs/sdm660_cdc/msm-analog-cdc.h @@ -0,0 +1,240 @@ +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef MSM_ANALOG_CDC_H +#define MSM_ANALOG_CDC_H + +#include +#include +#include +#include "../wcd-mbhc-v2.h" +#include "../wcdcal-hwdep.h" +#include "sdm660-cdc-registers.h" + +#define MICBIAS_EXT_BYP_CAP 0x00 +#define MICBIAS_NO_EXT_BYP_CAP 0x01 + +#define MSM89XX_NUM_IRQ_REGS 2 +#define MAX_REGULATOR 7 +#define MSM89XX_REG_VAL(reg, val) {reg, 0, val} + +#define MSM89XX_VDD_SPKDRV_NAME "cdc-vdd-spkdrv" + +#define DEFAULT_MULTIPLIER 800 +#define DEFAULT_GAIN 9 +#define DEFAULT_OFFSET 100 + +extern const u8 msm89xx_pmic_cdc_reg_readable[MSM89XX_PMIC_CDC_CACHE_SIZE]; +extern const u8 msm89xx_cdc_core_reg_readable[MSM89XX_CDC_CORE_CACHE_SIZE]; +extern struct regmap_config msm89xx_cdc_core_regmap_config; +extern struct regmap_config msm89xx_pmic_cdc_regmap_config; + +enum wcd_curr_ref { + I_h4_UA = 0, + I_pt5_UA, + I_14_UA, + I_l4_UA, + I_1_UA, +}; + +enum wcd_mbhc_imp_det_pin { + WCD_MBHC_DET_NONE = 0, + WCD_MBHC_DET_HPHL, + WCD_MBHC_DET_HPHR, + WCD_MBHC_DET_BOTH, +}; + + +/* Each micbias can be assigned to one of three cfilters + * Vbatt_min >= .15V + ldoh_v + * ldoh_v >= .15v + cfiltx_mv + * If ldoh_v = 1.95 160 mv < cfiltx_mv < 1800 mv + * If ldoh_v = 2.35 200 mv < cfiltx_mv < 2200 mv + * If ldoh_v = 2.75 240 mv < cfiltx_mv < 2600 mv + * If ldoh_v = 2.85 250 mv < cfiltx_mv < 2700 mv + */ + +struct wcd_micbias_setting { + u8 ldoh_v; + u32 cfilt1_mv; /* in mv */ + u32 cfilt2_mv; /* in mv */ + u32 cfilt3_mv; /* in mv */ + /* Different WCD9xxx series codecs may not + * have 4 mic biases. If a codec has fewer + * mic biases, some of these properties will + * not be used. + */ + u8 bias1_cfilt_sel; + u8 bias2_cfilt_sel; + u8 bias3_cfilt_sel; + u8 bias4_cfilt_sel; + u8 bias1_cap_mode; + u8 bias2_cap_mode; + u8 bias3_cap_mode; + u8 bias4_cap_mode; + bool bias2_is_headset_only; +}; + +enum sdm660_cdc_pid_current { + MSM89XX_PID_MIC_2P5_UA, + MSM89XX_PID_MIC_5_UA, + MSM89XX_PID_MIC_10_UA, + MSM89XX_PID_MIC_20_UA, +}; + +struct sdm660_cdc_reg_mask_val { + u16 reg; + u8 mask; + u8 val; +}; + +enum { + /* INTR_REG 0 - Digital Periph */ + MSM89XX_IRQ_SPKR_CNP = 0, + MSM89XX_IRQ_SPKR_CLIP, + MSM89XX_IRQ_SPKR_OCP, + MSM89XX_IRQ_MBHC_INSREM_DET1, + MSM89XX_IRQ_MBHC_RELEASE, + MSM89XX_IRQ_MBHC_PRESS, + MSM89XX_IRQ_MBHC_INSREM_DET, + MSM89XX_IRQ_MBHC_HS_DET, + /* INTR_REG 1 - Analog Periph */ + MSM89XX_IRQ_EAR_OCP, + MSM89XX_IRQ_HPHR_OCP, + MSM89XX_IRQ_HPHL_OCP, + MSM89XX_IRQ_EAR_CNP, + MSM89XX_IRQ_HPHR_CNP, + MSM89XX_IRQ_HPHL_CNP, + MSM89XX_NUM_IRQS, +}; + +enum { + ON_DEMAND_MICBIAS = 0, + ON_DEMAND_SPKDRV, + ON_DEMAND_SUPPLIES_MAX, +}; + +/* + * The delay list is per codec HW specification. + * Please add delay in the list in the future instead + * of magic number + */ +enum { + CODEC_DELAY_1_MS = 1000, + CODEC_DELAY_1_1_MS = 1100, +}; + +struct sdm660_cdc_regulator { + const char *name; + int min_uv; + int max_uv; + int optimum_ua; + bool ondemand; + struct regulator *regulator; +}; + +struct on_demand_supply { + struct regulator *supply; + atomic_t ref; +}; + +struct wcd_imped_i_ref { + enum wcd_curr_ref curr_ref; + int min_val; + int multiplier; + int gain_adj; + int offset; +}; + +enum sdm660_cdc_micbias_num { + MSM89XX_MICBIAS1 = 0, +}; + +/* Hold instance to digital codec platform device */ +struct msm_dig_ctrl_data { + struct platform_device *dig_pdev; +}; + +struct msm_dig_ctrl_platform_data { + void *handle; + void (*update_clkdiv)(void *handle, int val); + int (*get_cdc_version)(void *handle); + int (*register_notifier)(void *handle, + struct notifier_block *nblock, + bool enable); +}; + +struct sdm660_cdc { + struct device *dev; + u32 num_of_supplies; + struct regulator_bulk_data *supplies; + struct snd_soc_codec *codec; + struct work_struct msm_anlg_add_child_devices_work; + struct msm_dig_ctrl_platform_data dig_plat_data; + /* digital codec data structure */ + struct msm_dig_ctrl_data *dig_ctrl_data; + struct blocking_notifier_head notifier; +}; + +struct sdm660_cdc_pdata { + struct wcd_micbias_setting micbias; + struct sdm660_cdc_regulator regulator[MAX_REGULATOR]; +}; + +struct sdm660_cdc_priv { + struct snd_soc_codec *codec; + u16 pmic_rev; + u16 codec_version; + u16 analog_major_rev; + u32 boost_voltage; + u32 adc_count; + u32 rx_bias_count; + bool int_mclk0_enabled; + u16 boost_option; + /* mode to select hd2 */ + u32 hph_mode; + /* compander used for each rx chain */ + bool spk_boost_set; + bool ear_pa_boost_set; + bool ext_spk_boost_set; + struct on_demand_supply on_demand_list[ON_DEMAND_SUPPLIES_MAX]; + struct regulator *spkdrv_reg; + struct blocking_notifier_head notifier; + /* mbhc module */ + struct wcd_mbhc mbhc; + /* cal info for codec */ + struct fw_info *fw_data; + struct notifier_block audio_ssr_nb; + int (*codec_spk_ext_pa_cb)(struct snd_soc_codec *codec, int enable); + unsigned long status_mask; + struct wcd_imped_i_ref imped_i_ref; + enum wcd_mbhc_imp_det_pin imped_det_pin; + /* Entry for version info */ + struct snd_info_entry *entry; + struct snd_info_entry *version_entry; +}; + +extern int msm_anlg_cdc_mclk_enable(struct snd_soc_codec *codec, + int mclk_enable, bool dapm); + +extern int msm_anlg_cdc_hs_detect(struct snd_soc_codec *codec, + struct wcd_mbhc_config *mbhc_cfg); + +extern void msm_anlg_cdc_hs_detect_exit(struct snd_soc_codec *codec); + +extern void sdm660_cdc_update_int_spk_boost(bool enable); + +extern void msm_anlg_cdc_spk_ext_pa_cb( + int (*codec_spk_ext_pa)(struct snd_soc_codec *codec, + int enable), struct snd_soc_codec *codec); +int msm_anlg_codec_info_create_codec_entry(struct snd_info_entry *codec_root, + struct snd_soc_codec *codec); +#endif diff --git a/sound/soc/codecs/sdm660_cdc/msm-cdc-common.h b/sound/soc/codecs/sdm660_cdc/msm-cdc-common.h new file mode 100644 index 000000000000..7a63a71ceeb1 --- /dev/null +++ b/sound/soc/codecs/sdm660_cdc/msm-cdc-common.h @@ -0,0 +1,66 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "sdm660-cdc-registers.h" + +extern struct reg_default + msm89xx_cdc_core_defaults[MSM89XX_CDC_CORE_CACHE_SIZE]; +extern struct reg_default + msm89xx_pmic_cdc_defaults[MSM89XX_PMIC_CDC_CACHE_SIZE]; + +bool msm89xx_cdc_core_readable_reg(struct device *dev, unsigned int reg); +bool msm89xx_cdc_core_volatile_reg(struct device *dev, unsigned int reg); + +enum { + AIF1_PB = 0, + AIF1_CAP, + AIF2_VIFEED, + AIF3_SVA, + NUM_CODEC_DAIS, +}; + +enum codec_versions { + TOMBAK_1_0, + TOMBAK_2_0, + CONGA, + CAJON, + CAJON_2_0, + DIANGU, + DRAX_CDC, + UNSUPPORTED, +}; + +/* Support different hph modes */ +enum { + NORMAL_MODE = 0, + HD2_MODE, +}; + +enum dig_cdc_notify_event { + DIG_CDC_EVENT_INVALID, + DIG_CDC_EVENT_CLK_ON, + DIG_CDC_EVENT_CLK_OFF, + DIG_CDC_EVENT_RX1_MUTE_ON, + DIG_CDC_EVENT_RX1_MUTE_OFF, + DIG_CDC_EVENT_RX2_MUTE_ON, + DIG_CDC_EVENT_RX2_MUTE_OFF, + DIG_CDC_EVENT_RX3_MUTE_ON, + DIG_CDC_EVENT_RX3_MUTE_OFF, + DIG_CDC_EVENT_PRE_RX1_INT_ON, + DIG_CDC_EVENT_PRE_RX2_INT_ON, + DIG_CDC_EVENT_POST_RX1_INT_OFF, + DIG_CDC_EVENT_POST_RX2_INT_OFF, + DIG_CDC_EVENT_SSR_DOWN, + DIG_CDC_EVENT_SSR_UP, + DIG_CDC_EVENT_LAST, +}; diff --git a/sound/soc/codecs/sdm660_cdc/msm-digital-cdc.c b/sound/soc/codecs/sdm660_cdc/msm-digital-cdc.c new file mode 100644 index 000000000000..ac71e3c6d6a1 --- /dev/null +++ b/sound/soc/codecs/sdm660_cdc/msm-digital-cdc.c @@ -0,0 +1,2039 @@ +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "sdm660-cdc-registers.h" +#include "msm-digital-cdc.h" +#include "msm-cdc-common.h" +#include "../../msm/sdm660-common.h" + +#define DRV_NAME "msm_digital_codec" +#define MCLK_RATE_9P6MHZ 9600000 +#define MCLK_RATE_12P288MHZ 12288000 +#define TX_MUX_CTL_CUT_OFF_FREQ_MASK 0x30 +#define CF_MIN_3DB_4HZ 0x0 +#define CF_MIN_3DB_75HZ 0x1 +#define CF_MIN_3DB_150HZ 0x2 + +#define MSM_DIG_CDC_VERSION_ENTRY_SIZE 32 + +static unsigned long rx_digital_gain_reg[] = { + MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL, + MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL, + MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL, +}; + +static unsigned long tx_digital_gain_reg[] = { + MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN, + MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN, +}; + +static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0); + +struct snd_soc_codec *registered_digcodec; +struct hpf_work tx_hpf_work[NUM_DECIMATORS]; + +/* Codec supports 2 IIR filters */ +enum { + IIR1 = 0, + IIR2, + IIR_MAX, +}; + +static int msm_digcdc_clock_control(bool flag) +{ + int ret = -EINVAL; + struct msm_asoc_mach_data *pdata = NULL; + + pdata = snd_soc_card_get_drvdata(registered_digcodec->component.card); + + if (flag) { + if (atomic_read(&pdata->int_mclk0_enabled) == false) { + pdata->digital_cdc_core_clk.enable = 1; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_PRIMARY_MI2S_RX, + &pdata->digital_cdc_core_clk); + if (ret < 0) { + pr_err("%s:failed to enable the MCLK\n", + __func__); + return ret; + } + pr_debug("enabled digital codec core clk\n"); + atomic_set(&pdata->int_mclk0_enabled, true); + schedule_delayed_work(&pdata->disable_int_mclk0_work, + 50); + } + } else { + dev_dbg(registered_digcodec->dev, + "disable MCLK, workq to disable set already\n"); + } + return 0; +} + +static void enable_digital_callback(void *flag) +{ + msm_digcdc_clock_control(true); +} + +static void disable_digital_callback(void *flag) +{ + pr_debug("disable mclk happens in workq\n"); +} + +static int msm_dig_cdc_put_dec_enum(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget_list *wlist = + dapm_kcontrol_get_wlist(kcontrol); + struct snd_soc_dapm_widget *w = wlist->widgets[0]; + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + unsigned int dec_mux, decimator; + char *dec_name = NULL; + char *widget_name = NULL; + char *temp; + u16 tx_mux_ctl_reg; + u8 adc_dmic_sel = 0x0; + int ret = 0; + char *dec_num; + + if (ucontrol->value.enumerated.item[0] > e->items) { + dev_err(codec->dev, "%s: Invalid enum value: %d\n", + __func__, ucontrol->value.enumerated.item[0]); + return -EINVAL; + } + dec_mux = ucontrol->value.enumerated.item[0]; + + widget_name = kstrndup(w->name, 15, GFP_KERNEL); + if (!widget_name) { + dev_err(codec->dev, "%s: failed to copy string\n", + __func__); + return -ENOMEM; + } + temp = widget_name; + + dec_name = strsep(&widget_name, " "); + widget_name = temp; + if (!dec_name) { + dev_err(codec->dev, "%s: Invalid decimator = %s\n", + __func__, w->name); + ret = -EINVAL; + goto out; + } + + dec_num = strpbrk(dec_name, "12345"); + if (dec_num == NULL) { + dev_err(codec->dev, "%s: Invalid DEC selected\n", __func__); + ret = -EINVAL; + goto out; + } + + ret = kstrtouint(dec_num, 10, &decimator); + if (ret < 0) { + dev_err(codec->dev, "%s: Invalid decimator = %s\n", + __func__, dec_name); + ret = -EINVAL; + goto out; + } + + dev_dbg(w->dapm->dev, "%s(): widget = %s decimator = %u dec_mux = %u\n" + , __func__, w->name, decimator, dec_mux); + + switch (decimator) { + case 1: + case 2: + case 3: + case 4: + case 5: + if ((dec_mux == 4) || (dec_mux == 5) || + (dec_mux == 6) || (dec_mux == 7)) + adc_dmic_sel = 0x1; + else + adc_dmic_sel = 0x0; + break; + default: + dev_err(codec->dev, "%s: Invalid Decimator = %u\n", + __func__, decimator); + ret = -EINVAL; + goto out; + } + + tx_mux_ctl_reg = + MSM89XX_CDC_CORE_TX1_MUX_CTL + 32 * (decimator - 1); + + snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x1, adc_dmic_sel); + + ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol); + +out: + kfree(widget_name); + return ret; +} + + +static int msm_dig_cdc_codec_config_compander(struct snd_soc_codec *codec, + int interp_n, int event) +{ + struct msm_dig_priv *dig_cdc = snd_soc_codec_get_drvdata(codec); + + dev_dbg(codec->dev, "%s: event %d shift %d, enabled %d\n", + __func__, event, interp_n, + dig_cdc->comp_enabled[interp_n]); + + /* compander is not enabled */ + if (!dig_cdc->comp_enabled[interp_n]) + return 0; + + switch (dig_cdc->comp_enabled[interp_n]) { + case COMPANDER_1: + if (SND_SOC_DAPM_EVENT_ON(event)) { + /* Enable Compander Clock */ + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_COMP0_B2_CTL, 0x0F, 0x09); + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_CLK_RX_B2_CTL, 0x01, 0x01); + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_COMP0_B1_CTL, + 1 << interp_n, 1 << interp_n); + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_COMP0_B3_CTL, 0xFF, 0x01); + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_COMP0_B2_CTL, 0xF0, 0x50); + /* add sleep for compander to settle */ + usleep_range(1000, 1100); + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_COMP0_B3_CTL, 0xFF, 0x28); + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_COMP0_B2_CTL, 0xF0, 0xB0); + + /* Enable Compander GPIO */ + if (dig_cdc->codec_hph_comp_gpio) + dig_cdc->codec_hph_comp_gpio(1, codec); + } else if (SND_SOC_DAPM_EVENT_OFF(event)) { + /* Disable Compander GPIO */ + if (dig_cdc->codec_hph_comp_gpio) + dig_cdc->codec_hph_comp_gpio(0, codec); + + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_COMP0_B2_CTL, 0x0F, 0x05); + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_COMP0_B1_CTL, + 1 << interp_n, 0); + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_CLK_RX_B2_CTL, 0x01, 0x00); + } + break; + default: + dev_dbg(codec->dev, "%s: Invalid compander %d\n", __func__, + dig_cdc->comp_enabled[interp_n]); + break; + }; + + return 0; +} + +/** + * msm_dig_cdc_hph_comp_cb - registers callback to codec by machine driver. + * + * @codec_hph_comp_gpio: function pointer to set comp gpio at machine driver + * @codec: codec pointer + * + */ +void msm_dig_cdc_hph_comp_cb( + int (*codec_hph_comp_gpio)(bool enable, struct snd_soc_codec *codec), + struct snd_soc_codec *codec) +{ + struct msm_dig_priv *dig_cdc = snd_soc_codec_get_drvdata(codec); + + pr_debug("%s: Enter\n", __func__); + dig_cdc->codec_hph_comp_gpio = codec_hph_comp_gpio; +} +EXPORT_SYMBOL(msm_dig_cdc_hph_comp_cb); + +static int msm_dig_cdc_codec_enable_interpolator(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct msm_dig *msm_dig_cdc = dev_get_drvdata(codec->dev); + + dev_dbg(codec->dev, "%s %d %s\n", __func__, event, w->name); + + if (w->shift >= MSM89XX_RX_MAX || w->shift < 0) { + dev_err(codec->dev, "%s: wrong RX index: %d\n", + __func__, w->shift); + return -EINVAL; + } + switch (event) { + case SND_SOC_DAPM_POST_PMU: + msm_dig_cdc_codec_config_compander(codec, w->shift, event); + /* apply the digital gain after the interpolator is enabled*/ + if ((w->shift) < ARRAY_SIZE(rx_digital_gain_reg)) + snd_soc_write(codec, + rx_digital_gain_reg[w->shift], + snd_soc_read(codec, + rx_digital_gain_reg[w->shift]) + ); + break; + case SND_SOC_DAPM_POST_PMD: + msm_dig_cdc_codec_config_compander(codec, w->shift, event); + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_CLK_RX_RESET_CTL, + 1 << w->shift, 1 << w->shift); + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_CLK_RX_RESET_CTL, + 1 << w->shift, 0x0); + /* + * disable the mute enabled during the PMD of this device + */ + if ((w->shift == 0) && + (msm_dig_cdc->mute_mask & HPHL_PA_DISABLE)) { + pr_debug("disabling HPHL mute\n"); + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_RX1_B6_CTL, 0x01, 0x00); + msm_dig_cdc->mute_mask &= ~(HPHL_PA_DISABLE); + } else if ((w->shift == 1) && + (msm_dig_cdc->mute_mask & HPHR_PA_DISABLE)) { + pr_debug("disabling HPHR mute\n"); + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_RX2_B6_CTL, 0x01, 0x00); + msm_dig_cdc->mute_mask &= ~(HPHR_PA_DISABLE); + } else if ((w->shift == 2) && + (msm_dig_cdc->mute_mask & SPKR_PA_DISABLE)) { + pr_debug("disabling SPKR mute\n"); + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_RX3_B6_CTL, 0x01, 0x00); + msm_dig_cdc->mute_mask &= ~(SPKR_PA_DISABLE); + } + } + return 0; +} + +static int msm_dig_cdc_codec_enable_rx_chain(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + + switch (event) { + case SND_SOC_DAPM_POST_PMD: + snd_soc_update_bits(codec, w->reg, + 1 << w->shift, 0x00); + break; + } + return 0; +} + +static int msm_dig_cdc_get_iir_enable_audio_mixer( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + int iir_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->reg; + int band_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->shift; + + ucontrol->value.integer.value[0] = + (snd_soc_read(codec, + (MSM89XX_CDC_CORE_IIR1_CTL + 64 * iir_idx)) & + (1 << band_idx)) != 0; + + dev_dbg(codec->dev, "%s: IIR #%d band #%d enable %d\n", __func__, + iir_idx, band_idx, + (uint32_t)ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_dig_cdc_put_iir_enable_audio_mixer( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + int iir_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->reg; + int band_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->shift; + int value = ucontrol->value.integer.value[0]; + + /* Mask first 5 bits, 6-8 are reserved */ + snd_soc_update_bits(codec, + (MSM89XX_CDC_CORE_IIR1_CTL + 64 * iir_idx), + (1 << band_idx), (value << band_idx)); + + dev_dbg(codec->dev, "%s: IIR #%d band #%d enable %d\n", __func__, + iir_idx, band_idx, + ((snd_soc_read(codec, + (MSM89XX_CDC_CORE_IIR1_CTL + 64 * iir_idx)) & + (1 << band_idx)) != 0)); + + return 0; +} + +static uint32_t get_iir_band_coeff(struct snd_soc_codec *codec, + int iir_idx, int band_idx, + int coeff_idx) +{ + uint32_t value = 0; + + /* Address does not automatically update if reading */ + snd_soc_write(codec, + (MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL + 64 * iir_idx), + ((band_idx * BAND_MAX + coeff_idx) + * sizeof(uint32_t)) & 0x7F); + + value |= snd_soc_read(codec, + (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx)); + + snd_soc_write(codec, + (MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL + 64 * iir_idx), + ((band_idx * BAND_MAX + coeff_idx) + * sizeof(uint32_t) + 1) & 0x7F); + + value |= (snd_soc_read(codec, + (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx)) << 8); + + snd_soc_write(codec, + (MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL + 64 * iir_idx), + ((band_idx * BAND_MAX + coeff_idx) + * sizeof(uint32_t) + 2) & 0x7F); + + value |= (snd_soc_read(codec, + (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx)) << 16); + + snd_soc_write(codec, + (MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL + 64 * iir_idx), + ((band_idx * BAND_MAX + coeff_idx) + * sizeof(uint32_t) + 3) & 0x7F); + + /* Mask bits top 2 bits since they are reserved */ + value |= ((snd_soc_read(codec, (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + + 64 * iir_idx)) & 0x3f) << 24); + + return value; + +} + +static void set_iir_band_coeff(struct snd_soc_codec *codec, + int iir_idx, int band_idx, + uint32_t value) +{ + snd_soc_write(codec, + (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx), + (value & 0xFF)); + + snd_soc_write(codec, + (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx), + (value >> 8) & 0xFF); + + snd_soc_write(codec, + (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx), + (value >> 16) & 0xFF); + + /* Mask top 2 bits, 7-8 are reserved */ + snd_soc_write(codec, + (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx), + (value >> 24) & 0x3F); + +} + +static int msm_dig_cdc_get_iir_band_audio_mixer( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + int iir_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->reg; + int band_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->shift; + + ucontrol->value.integer.value[0] = + get_iir_band_coeff(codec, iir_idx, band_idx, 0); + ucontrol->value.integer.value[1] = + get_iir_band_coeff(codec, iir_idx, band_idx, 1); + ucontrol->value.integer.value[2] = + get_iir_band_coeff(codec, iir_idx, band_idx, 2); + ucontrol->value.integer.value[3] = + get_iir_band_coeff(codec, iir_idx, band_idx, 3); + ucontrol->value.integer.value[4] = + get_iir_band_coeff(codec, iir_idx, band_idx, 4); + + dev_dbg(codec->dev, "%s: IIR #%d band #%d b0 = 0x%x\n" + "%s: IIR #%d band #%d b1 = 0x%x\n" + "%s: IIR #%d band #%d b2 = 0x%x\n" + "%s: IIR #%d band #%d a1 = 0x%x\n" + "%s: IIR #%d band #%d a2 = 0x%x\n", + __func__, iir_idx, band_idx, + (uint32_t)ucontrol->value.integer.value[0], + __func__, iir_idx, band_idx, + (uint32_t)ucontrol->value.integer.value[1], + __func__, iir_idx, band_idx, + (uint32_t)ucontrol->value.integer.value[2], + __func__, iir_idx, band_idx, + (uint32_t)ucontrol->value.integer.value[3], + __func__, iir_idx, band_idx, + (uint32_t)ucontrol->value.integer.value[4]); + return 0; +} + +static int msm_dig_cdc_put_iir_band_audio_mixer( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + int iir_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->reg; + int band_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->shift; + + /* Mask top bit it is reserved */ + /* Updates addr automatically for each B2 write */ + snd_soc_write(codec, + (MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL + 64 * iir_idx), + (band_idx * BAND_MAX * sizeof(uint32_t)) & 0x7F); + + + set_iir_band_coeff(codec, iir_idx, band_idx, + ucontrol->value.integer.value[0]); + set_iir_band_coeff(codec, iir_idx, band_idx, + ucontrol->value.integer.value[1]); + set_iir_band_coeff(codec, iir_idx, band_idx, + ucontrol->value.integer.value[2]); + set_iir_band_coeff(codec, iir_idx, band_idx, + ucontrol->value.integer.value[3]); + set_iir_band_coeff(codec, iir_idx, band_idx, + ucontrol->value.integer.value[4]); + + dev_dbg(codec->dev, "%s: IIR #%d band #%d b0 = 0x%x\n" + "%s: IIR #%d band #%d b1 = 0x%x\n" + "%s: IIR #%d band #%d b2 = 0x%x\n" + "%s: IIR #%d band #%d a1 = 0x%x\n" + "%s: IIR #%d band #%d a2 = 0x%x\n", + __func__, iir_idx, band_idx, + get_iir_band_coeff(codec, iir_idx, band_idx, 0), + __func__, iir_idx, band_idx, + get_iir_band_coeff(codec, iir_idx, band_idx, 1), + __func__, iir_idx, band_idx, + get_iir_band_coeff(codec, iir_idx, band_idx, 2), + __func__, iir_idx, band_idx, + get_iir_band_coeff(codec, iir_idx, band_idx, 3), + __func__, iir_idx, band_idx, + get_iir_band_coeff(codec, iir_idx, band_idx, 4)); + return 0; +} + +static void tx_hpf_corner_freq_callback(struct work_struct *work) +{ + struct delayed_work *hpf_delayed_work; + struct hpf_work *hpf_work; + struct snd_soc_codec *codec; + struct msm_dig *msm_dig_cdc; + u16 tx_mux_ctl_reg; + u8 hpf_cut_of_freq; + + hpf_delayed_work = to_delayed_work(work); + hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork); + codec = hpf_work->dig_cdc->codec; + msm_dig_cdc = codec->control_data; + hpf_cut_of_freq = hpf_work->tx_hpf_cut_of_freq; + + tx_mux_ctl_reg = MSM89XX_CDC_CORE_TX1_MUX_CTL + + (hpf_work->decimator - 1) * 32; + + dev_dbg(codec->dev, "%s(): decimator %u hpf_cut_of_freq 0x%x\n", + __func__, hpf_work->decimator, (unsigned int)hpf_cut_of_freq); + msm_dig_cdc->update_clkdiv(msm_dig_cdc->handle, 0x51); + + snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x30, hpf_cut_of_freq << 4); +} + +static int msm_dig_cdc_codec_set_iir_gain(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + int value = 0, reg; + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + if (w->shift == 0) + reg = MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL; + else if (w->shift == 1) + reg = MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL; + else + goto ret; + value = snd_soc_read(codec, reg); + snd_soc_write(codec, reg, value); + break; + default: + pr_err("%s: event = %d not expected\n", __func__, event); + } +ret: + return 0; +} + +static int msm_dig_cdc_compander_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct msm_dig_priv *dig_cdc = snd_soc_codec_get_drvdata(codec); + int comp_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->reg; + int rx_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->shift; + + dev_dbg(codec->dev, "%s: msm_dig_cdc->comp[%d]_enabled[%d] = %d\n", + __func__, comp_idx, rx_idx, + dig_cdc->comp_enabled[rx_idx]); + + ucontrol->value.integer.value[0] = dig_cdc->comp_enabled[rx_idx]; + + dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", + __func__, ucontrol->value.integer.value[0]); + + return 0; +} + +static int msm_dig_cdc_compander_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct msm_dig_priv *dig_cdc = snd_soc_codec_get_drvdata(codec); + int comp_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->reg; + int rx_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->shift; + int value = ucontrol->value.integer.value[0]; + + dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", + __func__, ucontrol->value.integer.value[0]); + + if (dig_cdc->version >= DIANGU) { + if (!value) + dig_cdc->comp_enabled[rx_idx] = 0; + else + dig_cdc->comp_enabled[rx_idx] = comp_idx; + } + + dev_dbg(codec->dev, "%s: msm_dig_cdc->comp[%d]_enabled[%d] = %d\n", + __func__, comp_idx, rx_idx, + dig_cdc->comp_enabled[rx_idx]); + + return 0; +} + +static const struct snd_kcontrol_new compander_kcontrols[] = { + SOC_SINGLE_EXT("COMP0 RX1", COMPANDER_1, MSM89XX_RX1, 1, 0, + msm_dig_cdc_compander_get, msm_dig_cdc_compander_set), + + SOC_SINGLE_EXT("COMP0 RX2", COMPANDER_1, MSM89XX_RX2, 1, 0, + msm_dig_cdc_compander_get, msm_dig_cdc_compander_set), + +}; + +static int msm_dig_cdc_set_interpolator_rate(struct snd_soc_dai *dai, + u8 rx_fs_rate_reg_val, + u32 sample_rate) +{ + snd_soc_update_bits(dai->codec, + MSM89XX_CDC_CORE_RX1_B5_CTL, 0xF0, rx_fs_rate_reg_val); + snd_soc_update_bits(dai->codec, + MSM89XX_CDC_CORE_RX2_B5_CTL, 0xF0, rx_fs_rate_reg_val); + return 0; +} + +static int msm_dig_cdc_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + u8 tx_fs_rate, rx_fs_rate, rx_clk_fs_rate; + int ret; + + dev_dbg(dai->codec->dev, + "%s: dai_name = %s DAI-ID %x rate %d num_ch %d format %d\n", + __func__, dai->name, dai->id, params_rate(params), + params_channels(params), params_format(params)); + + switch (params_rate(params)) { + case 8000: + tx_fs_rate = 0x00; + rx_fs_rate = 0x00; + rx_clk_fs_rate = 0x00; + break; + case 16000: + tx_fs_rate = 0x20; + rx_fs_rate = 0x20; + rx_clk_fs_rate = 0x01; + break; + case 32000: + tx_fs_rate = 0x40; + rx_fs_rate = 0x40; + rx_clk_fs_rate = 0x02; + break; + case 44100: + case 48000: + tx_fs_rate = 0x60; + rx_fs_rate = 0x60; + rx_clk_fs_rate = 0x03; + break; + case 96000: + tx_fs_rate = 0x80; + rx_fs_rate = 0x80; + rx_clk_fs_rate = 0x04; + break; + case 192000: + tx_fs_rate = 0xA0; + rx_fs_rate = 0xA0; + rx_clk_fs_rate = 0x05; + break; + default: + dev_err(dai->codec->dev, + "%s: Invalid sampling rate %d\n", __func__, + params_rate(params)); + return -EINVAL; + } + + snd_soc_update_bits(dai->codec, + MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 0x0F, rx_clk_fs_rate); + + switch (substream->stream) { + case SNDRV_PCM_STREAM_CAPTURE: + break; + case SNDRV_PCM_STREAM_PLAYBACK: + ret = msm_dig_cdc_set_interpolator_rate(dai, rx_fs_rate, + params_rate(params)); + if (ret < 0) { + dev_err(dai->codec->dev, + "%s: set decimator rate failed %d\n", __func__, + ret); + return ret; + } + break; + default: + dev_err(dai->codec->dev, + "%s: Invalid stream type %d\n", __func__, + substream->stream); + return -EINVAL; + } + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + snd_soc_update_bits(dai->codec, + MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 0x20, 0x20); + break; + case SNDRV_PCM_FORMAT_S24_LE: + snd_soc_update_bits(dai->codec, + MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 0x20, 0x00); + break; + default: + dev_err(dai->codec->dev, "%s: wrong format selected\n", + __func__); + return -EINVAL; + } + return 0; +} + +static int msm_dig_cdc_codec_enable_dmic(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct msm_dig_priv *dig_cdc = snd_soc_codec_get_drvdata(codec); + u8 dmic_clk_en; + u16 dmic_clk_reg; + s32 *dmic_clk_cnt; + unsigned int dmic; + int ret; + char *dmic_num = strpbrk(w->name, "1234"); + + if (dmic_num == NULL) { + dev_err(codec->dev, "%s: Invalid DMIC\n", __func__); + return -EINVAL; + } + + ret = kstrtouint(dmic_num, 10, &dmic); + if (ret < 0) { + dev_err(codec->dev, + "%s: Invalid DMIC line on the codec\n", __func__); + return -EINVAL; + } + + switch (dmic) { + case 1: + case 2: + dmic_clk_en = 0x01; + dmic_clk_cnt = &(dig_cdc->dmic_1_2_clk_cnt); + dmic_clk_reg = MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL; + dev_dbg(codec->dev, + "%s() event %d DMIC%d dmic_1_2_clk_cnt %d\n", + __func__, event, dmic, *dmic_clk_cnt); + break; + case 3: + case 4: + dmic_clk_en = 0x01; + dmic_clk_cnt = &(dig_cdc->dmic_3_4_clk_cnt); + dmic_clk_reg = MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL; + dev_dbg(codec->dev, + "%s() event %d DMIC%d dmic_3_4_clk_cnt %d\n", + __func__, event, dmic, *dmic_clk_cnt); + break; + default: + dev_err(codec->dev, "%s: Invalid DMIC Selection\n", __func__); + return -EINVAL; + } + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + (*dmic_clk_cnt)++; + if (*dmic_clk_cnt == 1) { + snd_soc_update_bits(codec, dmic_clk_reg, + 0x0E, 0x02); + snd_soc_update_bits(codec, dmic_clk_reg, + dmic_clk_en, dmic_clk_en); + } + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_TX1_DMIC_CTL + (dmic - 1) * 0x20, + 0x07, 0x01); + break; + case SND_SOC_DAPM_POST_PMD: + (*dmic_clk_cnt)--; + if (*dmic_clk_cnt == 0) + snd_soc_update_bits(codec, dmic_clk_reg, + dmic_clk_en, 0); + break; + } + return 0; +} + +static int msm_dig_cdc_codec_enable_dec(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct msm_asoc_mach_data *pdata = NULL; + unsigned int decimator; + struct msm_dig_priv *dig_cdc = snd_soc_codec_get_drvdata(codec); + struct msm_dig *msm_dig_cdc = codec->control_data; + char *dec_name = NULL; + char *widget_name = NULL; + char *temp; + int ret = 0, i; + u16 dec_reset_reg, tx_vol_ctl_reg, tx_mux_ctl_reg; + u8 dec_hpf_cut_of_freq; + int offset; + char *dec_num; + + pdata = snd_soc_card_get_drvdata(codec->component.card); + dev_dbg(codec->dev, "%s %d\n", __func__, event); + + widget_name = kstrndup(w->name, 15, GFP_KERNEL); + if (!widget_name) + return -ENOMEM; + temp = widget_name; + + dec_name = strsep(&widget_name, " "); + widget_name = temp; + if (!dec_name) { + dev_err(codec->dev, + "%s: Invalid decimator = %s\n", __func__, w->name); + ret = -EINVAL; + goto out; + } + + dec_num = strpbrk(dec_name, "12345"); + if (dec_num == NULL) { + dev_err(codec->dev, "%s: Invalid Decimator\n", __func__); + ret = -EINVAL; + goto out; + } + + ret = kstrtouint(dec_num, 10, &decimator); + if (ret < 0) { + dev_err(codec->dev, + "%s: Invalid decimator = %s\n", __func__, dec_name); + ret = -EINVAL; + goto out; + } + + dev_dbg(codec->dev, + "%s(): widget = %s dec_name = %s decimator = %u\n", __func__, + w->name, dec_name, decimator); + + if (w->reg == MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL) { + dec_reset_reg = MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL; + offset = 0; + } else { + dev_err(codec->dev, "%s: Error, incorrect dec\n", __func__); + ret = -EINVAL; + goto out; + } + + tx_vol_ctl_reg = MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG + + 32 * (decimator - 1); + tx_mux_ctl_reg = MSM89XX_CDC_CORE_TX1_MUX_CTL + + 32 * (decimator - 1); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + /* Enableable TX digital mute */ + snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x01); + for (i = 0; i < NUM_DECIMATORS; i++) { + if (decimator == i + 1) + dig_cdc->dec_active[i] = true; + } + + dec_hpf_cut_of_freq = snd_soc_read(codec, tx_mux_ctl_reg); + + dec_hpf_cut_of_freq = (dec_hpf_cut_of_freq & 0x30) >> 4; + + tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq = + dec_hpf_cut_of_freq; + + if (dec_hpf_cut_of_freq != CF_MIN_3DB_150HZ) { + + /* set cut of freq to CF_MIN_3DB_150HZ (0x1); */ + snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x30, + CF_MIN_3DB_150HZ << 4); + } + msm_dig_cdc->update_clkdiv(msm_dig_cdc->handle, 0x42); + break; + case SND_SOC_DAPM_POST_PMU: + /* enable HPF */ + snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x08, 0x00); + + if (tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq != + CF_MIN_3DB_150HZ) { + + schedule_delayed_work(&tx_hpf_work[decimator - 1].dwork, + msecs_to_jiffies(300)); + } + /* apply the digital gain after the decimator is enabled*/ + if ((w->shift) < ARRAY_SIZE(tx_digital_gain_reg)) + snd_soc_write(codec, + tx_digital_gain_reg[w->shift + offset], + snd_soc_read(codec, + tx_digital_gain_reg[w->shift + offset]) + ); + if (pdata->lb_mode) { + pr_debug("%s: loopback mode unmute the DEC\n", + __func__); + snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x00); + } + snd_soc_update_bits(codec, tx_vol_ctl_reg, + 0x01, 0x00); + + break; + case SND_SOC_DAPM_PRE_PMD: + snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x01); + msleep(20); + snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x08, 0x08); + cancel_delayed_work_sync(&tx_hpf_work[decimator - 1].dwork); + break; + case SND_SOC_DAPM_POST_PMD: + snd_soc_update_bits(codec, dec_reset_reg, 1 << w->shift, + 1 << w->shift); + snd_soc_update_bits(codec, dec_reset_reg, 1 << w->shift, 0x0); + snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x08, 0x08); + snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x30, + (tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq) << 4); + snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x00); + for (i = 0; i < NUM_DECIMATORS; i++) { + if (decimator == i + 1) + dig_cdc->dec_active[i] = false; + } + break; + } +out: + kfree(widget_name); + return ret; +} + +static int msm_dig_cdc_event_notify(struct notifier_block *block, + unsigned long val, + void *data) +{ + enum dig_cdc_notify_event event = (enum dig_cdc_notify_event)val; + struct snd_soc_codec *codec = registered_digcodec; + struct msm_dig *msm_dig_cdc = codec->control_data; + struct msm_asoc_mach_data *pdata = NULL; + + pdata = snd_soc_card_get_drvdata(codec->component.card); + + switch (event) { + case DIG_CDC_EVENT_CLK_ON: + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_CLK_PDM_CTL, 0x03, 0x03); + if (pdata->mclk_freq == MCLK_RATE_12P288MHZ || + pdata->native_clk_set) + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_TOP_CTL, 0x01, 0x00); + else if (pdata->mclk_freq == MCLK_RATE_9P6MHZ) + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_TOP_CTL, 0x01, 0x01); + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_CLK_MCLK_CTL, 0x01, 0x01); + break; + case DIG_CDC_EVENT_CLK_OFF: + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_CLK_PDM_CTL, 0x03, 0x00); + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_CLK_MCLK_CTL, 0x01, 0x00); + break; + case DIG_CDC_EVENT_RX1_MUTE_ON: + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_RX1_B6_CTL, 0x01, 0x01); + msm_dig_cdc->mute_mask |= HPHL_PA_DISABLE; + break; + case DIG_CDC_EVENT_RX1_MUTE_OFF: + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_RX1_B6_CTL, 0x01, 0x00); + msm_dig_cdc->mute_mask &= (~HPHL_PA_DISABLE); + break; + case DIG_CDC_EVENT_RX2_MUTE_ON: + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_RX2_B6_CTL, 0x01, 0x01); + msm_dig_cdc->mute_mask |= HPHR_PA_DISABLE; + break; + case DIG_CDC_EVENT_RX2_MUTE_OFF: + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_RX2_B6_CTL, 0x01, 0x00); + msm_dig_cdc->mute_mask &= (~HPHR_PA_DISABLE); + break; + case DIG_CDC_EVENT_RX3_MUTE_ON: + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_RX3_B6_CTL, 0x01, 0x01); + msm_dig_cdc->mute_mask |= SPKR_PA_DISABLE; + break; + case DIG_CDC_EVENT_RX3_MUTE_OFF: + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_RX3_B6_CTL, 0x01, 0x00); + msm_dig_cdc->mute_mask &= (~SPKR_PA_DISABLE); + break; + case DIG_CDC_EVENT_PRE_RX1_INT_ON: + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_RX1_B3_CTL, 0x1C, 0x14); + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_RX1_B4_CTL, 0x18, 0x10); + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_RX1_B3_CTL, 0x80, 0x80); + break; + case DIG_CDC_EVENT_PRE_RX2_INT_ON: + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_RX2_B3_CTL, 0x1C, 0x14); + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_RX2_B4_CTL, 0x18, 0x10); + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_RX2_B3_CTL, 0x80, 0x80); + break; + case DIG_CDC_EVENT_POST_RX1_INT_OFF: + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_RX1_B3_CTL, 0x1C, 0x00); + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_RX1_B4_CTL, 0x18, 0xFF); + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_RX1_B3_CTL, 0x80, 0x00); + break; + case DIG_CDC_EVENT_POST_RX2_INT_OFF: + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_RX2_B3_CTL, 0x1C, 0x00); + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_RX2_B4_CTL, 0x18, 0xFF); + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_RX2_B3_CTL, 0x80, 0x00); + break; + case DIG_CDC_EVENT_SSR_DOWN: + regcache_cache_only(msm_dig_cdc->regmap, true); + break; + case DIG_CDC_EVENT_SSR_UP: + regcache_cache_only(msm_dig_cdc->regmap, false); + regcache_mark_dirty(msm_dig_cdc->regmap); + regcache_sync(msm_dig_cdc->regmap); + break; + case DIG_CDC_EVENT_INVALID: + default: + break; + } + return 0; +} + +static ssize_t msm_dig_codec_version_read(struct snd_info_entry *entry, + void *file_private_data, + struct file *file, + char __user *buf, size_t count, + loff_t pos) +{ + struct msm_dig_priv *msm_dig; + char buffer[MSM_DIG_CDC_VERSION_ENTRY_SIZE]; + int len = 0; + + msm_dig = (struct msm_dig_priv *) entry->private_data; + if (!msm_dig) { + pr_err("%s: msm_dig priv is null\n", __func__); + return -EINVAL; + } + + switch (msm_dig->version) { + case DRAX_CDC: + len = snprintf(buffer, sizeof(buffer), "DRAX_CDC_1_0\n"); + break; + default: + len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n"); + } + + return simple_read_from_buffer(buf, count, &pos, buffer, len); +} + +static struct snd_info_entry_ops msm_dig_codec_info_ops = { + .read = msm_dig_codec_version_read, +}; + +/* + * msm_dig_codec_info_create_codec_entry - creates msm_dig module + * @codec_root: The parent directory + * @codec: Codec instance + * + * Creates msm_dig module and version entry under the given + * parent directory. + * + * Return: 0 on success or negative error code on failure. + */ +int msm_dig_codec_info_create_codec_entry(struct snd_info_entry *codec_root, + struct snd_soc_codec *codec) +{ + struct snd_info_entry *version_entry; + struct msm_dig_priv *msm_dig; + struct snd_soc_card *card; + + if (!codec_root || !codec) + return -EINVAL; + + msm_dig = snd_soc_codec_get_drvdata(codec); + card = codec->component.card; + msm_dig->entry = snd_register_module_info(codec_root->module, + "msm_digital", + codec_root); + if (!msm_dig->entry) { + dev_dbg(codec->dev, "%s: failed to create msm_digital entry\n", + __func__); + return -ENOMEM; + } + + version_entry = snd_info_create_card_entry(card->snd_card, + "version", + msm_dig->entry); + if (!version_entry) { + dev_dbg(codec->dev, "%s: failed to create msm_digital version entry\n", + __func__); + return -ENOMEM; + } + + version_entry->private_data = msm_dig; + version_entry->size = MSM_DIG_CDC_VERSION_ENTRY_SIZE; + version_entry->content = SNDRV_INFO_CONTENT_DATA; + version_entry->c.ops = &msm_dig_codec_info_ops; + + if (snd_info_register(version_entry) < 0) { + snd_info_free_entry(version_entry); + return -ENOMEM; + } + msm_dig->version_entry = version_entry; + return 0; +} +EXPORT_SYMBOL(msm_dig_codec_info_create_codec_entry); + +static int msm_dig_cdc_soc_probe(struct snd_soc_codec *codec) +{ + struct msm_dig_priv *dig_cdc = NULL; + struct msm_dig *msm_dig_cdc = dev_get_drvdata(codec->dev); + int i, ret; + + dig_cdc = devm_kzalloc(codec->dev, sizeof(struct msm_dig_priv), + GFP_KERNEL); + if (!dig_cdc) + return -ENOMEM; + snd_soc_codec_set_drvdata(codec, dig_cdc); + dig_cdc->codec = codec; + codec->control_data = msm_dig_cdc; + + snd_soc_add_codec_controls(codec, compander_kcontrols, + ARRAY_SIZE(compander_kcontrols)); + + for (i = 0; i < NUM_DECIMATORS; i++) { + tx_hpf_work[i].dig_cdc = dig_cdc; + tx_hpf_work[i].decimator = i + 1; + INIT_DELAYED_WORK(&tx_hpf_work[i].dwork, + tx_hpf_corner_freq_callback); + } + + for (i = 0; i < MSM89XX_RX_MAX; i++) + dig_cdc->comp_enabled[i] = COMPANDER_NONE; + + /* Register event notifier */ + msm_dig_cdc->nblock.notifier_call = msm_dig_cdc_event_notify; + if (msm_dig_cdc->register_notifier) { + ret = msm_dig_cdc->register_notifier(msm_dig_cdc->handle, + &msm_dig_cdc->nblock, + true); + if (ret) { + pr_err("%s: Failed to register notifier %d\n", + __func__, ret); + return ret; + } + } + if (msm_dig_cdc->get_cdc_version) + dig_cdc->version = msm_dig_cdc->get_cdc_version( + msm_dig_cdc->handle); + registered_digcodec = codec; + return 0; +} + +static int msm_dig_cdc_soc_remove(struct snd_soc_codec *codec) +{ + struct msm_dig *msm_dig_cdc = dev_get_drvdata(codec->dev); + + if (msm_dig_cdc->register_notifier) + msm_dig_cdc->register_notifier(msm_dig_cdc->handle, + &msm_dig_cdc->nblock, + false); + iounmap(msm_dig_cdc->dig_base); + return 0; +} + +static const struct snd_soc_dapm_route audio_dig_map[] = { + {"RX_I2S_CLK", NULL, "CDC_CONN"}, + {"I2S RX1", NULL, "RX_I2S_CLK"}, + {"I2S RX2", NULL, "RX_I2S_CLK"}, + {"I2S RX3", NULL, "RX_I2S_CLK"}, + + {"I2S TX1", NULL, "TX_I2S_CLK"}, + {"I2S TX2", NULL, "TX_I2S_CLK"}, + {"I2S TX3", NULL, "TX_I2S_CLK"}, + {"I2S TX4", NULL, "TX_I2S_CLK"}, + {"I2S TX5", NULL, "TX_I2S_CLK"}, + {"I2S TX6", NULL, "TX_I2S_CLK"}, + + {"I2S TX1", NULL, "DEC1 MUX"}, + {"I2S TX2", NULL, "DEC2 MUX"}, + {"I2S TX3", NULL, "DEC3 MUX"}, + {"I2S TX4", NULL, "DEC4 MUX"}, + {"I2S TX5", NULL, "DEC3 MUX"}, + {"I2S TX6", NULL, "DEC4 MUX"}, + {"I2S TX6", NULL, "DEC5 MUX"}, + + {"PDM_OUT_RX1", NULL, "RX1 CHAIN"}, + {"PDM_OUT_RX2", NULL, "RX2 CHAIN"}, + {"PDM_OUT_RX3", NULL, "RX3 CHAIN"}, + + {"RX1 CHAIN", NULL, "RX1 MIX2"}, + {"RX2 CHAIN", NULL, "RX2 MIX2"}, + {"RX3 CHAIN", NULL, "RX3 MIX1"}, + + {"RX1 MIX1", NULL, "RX1 MIX1 INP1"}, + {"RX1 MIX1", NULL, "RX1 MIX1 INP2"}, + {"RX1 MIX1", NULL, "RX1 MIX1 INP3"}, + {"RX2 MIX1", NULL, "RX2 MIX1 INP1"}, + {"RX2 MIX1", NULL, "RX2 MIX1 INP2"}, + {"RX3 MIX1", NULL, "RX3 MIX1 INP1"}, + {"RX3 MIX1", NULL, "RX3 MIX1 INP2"}, + {"RX1 MIX2", NULL, "RX1 MIX1"}, + {"RX1 MIX2", NULL, "RX1 MIX2 INP1"}, + {"RX2 MIX2", NULL, "RX2 MIX1"}, + {"RX2 MIX2", NULL, "RX2 MIX2 INP1"}, + + {"RX1 MIX1 INP1", "RX1", "I2S RX1"}, + {"RX1 MIX1 INP1", "RX2", "I2S RX2"}, + {"RX1 MIX1 INP1", "RX3", "I2S RX3"}, + {"RX1 MIX1 INP1", "IIR1", "IIR1"}, + {"RX1 MIX1 INP1", "IIR2", "IIR2"}, + {"RX1 MIX1 INP2", "RX1", "I2S RX1"}, + {"RX1 MIX1 INP2", "RX2", "I2S RX2"}, + {"RX1 MIX1 INP2", "RX3", "I2S RX3"}, + {"RX1 MIX1 INP2", "IIR1", "IIR1"}, + {"RX1 MIX1 INP2", "IIR2", "IIR2"}, + {"RX1 MIX1 INP3", "RX1", "I2S RX1"}, + {"RX1 MIX1 INP3", "RX2", "I2S RX2"}, + {"RX1 MIX1 INP3", "RX3", "I2S RX3"}, + + {"RX2 MIX1 INP1", "RX1", "I2S RX1"}, + {"RX2 MIX1 INP1", "RX2", "I2S RX2"}, + {"RX2 MIX1 INP1", "RX3", "I2S RX3"}, + {"RX2 MIX1 INP1", "IIR1", "IIR1"}, + {"RX2 MIX1 INP1", "IIR2", "IIR2"}, + {"RX2 MIX1 INP2", "RX1", "I2S RX1"}, + {"RX2 MIX1 INP2", "RX2", "I2S RX2"}, + {"RX2 MIX1 INP2", "RX3", "I2S RX3"}, + {"RX2 MIX1 INP2", "IIR1", "IIR1"}, + {"RX2 MIX1 INP2", "IIR2", "IIR2"}, + + {"RX3 MIX1 INP1", "RX1", "I2S RX1"}, + {"RX3 MIX1 INP1", "RX2", "I2S RX2"}, + {"RX3 MIX1 INP1", "RX3", "I2S RX3"}, + {"RX3 MIX1 INP1", "IIR1", "IIR1"}, + {"RX3 MIX1 INP1", "IIR2", "IIR2"}, + {"RX3 MIX1 INP2", "RX1", "I2S RX1"}, + {"RX3 MIX1 INP2", "RX2", "I2S RX2"}, + {"RX3 MIX1 INP2", "RX3", "I2S RX3"}, + {"RX3 MIX1 INP2", "IIR1", "IIR1"}, + {"RX3 MIX1 INP2", "IIR2", "IIR2"}, + + {"RX1 MIX2 INP1", "IIR1", "IIR1"}, + {"RX2 MIX2 INP1", "IIR1", "IIR1"}, + {"RX1 MIX2 INP1", "IIR2", "IIR2"}, + {"RX2 MIX2 INP1", "IIR2", "IIR2"}, + + /* Decimator Inputs */ + {"DEC1 MUX", "DMIC1", "DMIC1"}, + {"DEC1 MUX", "DMIC2", "DMIC2"}, + {"DEC1 MUX", "DMIC3", "DMIC3"}, + {"DEC1 MUX", "DMIC4", "DMIC4"}, + {"DEC1 MUX", "ADC1", "ADC1_IN"}, + {"DEC1 MUX", "ADC2", "ADC2_IN"}, + {"DEC1 MUX", "ADC3", "ADC3_IN"}, + {"DEC1 MUX", NULL, "CDC_CONN"}, + + {"DEC2 MUX", "DMIC1", "DMIC1"}, + {"DEC2 MUX", "DMIC2", "DMIC2"}, + {"DEC2 MUX", "DMIC3", "DMIC3"}, + {"DEC2 MUX", "DMIC4", "DMIC4"}, + {"DEC2 MUX", "ADC1", "ADC1_IN"}, + {"DEC2 MUX", "ADC2", "ADC2_IN"}, + {"DEC2 MUX", "ADC3", "ADC3_IN"}, + {"DEC2 MUX", NULL, "CDC_CONN"}, + + {"DEC3 MUX", "DMIC1", "DMIC1"}, + {"DEC3 MUX", "DMIC2", "DMIC2"}, + {"DEC3 MUX", "DMIC3", "DMIC3"}, + {"DEC3 MUX", "DMIC4", "DMIC4"}, + {"DEC3 MUX", "ADC1", "ADC1_IN"}, + {"DEC3 MUX", "ADC2", "ADC2_IN"}, + {"DEC3 MUX", "ADC3", "ADC3_IN"}, + {"DEC3 MUX", NULL, "CDC_CONN"}, + + {"DEC4 MUX", "DMIC1", "DMIC1"}, + {"DEC4 MUX", "DMIC2", "DMIC2"}, + {"DEC4 MUX", "DMIC3", "DMIC3"}, + {"DEC4 MUX", "DMIC4", "DMIC4"}, + {"DEC4 MUX", "ADC1", "ADC1_IN"}, + {"DEC4 MUX", "ADC2", "ADC2_IN"}, + {"DEC4 MUX", "ADC3", "ADC3_IN"}, + {"DEC4 MUX", NULL, "CDC_CONN"}, + + {"DEC5 MUX", "DMIC1", "DMIC1"}, + {"DEC5 MUX", "DMIC2", "DMIC2"}, + {"DEC5 MUX", "DMIC3", "DMIC3"}, + {"DEC5 MUX", "DMIC4", "DMIC4"}, + {"DEC5 MUX", "ADC1", "ADC1_IN"}, + {"DEC5 MUX", "ADC2", "ADC2_IN"}, + {"DEC5 MUX", "ADC3", "ADC3_IN"}, + {"DEC5 MUX", NULL, "CDC_CONN"}, + + {"IIR1", NULL, "IIR1 INP1 MUX"}, + {"IIR1 INP1 MUX", "DEC1", "DEC1 MUX"}, + {"IIR1 INP1 MUX", "DEC2", "DEC2 MUX"}, + {"IIR1 INP1 MUX", "DEC3", "DEC3 MUX"}, + {"IIR1 INP1 MUX", "DEC4", "DEC4 MUX"}, + {"IIR2", NULL, "IIR2 INP1 MUX"}, + {"IIR2 INP1 MUX", "DEC1", "DEC1 MUX"}, + {"IIR2 INP1 MUX", "DEC2", "DEC2 MUX"}, + {"IIR1 INP1 MUX", "DEC3", "DEC3 MUX"}, + {"IIR1 INP1 MUX", "DEC4", "DEC4 MUX"}, +}; + +static const char * const rx_mix1_text[] = { + "ZERO", "IIR1", "IIR2", "RX1", "RX2", "RX3" +}; + +static const char * const rx_mix2_text[] = { + "ZERO", "IIR1", "IIR2" +}; + +static const char * const dec_mux_text[] = { + "ZERO", "ADC1", "ADC2", "ADC3", "DMIC1", "DMIC2", "DMIC3", "DMIC4" +}; + +static const char * const iir_inp1_text[] = { + "ZERO", "DEC1", "DEC2", "RX1", "RX2", "RX3", "DEC3", "DEC4" +}; +/* RX1 MIX1 */ +static const struct soc_enum rx_mix1_inp1_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX1_B1_CTL, + 0, 6, rx_mix1_text); + +static const struct soc_enum rx_mix1_inp2_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX1_B1_CTL, + 3, 6, rx_mix1_text); + +static const struct soc_enum rx_mix1_inp3_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX1_B2_CTL, + 0, 6, rx_mix1_text); + +/* RX1 MIX2 */ +static const struct soc_enum rx_mix2_inp1_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX1_B3_CTL, + 0, 3, rx_mix2_text); + +/* RX2 MIX1 */ +static const struct soc_enum rx2_mix1_inp1_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX2_B1_CTL, + 0, 6, rx_mix1_text); + +static const struct soc_enum rx2_mix1_inp2_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX2_B1_CTL, + 3, 6, rx_mix1_text); + +static const struct soc_enum rx2_mix1_inp3_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX2_B1_CTL, + 0, 6, rx_mix1_text); + +/* RX2 MIX2 */ +static const struct soc_enum rx2_mix2_inp1_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX2_B3_CTL, + 0, 3, rx_mix2_text); + +/* RX3 MIX1 */ +static const struct soc_enum rx3_mix1_inp1_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX3_B1_CTL, + 0, 6, rx_mix1_text); + +static const struct soc_enum rx3_mix1_inp2_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX3_B1_CTL, + 3, 6, rx_mix1_text); + +static const struct soc_enum rx3_mix1_inp3_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX3_B1_CTL, + 0, 6, rx_mix1_text); + +/* DEC */ +static const struct soc_enum dec1_mux_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_TX_B1_CTL, + 0, 8, dec_mux_text); + +static const struct soc_enum dec2_mux_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_TX_B1_CTL, + 3, 8, dec_mux_text); + +static const struct soc_enum dec3_mux_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_TX_B2_CTL, + 0, 8, dec_mux_text); + +static const struct soc_enum dec4_mux_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_TX_B2_CTL, + 3, 8, dec_mux_text); + +static const struct soc_enum decsva_mux_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_TX_B3_CTL, + 0, 8, dec_mux_text); + +static const struct soc_enum iir1_inp1_mux_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL, + 0, 8, iir_inp1_text); + +static const struct soc_enum iir2_inp1_mux_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL, + 0, 8, iir_inp1_text); + +/*cut of frequency for high pass filter*/ +static const char * const cf_text[] = { + "MIN_3DB_4Hz", "MIN_3DB_75Hz", "MIN_3DB_150Hz" +}; + +static const struct soc_enum cf_rxmix1_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_RX1_B4_CTL, 0, 3, cf_text); + +static const struct soc_enum cf_rxmix2_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_RX2_B4_CTL, 0, 3, cf_text); + +static const struct soc_enum cf_rxmix3_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_RX3_B4_CTL, 0, 3, cf_text); + +static const struct snd_kcontrol_new rx3_mix1_inp1_mux = + SOC_DAPM_ENUM("RX3 MIX1 INP1 Mux", rx3_mix1_inp1_chain_enum); + +#define MSM89XX_DEC_ENUM(xname, xenum) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_info_enum_double, \ + .get = snd_soc_dapm_get_enum_double, \ + .put = msm_dig_cdc_put_dec_enum, \ + .private_value = (unsigned long)&xenum } + +static const struct snd_kcontrol_new dec1_mux = + MSM89XX_DEC_ENUM("DEC1 MUX Mux", dec1_mux_enum); + +static const struct snd_kcontrol_new dec2_mux = + MSM89XX_DEC_ENUM("DEC2 MUX Mux", dec2_mux_enum); + +static const struct snd_kcontrol_new dec3_mux = + MSM89XX_DEC_ENUM("DEC3 MUX Mux", dec3_mux_enum); + +static const struct snd_kcontrol_new dec4_mux = + MSM89XX_DEC_ENUM("DEC4 MUX Mux", dec4_mux_enum); + +static const struct snd_kcontrol_new decsva_mux = + MSM89XX_DEC_ENUM("DEC5 MUX Mux", decsva_mux_enum); + +static const struct snd_kcontrol_new iir1_inp1_mux = + SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum); + +static const struct snd_kcontrol_new iir2_inp1_mux = + SOC_DAPM_ENUM("IIR2 INP1 Mux", iir2_inp1_mux_enum); + +static const struct snd_kcontrol_new rx_mix1_inp1_mux = + SOC_DAPM_ENUM("RX1 MIX1 INP1 Mux", rx_mix1_inp1_chain_enum); + +static const struct snd_kcontrol_new rx_mix1_inp2_mux = + SOC_DAPM_ENUM("RX1 MIX1 INP2 Mux", rx_mix1_inp2_chain_enum); + +static const struct snd_kcontrol_new rx_mix1_inp3_mux = + SOC_DAPM_ENUM("RX1 MIX1 INP3 Mux", rx_mix1_inp3_chain_enum); + +static const struct snd_kcontrol_new rx2_mix1_inp1_mux = + SOC_DAPM_ENUM("RX2 MIX1 INP1 Mux", rx2_mix1_inp1_chain_enum); + +static const struct snd_kcontrol_new rx2_mix1_inp2_mux = + SOC_DAPM_ENUM("RX2 MIX1 INP2 Mux", rx2_mix1_inp2_chain_enum); + +static const struct snd_kcontrol_new rx2_mix1_inp3_mux = + SOC_DAPM_ENUM("RX2 MIX1 INP3 Mux", rx2_mix1_inp3_chain_enum); + +static const struct snd_kcontrol_new rx3_mix1_inp2_mux = + SOC_DAPM_ENUM("RX3 MIX1 INP2 Mux", rx3_mix1_inp2_chain_enum); + +static const struct snd_kcontrol_new rx3_mix1_inp3_mux = + SOC_DAPM_ENUM("RX3 MIX1 INP3 Mux", rx3_mix1_inp3_chain_enum); + +static const struct snd_kcontrol_new rx1_mix2_inp1_mux = + SOC_DAPM_ENUM("RX1 MIX2 INP1 Mux", rx_mix2_inp1_chain_enum); + +static const struct snd_kcontrol_new rx2_mix2_inp1_mux = + SOC_DAPM_ENUM("RX2 MIX2 INP1 Mux", rx2_mix2_inp1_chain_enum); + +static const struct snd_soc_dapm_widget msm_dig_dapm_widgets[] = { + SND_SOC_DAPM_AIF_IN("I2S RX1", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("I2S RX2", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("I2S RX3", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), + + SND_SOC_DAPM_AIF_OUT("I2S TX1", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("I2S TX2", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("I2S TX3", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("I2S TX4", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("I2S TX5", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("I2S TX6", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), + + SND_SOC_DAPM_MIXER_E("RX1 MIX2", MSM89XX_CDC_CORE_CLK_RX_B1_CTL, + MSM89XX_RX1, 0, NULL, 0, + msm_dig_cdc_codec_enable_interpolator, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_MIXER_E("RX2 MIX2", MSM89XX_CDC_CORE_CLK_RX_B1_CTL, + MSM89XX_RX2, 0, NULL, 0, + msm_dig_cdc_codec_enable_interpolator, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_MIXER_E("RX3 MIX1", MSM89XX_CDC_CORE_CLK_RX_B1_CTL, + MSM89XX_RX3, 0, NULL, 0, + msm_dig_cdc_codec_enable_interpolator, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MIXER("RX1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_MIXER("RX2 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), + + SND_SOC_DAPM_MIXER_E("RX1 CHAIN", MSM89XX_CDC_CORE_RX1_B6_CTL, + MSM89XX_RX1, 0, NULL, 0, + msm_dig_cdc_codec_enable_rx_chain, + SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_MIXER_E("RX2 CHAIN", MSM89XX_CDC_CORE_RX2_B6_CTL, + MSM89XX_RX2, 0, NULL, 0, + msm_dig_cdc_codec_enable_rx_chain, SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_MIXER_E("RX3 CHAIN", MSM89XX_CDC_CORE_RX3_B6_CTL, + MSM89XX_RX3, 0, NULL, 0, + msm_dig_cdc_codec_enable_rx_chain, SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MUX("RX1 MIX1 INP1", SND_SOC_NOPM, 0, 0, + &rx_mix1_inp1_mux), + SND_SOC_DAPM_MUX("RX1 MIX1 INP2", SND_SOC_NOPM, 0, 0, + &rx_mix1_inp2_mux), + SND_SOC_DAPM_MUX("RX1 MIX1 INP3", SND_SOC_NOPM, 0, 0, + &rx_mix1_inp3_mux), + + SND_SOC_DAPM_MUX("RX2 MIX1 INP1", SND_SOC_NOPM, 0, 0, + &rx2_mix1_inp1_mux), + SND_SOC_DAPM_MUX("RX2 MIX1 INP2", SND_SOC_NOPM, 0, 0, + &rx2_mix1_inp2_mux), + SND_SOC_DAPM_MUX("RX2 MIX1 INP3", SND_SOC_NOPM, 0, 0, + &rx2_mix1_inp3_mux), + + SND_SOC_DAPM_MUX("RX3 MIX1 INP1", SND_SOC_NOPM, 0, 0, + &rx3_mix1_inp1_mux), + SND_SOC_DAPM_MUX("RX3 MIX1 INP2", SND_SOC_NOPM, 0, 0, + &rx3_mix1_inp2_mux), + SND_SOC_DAPM_MUX("RX3 MIX1 INP3", SND_SOC_NOPM, 0, 0, + &rx3_mix1_inp3_mux), + + SND_SOC_DAPM_MUX("RX1 MIX2 INP1", SND_SOC_NOPM, 0, 0, + &rx1_mix2_inp1_mux), + SND_SOC_DAPM_MUX("RX2 MIX2 INP1", SND_SOC_NOPM, 0, 0, + &rx2_mix2_inp1_mux), + + SND_SOC_DAPM_SUPPLY_S("CDC_CONN", -2, MSM89XX_CDC_CORE_CLK_OTHR_CTL, + 2, 0, NULL, 0), + + SND_SOC_DAPM_MUX_E("DEC1 MUX", + MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 0, 0, + &dec1_mux, msm_dig_cdc_codec_enable_dec, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MUX_E("DEC2 MUX", + MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 1, 0, + &dec2_mux, msm_dig_cdc_codec_enable_dec, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MUX_E("DEC3 MUX", + MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 2, 0, + &dec3_mux, msm_dig_cdc_codec_enable_dec, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MUX_E("DEC4 MUX", + MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 3, 0, + &dec4_mux, msm_dig_cdc_codec_enable_dec, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MUX_E("DEC5 MUX", + MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 4, 0, + &decsva_mux, msm_dig_cdc_codec_enable_dec, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), + + /* Sidetone */ + SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux), + SND_SOC_DAPM_PGA_E("IIR1", MSM89XX_CDC_CORE_CLK_SD_CTL, 0, 0, NULL, 0, + msm_dig_cdc_codec_set_iir_gain, SND_SOC_DAPM_POST_PMU), + + SND_SOC_DAPM_MUX("IIR2 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir2_inp1_mux), + SND_SOC_DAPM_PGA_E("IIR2", MSM89XX_CDC_CORE_CLK_SD_CTL, 1, 0, NULL, 0, + msm_dig_cdc_codec_set_iir_gain, SND_SOC_DAPM_POST_PMU), + + SND_SOC_DAPM_SUPPLY("RX_I2S_CLK", + MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 4, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("TX_I2S_CLK", + MSM89XX_CDC_CORE_CLK_TX_I2S_CTL, 4, 0, NULL, 0), + + /* Digital Mic Inputs */ + SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, + msm_dig_cdc_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0, + msm_dig_cdc_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0, + msm_dig_cdc_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0, + msm_dig_cdc_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_INPUT("ADC1_IN"), + SND_SOC_DAPM_INPUT("ADC2_IN"), + SND_SOC_DAPM_INPUT("ADC3_IN"), + SND_SOC_DAPM_OUTPUT("PDM_OUT_RX1"), + SND_SOC_DAPM_OUTPUT("PDM_OUT_RX2"), + SND_SOC_DAPM_OUTPUT("PDM_OUT_RX3"), +}; + +static const struct soc_enum cf_dec1_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX1_MUX_CTL, 4, 3, cf_text); + +static const struct soc_enum cf_dec2_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX2_MUX_CTL, 4, 3, cf_text); + +static const struct soc_enum cf_dec3_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX3_MUX_CTL, 4, 3, cf_text); + +static const struct soc_enum cf_dec4_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX4_MUX_CTL, 4, 3, cf_text); + +static const struct soc_enum cf_decsva_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX5_MUX_CTL, 4, 3, cf_text); + +static const struct snd_kcontrol_new msm_dig_snd_controls[] = { + SOC_SINGLE_SX_TLV("DEC1 Volume", + MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("DEC2 Volume", + MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("DEC3 Volume", + MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("DEC4 Volume", + MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("DEC5 Volume", + MSM89XX_CDC_CORE_TX5_VOL_CTL_GAIN, + 0, -84, 40, digital_gain), + + SOC_SINGLE_SX_TLV("IIR1 INP1 Volume", + MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("IIR1 INP2 Volume", + MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("IIR1 INP3 Volume", + MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("IIR1 INP4 Volume", + MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("IIR2 INP1 Volume", + MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL, + 0, -84, 40, digital_gain), + + SOC_SINGLE_SX_TLV("RX1 Digital Volume", + MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("RX2 Digital Volume", + MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("RX3 Digital Volume", + MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL, + 0, -84, 40, digital_gain), + + SOC_SINGLE_EXT("IIR1 Enable Band1", IIR1, BAND1, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + SOC_SINGLE_EXT("IIR1 Enable Band2", IIR1, BAND2, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + SOC_SINGLE_EXT("IIR1 Enable Band3", IIR1, BAND3, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + SOC_SINGLE_EXT("IIR1 Enable Band4", IIR1, BAND4, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + SOC_SINGLE_EXT("IIR1 Enable Band5", IIR1, BAND5, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + + SOC_SINGLE_EXT("IIR2 Enable Band1", IIR2, BAND1, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + SOC_SINGLE_EXT("IIR2 Enable Band2", IIR2, BAND2, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + SOC_SINGLE_EXT("IIR2 Enable Band3", IIR2, BAND3, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + SOC_SINGLE_EXT("IIR2 Enable Band4", IIR2, BAND4, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + SOC_SINGLE_EXT("IIR2 Enable Band5", IIR2, BAND5, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + + SOC_SINGLE_MULTI_EXT("IIR1 Band1", IIR1, BAND1, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + SOC_SINGLE_MULTI_EXT("IIR1 Band2", IIR1, BAND2, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + SOC_SINGLE_MULTI_EXT("IIR1 Band3", IIR1, BAND3, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + SOC_SINGLE_MULTI_EXT("IIR1 Band4", IIR1, BAND4, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + SOC_SINGLE_MULTI_EXT("IIR1 Band5", IIR1, BAND5, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + + SOC_SINGLE_MULTI_EXT("IIR2 Band1", IIR2, BAND1, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + SOC_SINGLE_MULTI_EXT("IIR2 Band2", IIR2, BAND2, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + SOC_SINGLE_MULTI_EXT("IIR2 Band3", IIR2, BAND3, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + SOC_SINGLE_MULTI_EXT("IIR2 Band4", IIR2, BAND4, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + SOC_SINGLE_MULTI_EXT("IIR2 Band5", IIR2, BAND5, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + + SOC_SINGLE("RX1 HPF Switch", + MSM89XX_CDC_CORE_RX1_B5_CTL, 2, 1, 0), + SOC_SINGLE("RX2 HPF Switch", + MSM89XX_CDC_CORE_RX2_B5_CTL, 2, 1, 0), + SOC_SINGLE("RX3 HPF Switch", + MSM89XX_CDC_CORE_RX3_B5_CTL, 2, 1, 0), + + SOC_ENUM("RX1 HPF cut off", cf_rxmix1_enum), + SOC_ENUM("RX2 HPF cut off", cf_rxmix2_enum), + SOC_ENUM("RX3 HPF cut off", cf_rxmix3_enum), + + SOC_ENUM("TX1 HPF cut off", cf_dec1_enum), + SOC_ENUM("TX2 HPF cut off", cf_dec2_enum), + SOC_ENUM("TX3 HPF cut off", cf_dec3_enum), + SOC_ENUM("TX4 HPF cut off", cf_dec4_enum), + SOC_ENUM("TX5 HPF cut off", cf_decsva_enum), + SOC_SINGLE("TX1 HPF Switch", + MSM89XX_CDC_CORE_TX1_MUX_CTL, 3, 1, 0), + SOC_SINGLE("TX2 HPF Switch", + MSM89XX_CDC_CORE_TX2_MUX_CTL, 3, 1, 0), + SOC_SINGLE("TX3 HPF Switch", + MSM89XX_CDC_CORE_TX3_MUX_CTL, 3, 1, 0), + SOC_SINGLE("TX4 HPF Switch", + MSM89XX_CDC_CORE_TX4_MUX_CTL, 3, 1, 0), + SOC_SINGLE("TX5 HPF Switch", + MSM89XX_CDC_CORE_TX5_MUX_CTL, 3, 1, 0), +}; + +static int msm_dig_cdc_digital_mute(struct snd_soc_dai *dai, int mute) +{ + struct snd_soc_codec *codec = NULL; + u16 tx_vol_ctl_reg = 0; + u8 decimator = 0, i; + struct msm_dig_priv *dig_cdc; + + pr_debug("%s: Digital Mute val = %d\n", __func__, mute); + + if (!dai || !dai->codec) { + pr_err("%s: Invalid params\n", __func__); + return -EINVAL; + } + codec = dai->codec; + dig_cdc = snd_soc_codec_get_drvdata(codec); + + if (dai->id == AIF1_PB) { + dev_dbg(codec->dev, "%s: Not capture use case skip\n", + __func__); + return 0; + } + + mute = (mute) ? 1 : 0; + if (!mute) { + /* + * 15 ms is an emperical value for the mute time + * that was arrived by checking the pop level + * to be inaudible + */ + usleep_range(15000, 15010); + } + + if (dai->id == AIF3_SVA) { + snd_soc_update_bits(codec, + MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG, 0x01, mute); + goto ret; + } + for (i = 0; i < (NUM_DECIMATORS - 1); i++) { + if (dig_cdc->dec_active[i]) + decimator = i + 1; + if (decimator && decimator < NUM_DECIMATORS) { + /* mute/unmute decimators corresponding to Tx DAI's */ + tx_vol_ctl_reg = + MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG + + 32 * (decimator - 1); + snd_soc_update_bits(codec, tx_vol_ctl_reg, + 0x01, mute); + } + decimator = 0; + } +ret: + return 0; +} + +static struct snd_soc_dai_ops msm_dig_dai_ops = { + .hw_params = msm_dig_cdc_hw_params, + .digital_mute = msm_dig_cdc_digital_mute, +}; + + +static struct snd_soc_dai_driver msm_codec_dais[] = { + { + .name = "msm_dig_cdc_dai_rx1", + .id = AIF1_PB, + .playback = { /* Support maximum range */ + .stream_name = "AIF1 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .ops = &msm_dig_dai_ops, + }, + { + .name = "msm_dig_cdc_dai_tx1", + .id = AIF1_CAP, + .capture = { /* Support maximum range */ + .stream_name = "AIF1 Capture", + .channels_min = 1, + .channels_max = 4, + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .ops = &msm_dig_dai_ops, + }, + { + .name = "msm_dig_cdc_dai_tx2", + .id = AIF3_SVA, + .capture = { /* Support maximum range */ + .stream_name = "AIF2 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .ops = &msm_dig_dai_ops, + }, + { + .name = "msm_dig_cdc_dai_vifeed", + .id = AIF2_VIFEED, + .capture = { /* Support maximum range */ + .stream_name = "AIF2 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .ops = &msm_dig_dai_ops, + }, +}; + +static struct regmap *msm_digital_get_regmap(struct device *dev) +{ + struct msm_dig *msm_dig_cdc = dev_get_drvdata(dev); + + return msm_dig_cdc->regmap; +} + +static struct snd_soc_codec_driver soc_msm_dig_codec = { + .probe = msm_dig_cdc_soc_probe, + .remove = msm_dig_cdc_soc_remove, + .controls = msm_dig_snd_controls, + .num_controls = ARRAY_SIZE(msm_dig_snd_controls), + .dapm_widgets = msm_dig_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(msm_dig_dapm_widgets), + .dapm_routes = audio_dig_map, + .num_dapm_routes = ARRAY_SIZE(audio_dig_map), + .get_regmap = msm_digital_get_regmap, +}; + +const struct regmap_config msm_digital_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .lock = enable_digital_callback, + .unlock = disable_digital_callback, + .cache_type = REGCACHE_FLAT, + .reg_defaults = msm89xx_cdc_core_defaults, + .num_reg_defaults = MSM89XX_CDC_CORE_MAX_REGISTER, + .readable_reg = msm89xx_cdc_core_readable_reg, + .volatile_reg = msm89xx_cdc_core_volatile_reg, + .reg_format_endian = REGMAP_ENDIAN_NATIVE, + .val_format_endian = REGMAP_ENDIAN_NATIVE, + .max_register = MSM89XX_CDC_CORE_MAX_REGISTER, +}; + +static int msm_dig_cdc_probe(struct platform_device *pdev) +{ + int ret; + u32 dig_cdc_addr; + struct msm_dig *msm_dig_cdc; + struct dig_ctrl_platform_data *pdata; + + msm_dig_cdc = devm_kzalloc(&pdev->dev, sizeof(struct msm_dig), + GFP_KERNEL); + if (!msm_dig_cdc) + return -ENOMEM; + pdata = dev_get_platdata(&pdev->dev); + if (!pdata) { + dev_err(&pdev->dev, "%s: pdata from parent is NULL\n", + __func__); + ret = -EINVAL; + goto rtn; + } + dev_set_drvdata(&pdev->dev, msm_dig_cdc); + + ret = of_property_read_u32(pdev->dev.of_node, "reg", + &dig_cdc_addr); + if (ret) { + dev_err(&pdev->dev, "%s: could not find %s entry in dt\n", + __func__, "reg"); + return ret; + } + + msm_dig_cdc->dig_base = ioremap(dig_cdc_addr, + MSM89XX_CDC_CORE_MAX_REGISTER); + if (msm_dig_cdc->dig_base == NULL) { + dev_err(&pdev->dev, "%s ioremap failed\n", __func__); + return -ENOMEM; + } + msm_dig_cdc->regmap = + devm_regmap_init_mmio_clk(&pdev->dev, NULL, + msm_dig_cdc->dig_base, &msm_digital_regmap_config); + + msm_dig_cdc->update_clkdiv = pdata->update_clkdiv; + msm_dig_cdc->get_cdc_version = pdata->get_cdc_version; + msm_dig_cdc->handle = pdata->handle; + msm_dig_cdc->register_notifier = pdata->register_notifier; + + snd_soc_register_codec(&pdev->dev, &soc_msm_dig_codec, + msm_codec_dais, ARRAY_SIZE(msm_codec_dais)); + dev_dbg(&pdev->dev, "%s: registered DIG CODEC 0x%x\n", + __func__, dig_cdc_addr); +rtn: + return ret; +} + +static int msm_dig_cdc_remove(struct platform_device *pdev) +{ + snd_soc_unregister_codec(&pdev->dev); + return 0; +} + +static const struct of_device_id msm_dig_cdc_of_match[] = { + {.compatible = "qcom,msm-digital-codec"}, + {}, +}; + +static struct platform_driver msm_digcodec_driver = { + .driver = { + .owner = THIS_MODULE, + .name = DRV_NAME, + .of_match_table = msm_dig_cdc_of_match, + }, + .probe = msm_dig_cdc_probe, + .remove = msm_dig_cdc_remove, +}; +module_platform_driver(msm_digcodec_driver); + +MODULE_DESCRIPTION("MSM Audio Digital codec driver"); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/codecs/sdm660_cdc/msm-digital-cdc.h b/sound/soc/codecs/sdm660_cdc/msm-digital-cdc.h new file mode 100644 index 000000000000..4cb82cd421b0 --- /dev/null +++ b/sound/soc/codecs/sdm660_cdc/msm-digital-cdc.h @@ -0,0 +1,93 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef MSM_DIGITAL_CDC_H +#define MSM_DIGITAL_CDC_H + +#define HPHL_PA_DISABLE (0x01 << 1) +#define HPHR_PA_DISABLE (0x01 << 2) +#define SPKR_PA_DISABLE (0x01 << 3) + +#define NUM_DECIMATORS 5 +/* Codec supports 1 compander */ +enum { + COMPANDER_NONE = 0, + COMPANDER_1, /* HPHL/R */ + COMPANDER_MAX, +}; + +/* Number of output I2S port */ +enum { + MSM89XX_RX1 = 0, + MSM89XX_RX2, + MSM89XX_RX3, + MSM89XX_RX_MAX, +}; + +struct msm_dig_priv { + struct snd_soc_codec *codec; + u32 comp_enabled[MSM89XX_RX_MAX]; + int (*codec_hph_comp_gpio)(bool enable, struct snd_soc_codec *codec); + s32 dmic_1_2_clk_cnt; + s32 dmic_3_4_clk_cnt; + bool dec_active[NUM_DECIMATORS]; + int version; + /* Entry for version info */ + struct snd_info_entry *entry; + struct snd_info_entry *version_entry; +}; + +struct msm_dig { + char __iomem *dig_base; + struct regmap *regmap; + struct notifier_block nblock; + u32 mute_mask; + void *handle; + void (*update_clkdiv)(void *handle, int val); + int (*get_cdc_version)(void *handle); + int (*register_notifier)(void *handle, + struct notifier_block *nblock, + bool enable); +}; + +struct dig_ctrl_platform_data { + void *handle; + void (*update_clkdiv)(void *handle, int val); + int (*get_cdc_version)(void *handle); + int (*register_notifier)(void *handle, + struct notifier_block *nblock, + bool enable); +}; + +struct hpf_work { + struct msm_dig_priv *dig_cdc; + u32 decimator; + u8 tx_hpf_cut_of_freq; + struct delayed_work dwork; +}; + +/* Codec supports 5 bands */ +enum { + BAND1 = 0, + BAND2, + BAND3, + BAND4, + BAND5, + BAND_MAX, +}; + +extern void msm_dig_cdc_hph_comp_cb( + int (*codec_hph_comp_gpio)( + bool enable, struct snd_soc_codec *codec), + struct snd_soc_codec *codec); +int msm_dig_codec_info_create_codec_entry(struct snd_info_entry *codec_root, + struct snd_soc_codec *codec); +#endif diff --git a/sound/soc/codecs/sdm660_cdc/sdm660-cdc-irq.c b/sound/soc/codecs/sdm660_cdc/sdm660-cdc-irq.c new file mode 100644 index 000000000000..63a715c5248c --- /dev/null +++ b/sound/soc/codecs/sdm660_cdc/sdm660-cdc-irq.c @@ -0,0 +1,441 @@ +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "msm-analog-cdc.h" +#include "sdm660-cdc-irq.h" +#include "sdm660-cdc-registers.h" + +#define MAX_NUM_IRQS 14 +#define NUM_IRQ_REGS 2 +#define WCD9XXX_SYSTEM_RESUME_TIMEOUT_MS 700 + +#define BYTE_BIT_MASK(nr) (1UL << ((nr) % BITS_PER_BYTE)) +#define BIT_BYTE(nr) ((nr) / BITS_PER_BYTE) + +static irqreturn_t wcd9xxx_spmi_irq_handler(int linux_irq, void *data); + +char *irq_names[MAX_NUM_IRQS] = { + "spk_cnp_int", + "spk_clip_int", + "spk_ocp_int", + "ins_rem_det1", + "but_rel_det", + "but_press_det", + "ins_rem_det", + "mbhc_int", + "ear_ocp_int", + "hphr_ocp_int", + "hphl_ocp_det", + "ear_cnp_int", + "hphr_cnp_int", + "hphl_cnp_int" +}; + +int order[MAX_NUM_IRQS] = { + MSM89XX_IRQ_SPKR_CNP, + MSM89XX_IRQ_SPKR_CLIP, + MSM89XX_IRQ_SPKR_OCP, + MSM89XX_IRQ_MBHC_INSREM_DET1, + MSM89XX_IRQ_MBHC_RELEASE, + MSM89XX_IRQ_MBHC_PRESS, + MSM89XX_IRQ_MBHC_INSREM_DET, + MSM89XX_IRQ_MBHC_HS_DET, + MSM89XX_IRQ_EAR_OCP, + MSM89XX_IRQ_HPHR_OCP, + MSM89XX_IRQ_HPHL_OCP, + MSM89XX_IRQ_EAR_CNP, + MSM89XX_IRQ_HPHR_CNP, + MSM89XX_IRQ_HPHL_CNP, +}; + +enum wcd9xxx_spmi_pm_state { + WCD9XXX_PM_SLEEPABLE, + WCD9XXX_PM_AWAKE, + WCD9XXX_PM_ASLEEP, +}; + +struct wcd9xxx_spmi_map { + uint8_t handled[NUM_IRQ_REGS]; + uint8_t mask[NUM_IRQ_REGS]; + int linuxirq[MAX_NUM_IRQS]; + irq_handler_t handler[MAX_NUM_IRQS]; + struct spmi_device *spmi[NUM_IRQ_REGS]; + struct snd_soc_codec *codec; + + enum wcd9xxx_spmi_pm_state pm_state; + struct mutex pm_lock; + /* pm_wq notifies change of pm_state */ + wait_queue_head_t pm_wq; + struct pm_qos_request pm_qos_req; + int wlock_holders; +}; + +struct wcd9xxx_spmi_map map; + +void wcd9xxx_spmi_enable_irq(int irq) +{ + pr_debug("%s: irqno =%d\n", __func__, irq); + if ((irq >= 0) && (irq <= 7)) { + snd_soc_update_bits(map.codec, + MSM89XX_PMIC_DIGITAL_INT_EN_CLR, + (0x01 << irq), 0x00); + snd_soc_update_bits(map.codec, + MSM89XX_PMIC_DIGITAL_INT_EN_SET, + (0x01 << irq), (0x01 << irq)); + } + if ((irq > 7) && (irq <= 15)) { + snd_soc_update_bits(map.codec, + MSM89XX_PMIC_ANALOG_INT_EN_CLR, + (0x01 << (irq - 8)), 0x00); + snd_soc_update_bits(map.codec, + MSM89XX_PMIC_ANALOG_INT_EN_SET, + (0x01 << (irq - 8)), (0x01 << (irq - 8))); + } + + if (!(map.mask[BIT_BYTE(irq)] & (BYTE_BIT_MASK(irq)))) + return; + + map.mask[BIT_BYTE(irq)] &= + ~(BYTE_BIT_MASK(irq)); + + enable_irq(map.linuxirq[irq]); +} + +void wcd9xxx_spmi_disable_irq(int irq) +{ + pr_debug("%s: irqno =%d\n", __func__, irq); + if ((irq >= 0) && (irq <= 7)) { + snd_soc_update_bits(map.codec, + MSM89XX_PMIC_DIGITAL_INT_EN_SET, + (0x01 << (irq)), 0x00); + snd_soc_update_bits(map.codec, + MSM89XX_PMIC_DIGITAL_INT_EN_CLR, + (0x01 << irq), (0x01 << irq)); + } + + if ((irq > 7) && (irq <= 15)) { + snd_soc_update_bits(map.codec, + MSM89XX_PMIC_ANALOG_INT_EN_SET, + (0x01 << (irq - 8)), 0x00); + snd_soc_update_bits(map.codec, + MSM89XX_PMIC_ANALOG_INT_EN_CLR, + (0x01 << (irq - 8)), (0x01 << (irq - 8))); + } + + if (map.mask[BIT_BYTE(irq)] & (BYTE_BIT_MASK(irq))) + return; + + map.mask[BIT_BYTE(irq)] |= + (BYTE_BIT_MASK(irq)); + + disable_irq_nosync(map.linuxirq[irq]); +} + +int wcd9xxx_spmi_request_irq(int irq, irq_handler_t handler, + const char *name, void *priv) +{ + int rc; + unsigned long irq_flags; + + if (strcmp(name, "mbhc sw intr")) + irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | + IRQF_ONESHOT; + else + irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | + IRQF_ONESHOT | IRQF_NO_SUSPEND; + pr_debug("%s: name:%s irq_flags = %lx\n", __func__, name, irq_flags); + + rc = devm_request_threaded_irq(&map.spmi[BIT_BYTE(irq)]->dev, + map.linuxirq[irq], NULL, + wcd9xxx_spmi_irq_handler, + irq_flags, + name, priv); + if (rc < 0) { + dev_err(&map.spmi[BIT_BYTE(irq)]->dev, + "Can't request %d IRQ\n", irq); + return rc; + } + + dev_dbg(&map.spmi[BIT_BYTE(irq)]->dev, + "irq %d linuxIRQ: %d\n", irq, map.linuxirq[irq]); + map.mask[BIT_BYTE(irq)] &= ~BYTE_BIT_MASK(irq); + map.handler[irq] = handler; + enable_irq_wake(map.linuxirq[irq]); + return 0; +} + +int wcd9xxx_spmi_free_irq(int irq, void *priv) +{ + devm_free_irq(&map.spmi[BIT_BYTE(irq)]->dev, map.linuxirq[irq], + priv); + map.mask[BIT_BYTE(irq)] |= BYTE_BIT_MASK(irq); + return 0; +} + +static int get_irq_bit(int linux_irq) +{ + int i = 0; + + for (; i < MAX_NUM_IRQS; i++) + if (map.linuxirq[i] == linux_irq) + return i; + + return i; +} + +static int get_order_irq(int i) +{ + return order[i]; +} + +static irqreturn_t wcd9xxx_spmi_irq_handler(int linux_irq, void *data) +{ + int irq, i, j; + unsigned long status[NUM_IRQ_REGS] = {0}; + + if (unlikely(wcd9xxx_spmi_lock_sleep() == false)) { + pr_err("Failed to hold suspend\n"); + return IRQ_NONE; + } + + irq = get_irq_bit(linux_irq); + if (irq == MAX_NUM_IRQS) + return IRQ_HANDLED; + + status[BIT_BYTE(irq)] |= BYTE_BIT_MASK(irq); + for (i = 0; i < NUM_IRQ_REGS; i++) { + status[i] |= snd_soc_read(map.codec, + BIT_BYTE(irq) * 0x100 + + MSM89XX_PMIC_DIGITAL_INT_LATCHED_STS); + status[i] &= ~map.mask[i]; + } + for (i = 0; i < MAX_NUM_IRQS; i++) { + j = get_order_irq(i); + if ((status[BIT_BYTE(j)] & BYTE_BIT_MASK(j)) && + ((map.handled[BIT_BYTE(j)] & + BYTE_BIT_MASK(j)) == 0)) { + map.handler[j](irq, data); + map.handled[BIT_BYTE(j)] |= + BYTE_BIT_MASK(j); + } + } + map.handled[BIT_BYTE(irq)] &= ~BYTE_BIT_MASK(irq); + wcd9xxx_spmi_unlock_sleep(); + + return IRQ_HANDLED; +} + +enum wcd9xxx_spmi_pm_state wcd9xxx_spmi_pm_cmpxchg( + enum wcd9xxx_spmi_pm_state o, + enum wcd9xxx_spmi_pm_state n) +{ + enum wcd9xxx_spmi_pm_state old; + + mutex_lock(&map.pm_lock); + old = map.pm_state; + if (old == o) + map.pm_state = n; + pr_debug("%s: map.pm_state = %d\n", __func__, map.pm_state); + mutex_unlock(&map.pm_lock); + return old; +} +EXPORT_SYMBOL(wcd9xxx_spmi_pm_cmpxchg); + +int wcd9xxx_spmi_suspend(pm_message_t pmesg) +{ + int ret = 0; + + pr_debug("%s: enter\n", __func__); + /* + * pm_qos_update_request() can be called after this suspend chain call + * started. thus suspend can be called while lock is being held + */ + mutex_lock(&map.pm_lock); + if (map.pm_state == WCD9XXX_PM_SLEEPABLE) { + pr_debug("%s: suspending system, state %d, wlock %d\n", + __func__, map.pm_state, + map.wlock_holders); + map.pm_state = WCD9XXX_PM_ASLEEP; + } else if (map.pm_state == WCD9XXX_PM_AWAKE) { + /* + * unlock to wait for pm_state == WCD9XXX_PM_SLEEPABLE + * then set to WCD9XXX_PM_ASLEEP + */ + pr_debug("%s: waiting to suspend system, state %d, wlock %d\n", + __func__, map.pm_state, + map.wlock_holders); + mutex_unlock(&map.pm_lock); + if (!(wait_event_timeout(map.pm_wq, + wcd9xxx_spmi_pm_cmpxchg( + WCD9XXX_PM_SLEEPABLE, + WCD9XXX_PM_ASLEEP) == + WCD9XXX_PM_SLEEPABLE, + HZ))) { + pr_debug("%s: suspend failed state %d, wlock %d\n", + __func__, map.pm_state, + map.wlock_holders); + ret = -EBUSY; + } else { + pr_debug("%s: done, state %d, wlock %d\n", __func__, + map.pm_state, + map.wlock_holders); + } + mutex_lock(&map.pm_lock); + } else if (map.pm_state == WCD9XXX_PM_ASLEEP) { + pr_warn("%s: system is already suspended, state %d, wlock %dn", + __func__, map.pm_state, + map.wlock_holders); + } + mutex_unlock(&map.pm_lock); + + return ret; +} +EXPORT_SYMBOL(wcd9xxx_spmi_suspend); + +int wcd9xxx_spmi_resume(void) +{ + int ret = 0; + + pr_debug("%s: enter\n", __func__); + mutex_lock(&map.pm_lock); + if (map.pm_state == WCD9XXX_PM_ASLEEP) { + pr_debug("%s: resuming system, state %d, wlock %d\n", __func__, + map.pm_state, + map.wlock_holders); + map.pm_state = WCD9XXX_PM_SLEEPABLE; + } else { + pr_warn("%s: system is already awake, state %d wlock %d\n", + __func__, map.pm_state, + map.wlock_holders); + } + mutex_unlock(&map.pm_lock); + wake_up_all(&map.pm_wq); + + return ret; +} +EXPORT_SYMBOL(wcd9xxx_spmi_resume); + +bool wcd9xxx_spmi_lock_sleep(void) +{ + /* + * wcd9xxx_spmi_{lock/unlock}_sleep will be called by + * wcd9xxx_spmi_irq_thread + * and its subroutines only motly. + * but btn0_lpress_fn is not wcd9xxx_spmi_irq_thread's subroutine and + * It can race with wcd9xxx_spmi_irq_thread. + * So need to embrace wlock_holders with mutex. + */ + mutex_lock(&map.pm_lock); + if (map.wlock_holders++ == 0) { + pr_debug("%s: holding wake lock\n", __func__); + pm_qos_update_request(&map.pm_qos_req, + msm_cpuidle_get_deep_idle_latency()); + pm_stay_awake(&map.spmi[0]->dev); + } + mutex_unlock(&map.pm_lock); + pr_debug("%s: wake lock counter %d\n", __func__, + map.wlock_holders); + pr_debug("%s: map.pm_state = %d\n", __func__, map.pm_state); + + if (!wait_event_timeout(map.pm_wq, + ((wcd9xxx_spmi_pm_cmpxchg( + WCD9XXX_PM_SLEEPABLE, + WCD9XXX_PM_AWAKE)) == + WCD9XXX_PM_SLEEPABLE || + (wcd9xxx_spmi_pm_cmpxchg( + WCD9XXX_PM_SLEEPABLE, + WCD9XXX_PM_AWAKE) == + WCD9XXX_PM_AWAKE)), + msecs_to_jiffies( + WCD9XXX_SYSTEM_RESUME_TIMEOUT_MS))) { + pr_warn("%s: system didn't resume within %dms, s %d, w %d\n", + __func__, + WCD9XXX_SYSTEM_RESUME_TIMEOUT_MS, map.pm_state, + map.wlock_holders); + wcd9xxx_spmi_unlock_sleep(); + return false; + } + wake_up_all(&map.pm_wq); + pr_debug("%s: leaving pm_state = %d\n", __func__, map.pm_state); + return true; +} +EXPORT_SYMBOL(wcd9xxx_spmi_lock_sleep); + +void wcd9xxx_spmi_unlock_sleep(void) +{ + mutex_lock(&map.pm_lock); + if (--map.wlock_holders == 0) { + pr_debug("%s: releasing wake lock pm_state %d -> %d\n", + __func__, map.pm_state, WCD9XXX_PM_SLEEPABLE); + /* + * if wcd9xxx_spmi_lock_sleep failed, pm_state would be still + * WCD9XXX_PM_ASLEEP, don't overwrite + */ + if (likely(map.pm_state == WCD9XXX_PM_AWAKE)) + map.pm_state = WCD9XXX_PM_SLEEPABLE; + pm_qos_update_request(&map.pm_qos_req, + PM_QOS_DEFAULT_VALUE); + pm_relax(&map.spmi[0]->dev); + } + mutex_unlock(&map.pm_lock); + pr_debug("%s: wake lock counter %d\n", __func__, + map.wlock_holders); + pr_debug("%s: map.pm_state = %d\n", __func__, map.pm_state); + wake_up_all(&map.pm_wq); +} +EXPORT_SYMBOL(wcd9xxx_spmi_unlock_sleep); + +void wcd9xxx_spmi_set_codec(struct snd_soc_codec *codec) +{ + map.codec = codec; +} + +void wcd9xxx_spmi_set_dev(struct spmi_device *spmi, int i) +{ + if (i < NUM_IRQ_REGS) + map.spmi[i] = spmi; +} + +int wcd9xxx_spmi_irq_init(void) +{ + int i = 0; + + for (; i < MAX_NUM_IRQS; i++) + map.mask[BIT_BYTE(i)] |= BYTE_BIT_MASK(i); + mutex_init(&map.pm_lock); + map.wlock_holders = 0; + map.pm_state = WCD9XXX_PM_SLEEPABLE; + init_waitqueue_head(&map.pm_wq); + pm_qos_add_request(&map.pm_qos_req, + PM_QOS_CPU_DMA_LATENCY, + PM_QOS_DEFAULT_VALUE); + + return 0; +} + +MODULE_DESCRIPTION("MSM8x16 SPMI IRQ driver"); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/codecs/sdm660_cdc/sdm660-cdc-irq.h b/sound/soc/codecs/sdm660_cdc/sdm660-cdc-irq.h new file mode 100644 index 000000000000..659e52cc2a5e --- /dev/null +++ b/sound/soc/codecs/sdm660_cdc/sdm660-cdc-irq.h @@ -0,0 +1,34 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __WCD9XXX_SPMI_IRQ_H__ +#define __WCD9XXX_SPMI_IRQ_H__ + +#include +#include +#include +#include +#include + +extern void wcd9xxx_spmi_enable_irq(int irq); +extern void wcd9xxx_spmi_disable_irq(int irq); +extern int wcd9xxx_spmi_request_irq(int irq, irq_handler_t handler, + const char *name, void *priv); +extern int wcd9xxx_spmi_free_irq(int irq, void *priv); +extern void wcd9xxx_spmi_set_codec(struct snd_soc_codec *codec); +extern void wcd9xxx_spmi_set_dev(struct spmi_device *spmi, int i); +extern int wcd9xxx_spmi_irq_init(void); +extern int wcd9xxx_spmi_suspend(pm_message_t); +extern int wcd9xxx_spmi_resume(void); +bool wcd9xxx_spmi_lock_sleep(void); +void wcd9xxx_spmi_unlock_sleep(void); + +#endif diff --git a/sound/soc/codecs/sdm660_cdc/sdm660-cdc-registers.h b/sound/soc/codecs/sdm660_cdc/sdm660-cdc-registers.h new file mode 100644 index 000000000000..5e042e2d466a --- /dev/null +++ b/sound/soc/codecs/sdm660_cdc/sdm660-cdc-registers.h @@ -0,0 +1,603 @@ + /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef SDM660_WCD_REGISTERS_H +#define SDM660_WCD_REGISTERS_H + +#define CDC_DIG_BASE 0xF000 +#define CDC_ANA_BASE 0xF100 + +#define MSM89XX_PMIC_DIGITAL_REVISION1 (CDC_DIG_BASE+0x000) +#define MSM89XX_PMIC_DIGITAL_REVISION1__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_REVISION2 (CDC_DIG_BASE+0x001) +#define MSM89XX_PMIC_DIGITAL_REVISION2__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_PERPH_TYPE (CDC_DIG_BASE+0x004) +#define MSM89XX_PMIC_DIGITAL_PERPH_TYPE__POR (0x23) +#define MSM89XX_PMIC_DIGITAL_PERPH_SUBTYPE (CDC_DIG_BASE+0x005) +#define MSM89XX_PMIC_DIGITAL_PERPH_SUBTYPE__POR (0x01) +#define MSM89XX_PMIC_DIGITAL_INT_RT_STS (CDC_DIG_BASE+0x010) +#define MSM89XX_PMIC_DIGITAL_INT_RT_STS__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_INT_SET_TYPE (CDC_DIG_BASE+0x011) +#define MSM89XX_PMIC_DIGITAL_INT_SET_TYPE__POR (0xFF) +#define MSM89XX_PMIC_DIGITAL_INT_POLARITY_HIGH (CDC_DIG_BASE+0x012) +#define MSM89XX_PMIC_DIGITAL_INT_POLARITY_HIGH__POR (0xFF) +#define MSM89XX_PMIC_DIGITAL_INT_POLARITY_LOW (CDC_DIG_BASE+0x013) +#define MSM89XX_PMIC_DIGITAL_INT_POLARITY_LOW__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_INT_LATCHED_CLR (CDC_DIG_BASE+0x014) +#define MSM89XX_PMIC_DIGITAL_INT_LATCHED_CLR__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_INT_EN_SET (CDC_DIG_BASE+0x015) +#define MSM89XX_PMIC_DIGITAL_INT_EN_SET__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_INT_EN_CLR (CDC_DIG_BASE+0x016) +#define MSM89XX_PMIC_DIGITAL_INT_EN_CLR__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_INT_LATCHED_STS (CDC_DIG_BASE+0x018) +#define MSM89XX_PMIC_DIGITAL_INT_LATCHED_STS__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_INT_PENDING_STS (CDC_DIG_BASE+0x019) +#define MSM89XX_PMIC_DIGITAL_INT_PENDING_STS__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_INT_MID_SEL (CDC_DIG_BASE+0x01A) +#define MSM89XX_PMIC_DIGITAL_INT_MID_SEL__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_INT_PRIORITY (CDC_DIG_BASE+0x01B) +#define MSM89XX_PMIC_DIGITAL_INT_PRIORITY__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_GPIO_MODE (CDC_DIG_BASE+0x040) +#define MSM89XX_PMIC_DIGITAL_GPIO_MODE__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_PIN_CTL_OE (CDC_DIG_BASE+0x041) +#define MSM89XX_PMIC_DIGITAL_PIN_CTL_OE__POR (0x01) +#define MSM89XX_PMIC_DIGITAL_PIN_CTL_DATA (CDC_DIG_BASE+0x042) +#define MSM89XX_PMIC_DIGITAL_PIN_CTL_DATA__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_PIN_STATUS (CDC_DIG_BASE+0x043) +#define MSM89XX_PMIC_DIGITAL_PIN_STATUS__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_HDRIVE_CTL (CDC_DIG_BASE+0x044) +#define MSM89XX_PMIC_DIGITAL_HDRIVE_CTL__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_CDC_RST_CTL (CDC_DIG_BASE+0x046) +#define MSM89XX_PMIC_DIGITAL_CDC_RST_CTL__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL (CDC_DIG_BASE+0x048) +#define MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL (CDC_DIG_BASE+0x049) +#define MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL (CDC_DIG_BASE+0x04A) +#define MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_CDC_CONN_TX1_CTL (CDC_DIG_BASE+0x050) +#define MSM89XX_PMIC_DIGITAL_CDC_CONN_TX1_CTL__POR (0x02) +#define MSM89XX_PMIC_DIGITAL_CDC_CONN_TX2_CTL (CDC_DIG_BASE+0x051) +#define MSM89XX_PMIC_DIGITAL_CDC_CONN_TX2_CTL__POR (0x02) +#define MSM89XX_PMIC_DIGITAL_CDC_CONN_HPHR_DAC_CTL (CDC_DIG_BASE+0x052) +#define MSM89XX_PMIC_DIGITAL_CDC_CONN_HPHR_DAC_CTL__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX1_CTL (CDC_DIG_BASE+0x053) +#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX1_CTL__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX2_CTL (CDC_DIG_BASE+0x054) +#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX2_CTL__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX3_CTL (CDC_DIG_BASE+0x055) +#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX3_CTL__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX_LB_CTL (CDC_DIG_BASE+0x056) +#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX_LB_CTL__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL1 (CDC_DIG_BASE+0x058) +#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL1__POR (0x7C) +#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL2 (CDC_DIG_BASE+0x059) +#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL2__POR (0x7C) +#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL3 (CDC_DIG_BASE+0x05A) +#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL3__POR (0x7C) +#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA0 (CDC_DIG_BASE+0x05B) +#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA0__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA1 (CDC_DIG_BASE+0x05C) +#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA1__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA2 (CDC_DIG_BASE+0x05D) +#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA2__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA3 (CDC_DIG_BASE+0x05E) +#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA3__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_DIG_DEBUG_CTL (CDC_DIG_BASE+0x068) +#define MSM89XX_PMIC_DIGITAL_DIG_DEBUG_CTL__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_DIG_DEBUG_EN (CDC_DIG_BASE+0x069) +#define MSM89XX_PMIC_DIGITAL_DIG_DEBUG_EN__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_SPARE_0 (CDC_DIG_BASE+0x070) +#define MSM89XX_PMIC_DIGITAL_SPARE_0__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_SPARE_1 (CDC_DIG_BASE+0x071) +#define MSM89XX_PMIC_DIGITAL_SPARE_1__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_SPARE_2 (CDC_DIG_BASE+0x072) +#define MSM89XX_PMIC_DIGITAL_SPARE_2__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_SEC_ACCESS (CDC_DIG_BASE+0x0D0) +#define MSM89XX_PMIC_DIGITAL_SEC_ACCESS__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL1 (CDC_DIG_BASE+0x0D8) +#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL1__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL2 (CDC_DIG_BASE+0x0D9) +#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL2__POR (0x01) +#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3 (CDC_DIG_BASE+0x0DA) +#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3__POR (0x05) +#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL4 (CDC_DIG_BASE+0x0DB) +#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL4__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_INT_TEST1 (CDC_DIG_BASE+0x0E0) +#define MSM89XX_PMIC_DIGITAL_INT_TEST1__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_INT_TEST_VAL (CDC_DIG_BASE+0x0E1) +#define MSM89XX_PMIC_DIGITAL_INT_TEST_VAL__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_TRIM_NUM (CDC_DIG_BASE+0x0F0) +#define MSM89XX_PMIC_DIGITAL_TRIM_NUM__POR (0x00) +#define MSM89XX_PMIC_DIGITAL_TRIM_CTRL (CDC_DIG_BASE+0x0F1) +#define MSM89XX_PMIC_DIGITAL_TRIM_CTRL__POR (0x00) + +#define MSM89XX_PMIC_ANALOG_REVISION1 (CDC_ANA_BASE+0x00) +#define MSM89XX_PMIC_ANALOG_REVISION1__POR (0x00) +#define MSM89XX_PMIC_ANALOG_REVISION2 (CDC_ANA_BASE+0x01) +#define MSM89XX_PMIC_ANALOG_REVISION2__POR (0x00) +#define MSM89XX_PMIC_ANALOG_REVISION3 (CDC_ANA_BASE+0x02) +#define MSM89XX_PMIC_ANALOG_REVISION3__POR (0x00) +#define MSM89XX_PMIC_ANALOG_REVISION4 (CDC_ANA_BASE+0x03) +#define MSM89XX_PMIC_ANALOG_REVISION4__POR (0x00) +#define MSM89XX_PMIC_ANALOG_PERPH_TYPE (CDC_ANA_BASE+0x04) +#define MSM89XX_PMIC_ANALOG_PERPH_TYPE__POR (0x23) +#define MSM89XX_PMIC_ANALOG_PERPH_SUBTYPE (CDC_ANA_BASE+0x05) +#define MSM89XX_PMIC_ANALOG_PERPH_SUBTYPE__POR (0x09) +#define MSM89XX_PMIC_ANALOG_INT_RT_STS (CDC_ANA_BASE+0x10) +#define MSM89XX_PMIC_ANALOG_INT_RT_STS__POR (0x00) +#define MSM89XX_PMIC_ANALOG_INT_SET_TYPE (CDC_ANA_BASE+0x11) +#define MSM89XX_PMIC_ANALOG_INT_SET_TYPE__POR (0x3F) +#define MSM89XX_PMIC_ANALOG_INT_POLARITY_HIGH (CDC_ANA_BASE+0x12) +#define MSM89XX_PMIC_ANALOG_INT_POLARITY_HIGH__POR (0x3F) +#define MSM89XX_PMIC_ANALOG_INT_POLARITY_LOW (CDC_ANA_BASE+0x13) +#define MSM89XX_PMIC_ANALOG_INT_POLARITY_LOW__POR (0x00) +#define MSM89XX_PMIC_ANALOG_INT_LATCHED_CLR (CDC_ANA_BASE+0x14) +#define MSM89XX_PMIC_ANALOG_INT_LATCHED_CLR__POR (0x00) +#define MSM89XX_PMIC_ANALOG_INT_EN_SET (CDC_ANA_BASE+0x15) +#define MSM89XX_PMIC_ANALOG_INT_EN_SET__POR (0x00) +#define MSM89XX_PMIC_ANALOG_INT_EN_CLR (CDC_ANA_BASE+0x16) +#define MSM89XX_PMIC_ANALOG_INT_EN_CLR__POR (0x00) +#define MSM89XX_PMIC_ANALOG_INT_LATCHED_STS (CDC_ANA_BASE+0x18) +#define MSM89XX_PMIC_ANALOG_INT_LATCHED_STS__POR (0x00) +#define MSM89XX_PMIC_ANALOG_INT_PENDING_STS (CDC_ANA_BASE+0x19) +#define MSM89XX_PMIC_ANALOG_INT_PENDING_STS__POR (0x00) +#define MSM89XX_PMIC_ANALOG_INT_MID_SEL (CDC_ANA_BASE+0x1A) +#define MSM89XX_PMIC_ANALOG_INT_MID_SEL__POR (0x00) +#define MSM89XX_PMIC_ANALOG_INT_PRIORITY (CDC_ANA_BASE+0x1B) +#define MSM89XX_PMIC_ANALOG_INT_PRIORITY__POR (0x00) +#define MSM89XX_PMIC_ANALOG_MICB_1_EN (CDC_ANA_BASE+0x40) +#define MSM89XX_PMIC_ANALOG_MICB_1_EN__POR (0x00) +#define MSM89XX_PMIC_ANALOG_MICB_1_VAL (CDC_ANA_BASE+0x41) +#define MSM89XX_PMIC_ANALOG_MICB_1_VAL__POR (0x20) +#define MSM89XX_PMIC_ANALOG_MICB_1_CTL (CDC_ANA_BASE+0x42) +#define MSM89XX_PMIC_ANALOG_MICB_1_CTL__POR (0x00) +#define MSM89XX_PMIC_ANALOG_MICB_1_INT_RBIAS (CDC_ANA_BASE+0x43) +#define MSM89XX_PMIC_ANALOG_MICB_1_INT_RBIAS__POR (0x49) +#define MSM89XX_PMIC_ANALOG_MICB_2_EN (CDC_ANA_BASE+0x44) +#define MSM89XX_PMIC_ANALOG_MICB_2_EN__POR (0x20) +#define MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2 (CDC_ANA_BASE+0x45) +#define MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2__POR (0x00) +#define MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL (CDC_ANA_BASE+0x46) +#define MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL__POR (0x00) +#define MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1 (CDC_ANA_BASE+0x47) +#define MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1__POR (0x35) +#define MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2 (CDC_ANA_BASE+0x50) +#define MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2__POR (0x08) +#define MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL (CDC_ANA_BASE+0x51) +#define MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL__POR (0x00) +#define MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER (CDC_ANA_BASE+0x52) +#define MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER__POR (0x98) +#define MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL (CDC_ANA_BASE+0x53) +#define MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL__POR (0x00) +#define MSM89XX_PMIC_ANALOG_MBHC_BTN1_ZDETM_CTL (CDC_ANA_BASE+0x54) +#define MSM89XX_PMIC_ANALOG_MBHC_BTN1_ZDETM_CTL__POR (0x20) +#define MSM89XX_PMIC_ANALOG_MBHC_BTN2_ZDETH_CTL (CDC_ANA_BASE+0x55) +#define MSM89XX_PMIC_ANALOG_MBHC_BTN2_ZDETH_CTL__POR (0x40) +#define MSM89XX_PMIC_ANALOG_MBHC_BTN3_CTL (CDC_ANA_BASE+0x56) +#define MSM89XX_PMIC_ANALOG_MBHC_BTN3_CTL__POR (0x61) +#define MSM89XX_PMIC_ANALOG_MBHC_BTN4_CTL (CDC_ANA_BASE+0x57) +#define MSM89XX_PMIC_ANALOG_MBHC_BTN4_CTL__POR (0x80) +#define MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT (CDC_ANA_BASE+0x58) +#define MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT__POR (0x00) +#define MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT (CDC_ANA_BASE+0x59) +#define MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT__POR (0x00) +#define MSM89XX_PMIC_ANALOG_TX_1_EN (CDC_ANA_BASE+0x60) +#define MSM89XX_PMIC_ANALOG_TX_1_EN__POR (0x03) +#define MSM89XX_PMIC_ANALOG_TX_2_EN (CDC_ANA_BASE+0x61) +#define MSM89XX_PMIC_ANALOG_TX_2_EN__POR (0x03) +#define MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_1 (CDC_ANA_BASE+0x62) +#define MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_1__POR (0xBF) +#define MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_2 (CDC_ANA_BASE+0x63) +#define MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_2__POR (0x8C) +#define MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL (CDC_ANA_BASE+0x64) +#define MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL__POR (0x00) +#define MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS (CDC_ANA_BASE+0x65) +#define MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS__POR (0x6B) +#define MSM89XX_PMIC_ANALOG_TX_1_2_TXFE_CLKDIV (CDC_ANA_BASE+0x66) +#define MSM89XX_PMIC_ANALOG_TX_1_2_TXFE_CLKDIV__POR (0x51) +#define MSM89XX_PMIC_ANALOG_TX_3_EN (CDC_ANA_BASE+0x67) +#define MSM89XX_PMIC_ANALOG_TX_3_EN__POR (0x02) +#define MSM89XX_PMIC_ANALOG_NCP_EN (CDC_ANA_BASE+0x80) +#define MSM89XX_PMIC_ANALOG_NCP_EN__POR (0x26) +#define MSM89XX_PMIC_ANALOG_NCP_CLK (CDC_ANA_BASE+0x81) +#define MSM89XX_PMIC_ANALOG_NCP_CLK__POR (0x23) +#define MSM89XX_PMIC_ANALOG_NCP_DEGLITCH (CDC_ANA_BASE+0x82) +#define MSM89XX_PMIC_ANALOG_NCP_DEGLITCH__POR (0x5B) +#define MSM89XX_PMIC_ANALOG_NCP_FBCTRL (CDC_ANA_BASE+0x83) +#define MSM89XX_PMIC_ANALOG_NCP_FBCTRL__POR (0x08) +#define MSM89XX_PMIC_ANALOG_NCP_BIAS (CDC_ANA_BASE+0x84) +#define MSM89XX_PMIC_ANALOG_NCP_BIAS__POR (0x29) +#define MSM89XX_PMIC_ANALOG_NCP_VCTRL (CDC_ANA_BASE+0x85) +#define MSM89XX_PMIC_ANALOG_NCP_VCTRL__POR (0x24) +#define MSM89XX_PMIC_ANALOG_NCP_TEST (CDC_ANA_BASE+0x86) +#define MSM89XX_PMIC_ANALOG_NCP_TEST__POR (0x00) +#define MSM89XX_PMIC_ANALOG_NCP_CLIM_ADDR (CDC_ANA_BASE+0x87) +#define MSM89XX_PMIC_ANALOG_NCP_CLIM_ADDR__POR (0xD5) +#define MSM89XX_PMIC_ANALOG_RX_CLOCK_DIVIDER (CDC_ANA_BASE+0x90) +#define MSM89XX_PMIC_ANALOG_RX_CLOCK_DIVIDER__POR (0xE8) +#define MSM89XX_PMIC_ANALOG_RX_COM_OCP_CTL (CDC_ANA_BASE+0x91) +#define MSM89XX_PMIC_ANALOG_RX_COM_OCP_CTL__POR (0xCF) +#define MSM89XX_PMIC_ANALOG_RX_COM_OCP_COUNT (CDC_ANA_BASE+0x92) +#define MSM89XX_PMIC_ANALOG_RX_COM_OCP_COUNT__POR (0x6E) +#define MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC (CDC_ANA_BASE+0x93) +#define MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC__POR (0x18) +#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_PA (CDC_ANA_BASE+0x94) +#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_PA__POR (0x5A) +#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_LDO_OCP (CDC_ANA_BASE+0x95) +#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_LDO_OCP__POR (0x69) +#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_CNP (CDC_ANA_BASE+0x96) +#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_CNP__POR (0x29) +#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN (CDC_ANA_BASE+0x97) +#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN__POR (0x80) +#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_CTL (CDC_ANA_BASE+0x98) +#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_CTL__POR (0xDA) +#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME (CDC_ANA_BASE+0x99) +#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME__POR (0x16) +#define MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST (CDC_ANA_BASE+0x9A) +#define MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST__POR (0x00) +#define MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL (CDC_ANA_BASE+0x9B) +#define MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL__POR (0x20) +#define MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST (CDC_ANA_BASE+0x9C) +#define MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST__POR (0x00) +#define MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL (CDC_ANA_BASE+0x9D) +#define MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL__POR (0x20) +#define MSM89XX_PMIC_ANALOG_RX_EAR_CTL (CDC_ANA_BASE+0x9E) +#define MSM89XX_PMIC_ANALOG_RX_EAR_CTL___POR (0x12) +#define MSM89XX_PMIC_ANALOG_RX_ATEST (CDC_ANA_BASE+0x9F) +#define MSM89XX_PMIC_ANALOG_RX_ATEST__POR (0x00) +#define MSM89XX_PMIC_ANALOG_RX_HPH_STATUS (CDC_ANA_BASE+0xA0) +#define MSM89XX_PMIC_ANALOG_RX_HPH_STATUS__POR (0x0C) +#define MSM89XX_PMIC_ANALOG_RX_EAR_STATUS (CDC_ANA_BASE+0xA1) +#define MSM89XX_PMIC_ANALOG_RX_EAR_STATUS__POR (0x00) +#define MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL (CDC_ANA_BASE+0xAC) +#define MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL__POR (0x00) +#define MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL (CDC_ANA_BASE+0xAD) +#define MSM89XX_PMIC_ANALOG_RX_RX_LO_EN_CTL__POR (0x00) +#define MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL (CDC_ANA_BASE+0xB0) +#define MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL__POR (0x83) +#define MSM89XX_PMIC_ANALOG_SPKR_DRV_CLIP_DET (CDC_ANA_BASE+0xB1) +#define MSM89XX_PMIC_ANALOG_SPKR_DRV_CLIP_DET__POR (0x91) +#define MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL (CDC_ANA_BASE+0xB2) +#define MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL__POR (0x29) +#define MSM89XX_PMIC_ANALOG_SPKR_ANA_BIAS_SET (CDC_ANA_BASE+0xB3) +#define MSM89XX_PMIC_ANALOG_SPKR_ANA_BIAS_SET__POR (0x4D) +#define MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL (CDC_ANA_BASE+0xB4) +#define MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL__POR (0xE1) +#define MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL (CDC_ANA_BASE+0xB5) +#define MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL__POR (0x1E) +#define MSM89XX_PMIC_ANALOG_SPKR_DRV_MISC (CDC_ANA_BASE+0xB6) +#define MSM89XX_PMIC_ANALOG_SPKR_DRV_MISC__POR (0xCB) +#define MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG (CDC_ANA_BASE+0xB7) +#define MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG__POR (0x00) +#define MSM89XX_PMIC_ANALOG_CURRENT_LIMIT (CDC_ANA_BASE+0xC0) +#define MSM89XX_PMIC_ANALOG_CURRENT_LIMIT__POR (0x02) +#define MSM89XX_PMIC_ANALOG_OUTPUT_VOLTAGE (CDC_ANA_BASE+0xC1) +#define MSM89XX_PMIC_ANALOG_OUTPUT_VOLTAGE__POR (0x14) +#define MSM89XX_PMIC_ANALOG_BYPASS_MODE (CDC_ANA_BASE+0xC2) +#define MSM89XX_PMIC_ANALOG_BYPASS_MODE__POR (0x00) +#define MSM89XX_PMIC_ANALOG_BOOST_EN_CTL (CDC_ANA_BASE+0xC3) +#define MSM89XX_PMIC_ANALOG_BOOST_EN_CTL__POR (0x1F) +#define MSM89XX_PMIC_ANALOG_SLOPE_COMP_IP_ZERO (CDC_ANA_BASE+0xC4) +#define MSM89XX_PMIC_ANALOG_SLOPE_COMP_IP_ZERO__POR (0x8C) +#define MSM89XX_PMIC_ANALOG_RDSON_MAX_DUTY_CYCLE (CDC_ANA_BASE+0xC5) +#define MSM89XX_PMIC_ANALOG_RDSON_MAX_DUTY_CYCLE__POR (0xC0) +#define MSM89XX_PMIC_ANALOG_BOOST_TEST1_1 (CDC_ANA_BASE+0xC6) +#define MSM89XX_PMIC_ANALOG_BOOST_TEST1_1__POR (0x00) +#define MSM89XX_PMIC_ANALOG_BOOST_TEST_2 (CDC_ANA_BASE+0xC7) +#define MSM89XX_PMIC_ANALOG_BOOST_TEST_2__POR (0x00) +#define MSM89XX_PMIC_ANALOG_SPKR_SAR_STATUS (CDC_ANA_BASE+0xC8) +#define MSM89XX_PMIC_ANALOG_SPKR_SAR_STATUS__POR (0x00) +#define MSM89XX_PMIC_ANALOG_SPKR_DRV_STATUS (CDC_ANA_BASE+0xC9) +#define MSM89XX_PMIC_ANALOG_SPKR_DRV_STATUS__POR (0x00) +#define MSM89XX_PMIC_ANALOG_PBUS_ADD_CSR (CDC_ANA_BASE+0xCE) +#define MSM89XX_PMIC_ANALOG_PBUS_ADD_CSR__POR (0x00) +#define MSM89XX_PMIC_ANALOG_PBUS_ADD_SEL (CDC_ANA_BASE+0xCF) +#define MSM89XX_PMIC_ANALOG_PBUS_ADD_SEL__POR (0x00) +#define MSM89XX_PMIC_ANALOG_SEC_ACCESS (CDC_ANA_BASE+0xD0) +#define MSM89XX_PMIC_ANALOG_SEC_ACCESS__POR (0x00) +#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL1 (CDC_ANA_BASE+0xD8) +#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL1__POR (0x00) +#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL2 (CDC_ANA_BASE+0xD9) +#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL2__POR (0x01) +#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3 (CDC_ANA_BASE+0xDA) +#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3__POR (0x05) +#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL4 (CDC_ANA_BASE+0xDB) +#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL4__POR (0x00) +#define MSM89XX_PMIC_ANALOG_INT_TEST1 (CDC_ANA_BASE+0xE0) +#define MSM89XX_PMIC_ANALOG_INT_TEST1__POR (0x00) +#define MSM89XX_PMIC_ANALOG_INT_TEST_VAL (CDC_ANA_BASE+0xE1) +#define MSM89XX_PMIC_ANALOG_INT_TEST_VAL__POR (0x00) +#define MSM89XX_PMIC_ANALOG_TRIM_NUM (CDC_ANA_BASE+0xF0) +#define MSM89XX_PMIC_ANALOG_TRIM_NUM__POR (0x04) +#define MSM89XX_PMIC_ANALOG_TRIM_CTRL1 (CDC_ANA_BASE+0xF1) +#define MSM89XX_PMIC_ANALOG_TRIM_CTRL1__POR (0x00) +#define MSM89XX_PMIC_ANALOG_TRIM_CTRL2 (CDC_ANA_BASE+0xF2) +#define MSM89XX_PMIC_ANALOG_TRIM_CTRL2__POR (0x00) +#define MSM89XX_PMIC_ANALOG_TRIM_CTRL3 (CDC_ANA_BASE+0xF3) +#define MSM89XX_PMIC_ANALOG_TRIM_CTRL3__POR (0x00) +#define MSM89XX_PMIC_ANALOG_TRIM_CTRL4 (CDC_ANA_BASE+0xF4) +#define MSM89XX_PMIC_ANALOG_TRIM_CTRL4__POR (0x00) + +#define MSM89XX_PMIC_CDC_NUM_REGISTERS \ + (MSM89XX_PMIC_ANALOG_TRIM_CTRL4+1) +#define MSM89XX_PMIC_CDC_MAX_REGISTER \ + (MSM89XX_PMIC_CDC_NUM_REGISTERS-1) +#define MSM89XX_PMIC_CDC_CACHE_SIZE \ + MSM89XX_PMIC_CDC_NUM_REGISTERS + + +#define MSM89XX_CDC_CORE_CLK_RX_RESET_CTL (0x00) +#define MSM89XX_CDC_CORE_CLK_RX_RESET_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL (0x04) +#define MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL (0x08) +#define MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CLK_RX_I2S_CTL (0x0C) +#define MSM89XX_CDC_CORE_CLK_RX_I2S_CTL__POR (0x13) +#define MSM89XX_CDC_CORE_CLK_TX_I2S_CTL (0x10) +#define MSM89XX_CDC_CORE_CLK_TX_I2S_CTL__POR (0x13) +#define MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL (0x14) +#define MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL (0x18) +#define MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CLK_OTHR_CTL (0x1C) +#define MSM89XX_CDC_CORE_CLK_OTHR_CTL__POR (0x04) +#define MSM89XX_CDC_CORE_CLK_RX_B1_CTL (0x20) +#define MSM89XX_CDC_CORE_CLK_RX_B1_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CLK_MCLK_CTL (0x24) +#define MSM89XX_CDC_CORE_CLK_MCLK_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CLK_PDM_CTL (0x28) +#define MSM89XX_CDC_CORE_CLK_PDM_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CLK_SD_CTL (0x2C) +#define MSM89XX_CDC_CORE_CLK_SD_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL (0x30) +#define MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CLK_RX_B2_CTL (0x34) +#define MSM89XX_CDC_CORE_CLK_RX_B2_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CLK_TX2_I2S_CTL (0x38) +#define MSM89XX_CDC_CORE_CLK_TX2_I2S_CTL__POR (0x13) +#define MSM89XX_CDC_CORE_RX1_B1_CTL (0x40) +#define MSM89XX_CDC_CORE_RX1_B1_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_RX2_B1_CTL (0x60) +#define MSM89XX_CDC_CORE_RX2_B1_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_RX3_B1_CTL (0x80) +#define MSM89XX_CDC_CORE_RX3_B1_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_RX1_B2_CTL (0x44) +#define MSM89XX_CDC_CORE_RX1_B2_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_RX2_B2_CTL (0x64) +#define MSM89XX_CDC_CORE_RX2_B2_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_RX3_B2_CTL (0x84) +#define MSM89XX_CDC_CORE_RX3_B2_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_RX1_B3_CTL (0x48) +#define MSM89XX_CDC_CORE_RX1_B3_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_RX2_B3_CTL (0x68) +#define MSM89XX_CDC_CORE_RX2_B3_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_RX3_B3_CTL (0x88) +#define MSM89XX_CDC_CORE_RX3_B3_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_RX1_B4_CTL (0x4C) +#define MSM89XX_CDC_CORE_RX1_B4_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_RX2_B4_CTL (0x6C) +#define MSM89XX_CDC_CORE_RX2_B4_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_RX3_B4_CTL (0x8C) +#define MSM89XX_CDC_CORE_RX3_B4_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_RX1_B5_CTL (0x50) +#define MSM89XX_CDC_CORE_RX1_B5_CTL__POR (0x68) +#define MSM89XX_CDC_CORE_RX2_B5_CTL (0x70) +#define MSM89XX_CDC_CORE_RX2_B5_CTL__POR (0x68) +#define MSM89XX_CDC_CORE_RX3_B5_CTL (0x90) +#define MSM89XX_CDC_CORE_RX3_B5_CTL__POR (0x68) +#define MSM89XX_CDC_CORE_RX1_B6_CTL (0x54) +#define MSM89XX_CDC_CORE_RX1_B6_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_RX2_B6_CTL (0x74) +#define MSM89XX_CDC_CORE_RX2_B6_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_RX3_B6_CTL (0x94) +#define MSM89XX_CDC_CORE_RX3_B6_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL (0x58) +#define MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL (0x78) +#define MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL (0x98) +#define MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL (0x5C) +#define MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL (0x7C) +#define MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL (0x9C) +#define MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_TOP_GAIN_UPDATE (0xA0) +#define MSM89XX_CDC_CORE_TOP_GAIN_UPDATE__POR (0x00) +#define MSM89XX_CDC_CORE_TOP_CTL (0xA4) +#define MSM89XX_CDC_CORE_TOP_CTL__POR (0x01) +#define MSM89XX_CDC_CORE_COMP0_B1_CTL (0xB0) +#define MSM89XX_CDC_CORE_COMP0_B1_CTL__POR (0x30) +#define MSM89XX_CDC_CORE_COMP0_B2_CTL (0xB4) +#define MSM89XX_CDC_CORE_COMP0_B2_CTL__POR (0xB5) +#define MSM89XX_CDC_CORE_COMP0_B3_CTL (0xB8) +#define MSM89XX_CDC_CORE_COMP0_B3_CTL__POR (0x28) +#define MSM89XX_CDC_CORE_COMP0_B4_CTL (0xBC) +#define MSM89XX_CDC_CORE_COMP0_B4_CTL__POR (0x37) +#define MSM89XX_CDC_CORE_COMP0_B5_CTL (0xC0) +#define MSM89XX_CDC_CORE_COMP0_B5_CTL__POR (0x7F) +#define MSM89XX_CDC_CORE_COMP0_B6_CTL (0xC4) +#define MSM89XX_CDC_CORE_COMP0_B6_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_COMP0_SHUT_DOWN_STATUS (0xC8) +#define MSM89XX_CDC_CORE_COMP0_SHUT_DOWN_STATUS__POR (0x03) +#define MSM89XX_CDC_CORE_COMP0_FS_CFG (0xCC) +#define MSM89XX_CDC_CORE_COMP0_FS_CFG__POR (0x03) +#define MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL (0xD0) +#define MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL__POR (0x02) +#define MSM89XX_CDC_CORE_DEBUG_DESER1_CTL (0xE0) +#define MSM89XX_CDC_CORE_DEBUG_DESER1_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_DEBUG_DESER2_CTL (0xE4) +#define MSM89XX_CDC_CORE_DEBUG_DESER2_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG (0xE8) +#define MSM89XX_CDC_CORE_DEBUG_B1_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG (0xEC) +#define MSM89XX_CDC_CORE_DEBUG_B2_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG (0xF0) +#define MSM89XX_CDC_CORE_DEBUG_B3_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL (0x100) +#define MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL (0x140) +#define MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL (0x104) +#define MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL (0x144) +#define MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL (0x108) +#define MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL (0x148) +#define MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL (0x10C) +#define MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL (0x14C) +#define MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL (0x110) +#define MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL (0x150) +#define MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL (0x114) +#define MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL (0x154) +#define MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL (0x118) +#define MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL (0x158) +#define MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL (0x11C) +#define MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL (0x15C) +#define MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_IIR1_CTL (0x120) +#define MSM89XX_CDC_CORE_IIR1_CTL__POR (0x40) +#define MSM89XX_CDC_CORE_IIR2_CTL (0x160) +#define MSM89XX_CDC_CORE_IIR2_CTL__POR (0x40) +#define MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL (0x124) +#define MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL (0x164) +#define MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL (0x128) +#define MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL (0x168) +#define MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL (0x12C) +#define MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL (0x16C) +#define MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CONN_RX1_B1_CTL (0x180) +#define MSM89XX_CDC_CORE_CONN_RX1_B1_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CONN_RX1_B2_CTL (0x184) +#define MSM89XX_CDC_CORE_CONN_RX1_B2_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CONN_RX1_B3_CTL (0x188) +#define MSM89XX_CDC_CORE_CONN_RX1_B3_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CONN_RX2_B1_CTL (0x18C) +#define MSM89XX_CDC_CORE_CONN_RX2_B1_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CONN_RX2_B2_CTL (0x190) +#define MSM89XX_CDC_CORE_CONN_RX2_B2_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CONN_RX2_B3_CTL (0x194) +#define MSM89XX_CDC_CORE_CONN_RX2_B3_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CONN_RX3_B1_CTL (0x198) +#define MSM89XX_CDC_CORE_CONN_RX3_B1_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CONN_RX3_B2_CTL (0x19C) +#define MSM89XX_CDC_CORE_CONN_RX3_B2_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CONN_TX_B1_CTL (0x1A0) +#define MSM89XX_CDC_CORE_CONN_TX_B1_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CONN_TX_B2_CTL (0x1A4) +#define MSM89XX_CDC_CORE_CONN_TX_B2_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL (0x1A8) +#define MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL (0x1AC) +#define MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL (0x1B0) +#define MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL (0x1B4) +#define MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL (0x1B8) +#define MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL (0x1BC) +#define MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL (0x1C0) +#define MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL (0x1C4) +#define MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL (0x1C8) +#define MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_CONN_TX_B3_CTL (0x1CC) +#define MSM89XX_CDC_CORE_CONN_TX_B3_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_TX5_VOL_CTL_TIMER (0x1E0) +#define MSM89XX_CDC_CORE_TX5_VOL_CTL_TIMER__POR (0x00) +#define MSM89XX_CDC_CORE_TX5_VOL_CTL_GAIN (0x1E4) +#define MSM89XX_CDC_CORE_TX5_VOL_CTL_GAIN__POR (0x00) +#define MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG (0x1E8) +#define MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG__POR (0x00) +#define MSM89XX_CDC_CORE_TX5_MUX_CTL (0x1EC) +#define MSM89XX_CDC_CORE_TX5_MUX_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_TX5_CLK_FS_CTL (0x1F0) +#define MSM89XX_CDC_CORE_TX5_CLK_FS_CTL__POR (0x03) +#define MSM89XX_CDC_CORE_TX5_DMIC_CTL (0x1F4) +#define MSM89XX_CDC_CORE_TX5_DMIC_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER (0x280) +#define MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER__POR (0x00) +#define MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER (0x2A0) +#define MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER__POR (0x00) +#define MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER (0x2C0) +#define MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER__POR (0x00) +#define MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER (0x2E0) +#define MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER__POR (0x00) +#define MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN (0x284) +#define MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN__POR (0x00) +#define MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN (0x2A4) +#define MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN__POR (0x00) +#define MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN (0x2C4) +#define MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN__POR (0x00) +#define MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN (0x2E4) +#define MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN__POR (0x00) +#define MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG (0x288) +#define MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG__POR (0x00) +#define MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG (0x2A8) +#define MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG__POR (0x00) +#define MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG (0x2C8) +#define MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG__POR (0x00) +#define MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG (0x2E8) +#define MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG__POR (0x00) +#define MSM89XX_CDC_CORE_TX1_MUX_CTL (0x28C) +#define MSM89XX_CDC_CORE_TX1_MUX_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_TX2_MUX_CTL (0x2AC) +#define MSM89XX_CDC_CORE_TX2_MUX_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_TX3_MUX_CTL (0x2CC) +#define MSM89XX_CDC_CORE_TX3_MUX_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_TX4_MUX_CTL (0x2EC) +#define MSM89XX_CDC_CORE_TX4_MUX_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_TX1_CLK_FS_CTL (0x290) +#define MSM89XX_CDC_CORE_TX1_CLK_FS_CTL__POR (0x03) +#define MSM89XX_CDC_CORE_TX2_CLK_FS_CTL (0x2B0) +#define MSM89XX_CDC_CORE_TX2_CLK_FS_CTL__POR (0x03) +#define MSM89XX_CDC_CORE_TX3_CLK_FS_CTL (0x2D0) +#define MSM89XX_CDC_CORE_TX3_CLK_FS_CTL__POR (0x03) +#define MSM89XX_CDC_CORE_TX4_CLK_FS_CTL (0x2F0) +#define MSM89XX_CDC_CORE_TX4_CLK_FS_CTL__POR (0x03) +#define MSM89XX_CDC_CORE_TX1_DMIC_CTL (0x294) +#define MSM89XX_CDC_CORE_TX1_DMIC_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_TX2_DMIC_CTL (0x2B4) +#define MSM89XX_CDC_CORE_TX2_DMIC_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_TX3_DMIC_CTL (0x2D4) +#define MSM89XX_CDC_CORE_TX3_DMIC_CTL__POR (0x00) +#define MSM89XX_CDC_CORE_TX4_DMIC_CTL (0x2F4) +#define MSM89XX_CDC_CORE_TX4_DMIC_CTL__POR (0x00) + +#define MSM89XX_CDC_CORE_NUM_REGISTERS \ + (MSM89XX_CDC_CORE_TX4_DMIC_CTL+1) +#define MSM89XX_CDC_CORE_MAX_REGISTER \ + (MSM89XX_CDC_CORE_NUM_REGISTERS-1) +#define MSM89XX_CDC_CORE_CACHE_SIZE \ + MSM89XX_CDC_CORE_NUM_REGISTERS +#endif diff --git a/sound/soc/codecs/sdm660_cdc/sdm660-regmap.c b/sound/soc/codecs/sdm660_cdc/sdm660-regmap.c new file mode 100644 index 000000000000..1c3a8d2c2fd9 --- /dev/null +++ b/sound/soc/codecs/sdm660_cdc/sdm660-regmap.c @@ -0,0 +1,471 @@ +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "sdm660-cdc-registers.h" + +/* + * Default register reset values that are common across different versions + * are defined here. If a register reset value is changed based on version + * then remove it from this structure and add it in version specific + * structures. + */ +struct reg_default + msm89xx_cdc_core_defaults[MSM89XX_CDC_CORE_CACHE_SIZE] = { + {MSM89XX_CDC_CORE_CLK_RX_RESET_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 0x13}, + {MSM89XX_CDC_CORE_CLK_TX_I2S_CTL, 0x13}, + {MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_OTHR_CTL, 0x04}, + {MSM89XX_CDC_CORE_CLK_RX_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_MCLK_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_PDM_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_SD_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_RX_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_TX2_I2S_CTL, 0x13}, + {MSM89XX_CDC_CORE_RX1_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX2_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX3_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX1_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX2_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX3_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX1_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX2_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX3_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX1_B4_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX2_B4_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX3_B4_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX1_B5_CTL, 0x68}, + {MSM89XX_CDC_CORE_RX2_B5_CTL, 0x68}, + {MSM89XX_CDC_CORE_RX3_B5_CTL, 0x68}, + {MSM89XX_CDC_CORE_RX1_B6_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX2_B6_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX3_B6_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_TOP_GAIN_UPDATE, 0x00}, + {MSM89XX_CDC_CORE_TOP_CTL, 0x01}, + {MSM89XX_CDC_CORE_COMP0_B1_CTL, 0x30}, + {MSM89XX_CDC_CORE_COMP0_B2_CTL, 0xB5}, + {MSM89XX_CDC_CORE_COMP0_B3_CTL, 0x28}, + {MSM89XX_CDC_CORE_COMP0_B4_CTL, 0x37}, + {MSM89XX_CDC_CORE_COMP0_B5_CTL, 0x7F}, + {MSM89XX_CDC_CORE_COMP0_B6_CTL, 0x00}, + {MSM89XX_CDC_CORE_COMP0_SHUT_DOWN_STATUS, 0x03}, + {MSM89XX_CDC_CORE_COMP0_FS_CFG, 0x03}, + {MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL, 0x02}, + {MSM89XX_CDC_CORE_DEBUG_DESER1_CTL, 0x00}, + {MSM89XX_CDC_CORE_DEBUG_DESER2_CTL, 0x00}, + {MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG, 0x00}, + {MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG, 0x00}, + {MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG, 0x00}, + {MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_CTL, 0x40}, + {MSM89XX_CDC_CORE_IIR2_CTL, 0x40}, + {MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_RX1_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_RX1_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_RX1_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_RX2_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_RX2_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_RX2_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_RX3_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_RX3_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_TX_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_TX_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_TX_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX5_VOL_CTL_TIMER, 0x00}, + {MSM89XX_CDC_CORE_TX5_VOL_CTL_GAIN, 0x00}, + {MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG, 0x00}, + {MSM89XX_CDC_CORE_TX5_MUX_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX5_CLK_FS_CTL, 0x03}, + {MSM89XX_CDC_CORE_TX5_DMIC_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER, 0x00}, + {MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER, 0x00}, + {MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER, 0x00}, + {MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER, 0x00}, + {MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN, 0x00}, + {MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN, 0x00}, + {MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN, 0x00}, + {MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN, 0x00}, + {MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG, 0x00}, + {MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG, 0x00}, + {MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG, 0x00}, + {MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG, 0x00}, + {MSM89XX_CDC_CORE_TX1_MUX_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX2_MUX_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX3_MUX_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX4_MUX_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX1_CLK_FS_CTL, 0x03}, + {MSM89XX_CDC_CORE_TX2_CLK_FS_CTL, 0x03}, + {MSM89XX_CDC_CORE_TX3_CLK_FS_CTL, 0x03}, + {MSM89XX_CDC_CORE_TX4_CLK_FS_CTL, 0x03}, + {MSM89XX_CDC_CORE_TX1_DMIC_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX2_DMIC_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX3_DMIC_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX4_DMIC_CTL, 0x00}, +}; + +struct reg_default + msm89xx_pmic_cdc_defaults[MSM89XX_PMIC_CDC_CACHE_SIZE] = { + {MSM89XX_PMIC_DIGITAL_REVISION1, 0x00}, + {MSM89XX_PMIC_DIGITAL_REVISION2, 0x00}, + {MSM89XX_PMIC_DIGITAL_PERPH_TYPE, 0x23}, + {MSM89XX_PMIC_DIGITAL_PERPH_SUBTYPE, 0x01}, + {MSM89XX_PMIC_DIGITAL_INT_RT_STS, 0x00}, + {MSM89XX_PMIC_DIGITAL_INT_SET_TYPE, 0xFF}, + {MSM89XX_PMIC_DIGITAL_INT_POLARITY_HIGH, 0xFF}, + {MSM89XX_PMIC_DIGITAL_INT_POLARITY_LOW, 0x00}, + {MSM89XX_PMIC_DIGITAL_INT_LATCHED_CLR, 0x00}, + {MSM89XX_PMIC_DIGITAL_INT_EN_SET, 0x00}, + {MSM89XX_PMIC_DIGITAL_INT_EN_CLR, 0x00}, + {MSM89XX_PMIC_DIGITAL_INT_LATCHED_STS, 0x00}, + {MSM89XX_PMIC_DIGITAL_INT_PENDING_STS, 0x00}, + {MSM89XX_PMIC_DIGITAL_INT_MID_SEL, 0x00}, + {MSM89XX_PMIC_DIGITAL_INT_PRIORITY, 0x00}, + {MSM89XX_PMIC_DIGITAL_GPIO_MODE, 0x00}, + {MSM89XX_PMIC_DIGITAL_PIN_CTL_OE, 0x01}, + {MSM89XX_PMIC_DIGITAL_PIN_CTL_DATA, 0x00}, + {MSM89XX_PMIC_DIGITAL_PIN_STATUS, 0x00}, + {MSM89XX_PMIC_DIGITAL_HDRIVE_CTL, 0x00}, + {MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x00}, + {MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL, 0x00}, + {MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x00}, + {MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x00}, + {MSM89XX_PMIC_DIGITAL_CDC_CONN_TX1_CTL, 0x02}, + {MSM89XX_PMIC_DIGITAL_CDC_CONN_TX2_CTL, 0x02}, + {MSM89XX_PMIC_DIGITAL_CDC_CONN_HPHR_DAC_CTL, 0x00}, + {MSM89XX_PMIC_DIGITAL_CDC_CONN_RX1_CTL, 0x00}, + {MSM89XX_PMIC_DIGITAL_CDC_CONN_RX2_CTL, 0x00}, + {MSM89XX_PMIC_DIGITAL_CDC_CONN_RX3_CTL, 0x00}, + {MSM89XX_PMIC_DIGITAL_CDC_CONN_RX_LB_CTL, 0x00}, + {MSM89XX_PMIC_DIGITAL_CDC_RX_CTL1, 0x7C}, + {MSM89XX_PMIC_DIGITAL_CDC_RX_CTL2, 0x7C}, + {MSM89XX_PMIC_DIGITAL_CDC_RX_CTL3, 0x7C}, + {MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA0, 0x00}, + {MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA1, 0x00}, + {MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA2, 0x00}, + {MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA3, 0x00}, + {MSM89XX_PMIC_DIGITAL_DIG_DEBUG_CTL, 0x00}, + {MSM89XX_PMIC_DIGITAL_DIG_DEBUG_EN, 0x00}, + {MSM89XX_PMIC_DIGITAL_SPARE_0, 0x00}, + {MSM89XX_PMIC_DIGITAL_SPARE_1, 0x00}, + {MSM89XX_PMIC_DIGITAL_SPARE_2, 0x00}, + {MSM89XX_PMIC_DIGITAL_SEC_ACCESS, 0x00}, + {MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL1, 0x00}, + {MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL2, 0x02}, + {MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x05}, + {MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL4, 0x00}, + {MSM89XX_PMIC_DIGITAL_INT_TEST1, 0x00}, + {MSM89XX_PMIC_DIGITAL_INT_TEST_VAL, 0x00}, + {MSM89XX_PMIC_DIGITAL_TRIM_NUM, 0x00}, + {MSM89XX_PMIC_DIGITAL_TRIM_CTRL, 0x00}, + {MSM89XX_PMIC_ANALOG_REVISION1, 0x00}, + {MSM89XX_PMIC_ANALOG_REVISION2, 0x00}, + {MSM89XX_PMIC_ANALOG_REVISION3, 0x00}, + {MSM89XX_PMIC_ANALOG_REVISION4, 0x00}, + {MSM89XX_PMIC_ANALOG_PERPH_TYPE, 0x23}, + {MSM89XX_PMIC_ANALOG_PERPH_SUBTYPE, 0x09}, + {MSM89XX_PMIC_ANALOG_INT_RT_STS, 0x00}, + {MSM89XX_PMIC_ANALOG_INT_SET_TYPE, 0x3F}, + {MSM89XX_PMIC_ANALOG_INT_POLARITY_HIGH, 0x3F}, + {MSM89XX_PMIC_ANALOG_INT_POLARITY_LOW, 0x00}, + {MSM89XX_PMIC_ANALOG_INT_LATCHED_CLR, 0x00}, + {MSM89XX_PMIC_ANALOG_INT_EN_SET, 0x00}, + {MSM89XX_PMIC_ANALOG_INT_EN_CLR, 0x00}, + {MSM89XX_PMIC_ANALOG_INT_LATCHED_STS, 0x00}, + {MSM89XX_PMIC_ANALOG_INT_PENDING_STS, 0x00}, + {MSM89XX_PMIC_ANALOG_INT_MID_SEL, 0x00}, + {MSM89XX_PMIC_ANALOG_INT_PRIORITY, 0x00}, + {MSM89XX_PMIC_ANALOG_MICB_1_EN, 0x00}, + {MSM89XX_PMIC_ANALOG_MICB_1_VAL, 0x20}, + {MSM89XX_PMIC_ANALOG_MICB_1_CTL, 0x00}, + {MSM89XX_PMIC_ANALOG_MICB_1_INT_RBIAS, 0x49}, + {MSM89XX_PMIC_ANALOG_MICB_2_EN, 0x20}, + {MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2, 0x00}, + {MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL, 0x00}, + {MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1, 0x35}, + {MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0x08}, + {MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, 0x00}, + {MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER, 0x98}, + {MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL, 0x00}, + {MSM89XX_PMIC_ANALOG_MBHC_BTN1_ZDETM_CTL, 0x20}, + {MSM89XX_PMIC_ANALOG_MBHC_BTN2_ZDETH_CTL, 0x40}, + {MSM89XX_PMIC_ANALOG_MBHC_BTN3_CTL, 0x61}, + {MSM89XX_PMIC_ANALOG_MBHC_BTN4_CTL, 0x80}, + {MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT, 0x00}, + {MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT, 0x00}, + {MSM89XX_PMIC_ANALOG_TX_1_EN, 0x03}, + {MSM89XX_PMIC_ANALOG_TX_2_EN, 0x03}, + {MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_1, 0xBF}, + {MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_2, 0x8C}, + {MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL, 0x00}, + {MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS, 0x6B}, + {MSM89XX_PMIC_ANALOG_TX_1_2_TXFE_CLKDIV, 0x51}, + {MSM89XX_PMIC_ANALOG_TX_3_EN, 0x02}, + {MSM89XX_PMIC_ANALOG_NCP_EN, 0x26}, + {MSM89XX_PMIC_ANALOG_NCP_CLK, 0x23}, + {MSM89XX_PMIC_ANALOG_NCP_DEGLITCH, 0x5B}, + {MSM89XX_PMIC_ANALOG_NCP_FBCTRL, 0x08}, + {MSM89XX_PMIC_ANALOG_NCP_BIAS, 0x29}, + {MSM89XX_PMIC_ANALOG_NCP_VCTRL, 0x24}, + {MSM89XX_PMIC_ANALOG_NCP_TEST, 0x00}, + {MSM89XX_PMIC_ANALOG_NCP_CLIM_ADDR, 0xD5}, + {MSM89XX_PMIC_ANALOG_RX_CLOCK_DIVIDER, 0xE8}, + {MSM89XX_PMIC_ANALOG_RX_COM_OCP_CTL, 0xCF}, + {MSM89XX_PMIC_ANALOG_RX_COM_OCP_COUNT, 0x6E}, + {MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, 0x18}, + {MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_PA, 0x5A}, + {MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_LDO_OCP, 0x69}, + {MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_CNP, 0x29}, + {MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, 0x80}, + {MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_CTL, 0xDA}, + {MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME, 0x16}, + {MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST, 0x00}, + {MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL, 0x20}, + {MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST, 0x00}, + {MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL, 0x20}, + {MSM89XX_PMIC_ANALOG_RX_EAR_CTL, 0x12}, + {MSM89XX_PMIC_ANALOG_RX_ATEST, 0x00}, + {MSM89XX_PMIC_ANALOG_RX_HPH_STATUS, 0x0C}, + {MSM89XX_PMIC_ANALOG_RX_EAR_STATUS, 0x00}, + {MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x00}, + {MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL, 0x00}, + {MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x83}, + {MSM89XX_PMIC_ANALOG_SPKR_DRV_CLIP_DET, 0x91}, + {MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, 0x29}, + {MSM89XX_PMIC_ANALOG_SPKR_ANA_BIAS_SET, 0x4D}, + {MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL, 0xE1}, + {MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, 0x1E}, + {MSM89XX_PMIC_ANALOG_SPKR_DRV_MISC, 0xCB}, + {MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG, 0x00}, + {MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0x02}, + {MSM89XX_PMIC_ANALOG_OUTPUT_VOLTAGE, 0x14}, + {MSM89XX_PMIC_ANALOG_BYPASS_MODE, 0x00}, + {MSM89XX_PMIC_ANALOG_BOOST_EN_CTL, 0x1F}, + {MSM89XX_PMIC_ANALOG_SLOPE_COMP_IP_ZERO, 0x8C}, + {MSM89XX_PMIC_ANALOG_RDSON_MAX_DUTY_CYCLE, 0xC0}, + {MSM89XX_PMIC_ANALOG_BOOST_TEST1_1, 0x00}, + {MSM89XX_PMIC_ANALOG_BOOST_TEST_2, 0x00}, + {MSM89XX_PMIC_ANALOG_SPKR_SAR_STATUS, 0x00}, + {MSM89XX_PMIC_ANALOG_SPKR_DRV_STATUS, 0x00}, + {MSM89XX_PMIC_ANALOG_PBUS_ADD_CSR, 0x00}, + {MSM89XX_PMIC_ANALOG_PBUS_ADD_SEL, 0x00}, + {MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0x00}, + {MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL1, 0x00}, + {MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL2, 0x01}, + {MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3, 0x05}, + {MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL4, 0x00}, + {MSM89XX_PMIC_ANALOG_INT_TEST1, 0x00}, + {MSM89XX_PMIC_ANALOG_INT_TEST_VAL, 0x00}, + {MSM89XX_PMIC_ANALOG_TRIM_NUM, 0x04}, + {MSM89XX_PMIC_ANALOG_TRIM_CTRL1, 0x00}, + {MSM89XX_PMIC_ANALOG_TRIM_CTRL2, 0x00}, + {MSM89XX_PMIC_ANALOG_TRIM_CTRL3, 0x00}, + {MSM89XX_PMIC_ANALOG_TRIM_CTRL4, 0x00}, +}; + +static const u8 msm89xx_cdc_core_reg_readable[MSM89XX_CDC_CORE_CACHE_SIZE] = { + [MSM89XX_CDC_CORE_CLK_RX_RESET_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_RX_I2S_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_TX_I2S_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_OTHR_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_RX_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_MCLK_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_PDM_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_SD_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_RX_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_TX2_I2S_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B3_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B3_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B3_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B4_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B4_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B4_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B5_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B5_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B5_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B6_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B6_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B6_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL] = 1, + [MSM89XX_CDC_CORE_TOP_GAIN_UPDATE] = 1, + [MSM89XX_CDC_CORE_TOP_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B1_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B2_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B3_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B4_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B5_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B6_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_SHUT_DOWN_STATUS] = 1, + [MSM89XX_CDC_CORE_COMP0_FS_CFG] = 1, + [MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL] = 1, + [MSM89XX_CDC_CORE_DEBUG_DESER1_CTL] = 1, + [MSM89XX_CDC_CORE_DEBUG_DESER2_CTL] = 1, + [MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX1_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX1_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX1_B3_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX2_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX2_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX2_B3_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX3_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX3_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_TX_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_TX_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_TX_B3_CTL] = 1, + [MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER] = 1, + [MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER] = 1, + [MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER] = 1, + [MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER] = 1, + [MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN] = 1, + [MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN] = 1, + [MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN] = 1, + [MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN] = 1, + [MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_TX1_MUX_CTL] = 1, + [MSM89XX_CDC_CORE_TX2_MUX_CTL] = 1, + [MSM89XX_CDC_CORE_TX3_MUX_CTL] = 1, + [MSM89XX_CDC_CORE_TX4_MUX_CTL] = 1, + [MSM89XX_CDC_CORE_TX1_CLK_FS_CTL] = 1, + [MSM89XX_CDC_CORE_TX2_CLK_FS_CTL] = 1, + [MSM89XX_CDC_CORE_TX3_CLK_FS_CTL] = 1, + [MSM89XX_CDC_CORE_TX4_CLK_FS_CTL] = 1, + [MSM89XX_CDC_CORE_TX5_VOL_CTL_TIMER] = 1, + [MSM89XX_CDC_CORE_TX5_VOL_CTL_GAIN] = 1, + [MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_TX5_MUX_CTL] = 1, + [MSM89XX_CDC_CORE_TX5_CLK_FS_CTL] = 1, + [MSM89XX_CDC_CORE_TX5_DMIC_CTL] = 1, + [MSM89XX_CDC_CORE_TX1_DMIC_CTL] = 1, + [MSM89XX_CDC_CORE_TX2_DMIC_CTL] = 1, + [MSM89XX_CDC_CORE_TX3_DMIC_CTL] = 1, + [MSM89XX_CDC_CORE_TX4_DMIC_CTL] = 1, +}; + +bool msm89xx_cdc_core_readable_reg(struct device *dev, unsigned int reg) +{ + return msm89xx_cdc_core_reg_readable[reg]; +} + +bool msm89xx_cdc_core_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case MSM89XX_CDC_CORE_RX1_B1_CTL: + case MSM89XX_CDC_CORE_RX2_B1_CTL: + case MSM89XX_CDC_CORE_RX3_B1_CTL: + case MSM89XX_CDC_CORE_RX1_B6_CTL: + case MSM89XX_CDC_CORE_RX2_B6_CTL: + case MSM89XX_CDC_CORE_RX3_B6_CTL: + case MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG: + case MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG: + case MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL: + case MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL: + case MSM89XX_CDC_CORE_CLK_MCLK_CTL: + case MSM89XX_CDC_CORE_CLK_PDM_CTL: + return true; + default: + return false; + } +} diff --git a/sound/soc/msm/Kconfig b/sound/soc/msm/Kconfig index 69d74a8703b6..835022b76b78 100644 --- a/sound/soc/msm/Kconfig +++ b/sound/soc/msm/Kconfig @@ -108,7 +108,7 @@ config SND_SOC_CPE listen on codec. config SND_SOC_INT_CODEC - tristate "SoC Machine driver for MSMFALCON_INT" + tristate "SoC Machine driver for SDM660_INT" depends on ARCH_QCOM select SND_SOC_QDSP6V2 select SND_SOC_MSM_STUB @@ -121,7 +121,7 @@ config SND_SOC_INT_CODEC select MSM_QDSP6V2_CODECS select MSM_CDC_PINCTRL select SND_SOC_MSM_SDW - select SND_SOC_MSMFALCON_CDC + select SND_SOC_SDM660_CDC select QTI_PP select DTS_SRS_TM select DOLBY_DAP @@ -129,7 +129,7 @@ config SND_SOC_INT_CODEC select SND_HWDEP select MSM_ULTRASOUND select DTS_EAGLE - select SND_SOC_MSMFALCON_COMMON + select SND_SOC_SDM660_COMMON select SND_SOC_COMPRESS select PINCTRL_LPI help @@ -140,7 +140,7 @@ config SND_SOC_INT_CODEC DAI-links config SND_SOC_EXT_CODEC - tristate "SoC Machine driver for MSMFALCON_EXT" + tristate "SoC Machine driver for SDM660_EXT" depends on ARCH_QCOM select SND_SOC_QDSP6V2 select SND_SOC_MSM_STUB @@ -164,7 +164,7 @@ config SND_SOC_EXT_CODEC select SND_HWDEP select MSM_ULTRASOUND select DTS_EAGLE - select SND_SOC_MSMFALCON_COMMON + select SND_SOC_SDM660_COMMON select SND_SOC_COMPRESS select PINCTRL_LPI help @@ -233,13 +233,13 @@ config SND_SOC_MSM8998 the machine driver and the corresponding DAI-links -config SND_SOC_FALCON - tristate "SoC Machine driver for MSMFALCON boards" - depends on ARCH_MSMFALCON +config SND_SOC_660 + tristate "SoC Machine driver for SDM660 boards" + depends on ARCH_SDM660 select SND_SOC_INT_CODEC select SND_SOC_EXT_CODEC help - To add support for SoC audio on MSMFALCON. + To add support for SoC audio on SDM660. This will enable sound soc drivers which interfaces with DSP, also it will enable the machine driver and the corresponding diff --git a/sound/soc/msm/Makefile b/sound/soc/msm/Makefile index d66f9eb79cea..cd63b491285c 100644 --- a/sound/soc/msm/Makefile +++ b/sound/soc/msm/Makefile @@ -20,16 +20,16 @@ obj-$(CONFIG_SND_SOC_MSM8996) += snd-soc-msm8996.o snd-soc-msm8998-objs := msm8998.o obj-$(CONFIG_SND_SOC_MSM8998) += snd-soc-msm8998.o -# for MSMFALCON sound card driver -snd-soc-msmfalcon-common-objs := msmfalcon-common.o -obj-$(CONFIG_SND_SOC_MSMFALCON_COMMON) += snd-soc-msmfalcon-common.o +# for SDM660 sound card driver +snd-soc-sdm660-common-objs := sdm660-common.o +obj-$(CONFIG_SND_SOC_SDM660_COMMON) += snd-soc-sdm660-common.o -# for MSMFALCON sound card driver -snd-soc-int-codec-objs := msmfalcon-internal.o -obj-$(CONFIG_SND_SOC_INT_CODEC) += snd-soc-msmfalcon-common.o +# for SDM660 sound card driver +snd-soc-int-codec-objs := sdm660-internal.o +obj-$(CONFIG_SND_SOC_INT_CODEC) += snd-soc-sdm660-common.o obj-$(CONFIG_SND_SOC_INT_CODEC) += snd-soc-int-codec.o -# for MSMFALCON sound card driver -snd-soc-ext-codec-objs := msmfalcon-external.o msmfalcon-ext-dai-links.o -obj-$(CONFIG_SND_SOC_EXT_CODEC) += snd-soc-msmfalcon-common.o +# for SDM660 sound card driver +snd-soc-ext-codec-objs := sdm660-external.o sdm660-ext-dai-links.o +obj-$(CONFIG_SND_SOC_EXT_CODEC) += snd-soc-sdm660-common.o obj-$(CONFIG_SND_SOC_EXT_CODEC) += snd-soc-ext-codec.o diff --git a/sound/soc/msm/msmfalcon-common.c b/sound/soc/msm/msmfalcon-common.c deleted file mode 100644 index 013127c48984..000000000000 --- a/sound/soc/msm/msmfalcon-common.c +++ /dev/null @@ -1,2839 +0,0 @@ -/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include "qdsp6v2/msm-pcm-routing-v2.h" -#include "msmfalcon-common.h" -#include "msmfalcon-internal.h" -#include "msmfalcon-external.h" -#include "../codecs/msmfalcon_cdc/msm-analog-cdc.h" -#include "../codecs/wsa881x.h" - -#define DRV_NAME "msmfalcon-asoc-snd" - -#define MSM_INT_DIGITAL_CODEC "msm-dig-codec" -#define PMIC_INT_ANALOG_CODEC "analog-codec" - -#define DEV_NAME_STR_LEN 32 -#define DEFAULT_MCLK_RATE 9600000 - -struct dev_config { - u32 sample_rate; - u32 bit_format; - u32 channels; -}; - -/* TDM default config */ -static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = { - { /* PRI TDM */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */ - }, - { /* SEC TDM */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */ - }, - { /* TERT TDM */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */ - }, - { /* QUAT TDM */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */ - } -}; - -/* TDM default config */ -static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = { - { /* PRI TDM */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */ - }, - { /* SEC TDM */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */ - }, - { /* TERT TDM */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */ - }, - { /* QUAT TDM */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */ - {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */ - } -}; - -static struct dev_config usb_rx_cfg = { - .sample_rate = SAMPLING_RATE_48KHZ, - .bit_format = SNDRV_PCM_FORMAT_S16_LE, - .channels = 2, -}; - -static struct dev_config usb_tx_cfg = { - .sample_rate = SAMPLING_RATE_48KHZ, - .bit_format = SNDRV_PCM_FORMAT_S16_LE, - .channels = 1, -}; - -enum { - PRIM_MI2S = 0, - SEC_MI2S, - TERT_MI2S, - QUAT_MI2S, - MI2S_MAX, -}; - -enum { - PRIM_AUX_PCM = 0, - SEC_AUX_PCM, - TERT_AUX_PCM, - QUAT_AUX_PCM, - AUX_PCM_MAX, -}; - -enum { - PCM_I2S_SEL_PRIM = 0, - PCM_I2S_SEL_SEC, - PCM_I2S_SEL_TERT, - PCM_I2S_SEL_QUAT, - PCM_I2S_SEL_MAX, -}; - -struct mi2s_aux_pcm_common_conf { - struct mutex lock; - void *pcm_i2s_sel_vt_addr; -}; - -struct mi2s_conf { - struct mutex lock; - u32 ref_cnt; - u32 msm_is_mi2s_master; -}; - -struct auxpcm_conf { - struct mutex lock; - u32 ref_cnt; -}; - -struct msm_wsa881x_dev_info { - struct device_node *of_node; - u32 index; -}; -static struct snd_soc_aux_dev *msm_aux_dev; -static struct snd_soc_codec_conf *msm_codec_conf; - -static bool msm_swap_gnd_mic(struct snd_soc_codec *codec); - -static struct wcd_mbhc_config mbhc_cfg = { - .read_fw_bin = false, - .calibration = NULL, - .detect_extn_cable = true, - .mono_stero_detection = false, - .swap_gnd_mic = NULL, - .hs_ext_micbias = true, - .key_code[0] = KEY_MEDIA, - .key_code[1] = KEY_VOICECOMMAND, - .key_code[2] = KEY_VOLUMEUP, - .key_code[3] = KEY_VOLUMEDOWN, - .key_code[4] = 0, - .key_code[5] = 0, - .key_code[6] = 0, - .key_code[7] = 0, - .linein_th = 5000, - .moisture_en = false, - .mbhc_micbias = 0, - .anc_micbias = 0, - .enable_anc_mic_detect = false, -}; - -static struct dev_config proxy_rx_cfg = { - .sample_rate = SAMPLING_RATE_48KHZ, - .bit_format = SNDRV_PCM_FORMAT_S16_LE, - .channels = 2, -}; - -/* Default configuration of MI2S channels */ -static struct dev_config mi2s_rx_cfg[] = { - [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, - [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, - [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, - [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, -}; - -static struct dev_config mi2s_tx_cfg[] = { - [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, -}; - -static struct dev_config aux_pcm_rx_cfg[] = { - [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, -}; - -static struct dev_config aux_pcm_tx_cfg[] = { - [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, -}; - -static char const *ch_text[] = {"Two", "Three", "Four", "Five", - "Six", "Seven", "Eight"}; -static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"}; -static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_16", - "KHZ_32", "KHZ_44P1", "KHZ_48", - "KHZ_96", "KHZ_192"}; -static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four", - "Five", "Six", "Seven", - "Eight"}; -static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE", - "S32_LE"}; -static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four", - "Five", "Six", "Seven", "Eight"}; -static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"}; -static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32", - "KHZ_44P1", "KHZ_48", "KHZ_96", - "KHZ_192", "KHZ_352P8", "KHZ_384"}; -static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four", - "Five", "Six", "Seven", - "Eight"}; -static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025", - "KHZ_16", "KHZ_22P05", - "KHZ_32", "KHZ_44P1", "KHZ_48", - "KHZ_96", "KHZ_192", "KHZ_384"}; - -static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text); -static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text); -static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text); -static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text); -static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text); -static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text); -static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text); -static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text); -static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text); -static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text); -static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text); -static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text); -static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text); -static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text); -static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text); -static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text); -static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text); -static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text); - -static struct afe_clk_set mi2s_clk[MI2S_MAX] = { - { - AFE_API_VERSION_I2S_CONFIG, - Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT, - Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, - Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, - Q6AFE_LPASS_CLK_ROOT_DEFAULT, - 0, - }, - { - AFE_API_VERSION_I2S_CONFIG, - Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT, - Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, - Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, - Q6AFE_LPASS_CLK_ROOT_DEFAULT, - 0, - }, - { - AFE_API_VERSION_I2S_CONFIG, - Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT, - Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, - Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, - Q6AFE_LPASS_CLK_ROOT_DEFAULT, - 0, - }, - { - AFE_API_VERSION_I2S_CONFIG, - Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT, - Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, - Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, - Q6AFE_LPASS_CLK_ROOT_DEFAULT, - 0, - } -}; - -static struct mi2s_aux_pcm_common_conf mi2s_auxpcm_conf[PCM_I2S_SEL_MAX]; -static struct mi2s_conf mi2s_intf_conf[MI2S_MAX]; -static struct auxpcm_conf auxpcm_intf_conf[AUX_PCM_MAX]; - -static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - pr_debug("%s: proxy_rx channels = %d\n", - __func__, proxy_rx_cfg.channels); - ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2; - - return 0; -} - -static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2; - pr_debug("%s: proxy_rx channels = %d\n", - __func__, proxy_rx_cfg.channels); - - return 1; -} - -static int tdm_get_sample_rate(int value) -{ - int sample_rate = 0; - - switch (value) { - case 0: - sample_rate = SAMPLING_RATE_8KHZ; - break; - case 1: - sample_rate = SAMPLING_RATE_16KHZ; - break; - case 2: - sample_rate = SAMPLING_RATE_32KHZ; - break; - case 3: - sample_rate = SAMPLING_RATE_44P1KHZ; - break; - case 4: - sample_rate = SAMPLING_RATE_48KHZ; - break; - case 5: - sample_rate = SAMPLING_RATE_96KHZ; - break; - case 6: - sample_rate = SAMPLING_RATE_192KHZ; - break; - case 7: - sample_rate = SAMPLING_RATE_352P8KHZ; - break; - case 8: - sample_rate = SAMPLING_RATE_384KHZ; - break; - default: - sample_rate = SAMPLING_RATE_48KHZ; - break; - } - return sample_rate; -} - -static int tdm_get_sample_rate_val(int sample_rate) -{ - int sample_rate_val = 0; - - switch (sample_rate) { - case SAMPLING_RATE_8KHZ: - sample_rate_val = 0; - break; - case SAMPLING_RATE_16KHZ: - sample_rate_val = 1; - break; - case SAMPLING_RATE_32KHZ: - sample_rate_val = 2; - break; - case SAMPLING_RATE_44P1KHZ: - sample_rate_val = 3; - break; - case SAMPLING_RATE_48KHZ: - sample_rate_val = 4; - break; - case SAMPLING_RATE_96KHZ: - sample_rate_val = 5; - break; - case SAMPLING_RATE_192KHZ: - sample_rate_val = 6; - break; - case SAMPLING_RATE_352P8KHZ: - sample_rate_val = 7; - break; - case SAMPLING_RATE_384KHZ: - sample_rate_val = 8; - break; - default: - sample_rate_val = 4; - break; - } - return sample_rate_val; -} - -static int tdm_get_port_idx(struct snd_kcontrol *kcontrol, - struct tdm_port *port) -{ - if (port) { - if (strnstr(kcontrol->id.name, "PRI", - sizeof(kcontrol->id.name))) { - port->mode = TDM_PRI; - } else if (strnstr(kcontrol->id.name, "SEC", - sizeof(kcontrol->id.name))) { - port->mode = TDM_SEC; - } else if (strnstr(kcontrol->id.name, "TERT", - sizeof(kcontrol->id.name))) { - port->mode = TDM_TERT; - } else if (strnstr(kcontrol->id.name, "QUAT", - sizeof(kcontrol->id.name))) { - port->mode = TDM_QUAT; - } else { - pr_err("%s: unsupported mode in: %s", - __func__, kcontrol->id.name); - return -EINVAL; - } - - if (strnstr(kcontrol->id.name, "RX_0", - sizeof(kcontrol->id.name)) || - strnstr(kcontrol->id.name, "TX_0", - sizeof(kcontrol->id.name))) { - port->channel = TDM_0; - } else if (strnstr(kcontrol->id.name, "RX_1", - sizeof(kcontrol->id.name)) || - strnstr(kcontrol->id.name, "TX_1", - sizeof(kcontrol->id.name))) { - port->channel = TDM_1; - } else if (strnstr(kcontrol->id.name, "RX_2", - sizeof(kcontrol->id.name)) || - strnstr(kcontrol->id.name, "TX_2", - sizeof(kcontrol->id.name))) { - port->channel = TDM_2; - } else if (strnstr(kcontrol->id.name, "RX_3", - sizeof(kcontrol->id.name)) || - strnstr(kcontrol->id.name, "TX_3", - sizeof(kcontrol->id.name))) { - port->channel = TDM_3; - } else if (strnstr(kcontrol->id.name, "RX_4", - sizeof(kcontrol->id.name)) || - strnstr(kcontrol->id.name, "TX_4", - sizeof(kcontrol->id.name))) { - port->channel = TDM_4; - } else if (strnstr(kcontrol->id.name, "RX_5", - sizeof(kcontrol->id.name)) || - strnstr(kcontrol->id.name, "TX_5", - sizeof(kcontrol->id.name))) { - port->channel = TDM_5; - } else if (strnstr(kcontrol->id.name, "RX_6", - sizeof(kcontrol->id.name)) || - strnstr(kcontrol->id.name, "TX_6", - sizeof(kcontrol->id.name))) { - port->channel = TDM_6; - } else if (strnstr(kcontrol->id.name, "RX_7", - sizeof(kcontrol->id.name)) || - strnstr(kcontrol->id.name, "TX_7", - sizeof(kcontrol->id.name))) { - port->channel = TDM_7; - } else { - pr_err("%s: unsupported channel in: %s", - __func__, kcontrol->id.name); - return -EINVAL; - } - } else - return -EINVAL; - return 0; -} - -static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct tdm_port port; - int ret = tdm_get_port_idx(kcontrol, &port); - - if (ret) { - pr_err("%s: unsupported control: %s", - __func__, kcontrol->id.name); - } else { - ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val( - tdm_rx_cfg[port.mode][port.channel].sample_rate); - - pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__, - tdm_rx_cfg[port.mode][port.channel].sample_rate, - ucontrol->value.enumerated.item[0]); - } - return ret; -} - -static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct tdm_port port; - int ret = tdm_get_port_idx(kcontrol, &port); - - if (ret) { - pr_err("%s: unsupported control: %s", - __func__, kcontrol->id.name); - } else { - tdm_rx_cfg[port.mode][port.channel].sample_rate = - tdm_get_sample_rate(ucontrol->value.enumerated.item[0]); - - pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__, - tdm_rx_cfg[port.mode][port.channel].sample_rate, - ucontrol->value.enumerated.item[0]); - } - return ret; -} - -static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct tdm_port port; - int ret = tdm_get_port_idx(kcontrol, &port); - - if (ret) { - pr_err("%s: unsupported control: %s", - __func__, kcontrol->id.name); - } else { - ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val( - tdm_tx_cfg[port.mode][port.channel].sample_rate); - - pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__, - tdm_tx_cfg[port.mode][port.channel].sample_rate, - ucontrol->value.enumerated.item[0]); - } - return ret; -} - -static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct tdm_port port; - int ret = tdm_get_port_idx(kcontrol, &port); - - if (ret) { - pr_err("%s: unsupported control: %s", - __func__, kcontrol->id.name); - } else { - tdm_tx_cfg[port.mode][port.channel].sample_rate = - tdm_get_sample_rate(ucontrol->value.enumerated.item[0]); - - pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__, - tdm_tx_cfg[port.mode][port.channel].sample_rate, - ucontrol->value.enumerated.item[0]); - } - return ret; -} - -static int tdm_get_format(int value) -{ - int format = 0; - - switch (value) { - case 0: - format = SNDRV_PCM_FORMAT_S16_LE; - break; - case 1: - format = SNDRV_PCM_FORMAT_S24_LE; - break; - case 2: - format = SNDRV_PCM_FORMAT_S32_LE; - break; - default: - format = SNDRV_PCM_FORMAT_S16_LE; - break; - } - return format; -} - -static int tdm_get_format_val(int format) -{ - int value = 0; - - switch (format) { - case SNDRV_PCM_FORMAT_S16_LE: - value = 0; - break; - case SNDRV_PCM_FORMAT_S24_LE: - value = 1; - break; - case SNDRV_PCM_FORMAT_S32_LE: - value = 2; - break; - default: - value = 0; - break; - } - return value; -} - -static int tdm_rx_format_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct tdm_port port; - int ret = tdm_get_port_idx(kcontrol, &port); - - if (ret) { - pr_err("%s: unsupported control: %s", - __func__, kcontrol->id.name); - } else { - ucontrol->value.enumerated.item[0] = tdm_get_format_val( - tdm_rx_cfg[port.mode][port.channel].bit_format); - - pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__, - tdm_rx_cfg[port.mode][port.channel].bit_format, - ucontrol->value.enumerated.item[0]); - } - return ret; -} - -static int tdm_rx_format_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct tdm_port port; - int ret = tdm_get_port_idx(kcontrol, &port); - - if (ret) { - pr_err("%s: unsupported control: %s", - __func__, kcontrol->id.name); - } else { - tdm_rx_cfg[port.mode][port.channel].bit_format = - tdm_get_format(ucontrol->value.enumerated.item[0]); - - pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__, - tdm_rx_cfg[port.mode][port.channel].bit_format, - ucontrol->value.enumerated.item[0]); - } - return ret; -} - -static int tdm_tx_format_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct tdm_port port; - int ret = tdm_get_port_idx(kcontrol, &port); - - if (ret) { - pr_err("%s: unsupported control: %s", - __func__, kcontrol->id.name); - } else { - ucontrol->value.enumerated.item[0] = tdm_get_format_val( - tdm_tx_cfg[port.mode][port.channel].bit_format); - - pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__, - tdm_tx_cfg[port.mode][port.channel].bit_format, - ucontrol->value.enumerated.item[0]); - } - return ret; -} - -static int tdm_tx_format_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct tdm_port port; - int ret = tdm_get_port_idx(kcontrol, &port); - - if (ret) { - pr_err("%s: unsupported control: %s", - __func__, kcontrol->id.name); - } else { - tdm_tx_cfg[port.mode][port.channel].bit_format = - tdm_get_format(ucontrol->value.enumerated.item[0]); - - pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__, - tdm_tx_cfg[port.mode][port.channel].bit_format, - ucontrol->value.enumerated.item[0]); - } - return ret; -} - -static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct tdm_port port; - int ret = tdm_get_port_idx(kcontrol, &port); - - if (ret) { - pr_err("%s: unsupported control: %s", - __func__, kcontrol->id.name); - } else { - - ucontrol->value.enumerated.item[0] = - tdm_rx_cfg[port.mode][port.channel].channels - 1; - - pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__, - tdm_rx_cfg[port.mode][port.channel].channels - 1, - ucontrol->value.enumerated.item[0]); - } - return ret; -} - -static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct tdm_port port; - int ret = tdm_get_port_idx(kcontrol, &port); - - if (ret) { - pr_err("%s: unsupported control: %s", - __func__, kcontrol->id.name); - } else { - tdm_rx_cfg[port.mode][port.channel].channels = - ucontrol->value.enumerated.item[0] + 1; - - pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__, - tdm_rx_cfg[port.mode][port.channel].channels, - ucontrol->value.enumerated.item[0] + 1); - } - return ret; -} - -static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct tdm_port port; - int ret = tdm_get_port_idx(kcontrol, &port); - - if (ret) { - pr_err("%s: unsupported control: %s", - __func__, kcontrol->id.name); - } else { - ucontrol->value.enumerated.item[0] = - tdm_tx_cfg[port.mode][port.channel].channels - 1; - - pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__, - tdm_tx_cfg[port.mode][port.channel].channels - 1, - ucontrol->value.enumerated.item[0]); - } - return ret; -} - -static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct tdm_port port; - int ret = tdm_get_port_idx(kcontrol, &port); - - if (ret) { - pr_err("%s: unsupported control: %s", - __func__, kcontrol->id.name); - } else { - tdm_tx_cfg[port.mode][port.channel].channels = - ucontrol->value.enumerated.item[0] + 1; - - pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__, - tdm_tx_cfg[port.mode][port.channel].channels, - ucontrol->value.enumerated.item[0] + 1); - } - return ret; -} - -static int aux_pcm_get_sample_rate(int value) -{ - int sample_rate; - - switch (value) { - case 1: - sample_rate = SAMPLING_RATE_16KHZ; - break; - case 0: - default: - sample_rate = SAMPLING_RATE_8KHZ; - break; - } - return sample_rate; -} - -static int aux_pcm_get_sample_rate_val(int sample_rate) -{ - int sample_rate_val; - - switch (sample_rate) { - case SAMPLING_RATE_16KHZ: - sample_rate_val = 1; - break; - case SAMPLING_RATE_8KHZ: - default: - sample_rate_val = 0; - break; - } - return sample_rate_val; -} - -static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol) -{ - int idx; - - if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM", - sizeof("PRIM_AUX_PCM"))) - idx = PRIM_AUX_PCM; - else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM", - sizeof("SEC_AUX_PCM"))) - idx = SEC_AUX_PCM; - else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM", - sizeof("TERT_AUX_PCM"))) - idx = TERT_AUX_PCM; - else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM", - sizeof("QUAT_AUX_PCM"))) - idx = QUAT_AUX_PCM; - else { - pr_err("%s: unsupported port: %s", - __func__, kcontrol->id.name); - idx = -EINVAL; - } - - return idx; -} - -static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int idx = aux_pcm_get_port_idx(kcontrol); - - if (idx < 0) - return idx; - - aux_pcm_rx_cfg[idx].sample_rate = - aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]); - - pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__, - idx, aux_pcm_rx_cfg[idx].sample_rate, - ucontrol->value.enumerated.item[0]); - - return 0; -} - -static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int idx = aux_pcm_get_port_idx(kcontrol); - - if (idx < 0) - return idx; - - ucontrol->value.enumerated.item[0] = - aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate); - - pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__, - idx, aux_pcm_rx_cfg[idx].sample_rate, - ucontrol->value.enumerated.item[0]); - - return 0; -} - -static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int idx = aux_pcm_get_port_idx(kcontrol); - - if (idx < 0) - return idx; - - aux_pcm_tx_cfg[idx].sample_rate = - aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]); - - pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__, - idx, aux_pcm_tx_cfg[idx].sample_rate, - ucontrol->value.enumerated.item[0]); - - return 0; -} - -static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int idx = aux_pcm_get_port_idx(kcontrol); - - if (idx < 0) - return idx; - - ucontrol->value.enumerated.item[0] = - aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate); - - pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__, - idx, aux_pcm_tx_cfg[idx].sample_rate, - ucontrol->value.enumerated.item[0]); - - return 0; -} - -static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol) -{ - int idx; - - if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX", - sizeof("PRIM_MI2S_RX"))) - idx = PRIM_MI2S; - else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX", - sizeof("SEC_MI2S_RX"))) - idx = SEC_MI2S; - else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX", - sizeof("TERT_MI2S_RX"))) - idx = TERT_MI2S; - else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX", - sizeof("QUAT_MI2S_RX"))) - idx = QUAT_MI2S; - else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX", - sizeof("PRIM_MI2S_TX"))) - idx = PRIM_MI2S; - else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX", - sizeof("SEC_MI2S_TX"))) - idx = SEC_MI2S; - else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX", - sizeof("TERT_MI2S_TX"))) - idx = TERT_MI2S; - else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX", - sizeof("QUAT_MI2S_TX"))) - idx = QUAT_MI2S; - else { - pr_err("%s: unsupported channel: %s", - __func__, kcontrol->id.name); - idx = -EINVAL; - } - - return idx; -} - -static int mi2s_get_sample_rate_val(int sample_rate) -{ - int sample_rate_val; - - switch (sample_rate) { - case SAMPLING_RATE_8KHZ: - sample_rate_val = 0; - break; - case SAMPLING_RATE_16KHZ: - sample_rate_val = 1; - break; - case SAMPLING_RATE_32KHZ: - sample_rate_val = 2; - break; - case SAMPLING_RATE_44P1KHZ: - sample_rate_val = 3; - break; - case SAMPLING_RATE_48KHZ: - sample_rate_val = 4; - break; - case SAMPLING_RATE_96KHZ: - sample_rate_val = 5; - break; - case SAMPLING_RATE_192KHZ: - sample_rate_val = 6; - break; - default: - sample_rate_val = 4; - break; - } - return sample_rate_val; -} - -static int mi2s_get_sample_rate(int value) -{ - int sample_rate; - - switch (value) { - case 0: - sample_rate = SAMPLING_RATE_8KHZ; - break; - case 1: - sample_rate = SAMPLING_RATE_16KHZ; - break; - case 2: - sample_rate = SAMPLING_RATE_32KHZ; - break; - case 3: - sample_rate = SAMPLING_RATE_44P1KHZ; - break; - case 4: - sample_rate = SAMPLING_RATE_48KHZ; - break; - case 5: - sample_rate = SAMPLING_RATE_96KHZ; - break; - case 6: - sample_rate = SAMPLING_RATE_192KHZ; - break; - default: - sample_rate = SAMPLING_RATE_48KHZ; - break; - } - return sample_rate; -} - -static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int idx = mi2s_get_port_idx(kcontrol); - - if (idx < 0) - return idx; - - mi2s_rx_cfg[idx].sample_rate = - mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]); - - pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__, - idx, mi2s_rx_cfg[idx].sample_rate, - ucontrol->value.enumerated.item[0]); - - return 0; -} - -static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int idx = mi2s_get_port_idx(kcontrol); - - if (idx < 0) - return idx; - - ucontrol->value.enumerated.item[0] = - mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate); - - pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__, - idx, mi2s_rx_cfg[idx].sample_rate, - ucontrol->value.enumerated.item[0]); - - return 0; -} - -static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int idx = mi2s_get_port_idx(kcontrol); - - if (idx < 0) - return idx; - - mi2s_tx_cfg[idx].sample_rate = - mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]); - - pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__, - idx, mi2s_tx_cfg[idx].sample_rate, - ucontrol->value.enumerated.item[0]); - - return 0; -} - -static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int idx = mi2s_get_port_idx(kcontrol); - - if (idx < 0) - return idx; - - ucontrol->value.enumerated.item[0] = - mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate); - - pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__, - idx, mi2s_tx_cfg[idx].sample_rate, - ucontrol->value.enumerated.item[0]); - - return 0; -} - -static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int idx = mi2s_get_port_idx(kcontrol); - - if (idx < 0) - return idx; - - pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__, - idx, mi2s_rx_cfg[idx].channels); - ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1; - - return 0; -} - -static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int idx = mi2s_get_port_idx(kcontrol); - - if (idx < 0) - return idx; - - mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1; - pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__, - idx, mi2s_rx_cfg[idx].channels); - - return 1; -} - -static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int idx = mi2s_get_port_idx(kcontrol); - - if (idx < 0) - return idx; - - pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__, - idx, mi2s_tx_cfg[idx].channels); - ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1; - - return 0; -} - -static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int idx = mi2s_get_port_idx(kcontrol); - - if (idx < 0) - return idx; - - mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1; - pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__, - idx, mi2s_tx_cfg[idx].channels); - - return 1; -} - -static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, - usb_rx_cfg.channels); - ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1; - return 0; -} - -static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1; - - pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels); - return 1; -} - -static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int sample_rate_val; - - switch (usb_rx_cfg.sample_rate) { - case SAMPLING_RATE_384KHZ: - sample_rate_val = 9; - break; - case SAMPLING_RATE_192KHZ: - sample_rate_val = 8; - break; - case SAMPLING_RATE_96KHZ: - sample_rate_val = 7; - break; - case SAMPLING_RATE_48KHZ: - sample_rate_val = 6; - break; - case SAMPLING_RATE_44P1KHZ: - sample_rate_val = 5; - break; - case SAMPLING_RATE_32KHZ: - sample_rate_val = 4; - break; - case SAMPLING_RATE_22P05KHZ: - sample_rate_val = 3; - break; - case SAMPLING_RATE_16KHZ: - sample_rate_val = 2; - break; - case SAMPLING_RATE_11P025KHZ: - sample_rate_val = 1; - break; - case SAMPLING_RATE_8KHZ: - default: - sample_rate_val = 0; - break; - } - - ucontrol->value.integer.value[0] = sample_rate_val; - pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__, - usb_rx_cfg.sample_rate); - return 0; -} - -static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - switch (ucontrol->value.integer.value[0]) { - case 9: - usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ; - break; - case 8: - usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ; - break; - case 7: - usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ; - break; - case 6: - usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ; - break; - case 5: - usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ; - break; - case 4: - usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ; - break; - case 3: - usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ; - break; - case 2: - usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ; - break; - case 1: - usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ; - break; - case 0: - usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ; - break; - default: - usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ; - break; - } - - pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n", - __func__, ucontrol->value.integer.value[0], - usb_rx_cfg.sample_rate); - return 0; -} - -static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - switch (usb_rx_cfg.bit_format) { - case SNDRV_PCM_FORMAT_S32_LE: - ucontrol->value.integer.value[0] = 3; - break; - case SNDRV_PCM_FORMAT_S24_3LE: - ucontrol->value.integer.value[0] = 2; - break; - case SNDRV_PCM_FORMAT_S24_LE: - ucontrol->value.integer.value[0] = 1; - break; - case SNDRV_PCM_FORMAT_S16_LE: - default: - ucontrol->value.integer.value[0] = 0; - break; - } - - pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n", - __func__, usb_rx_cfg.bit_format, - ucontrol->value.integer.value[0]); - return 0; -} - -static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int rc = 0; - - switch (ucontrol->value.integer.value[0]) { - case 3: - usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE; - break; - case 2: - usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE; - break; - case 1: - usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE; - break; - case 0: - default: - usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE; - break; - } - pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n", - __func__, usb_rx_cfg.bit_format, - ucontrol->value.integer.value[0]); - - return rc; -} - -static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, - usb_tx_cfg.channels); - ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1; - return 0; -} - -static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1; - - pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels); - return 1; -} - -static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int sample_rate_val; - - switch (usb_tx_cfg.sample_rate) { - case SAMPLING_RATE_384KHZ: - sample_rate_val = 9; - break; - case SAMPLING_RATE_192KHZ: - sample_rate_val = 8; - break; - case SAMPLING_RATE_96KHZ: - sample_rate_val = 7; - break; - case SAMPLING_RATE_48KHZ: - sample_rate_val = 6; - break; - case SAMPLING_RATE_44P1KHZ: - sample_rate_val = 5; - break; - case SAMPLING_RATE_32KHZ: - sample_rate_val = 4; - break; - case SAMPLING_RATE_22P05KHZ: - sample_rate_val = 3; - break; - case SAMPLING_RATE_16KHZ: - sample_rate_val = 2; - break; - case SAMPLING_RATE_11P025KHZ: - sample_rate_val = 1; - break; - case SAMPLING_RATE_8KHZ: - sample_rate_val = 0; - break; - default: - sample_rate_val = 6; - break; - } - - ucontrol->value.integer.value[0] = sample_rate_val; - pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__, - usb_tx_cfg.sample_rate); - return 0; -} - -static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - switch (ucontrol->value.integer.value[0]) { - case 9: - usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ; - break; - case 8: - usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ; - break; - case 7: - usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ; - break; - case 6: - usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ; - break; - case 5: - usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ; - break; - case 4: - usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ; - break; - case 3: - usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ; - break; - case 2: - usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ; - break; - case 1: - usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ; - break; - case 0: - usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ; - break; - default: - usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ; - break; - } - - pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n", - __func__, ucontrol->value.integer.value[0], - usb_tx_cfg.sample_rate); - return 0; -} - -static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - switch (usb_tx_cfg.bit_format) { - case SNDRV_PCM_FORMAT_S32_LE: - ucontrol->value.integer.value[0] = 3; - break; - case SNDRV_PCM_FORMAT_S24_3LE: - ucontrol->value.integer.value[0] = 2; - break; - case SNDRV_PCM_FORMAT_S24_LE: - ucontrol->value.integer.value[0] = 1; - break; - case SNDRV_PCM_FORMAT_S16_LE: - default: - ucontrol->value.integer.value[0] = 0; - break; - } - - pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n", - __func__, usb_tx_cfg.bit_format, - ucontrol->value.integer.value[0]); - return 0; -} - -static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int rc = 0; - - switch (ucontrol->value.integer.value[0]) { - case 3: - usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE; - break; - case 2: - usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE; - break; - case 1: - usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE; - break; - case 0: - default: - usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE; - break; - } - pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n", - __func__, usb_tx_cfg.bit_format, - ucontrol->value.integer.value[0]); - - return rc; -} - -const struct snd_kcontrol_new msm_common_snd_controls[] = { - SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs, - proxy_rx_ch_get, proxy_rx_ch_put), - SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate, - aux_pcm_rx_sample_rate_get, - aux_pcm_rx_sample_rate_put), - SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate, - aux_pcm_rx_sample_rate_get, - aux_pcm_rx_sample_rate_put), - SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate, - aux_pcm_rx_sample_rate_get, - aux_pcm_rx_sample_rate_put), - SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate, - aux_pcm_rx_sample_rate_get, - aux_pcm_rx_sample_rate_put), - SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate, - aux_pcm_tx_sample_rate_get, - aux_pcm_tx_sample_rate_put), - SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate, - aux_pcm_tx_sample_rate_get, - aux_pcm_tx_sample_rate_put), - SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate, - aux_pcm_tx_sample_rate_get, - aux_pcm_tx_sample_rate_put), - SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate, - aux_pcm_tx_sample_rate_get, - aux_pcm_tx_sample_rate_put), - SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate, - mi2s_rx_sample_rate_get, - mi2s_rx_sample_rate_put), - SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate, - mi2s_rx_sample_rate_get, - mi2s_rx_sample_rate_put), - SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate, - mi2s_rx_sample_rate_get, - mi2s_rx_sample_rate_put), - SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate, - mi2s_rx_sample_rate_get, - mi2s_rx_sample_rate_put), - SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate, - mi2s_tx_sample_rate_get, - mi2s_tx_sample_rate_put), - SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate, - mi2s_tx_sample_rate_get, - mi2s_tx_sample_rate_put), - SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate, - mi2s_tx_sample_rate_get, - mi2s_tx_sample_rate_put), - SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate, - mi2s_tx_sample_rate_get, - mi2s_tx_sample_rate_put), - SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs, - msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put), - SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs, - msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put), - SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs, - msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put), - SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs, - msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put), - SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs, - msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put), - SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs, - msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put), - SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs, - msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put), - SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs, - msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put), - SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs, - usb_audio_rx_ch_get, usb_audio_rx_ch_put), - SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs, - usb_audio_tx_ch_get, usb_audio_tx_ch_put), - SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format, - usb_audio_rx_format_get, usb_audio_rx_format_put), - SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format, - usb_audio_tx_format_get, usb_audio_tx_format_put), - SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate, - usb_audio_rx_sample_rate_get, - usb_audio_rx_sample_rate_put), - SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate, - usb_audio_tx_sample_rate_get, - usb_audio_tx_sample_rate_put), - SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate, - tdm_rx_sample_rate_get, - tdm_rx_sample_rate_put), - SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate, - tdm_tx_sample_rate_get, - tdm_tx_sample_rate_put), - SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format, - tdm_rx_format_get, - tdm_rx_format_put), - SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format, - tdm_tx_format_get, - tdm_tx_format_put), - SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs, - tdm_rx_ch_get, - tdm_rx_ch_put), - SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs, - tdm_tx_ch_get, - tdm_tx_ch_put), - SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate, - tdm_rx_sample_rate_get, - tdm_rx_sample_rate_put), - SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate, - tdm_tx_sample_rate_get, - tdm_tx_sample_rate_put), - SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format, - tdm_rx_format_get, - tdm_rx_format_put), - SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format, - tdm_tx_format_get, - tdm_tx_format_put), - SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs, - tdm_rx_ch_get, - tdm_rx_ch_put), - SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs, - tdm_tx_ch_get, - tdm_tx_ch_put), - SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate, - tdm_rx_sample_rate_get, - tdm_rx_sample_rate_put), - SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate, - tdm_tx_sample_rate_get, - tdm_tx_sample_rate_put), - SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format, - tdm_rx_format_get, - tdm_rx_format_put), - SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format, - tdm_tx_format_get, - tdm_tx_format_put), - SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs, - tdm_rx_ch_get, - tdm_rx_ch_put), - SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs, - tdm_tx_ch_get, - tdm_tx_ch_put), - SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate, - tdm_rx_sample_rate_get, - tdm_rx_sample_rate_put), - SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate, - tdm_tx_sample_rate_get, - tdm_tx_sample_rate_put), - SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format, - tdm_rx_format_get, - tdm_rx_format_put), - SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format, - tdm_tx_format_get, - tdm_tx_format_put), - SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs, - tdm_rx_ch_get, - tdm_rx_ch_put), - SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs, - tdm_tx_ch_get, - tdm_tx_ch_put), -}; - -static inline int param_is_mask(int p) -{ - return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) && - (p <= SNDRV_PCM_HW_PARAM_LAST_MASK); -} - -static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p, - int n) -{ - return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]); -} - -static void param_set_mask(struct snd_pcm_hw_params *p, int n, unsigned bit) -{ - if (bit >= SNDRV_MASK_MAX) - return; - if (param_is_mask(n)) { - struct snd_mask *m = param_to_mask(p, n); - - m->bits[0] = 0; - m->bits[1] = 0; - m->bits[bit >> 5] |= (1 << (bit & 31)); - } -} - -/** - * msm_common_be_hw_params_fixup - updates settings of ALSA BE hw params. - * - * @rtd: runtime dailink instance - * @params: HW params of associated backend dailink. - * - * Returns 0. - */ -int msm_common_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, - struct snd_pcm_hw_params *params) -{ - struct snd_soc_dai_link *dai_link = rtd->dai_link; - struct snd_interval *rate = hw_param_interval(params, - SNDRV_PCM_HW_PARAM_RATE); - struct snd_interval *channels = hw_param_interval(params, - SNDRV_PCM_HW_PARAM_CHANNELS); - int rc = 0; - - pr_debug("%s: format = %d, rate = %d\n", - __func__, params_format(params), params_rate(params)); - - switch (dai_link->be_id) { - case MSM_BACKEND_DAI_USB_RX: - param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, - usb_rx_cfg.bit_format); - rate->min = rate->max = usb_rx_cfg.sample_rate; - channels->min = channels->max = usb_rx_cfg.channels; - break; - - case MSM_BACKEND_DAI_USB_TX: - param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, - usb_tx_cfg.bit_format); - rate->min = rate->max = usb_tx_cfg.sample_rate; - channels->min = channels->max = usb_tx_cfg.channels; - break; - - case MSM_BACKEND_DAI_AFE_PCM_RX: - channels->min = channels->max = proxy_rx_cfg.channels; - rate->min = rate->max = SAMPLING_RATE_48KHZ; - break; - - case MSM_BACKEND_DAI_PRI_TDM_RX_0: - channels->min = channels->max = - tdm_rx_cfg[TDM_PRI][TDM_0].channels; - param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, - tdm_rx_cfg[TDM_PRI][TDM_0].bit_format); - rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate; - break; - - case MSM_BACKEND_DAI_PRI_TDM_TX_0: - channels->min = channels->max = - tdm_tx_cfg[TDM_PRI][TDM_0].channels; - param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, - tdm_tx_cfg[TDM_PRI][TDM_0].bit_format); - rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate; - break; - - case MSM_BACKEND_DAI_SEC_TDM_RX_0: - channels->min = channels->max = - tdm_rx_cfg[TDM_SEC][TDM_0].channels; - param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, - tdm_rx_cfg[TDM_SEC][TDM_0].bit_format); - rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate; - break; - - case MSM_BACKEND_DAI_SEC_TDM_TX_0: - channels->min = channels->max = - tdm_tx_cfg[TDM_SEC][TDM_0].channels; - param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, - tdm_tx_cfg[TDM_SEC][TDM_0].bit_format); - rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate; - break; - - case MSM_BACKEND_DAI_TERT_TDM_RX_0: - channels->min = channels->max = - tdm_rx_cfg[TDM_TERT][TDM_0].channels; - param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, - tdm_rx_cfg[TDM_TERT][TDM_0].bit_format); - rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate; - break; - - case MSM_BACKEND_DAI_TERT_TDM_TX_0: - channels->min = channels->max = - tdm_tx_cfg[TDM_TERT][TDM_0].channels; - param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, - tdm_tx_cfg[TDM_TERT][TDM_0].bit_format); - rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate; - break; - - case MSM_BACKEND_DAI_QUAT_TDM_RX_0: - channels->min = channels->max = - tdm_rx_cfg[TDM_QUAT][TDM_0].channels; - param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, - tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format); - rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate; - break; - - case MSM_BACKEND_DAI_QUAT_TDM_TX_0: - channels->min = channels->max = - tdm_tx_cfg[TDM_QUAT][TDM_0].channels; - param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, - tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format); - rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate; - break; - - case MSM_BACKEND_DAI_AUXPCM_RX: - rate->min = rate->max = - aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate; - channels->min = channels->max = - aux_pcm_rx_cfg[PRIM_AUX_PCM].channels; - break; - - case MSM_BACKEND_DAI_AUXPCM_TX: - rate->min = rate->max = - aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate; - channels->min = channels->max = - aux_pcm_tx_cfg[PRIM_AUX_PCM].channels; - break; - - case MSM_BACKEND_DAI_SEC_AUXPCM_RX: - rate->min = rate->max = - aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate; - channels->min = channels->max = - aux_pcm_rx_cfg[SEC_AUX_PCM].channels; - break; - - case MSM_BACKEND_DAI_SEC_AUXPCM_TX: - rate->min = rate->max = - aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate; - channels->min = channels->max = - aux_pcm_tx_cfg[SEC_AUX_PCM].channels; - break; - - case MSM_BACKEND_DAI_TERT_AUXPCM_RX: - rate->min = rate->max = - aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate; - channels->min = channels->max = - aux_pcm_rx_cfg[TERT_AUX_PCM].channels; - break; - - case MSM_BACKEND_DAI_TERT_AUXPCM_TX: - rate->min = rate->max = - aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate; - channels->min = channels->max = - aux_pcm_tx_cfg[TERT_AUX_PCM].channels; - break; - - case MSM_BACKEND_DAI_QUAT_AUXPCM_RX: - rate->min = rate->max = - aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate; - channels->min = channels->max = - aux_pcm_rx_cfg[QUAT_AUX_PCM].channels; - break; - - case MSM_BACKEND_DAI_QUAT_AUXPCM_TX: - rate->min = rate->max = - aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate; - channels->min = channels->max = - aux_pcm_tx_cfg[QUAT_AUX_PCM].channels; - break; - - case MSM_BACKEND_DAI_PRI_MI2S_RX: - rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate; - channels->min = channels->max = - mi2s_rx_cfg[PRIM_MI2S].channels; - break; - - case MSM_BACKEND_DAI_PRI_MI2S_TX: - rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate; - channels->min = channels->max = - mi2s_tx_cfg[PRIM_MI2S].channels; - break; - - case MSM_BACKEND_DAI_SECONDARY_MI2S_RX: - rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate; - channels->min = channels->max = - mi2s_rx_cfg[SEC_MI2S].channels; - break; - - case MSM_BACKEND_DAI_SECONDARY_MI2S_TX: - rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate; - channels->min = channels->max = - mi2s_tx_cfg[SEC_MI2S].channels; - break; - - case MSM_BACKEND_DAI_TERTIARY_MI2S_RX: - rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate; - channels->min = channels->max = - mi2s_rx_cfg[TERT_MI2S].channels; - break; - - case MSM_BACKEND_DAI_TERTIARY_MI2S_TX: - rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate; - channels->min = channels->max = - mi2s_tx_cfg[TERT_MI2S].channels; - break; - - case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX: - rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate; - channels->min = channels->max = - mi2s_rx_cfg[QUAT_MI2S].channels; - break; - - case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX: - rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate; - channels->min = channels->max = - mi2s_tx_cfg[QUAT_MI2S].channels; - break; - - default: - rate->min = rate->max = SAMPLING_RATE_48KHZ; - break; - } - return rc; -} -EXPORT_SYMBOL(msm_common_be_hw_params_fixup); - -/** - * msm_aux_pcm_snd_startup - startup ops of auxpcm. - * - * @substream: PCM stream pointer of associated backend dailink - * - * Returns 0 on success or -EINVAL on error. - */ -int msm_aux_pcm_snd_startup(struct snd_pcm_substream *substream) -{ - int ret = 0; - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct snd_soc_dai *cpu_dai = rtd->cpu_dai; - int index = cpu_dai->id - 1; - return ret = 0; - - dev_dbg(rtd->card->dev, - "%s: substream = %s stream = %d, dai name %s, dai ID %d\n", - __func__, substream->name, substream->stream, - cpu_dai->name, cpu_dai->id); - - if (index < PRIM_AUX_PCM || index > QUAT_AUX_PCM) { - ret = -EINVAL; - dev_err(rtd->card->dev, - "%s: CPU DAI id (%d) out of range\n", - __func__, cpu_dai->id); - goto done; - } - - mutex_lock(&auxpcm_intf_conf[index].lock); - if (++auxpcm_intf_conf[index].ref_cnt == 1) { - if (mi2s_auxpcm_conf[index].pcm_i2s_sel_vt_addr != NULL) { - mutex_lock(&mi2s_auxpcm_conf[index].lock); - iowrite32(1, - mi2s_auxpcm_conf[index].pcm_i2s_sel_vt_addr); - mutex_unlock(&mi2s_auxpcm_conf[index].lock); - } else { - dev_err(rtd->card->dev, - "%s lpaif_tert_muxsel_virt_addr is NULL\n", - __func__); - ret = -EINVAL; - } - } - if (IS_ERR_VALUE(ret)) - auxpcm_intf_conf[index].ref_cnt--; - - mutex_unlock(&auxpcm_intf_conf[index].lock); - -done: - return ret; -} -EXPORT_SYMBOL(msm_aux_pcm_snd_startup); - -/** - * msm_aux_pcm_snd_shutdown - shutdown ops of auxpcm. - * - * @substream: PCM stream pointer of associated backend dailink - */ -void msm_aux_pcm_snd_shutdown(struct snd_pcm_substream *substream) -{ - struct snd_soc_pcm_runtime *rtd = substream->private_data; - int index = rtd->cpu_dai->id - 1; - - dev_dbg(rtd->card->dev, - "%s: substream = %s stream = %d, dai name %s, dai ID %d\n", - __func__, - substream->name, substream->stream, - rtd->cpu_dai->name, rtd->cpu_dai->id); - - if (index < PRIM_AUX_PCM || index > QUAT_AUX_PCM) { - dev_err(rtd->card->dev, - "%s: CPU DAI id (%d) out of range\n", - __func__, rtd->cpu_dai->id); - return; - } - - mutex_lock(&auxpcm_intf_conf[index].lock); - if (--auxpcm_intf_conf[index].ref_cnt == 0) { - if (mi2s_auxpcm_conf[index].pcm_i2s_sel_vt_addr != NULL) { - mutex_lock(&mi2s_auxpcm_conf[index].lock); - iowrite32(0, - mi2s_auxpcm_conf[index].pcm_i2s_sel_vt_addr); - mutex_unlock(&mi2s_auxpcm_conf[index].lock); - } else { - dev_err(rtd->card->dev, - "%s lpaif_tert_muxsel_virt_addr is NULL\n", - __func__); - auxpcm_intf_conf[index].ref_cnt++; - } - } - mutex_unlock(&auxpcm_intf_conf[index].lock); -} -EXPORT_SYMBOL(msm_aux_pcm_snd_shutdown); - -static int msm_get_port_id(int be_id) -{ - int afe_port_id; - - switch (be_id) { - case MSM_BACKEND_DAI_PRI_MI2S_RX: - afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX; - break; - case MSM_BACKEND_DAI_PRI_MI2S_TX: - afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX; - break; - case MSM_BACKEND_DAI_SECONDARY_MI2S_RX: - afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX; - break; - case MSM_BACKEND_DAI_SECONDARY_MI2S_TX: - afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX; - break; - case MSM_BACKEND_DAI_TERTIARY_MI2S_RX: - afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX; - break; - case MSM_BACKEND_DAI_TERTIARY_MI2S_TX: - afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX; - break; - case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX: - afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX; - break; - case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX: - afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX; - break; - default: - pr_err("%s: Invalid be_id: %d\n", __func__, be_id); - afe_port_id = -EINVAL; - } - - return afe_port_id; -} - -static u32 get_mi2s_bits_per_sample(u32 bit_format) -{ - u32 bit_per_sample; - - switch (bit_format) { - case SNDRV_PCM_FORMAT_S24_3LE: - case SNDRV_PCM_FORMAT_S24_LE: - bit_per_sample = 32; - break; - case SNDRV_PCM_FORMAT_S16_LE: - default: - bit_per_sample = 16; - break; - } - - return bit_per_sample; -} - -static void update_mi2s_clk_val(int dai_id, int stream) -{ - u32 bit_per_sample; - - if (stream == SNDRV_PCM_STREAM_PLAYBACK) { - bit_per_sample = - get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format); - mi2s_clk[dai_id].clk_freq_in_hz = - mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample; - } else { - bit_per_sample = - get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format); - mi2s_clk[dai_id].clk_freq_in_hz = - mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample; - } - - if (!mi2s_intf_conf[dai_id].msm_is_mi2s_master) - mi2s_clk[dai_id].clk_freq_in_hz = 0; -} - -static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable) -{ - int ret = 0; - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct snd_soc_dai *cpu_dai = rtd->cpu_dai; - int port_id = 0; - int index = cpu_dai->id; - - port_id = msm_get_port_id(rtd->dai_link->be_id); - if (IS_ERR_VALUE(port_id)) { - dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__); - ret = port_id; - goto done; - } - - if (enable) { - update_mi2s_clk_val(index, substream->stream); - dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__, - mi2s_clk[index].clk_freq_in_hz); - } - - mi2s_clk[index].enable = enable; - ret = afe_set_lpass_clock_v2(port_id, - &mi2s_clk[index]); - if (ret < 0) { - dev_err(rtd->card->dev, - "%s: afe lpass clock failed for port 0x%x , err:%d\n", - __func__, port_id, ret); - goto done; - } - -done: - return ret; -} - -/** - * msm_mi2s_snd_startup - startup ops of mi2s. - * - * @substream: PCM stream pointer of associated backend dailink - * - * Returns 0 on success or -EINVAL on error. - */ -int msm_mi2s_snd_startup(struct snd_pcm_substream *substream) -{ - int ret = 0; - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct snd_soc_dai *cpu_dai = rtd->cpu_dai; - int index = cpu_dai->id; - unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS; - - dev_dbg(rtd->card->dev, - "%s: substream = %s stream = %d, dai name %s, dai ID %d\n", - __func__, substream->name, substream->stream, - cpu_dai->name, cpu_dai->id); - - if (index < PRIM_MI2S || index > QUAT_MI2S) { - ret = -EINVAL; - dev_err(rtd->card->dev, - "%s: CPU DAI id (%d) out of range\n", - __func__, cpu_dai->id); - goto done; - } - /* - * Muxtex protection in case the same MI2S - * interface using for both TX and RX so - * that the same clock won't be enable twice. - */ - mutex_lock(&mi2s_intf_conf[index].lock); - if (++mi2s_intf_conf[index].ref_cnt == 1) { - ret = msm_mi2s_set_sclk(substream, true); - if (IS_ERR_VALUE(ret)) { - dev_err(rtd->card->dev, - "%s: afe lpass clock failed to enable MI2S clock, err:%d\n", - __func__, ret); - goto clean_up; - } - if (mi2s_auxpcm_conf[index].pcm_i2s_sel_vt_addr != NULL) { - mutex_lock(&mi2s_auxpcm_conf[index].lock); - iowrite32(0, - mi2s_auxpcm_conf[index].pcm_i2s_sel_vt_addr); - mutex_unlock(&mi2s_auxpcm_conf[index].lock); - } else { - dev_err(rtd->card->dev, - "%s lpaif_muxsel_virt_addr is NULL for dai %d\n", - __func__, index); - ret = -EINVAL; - goto clk_off; - } - /* Check if msm needs to provide the clock to the interface */ - if (!mi2s_intf_conf[index].msm_is_mi2s_master) - fmt = SND_SOC_DAIFMT_CBM_CFM; - ret = snd_soc_dai_set_fmt(cpu_dai, fmt); - if (IS_ERR_VALUE(ret)) { - dev_err(rtd->card->dev, - "%s: set fmt cpu dai failed for MI2S (%d), err:%d\n", - __func__, index, ret); - goto clk_off; - } - } -clk_off: - if (IS_ERR_VALUE(ret)) - msm_mi2s_set_sclk(substream, false); -clean_up: - if (IS_ERR_VALUE(ret)) - mi2s_intf_conf[index].ref_cnt--; - mutex_unlock(&mi2s_intf_conf[index].lock); -done: - return ret; -} -EXPORT_SYMBOL(msm_mi2s_snd_startup); - -/** - * msm_mi2s_snd_shutdown - shutdown ops of mi2s. - * - * @substream: PCM stream pointer of associated backend dailink - */ -void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream) -{ - int ret; - struct snd_soc_pcm_runtime *rtd = substream->private_data; - int index = rtd->cpu_dai->id; - - pr_debug("%s(): substream = %s stream = %d\n", __func__, - substream->name, substream->stream); - if (index < PRIM_MI2S || index > QUAT_MI2S) { - pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index); - return; - } - - mutex_lock(&mi2s_intf_conf[index].lock); - if (--mi2s_intf_conf[index].ref_cnt == 0) { - ret = msm_mi2s_set_sclk(substream, false); - if (ret < 0) { - pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n", - __func__, index, ret); - mi2s_intf_conf[index].ref_cnt++; - } - } - mutex_unlock(&mi2s_intf_conf[index].lock); -} -EXPORT_SYMBOL(msm_mi2s_snd_shutdown); - -/* Validate whether US EU switch is present or not */ -static int msm_prepare_us_euro(struct snd_soc_card *card) -{ - struct msm_asoc_mach_data *pdata = - snd_soc_card_get_drvdata(card); - int ret = 0; - - if (pdata->us_euro_gpio >= 0) { - dev_dbg(card->dev, "%s: us_euro gpio request %d", __func__, - pdata->us_euro_gpio); - ret = gpio_request(pdata->us_euro_gpio, "TASHA_CODEC_US_EURO"); - if (ret) { - dev_err(card->dev, - "%s: Failed to request codec US/EURO gpio %d error %d\n", - __func__, pdata->us_euro_gpio, ret); - } - } - - return ret; -} - -static bool msm_swap_gnd_mic(struct snd_soc_codec *codec) -{ - struct snd_soc_card *card = codec->component.card; - struct msm_asoc_mach_data *pdata = - snd_soc_card_get_drvdata(card); - int value = 0; - - if (pdata->us_euro_gpio_p) { - value = msm_cdc_pinctrl_get_state(pdata->us_euro_gpio_p); - if (value) - msm_cdc_pinctrl_select_sleep_state( - pdata->us_euro_gpio_p); - else - msm_cdc_pinctrl_select_active_state( - pdata->us_euro_gpio_p); - } else if (pdata->us_euro_gpio >= 0) { - value = gpio_get_value_cansleep(pdata->us_euro_gpio); - gpio_set_value_cansleep(pdata->us_euro_gpio, !value); - } - pr_debug("%s: swap select switch %d to %d\n", __func__, value, !value); - return true; -} - -static int msm_populate_dai_link_component_of_node( - struct msm_asoc_mach_data *pdata, - struct snd_soc_card *card) -{ - int i, index, ret = 0; - struct device *cdev = card->dev; - struct snd_soc_dai_link *dai_link = card->dai_link; - struct device_node *phandle; - - if (!cdev) { - pr_err("%s: Sound card device memory NULL\n", __func__); - return -ENODEV; - } - - for (i = 0; i < card->num_links; i++) { - if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node) - continue; - - /* populate platform_of_node for snd card dai links */ - if (dai_link[i].platform_name && - !dai_link[i].platform_of_node) { - index = of_property_match_string(cdev->of_node, - "asoc-platform-names", - dai_link[i].platform_name); - if (index < 0) { - pr_err("%s: No match found for platform name: %s\n", - __func__, dai_link[i].platform_name); - ret = index; - goto cpu_dai; - } - phandle = of_parse_phandle(cdev->of_node, - "asoc-platform", - index); - if (!phandle) { - pr_err("%s: retrieving phandle for platform %s, index %d failed\n", - __func__, dai_link[i].platform_name, - index); - ret = -ENODEV; - goto err; - } - dai_link[i].platform_of_node = phandle; - dai_link[i].platform_name = NULL; - } -cpu_dai: - /* populate cpu_of_node for snd card dai links */ - if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) { - index = of_property_match_string(cdev->of_node, - "asoc-cpu-names", - dai_link[i].cpu_dai_name); - if (index < 0) - goto codec_dai; - phandle = of_parse_phandle(cdev->of_node, "asoc-cpu", - index); - if (!phandle) { - pr_err("%s: retrieving phandle for cpu dai %s failed\n", - __func__, dai_link[i].cpu_dai_name); - ret = -ENODEV; - goto err; - } - dai_link[i].cpu_of_node = phandle; - dai_link[i].cpu_dai_name = NULL; - } -codec_dai: - /* populate codec_of_node for snd card dai links */ - if (dai_link[i].codec_name && !dai_link[i].codec_of_node) { - index = of_property_match_string(cdev->of_node, - "asoc-codec-names", - dai_link[i].codec_name); - if (index < 0) - continue; - phandle = of_parse_phandle(cdev->of_node, "asoc-codec", - index); - if (!phandle) { - pr_err("%s: retrieving phandle for codec dai %s failed\n", - __func__, dai_link[i].codec_name); - ret = -ENODEV; - goto err; - } - dai_link[i].codec_of_node = phandle; - dai_link[i].codec_name = NULL; - } - if (pdata->snd_card_val == INT_SND_CARD) { - if ((dai_link[i].be_id == - MSM_BACKEND_DAI_INT0_MI2S_RX) || - (dai_link[i].be_id == - MSM_BACKEND_DAI_INT1_MI2S_RX) || - (dai_link[i].be_id == - MSM_BACKEND_DAI_INT2_MI2S_TX) || - (dai_link[i].be_id == - MSM_BACKEND_DAI_INT3_MI2S_TX)) { - index = of_property_match_string(cdev->of_node, - "asoc-codec-names", - MSM_INT_DIGITAL_CODEC); - phandle = of_parse_phandle(cdev->of_node, - "asoc-codec", - index); - dai_link[i].codecs[DIG_CDC].of_node = phandle; - index = of_property_match_string(cdev->of_node, - "asoc-codec-names", - PMIC_INT_ANALOG_CODEC); - phandle = of_parse_phandle(cdev->of_node, - "asoc-codec", - index); - dai_link[i].codecs[ANA_CDC].of_node = phandle; - } - } - } -err: - return ret; -} - -static int msm_wsa881x_init(struct snd_soc_component *component) -{ - u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {100, 101, 102, 106}; - u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {103, 104, 105, 107}; - unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200}; - unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3}; - struct snd_soc_codec *codec = snd_soc_component_to_codec(component); - struct msm_asoc_mach_data *pdata; - struct snd_soc_dapm_context *dapm = - snd_soc_codec_get_dapm(codec); - - if (!codec) { - pr_err("%s codec is NULL\n", __func__); - return -EINVAL; - } - - if (!strcmp(component->name_prefix, "SpkrLeft")) { - dev_dbg(codec->dev, "%s: setting left ch map to codec %s\n", - __func__, codec->component.name); - wsa881x_set_channel_map(codec, &spkleft_ports[0], - WSA881X_MAX_SWR_PORTS, &ch_mask[0], - &ch_rate[0]); - if (dapm->component) { - snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN"); - snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR"); - } - } else if (!strcmp(component->name_prefix, "SpkrRight")) { - dev_dbg(codec->dev, "%s: setting right ch map to codec %s\n", - __func__, codec->component.name); - wsa881x_set_channel_map(codec, &spkright_ports[0], - WSA881X_MAX_SWR_PORTS, &ch_mask[0], - &ch_rate[0]); - if (dapm->component) { - snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN"); - snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR"); - } - } else { - dev_err(codec->dev, "%s: wrong codec name %s\n", __func__, - codec->component.name); - return -EINVAL; - } - - - pdata = snd_soc_card_get_drvdata(component->card); - if (pdata && pdata->codec_root) - wsa881x_codec_info_create_codec_entry(pdata->codec_root, - codec); - return 0; -} - - -static int msm_init_wsa_dev(struct platform_device *pdev, - struct snd_soc_card *card) -{ - struct device_node *wsa_of_node; - u32 wsa_max_devs; - u32 wsa_dev_cnt; - char *dev_name_str = NULL; - struct msm_wsa881x_dev_info *wsa881x_dev_info; - const char *wsa_auxdev_name_prefix[1]; - int found = 0; - int i; - int ret; - - /* Get maximum WSA device count for this platform */ - ret = of_property_read_u32(pdev->dev.of_node, - "qcom,wsa-max-devs", &wsa_max_devs); - if (ret) { - dev_dbg(&pdev->dev, - "%s: wsa-max-devs property missing in DT %s, ret = %d\n", - __func__, pdev->dev.of_node->full_name, ret); - goto err_dt; - } - if (wsa_max_devs == 0) { - dev_warn(&pdev->dev, - "%s: Max WSA devices is 0 for this target?\n", - __func__); - goto err_dt; - } - - /* Get count of WSA device phandles for this platform */ - wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node, - "qcom,wsa-devs", NULL); - if (wsa_dev_cnt == -ENOENT) { - dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n", - __func__); - goto err_dt; - } else if (wsa_dev_cnt <= 0) { - dev_err(&pdev->dev, - "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n", - __func__, wsa_dev_cnt); - ret = -EINVAL; - goto err_dt; - } - - /* - * Expect total phandles count to be NOT less than maximum possible - * WSA count. However, if it is less, then assign same value to - * max count as well. - */ - if (wsa_dev_cnt < wsa_max_devs) { - dev_dbg(&pdev->dev, - "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n", - __func__, wsa_max_devs, wsa_dev_cnt); - wsa_max_devs = wsa_dev_cnt; - } - - /* Make sure prefix string passed for each WSA device */ - ret = of_property_count_strings(pdev->dev.of_node, - "qcom,wsa-aux-dev-prefix"); - if (ret != wsa_dev_cnt) { - dev_err(&pdev->dev, - "%s: expecting %d wsa prefix. Defined only %d in DT\n", - __func__, wsa_dev_cnt, ret); - ret = -EINVAL; - goto err_dt; - } - - /* - * Alloc mem to store phandle and index info of WSA device, if already - * registered with ALSA core - */ - wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs, - sizeof(struct msm_wsa881x_dev_info), - GFP_KERNEL); - if (!wsa881x_dev_info) { - ret = -ENOMEM; - goto err_mem; - } - - /* - * search and check whether all WSA devices are already - * registered with ALSA core or not. If found a node, store - * the node and the index in a local array of struct for later - * use. - */ - for (i = 0; i < wsa_dev_cnt; i++) { - wsa_of_node = of_parse_phandle(pdev->dev.of_node, - "qcom,wsa-devs", i); - if (unlikely(!wsa_of_node)) { - /* we should not be here */ - dev_err(&pdev->dev, - "%s: wsa dev node is not present\n", - __func__); - ret = -EINVAL; - goto err_dev_node; - } - if (soc_find_component(wsa_of_node, NULL)) { - /* WSA device registered with ALSA core */ - wsa881x_dev_info[found].of_node = wsa_of_node; - wsa881x_dev_info[found].index = i; - found++; - if (found == wsa_max_devs) - break; - } - } - - if (found < wsa_max_devs) { - dev_dbg(&pdev->dev, - "%s: failed to find %d components. Found only %d\n", - __func__, wsa_max_devs, found); - return -EPROBE_DEFER; - } - dev_info(&pdev->dev, - "%s: found %d wsa881x devices registered with ALSA core\n", - __func__, found); - - card->num_aux_devs = wsa_max_devs; - card->num_configs = wsa_max_devs; - - /* Alloc array of AUX devs struct */ - msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs, - sizeof(struct snd_soc_aux_dev), - GFP_KERNEL); - if (!msm_aux_dev) { - ret = -ENOMEM; - goto err_auxdev_mem; - } - - /* Alloc array of codec conf struct */ - msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs, - sizeof(struct snd_soc_codec_conf), - GFP_KERNEL); - if (!msm_codec_conf) { - ret = -ENOMEM; - goto err_codec_conf; - } - - for (i = 0; i < card->num_aux_devs; i++) { - dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN, - GFP_KERNEL); - if (!dev_name_str) { - ret = -ENOMEM; - goto err_dev_str; - } - - ret = of_property_read_string_index(pdev->dev.of_node, - "qcom,wsa-aux-dev-prefix", - wsa881x_dev_info[i].index, - wsa_auxdev_name_prefix); - if (ret) { - dev_err(&pdev->dev, - "%s: failed to read wsa aux dev prefix, ret = %d\n", - __func__, ret); - ret = -EINVAL; - goto err_dt_prop; - } - - snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i); - msm_aux_dev[i].name = dev_name_str; - msm_aux_dev[i].codec_name = NULL; - msm_aux_dev[i].codec_of_node = - wsa881x_dev_info[i].of_node; - msm_aux_dev[i].init = msm_wsa881x_init; - msm_codec_conf[i].dev_name = NULL; - msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0]; - msm_codec_conf[i].of_node = wsa881x_dev_info[i].of_node; - } - card->codec_conf = msm_codec_conf; - card->aux_dev = msm_aux_dev; - - return 0; - -err_dt_prop: - devm_kfree(&pdev->dev, dev_name_str); -err_dev_str: - devm_kfree(&pdev->dev, msm_codec_conf); -err_codec_conf: - devm_kfree(&pdev->dev, msm_aux_dev); -err_auxdev_mem: -err_dev_node: - devm_kfree(&pdev->dev, wsa881x_dev_info); -err_mem: -err_dt: - return ret; -} - -static void msm_free_auxdev_mem(struct platform_device *pdev) -{ - struct snd_soc_card *card = platform_get_drvdata(pdev); - int i; - - if (card->num_aux_devs > 0) { - for (i = 0; i < card->num_aux_devs; i++) { - kfree(msm_aux_dev[i].codec_name); - kfree(msm_codec_conf[i].dev_name); - kfree(msm_codec_conf[i].name_prefix); - } - } -} - -static void i2s_auxpcm_init(struct platform_device *pdev) -{ - struct resource *muxsel; - int count; - u32 mi2s_master_slave[MI2S_MAX]; - int ret; - char *str[PCM_I2S_SEL_MAX] = { - "lpaif_pri_mode_muxsel", - "lpaif_sec_mode_muxsel", - "lpaif_tert_mode_muxsel", - "lpaif_quat_mode_muxsel" - }; - - for (count = 0; count < MI2S_MAX; count++) { - mutex_init(&mi2s_intf_conf[count].lock); - mi2s_intf_conf[count].ref_cnt = 0; - } - - for (count = 0; count < AUX_PCM_MAX; count++) { - mutex_init(&auxpcm_intf_conf[count].lock); - auxpcm_intf_conf[count].ref_cnt = 0; - } - - for (count = 0; count < PCM_I2S_SEL_MAX; count++) { - mutex_init(&mi2s_auxpcm_conf[count].lock); - mi2s_auxpcm_conf[count].pcm_i2s_sel_vt_addr = NULL; - } - - for (count = 0; count < PCM_I2S_SEL_MAX; count++) { - muxsel = platform_get_resource_byname(pdev, IORESOURCE_MEM, - str[count]); - if (muxsel) { - mi2s_auxpcm_conf[count].pcm_i2s_sel_vt_addr - = ioremap(muxsel->start, resource_size(muxsel)); - } - } - - ret = of_property_read_u32_array(pdev->dev.of_node, - "qcom,msm-mi2s-master", - mi2s_master_slave, MI2S_MAX); - if (ret) { - dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n", - __func__); - } else { - for (count = 0; count < MI2S_MAX; count++) { - mi2s_intf_conf[count].msm_is_mi2s_master = - mi2s_master_slave[count]; - } - } -} - -static void i2s_auxpcm_deinit(void) -{ - int count; - - for (count = 0; count < PCM_I2S_SEL_MAX; count++) - if (mi2s_auxpcm_conf[count].pcm_i2s_sel_vt_addr != - NULL) - iounmap( - mi2s_auxpcm_conf[count].pcm_i2s_sel_vt_addr); -} - -static const struct of_device_id msmfalcon_asoc_machine_of_match[] = { - { .compatible = "qcom,msmfalcon-asoc-snd", - .data = "internal_codec"}, - { .compatible = "qcom,msmfalcon-asoc-snd-tasha", - .data = "tasha_codec"}, - { .compatible = "qcom,msmfalcon-asoc-snd-tavil", - .data = "tavil_codec"}, - {}, -}; - -static int msm_asoc_machine_probe(struct platform_device *pdev) -{ - struct snd_soc_card *card = NULL; - struct msm_asoc_mach_data *pdata = NULL; - const char *mclk = "qcom,msm-mclk-freq"; - int ret = -EINVAL, id; - const struct of_device_id *match; - - pdata = devm_kzalloc(&pdev->dev, - sizeof(struct msm_asoc_mach_data), - GFP_KERNEL); - if (!pdata) - return -ENOMEM; - - match = of_match_node(msmfalcon_asoc_machine_of_match, - pdev->dev.of_node); - if (!match) - goto err; - - ret = of_property_read_u32(pdev->dev.of_node, mclk, &id); - if (ret) { - dev_err(&pdev->dev, - "%s: missing %s in dt node\n", __func__, mclk); - id = DEFAULT_MCLK_RATE; - } - pdata->mclk_freq = id; - - if (!strcmp(match->data, "tasha_codec") || - !strcmp(match->data, "tavil_codec")) { - if (!strcmp(match->data, "tasha_codec")) - pdata->snd_card_val = EXT_SND_CARD_TASHA; - else - pdata->snd_card_val = EXT_SND_CARD_TAVIL; - ret = msm_ext_cdc_init(pdev, pdata, &card, &mbhc_cfg); - if (ret) - goto err; - } else if (!strcmp(match->data, "internal_codec")) { - pdata->snd_card_val = INT_SND_CARD; - ret = msm_int_cdc_init(pdev, pdata, &card, &mbhc_cfg); - if (ret) - goto err; - } else { - dev_err(&pdev->dev, - "%s: Not a matching DT sound node\n", __func__); - goto err; - } - if (!card) - goto err; - - if (pdata->snd_card_val == INT_SND_CARD) { - /*reading the gpio configurations from dtsi file*/ - pdata->pdm_gpio_p = of_parse_phandle(pdev->dev.of_node, - "qcom,cdc-pdm-gpios", 0); - pdata->comp_gpio_p = of_parse_phandle(pdev->dev.of_node, - "qcom,cdc-comp-gpios", 0); - pdata->sdw_gpio_p = of_parse_phandle(pdev->dev.of_node, - "qcom,cdc-sdw-gpios", 0); - pdata->dmic_gpio_p = of_parse_phandle(pdev->dev.of_node, - "qcom,cdc-dmic-gpios", 0); - pdata->ext_spk_gpio_p = of_parse_phandle(pdev->dev.of_node, - "qcom,cdc-ext-spk-gpios", 0); - } - - /* - * Parse US-Euro gpio info from DT. Report no error if us-euro - * entry is not found in DT file as some targets do not support - * US-Euro detection - */ - pdata->us_euro_gpio = of_get_named_gpio(pdev->dev.of_node, - "qcom,us-euro-gpios", 0); - if (!gpio_is_valid(pdata->us_euro_gpio)) - pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node, - "qcom,us-euro-gpios", 0); - if (!gpio_is_valid(pdata->us_euro_gpio) && (!pdata->us_euro_gpio_p)) { - dev_dbg(&pdev->dev, "property %s not detected in node %s", - "qcom,us-euro-gpios", pdev->dev.of_node->full_name); - } else { - dev_dbg(&pdev->dev, "%s detected", - "qcom,us-euro-gpios"); - mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic; - } - - ret = msm_prepare_us_euro(card); - if (ret) - dev_dbg(&pdev->dev, "msm_prepare_us_euro failed (%d)\n", - ret); - - i2s_auxpcm_init(pdev); - - ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing"); - if (ret) - goto err; - - ret = msm_populate_dai_link_component_of_node(pdata, card); - if (ret) { - ret = -EPROBE_DEFER; - goto err; - } - ret = msm_init_wsa_dev(pdev, card); - if (ret) - goto err; - - - ret = devm_snd_soc_register_card(&pdev->dev, card); - if (ret) { - dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", - ret); - goto err; - } - return 0; -err: - if (pdata->us_euro_gpio > 0) { - dev_dbg(&pdev->dev, "%s free us_euro gpio %d\n", - __func__, pdata->us_euro_gpio); - pdata->us_euro_gpio = 0; - } - if (pdata->hph_en1_gpio > 0) { - dev_dbg(&pdev->dev, "%s free hph_en1_gpio %d\n", - __func__, pdata->hph_en1_gpio); - gpio_free(pdata->hph_en1_gpio); - pdata->hph_en1_gpio = 0; - } - if (pdata->hph_en0_gpio > 0) { - dev_dbg(&pdev->dev, "%s free hph_en0_gpio %d\n", - __func__, pdata->hph_en0_gpio); - gpio_free(pdata->hph_en0_gpio); - pdata->hph_en0_gpio = 0; - } - devm_kfree(&pdev->dev, pdata); - if (pdata->snd_card_val != INT_SND_CARD) - msm_ext_cdc_deinit(); - return ret; -} - -static int msm_asoc_machine_remove(struct platform_device *pdev) -{ - struct snd_soc_card *card = platform_get_drvdata(pdev); - struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); - - if (pdata->snd_card_val == INT_SND_CARD) - mutex_destroy(&pdata->cdc_int_mclk0_mutex); - else - msm_ext_cdc_deinit(); - msm_free_auxdev_mem(pdev); - - gpio_free(pdata->us_euro_gpio); - gpio_free(pdata->hph_en1_gpio); - gpio_free(pdata->hph_en0_gpio); - i2s_auxpcm_deinit(); - snd_soc_unregister_card(card); - return 0; -} - -static struct platform_driver msmfalcon_asoc_machine_driver = { - .driver = { - .name = DRV_NAME, - .owner = THIS_MODULE, - .pm = &snd_soc_pm_ops, - .of_match_table = msmfalcon_asoc_machine_of_match, - }, - .probe = msm_asoc_machine_probe, - .remove = msm_asoc_machine_remove, -}; -module_platform_driver(msmfalcon_asoc_machine_driver); - -MODULE_DESCRIPTION("ALSA SoC msm"); -MODULE_LICENSE("GPL v2"); -MODULE_ALIAS("platform:" DRV_NAME); -MODULE_DEVICE_TABLE(of, msmfalcon_asoc_machine_of_match); diff --git a/sound/soc/msm/msmfalcon-common.h b/sound/soc/msm/msmfalcon-common.h deleted file mode 100644 index 3c18852cf897..000000000000 --- a/sound/soc/msm/msmfalcon-common.h +++ /dev/null @@ -1,115 +0,0 @@ -/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MSM_COMMON -#define __MSM_COMMON - -#include -#include -#include "../codecs/wcd-mbhc-v2.h" - -#define SAMPLING_RATE_8KHZ 8000 -#define SAMPLING_RATE_11P025KHZ 11025 -#define SAMPLING_RATE_16KHZ 16000 -#define SAMPLING_RATE_22P05KHZ 22050 -#define SAMPLING_RATE_32KHZ 32000 -#define SAMPLING_RATE_44P1KHZ 44100 -#define SAMPLING_RATE_48KHZ 48000 -#define SAMPLING_RATE_88P2KHZ 88200 -#define SAMPLING_RATE_96KHZ 96000 -#define SAMPLING_RATE_176P4KHZ 176400 -#define SAMPLING_RATE_192KHZ 192000 -#define SAMPLING_RATE_352P8KHZ 352800 -#define SAMPLING_RATE_384KHZ 384000 - -#define TDM_CHANNEL_MAX 8 -#define TDM_SLOT_OFFSET_MAX 8 - -enum { - TDM_0 = 0, - TDM_1, - TDM_2, - TDM_3, - TDM_4, - TDM_5, - TDM_6, - TDM_7, - TDM_PORT_MAX, -}; - -enum { - TDM_PRI = 0, - TDM_SEC, - TDM_TERT, - TDM_QUAT, - TDM_INTERFACE_MAX, -}; - -struct tdm_port { - u32 mode; - u32 channel; -}; - -enum { - DIG_CDC, - ANA_CDC, - CODECS_MAX, -}; - -extern const struct snd_kcontrol_new msm_common_snd_controls[]; -struct msmfalcon_codec { - void* (*get_afe_config_fn)(struct snd_soc_codec *codec, - enum afe_config_type config_type); -}; - -enum { - INT_SND_CARD, - EXT_SND_CARD_TASHA, - EXT_SND_CARD_TAVIL, -}; - -struct msm_asoc_mach_data { - int us_euro_gpio; /* used by gpio driver API */ - int hph_en1_gpio; - int hph_en0_gpio; - struct device_node *us_euro_gpio_p; /* used by pinctrl API */ - struct device_node *hph_en1_gpio_p; /* used by pinctrl API */ - struct device_node *hph_en0_gpio_p; /* used by pinctrl API */ - struct device_node *pdm_gpio_p; /* used by pinctrl API */ - struct device_node *comp_gpio_p; /* used by pinctrl API */ - struct device_node *sdw_gpio_p; /* used by pinctrl API */ - struct device_node *dmic_gpio_p; /* used by pinctrl API */ - struct device_node *ext_spk_gpio_p; /* used by pinctrl API */ - struct snd_soc_codec *codec; - struct msmfalcon_codec msmfalcon_codec_fn; - struct snd_info_entry *codec_root; - int spk_ext_pa_gpio; - int mclk_freq; - bool native_clk_set; - int lb_mode; - int snd_card_val; - u8 micbias1_cap_mode; - u8 micbias2_cap_mode; - atomic_t int_mclk0_rsc_ref; - atomic_t int_mclk0_enabled; - struct mutex cdc_int_mclk0_mutex; - struct delayed_work disable_int_mclk0_work; - struct afe_clk_set digital_cdc_core_clk; -}; - -int msm_common_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, - struct snd_pcm_hw_params *params); -int msm_aux_pcm_snd_startup(struct snd_pcm_substream *substream); -void msm_aux_pcm_snd_shutdown(struct snd_pcm_substream *substream); -int msm_mi2s_snd_startup(struct snd_pcm_substream *substream); -void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream); -#endif diff --git a/sound/soc/msm/msmfalcon-ext-dai-links.c b/sound/soc/msm/msmfalcon-ext-dai-links.c deleted file mode 100644 index fc6d52233a33..000000000000 --- a/sound/soc/msm/msmfalcon-ext-dai-links.c +++ /dev/null @@ -1,1968 +0,0 @@ -/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "qdsp6v2/msm-pcm-routing-v2.h" -#include "../codecs/wcd9335.h" -#include "msmfalcon-common.h" -#include "msmfalcon-external.h" - -#define DEV_NAME_STR_LEN 32 -#define __CHIPSET__ "MSMFALCON " -#define MSM_DAILINK_NAME(name) (__CHIPSET__#name) - -#define WCN_CDC_SLIM_RX_CH_MAX 2 -#define WCN_CDC_SLIM_TX_CH_MAX 3 - -static struct snd_soc_card snd_soc_card_msm_card_tavil; -static struct snd_soc_card snd_soc_card_msm_card_tasha; - -static struct snd_soc_ops msm_ext_slimbus_be_ops = { - .hw_params = msm_snd_hw_params, -}; - -static struct snd_soc_ops msm_ext_cpe_ops = { - .hw_params = msm_snd_cpe_hw_params, -}; - -static struct snd_soc_ops msm_ext_slimbus_2_be_ops = { - .hw_params = msm_ext_slimbus_2_hw_params, -}; - -static struct snd_soc_ops msm_mi2s_be_ops = { - .startup = msm_mi2s_snd_startup, - .shutdown = msm_mi2s_snd_shutdown, -}; - -static struct snd_soc_ops msm_aux_pcm_be_ops = { - .startup = msm_aux_pcm_snd_startup, - .shutdown = msm_aux_pcm_snd_shutdown, -}; - -static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd) -{ - unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158}; - unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161}; - struct snd_soc_dai *codec_dai = rtd->codec_dai; - - return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch), - tx_ch, ARRAY_SIZE(rx_ch), rx_ch); -} - -static int msm_wcn_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params) -{ - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct snd_soc_dai *codec_dai = rtd->codec_dai; - struct snd_soc_dai *cpu_dai = rtd->cpu_dai; - struct snd_soc_dai_link *dai_link = rtd->dai_link; - u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX]; - u32 rx_ch_cnt = 0, tx_ch_cnt = 0; - int ret; - - dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__, - codec_dai->name, codec_dai->id); - ret = snd_soc_dai_get_channel_map(codec_dai, - &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch); - if (ret) { - dev_err(rtd->dev, - "%s: failed to get BTFM codec chan map\n, err:%d\n", - __func__, ret); - goto exit; - } - - dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) be_id %d\n", - __func__, tx_ch_cnt, dai_link->be_id); - - ret = snd_soc_dai_set_channel_map(cpu_dai, - tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch); - if (ret) - dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n", - __func__, ret); - -exit: - return ret; -} - -static struct snd_soc_ops msm_wcn_ops = { - .hw_params = msm_wcn_hw_params, -}; - -/*TDM default offset currently only supporting TDM_RX_0 and TDM_TX_0 */ -static unsigned int tdm_slot_offset[TDM_PORT_MAX][TDM_SLOT_OFFSET_MAX] = { - {0, 4, 8, 12, 16, 20, 24, 28},/* TX_0 | RX_0 */ - {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_1 | RX_1 */ - {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_2 | RX_2 */ - {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_3 | RX_3 */ - {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_4 | RX_4 */ - {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_5 | RX_5 */ - {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_6 | RX_6 */ - {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_7 | RX_7 */ -}; - -static unsigned int tdm_param_set_slot_mask(u16 port_id, int slot_width, - int slots) -{ - unsigned int slot_mask = 0; - int i, j; - unsigned int *slot_offset; - - for (i = TDM_0; i < TDM_PORT_MAX; i++) { - slot_offset = tdm_slot_offset[i]; - - for (j = 0; j < TDM_SLOT_OFFSET_MAX; j++) { - if (slot_offset[j] != AFE_SLOT_MAPPING_OFFSET_INVALID) - slot_mask |= - (1 << ((slot_offset[j] * 8) / slot_width)); - else - break; - } - } - - return slot_mask; -} - -static int msm_tdm_snd_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params) -{ - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct snd_soc_dai *cpu_dai = rtd->cpu_dai; - int ret = 0; - int channels, slot_width, slots; - unsigned int slot_mask; - unsigned int *slot_offset; - int offset_channels = 0; - int i; - - pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id); - - channels = params_channels(params); - switch (channels) { - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: - case 8: - switch (params_format(params)) { - case SNDRV_PCM_FORMAT_S32_LE: - case SNDRV_PCM_FORMAT_S24_LE: - case SNDRV_PCM_FORMAT_S16_LE: - /* - * up to 8 channels HW config should - * use 32 bit slot width for max support of - * stream bit width. (slot_width > bit_width) - */ - slot_width = 32; - break; - default: - pr_err("%s: invalid param format 0x%x\n", - __func__, params_format(params)); - return -EINVAL; - } - slots = 8; - slot_mask = tdm_param_set_slot_mask(cpu_dai->id, - slot_width, - slots); - if (!slot_mask) { - pr_err("%s: invalid slot_mask 0x%x\n", - __func__, slot_mask); - return -EINVAL; - } - break; - default: - pr_err("%s: invalid param channels %d\n", - __func__, channels); - return -EINVAL; - } - /* currently only supporting TDM_RX_0 and TDM_TX_0 */ - switch (cpu_dai->id) { - case AFE_PORT_ID_PRIMARY_TDM_RX: - case AFE_PORT_ID_SECONDARY_TDM_RX: - case AFE_PORT_ID_TERTIARY_TDM_RX: - case AFE_PORT_ID_QUATERNARY_TDM_RX: - case AFE_PORT_ID_PRIMARY_TDM_TX: - case AFE_PORT_ID_SECONDARY_TDM_TX: - case AFE_PORT_ID_TERTIARY_TDM_TX: - case AFE_PORT_ID_QUATERNARY_TDM_TX: - slot_offset = tdm_slot_offset[TDM_0]; - break; - default: - pr_err("%s: dai id 0x%x not supported\n", - __func__, cpu_dai->id); - return -EINVAL; - } - - for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) { - if (slot_offset[i] != AFE_SLOT_MAPPING_OFFSET_INVALID) - offset_channels++; - else - break; - } - - if (offset_channels == 0) { - pr_err("%s: slot offset not supported, offset_channels %d\n", - __func__, offset_channels); - return -EINVAL; - } - - if (channels > offset_channels) { - pr_err("%s: channels %d exceed offset_channels %d\n", - __func__, channels, offset_channels); - return -EINVAL; - } - - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask, - slots, slot_width); - if (ret < 0) { - pr_err("%s: failed to set tdm slot, err:%d\n", - __func__, ret); - goto end; - } - - ret = snd_soc_dai_set_channel_map(cpu_dai, 0, NULL, - channels, slot_offset); - if (ret < 0) { - pr_err("%s: failed to set channel map, err:%d\n", - __func__, ret); - goto end; - } - } else { - ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0, - slots, slot_width); - if (ret < 0) { - pr_err("%s: failed to set tdm slot, err:%d\n", - __func__, ret); - goto end; - } - - ret = snd_soc_dai_set_channel_map(cpu_dai, channels, - slot_offset, 0, NULL); - if (ret < 0) { - pr_err("%s: failed to set channel map, err:%d\n", - __func__, ret); - goto end; - } - } -end: - return ret; -} - -static struct snd_soc_ops msm_tdm_be_ops = { - .hw_params = msm_tdm_snd_hw_params -}; - -static struct snd_soc_dai_link msm_ext_tasha_fe_dai[] = { - /* tasha_vifeedback for speaker protection */ - { - .name = LPASS_BE_SLIMBUS_4_TX, - .stream_name = "Slimbus4 Capture", - .cpu_dai_name = "msm-dai-q6-dev.16393", - .platform_name = "msm-pcm-hostless", - .codec_name = "tasha_codec", - .codec_dai_name = "tasha_vifeedback", - .be_id = MSM_BACKEND_DAI_SLIMBUS_4_TX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ops = &msm_ext_slimbus_be_ops, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - }, - /* Ultrasound RX DAI Link */ - { - .name = "SLIMBUS_2 Hostless Playback", - .stream_name = "SLIMBUS_2 Hostless Playback", - .cpu_dai_name = "msm-dai-q6-dev.16388", - .platform_name = "msm-pcm-hostless", - .codec_name = "tasha_codec", - .codec_dai_name = "tasha_rx2", - .ignore_suspend = 1, - .dpcm_playback = 1, - .dpcm_capture = 1, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ops = &msm_ext_slimbus_2_be_ops, - }, - /* Ultrasound TX DAI Link */ - { - .name = "SLIMBUS_2 Hostless Capture", - .stream_name = "SLIMBUS_2 Hostless Capture", - .cpu_dai_name = "msm-dai-q6-dev.16389", - .platform_name = "msm-pcm-hostless", - .codec_name = "tasha_codec", - .codec_dai_name = "tasha_tx2", - .ignore_suspend = 1, - .dpcm_capture = 1, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ops = &msm_ext_slimbus_2_be_ops, - }, - /* CPE LSM direct dai-link */ - { - .name = "CPE Listen service", - .stream_name = "CPE Listen Audio Service", - .cpu_dai_name = "msm-dai-slim", - .platform_name = "msm-cpe-lsm", - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .dpcm_capture = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "tasha_mad1", - .codec_name = "tasha_codec", - .ops = &msm_ext_cpe_ops, - }, - { - .name = "SLIMBUS_6 Hostless Playback", - .stream_name = "SLIMBUS_6 Hostless", - .cpu_dai_name = "SLIMBUS6_HOSTLESS", - .platform_name = "msm-pcm-hostless", - .dynamic = 1, - .dpcm_playback = 1, - .dpcm_capture = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - /* this dailink has playback support */ - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - }, - /* CPE LSM EC PP direct dai-link */ - { - .name = "CPE Listen service ECPP", - .stream_name = "CPE Listen Audio Service ECPP", - .cpu_dai_name = "CPE_LSM_NOHOST", - .platform_name = "msm-cpe-lsm.3", - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "tasha_cpe", - .codec_name = "tasha_codec", - }, -}; - -static struct snd_soc_dai_link msm_ext_tavil_fe_dai[] = { - { - .name = LPASS_BE_SLIMBUS_4_TX, - .stream_name = "Slimbus4 Capture", - .cpu_dai_name = "msm-dai-q6-dev.16393", - .platform_name = "msm-pcm-hostless", - .codec_name = "tavil_codec", - .codec_dai_name = "tavil_vifeedback", - .be_id = MSM_BACKEND_DAI_SLIMBUS_4_TX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ops = &msm_ext_slimbus_be_ops, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - }, - /* Ultrasound RX DAI Link */ - { - .name = "SLIMBUS_2 Hostless Playback", - .stream_name = "SLIMBUS_2 Hostless Playback", - .cpu_dai_name = "msm-dai-q6-dev.16388", - .platform_name = "msm-pcm-hostless", - .codec_name = "tavil_codec", - .codec_dai_name = "tavil_rx2", - .ignore_suspend = 1, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ops = &msm_ext_slimbus_2_be_ops, - }, - /* Ultrasound TX DAI Link */ - { - .name = "SLIMBUS_2 Hostless Capture", - .stream_name = "SLIMBUS_2 Hostless Capture", - .cpu_dai_name = "msm-dai-q6-dev.16389", - .platform_name = "msm-pcm-hostless", - .codec_name = "tavil_codec", - .codec_dai_name = "tavil_tx2", - .ignore_suspend = 1, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ops = &msm_ext_slimbus_2_be_ops, - }, -}; - -static struct snd_soc_dai_link msm_ext_tasha_be_dai[] = { - /* Backend DAI Links */ - { - .name = LPASS_BE_SLIMBUS_0_RX, - .stream_name = "Slimbus Playback", - .cpu_dai_name = "msm-dai-q6-dev.16384", - .platform_name = "msm-pcm-routing", - .codec_name = "tasha_codec", - .codec_dai_name = "tasha_mix_rx1", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_0_RX, - .init = &msm_audrx_init, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - /* this dainlink has playback support */ - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - .ops = &msm_ext_slimbus_be_ops, - }, - { - .name = LPASS_BE_SLIMBUS_0_TX, - .stream_name = "Slimbus Capture", - .cpu_dai_name = "msm-dai-q6-dev.16385", - .platform_name = "msm-pcm-routing", - .codec_name = "tasha_codec", - .codec_dai_name = "tasha_tx1", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_0_TX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ignore_suspend = 1, - .ops = &msm_ext_slimbus_be_ops, - }, - { - .name = LPASS_BE_SLIMBUS_1_RX, - .stream_name = "Slimbus1 Playback", - .cpu_dai_name = "msm-dai-q6-dev.16386", - .platform_name = "msm-pcm-routing", - .codec_name = "tasha_codec", - .codec_dai_name = "tasha_mix_rx1", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_1_RX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ops = &msm_ext_slimbus_be_ops, - /* dai link has playback support */ - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_SLIMBUS_1_TX, - .stream_name = "Slimbus1 Capture", - .cpu_dai_name = "msm-dai-q6-dev.16387", - .platform_name = "msm-pcm-routing", - .codec_name = "tasha_codec", - .codec_dai_name = "tasha_tx3", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_1_TX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ops = &msm_ext_slimbus_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_SLIMBUS_3_RX, - .stream_name = "Slimbus3 Playback", - .cpu_dai_name = "msm-dai-q6-dev.16390", - .platform_name = "msm-pcm-routing", - .codec_name = "tasha_codec", - .codec_dai_name = "tasha_mix_rx1", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_3_RX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ops = &msm_ext_slimbus_be_ops, - /* dai link has playback support */ - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_SLIMBUS_3_TX, - .stream_name = "Slimbus3 Capture", - .cpu_dai_name = "msm-dai-q6-dev.16391", - .platform_name = "msm-pcm-routing", - .codec_name = "tasha_codec", - .codec_dai_name = "tasha_tx1", - .no_pcm = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_3_TX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ops = &msm_ext_slimbus_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_SLIMBUS_4_RX, - .stream_name = "Slimbus4 Playback", - .cpu_dai_name = "msm-dai-q6-dev.16392", - .platform_name = "msm-pcm-routing", - .codec_name = "tasha_codec", - .codec_dai_name = "tasha_mix_rx1", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_4_RX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ops = &msm_ext_slimbus_be_ops, - /* dai link has playback support */ - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_SLIMBUS_5_RX, - .stream_name = "Slimbus5 Playback", - .cpu_dai_name = "msm-dai-q6-dev.16394", - .platform_name = "msm-pcm-routing", - .codec_name = "tasha_codec", - .codec_dai_name = "tasha_rx3", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_5_RX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ops = &msm_ext_slimbus_be_ops, - /* dai link has playback support */ - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - }, - /* MAD BE */ - { - .name = LPASS_BE_SLIMBUS_5_TX, - .stream_name = "Slimbus5 Capture", - .cpu_dai_name = "msm-dai-q6-dev.16395", - .platform_name = "msm-pcm-routing", - .codec_name = "tasha_codec", - .codec_dai_name = "tasha_mad1", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_5_TX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ops = &msm_ext_slimbus_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_SLIMBUS_6_RX, - .stream_name = "Slimbus6 Playback", - .cpu_dai_name = "msm-dai-q6-dev.16396", - .platform_name = "msm-pcm-routing", - .codec_name = "tasha_codec", - .codec_dai_name = "tasha_rx4", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_6_RX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ops = &msm_ext_slimbus_be_ops, - /* dai link has playback support */ - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - }, -}; - -static struct snd_soc_dai_link msm_ext_tavil_be_dai[] = { - { - .name = LPASS_BE_SLIMBUS_0_RX, - .stream_name = "Slimbus Playback", - .cpu_dai_name = "msm-dai-q6-dev.16384", - .platform_name = "msm-pcm-routing", - .codec_name = "tavil_codec", - .codec_dai_name = "tavil_rx1", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_0_RX, - .init = &msm_audrx_init, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - /* this dainlink has playback support */ - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - .ops = &msm_ext_slimbus_be_ops, - }, - { - .name = LPASS_BE_SLIMBUS_0_TX, - .stream_name = "Slimbus Capture", - .cpu_dai_name = "msm-dai-q6-dev.16385", - .platform_name = "msm-pcm-routing", - .codec_name = "tavil_codec", - .codec_dai_name = "tavil_tx1", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_0_TX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ignore_suspend = 1, - .ops = &msm_ext_slimbus_be_ops, - }, - { - .name = LPASS_BE_SLIMBUS_1_RX, - .stream_name = "Slimbus1 Playback", - .cpu_dai_name = "msm-dai-q6-dev.16386", - .platform_name = "msm-pcm-routing", - .codec_name = "tavil_codec", - .codec_dai_name = "tavil_rx1", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_1_RX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ops = &msm_ext_slimbus_be_ops, - /* dai link has playback support */ - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_SLIMBUS_1_TX, - .stream_name = "Slimbus1 Capture", - .cpu_dai_name = "msm-dai-q6-dev.16387", - .platform_name = "msm-pcm-routing", - .codec_name = "tavil_codec", - .codec_dai_name = "tavil_tx3", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_1_TX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ops = &msm_ext_slimbus_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_SLIMBUS_2_RX, - .stream_name = "Slimbus2 Playback", - .cpu_dai_name = "msm-dai-q6-dev.16388", - .platform_name = "msm-pcm-routing", - .codec_name = "tavil_codec", - .codec_dai_name = "tavil_rx2", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_2_RX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ops = &msm_ext_slimbus_be_ops, - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_SLIMBUS_3_RX, - .stream_name = "Slimbus3 Playback", - .cpu_dai_name = "msm-dai-q6-dev.16390", - .platform_name = "msm-pcm-routing", - .codec_name = "tavil_codec", - .codec_dai_name = "tavil_rx1", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_3_RX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ops = &msm_ext_slimbus_be_ops, - /* dai link has playback support */ - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_SLIMBUS_3_TX, - .stream_name = "Slimbus3 Capture", - .cpu_dai_name = "msm-dai-q6-dev.16391", - .platform_name = "msm-pcm-routing", - .codec_name = "tavil_codec", - .codec_dai_name = "tavil_tx1", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_3_TX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ops = &msm_ext_slimbus_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_SLIMBUS_4_RX, - .stream_name = "Slimbus4 Playback", - .cpu_dai_name = "msm-dai-q6-dev.16392", - .platform_name = "msm-pcm-routing", - .codec_name = "tavil_codec", - .codec_dai_name = "tavil_rx1", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_4_RX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ops = &msm_ext_slimbus_be_ops, - /* dai link has playback support */ - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_SLIMBUS_5_RX, - .stream_name = "Slimbus5 Playback", - .cpu_dai_name = "msm-dai-q6-dev.16394", - .platform_name = "msm-pcm-routing", - .codec_name = "tavil_codec", - .codec_dai_name = "tavil_rx3", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_5_RX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ops = &msm_ext_slimbus_be_ops, - /* dai link has playback support */ - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - }, - /* MAD BE */ - { - .name = LPASS_BE_SLIMBUS_5_TX, - .stream_name = "Slimbus5 Capture", - .cpu_dai_name = "msm-dai-q6-dev.16395", - .platform_name = "msm-pcm-routing", - .codec_name = "tavil_codec", - .codec_dai_name = "tavil_mad1", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_5_TX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ops = &msm_ext_slimbus_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_SLIMBUS_6_RX, - .stream_name = "Slimbus6 Playback", - .cpu_dai_name = "msm-dai-q6-dev.16396", - .platform_name = "msm-pcm-routing", - .codec_name = "tavil_codec", - .codec_dai_name = "tavil_rx4", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_6_RX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ops = &msm_ext_slimbus_be_ops, - /* dai link has playback support */ - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - }, -}; - -static struct snd_soc_dai_link msm_ext_common_fe_dai[] = { - /* FrontEnd DAI Links */ - {/* hw:x,0 */ - .name = MSM_DAILINK_NAME(Media1), - .stream_name = "MultiMedia1", - .cpu_dai_name = "MultiMedia1", - .platform_name = "msm-pcm-dsp.0", - .dynamic = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - .dpcm_playback = 1, - .dpcm_capture = 1, - /* this dai link has playback support */ - .ignore_pmdown_time = 1, - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA1 - }, - {/* hw:x,1 */ - .name = MSM_DAILINK_NAME(Media2), - .stream_name = "MultiMedia2", - .cpu_dai_name = "MultiMedia2", - .platform_name = "msm-pcm-dsp.0", - .dynamic = 1, - .dpcm_playback = 1, - .dpcm_capture = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .ignore_suspend = 1, - /* this dai link has playback support */ - .ignore_pmdown_time = 1, - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA2, - }, - {/* hw:x,2 */ - .name = "VoiceMMode1", - .stream_name = "VoiceMMode1", - .cpu_dai_name = "VoiceMMode1", - .platform_name = "msm-pcm-voice", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .be_id = MSM_FRONTEND_DAI_VOICEMMODE1, - }, - {/* hw:x,3 */ - .name = "MSM VoIP", - .stream_name = "VoIP", - .cpu_dai_name = "VoIP", - .platform_name = "msm-voip-dsp", - .dynamic = 1, - .dpcm_playback = 1, - .dpcm_capture = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - /* this dai link has playback support */ - .ignore_pmdown_time = 1, - .be_id = MSM_FRONTEND_DAI_VOIP, - }, - {/* hw:x,4 */ - .name = MSM_DAILINK_NAME(ULL), - .stream_name = "ULL", - .cpu_dai_name = "MultiMedia3", - .platform_name = "msm-pcm-dsp.2", - .dynamic = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - /* this dai link has playback support */ - .ignore_pmdown_time = 1, - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA3, - }, - /* Hostless PCM purpose */ - {/* hw:x,5 */ - .name = "SLIMBUS_0 Hostless", - .stream_name = "SLIMBUS_0 Hostless", - .cpu_dai_name = "SLIMBUS0_HOSTLESS", - .platform_name = "msm-pcm-hostless", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - /* This dai link has MI2S support */ - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - }, - {/* hw:x,6 */ - .name = "MSM AFE-PCM RX", - .stream_name = "AFE-PROXY RX", - .cpu_dai_name = "msm-dai-q6-dev.241", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .platform_name = "msm-pcm-afe", - .ignore_suspend = 1, - /* this dai link has playback support */ - .ignore_pmdown_time = 1, - }, - {/* hw:x,7 */ - .name = "MSM AFE-PCM TX", - .stream_name = "AFE-PROXY TX", - .cpu_dai_name = "msm-dai-q6-dev.240", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .platform_name = "msm-pcm-afe", - .ignore_suspend = 1, - }, - {/* hw:x,8 */ - .name = MSM_DAILINK_NAME(Compress1), - .stream_name = "Compress1", - .cpu_dai_name = "MultiMedia4", - .platform_name = "msm-compress-dsp", - .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS, - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - /* this dai link has playback support */ - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA4, - }, - {/* hw:x,9*/ - .name = "AUXPCM Hostless", - .stream_name = "AUXPCM Hostless", - .cpu_dai_name = "AUXPCM_HOSTLESS", - .platform_name = "msm-pcm-hostless", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - /* this dai link has playback support */ - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - }, - {/* hw:x,10 */ - .name = "SLIMBUS_1 Hostless", - .stream_name = "SLIMBUS_1 Hostless", - .cpu_dai_name = "SLIMBUS1_HOSTLESS", - .platform_name = "msm-pcm-hostless", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, /* dai link has playback support */ - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - }, - {/* hw:x,11 */ - .name = "SLIMBUS_3 Hostless", - .stream_name = "SLIMBUS_3 Hostless", - .cpu_dai_name = "SLIMBUS3_HOSTLESS", - .platform_name = "msm-pcm-hostless", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, /* dai link has playback support */ - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - }, - {/* hw:x,12 */ - .name = "SLIMBUS_4 Hostless", - .stream_name = "SLIMBUS_4 Hostless", - .cpu_dai_name = "SLIMBUS4_HOSTLESS", - .platform_name = "msm-pcm-hostless", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, /* dai link has playback support */ - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - }, - {/* hw:x,13 */ - .name = MSM_DAILINK_NAME(LowLatency), - .stream_name = "MultiMedia5", - .cpu_dai_name = "MultiMedia5", - .platform_name = "msm-pcm-dsp.1", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .ignore_suspend = 1, - /* this dai link has playback support */ - .ignore_pmdown_time = 1, - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA5, - }, - /* LSM FE */ - {/* hw:x,14 */ - .name = "Listen 1 Audio Service", - .stream_name = "Listen 1 Audio Service", - .cpu_dai_name = "LSM1", - .platform_name = "msm-lsm-client", - .dynamic = 1, - .dpcm_capture = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST }, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .be_id = MSM_FRONTEND_DAI_LSM1, - }, - {/* hw:x,15 */ - .name = MSM_DAILINK_NAME(Compress2), - .stream_name = "Compress2", - .cpu_dai_name = "MultiMedia7", - .platform_name = "msm-compress-dsp", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .ignore_suspend = 1, - /* this dai link has playback support */ - .ignore_pmdown_time = 1, - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA7, - }, - {/* hw:x,16 */ - .name = MSM_DAILINK_NAME(Compress3), - .stream_name = "Compress3", - .cpu_dai_name = "MultiMedia10", - .platform_name = "msm-compress-dsp", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - /* this dai link has playback support */ - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA10, - }, - {/* hw:x,17 */ - .name = MSM_DAILINK_NAME(ULL_NOIRQ), - .stream_name = "MM_NOIRQ", - .cpu_dai_name = "MultiMedia8", - .platform_name = "msm-pcm-dsp-noirq", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - /* this dai link has playback support */ - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA8, - }, - {/* hw:x,18 */ - .name = "HDMI_RX_HOSTLESS", - .stream_name = "HDMI_RX_HOSTLESS", - .cpu_dai_name = "HDMI_HOSTLESS", - .platform_name = "msm-pcm-hostless", - .dynamic = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - }, - {/* hw:x,19 */ - .name = "VoiceMMode2", - .stream_name = "VoiceMMode2", - .cpu_dai_name = "VoiceMMode2", - .platform_name = "msm-pcm-voice", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .be_id = MSM_FRONTEND_DAI_VOICEMMODE2, - }, - {/* hw:x,20 */ - .name = "Listen 2 Audio Service", - .stream_name = "Listen 2 Audio Service", - .cpu_dai_name = "LSM2", - .platform_name = "msm-lsm-client", - .dynamic = 1, - .dpcm_capture = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST }, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .be_id = MSM_FRONTEND_DAI_LSM2, - }, - {/* hw:x,21 */ - .name = "Listen 3 Audio Service", - .stream_name = "Listen 3 Audio Service", - .cpu_dai_name = "LSM3", - .platform_name = "msm-lsm-client", - .dynamic = 1, - .dpcm_capture = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST }, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .be_id = MSM_FRONTEND_DAI_LSM3, - }, - {/* hw:x,22 */ - .name = "Listen 4 Audio Service", - .stream_name = "Listen 4 Audio Service", - .cpu_dai_name = "LSM4", - .platform_name = "msm-lsm-client", - .dynamic = 1, - .dpcm_capture = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST }, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .be_id = MSM_FRONTEND_DAI_LSM4, - }, - {/* hw:x,23 */ - .name = "Listen 5 Audio Service", - .stream_name = "Listen 5 Audio Service", - .cpu_dai_name = "LSM5", - .platform_name = "msm-lsm-client", - .dynamic = 1, - .dpcm_capture = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST }, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .be_id = MSM_FRONTEND_DAI_LSM5, - }, - {/* hw:x,24 */ - .name = "Listen 6 Audio Service", - .stream_name = "Listen 6 Audio Service", - .cpu_dai_name = "LSM6", - .platform_name = "msm-lsm-client", - .dynamic = 1, - .dpcm_capture = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST }, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .be_id = MSM_FRONTEND_DAI_LSM6 - }, - {/* hw:x,25 */ - .name = "Listen 7 Audio Service", - .stream_name = "Listen 7 Audio Service", - .cpu_dai_name = "LSM7", - .platform_name = "msm-lsm-client", - .dynamic = 1, - .dpcm_capture = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST }, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .be_id = MSM_FRONTEND_DAI_LSM7, - }, - {/* hw:x,26 */ - .name = "Listen 8 Audio Service", - .stream_name = "Listen 8 Audio Service", - .cpu_dai_name = "LSM8", - .platform_name = "msm-lsm-client", - .dynamic = 1, - .dpcm_capture = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST }, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .be_id = MSM_FRONTEND_DAI_LSM8, - }, - {/* hw:x,27 */ - .name = MSM_DAILINK_NAME(Media9), - .stream_name = "MultiMedia9", - .cpu_dai_name = "MultiMedia9", - .platform_name = "msm-pcm-dsp.0", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - /* this dai link has playback support */ - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA9, - }, - {/* hw:x,28 */ - .name = MSM_DAILINK_NAME(Compress4), - .stream_name = "Compress4", - .cpu_dai_name = "MultiMedia11", - .platform_name = "msm-compress-dsp", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - /* this dai link has playback support */ - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA11, - }, - {/* hw:x,29 */ - .name = MSM_DAILINK_NAME(Compress5), - .stream_name = "Compress5", - .cpu_dai_name = "MultiMedia12", - .platform_name = "msm-compress-dsp", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - /* this dai link has playback support */ - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA12, - }, - {/* hw:x,30 */ - .name = MSM_DAILINK_NAME(Compress6), - .stream_name = "Compress6", - .cpu_dai_name = "MultiMedia13", - .platform_name = "msm-compress-dsp", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - /* this dai link has playback support */ - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA13, - }, - {/* hw:x,31 */ - .name = MSM_DAILINK_NAME(Compress7), - .stream_name = "Compress7", - .cpu_dai_name = "MultiMedia14", - .platform_name = "msm-compress-dsp", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - /* this dai link has playback support */ - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA14, - }, - {/* hw:x,32 */ - .name = MSM_DAILINK_NAME(Compress8), - .stream_name = "Compress8", - .cpu_dai_name = "MultiMedia15", - .platform_name = "msm-compress-dsp", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - /* this dai link has playback support */ - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA15, - }, - {/* hw:x,33 */ - .name = MSM_DAILINK_NAME(Compress9), - .stream_name = "Compress9", - .cpu_dai_name = "MultiMedia16", - .platform_name = "msm-compress-dsp", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - /* this dai link has playback support */ - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA16, - }, - {/* hw:x,34 */ - .name = "SLIMBUS_8 Hostless", - .stream_name = "SLIMBUS8_HOSTLESS Capture", - .cpu_dai_name = "SLIMBUS8_HOSTLESS", - .platform_name = "msm-pcm-hostless", - .dynamic = 1, - .dpcm_capture = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - }, -}; - -static struct snd_soc_dai_link msm_ext_common_be_dai[] = { - { - .name = LPASS_BE_AFE_PCM_RX, - .stream_name = "AFE Playback", - .cpu_dai_name = "msm-dai-q6-dev.224", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_AFE_PCM_RX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - /* this dai link has playback support */ - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_AFE_PCM_TX, - .stream_name = "AFE Capture", - .cpu_dai_name = "msm-dai-q6-dev.225", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_AFE_PCM_TX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ignore_suspend = 1, - }, - /* Incall Record Uplink BACK END DAI Link */ - { - .name = LPASS_BE_INCALL_RECORD_TX, - .stream_name = "Voice Uplink Capture", - .cpu_dai_name = "msm-dai-q6-dev.32772", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_INCALL_RECORD_TX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ignore_suspend = 1, - }, - /* Incall Record Downlink BACK END DAI Link */ - { - .name = LPASS_BE_INCALL_RECORD_RX, - .stream_name = "Voice Downlink Capture", - .cpu_dai_name = "msm-dai-q6-dev.32771", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_INCALL_RECORD_RX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ignore_suspend = 1, - }, - /* Incall Music BACK END DAI Link */ - { - .name = LPASS_BE_VOICE_PLAYBACK_TX, - .stream_name = "Voice Farend Playback", - .cpu_dai_name = "msm-dai-q6-dev.32773", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ignore_suspend = 1, - }, - /* Incall Music 2 BACK END DAI Link */ - { - .name = LPASS_BE_VOICE2_PLAYBACK_TX, - .stream_name = "Voice2 Farend Playback", - .cpu_dai_name = "msm-dai-q6-dev.32770", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_USB_AUDIO_RX, - .stream_name = "USB Audio Playback", - .cpu_dai_name = "msm-dai-q6-dev.28672", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_USB_RX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_USB_AUDIO_TX, - .stream_name = "USB Audio Capture", - .cpu_dai_name = "msm-dai-q6-dev.28673", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_USB_TX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_PRI_TDM_RX_0, - .stream_name = "Primary TDM0 Playback", - .cpu_dai_name = "msm-dai-q6-tdm.36864", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_PRI_TDM_RX_0, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_tdm_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_PRI_TDM_TX_0, - .stream_name = "Primary TDM0 Capture", - .cpu_dai_name = "msm-dai-q6-tdm.36865", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_PRI_TDM_TX_0, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_tdm_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_SEC_TDM_RX_0, - .stream_name = "Secondary TDM0 Playback", - .cpu_dai_name = "msm-dai-q6-tdm.36880", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_SEC_TDM_RX_0, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_tdm_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_SEC_TDM_TX_0, - .stream_name = "Secondary TDM0 Capture", - .cpu_dai_name = "msm-dai-q6-tdm.36881", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_SEC_TDM_TX_0, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_tdm_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_TERT_TDM_RX_0, - .stream_name = "Tertiary TDM0 Playback", - .cpu_dai_name = "msm-dai-q6-tdm.36896", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_TERT_TDM_RX_0, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_tdm_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_TERT_TDM_TX_0, - .stream_name = "Tertiary TDM0 Capture", - .cpu_dai_name = "msm-dai-q6-tdm.36897", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_TERT_TDM_TX_0, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_tdm_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_QUAT_TDM_RX_0, - .stream_name = "Quaternary TDM0 Playback", - .cpu_dai_name = "msm-dai-q6-tdm.36912", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_QUAT_TDM_RX_0, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_tdm_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_QUAT_TDM_TX_0, - .stream_name = "Quaternary TDM0 Capture", - .cpu_dai_name = "msm-dai-q6-tdm.36913", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_QUAT_TDM_TX_0, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_tdm_be_ops, - .ignore_suspend = 1, - }, -}; - -static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = { - { - .name = LPASS_BE_PRI_MI2S_RX, - .stream_name = "Primary MI2S Playback", - .cpu_dai_name = "msm-dai-q6-mi2s.0", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_PRI_MI2S_RX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_mi2s_be_ops, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - }, - { - .name = LPASS_BE_PRI_MI2S_TX, - .stream_name = "Primary MI2S Capture", - .cpu_dai_name = "msm-dai-q6-mi2s.0", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_PRI_MI2S_TX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_mi2s_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_SEC_MI2S_RX, - .stream_name = "Secondary MI2S Playback", - .cpu_dai_name = "msm-dai-q6-mi2s.1", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_mi2s_be_ops, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - }, - { - .name = LPASS_BE_SEC_MI2S_TX, - .stream_name = "Secondary MI2S Capture", - .cpu_dai_name = "msm-dai-q6-mi2s.1", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_mi2s_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_TERT_MI2S_RX, - .stream_name = "Tertiary MI2S Playback", - .cpu_dai_name = "msm-dai-q6-mi2s.2", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_mi2s_be_ops, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - }, - { - .name = LPASS_BE_TERT_MI2S_TX, - .stream_name = "Tertiary MI2S Capture", - .cpu_dai_name = "msm-dai-q6-mi2s.2", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_mi2s_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_QUAT_MI2S_RX, - .stream_name = "Quaternary MI2S Playback", - .cpu_dai_name = "msm-dai-q6-mi2s.3", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_mi2s_be_ops, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - }, - { - .name = LPASS_BE_QUAT_MI2S_TX, - .stream_name = "Quaternary MI2S Capture", - .cpu_dai_name = "msm-dai-q6-mi2s.3", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_mi2s_be_ops, - .ignore_suspend = 1, - }, -}; - -static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = { - /* Primary AUX PCM Backend DAI Links */ - { - .name = LPASS_BE_AUXPCM_RX, - .stream_name = "AUX PCM Playback", - .cpu_dai_name = "msm-dai-q6-auxpcm.1", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_AUXPCM_RX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - .ops = &msm_aux_pcm_be_ops, - }, - { - .name = LPASS_BE_AUXPCM_TX, - .stream_name = "AUX PCM Capture", - .cpu_dai_name = "msm-dai-q6-auxpcm.1", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_AUXPCM_TX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - .ops = &msm_aux_pcm_be_ops, - }, - /* Secondary AUX PCM Backend DAI Links */ - { - .name = LPASS_BE_SEC_AUXPCM_RX, - .stream_name = "Sec AUX PCM Playback", - .cpu_dai_name = "msm-dai-q6-auxpcm.2", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_SEC_AUXPCM_RX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - .ops = &msm_aux_pcm_be_ops, - }, - { - .name = LPASS_BE_SEC_AUXPCM_TX, - .stream_name = "Sec AUX PCM Capture", - .cpu_dai_name = "msm-dai-q6-auxpcm.2", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_SEC_AUXPCM_TX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .ops = &msm_aux_pcm_be_ops, - }, - /* Tertiary AUX PCM Backend DAI Links */ - { - .name = LPASS_BE_TERT_AUXPCM_RX, - .stream_name = "Tert AUX PCM Playback", - .cpu_dai_name = "msm-dai-q6-auxpcm.3", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_TERT_AUXPCM_RX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - .ops = &msm_aux_pcm_be_ops, - }, - { - .name = LPASS_BE_TERT_AUXPCM_TX, - .stream_name = "Tert AUX PCM Capture", - .cpu_dai_name = "msm-dai-q6-auxpcm.3", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_TERT_AUXPCM_TX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .ops = &msm_aux_pcm_be_ops, - }, - /* Quaternary AUX PCM Backend DAI Links */ - { - .name = LPASS_BE_QUAT_AUXPCM_RX, - .stream_name = "Quat AUX PCM Playback", - .cpu_dai_name = "msm-dai-q6-auxpcm.4", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - .ops = &msm_aux_pcm_be_ops, - }, - { - .name = LPASS_BE_QUAT_AUXPCM_TX, - .stream_name = "Quat AUX PCM Capture", - .cpu_dai_name = "msm-dai-q6-auxpcm.4", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .ops = &msm_aux_pcm_be_ops, - }, -}; - -static struct snd_soc_dai_link msm_wcn_be_dai_links[] = { - { - .name = LPASS_BE_SLIMBUS_7_RX, - .stream_name = "Slimbus7 Playback", - .cpu_dai_name = "msm-dai-q6-dev.16398", - .platform_name = "msm-pcm-routing", - .codec_name = "btfmslim_slave", - /* BT codec driver determines capabilities based on - * dai name, bt codecdai name should always contains - * supported usecase information - */ - .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_7_RX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ops = &msm_wcn_ops, - /* dai link has playback support */ - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_SLIMBUS_7_TX, - .stream_name = "Slimbus7 Capture", - .cpu_dai_name = "msm-dai-q6-dev.16399", - .platform_name = "msm-pcm-routing", - .codec_name = "btfmslim_slave", - .codec_dai_name = "btfm_bt_sco_slim_tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_7_TX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .ops = &msm_wcn_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_SLIMBUS_8_TX, - .stream_name = "Slimbus8 Capture", - .cpu_dai_name = "msm-dai-q6-dev.16401", - .platform_name = "msm-pcm-routing", - .codec_name = "btfmslim_slave", - .codec_dai_name = "btfm_fm_slim_tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_8_TX, - .be_hw_params_fixup = msm_ext_be_hw_params_fixup, - .init = &msm_wcn_init, - .ops = &msm_wcn_ops, - .ignore_suspend = 1, - }, -}; - -static struct snd_soc_dai_link msm_ext_tasha_dai_links[ -ARRAY_SIZE(msm_ext_common_fe_dai) + -ARRAY_SIZE(msm_ext_tasha_fe_dai) + -ARRAY_SIZE(msm_ext_common_be_dai) + -ARRAY_SIZE(msm_ext_tasha_be_dai) + -ARRAY_SIZE(msm_mi2s_be_dai_links) + -ARRAY_SIZE(msm_auxpcm_be_dai_links) + -ARRAY_SIZE(msm_wcn_be_dai_links)]; - -static struct snd_soc_dai_link msm_ext_tavil_dai_links[ -ARRAY_SIZE(msm_ext_common_fe_dai) + -ARRAY_SIZE(msm_ext_tavil_fe_dai) + -ARRAY_SIZE(msm_ext_common_be_dai) + -ARRAY_SIZE(msm_ext_tavil_be_dai) + -ARRAY_SIZE(msm_mi2s_be_dai_links) + -ARRAY_SIZE(msm_auxpcm_be_dai_links) + -ARRAY_SIZE(msm_wcn_be_dai_links)]; - -/** - * populate_snd_card_dailinks - prepares dailink array and initializes card. - * - * @dev: device handle - * - * Returns card on success or NULL on failure. - */ -struct snd_soc_card *populate_snd_card_dailinks(struct device *dev, - int snd_card_val) -{ - struct snd_soc_card *card; - struct snd_soc_dai_link *msm_ext_dai_links = NULL; - int ret, len1, len2, len3, len4; - enum codec_variant codec_ver = 0; - - if (snd_card_val == EXT_SND_CARD_TASHA) { - card = &snd_soc_card_msm_card_tasha; - } else if (snd_card_val == EXT_SND_CARD_TAVIL) { - card = &snd_soc_card_msm_card_tavil; - } else { - dev_err(dev, "%s: failing as no matching card name\n", - __func__); - return NULL; - } - - card->dev = dev; - ret = snd_soc_of_parse_card_name(card, "qcom,model"); - if (ret) { - dev_err(dev, "%s: parse card name failed, err:%d\n", - __func__, ret); - return NULL; - } - - if (strnstr(card->name, "tasha", strlen(card->name))) { - codec_ver = tasha_codec_ver(); - if (codec_ver == WCD9326) - card->name = "msmfalcon-tashalite-snd-card"; - - len1 = ARRAY_SIZE(msm_ext_common_fe_dai); - len2 = len1 + ARRAY_SIZE(msm_ext_tasha_fe_dai); - len3 = len2 + ARRAY_SIZE(msm_ext_common_be_dai); - memcpy(msm_ext_tasha_dai_links, msm_ext_common_fe_dai, - sizeof(msm_ext_common_fe_dai)); - memcpy(msm_ext_tasha_dai_links + len1, - msm_ext_tasha_fe_dai, sizeof(msm_ext_tasha_fe_dai)); - memcpy(msm_ext_tasha_dai_links + len2, - msm_ext_common_be_dai, sizeof(msm_ext_common_be_dai)); - memcpy(msm_ext_tasha_dai_links + len3, - msm_ext_tasha_be_dai, sizeof(msm_ext_tasha_be_dai)); - len4 = len3 + ARRAY_SIZE(msm_ext_tasha_be_dai); - if (of_property_read_bool(dev->of_node, - "qcom,mi2s-audio-intf")) { - memcpy(msm_ext_tasha_dai_links + len4, - msm_mi2s_be_dai_links, - sizeof(msm_mi2s_be_dai_links)); - len4 += ARRAY_SIZE(msm_mi2s_be_dai_links); - } - if (of_property_read_bool(dev->of_node, - "qcom,auxpcm-audio-intf")) { - memcpy(msm_ext_tasha_dai_links + len4, - msm_auxpcm_be_dai_links, - sizeof(msm_auxpcm_be_dai_links)); - len4 += ARRAY_SIZE(msm_auxpcm_be_dai_links); - } - if (of_property_read_bool(dev->of_node, "qcom,wcn-btfm")) { - dev_dbg(dev, "%s(): WCN BTFM support present\n", - __func__); - memcpy(msm_ext_tasha_dai_links + len4, - msm_wcn_be_dai_links, - sizeof(msm_wcn_be_dai_links)); - len4 += ARRAY_SIZE(msm_wcn_be_dai_links); - } - msm_ext_dai_links = msm_ext_tasha_dai_links; - } else if (strnstr(card->name, "tavil", strlen(card->name))) { - len1 = ARRAY_SIZE(msm_ext_common_fe_dai); - len2 = len1 + ARRAY_SIZE(msm_ext_tavil_fe_dai); - len3 = len2 + ARRAY_SIZE(msm_ext_common_be_dai); - memcpy(msm_ext_tavil_dai_links, msm_ext_common_fe_dai, - sizeof(msm_ext_common_fe_dai)); - memcpy(msm_ext_tavil_dai_links + len1, - msm_ext_tavil_fe_dai, sizeof(msm_ext_tavil_fe_dai)); - memcpy(msm_ext_tavil_dai_links + len2, - msm_ext_common_be_dai, sizeof(msm_ext_common_be_dai)); - memcpy(msm_ext_tavil_dai_links + len3, - msm_ext_tavil_be_dai, sizeof(msm_ext_tavil_be_dai)); - len4 = len3 + ARRAY_SIZE(msm_ext_tavil_be_dai); - if (of_property_read_bool(dev->of_node, - "qcom,mi2s-audio-intf")) { - memcpy(msm_ext_tavil_dai_links + len4, - msm_mi2s_be_dai_links, - sizeof(msm_mi2s_be_dai_links)); - len4 += ARRAY_SIZE(msm_mi2s_be_dai_links); - } - if (of_property_read_bool(dev->of_node, - "qcom,auxpcm-audio-intf")) { - memcpy(msm_ext_tavil_dai_links + len4, - msm_auxpcm_be_dai_links, - sizeof(msm_auxpcm_be_dai_links)); - len4 += ARRAY_SIZE(msm_auxpcm_be_dai_links); - } - if (of_property_read_bool(dev->of_node, "qcom,wcn-btfm")) { - dev_dbg(dev, "%s(): WCN BTFM support present\n", - __func__); - memcpy(msm_ext_tavil_dai_links + len4, - msm_wcn_be_dai_links, - sizeof(msm_wcn_be_dai_links)); - len4 += ARRAY_SIZE(msm_wcn_be_dai_links); - } - msm_ext_dai_links = msm_ext_tavil_dai_links; - } else { - dev_err(dev, "%s: failing as no matching card name\n", - __func__); - return NULL; - } - card->dai_link = msm_ext_dai_links; - card->num_links = len4; - - return card; -} -EXPORT_SYMBOL(populate_snd_card_dailinks); diff --git a/sound/soc/msm/msmfalcon-external.c b/sound/soc/msm/msmfalcon-external.c deleted file mode 100644 index ef0b23e2e51e..000000000000 --- a/sound/soc/msm/msmfalcon-external.c +++ /dev/null @@ -1,1841 +0,0 @@ -/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "qdsp6v2/msm-pcm-routing-v2.h" -#include "msm-audio-pinctrl.h" -#include "msmfalcon-common.h" -#include "msmfalcon-external.h" -#include "../codecs/wcd9335.h" -#include "../codecs/wcd934x/wcd934x.h" -#include "../codecs/wcd934x/wcd934x-mbhc.h" - -#define MSMFALCON_SPK_ON 1 -#define MSMFALCON_SPK_OFF 0 - -#define WCD9XXX_MBHC_DEF_BUTTONS 8 -#define WCD9XXX_MBHC_DEF_RLOADS 5 -#define CODEC_EXT_CLK_RATE 9600000 -#define ADSP_STATE_READY_TIMEOUT_MS 3000 - -#define TLMM_CENTER_MPM_WAKEUP_INT_EN_0 0x03596000 -#define LPI_GPIO_22_WAKEUP_VAL 0x00000002 - -#define TLMM_LPI_DIR_CONN_INTR1_CFG_APPS 0x0359D004 -#define LPI_GPIO_22_INTR1_CFG_VAL 0x01 -#define LPI_GPIO_22_INTR1_CFG_MASK 0x03 - -#define TLMM_LPI_GPIO_INTR_CFG1 0x0359B004 -#define LPI_GPIO_INTR_CFG1_VAL 0x00000113 - -#define TLMM_LPI_GPIO22_CFG 0x15078040 -#define LPI_GPIO22_CFG_VAL 0x0000009 - -#define TLMM_LPI_GPIO22_INOUT 0x15078044 -#define LPI_GPIO22_INOUT_VAL 0x00000000 - -#define WSA8810_NAME_1 "wsa881x.20170211" -#define WSA8810_NAME_2 "wsa881x.20170212" - -static int msm_ext_spk_control = 1; -static struct wcd_mbhc_config *wcd_mbhc_cfg_ptr; - -struct msm_asoc_wcd93xx_codec { - void* (*get_afe_config_fn)(struct snd_soc_codec *codec, - enum afe_config_type config_type); - void (*mbhc_hs_detect_exit)(struct snd_soc_codec *codec); -}; - -static struct msm_asoc_wcd93xx_codec msm_codec_fn; -static struct platform_device *spdev; - -struct msm_snd_interrupt { - void __iomem *mpm_wakeup; - void __iomem *intr1_cfg_apps; - void __iomem *lpi_gpio_intr_cfg; - void __iomem *lpi_gpio_cfg; - void __iomem *lpi_gpio_inout; -}; - -static struct msm_snd_interrupt msm_snd_intr_lpi; - -static bool is_initial_boot; - -static void *def_ext_mbhc_cal(void); - -enum { - SLIM_RX_0 = 0, - SLIM_RX_1, - SLIM_RX_2, - SLIM_RX_3, - SLIM_RX_4, - SLIM_RX_5, - SLIM_RX_6, - SLIM_RX_7, - SLIM_RX_MAX, -}; - -enum { - SLIM_TX_0 = 0, - SLIM_TX_1, - SLIM_TX_2, - SLIM_TX_3, - SLIM_TX_4, - SLIM_TX_5, - SLIM_TX_6, - SLIM_TX_7, - SLIM_TX_8, - SLIM_TX_MAX, -}; - -struct dev_config { - u32 sample_rate; - u32 bit_format; - u32 channels; -}; - -/* Default configuration of slimbus channels */ -static struct dev_config slim_rx_cfg[] = { - [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, -}; - -static struct dev_config slim_tx_cfg[] = { - [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, -}; - -static int msm_vi_feed_tx_ch = 2; -static const char *const slim_rx_ch_text[] = {"One", "Two"}; -static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four", - "Five", "Six", "Seven", - "Eight"}; -static const char *const vi_feed_ch_text[] = {"One", "Two"}; -static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE", - "S32_LE"}; -static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16", - "KHZ_32", "KHZ_44P1", "KHZ_48", - "KHZ_88P2", "KHZ_96", "KHZ_176P4", - "KHZ_192", "KHZ_352P8", "KHZ_384"}; -static const char *const spk_function_text[] = {"Off", "On"}; -static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_48"}; - -static SOC_ENUM_SINGLE_EXT_DECL(spk_func_en, spk_function_text); -static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text); -static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text); -static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text); -static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text); -static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text); -static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text); -static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text); -static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text); -static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text); -static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text); -static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text); -static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text); - -static int slim_get_sample_rate_val(int sample_rate) -{ - int sample_rate_val = 0; - - switch (sample_rate) { - case SAMPLING_RATE_8KHZ: - sample_rate_val = 0; - break; - case SAMPLING_RATE_16KHZ: - sample_rate_val = 1; - break; - case SAMPLING_RATE_32KHZ: - sample_rate_val = 2; - break; - case SAMPLING_RATE_44P1KHZ: - sample_rate_val = 3; - break; - case SAMPLING_RATE_48KHZ: - sample_rate_val = 4; - break; - case SAMPLING_RATE_88P2KHZ: - sample_rate_val = 5; - break; - case SAMPLING_RATE_96KHZ: - sample_rate_val = 6; - break; - case SAMPLING_RATE_176P4KHZ: - sample_rate_val = 7; - break; - case SAMPLING_RATE_192KHZ: - sample_rate_val = 8; - break; - case SAMPLING_RATE_352P8KHZ: - sample_rate_val = 9; - break; - case SAMPLING_RATE_384KHZ: - sample_rate_val = 10; - break; - default: - sample_rate_val = 4; - break; - } - return sample_rate_val; -} - -static int slim_get_sample_rate(int value) -{ - int sample_rate = 0; - - switch (value) { - case 0: - sample_rate = SAMPLING_RATE_8KHZ; - break; - case 1: - sample_rate = SAMPLING_RATE_16KHZ; - break; - case 2: - sample_rate = SAMPLING_RATE_32KHZ; - break; - case 3: - sample_rate = SAMPLING_RATE_44P1KHZ; - break; - case 4: - sample_rate = SAMPLING_RATE_48KHZ; - break; - case 5: - sample_rate = SAMPLING_RATE_88P2KHZ; - break; - case 6: - sample_rate = SAMPLING_RATE_96KHZ; - break; - case 7: - sample_rate = SAMPLING_RATE_176P4KHZ; - break; - case 8: - sample_rate = SAMPLING_RATE_192KHZ; - break; - case 9: - sample_rate = SAMPLING_RATE_352P8KHZ; - break; - case 10: - sample_rate = SAMPLING_RATE_384KHZ; - break; - default: - sample_rate = SAMPLING_RATE_48KHZ; - break; - } - return sample_rate; -} - -static int slim_get_bit_format_val(int bit_format) -{ - int val = 0; - - switch (bit_format) { - case SNDRV_PCM_FORMAT_S32_LE: - val = 3; - break; - case SNDRV_PCM_FORMAT_S24_3LE: - val = 2; - break; - case SNDRV_PCM_FORMAT_S24_LE: - val = 1; - break; - case SNDRV_PCM_FORMAT_S16_LE: - default: - val = 0; - break; - } - return val; -} - -static int slim_get_bit_format(int val) -{ - int bit_fmt = SNDRV_PCM_FORMAT_S16_LE; - - switch (val) { - case 0: - bit_fmt = SNDRV_PCM_FORMAT_S16_LE; - break; - case 1: - bit_fmt = SNDRV_PCM_FORMAT_S24_LE; - break; - case 2: - bit_fmt = SNDRV_PCM_FORMAT_S24_3LE; - break; - case 3: - bit_fmt = SNDRV_PCM_FORMAT_S32_LE; - break; - default: - bit_fmt = SNDRV_PCM_FORMAT_S16_LE; - break; - } - return bit_fmt; -} - -static int slim_get_port_idx(struct snd_kcontrol *kcontrol) -{ - int port_id = 0; - - if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) - port_id = SLIM_RX_0; - else if (strnstr(kcontrol->id.name, "SLIM_2_RX", sizeof("SLIM_2_RX"))) - port_id = SLIM_RX_2; - else if (strnstr(kcontrol->id.name, "SLIM_5_RX", sizeof("SLIM_5_RX"))) - port_id = SLIM_RX_5; - else if (strnstr(kcontrol->id.name, "SLIM_6_RX", sizeof("SLIM_6_RX"))) - port_id = SLIM_RX_6; - else if (strnstr(kcontrol->id.name, "SLIM_0_TX", sizeof("SLIM_0_TX"))) - port_id = SLIM_TX_0; - else if (strnstr(kcontrol->id.name, "SLIM_1_TX", sizeof("SLIM_1_TX"))) - port_id = SLIM_TX_1; - else { - pr_err("%s: unsupported channel: %s", - __func__, kcontrol->id.name); - return -EINVAL; - } - - return port_id; -} - -static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - /* - * Slimbus_7_Rx/Tx sample rate values should always be in sync (same) - * when used for BT_SCO use case. Return either Rx or Tx sample rate - * value. - */ - switch (slim_rx_cfg[SLIM_RX_7].sample_rate) { - case SAMPLING_RATE_48KHZ: - ucontrol->value.integer.value[0] = 2; - break; - case SAMPLING_RATE_16KHZ: - ucontrol->value.integer.value[0] = 1; - break; - case SAMPLING_RATE_8KHZ: - default: - ucontrol->value.integer.value[0] = 0; - break; - } - pr_debug("%s: sample rate = %d", __func__, - slim_rx_cfg[SLIM_RX_7].sample_rate); - - return 0; -} - -static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - switch (ucontrol->value.integer.value[0]) { - case 1: - slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ; - slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ; - break; - case 2: - slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ; - slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ; - break; - case 0: - default: - slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ; - slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ; - break; - } - pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n", - __func__, - slim_rx_cfg[SLIM_RX_7].sample_rate, - slim_tx_cfg[SLIM_TX_7].sample_rate, - ucontrol->value.enumerated.item[0]); - - return 0; -} - -static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ch_num = slim_get_port_idx(kcontrol); - - if (ch_num < 0) - return ch_num; - - ucontrol->value.enumerated.item[0] = - slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate); - - pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__, - ch_num, slim_rx_cfg[ch_num].sample_rate, - ucontrol->value.enumerated.item[0]); - - return 0; -} - -static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ch_num = slim_get_port_idx(kcontrol); - - if (ch_num < 0) - return ch_num; - - slim_rx_cfg[ch_num].sample_rate = - slim_get_sample_rate(ucontrol->value.enumerated.item[0]); - - pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__, - ch_num, slim_rx_cfg[ch_num].sample_rate, - ucontrol->value.enumerated.item[0]); - - return 0; -} - -static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ch_num = slim_get_port_idx(kcontrol); - - if (ch_num < 0) - return ch_num; - - ucontrol->value.enumerated.item[0] = - slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate); - - pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__, - ch_num, slim_tx_cfg[ch_num].sample_rate, - ucontrol->value.enumerated.item[0]); - - return 0; -} - -static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int sample_rate = 0; - int ch_num = slim_get_port_idx(kcontrol); - - if (ch_num < 0) - return ch_num; - - sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]); - if (sample_rate == SAMPLING_RATE_44P1KHZ) { - pr_err("%s: Unsupported sample rate %d: for Tx path\n", - __func__, sample_rate); - return -EINVAL; - } - slim_tx_cfg[ch_num].sample_rate = sample_rate; - - pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__, - ch_num, slim_tx_cfg[ch_num].sample_rate, - ucontrol->value.enumerated.item[0]); - - return 0; -} - -static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ch_num = slim_get_port_idx(kcontrol); - - if (ch_num < 0) - return ch_num; - - ucontrol->value.enumerated.item[0] = - slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format); - - pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n", - __func__, ch_num, slim_rx_cfg[ch_num].bit_format, - ucontrol->value.enumerated.item[0]); - - return 0; -} - -static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ch_num = slim_get_port_idx(kcontrol); - - if (ch_num < 0) - return ch_num; - - slim_rx_cfg[ch_num].bit_format = - slim_get_bit_format(ucontrol->value.enumerated.item[0]); - - pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n", - __func__, ch_num, slim_rx_cfg[ch_num].bit_format, - ucontrol->value.enumerated.item[0]); - - return 0; -} - -static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ch_num = slim_get_port_idx(kcontrol); - - if (ch_num < 0) - return ch_num; - - ucontrol->value.enumerated.item[0] = - slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format); - - pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n", - __func__, ch_num, slim_tx_cfg[ch_num].bit_format, - ucontrol->value.enumerated.item[0]); - - return 0; -} - -static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ch_num = slim_get_port_idx(kcontrol); - - if (ch_num < 0) - return ch_num; - - slim_tx_cfg[ch_num].bit_format = - slim_get_bit_format(ucontrol->value.enumerated.item[0]); - - pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n", - __func__, ch_num, slim_tx_cfg[ch_num].bit_format, - ucontrol->value.enumerated.item[0]); - - return 0; -} - -static int msm_slim_rx_ch_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ch_num = slim_get_port_idx(kcontrol); - - if (ch_num < 0) - return ch_num; - - pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__, - ch_num, slim_rx_cfg[ch_num].channels); - ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1; - - return 0; -} - -static int msm_slim_rx_ch_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ch_num = slim_get_port_idx(kcontrol); - - if (ch_num < 0) - return ch_num; - - slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1; - pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__, - ch_num, slim_rx_cfg[ch_num].channels); - - return 1; -} - -static int msm_slim_tx_ch_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ch_num = slim_get_port_idx(kcontrol); - - if (ch_num < 0) - return ch_num; - - pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__, - ch_num, slim_tx_cfg[ch_num].channels); - ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1; - - return 0; -} - -static int msm_slim_tx_ch_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ch_num = slim_get_port_idx(kcontrol); - - if (ch_num < 0) - return ch_num; - - slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1; - pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__, - ch_num, slim_tx_cfg[ch_num].channels); - - return 1; -} - -static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1; - pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__, - ucontrol->value.integer.value[0]); - return 0; -} - -static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1; - - pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch); - return 1; -} - -static void *def_ext_mbhc_cal(void) -{ - void *tavil_wcd_cal; - struct wcd_mbhc_btn_detect_cfg *btn_cfg; - u16 *btn_high; - - tavil_wcd_cal = kzalloc(WCD_MBHC_CAL_SIZE(WCD_MBHC_DEF_BUTTONS, - WCD9XXX_MBHC_DEF_RLOADS), GFP_KERNEL); - if (!tavil_wcd_cal) - return NULL; - -#define S(X, Y) ((WCD_MBHC_CAL_PLUG_TYPE_PTR(tavil_wcd_cal)->X) = (Y)) - S(v_hs_max, 1600); -#undef S -#define S(X, Y) ((WCD_MBHC_CAL_BTN_DET_PTR(tavil_wcd_cal)->X) = (Y)) - S(num_btn, WCD_MBHC_DEF_BUTTONS); -#undef S - - btn_cfg = WCD_MBHC_CAL_BTN_DET_PTR(tavil_wcd_cal); - btn_high = ((void *)&btn_cfg->_v_btn_low) + - (sizeof(btn_cfg->_v_btn_low[0]) * btn_cfg->num_btn); - - btn_high[0] = 75; - btn_high[1] = 150; - btn_high[2] = 237; - btn_high[3] = 500; - btn_high[4] = 500; - btn_high[5] = 500; - btn_high[6] = 500; - btn_high[7] = 500; - - return tavil_wcd_cal; -} - -static inline int param_is_mask(int p) -{ - return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) && - (p <= SNDRV_PCM_HW_PARAM_LAST_MASK); -} - -static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p, int n) -{ - return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]); -} - - -static void msm_ext_control(struct snd_soc_codec *codec) -{ - struct snd_soc_dapm_context *dapm = - snd_soc_codec_get_dapm(codec); - - pr_debug("%s: msm_ext_spk_control = %d", __func__, msm_ext_spk_control); - if (msm_ext_spk_control == MSMFALCON_SPK_ON) { - snd_soc_dapm_enable_pin(dapm, "Lineout_1 amp"); - snd_soc_dapm_enable_pin(dapm, "Lineout_3 amp"); - } else { - snd_soc_dapm_disable_pin(dapm, "Lineout_1 amp"); - snd_soc_dapm_disable_pin(dapm, "Lineout_3 amp"); - } - snd_soc_dapm_sync(dapm); -} - -static int msm_ext_get_spk(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - pr_debug("%s: msm_ext_spk_control = %d\n", - __func__, msm_ext_spk_control); - ucontrol->value.integer.value[0] = msm_ext_spk_control; - return 0; -} - -static int msm_ext_set_spk(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); - - pr_debug("%s()\n", __func__); - if (msm_ext_spk_control == ucontrol->value.integer.value[0]) - return 0; - - msm_ext_spk_control = ucontrol->value.integer.value[0]; - msm_ext_control(codec); - return 1; -} - - -int msm_ext_enable_codec_mclk(struct snd_soc_codec *codec, int enable, - bool dapm) -{ - int ret; - - pr_debug("%s: enable = %d\n", __func__, enable); - - if (!strcmp(dev_name(codec->dev), "tasha_codec")) - ret = tasha_cdc_mclk_enable(codec, enable, dapm); - else if (!strcmp(dev_name(codec->dev), "tavil_codec")) - ret = tavil_cdc_mclk_enable(codec, enable); - else { - dev_err(codec->dev, "%s: unknown codec to enable ext clk\n", - __func__); - ret = -EINVAL; - } - return ret; -} - -static const struct snd_kcontrol_new msm_snd_controls[] = { - SOC_ENUM_EXT("Speaker Function", spk_func_en, msm_ext_get_spk, - msm_ext_set_spk), - SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs, - msm_slim_rx_ch_get, msm_slim_rx_ch_put), - SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs, - msm_slim_rx_ch_get, msm_slim_rx_ch_put), - SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs, - msm_slim_tx_ch_get, msm_slim_tx_ch_put), - SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs, - msm_slim_tx_ch_get, msm_slim_tx_ch_put), - SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs, - msm_slim_rx_ch_get, msm_slim_rx_ch_put), - SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs, - msm_slim_rx_ch_get, msm_slim_rx_ch_put), - SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs, - msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put), - SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format, - slim_rx_bit_format_get, slim_rx_bit_format_put), - SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format, - slim_rx_bit_format_get, slim_rx_bit_format_put), - SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format, - slim_rx_bit_format_get, slim_rx_bit_format_put), - SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format, - slim_tx_bit_format_get, slim_tx_bit_format_put), - SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate, - slim_rx_sample_rate_get, slim_rx_sample_rate_put), - SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate, - slim_rx_sample_rate_get, slim_rx_sample_rate_put), - SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate, - slim_tx_sample_rate_get, slim_tx_sample_rate_put), - SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate, - slim_rx_sample_rate_get, slim_rx_sample_rate_put), - SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate, - slim_rx_sample_rate_get, slim_rx_sample_rate_put), - SOC_ENUM_EXT("BT SampleRate", bt_sample_rate, - msm_bt_sample_rate_get, - msm_bt_sample_rate_put), -}; - -static int msm_slim_get_ch_from_beid(int32_t be_id) -{ - int ch_id = 0; - - switch (be_id) { - case MSM_BACKEND_DAI_SLIMBUS_0_RX: - ch_id = SLIM_RX_0; - break; - case MSM_BACKEND_DAI_SLIMBUS_1_RX: - ch_id = SLIM_RX_1; - break; - case MSM_BACKEND_DAI_SLIMBUS_2_RX: - ch_id = SLIM_RX_2; - break; - case MSM_BACKEND_DAI_SLIMBUS_3_RX: - ch_id = SLIM_RX_3; - break; - case MSM_BACKEND_DAI_SLIMBUS_4_RX: - ch_id = SLIM_RX_4; - break; - case MSM_BACKEND_DAI_SLIMBUS_6_RX: - ch_id = SLIM_RX_6; - break; - case MSM_BACKEND_DAI_SLIMBUS_0_TX: - ch_id = SLIM_TX_0; - break; - case MSM_BACKEND_DAI_SLIMBUS_3_TX: - ch_id = SLIM_TX_3; - break; - default: - ch_id = SLIM_RX_0; - break; - } - - return ch_id; -} - -static void param_set_mask(struct snd_pcm_hw_params *p, int n, unsigned bit) -{ - if (bit >= SNDRV_MASK_MAX) - return; - if (param_is_mask(n)) { - struct snd_mask *m = param_to_mask(p, n); - - m->bits[0] = 0; - m->bits[1] = 0; - m->bits[bit >> 5] |= (1 << (bit & 31)); - } -} - -/** - * msm_ext_be_hw_params_fixup - updates settings of ALSA BE hw params. - * - * @rtd: runtime dailink instance - * @params: HW params of associated backend dailink. - * - * Returns 0 on success or rc on failure. - */ -int msm_ext_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, - struct snd_pcm_hw_params *params) -{ - struct snd_soc_dai_link *dai_link = rtd->dai_link; - struct snd_interval *rate = hw_param_interval(params, - SNDRV_PCM_HW_PARAM_RATE); - struct snd_interval *channels = hw_param_interval(params, - SNDRV_PCM_HW_PARAM_CHANNELS); - int rc = 0; - int idx; - void *config = NULL; - struct snd_soc_codec *codec = rtd->codec; - - pr_debug("%s: format = %d, rate = %d\n", - __func__, params_format(params), params_rate(params)); - - switch (dai_link->be_id) { - case MSM_BACKEND_DAI_SLIMBUS_0_RX: - case MSM_BACKEND_DAI_SLIMBUS_1_RX: - case MSM_BACKEND_DAI_SLIMBUS_2_RX: - case MSM_BACKEND_DAI_SLIMBUS_3_RX: - case MSM_BACKEND_DAI_SLIMBUS_4_RX: - case MSM_BACKEND_DAI_SLIMBUS_6_RX: - idx = msm_slim_get_ch_from_beid(dai_link->be_id); - param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, - slim_rx_cfg[idx].bit_format); - rate->min = rate->max = slim_rx_cfg[idx].sample_rate; - channels->min = channels->max = slim_rx_cfg[idx].channels; - break; - - case MSM_BACKEND_DAI_SLIMBUS_0_TX: - case MSM_BACKEND_DAI_SLIMBUS_3_TX: - idx = msm_slim_get_ch_from_beid(dai_link->be_id); - param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, - slim_tx_cfg[idx].bit_format); - rate->min = rate->max = slim_tx_cfg[idx].sample_rate; - channels->min = channels->max = slim_tx_cfg[idx].channels; - break; - - case MSM_BACKEND_DAI_SLIMBUS_1_TX: - param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, - slim_tx_cfg[1].bit_format); - rate->min = rate->max = slim_tx_cfg[1].sample_rate; - channels->min = channels->max = slim_tx_cfg[1].channels; - break; - - case MSM_BACKEND_DAI_SLIMBUS_4_TX: - param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, - SNDRV_PCM_FORMAT_S32_LE); - rate->min = rate->max = SAMPLING_RATE_8KHZ; - channels->min = channels->max = msm_vi_feed_tx_ch; - break; - - case MSM_BACKEND_DAI_SLIMBUS_5_RX: - param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, - slim_rx_cfg[5].bit_format); - rate->min = rate->max = slim_rx_cfg[5].sample_rate; - channels->min = channels->max = slim_rx_cfg[5].channels; - break; - - case MSM_BACKEND_DAI_SLIMBUS_5_TX: - rate->min = rate->max = SAMPLING_RATE_16KHZ; - channels->min = channels->max = 1; - - config = msm_codec_fn.get_afe_config_fn(codec, - AFE_SLIMBUS_SLAVE_PORT_CONFIG); - if (config) { - rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG, - config, SLIMBUS_5_TX); - if (rc) - pr_err("%s: Failed to set slimbus slave port config %d\n", - __func__, rc); - } - break; - - case MSM_BACKEND_DAI_SLIMBUS_7_RX: - param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, - slim_rx_cfg[SLIM_RX_7].bit_format); - rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate; - channels->min = channels->max = - slim_rx_cfg[SLIM_RX_7].channels; - break; - - case MSM_BACKEND_DAI_SLIMBUS_7_TX: - rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate; - channels->min = channels->max = - slim_tx_cfg[SLIM_TX_7].channels; - break; - - case MSM_BACKEND_DAI_SLIMBUS_8_TX: - rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate; - channels->min = channels->max = - slim_tx_cfg[SLIM_TX_8].channels; - break; - - default: - rate->min = rate->max = SAMPLING_RATE_48KHZ; - break; - } - return rc; -} -EXPORT_SYMBOL(msm_ext_be_hw_params_fixup); - -/** - * msm_snd_hw_params - hw params ops of backend dailink. - * - * @substream: PCM stream of associated backend dailink. - * @params: HW params of associated backend dailink. - * - * Returns 0 on success or ret on failure. - */ -int msm_snd_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params) -{ - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct snd_soc_dai *codec_dai = rtd->codec_dai; - struct snd_soc_dai *cpu_dai = rtd->cpu_dai; - struct snd_soc_dai_link *dai_link = rtd->dai_link; - - int ret = 0; - u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS]; - u32 rx_ch_cnt = 0, tx_ch_cnt = 0; - u32 user_set_tx_ch = 0; - u32 rx_ch_count; - - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - ret = snd_soc_dai_get_channel_map(codec_dai, - &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch); - if (ret < 0) { - pr_err("%s: failed to get codec chan map, err:%d\n", - __func__, ret); - goto err_ch_map; - } - if (dai_link->be_id == MSM_BACKEND_DAI_SLIMBUS_5_RX) { - pr_debug("%s: rx_5_ch=%d\n", __func__, - slim_rx_cfg[5].channels); - rx_ch_count = slim_rx_cfg[5].channels; - } else if (dai_link->be_id == MSM_BACKEND_DAI_SLIMBUS_2_RX) { - pr_debug("%s: rx_2_ch=%d\n", __func__, - slim_rx_cfg[2].channels); - rx_ch_count = slim_rx_cfg[2].channels; - } else if (dai_link->be_id == MSM_BACKEND_DAI_SLIMBUS_6_RX) { - pr_debug("%s: rx_6_ch=%d\n", __func__, - slim_rx_cfg[6].channels); - rx_ch_count = slim_rx_cfg[6].channels; - } else { - pr_debug("%s: rx_0_ch=%d\n", __func__, - slim_rx_cfg[0].channels); - rx_ch_count = slim_rx_cfg[0].channels; - } - ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0, - rx_ch_count, rx_ch); - if (ret < 0) { - pr_err("%s: failed to set cpu chan map, err:%d\n", - __func__, ret); - goto err_ch_map; - } - } else { - pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__, - codec_dai->name, codec_dai->id, user_set_tx_ch); - ret = snd_soc_dai_get_channel_map(codec_dai, - &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch); - if (ret < 0) { - pr_err("%s: failed to get codec chan map\n, err:%d\n", - __func__, ret); - goto err_ch_map; - } - /* For _tx1 case */ - if (dai_link->be_id == MSM_BACKEND_DAI_SLIMBUS_0_TX) - user_set_tx_ch = slim_tx_cfg[0].channels; - /* For _tx3 case */ - else if (dai_link->be_id == MSM_BACKEND_DAI_SLIMBUS_1_TX) - user_set_tx_ch = slim_tx_cfg[1].channels; - else if (dai_link->be_id == MSM_BACKEND_DAI_SLIMBUS_4_TX) - user_set_tx_ch = msm_vi_feed_tx_ch; - else - user_set_tx_ch = tx_ch_cnt; - - pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), be_id (%d)\n", - __func__, slim_tx_cfg[0].channels, user_set_tx_ch, - tx_ch_cnt, dai_link->be_id); - - ret = snd_soc_dai_set_channel_map(cpu_dai, - user_set_tx_ch, tx_ch, 0, 0); - if (ret < 0) - pr_err("%s: failed to set cpu chan map, err:%d\n", - __func__, ret); - } - -err_ch_map: - return ret; -} -EXPORT_SYMBOL(msm_snd_hw_params); - -/** - * msm_ext_slimbus_2_hw_params - hw params ops of slimbus_2 BE. - * - * @substream: PCM stream of associated backend dailink. - * @params: HW params of associated backend dailink. - * - * Returns 0 on success or ret on failure. - */ -int msm_ext_slimbus_2_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params) -{ - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct snd_soc_dai *codec_dai = rtd->codec_dai; - struct snd_soc_dai *cpu_dai = rtd->cpu_dai; - int ret = 0; - unsigned int rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS]; - unsigned int rx_ch_cnt = 0, tx_ch_cnt = 0; - unsigned int num_tx_ch = 0; - unsigned int num_rx_ch = 0; - - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - num_rx_ch = params_channels(params); - pr_debug("%s: %s rx_dai_id = %d num_ch = %d\n", __func__, - codec_dai->name, codec_dai->id, num_rx_ch); - ret = snd_soc_dai_get_channel_map(codec_dai, - &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch); - if (ret < 0) { - pr_err("%s: failed to get codec chan map, err:%d\n", - __func__, ret); - goto end; - } - ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0, - num_rx_ch, rx_ch); - if (ret < 0) { - pr_err("%s: failed to set cpu chan map, err:%d\n", - __func__, ret); - goto end; - } - } else { - num_tx_ch = params_channels(params); - pr_debug("%s: %s tx_dai_id = %d num_ch = %d\n", __func__, - codec_dai->name, codec_dai->id, num_tx_ch); - ret = snd_soc_dai_get_channel_map(codec_dai, - &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch); - if (ret < 0) { - pr_err("%s: failed to get codec chan map, err:%d\n", - __func__, ret); - goto end; - } - ret = snd_soc_dai_set_channel_map(cpu_dai, - num_tx_ch, tx_ch, 0, 0); - if (ret < 0) { - pr_err("%s: failed to set cpu chan map, err:%d\n", - __func__, ret); - goto end; - } - } -end: - return ret; -} -EXPORT_SYMBOL(msm_ext_slimbus_2_hw_params); - -/** - * msm_snd_cpe_hw_params - hw params ops of CPE backend. - * - * @substream: PCM stream of associated backend dailink. - * @params: HW params of associated backend dailink. - * - * Returns 0 on success or ret on failure. - */ -int msm_snd_cpe_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params) -{ - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct snd_soc_dai *codec_dai = rtd->codec_dai; - struct snd_soc_dai *cpu_dai = rtd->cpu_dai; - struct snd_soc_dai_link *dai_link = rtd->dai_link; - int ret = 0; - u32 tx_ch[SLIM_MAX_TX_PORTS]; - u32 tx_ch_cnt = 0; - - if (substream->stream != SNDRV_PCM_STREAM_CAPTURE) { - pr_err("%s: Invalid stream type %d\n", - __func__, substream->stream); - ret = -EINVAL; - goto end; - } - - pr_debug("%s: %s_tx_dai_id_%d\n", __func__, - codec_dai->name, codec_dai->id); - ret = snd_soc_dai_get_channel_map(codec_dai, - &tx_ch_cnt, tx_ch, NULL, NULL); - if (ret < 0) { - pr_err("%s: failed to get codec chan map\n, err:%d\n", - __func__, ret); - goto end; - } - - pr_debug("%s: tx_ch_cnt(%d) be_id %d\n", - __func__, tx_ch_cnt, dai_link->be_id); - - ret = snd_soc_dai_set_channel_map(cpu_dai, - tx_ch_cnt, tx_ch, 0, 0); - if (ret < 0) { - pr_err("%s: failed to set cpu chan map, err:%d\n", - __func__, ret); - goto end; - } -end: - return ret; -} -EXPORT_SYMBOL(msm_snd_cpe_hw_params); - -static int msm_afe_set_config(struct snd_soc_codec *codec) -{ - int rc; - void *config_data; - - pr_debug("%s: enter\n", __func__); - - if (!msm_codec_fn.get_afe_config_fn) { - dev_err(codec->dev, "%s: codec get afe config not init'ed\n", - __func__); - return -EINVAL; - } - config_data = msm_codec_fn.get_afe_config_fn(codec, - AFE_CDC_REGISTERS_CONFIG); - if (config_data) { - rc = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0); - if (rc) { - pr_err("%s: Failed to set codec registers config %d\n", - __func__, rc); - return rc; - } - } - - config_data = msm_codec_fn.get_afe_config_fn(codec, - AFE_CDC_REGISTER_PAGE_CONFIG); - if (config_data) { - rc = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data, - 0); - if (rc) - pr_err("%s: Failed to set cdc register page config\n", - __func__); - } - - config_data = msm_codec_fn.get_afe_config_fn(codec, - AFE_SLIMBUS_SLAVE_CONFIG); - if (config_data) { - rc = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0); - if (rc) { - pr_err("%s: Failed to set slimbus slave config %d\n", - __func__, rc); - return rc; - } - } - - config_data = msm_codec_fn.get_afe_config_fn(codec, - AFE_AANC_VERSION); - if (config_data) { - rc = afe_set_config(AFE_AANC_VERSION, config_data, 0); - if (rc) { - pr_err("%s: Failed to set AANC version %d\n", - __func__, rc); - return rc; - } - } - - config_data = msm_codec_fn.get_afe_config_fn(codec, - AFE_CDC_CLIP_REGISTERS_CONFIG); - if (config_data) { - rc = afe_set_config(AFE_CDC_CLIP_REGISTERS_CONFIG, - config_data, 0); - if (rc) { - pr_err("%s: Failed to set clip registers %d\n", - __func__, rc); - return rc; - } - } - - config_data = msm_codec_fn.get_afe_config_fn(codec, - AFE_CLIP_BANK_SEL); - if (config_data) { - rc = afe_set_config(AFE_CLIP_BANK_SEL, - config_data, 0); - if (rc) { - pr_err("%s: Failed to set AFE bank selection %d\n", - __func__, rc); - return rc; - } - } - - config_data = msm_codec_fn.get_afe_config_fn(codec, - AFE_CDC_REGISTER_PAGE_CONFIG); - if (config_data) { - rc = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data, - 0); - if (rc) - pr_err("%s: Failed to set cdc register page config\n", - __func__); - } - - return 0; -} - -static void msm_afe_clear_config(void) -{ - afe_clear_config(AFE_CDC_REGISTERS_CONFIG); - afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG); -} - -static void msm_snd_interrupt_config(void) -{ - int val; - - val = ioread32(msm_snd_intr_lpi.mpm_wakeup); - val |= LPI_GPIO_22_WAKEUP_VAL; - iowrite32(val, msm_snd_intr_lpi.mpm_wakeup); - - val = ioread32(msm_snd_intr_lpi.intr1_cfg_apps); - val &= ~(LPI_GPIO_22_INTR1_CFG_MASK); - val |= LPI_GPIO_22_INTR1_CFG_VAL; - iowrite32(val, msm_snd_intr_lpi.intr1_cfg_apps); - - iowrite32(LPI_GPIO_INTR_CFG1_VAL, - msm_snd_intr_lpi.lpi_gpio_intr_cfg); - iowrite32(LPI_GPIO22_CFG_VAL, - msm_snd_intr_lpi.lpi_gpio_cfg); - iowrite32(LPI_GPIO22_INOUT_VAL, - msm_snd_intr_lpi.lpi_gpio_inout); -} - -static int msm_adsp_power_up_config(struct snd_soc_codec *codec) -{ - int ret = 0; - unsigned long timeout; - int adsp_ready = 0; - - timeout = jiffies + - msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS); - - do { - if (q6core_is_adsp_ready()) { - pr_debug("%s: ADSP Audio is ready\n", __func__); - adsp_ready = 1; - break; - } - /* - * ADSP will be coming up after subsystem restart and - * it might not be fully up when the control reaches - * here. So, wait for 50msec before checking ADSP state - */ - msleep(50); - } while (time_after(timeout, jiffies)); - - if (!adsp_ready) { - pr_err("%s: timed out waiting for ADSP Audio\n", __func__); - ret = -ETIMEDOUT; - goto err_fail; - } - msm_snd_interrupt_config(); - - ret = msm_afe_set_config(codec); - if (ret) - pr_err("%s: Failed to set AFE config. err %d\n", - __func__, ret); - - return 0; - -err_fail: - return ret; -} - -static int msmfalcon_notifier_service_cb(struct notifier_block *this, - unsigned long opcode, void *ptr) -{ - int ret; - struct snd_soc_card *card = NULL; - const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX; - struct snd_soc_pcm_runtime *rtd; - struct snd_soc_codec *codec; - - pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode); - - switch (opcode) { - case AUDIO_NOTIFIER_SERVICE_DOWN: - /* - * Use flag to ignore initial boot notifications - * On initial boot msm_adsp_power_up_config is - * called on init. There is no need to clear - * and set the config again on initial boot. - */ - if (is_initial_boot) - break; - msm_afe_clear_config(); - break; - case AUDIO_NOTIFIER_SERVICE_UP: - if (is_initial_boot) { - is_initial_boot = false; - break; - } - if (!spdev) - return -EINVAL; - - card = platform_get_drvdata(spdev); - rtd = snd_soc_get_pcm_runtime(card, be_dl_name); - if (!rtd) { - dev_err(card->dev, - "%s: snd_soc_get_pcm_runtime for %s failed!\n", - __func__, be_dl_name); - ret = -EINVAL; - goto done; - } - codec = rtd->codec; - - ret = msm_adsp_power_up_config(codec); - if (ret < 0) { - dev_err(card->dev, - "%s: msm_adsp_power_up_config failed ret = %d!\n", - __func__, ret); - goto done; - } - break; - default: - break; - } -done: - return NOTIFY_OK; -} - -static struct notifier_block service_nb = { - .notifier_call = msmfalcon_notifier_service_cb, - .priority = -INT_MAX, -}; - -static int msm_config_hph_en0_gpio(struct snd_soc_codec *codec, bool high) -{ - struct snd_soc_card *card = codec->component.card; - struct msm_asoc_mach_data *pdata; - int val; - - if (!card) - return 0; - - pdata = snd_soc_card_get_drvdata(card); - if (!pdata || !gpio_is_valid(pdata->hph_en0_gpio)) - return 0; - - val = gpio_get_value_cansleep(pdata->hph_en0_gpio); - if ((!!val) == high) - return 0; - - gpio_direction_output(pdata->hph_en0_gpio, (int)high); - - return 1; -} - -static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_codec *codec, - int enable, bool dapm) -{ - int ret = 0; - - if (!strcmp(dev_name(codec->dev), "tasha_codec")) - ret = tasha_cdc_mclk_tx_enable(codec, enable, dapm); - else { - dev_err(codec->dev, "%s: unknown codec to enable ext clk\n", - __func__); - ret = -EINVAL; - } - return ret; -} - -static int msm_ext_mclk_tx_event(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, int event) -{ - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - - pr_debug("%s: event = %d\n", __func__, event); - - switch (event) { - case SND_SOC_DAPM_PRE_PMU: - return msm_snd_enable_codec_ext_tx_clk(codec, 1, true); - case SND_SOC_DAPM_POST_PMD: - return msm_snd_enable_codec_ext_tx_clk(codec, 0, true); - } - return 0; -} - -static int msm_ext_mclk_event(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, int event) -{ - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - - pr_debug("%s: event = %d\n", __func__, event); - - switch (event) { - case SND_SOC_DAPM_PRE_PMU: - return msm_ext_enable_codec_mclk(codec, 1, true); - case SND_SOC_DAPM_POST_PMD: - return msm_ext_enable_codec_mclk(codec, 0, true); - } - return 0; -} - -static int msm_ext_prepare_hifi(struct msm_asoc_mach_data *pdata) -{ - int ret = 0; - - if (gpio_is_valid(pdata->hph_en1_gpio)) { - pr_debug("%s: hph_en1_gpio request %d\n", __func__, - pdata->hph_en1_gpio); - ret = gpio_request(pdata->hph_en1_gpio, "hph_en1_gpio"); - if (ret) { - pr_err("%s: hph_en1_gpio request failed, ret:%d\n", - __func__, ret); - goto err; - } - } - if (gpio_is_valid(pdata->hph_en0_gpio)) { - pr_debug("%s: hph_en0_gpio request %d\n", __func__, - pdata->hph_en0_gpio); - ret = gpio_request(pdata->hph_en0_gpio, "hph_en0_gpio"); - if (ret) - pr_err("%s: hph_en0_gpio request failed, ret:%d\n", - __func__, ret); - } - -err: - return ret; -} - -static const struct snd_soc_dapm_widget msm_dapm_widgets[] = { - - SND_SOC_DAPM_SUPPLY_S("MCLK", -1, SND_SOC_NOPM, 0, 0, - msm_ext_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_SUPPLY_S("MCLK TX", -1, SND_SOC_NOPM, 0, 0, - msm_ext_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), - - SND_SOC_DAPM_SPK("Lineout_1 amp", NULL), - SND_SOC_DAPM_SPK("Lineout_3 amp", NULL), - SND_SOC_DAPM_SPK("Lineout_2 amp", NULL), - SND_SOC_DAPM_SPK("Lineout_4 amp", NULL), - SND_SOC_DAPM_MIC("Handset Mic", NULL), - SND_SOC_DAPM_MIC("Headset Mic", NULL), - SND_SOC_DAPM_MIC("Secondary Mic", NULL), - SND_SOC_DAPM_MIC("ANCRight Headset Mic", NULL), - SND_SOC_DAPM_MIC("ANCLeft Headset Mic", NULL), - SND_SOC_DAPM_MIC("Analog Mic4", NULL), - SND_SOC_DAPM_MIC("Analog Mic6", NULL), - SND_SOC_DAPM_MIC("Analog Mic7", NULL), - SND_SOC_DAPM_MIC("Analog Mic8", NULL), - - SND_SOC_DAPM_MIC("Digital Mic0", NULL), - SND_SOC_DAPM_MIC("Digital Mic1", NULL), - SND_SOC_DAPM_MIC("Digital Mic2", NULL), - SND_SOC_DAPM_MIC("Digital Mic3", NULL), - SND_SOC_DAPM_MIC("Digital Mic4", NULL), - SND_SOC_DAPM_MIC("Digital Mic5", NULL), - SND_SOC_DAPM_MIC("Digital Mic6", NULL), -}; - -static struct snd_soc_dapm_route wcd_audio_paths_tasha[] = { - {"MIC BIAS1", NULL, "MCLK TX"}, - {"MIC BIAS2", NULL, "MCLK TX"}, - {"MIC BIAS3", NULL, "MCLK TX"}, - {"MIC BIAS4", NULL, "MCLK TX"}, -}; - -static struct snd_soc_dapm_route wcd_audio_paths[] = { - {"MIC BIAS1", NULL, "MCLK"}, - {"MIC BIAS2", NULL, "MCLK"}, - {"MIC BIAS3", NULL, "MCLK"}, - {"MIC BIAS4", NULL, "MCLK"}, -}; - -/** - * msm_audrx_init - Audio init function of sound card instantiate. - * - * @rtd: runtime dailink instance - * - * Returns 0 on success or ret on failure. - */ -int msm_audrx_init(struct snd_soc_pcm_runtime *rtd) -{ - int ret; - void *config_data; - struct snd_soc_codec *codec = rtd->codec; - struct snd_soc_dapm_context *dapm = - snd_soc_codec_get_dapm(codec); - struct snd_soc_dai *cpu_dai = rtd->cpu_dai; - struct snd_soc_dai *codec_dai = rtd->codec_dai; - struct snd_soc_pcm_runtime *rtd_aux = rtd->card->rtd_aux; - struct snd_card *card; - struct snd_info_entry *entry; - struct msm_asoc_mach_data *pdata = - snd_soc_card_get_drvdata(rtd->card); - - /* Codec SLIMBUS configuration - * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8, RX9, RX10, RX11, RX12, RX13 - * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13 - * TX14, TX15, TX16 - */ - unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150, - 151, 152, 153, 154, 155, 156}; - unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133, - 134, 135, 136, 137, 138, 139, - 140, 141, 142, 143}; - - pr_debug("%s: dev_name%s\n", __func__, dev_name(cpu_dai->dev)); - - rtd->pmdown_time = 0; - - ret = snd_soc_add_codec_controls(codec, msm_snd_controls, - ARRAY_SIZE(msm_snd_controls)); - if (ret < 0) { - pr_err("%s: add_codec_controls failed: %d\n", - __func__, ret); - return ret; - } - - snd_soc_dapm_new_controls(dapm, msm_dapm_widgets, - ARRAY_SIZE(msm_dapm_widgets)); - - if (!strcmp(dev_name(codec_dai->dev), "tasha_codec")) - snd_soc_dapm_add_routes(dapm, wcd_audio_paths_tasha, - ARRAY_SIZE(wcd_audio_paths_tasha)); - else - snd_soc_dapm_add_routes(dapm, wcd_audio_paths, - ARRAY_SIZE(wcd_audio_paths)); - - snd_soc_dapm_enable_pin(dapm, "Lineout_1 amp"); - snd_soc_dapm_enable_pin(dapm, "Lineout_3 amp"); - snd_soc_dapm_enable_pin(dapm, "Lineout_2 amp"); - snd_soc_dapm_enable_pin(dapm, "Lineout_4 amp"); - - snd_soc_dapm_ignore_suspend(dapm, "MADINPUT"); - snd_soc_dapm_ignore_suspend(dapm, "MAD_CPE_INPUT"); - snd_soc_dapm_ignore_suspend(dapm, "Handset Mic"); - snd_soc_dapm_ignore_suspend(dapm, "Headset Mic"); - snd_soc_dapm_ignore_suspend(dapm, "Secondary Mic"); - snd_soc_dapm_ignore_suspend(dapm, "Lineout_1 amp"); - snd_soc_dapm_ignore_suspend(dapm, "Lineout_3 amp"); - snd_soc_dapm_ignore_suspend(dapm, "Lineout_2 amp"); - snd_soc_dapm_ignore_suspend(dapm, "Lineout_4 amp"); - snd_soc_dapm_ignore_suspend(dapm, "ANCRight Headset Mic"); - snd_soc_dapm_ignore_suspend(dapm, "ANCLeft Headset Mic"); - snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0"); - snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1"); - snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2"); - snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3"); - snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4"); - snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5"); - snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4"); - snd_soc_dapm_ignore_suspend(dapm, "Analog Mic6"); - snd_soc_dapm_ignore_suspend(dapm, "Analog Mic7"); - snd_soc_dapm_ignore_suspend(dapm, "Analog Mic8"); - - snd_soc_dapm_ignore_suspend(dapm, "EAR"); - snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1"); - snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2"); - snd_soc_dapm_ignore_suspend(dapm, "LINEOUT3"); - snd_soc_dapm_ignore_suspend(dapm, "LINEOUT4"); - snd_soc_dapm_ignore_suspend(dapm, "AMIC1"); - snd_soc_dapm_ignore_suspend(dapm, "AMIC2"); - snd_soc_dapm_ignore_suspend(dapm, "AMIC3"); - snd_soc_dapm_ignore_suspend(dapm, "AMIC4"); - snd_soc_dapm_ignore_suspend(dapm, "AMIC5"); - snd_soc_dapm_ignore_suspend(dapm, "AMIC6"); - snd_soc_dapm_ignore_suspend(dapm, "DMIC0"); - snd_soc_dapm_ignore_suspend(dapm, "DMIC1"); - snd_soc_dapm_ignore_suspend(dapm, "DMIC2"); - snd_soc_dapm_ignore_suspend(dapm, "DMIC3"); - snd_soc_dapm_ignore_suspend(dapm, "DMIC4"); - snd_soc_dapm_ignore_suspend(dapm, "DMIC5"); - snd_soc_dapm_ignore_suspend(dapm, "ANC EAR"); - snd_soc_dapm_ignore_suspend(dapm, "ANC HEADPHONE"); - snd_soc_dapm_ignore_suspend(dapm, "SPK1 OUT"); - snd_soc_dapm_ignore_suspend(dapm, "SPK2 OUT"); - snd_soc_dapm_ignore_suspend(dapm, "HPHL"); - snd_soc_dapm_ignore_suspend(dapm, "HPHR"); - snd_soc_dapm_ignore_suspend(dapm, "ANC HPHL"); - snd_soc_dapm_ignore_suspend(dapm, "ANC HPHR"); - snd_soc_dapm_ignore_suspend(dapm, "ANC LINEOUT1"); - snd_soc_dapm_ignore_suspend(dapm, "ANC LINEOUT2"); - snd_soc_dapm_ignore_suspend(dapm, "AIF4 VI"); - snd_soc_dapm_ignore_suspend(dapm, "VIINPUT"); - - snd_soc_dapm_sync(dapm); - snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch), - tx_ch, ARRAY_SIZE(rx_ch), rx_ch); - - if (!strcmp(dev_name(codec_dai->dev), "tavil_codec")) { - msm_codec_fn.get_afe_config_fn = tavil_get_afe_config; - } else { - msm_codec_fn.get_afe_config_fn = tasha_get_afe_config; - msm_codec_fn.mbhc_hs_detect_exit = tasha_mbhc_hs_detect_exit; - } - - ret = msm_adsp_power_up_config(codec); - if (ret) { - pr_err("%s: Failed to set AFE config %d\n", __func__, ret); - goto err_afe_cfg; - } - - config_data = msm_codec_fn.get_afe_config_fn(codec, - AFE_AANC_VERSION); - if (config_data) { - ret = afe_set_config(AFE_AANC_VERSION, config_data, 0); - if (ret) { - pr_err("%s: Failed to set aanc version %d\n", - __func__, ret); - goto err_afe_cfg; - } - } - - if (!strcmp(dev_name(codec_dai->dev), "tasha_codec")) { - config_data = msm_codec_fn.get_afe_config_fn(codec, - AFE_CDC_CLIP_REGISTERS_CONFIG); - if (config_data) { - ret = afe_set_config(AFE_CDC_CLIP_REGISTERS_CONFIG, - config_data, 0); - if (ret) { - pr_err("%s: Failed to set clip registers %d\n", - __func__, ret); - goto err_afe_cfg; - } - } - config_data = msm_codec_fn.get_afe_config_fn(codec, - AFE_CLIP_BANK_SEL); - if (config_data) { - ret = afe_set_config(AFE_CLIP_BANK_SEL, config_data, 0); - if (ret) { - pr_err("%s: Failed to set AFE bank selection %d\n", - __func__, ret); - goto err_afe_cfg; - } - } - } - - /* - * Send speaker configuration only for WSA8810. - * Defalut configuration is for WSA8815. - */ - if (!strcmp(dev_name(codec_dai->dev), "tavil_codec")) { - if (rtd_aux && rtd_aux->component) - if (!strcmp(rtd_aux->component->name, WSA8810_NAME_1) || - !strcmp(rtd_aux->component->name, WSA8810_NAME_2)) { - tavil_set_spkr_mode(rtd->codec, SPKR_MODE_1); - tavil_set_spkr_gain_offset(rtd->codec, - RX_GAIN_OFFSET_M1P5_DB); - } - card = rtd->card->snd_card; - entry = snd_register_module_info(card->module, "codecs", - card->proc_root); - if (!entry) { - pr_debug("%s: Cannot create codecs module entry\n", - __func__); - pdata->codec_root = NULL; - goto done; - } - pdata->codec_root = entry; - tavil_codec_info_create_codec_entry(pdata->codec_root, codec); - } else { - if (rtd_aux && rtd_aux->component) - if (!strcmp(rtd_aux->component->name, WSA8810_NAME_1) || - !strcmp(rtd_aux->component->name, WSA8810_NAME_2)) { - tasha_set_spkr_mode(rtd->codec, SPKR_MODE_1); - tasha_set_spkr_gain_offset(rtd->codec, - RX_GAIN_OFFSET_M1P5_DB); - } - card = rtd->card->snd_card; - entry = snd_register_module_info(card->module, "codecs", - card->proc_root); - if (!entry) { - pr_debug("%s: Cannot create codecs module entry\n", - __func__); - ret = 0; - goto err_snd_module; - } - pdata->codec_root = entry; - tasha_codec_info_create_codec_entry(pdata->codec_root, codec); - tasha_mbhc_zdet_gpio_ctrl(msm_config_hph_en0_gpio, rtd->codec); - } - - wcd_mbhc_cfg_ptr->calibration = def_ext_mbhc_cal(); - if (!strcmp(dev_name(codec_dai->dev), "tavil_codec")) { - if (wcd_mbhc_cfg_ptr->calibration) { - pdata->codec = codec; - ret = tavil_mbhc_hs_detect(codec, wcd_mbhc_cfg_ptr); - if (ret < 0) - pr_err("%s: Failed to intialise mbhc %d\n", - __func__, ret); - } else { - pr_err("%s: wcd_mbhc_cfg calibration is NULL\n", - __func__); - ret = -ENOMEM; - goto err_mbhc_cal; - } - } else { - if (wcd_mbhc_cfg_ptr->calibration) { - pdata->codec = codec; - ret = tasha_mbhc_hs_detect(codec, wcd_mbhc_cfg_ptr); - if (ret < 0) - pr_err("%s: Failed to intialise mbhc %d\n", - __func__, ret); - } else { - pr_err("%s: wcd_mbhc_cfg calibration is NULL\n", - __func__); - ret = -ENOMEM; - goto err_mbhc_cal; - } - - } -done: - return 0; - -err_snd_module: -err_afe_cfg: -err_mbhc_cal: - return ret; -} -EXPORT_SYMBOL(msm_audrx_init); - -/** - * msm_ext_register_audio_notifier - register SSR notifier. - */ -void msm_ext_register_audio_notifier(void) -{ - int ret; - - ret = audio_notifier_register("msmfalcon", AUDIO_NOTIFIER_ADSP_DOMAIN, - &service_nb); - if (ret < 0) - pr_err("%s: Audio notifier register failed ret = %d\n", - __func__, ret); -} -EXPORT_SYMBOL(msm_ext_register_audio_notifier); - -/** - * msm_ext_cdc_init - external codec machine specific init. - * - * @pdev: platform device handle - * @pdata: private data of machine driver - * @card: sound card pointer reference - * @mbhc_cfg: MBHC config reference - * - * Returns 0 on success or ret on failure. - */ -int msm_ext_cdc_init(struct platform_device *pdev, - struct msm_asoc_mach_data *pdata, - struct snd_soc_card **card, - struct wcd_mbhc_config *wcd_mbhc_cfg_ptr1) -{ - int ret = 0; - - wcd_mbhc_cfg_ptr = wcd_mbhc_cfg_ptr1; - pdev->id = 0; - wcd_mbhc_cfg_ptr->moisture_en = true; - wcd_mbhc_cfg_ptr->mbhc_micbias = MIC_BIAS_2; - wcd_mbhc_cfg_ptr->anc_micbias = MIC_BIAS_2; - wcd_mbhc_cfg_ptr->enable_anc_mic_detect = false; - - *card = populate_snd_card_dailinks(&pdev->dev, pdata->snd_card_val); - if (!(*card)) { - dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__); - ret = -EPROBE_DEFER; - goto err; - } - spdev = pdev; - platform_set_drvdata(pdev, *card); - snd_soc_card_set_drvdata(*card, pdata); - is_initial_boot = true; - pdata->hph_en1_gpio = of_get_named_gpio(pdev->dev.of_node, - "qcom,hph-en1-gpio", 0); - if (!gpio_is_valid(pdata->hph_en1_gpio)) - pdata->hph_en1_gpio_p = of_parse_phandle(pdev->dev.of_node, - "qcom,hph-en1-gpio", 0); - if (!gpio_is_valid(pdata->hph_en1_gpio) && (!pdata->hph_en1_gpio_p)) { - dev_dbg(&pdev->dev, "property %s not detected in node %s", - "qcom,hph-en1-gpio", pdev->dev.of_node->full_name); - } - - pdata->hph_en0_gpio = of_get_named_gpio(pdev->dev.of_node, - "qcom,hph-en0-gpio", 0); - if (!gpio_is_valid(pdata->hph_en0_gpio)) - pdata->hph_en0_gpio_p = of_parse_phandle(pdev->dev.of_node, - "qcom,hph-en0-gpio", 0); - if (!gpio_is_valid(pdata->hph_en0_gpio) && (!pdata->hph_en0_gpio_p)) { - dev_dbg(&pdev->dev, "property %s not detected in node %s", - "qcom,hph-en0-gpio", pdev->dev.of_node->full_name); - } - - ret = msm_ext_prepare_hifi(pdata); - if (ret) { - dev_dbg(&pdev->dev, "msm_ext_prepare_hifi failed (%d)\n", - ret); - ret = 0; - } - msm_snd_intr_lpi.mpm_wakeup = - ioremap(TLMM_CENTER_MPM_WAKEUP_INT_EN_0, 4); - msm_snd_intr_lpi.intr1_cfg_apps = - ioremap(TLMM_LPI_DIR_CONN_INTR1_CFG_APPS, 4); - msm_snd_intr_lpi.lpi_gpio_intr_cfg = - ioremap(TLMM_LPI_GPIO_INTR_CFG1, 4); - msm_snd_intr_lpi.lpi_gpio_cfg = - ioremap(TLMM_LPI_GPIO22_CFG, 4); - msm_snd_intr_lpi.lpi_gpio_inout = - ioremap(TLMM_LPI_GPIO22_INOUT, 4); -err: - return ret; -} -EXPORT_SYMBOL(msm_ext_cdc_init); - -/** - * msm_ext_cdc_deinit - external codec machine specific deinit. - */ -void msm_ext_cdc_deinit(void) -{ - if (msm_snd_intr_lpi.mpm_wakeup) - iounmap(msm_snd_intr_lpi.mpm_wakeup); - if (msm_snd_intr_lpi.intr1_cfg_apps) - iounmap(msm_snd_intr_lpi.intr1_cfg_apps); - if (msm_snd_intr_lpi.lpi_gpio_intr_cfg) - iounmap(msm_snd_intr_lpi.lpi_gpio_intr_cfg); - if (msm_snd_intr_lpi.lpi_gpio_cfg) - iounmap(msm_snd_intr_lpi.lpi_gpio_cfg); - if (msm_snd_intr_lpi.lpi_gpio_inout) - iounmap(msm_snd_intr_lpi.lpi_gpio_inout); -} -EXPORT_SYMBOL(msm_ext_cdc_deinit); diff --git a/sound/soc/msm/msmfalcon-external.h b/sound/soc/msm/msmfalcon-external.h deleted file mode 100644 index fc82b628dfac..000000000000 --- a/sound/soc/msm/msmfalcon-external.h +++ /dev/null @@ -1,54 +0,0 @@ -/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MSMFALCON_EXTERNAL -#define __MSMFALCON_EXTERNAL - -int msm_snd_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params); -int msm_ext_slimbus_2_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params); -int msm_btsco_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, - struct snd_pcm_hw_params *params); -int msm_proxy_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, - struct snd_pcm_hw_params *params); -int msm_proxy_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, - struct snd_pcm_hw_params *params); -int msm_audrx_init(struct snd_soc_pcm_runtime *rtd); -int msm_snd_cpe_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params); -struct snd_soc_card *populate_snd_card_dailinks(struct device *dev, - int snd_card_val); -int msm_ext_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, - struct snd_pcm_hw_params *params); -#ifdef CONFIG_SND_SOC_EXT_CODEC -int msm_ext_cdc_init(struct platform_device *, struct msm_asoc_mach_data *, - struct snd_soc_card **, struct wcd_mbhc_config *); -void msm_ext_register_audio_notifier(void); -void msm_ext_cdc_deinit(void); -#else -inline int msm_ext_cdc_init(struct platform_device *pdev, - struct msm_asoc_mach_data *pdata, - struct snd_soc_card **card, - struct wcd_mbhc_config *wcd_mbhc_cfg_ptr1) -{ - return 0; -} - -inline void msm_ext_register_audio_notifier(void) -{ -} -inline void msm_ext_cdc_deinit(void) -{ -} -#endif -#endif diff --git a/sound/soc/msm/msmfalcon-internal.c b/sound/soc/msm/msmfalcon-internal.c deleted file mode 100644 index 5226e791fcff..000000000000 --- a/sound/soc/msm/msmfalcon-internal.c +++ /dev/null @@ -1,3089 +0,0 @@ -/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include "qdsp6v2/msm-pcm-routing-v2.h" -#include "msmfalcon-common.h" -#include "../codecs/msmfalcon_cdc/msm-digital-cdc.h" -#include "../codecs/msmfalcon_cdc/msm-analog-cdc.h" -#include "../codecs/msm_sdw/msm_sdw.h" - -#define __CHIPSET__ "MSMFALCON " -#define MSM_DAILINK_NAME(name) (__CHIPSET__#name) - -#define DEFAULT_MCLK_RATE 9600000 -#define NATIVE_MCLK_RATE 11289600 - -#define WCD_MBHC_DEF_RLOADS 5 - -#define WCN_CDC_SLIM_RX_CH_MAX 2 -#define WCN_CDC_SLIM_TX_CH_MAX 3 - -#define WSA8810_NAME_1 "wsa881x.20170211" -#define WSA8810_NAME_2 "wsa881x.20170212" - -enum { - INT0_MI2S = 0, - INT1_MI2S, - INT2_MI2S, - INT3_MI2S, - INT4_MI2S, - INT5_MI2S, - INT6_MI2S, - INT_MI2S_MAX, -}; - -enum { - BT_SLIM7, - FM_SLIM8, - SLIM_MAX, -}; - -/*TDM default offset currently only supporting TDM_RX_0 and TDM_TX_0 */ -static unsigned int tdm_slot_offset[TDM_PORT_MAX][TDM_SLOT_OFFSET_MAX] = { - {0, 4, 8, 12, 16, 20, 24, 28},/* TX_0 | RX_0 */ - {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_1 | RX_1 */ - {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_2 | RX_2 */ - {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_3 | RX_3 */ - {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_4 | RX_4 */ - {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_5 | RX_5 */ - {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_6 | RX_6 */ - {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_7 | RX_7 */ -}; - -static struct afe_clk_set int_mi2s_clk[INT_MI2S_MAX] = { - { - AFE_API_VERSION_I2S_CONFIG, - Q6AFE_LPASS_CLK_ID_INT0_MI2S_IBIT, - Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, - Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, - Q6AFE_LPASS_CLK_ROOT_DEFAULT, - 0, - }, - { - AFE_API_VERSION_I2S_CONFIG, - Q6AFE_LPASS_CLK_ID_INT1_MI2S_IBIT, - Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, - Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, - Q6AFE_LPASS_CLK_ROOT_DEFAULT, - 0, - }, - { - AFE_API_VERSION_I2S_CONFIG, - Q6AFE_LPASS_CLK_ID_INT2_MI2S_IBIT, - Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, - Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, - Q6AFE_LPASS_CLK_ROOT_DEFAULT, - 0, - }, - { - AFE_API_VERSION_I2S_CONFIG, - Q6AFE_LPASS_CLK_ID_INT3_MI2S_IBIT, - Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, - Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, - Q6AFE_LPASS_CLK_ROOT_DEFAULT, - 0, - }, - { - AFE_API_VERSION_I2S_CONFIG, - Q6AFE_LPASS_CLK_ID_INT4_MI2S_IBIT, - Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, - Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, - Q6AFE_LPASS_CLK_ROOT_DEFAULT, - 0, - }, - { - AFE_API_VERSION_I2S_CONFIG, - Q6AFE_LPASS_CLK_ID_INT5_MI2S_IBIT, - Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, - Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, - Q6AFE_LPASS_CLK_ROOT_DEFAULT, - 0, - }, - { - AFE_API_VERSION_I2S_CONFIG, - Q6AFE_LPASS_CLK_ID_INT6_MI2S_IBIT, - Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, - Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, - Q6AFE_LPASS_CLK_ROOT_DEFAULT, - 0, - }, -}; - -struct dev_config { - u32 sample_rate; - u32 bit_format; - u32 channels; -}; - -/* Default configuration of MI2S channels */ -static struct dev_config int_mi2s_cfg[] = { - [INT0_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, - [INT1_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [INT2_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [INT3_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [INT4_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [INT5_MI2S] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, - [INT6_MI2S] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, -}; - -static struct dev_config bt_fm_cfg[] = { - [BT_SLIM7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, - [FM_SLIM8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, -}; - -static char const *int_mi2s_rate_text[] = {"KHZ_8", "KHZ_16", - "KHZ_32", "KHZ_44P1", "KHZ_48", - "KHZ_96", "KHZ_192"}; -static const char *const int_mi2s_ch_text[] = {"One", "Two"}; -static const char *const int_mi2s_tx_ch_text[] = {"One", "Two", - "Three", "Four"}; -static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE"}; -static const char *const loopback_mclk_text[] = {"DISABLE", "ENABLE"}; -static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_48"}; - -static SOC_ENUM_SINGLE_EXT_DECL(int0_mi2s_rx_sample_rate, int_mi2s_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(int0_mi2s_rx_chs, int_mi2s_ch_text); -static SOC_ENUM_SINGLE_EXT_DECL(int0_mi2s_rx_format, bit_format_text); -static SOC_ENUM_SINGLE_EXT_DECL(int2_mi2s_tx_sample_rate, int_mi2s_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(int2_mi2s_tx_chs, int_mi2s_tx_ch_text); -static SOC_ENUM_SINGLE_EXT_DECL(int2_mi2s_tx_format, bit_format_text); -static SOC_ENUM_SINGLE_EXT_DECL(int3_mi2s_tx_sample_rate, int_mi2s_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(int3_mi2s_tx_chs, int_mi2s_tx_ch_text); -static SOC_ENUM_SINGLE_EXT_DECL(int3_mi2s_tx_format, bit_format_text); -static SOC_ENUM_SINGLE_EXT_DECL(int4_mi2s_rx_sample_rate, int_mi2s_rate_text); -static SOC_ENUM_SINGLE_EXT_DECL(int4_mi2s_rx_chs, int_mi2s_ch_text); -static SOC_ENUM_SINGLE_EXT_DECL(int4_mi2s_rx_format, bit_format_text); -static SOC_ENUM_SINGLE_EXT_DECL(int5_mi2s_tx_chs, int_mi2s_ch_text); -static SOC_ENUM_SINGLE_EXT_DECL(loopback_mclk_en, loopback_mclk_text); -static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text); - -static int msm_dmic_event(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, int event); -static int msm_int_enable_dig_cdc_clk(struct snd_soc_codec *codec, int enable, - bool dapm); -static int msm_int_mclk0_event(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, int event); -static int msm_int_mi2s_snd_startup(struct snd_pcm_substream *substream); -static void msm_int_mi2s_snd_shutdown(struct snd_pcm_substream *substream); - -static struct wcd_mbhc_config *mbhc_cfg_ptr; -static struct snd_info_entry *msm_sdw_codec_root; -static struct snd_info_entry *msm_dig_codec_root; -static struct snd_info_entry *pmic_analog_codec_root; - -static int int_mi2s_get_bit_format_val(int bit_format) -{ - int val = 0; - - switch (bit_format) { - case SNDRV_PCM_FORMAT_S24_3LE: - val = 2; - break; - case SNDRV_PCM_FORMAT_S24_LE: - val = 1; - break; - case SNDRV_PCM_FORMAT_S16_LE: - default: - val = 0; - break; - } - return val; -} - -static int int_mi2s_get_bit_format(int val) -{ - int bit_fmt = SNDRV_PCM_FORMAT_S16_LE; - - switch (val) { - case 0: - bit_fmt = SNDRV_PCM_FORMAT_S16_LE; - break; - case 1: - bit_fmt = SNDRV_PCM_FORMAT_S24_LE; - break; - case 2: - bit_fmt = SNDRV_PCM_FORMAT_S24_3LE; - break; - default: - bit_fmt = SNDRV_PCM_FORMAT_S16_LE; - break; - } - return bit_fmt; -} - -static int int_mi2s_get_port_idx(struct snd_kcontrol *kcontrol) -{ - int port_id = 0; - - if (strnstr(kcontrol->id.name, "INT0_MI2S", sizeof("INT0_MI2S"))) - port_id = INT0_MI2S; - else if (strnstr(kcontrol->id.name, "INT2_MI2S", sizeof("INT2_MI2S"))) - port_id = INT2_MI2S; - else if (strnstr(kcontrol->id.name, "INT3_MI2S", sizeof("INT3_MI2S"))) - port_id = INT3_MI2S; - else if (strnstr(kcontrol->id.name, "INT4_MI2S", sizeof("INT4_MI2S"))) - port_id = INT4_MI2S; - else { - pr_err("%s: unsupported channel: %s", - __func__, kcontrol->id.name); - return -EINVAL; - } - - return port_id; -} - -static int int_mi2s_bit_format_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ch_num = int_mi2s_get_port_idx(kcontrol); - - if (ch_num < 0) - return ch_num; - - ucontrol->value.enumerated.item[0] = - int_mi2s_get_bit_format_val(int_mi2s_cfg[ch_num].bit_format); - - pr_debug("%s: int_mi2s[%d]_bit_format = %d, ucontrol value = %d\n", - __func__, ch_num, int_mi2s_cfg[ch_num].bit_format, - ucontrol->value.enumerated.item[0]); - - return 0; -} - -static int int_mi2s_bit_format_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ch_num = int_mi2s_get_port_idx(kcontrol); - - if (ch_num < 0) - return ch_num; - - int_mi2s_cfg[ch_num].bit_format = - int_mi2s_get_bit_format(ucontrol->value.enumerated.item[0]); - - pr_debug("%s: int_mi2s[%d]_rx_bit_format = %d, ucontrol value = %d\n", - __func__, ch_num, int_mi2s_cfg[ch_num].bit_format, - ucontrol->value.enumerated.item[0]); - - return 0; -} - -static inline int param_is_mask(int p) -{ - return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) && - (p <= SNDRV_PCM_HW_PARAM_LAST_MASK); -} - -static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p, - int n) -{ - return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]); -} - -static void param_set_mask(struct snd_pcm_hw_params *p, int n, unsigned bit) -{ - if (bit >= SNDRV_MASK_MAX) - return; - if (param_is_mask(n)) { - struct snd_mask *m = param_to_mask(p, n); - - m->bits[0] = 0; - m->bits[1] = 0; - m->bits[bit >> 5] |= (1 << (bit & 31)); - } -} - -static int int_mi2s_get_sample_rate_val(int sample_rate) -{ - int sample_rate_val; - - switch (sample_rate) { - case SAMPLING_RATE_8KHZ: - sample_rate_val = 0; - break; - case SAMPLING_RATE_16KHZ: - sample_rate_val = 1; - break; - case SAMPLING_RATE_32KHZ: - sample_rate_val = 2; - break; - case SAMPLING_RATE_44P1KHZ: - sample_rate_val = 3; - break; - case SAMPLING_RATE_48KHZ: - sample_rate_val = 4; - break; - case SAMPLING_RATE_96KHZ: - sample_rate_val = 5; - break; - case SAMPLING_RATE_192KHZ: - sample_rate_val = 6; - break; - default: - sample_rate_val = 4; - break; - } - return sample_rate_val; -} - -static int int_mi2s_get_sample_rate(int value) -{ - int sample_rate; - - switch (value) { - case 0: - sample_rate = SAMPLING_RATE_8KHZ; - break; - case 1: - sample_rate = SAMPLING_RATE_16KHZ; - break; - case 2: - sample_rate = SAMPLING_RATE_32KHZ; - break; - case 3: - sample_rate = SAMPLING_RATE_44P1KHZ; - break; - case 4: - sample_rate = SAMPLING_RATE_48KHZ; - break; - case 5: - sample_rate = SAMPLING_RATE_96KHZ; - break; - case 6: - sample_rate = SAMPLING_RATE_192KHZ; - break; - default: - sample_rate = SAMPLING_RATE_48KHZ; - break; - } - return sample_rate; -} - -static int int_mi2s_sample_rate_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int idx = int_mi2s_get_port_idx(kcontrol); - - if (idx < 0) - return idx; - - int_mi2s_cfg[idx].sample_rate = - int_mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]); - - pr_debug("%s: idx[%d]_sample_rate = %d, item = %d\n", __func__, - idx, int_mi2s_cfg[idx].sample_rate, - ucontrol->value.enumerated.item[0]); - - return 0; -} - -static int int_mi2s_sample_rate_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int idx = int_mi2s_get_port_idx(kcontrol); - - if (idx < 0) - return idx; - - ucontrol->value.enumerated.item[0] = - int_mi2s_get_sample_rate_val(int_mi2s_cfg[idx].sample_rate); - - pr_debug("%s: idx[%d]_sample_rate = %d, item = %d\n", __func__, - idx, int_mi2s_cfg[idx].sample_rate, - ucontrol->value.enumerated.item[0]); - - return 0; -} - -static int int_mi2s_ch_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int idx = int_mi2s_get_port_idx(kcontrol); - - if (idx < 0) - return idx; - - pr_debug("%s: int_mi2s_[%d]_rx_ch = %d\n", __func__, - idx, int_mi2s_cfg[idx].channels); - ucontrol->value.enumerated.item[0] = int_mi2s_cfg[idx].channels - 1; - - return 0; -} - -static int int_mi2s_ch_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int idx = int_mi2s_get_port_idx(kcontrol); - - if (idx < 0) - return idx; - - int_mi2s_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1; - pr_debug("%s: int_mi2s_[%d]_ch = %d\n", __func__, - idx, int_mi2s_cfg[idx].channels); - - return 1; -} - -static const struct snd_soc_dapm_widget msm_int_dapm_widgets[] = { - SND_SOC_DAPM_SUPPLY_S("INT_MCLK0", -1, SND_SOC_NOPM, 0, 0, - msm_int_mclk0_event, SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_MIC("Handset Mic", NULL), - SND_SOC_DAPM_MIC("Headset Mic", NULL), - SND_SOC_DAPM_MIC("Secondary Mic", NULL), - SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event), - SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event), - SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event), - SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event), -}; - -static int msm_config_hph_compander_gpio(bool enable, - struct snd_soc_codec *codec) -{ - struct snd_soc_card *card = codec->component.card; - struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); - int ret = 0; - - pr_debug("%s: %s HPH Compander\n", __func__, - enable ? "Enable" : "Disable"); - - if (enable) { - ret = msm_cdc_pinctrl_select_active_state(pdata->comp_gpio_p); - if (ret) { - pr_err("%s: gpio set cannot be activated %s\n", - __func__, "comp_gpio"); - goto done; - } - } else { - ret = msm_cdc_pinctrl_select_sleep_state(pdata->comp_gpio_p); - if (ret) { - pr_err("%s: gpio set cannot be de-activated %s\n", - __func__, "comp_gpio"); - goto done; - } - } - -done: - return ret; -} - -static int is_ext_spk_gpio_support(struct platform_device *pdev, - struct msm_asoc_mach_data *pdata) -{ - const char *spk_ext_pa = "qcom,msm-spk-ext-pa"; - - pr_debug("%s:Enter\n", __func__); - - pdata->spk_ext_pa_gpio = of_get_named_gpio(pdev->dev.of_node, - spk_ext_pa, 0); - - if (pdata->spk_ext_pa_gpio < 0) { - dev_dbg(&pdev->dev, - "%s: missing %s in dt node\n", __func__, spk_ext_pa); - } else { - if (!gpio_is_valid(pdata->spk_ext_pa_gpio)) { - pr_err("%s: Invalid external speaker gpio: %d", - __func__, pdata->spk_ext_pa_gpio); - return -EINVAL; - } - } - return 0; -} - -static int enable_spk_ext_pa(struct snd_soc_codec *codec, int enable) -{ - struct snd_soc_card *card = codec->component.card; - struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); - int ret; - - if (!gpio_is_valid(pdata->spk_ext_pa_gpio)) { - pr_err("%s: Invalid gpio: %d\n", __func__, - pdata->spk_ext_pa_gpio); - return false; - } - - pr_debug("%s: %s external speaker PA\n", __func__, - enable ? "Enable" : "Disable"); - - if (enable) { - ret = msm_cdc_pinctrl_select_active_state( - pdata->ext_spk_gpio_p); - if (ret) { - pr_err("%s: gpio set cannot be de-activated %s\n", - __func__, "ext_spk_gpio"); - return ret; - } - gpio_set_value_cansleep(pdata->spk_ext_pa_gpio, enable); - } else { - gpio_set_value_cansleep(pdata->spk_ext_pa_gpio, enable); - ret = msm_cdc_pinctrl_select_sleep_state( - pdata->ext_spk_gpio_p); - if (ret) { - pr_err("%s: gpio set cannot be de-activated %s\n", - __func__, "ext_spk_gpio"); - return ret; - } - } - return 0; -} - -static int msm_config_sdw_gpio(bool enable, struct snd_soc_codec *codec) -{ - struct snd_soc_card *card = codec->component.card; - struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); - int ret = 0; - - pr_debug("%s: %s SDW Clk/Data Gpios\n", __func__, - enable ? "Enable" : "Disable"); - - if (enable) { - ret = msm_cdc_pinctrl_select_active_state(pdata->sdw_gpio_p); - if (ret) { - pr_err("%s: gpio set cannot be activated %s\n", - __func__, "sdw_pin"); - goto done; - } - } else { - ret = msm_cdc_pinctrl_select_sleep_state(pdata->sdw_gpio_p); - if (ret) { - pr_err("%s: gpio set cannot be de-activated %s\n", - __func__, "sdw_pin"); - goto done; - } - } - -done: - return ret; -} - -static int int_mi2s_get_idx_from_beid(int32_t be_id) -{ - int idx = 0; - - switch (be_id) { - case MSM_BACKEND_DAI_INT0_MI2S_RX: - idx = INT0_MI2S; - break; - case MSM_BACKEND_DAI_INT2_MI2S_TX: - idx = INT2_MI2S; - break; - case MSM_BACKEND_DAI_INT3_MI2S_TX: - idx = INT3_MI2S; - break; - case MSM_BACKEND_DAI_INT4_MI2S_RX: - idx = INT4_MI2S; - break; - case MSM_BACKEND_DAI_INT5_MI2S_TX: - idx = INT5_MI2S; - break; - default: - idx = INT0_MI2S; - break; - } - - return idx; -} - -static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, - struct snd_pcm_hw_params *params) -{ - struct snd_interval *rate = hw_param_interval(params, - SNDRV_PCM_HW_PARAM_RATE); - - struct snd_interval *channels = hw_param_interval(params, - SNDRV_PCM_HW_PARAM_CHANNELS); - - pr_debug("%s()\n", __func__); - rate->min = rate->max = 48000; - channels->min = channels->max = 2; - - return 0; -} - -static int int_mi2s_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, - struct snd_pcm_hw_params *params) -{ - struct snd_soc_dai_link *dai_link = rtd->dai_link; - struct snd_interval *rate = hw_param_interval(params, - SNDRV_PCM_HW_PARAM_RATE); - struct snd_interval *channels = hw_param_interval(params, - SNDRV_PCM_HW_PARAM_CHANNELS); - int idx; - - pr_debug("%s: format = %d, rate = %d\n", - __func__, params_format(params), params_rate(params)); - - switch (dai_link->be_id) { - case MSM_BACKEND_DAI_INT0_MI2S_RX: - case MSM_BACKEND_DAI_INT2_MI2S_TX: - case MSM_BACKEND_DAI_INT3_MI2S_TX: - case MSM_BACKEND_DAI_INT4_MI2S_RX: - case MSM_BACKEND_DAI_INT5_MI2S_TX: - idx = int_mi2s_get_idx_from_beid(dai_link->be_id); - rate->min = rate->max = int_mi2s_cfg[idx].sample_rate; - channels->min = channels->max = - int_mi2s_cfg[idx].channels; - param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, - int_mi2s_cfg[idx].bit_format); - break; - default: - rate->min = rate->max = SAMPLING_RATE_48KHZ; - break; - } - return 0; -} - -static int msm_btfm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, - struct snd_pcm_hw_params *params) -{ - struct snd_soc_dai_link *dai_link = rtd->dai_link; - struct snd_interval *rate = hw_param_interval(params, - SNDRV_PCM_HW_PARAM_RATE); - struct snd_interval *channels = hw_param_interval(params, - SNDRV_PCM_HW_PARAM_CHANNELS); - - switch (dai_link->be_id) { - case MSM_BACKEND_DAI_SLIMBUS_7_RX: - case MSM_BACKEND_DAI_SLIMBUS_7_TX: - param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, - bt_fm_cfg[BT_SLIM7].bit_format); - rate->min = rate->max = bt_fm_cfg[BT_SLIM7].sample_rate; - channels->min = channels->max = - bt_fm_cfg[BT_SLIM7].channels; - break; - - case MSM_BACKEND_DAI_SLIMBUS_8_TX: - rate->min = rate->max = bt_fm_cfg[FM_SLIM8].sample_rate; - channels->min = channels->max = - bt_fm_cfg[FM_SLIM8].channels; - break; - - default: - rate->min = rate->max = SAMPLING_RATE_48KHZ; - break; - } - return 0; -} - -static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - ucontrol->value.integer.value[0] = - (int_mi2s_cfg[INT5_MI2S].channels/2 - 1); - pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__, - ucontrol->value.integer.value[0]); - return 0; -} - -static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int_mi2s_cfg[INT5_MI2S].channels = - roundup_pow_of_two(ucontrol->value.integer.value[0] + 2); - - pr_debug("%s: msm_vi_feed_tx_ch = %d\n", - __func__, int_mi2s_cfg[INT5_MI2S].channels); - return 1; -} - -static int msm_int_enable_dig_cdc_clk(struct snd_soc_codec *codec, - int enable, bool dapm) -{ - int ret = 0; - struct msm_asoc_mach_data *pdata = NULL; - int clk_freq_in_hz; - bool int_mclk0_freq_chg = false; - - pdata = snd_soc_card_get_drvdata(codec->component.card); - pr_debug("%s: enable %d mclk ref counter %d\n", - __func__, enable, - atomic_read(&pdata->int_mclk0_rsc_ref)); - if (enable) { - if (int_mi2s_cfg[INT0_MI2S].sample_rate == - SAMPLING_RATE_44P1KHZ) { - clk_freq_in_hz = NATIVE_MCLK_RATE; - pdata->native_clk_set = true; - } else { - clk_freq_in_hz = pdata->mclk_freq; - pdata->native_clk_set = false; - } - - if (pdata->digital_cdc_core_clk.clk_freq_in_hz - != clk_freq_in_hz) - int_mclk0_freq_chg = true; - if (!atomic_read(&pdata->int_mclk0_rsc_ref) || - int_mclk0_freq_chg) { - cancel_delayed_work_sync( - &pdata->disable_int_mclk0_work); - mutex_lock(&pdata->cdc_int_mclk0_mutex); - if (atomic_read(&pdata->int_mclk0_enabled) == false || - int_mclk0_freq_chg) { - pdata->digital_cdc_core_clk.clk_freq_in_hz = - clk_freq_in_hz; - pdata->digital_cdc_core_clk.enable = 1; - ret = afe_set_lpass_clock_v2( - AFE_PORT_ID_INT0_MI2S_RX, - &pdata->digital_cdc_core_clk); - if (ret < 0) { - pr_err("%s: failed to enable CCLK\n", - __func__); - mutex_unlock( - &pdata->cdc_int_mclk0_mutex); - return ret; - } - pr_debug("enabled digital codec core clk\n"); - atomic_set(&pdata->int_mclk0_enabled, true); - } - mutex_unlock(&pdata->cdc_int_mclk0_mutex); - } - atomic_inc(&pdata->int_mclk0_rsc_ref); - } else { - cancel_delayed_work_sync(&pdata->disable_int_mclk0_work); - mutex_lock(&pdata->cdc_int_mclk0_mutex); - if (atomic_read(&pdata->int_mclk0_enabled) == true) { - pdata->digital_cdc_core_clk.enable = 0; - ret = afe_set_lpass_clock_v2( - AFE_PORT_ID_INT0_MI2S_RX, - &pdata->digital_cdc_core_clk); - if (ret < 0) - pr_err("%s: failed to disable CCLK\n", - __func__); - atomic_set(&pdata->int_mclk0_enabled, false); - } - mutex_unlock(&pdata->cdc_int_mclk0_mutex); - } - return ret; -} - -static int loopback_mclk_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - pr_debug("%s\n", __func__); - return 0; -} - -static int loopback_mclk_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ret = -EINVAL; - struct msm_asoc_mach_data *pdata = NULL; - struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - - pdata = snd_soc_card_get_drvdata(codec->component.card); - pr_debug("%s: mclk_rsc_ref %d enable %ld\n", - __func__, atomic_read(&pdata->int_mclk0_rsc_ref), - ucontrol->value.integer.value[0]); - switch (ucontrol->value.integer.value[0]) { - case 1: - ret = msm_cdc_pinctrl_select_active_state(pdata->pdm_gpio_p); - if (ret) { - pr_err("%s: failed to enable the pri gpios: %d\n", - __func__, ret); - break; - } - mutex_lock(&pdata->cdc_int_mclk0_mutex); - if ((!atomic_read(&pdata->int_mclk0_rsc_ref)) && - (!atomic_read(&pdata->int_mclk0_enabled))) { - pdata->digital_cdc_core_clk.enable = 1; - ret = afe_set_lpass_clock_v2( - AFE_PORT_ID_INT0_MI2S_RX, - &pdata->digital_cdc_core_clk); - if (ret < 0) { - pr_err("%s: failed to enable the MCLK: %d\n", - __func__, ret); - mutex_unlock(&pdata->cdc_int_mclk0_mutex); - ret = msm_cdc_pinctrl_select_sleep_state( - pdata->pdm_gpio_p); - if (ret) - pr_err("%s: failed to disable the pri gpios: %d\n", - __func__, ret); - break; - } - atomic_set(&pdata->int_mclk0_enabled, true); - } - mutex_unlock(&pdata->cdc_int_mclk0_mutex); - atomic_inc(&pdata->int_mclk0_rsc_ref); - msm_anlg_cdc_mclk_enable(codec, 1, true); - break; - case 0: - if (atomic_read(&pdata->int_mclk0_rsc_ref) <= 0) - break; - msm_anlg_cdc_mclk_enable(codec, 0, true); - mutex_lock(&pdata->cdc_int_mclk0_mutex); - if ((!atomic_dec_return(&pdata->int_mclk0_rsc_ref)) && - (atomic_read(&pdata->int_mclk0_enabled))) { - pdata->digital_cdc_core_clk.enable = 0; - ret = afe_set_lpass_clock_v2( - AFE_PORT_ID_INT0_MI2S_RX, - &pdata->digital_cdc_core_clk); - if (ret < 0) { - pr_err("%s: failed to disable the CCLK: %d\n", - __func__, ret); - mutex_unlock(&pdata->cdc_int_mclk0_mutex); - break; - } - atomic_set(&pdata->int_mclk0_enabled, false); - } - mutex_unlock(&pdata->cdc_int_mclk0_mutex); - ret = msm_cdc_pinctrl_select_sleep_state(pdata->pdm_gpio_p); - if (ret) - pr_err("%s: failed to disable the pri gpios: %d\n", - __func__, ret); - break; - default: - pr_err("%s: Unexpected input value\n", __func__); - break; - } - return ret; -} - -static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - /* - * Slimbus_7_Rx/Tx sample rate values should always be in sync (same) - * when used for BT_SCO use case. Return either Rx or Tx sample rate - * value. - */ - switch (bt_fm_cfg[BT_SLIM7].sample_rate) { - case SAMPLING_RATE_48KHZ: - ucontrol->value.integer.value[0] = 2; - break; - case SAMPLING_RATE_16KHZ: - ucontrol->value.integer.value[0] = 1; - break; - case SAMPLING_RATE_8KHZ: - default: - ucontrol->value.integer.value[0] = 0; - break; - } - pr_debug("%s: sample rate = %d", __func__, - bt_fm_cfg[BT_SLIM7].sample_rate); - - return 0; -} - -static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - switch (ucontrol->value.integer.value[0]) { - case 1: - bt_fm_cfg[BT_SLIM7].sample_rate = SAMPLING_RATE_16KHZ; - break; - case 2: - bt_fm_cfg[BT_SLIM7].sample_rate = SAMPLING_RATE_48KHZ; - break; - case 0: - default: - bt_fm_cfg[BT_SLIM7].sample_rate = SAMPLING_RATE_8KHZ; - break; - } - pr_debug("%s: sample rates: slim7_rx = %d, value = %d\n", - __func__, - bt_fm_cfg[BT_SLIM7].sample_rate, - ucontrol->value.enumerated.item[0]); - - return 0; -} - -static const struct snd_kcontrol_new msm_snd_controls[] = { - SOC_ENUM_EXT("INT0_MI2S_RX Format", int0_mi2s_rx_format, - int_mi2s_bit_format_get, int_mi2s_bit_format_put), - SOC_ENUM_EXT("INT2_MI2S_TX Format", int2_mi2s_tx_format, - int_mi2s_bit_format_get, int_mi2s_bit_format_put), - SOC_ENUM_EXT("INT3_MI2S_TX Format", int3_mi2s_tx_format, - int_mi2s_bit_format_get, int_mi2s_bit_format_put), - SOC_ENUM_EXT("INT0_MI2S_RX SampleRate", int0_mi2s_rx_sample_rate, - int_mi2s_sample_rate_get, - int_mi2s_sample_rate_put), - SOC_ENUM_EXT("INT2_MI2S_TX SampleRate", int2_mi2s_tx_sample_rate, - int_mi2s_sample_rate_get, - int_mi2s_sample_rate_put), - SOC_ENUM_EXT("INT3_MI2S_TX SampleRate", int3_mi2s_tx_sample_rate, - int_mi2s_sample_rate_get, - int_mi2s_sample_rate_put), - SOC_ENUM_EXT("INT0_MI2S_RX SampleRate", int0_mi2s_rx_sample_rate, - int_mi2s_sample_rate_get, - int_mi2s_sample_rate_put), - SOC_ENUM_EXT("INT2_MI2S_TX SampleRate", int2_mi2s_tx_sample_rate, - int_mi2s_sample_rate_get, - int_mi2s_sample_rate_put), - SOC_ENUM_EXT("INT3_MI2S_TX SampleRate", int3_mi2s_tx_sample_rate, - int_mi2s_sample_rate_get, - int_mi2s_sample_rate_put), - SOC_ENUM_EXT("INT0_MI2S_RX Channels", int0_mi2s_rx_chs, - int_mi2s_ch_get, int_mi2s_ch_put), - SOC_ENUM_EXT("INT2_MI2S_TX Channels", int2_mi2s_tx_chs, - int_mi2s_ch_get, int_mi2s_ch_put), - SOC_ENUM_EXT("INT3_MI2S_TX Channels", int3_mi2s_tx_chs, - int_mi2s_ch_get, int_mi2s_ch_put), - SOC_ENUM_EXT("Loopback MCLK", loopback_mclk_en, - loopback_mclk_get, loopback_mclk_put), - SOC_ENUM_EXT("BT SampleRate", bt_sample_rate, - msm_bt_sample_rate_get, - msm_bt_sample_rate_put), -}; - -static const struct snd_kcontrol_new msm_sdw_controls[] = { - SOC_ENUM_EXT("INT4_MI2S_RX Format", int4_mi2s_rx_format, - int_mi2s_bit_format_get, int_mi2s_bit_format_put), - SOC_ENUM_EXT("INT4_MI2S_RX SampleRate", int4_mi2s_rx_sample_rate, - int_mi2s_sample_rate_get, - int_mi2s_sample_rate_put), - SOC_ENUM_EXT("INT4_MI2S_RX SampleRate", int4_mi2s_rx_sample_rate, - int_mi2s_sample_rate_get, - int_mi2s_sample_rate_put), - SOC_ENUM_EXT("INT4_MI2S_RX Channels", int4_mi2s_rx_chs, - int_mi2s_ch_get, int_mi2s_ch_put), - SOC_ENUM_EXT("VI_FEED_TX Channels", int5_mi2s_tx_chs, - msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put), -}; - -static int msm_dmic_event(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, int event) -{ - struct msm_asoc_mach_data *pdata = NULL; - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - int ret = 0; - - pdata = snd_soc_card_get_drvdata(codec->component.card); - pr_debug("%s: event = %d\n", __func__, event); - switch (event) { - case SND_SOC_DAPM_PRE_PMU: - ret = msm_cdc_pinctrl_select_active_state(pdata->dmic_gpio_p); - if (ret < 0) { - pr_err("%s: gpio set cannot be activated %sd", - __func__, "dmic_gpio"); - return ret; - } - break; - case SND_SOC_DAPM_POST_PMD: - ret = msm_cdc_pinctrl_select_sleep_state(pdata->dmic_gpio_p); - if (ret < 0) { - pr_err("%s: gpio set cannot be de-activated %sd", - __func__, "dmic_gpio"); - return ret; - } - break; - default: - pr_err("%s: invalid DAPM event %d\n", __func__, event); - return -EINVAL; - } - return 0; -} - -static int msm_int_mclk0_event(struct snd_soc_dapm_widget *w, - struct snd_kcontrol *kcontrol, int event) -{ - struct msm_asoc_mach_data *pdata = NULL; - struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - int ret = 0; - - pdata = snd_soc_card_get_drvdata(codec->component.card); - pr_debug("%s: event = %d\n", __func__, event); - switch (event) { - case SND_SOC_DAPM_POST_PMD: - pr_debug("%s: mclk_res_ref = %d\n", - __func__, atomic_read(&pdata->int_mclk0_rsc_ref)); - ret = msm_cdc_pinctrl_select_sleep_state(pdata->pdm_gpio_p); - if (ret < 0) { - pr_err("%s: gpio set cannot be de-activated %sd", - __func__, "int_pdm"); - return ret; - } - if (atomic_read(&pdata->int_mclk0_rsc_ref) == 0) { - pr_debug("%s: disabling MCLK\n", __func__); - /* disable the codec mclk config*/ - msm_anlg_cdc_mclk_enable(codec, 0, true); - msm_int_enable_dig_cdc_clk(codec, 0, true); - } - break; - default: - pr_err("%s: invalid DAPM event %d\n", __func__, event); - return -EINVAL; - } - return 0; -} - -static int int_mi2s_get_port_id(int be_id) -{ - int afe_port_id; - - switch (be_id) { - case MSM_BACKEND_DAI_INT0_MI2S_RX: - afe_port_id = AFE_PORT_ID_INT0_MI2S_RX; - break; - case MSM_BACKEND_DAI_INT2_MI2S_TX: - afe_port_id = AFE_PORT_ID_INT2_MI2S_TX; - break; - case MSM_BACKEND_DAI_INT3_MI2S_TX: - afe_port_id = AFE_PORT_ID_INT3_MI2S_TX; - break; - case MSM_BACKEND_DAI_INT4_MI2S_RX: - afe_port_id = AFE_PORT_ID_INT4_MI2S_RX; - break; - case MSM_BACKEND_DAI_INT5_MI2S_TX: - afe_port_id = AFE_PORT_ID_INT5_MI2S_TX; - break; - default: - pr_err("%s: Invalid be_id: %d\n", __func__, be_id); - afe_port_id = -EINVAL; - } - - return afe_port_id; -} - -static int int_mi2s_get_index(int port_id) -{ - int index; - - switch (port_id) { - case AFE_PORT_ID_INT0_MI2S_RX: - index = INT0_MI2S; - break; - case AFE_PORT_ID_INT2_MI2S_TX: - index = INT2_MI2S; - break; - case AFE_PORT_ID_INT3_MI2S_TX: - index = INT3_MI2S; - break; - case AFE_PORT_ID_INT4_MI2S_RX: - index = INT4_MI2S; - break; - case AFE_PORT_ID_INT5_MI2S_TX: - index = INT5_MI2S; - break; - default: - pr_err("%s: Invalid port_id: %d\n", __func__, port_id); - index = -EINVAL; - } - - return index; -} - -static u32 get_int_mi2s_bits_per_sample(u32 bit_format) -{ - u32 bit_per_sample; - - switch (bit_format) { - case SNDRV_PCM_FORMAT_S24_3LE: - case SNDRV_PCM_FORMAT_S24_LE: - bit_per_sample = 32; - break; - case SNDRV_PCM_FORMAT_S16_LE: - default: - bit_per_sample = 16; - break; - } - - return bit_per_sample; -} - -static void update_int_mi2s_clk_val(int idx, int stream) -{ - u32 bit_per_sample; - - bit_per_sample = - get_int_mi2s_bits_per_sample(int_mi2s_cfg[idx].bit_format); - int_mi2s_clk[idx].clk_freq_in_hz = - (int_mi2s_cfg[idx].sample_rate * int_mi2s_cfg[idx].channels - * bit_per_sample); -} - -static int int_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable) -{ - int ret = 0; - struct snd_soc_pcm_runtime *rtd = substream->private_data; - int port_id = 0; - int index; - - port_id = int_mi2s_get_port_id(rtd->dai_link->be_id); - if (IS_ERR_VALUE(port_id)) { - dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__); - ret = port_id; - goto done; - } - index = int_mi2s_get_index(port_id); - if (index < 0) { - dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__); - ret = port_id; - goto done; - } - if (enable) { - update_int_mi2s_clk_val(index, substream->stream); - dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__, - int_mi2s_clk[index].clk_freq_in_hz); - } - - int_mi2s_clk[index].enable = enable; - ret = afe_set_lpass_clock_v2(port_id, - &int_mi2s_clk[index]); - if (ret < 0) { - dev_err(rtd->card->dev, - "%s: afe lpass clock failed for port 0x%x , err:%d\n", - __func__, port_id, ret); - goto done; - } - -done: - return ret; -} - -static int msm_sdw_mi2s_snd_startup(struct snd_pcm_substream *substream) -{ - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct snd_soc_dai *cpu_dai = rtd->cpu_dai; - int ret = 0; - - pr_debug("%s(): substream = %s stream = %d\n", __func__, - substream->name, substream->stream); - - ret = int_mi2s_set_sclk(substream, true); - if (ret < 0) { - pr_err("%s: failed to enable sclk %d\n", - __func__, ret); - return ret; - } - ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBS_CFS); - if (ret < 0) - pr_err("%s: set fmt cpu dai failed; ret=%d\n", __func__, ret); - - return ret; -} - -static void msm_sdw_mi2s_snd_shutdown(struct snd_pcm_substream *substream) -{ - int ret; - - pr_debug("%s(): substream = %s stream = %d\n", __func__, - substream->name, substream->stream); - - ret = int_mi2s_set_sclk(substream, false); - if (ret < 0) - pr_err("%s:clock disable failed; ret=%d\n", __func__, - ret); -} - -static int msm_int_mi2s_snd_startup(struct snd_pcm_substream *substream) -{ - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct snd_soc_dai *cpu_dai = rtd->cpu_dai; - struct snd_soc_codec *codec = rtd->codec_dais[ANA_CDC]->codec; - int ret = 0; - struct msm_asoc_mach_data *pdata = NULL; - - pdata = snd_soc_card_get_drvdata(codec->component.card); - pr_debug("%s(): substream = %s stream = %d\n", __func__, - substream->name, substream->stream); - - ret = int_mi2s_set_sclk(substream, true); - if (ret < 0) { - pr_err("%s: failed to enable sclk %d\n", - __func__, ret); - return ret; - } - ret = msm_int_enable_dig_cdc_clk(codec, 1, true); - if (ret < 0) { - pr_err("failed to enable mclk\n"); - return ret; - } - /* Enable the codec mclk config */ - ret = msm_cdc_pinctrl_select_active_state(pdata->pdm_gpio_p); - if (ret < 0) { - pr_err("%s: gpio set cannot be activated %s\n", - __func__, "int_pdm"); - return ret; - } - msm_anlg_cdc_mclk_enable(codec, 1, true); - ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBS_CFS); - if (ret < 0) - pr_err("%s: set fmt cpu dai failed; ret=%d\n", __func__, ret); - - return ret; -} - -static void msm_int_mi2s_snd_shutdown(struct snd_pcm_substream *substream) -{ - int ret; - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct snd_soc_card *card = rtd->card; - struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); - - pr_debug("%s(): substream = %s stream = %d\n", __func__, - substream->name, substream->stream); - - ret = int_mi2s_set_sclk(substream, false); - if (ret < 0) - pr_err("%s:clock disable failed; ret=%d\n", __func__, - ret); - if (atomic_read(&pdata->int_mclk0_rsc_ref) > 0) { - atomic_dec(&pdata->int_mclk0_rsc_ref); - pr_debug("%s: decrementing mclk_res_ref %d\n", - __func__, - atomic_read(&pdata->int_mclk0_rsc_ref)); - } -} - -static void *def_msm_int_wcd_mbhc_cal(void) -{ - void *msm_int_wcd_cal; - struct wcd_mbhc_btn_detect_cfg *btn_cfg; - u16 *btn_low, *btn_high; - - msm_int_wcd_cal = kzalloc(WCD_MBHC_CAL_SIZE(WCD_MBHC_DEF_BUTTONS, - WCD_MBHC_DEF_RLOADS), GFP_KERNEL); - if (!msm_int_wcd_cal) - return NULL; - -#define S(X, Y) ((WCD_MBHC_CAL_PLUG_TYPE_PTR(msm_int_wcd_cal)->X) = (Y)) - S(v_hs_max, 1500); -#undef S -#define S(X, Y) ((WCD_MBHC_CAL_BTN_DET_PTR(msm_int_wcd_cal)->X) = (Y)) - S(num_btn, WCD_MBHC_DEF_BUTTONS); -#undef S - - - btn_cfg = WCD_MBHC_CAL_BTN_DET_PTR(msm_int_wcd_cal); - btn_low = btn_cfg->_v_btn_low; - btn_high = ((void *)&btn_cfg->_v_btn_low) + - (sizeof(btn_cfg->_v_btn_low[0]) * btn_cfg->num_btn); - - /* - * In SW we are maintaining two sets of threshold register - * one for current source and another for Micbias. - * all btn_low corresponds to threshold for current source - * all bt_high corresponds to threshold for Micbias - * Below thresholds are based on following resistances - * 0-70 == Button 0 - * 110-180 == Button 1 - * 210-290 == Button 2 - * 360-680 == Button 3 - */ - btn_low[0] = 75; - btn_high[0] = 75; - btn_low[1] = 150; - btn_high[1] = 150; - btn_low[2] = 225; - btn_high[2] = 225; - btn_low[3] = 450; - btn_high[3] = 450; - btn_low[4] = 500; - btn_high[4] = 500; - - return msm_int_wcd_cal; -} - -static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd) -{ - struct snd_soc_codec *dig_cdc = rtd->codec_dais[DIG_CDC]->codec; - struct snd_soc_codec *ana_cdc = rtd->codec_dais[ANA_CDC]->codec; - struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(ana_cdc); - struct snd_soc_dai *cpu_dai = rtd->cpu_dai; - struct snd_soc_pcm_runtime *rtd_aux = rtd->card->rtd_aux; - struct snd_card *card; - struct snd_info_entry *entry; - int ret = -ENOMEM; - - pr_debug("%s(),dev_name%s\n", __func__, dev_name(cpu_dai->dev)); - - snd_soc_add_codec_controls(ana_cdc, msm_snd_controls, - ARRAY_SIZE(msm_snd_controls)); - - snd_soc_dapm_new_controls(dapm, msm_int_dapm_widgets, - ARRAY_SIZE(msm_int_dapm_widgets)); - - snd_soc_dapm_ignore_suspend(dapm, "Handset Mic"); - snd_soc_dapm_ignore_suspend(dapm, "Headset Mic"); - snd_soc_dapm_ignore_suspend(dapm, "Secondary Mic"); - snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1"); - snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2"); - - snd_soc_dapm_ignore_suspend(dapm, "EAR"); - snd_soc_dapm_ignore_suspend(dapm, "HEADPHONE"); - snd_soc_dapm_ignore_suspend(dapm, "SPK_OUT"); - snd_soc_dapm_ignore_suspend(dapm, "AMIC1"); - snd_soc_dapm_ignore_suspend(dapm, "AMIC2"); - snd_soc_dapm_ignore_suspend(dapm, "AMIC3"); - snd_soc_dapm_ignore_suspend(dapm, "DMIC1"); - snd_soc_dapm_ignore_suspend(dapm, "DMIC2"); - snd_soc_dapm_ignore_suspend(dapm, "DMIC3"); - snd_soc_dapm_ignore_suspend(dapm, "DMIC4"); - - snd_soc_dapm_sync(dapm); - - /* - * Send speaker configuration only for WSA8810. - * Defalut configuration is for WSA8815. - */ - if (rtd_aux && rtd_aux->component) - if (!strcmp(rtd_aux->component->name, WSA8810_NAME_1) || - !strcmp(rtd_aux->component->name, WSA8810_NAME_2)) { - msm_sdw_set_spkr_mode(rtd->codec, SPKR_MODE_1); - msm_sdw_set_spkr_gain_offset(rtd->codec, - RX_GAIN_OFFSET_M1P5_DB); - } - msm_anlg_cdc_spk_ext_pa_cb(enable_spk_ext_pa, ana_cdc); - msm_dig_cdc_hph_comp_cb(msm_config_hph_compander_gpio, dig_cdc); - - mbhc_cfg_ptr->calibration = def_msm_int_wcd_mbhc_cal(); - if (mbhc_cfg_ptr->calibration) { - ret = msm_anlg_cdc_hs_detect(ana_cdc, mbhc_cfg_ptr); - if (ret) { - pr_err("%s: msm_anlg_cdc_hs_detect failed\n", __func__); - kfree(mbhc_cfg_ptr->calibration); - return ret; - } - } - card = rtd->card->snd_card; - entry = snd_register_module_info(card->module, "codecs", - card->proc_root); - if (!entry) { - pr_debug("%s: Cannot create codecs module entry\n", - __func__); - msm_dig_codec_root = NULL; - goto done; - } - msm_dig_codec_root = entry; - msm_dig_codec_info_create_codec_entry(msm_dig_codec_root, dig_cdc); - entry = snd_register_module_info(card->module, "codecs", - card->proc_root); - if (!entry) { - pr_debug("%s: Cannot create codecs module entry\n", - __func__); - pmic_analog_codec_root = NULL; - goto done; - } - pmic_analog_codec_root = entry; - msm_anlg_codec_info_create_codec_entry(pmic_analog_codec_root, ana_cdc); -done: - return 0; -} - -static int msm_sdw_audrx_init(struct snd_soc_pcm_runtime *rtd) -{ - struct snd_soc_codec *codec = rtd->codec; - struct snd_soc_dapm_context *dapm = - snd_soc_codec_get_dapm(codec); - struct snd_card *card; - struct snd_info_entry *entry; - - snd_soc_add_codec_controls(codec, msm_sdw_controls, - ARRAY_SIZE(msm_sdw_controls)); - - snd_soc_dapm_ignore_suspend(dapm, "AIF1_SDW Playback"); - snd_soc_dapm_ignore_suspend(dapm, "VIfeed_SDW"); - snd_soc_dapm_ignore_suspend(dapm, "SPK1 OUT"); - snd_soc_dapm_ignore_suspend(dapm, "SPK2 OUT"); - snd_soc_dapm_ignore_suspend(dapm, "AIF1_SDW VI"); - snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_SDW"); - - snd_soc_dapm_sync(dapm); - msm_sdw_gpio_cb(msm_config_sdw_gpio, codec); - card = rtd->card->snd_card; - entry = snd_register_module_info(card->module, "codecs", - card->proc_root); - if (!entry) { - pr_debug("%s: Cannot create codecs module entry\n", - __func__); - msm_sdw_codec_root = NULL; - goto done; - } - msm_sdw_codec_root = entry; - msm_sdw_codec_info_create_codec_entry(msm_sdw_codec_root, codec); -done: - return 0; -} - -static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd) -{ - unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158}; - unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161}; - struct snd_soc_dai *codec_dai = rtd->codec_dai; - - return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch), - tx_ch, ARRAY_SIZE(rx_ch), rx_ch); -} - -static int msm_wcn_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params) -{ - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct snd_soc_dai *codec_dai = rtd->codec_dai; - struct snd_soc_dai *cpu_dai = rtd->cpu_dai; - struct snd_soc_dai_link *dai_link = rtd->dai_link; - u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX]; - u32 rx_ch_cnt = 0, tx_ch_cnt = 0; - int ret; - - dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__, - codec_dai->name, codec_dai->id); - ret = snd_soc_dai_get_channel_map(codec_dai, - &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch); - if (ret) { - dev_err(rtd->dev, - "%s: failed to get BTFM codec chan map\n, err:%d\n", - __func__, ret); - goto exit; - } - - dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) be_id %d\n", - __func__, tx_ch_cnt, dai_link->be_id); - - ret = snd_soc_dai_set_channel_map(cpu_dai, - tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch); - if (ret) - dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n", - __func__, ret); - -exit: - return ret; -} - -static unsigned int tdm_param_set_slot_mask(u16 port_id, int slot_width, - int slots) -{ - unsigned int slot_mask = 0; - int i, j; - unsigned int *slot_offset; - - for (i = TDM_0; i < TDM_PORT_MAX; i++) { - slot_offset = tdm_slot_offset[i]; - - for (j = 0; j < TDM_SLOT_OFFSET_MAX; j++) { - if (slot_offset[j] != AFE_SLOT_MAPPING_OFFSET_INVALID) - slot_mask |= - (1 << ((slot_offset[j] * 8) / slot_width)); - else - break; - } - } - - return slot_mask; -} - -static int msm_tdm_snd_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params) -{ - struct snd_soc_pcm_runtime *rtd = substream->private_data; - struct snd_soc_dai *cpu_dai = rtd->cpu_dai; - int ret = 0; - int channels, slot_width, slots; - unsigned int slot_mask; - unsigned int *slot_offset; - int offset_channels = 0; - int i; - - pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id); - - channels = params_channels(params); - switch (channels) { - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: - case 8: - switch (params_format(params)) { - case SNDRV_PCM_FORMAT_S32_LE: - case SNDRV_PCM_FORMAT_S24_LE: - case SNDRV_PCM_FORMAT_S16_LE: - /* - * up to 8 channels HW config should - * use 32 bit slot width for max support of - * stream bit width. (slot_width > bit_width) - */ - slot_width = 32; - break; - default: - pr_err("%s: invalid param format 0x%x\n", - __func__, params_format(params)); - return -EINVAL; - } - slots = 8; - slot_mask = tdm_param_set_slot_mask(cpu_dai->id, - slot_width, - slots); - if (!slot_mask) { - pr_err("%s: invalid slot_mask 0x%x\n", - __func__, slot_mask); - return -EINVAL; - } - break; - default: - pr_err("%s: invalid param channels %d\n", - __func__, channels); - return -EINVAL; - } - /* currently only supporting TDM_RX_0 and TDM_TX_0 */ - switch (cpu_dai->id) { - case AFE_PORT_ID_PRIMARY_TDM_RX: - case AFE_PORT_ID_SECONDARY_TDM_RX: - case AFE_PORT_ID_TERTIARY_TDM_RX: - case AFE_PORT_ID_QUATERNARY_TDM_RX: - case AFE_PORT_ID_PRIMARY_TDM_TX: - case AFE_PORT_ID_SECONDARY_TDM_TX: - case AFE_PORT_ID_TERTIARY_TDM_TX: - case AFE_PORT_ID_QUATERNARY_TDM_TX: - slot_offset = tdm_slot_offset[TDM_0]; - break; - default: - pr_err("%s: dai id 0x%x not supported\n", - __func__, cpu_dai->id); - return -EINVAL; - } - - for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) { - if (slot_offset[i] != AFE_SLOT_MAPPING_OFFSET_INVALID) - offset_channels++; - else - break; - } - - if (offset_channels == 0) { - pr_err("%s: slot offset not supported, offset_channels %d\n", - __func__, offset_channels); - return -EINVAL; - } - - if (channels > offset_channels) { - pr_err("%s: channels %d exceed offset_channels %d\n", - __func__, channels, offset_channels); - return -EINVAL; - } - - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask, - slots, slot_width); - if (ret < 0) { - pr_err("%s: failed to set tdm slot, err:%d\n", - __func__, ret); - goto end; - } - - ret = snd_soc_dai_set_channel_map(cpu_dai, 0, NULL, - channels, slot_offset); - if (ret < 0) { - pr_err("%s: failed to set channel map, err:%d\n", - __func__, ret); - goto end; - } - } else { - ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0, - slots, slot_width); - if (ret < 0) { - pr_err("%s: failed to set tdm slot, err:%d\n", - __func__, ret); - goto end; - } - - ret = snd_soc_dai_set_channel_map(cpu_dai, channels, - slot_offset, 0, NULL); - if (ret < 0) { - pr_err("%s: failed to set channel map, err:%d\n", - __func__, ret); - goto end; - } - } -end: - return ret; -} - -static struct snd_soc_ops msm_tdm_be_ops = { - .hw_params = msm_tdm_snd_hw_params -}; - -static struct snd_soc_ops msm_wcn_ops = { - .hw_params = msm_wcn_hw_params, -}; - -static struct snd_soc_ops msm_mi2s_be_ops = { - .startup = msm_mi2s_snd_startup, - .shutdown = msm_mi2s_snd_shutdown, -}; - -static struct snd_soc_ops msm_aux_pcm_be_ops = { - .startup = msm_aux_pcm_snd_startup, - .shutdown = msm_aux_pcm_snd_shutdown, -}; - -static struct snd_soc_ops msm_int_mi2s_be_ops = { - .startup = msm_int_mi2s_snd_startup, - .shutdown = msm_int_mi2s_snd_shutdown, -}; - -static struct snd_soc_ops msm_sdw_mi2s_be_ops = { - .startup = msm_sdw_mi2s_snd_startup, - .shutdown = msm_sdw_mi2s_snd_shutdown, -}; - -struct snd_soc_dai_link_component dlc_rx1[] = { - { - .of_node = NULL, - .dai_name = "msm_dig_cdc_dai_rx1", - }, - { - .of_node = NULL, - .dai_name = "msm_anlg_cdc_i2s_rx1", - }, -}; - -struct snd_soc_dai_link_component dlc_tx1[] = { - { - .of_node = NULL, - .dai_name = "msm_dig_cdc_dai_tx1", - }, - { - .of_node = NULL, - .dai_name = "msm_anlg_cdc_i2s_tx1", - }, -}; - -struct snd_soc_dai_link_component dlc_tx2[] = { - { - .of_node = NULL, - .dai_name = "msm_dig_cdc_dai_tx2", - }, - { - .of_node = NULL, - .dai_name = "msm_anlg_cdc_i2s_tx2", - }, -}; - -/* Digital audio interface glue - connects codec <---> CPU */ -static struct snd_soc_dai_link msm_int_dai[] = { - /* FrontEnd DAI Links */ - {/* hw:x,0 */ - .name = MSM_DAILINK_NAME(Media1), - .stream_name = "MultiMedia1", - .cpu_dai_name = "MultiMedia1", - .platform_name = "msm-pcm-dsp.0", - .dynamic = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - .dpcm_playback = 1, - .dpcm_capture = 1, - /* this dai link has playback support */ - .ignore_pmdown_time = 1, - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA1 - }, - {/* hw:x,1 */ - .name = MSM_DAILINK_NAME(Media2), - .stream_name = "MultiMedia2", - .cpu_dai_name = "MultiMedia2", - .platform_name = "msm-pcm-dsp.0", - .dynamic = 1, - .dpcm_playback = 1, - .dpcm_capture = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .ignore_suspend = 1, - /* this dai link has playback support */ - .ignore_pmdown_time = 1, - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA2, - }, - {/* hw:x,2 */ - .name = "VoiceMMode1", - .stream_name = "VoiceMMode1", - .cpu_dai_name = "VoiceMMode1", - .platform_name = "msm-pcm-voice", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .be_id = MSM_FRONTEND_DAI_VOICEMMODE1, - }, - {/* hw:x,3 */ - .name = "MSM VoIP", - .stream_name = "VoIP", - .cpu_dai_name = "VoIP", - .platform_name = "msm-voip-dsp", - .dynamic = 1, - .dpcm_playback = 1, - .dpcm_capture = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - /* this dai link has playback support */ - .ignore_pmdown_time = 1, - .be_id = MSM_FRONTEND_DAI_VOIP, - }, - {/* hw:x,4 */ - .name = MSM_DAILINK_NAME(ULL), - .stream_name = "ULL", - .cpu_dai_name = "MultiMedia3", - .platform_name = "msm-pcm-dsp.2", - .dynamic = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - /* this dai link has playback support */ - .ignore_pmdown_time = 1, - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA3, - }, - /* Hostless PCM purpose */ - {/* hw:x,5 */ - .name = "INT4 MI2S_RX Hostless", - .stream_name = "INT4 MI2S_RX Hostless", - .cpu_dai_name = "INT4_MI2S_RX_HOSTLESS", - .platform_name = "msm-pcm-hostless", - .dynamic = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - /* this dailink has playback support */ - .ignore_pmdown_time = 1, - /* This dainlink has MI2S support */ - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - }, - {/* hw:x,6 */ - .name = "MSM AFE-PCM RX", - .stream_name = "AFE-PROXY RX", - .cpu_dai_name = "msm-dai-q6-dev.241", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .platform_name = "msm-pcm-afe", - .ignore_suspend = 1, - /* this dai link has playback support */ - .ignore_pmdown_time = 1, - }, - {/* hw:x,7 */ - .name = "MSM AFE-PCM TX", - .stream_name = "AFE-PROXY TX", - .cpu_dai_name = "msm-dai-q6-dev.240", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .platform_name = "msm-pcm-afe", - .ignore_suspend = 1, - }, - {/* hw:x,8 */ - .name = MSM_DAILINK_NAME(Compress1), - .stream_name = "Compress1", - .cpu_dai_name = "MultiMedia4", - .platform_name = "msm-compress-dsp", - .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS, - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - /* this dai link has playback support */ - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA4, - }, - {/* hw:x,9*/ - .name = "AUXPCM Hostless", - .stream_name = "AUXPCM Hostless", - .cpu_dai_name = "AUXPCM_HOSTLESS", - .platform_name = "msm-pcm-hostless", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - /* this dai link has playback support */ - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - }, - {/* hw:x,10 */ - .name = "SLIMBUS_1 Hostless", - .stream_name = "SLIMBUS_1 Hostless", - .cpu_dai_name = "SLIMBUS1_HOSTLESS", - .platform_name = "msm-pcm-hostless", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, /* dai link has playback support */ - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - }, - {/* hw:x,11 */ - .name = "INT3 MI2S_TX Hostless", - .stream_name = "INT3 MI2S_TX Hostless", - .cpu_dai_name = "INT3_MI2S_TX_HOSTLESS", - .platform_name = "msm-pcm-hostless", - .dynamic = 1, - .dpcm_capture = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - }, - {/* hw:x,12 */ - .name = "SLIMBUS_7 Hostless", - .stream_name = "SLIMBUS_7 Hostless", - .cpu_dai_name = "SLIMBUS7_HOSTLESS", - .platform_name = "msm-pcm-hostless", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, /* dai link has playback support */ - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - }, - {/* hw:x,13 */ - .name = MSM_DAILINK_NAME(LowLatency), - .stream_name = "MultiMedia5", - .cpu_dai_name = "MultiMedia5", - .platform_name = "msm-pcm-dsp.1", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .ignore_suspend = 1, - /* this dai link has playback support */ - .ignore_pmdown_time = 1, - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA5, - }, - /* LSM FE */ - {/* hw:x,14 */ - .name = "Listen 1 Audio Service", - .stream_name = "Listen 1 Audio Service", - .cpu_dai_name = "LSM1", - .platform_name = "msm-lsm-client", - .dynamic = 1, - .dpcm_capture = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST }, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .be_id = MSM_FRONTEND_DAI_LSM1, - }, - {/* hw:x,15 */ - .name = MSM_DAILINK_NAME(Compress2), - .stream_name = "Compress2", - .cpu_dai_name = "MultiMedia7", - .platform_name = "msm-compress-dsp", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .ignore_suspend = 1, - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA7, - }, - {/* hw:x,16 */ - .name = MSM_DAILINK_NAME(Compress3), - .stream_name = "Compress3", - .cpu_dai_name = "MultiMedia10", - .platform_name = "msm-compress-dsp", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - /* this dai link has playback support */ - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA10, - }, - {/* hw:x,17 */ - .name = MSM_DAILINK_NAME(ULL_NOIRQ), - .stream_name = "MM_NOIRQ", - .cpu_dai_name = "MultiMedia8", - .platform_name = "msm-pcm-dsp-noirq", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - /* this dai link has playback support */ - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA8, - }, - {/* hw:x,18 */ - .name = "HDMI_RX_HOSTLESS", - .stream_name = "HDMI_RX_HOSTLESS", - .cpu_dai_name = "HDMI_HOSTLESS", - .platform_name = "msm-pcm-hostless", - .dynamic = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - }, - {/* hw:x,19 */ - .name = "VoiceMMode2", - .stream_name = "VoiceMMode2", - .cpu_dai_name = "VoiceMMode2", - .platform_name = "msm-pcm-voice", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .be_id = MSM_FRONTEND_DAI_VOICEMMODE2, - }, - {/* hw:x,20 */ - .name = "Listen 2 Audio Service", - .stream_name = "Listen 2 Audio Service", - .cpu_dai_name = "LSM2", - .platform_name = "msm-lsm-client", - .dynamic = 1, - .dpcm_capture = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST }, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .be_id = MSM_FRONTEND_DAI_LSM2, - }, - {/* hw:x,21 */ - .name = "Listen 3 Audio Service", - .stream_name = "Listen 3 Audio Service", - .cpu_dai_name = "LSM3", - .platform_name = "msm-lsm-client", - .dynamic = 1, - .dpcm_capture = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST }, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .be_id = MSM_FRONTEND_DAI_LSM3, - }, - {/* hw:x,22 */ - .name = "Listen 4 Audio Service", - .stream_name = "Listen 4 Audio Service", - .cpu_dai_name = "LSM4", - .platform_name = "msm-lsm-client", - .dynamic = 1, - .dpcm_capture = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST }, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .be_id = MSM_FRONTEND_DAI_LSM4, - }, - {/* hw:x,23 */ - .name = "Listen 5 Audio Service", - .stream_name = "Listen 5 Audio Service", - .cpu_dai_name = "LSM5", - .platform_name = "msm-lsm-client", - .dynamic = 1, - .dpcm_capture = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST }, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .be_id = MSM_FRONTEND_DAI_LSM5, - }, - {/* hw:x,24 */ - .name = "Listen 6 Audio Service", - .stream_name = "Listen 6 Audio Service", - .cpu_dai_name = "LSM6", - .platform_name = "msm-lsm-client", - .dynamic = 1, - .dpcm_capture = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST }, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .be_id = MSM_FRONTEND_DAI_LSM6 - }, - {/* hw:x,25 */ - .name = "Listen 7 Audio Service", - .stream_name = "Listen 7 Audio Service", - .cpu_dai_name = "LSM7", - .platform_name = "msm-lsm-client", - .dynamic = 1, - .dpcm_capture = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST }, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .be_id = MSM_FRONTEND_DAI_LSM7, - }, - {/* hw:x,26 */ - .name = "Listen 8 Audio Service", - .stream_name = "Listen 8 Audio Service", - .cpu_dai_name = "LSM8", - .platform_name = "msm-lsm-client", - .dynamic = 1, - .dpcm_capture = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST }, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .be_id = MSM_FRONTEND_DAI_LSM8, - }, - {/* hw:x,27 */ - .name = MSM_DAILINK_NAME(Media9), - .stream_name = "MultiMedia9", - .cpu_dai_name = "MultiMedia9", - .platform_name = "msm-pcm-dsp.0", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - /* this dai link has playback support */ - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA9, - }, - {/* hw:x,28 */ - .name = MSM_DAILINK_NAME(Compress4), - .stream_name = "Compress4", - .cpu_dai_name = "MultiMedia11", - .platform_name = "msm-compress-dsp", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - /* this dai link has playback support */ - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA11, - }, - {/* hw:x,29 */ - .name = MSM_DAILINK_NAME(Compress5), - .stream_name = "Compress5", - .cpu_dai_name = "MultiMedia12", - .platform_name = "msm-compress-dsp", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - /* this dai link has playback support */ - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA12, - }, - {/* hw:x,30 */ - .name = MSM_DAILINK_NAME(Compress6), - .stream_name = "Compress6", - .cpu_dai_name = "MultiMedia13", - .platform_name = "msm-compress-dsp", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - /* this dai link has playback support */ - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA13, - }, - {/* hw:x,31 */ - .name = MSM_DAILINK_NAME(Compress7), - .stream_name = "Compress7", - .cpu_dai_name = "MultiMedia14", - .platform_name = "msm-compress-dsp", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - /* this dai link has playback support */ - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA14, - }, - {/* hw:x,32 */ - .name = MSM_DAILINK_NAME(Compress8), - .stream_name = "Compress8", - .cpu_dai_name = "MultiMedia15", - .platform_name = "msm-compress-dsp", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - /* this dai link has playback support */ - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA15, - }, - {/* hw:x,33 */ - .name = MSM_DAILINK_NAME(Compress9), - .stream_name = "Compress9", - .cpu_dai_name = "MultiMedia16", - .platform_name = "msm-compress-dsp", - .dynamic = 1, - .dpcm_capture = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - /* this dai link has playback support */ - .be_id = MSM_FRONTEND_DAI_MULTIMEDIA16, - }, - {/* hw:x,34 */ - .name = "SLIMBUS_8 Hostless", - .stream_name = "SLIMBUS8_HOSTLESS Capture", - .cpu_dai_name = "SLIMBUS8_HOSTLESS", - .platform_name = "msm-pcm-hostless", - .dynamic = 1, - .dpcm_capture = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - }, - {/* hw:x,35 */ - .name = LPASS_BE_INT5_MI2S_TX, - .stream_name = "INT5_mi2s Capture", - .cpu_dai_name = "msm-dai-q6-mi2s.12", - .platform_name = "msm-pcm-hostless", - .codec_name = "msm_sdw_codec", - .codec_dai_name = "msm_sdw_vifeedback", - .be_id = MSM_BACKEND_DAI_INT5_MI2S_TX, - .be_hw_params_fixup = int_mi2s_be_hw_params_fixup, - .ops = &msm_sdw_mi2s_be_ops, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - .dpcm_capture = 1, - .ignore_pmdown_time = 1, - }, - {/* hw:x,36 */ - .name = "Primary MI2S_RX Hostless", - .stream_name = "Primary MI2S_RX Hostless", - .cpu_dai_name = "PRI_MI2S_RX_HOSTLESS", - .platform_name = "msm-pcm-hostless", - .dynamic = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - /* this dailink has playback support */ - .ignore_pmdown_time = 1, - /* This dainlink has MI2S support */ - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - }, - {/* hw:x,37 */ - .name = "Secondary MI2S_RX Hostless", - .stream_name = "Secondary MI2S_RX Hostless", - .cpu_dai_name = "SEC_MI2S_RX_HOSTLESS", - .platform_name = "msm-pcm-hostless", - .dynamic = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - /* this dailink has playback support */ - .ignore_pmdown_time = 1, - /* This dainlink has MI2S support */ - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - }, - {/* hw:x,38 */ - .name = "Tertiary MI2S_RX Hostless", - .stream_name = "Tertiary MI2S_RX Hostless", - .cpu_dai_name = "TERT_MI2S_RX_HOSTLESS", - .platform_name = "msm-pcm-hostless", - .dynamic = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - /* this dailink has playback support */ - .ignore_pmdown_time = 1, - /* This dainlink has MI2S support */ - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - }, - {/* hw:x,39 */ - .name = "INT0 MI2S_RX Hostless", - .stream_name = "INT0 MI2S_RX Hostless", - .cpu_dai_name = "INT0_MI2S_RX_HOSTLESS", - .platform_name = "msm-pcm-hostless", - .dynamic = 1, - .dpcm_playback = 1, - .trigger = {SND_SOC_DPCM_TRIGGER_POST, - SND_SOC_DPCM_TRIGGER_POST}, - .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, - .ignore_suspend = 1, - /* this dailink has playback support */ - .ignore_pmdown_time = 1, - /* This dainlink has MI2S support */ - .codec_dai_name = "snd-soc-dummy-dai", - .codec_name = "snd-soc-dummy", - }, - /* Backend I2S DAI Links */ - { - .name = LPASS_BE_INT0_MI2S_RX, - .stream_name = "INT0 MI2S Playback", - .cpu_dai_name = "msm-dai-q6-mi2s.7", - .platform_name = "msm-pcm-routing", - .codecs = dlc_rx1, - .num_codecs = CODECS_MAX, - .no_pcm = 1, - .dpcm_playback = 1, - .async_ops = ASYNC_DPCM_SND_SOC_PREPARE | - ASYNC_DPCM_SND_SOC_HW_PARAMS, - .be_id = MSM_BACKEND_DAI_INT0_MI2S_RX, - .init = &msm_audrx_init, - .be_hw_params_fixup = int_mi2s_be_hw_params_fixup, - .ops = &msm_int_mi2s_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_INT3_MI2S_TX, - .stream_name = "INT3 MI2S Capture", - .cpu_dai_name = "msm-dai-q6-mi2s.10", - .platform_name = "msm-pcm-routing", - .codecs = dlc_tx1, - .num_codecs = CODECS_MAX, - .no_pcm = 1, - .dpcm_capture = 1, - .async_ops = ASYNC_DPCM_SND_SOC_PREPARE | - ASYNC_DPCM_SND_SOC_HW_PARAMS, - .be_id = MSM_BACKEND_DAI_INT3_MI2S_TX, - .be_hw_params_fixup = msm_be_hw_params_fixup, - .ops = &msm_int_mi2s_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_INT4_MI2S_RX, - .stream_name = "INT4 MI2S Playback", - .cpu_dai_name = "msm-dai-q6-mi2s.11", - .platform_name = "msm-pcm-routing", - .codec_name = "msm_sdw_codec", - .codec_dai_name = "msm_sdw_i2s_rx1", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_INT4_MI2S_RX, - .init = &msm_sdw_audrx_init, - .be_hw_params_fixup = int_mi2s_be_hw_params_fixup, - .ops = &msm_sdw_mi2s_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_INT2_MI2S_TX, - .stream_name = "INT2 MI2S Capture", - .cpu_dai_name = "msm-dai-q6-mi2s.9", - .platform_name = "msm-pcm-routing", - .codecs = dlc_tx2, - .num_codecs = CODECS_MAX, - .no_pcm = 1, - .dpcm_capture = 1, - .async_ops = ASYNC_DPCM_SND_SOC_PREPARE | - ASYNC_DPCM_SND_SOC_HW_PARAMS, - .be_id = MSM_BACKEND_DAI_INT2_MI2S_TX, - .be_hw_params_fixup = int_mi2s_be_hw_params_fixup, - .ops = &msm_int_mi2s_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_AFE_PCM_RX, - .stream_name = "AFE Playback", - .cpu_dai_name = "msm-dai-q6-dev.224", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_AFE_PCM_RX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - /* this dainlink has playback support */ - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_AFE_PCM_TX, - .stream_name = "AFE Capture", - .cpu_dai_name = "msm-dai-q6-dev.225", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_AFE_PCM_TX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ignore_suspend = 1, - }, - /* Incall Record Uplink BACK END DAI Link */ - { - .name = LPASS_BE_INCALL_RECORD_TX, - .stream_name = "Voice Uplink Capture", - .cpu_dai_name = "msm-dai-q6-dev.32772", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_INCALL_RECORD_TX, - .be_hw_params_fixup = msm_be_hw_params_fixup, - .ignore_suspend = 1, - }, - /* Incall Record Downlink BACK END DAI Link */ - { - .name = LPASS_BE_INCALL_RECORD_RX, - .stream_name = "Voice Downlink Capture", - .cpu_dai_name = "msm-dai-q6-dev.32771", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_INCALL_RECORD_RX, - .be_hw_params_fixup = msm_be_hw_params_fixup, - .ignore_suspend = 1, - }, - /* Incall Music BACK END DAI Link */ - { - .name = LPASS_BE_VOICE_PLAYBACK_TX, - .stream_name = "Voice Farend Playback", - .cpu_dai_name = "msm-dai-q6-dev.32773", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, - .be_hw_params_fixup = msm_be_hw_params_fixup, - .ignore_suspend = 1, - }, - /* Incall Music 2 BACK END DAI Link */ - { - .name = LPASS_BE_VOICE2_PLAYBACK_TX, - .stream_name = "Voice2 Farend Playback", - .cpu_dai_name = "msm-dai-q6-dev.32770", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX, - .be_hw_params_fixup = msm_be_hw_params_fixup, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_USB_AUDIO_RX, - .stream_name = "USB Audio Playback", - .cpu_dai_name = "msm-dai-q6-dev.28672", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_USB_RX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_USB_AUDIO_TX, - .stream_name = "USB Audio Capture", - .cpu_dai_name = "msm-dai-q6-dev.28673", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_USB_TX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_PRI_TDM_RX_0, - .stream_name = "Primary TDM0 Playback", - .cpu_dai_name = "msm-dai-q6-tdm.36864", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_PRI_TDM_RX_0, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_tdm_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_PRI_TDM_TX_0, - .stream_name = "Primary TDM0 Capture", - .cpu_dai_name = "msm-dai-q6-tdm.36865", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_PRI_TDM_TX_0, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_tdm_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_SEC_TDM_RX_0, - .stream_name = "Secondary TDM0 Playback", - .cpu_dai_name = "msm-dai-q6-tdm.36880", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_SEC_TDM_RX_0, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_tdm_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_SEC_TDM_TX_0, - .stream_name = "Secondary TDM0 Capture", - .cpu_dai_name = "msm-dai-q6-tdm.36881", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_SEC_TDM_TX_0, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_tdm_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_TERT_TDM_RX_0, - .stream_name = "Tertiary TDM0 Playback", - .cpu_dai_name = "msm-dai-q6-tdm.36896", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_TERT_TDM_RX_0, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_tdm_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_TERT_TDM_TX_0, - .stream_name = "Tertiary TDM0 Capture", - .cpu_dai_name = "msm-dai-q6-tdm.36897", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_TERT_TDM_TX_0, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_tdm_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_QUAT_TDM_RX_0, - .stream_name = "Quaternary TDM0 Playback", - .cpu_dai_name = "msm-dai-q6-tdm.36912", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_QUAT_TDM_RX_0, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_tdm_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_QUAT_TDM_TX_0, - .stream_name = "Quaternary TDM0 Capture", - .cpu_dai_name = "msm-dai-q6-tdm.36913", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_QUAT_TDM_TX_0, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_tdm_be_ops, - .ignore_suspend = 1, - }, -}; - -static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = { - { - .name = LPASS_BE_PRI_MI2S_RX, - .stream_name = "Primary MI2S Playback", - .cpu_dai_name = "msm-dai-q6-mi2s.0", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_PRI_MI2S_RX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_mi2s_be_ops, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - }, - { - .name = LPASS_BE_PRI_MI2S_TX, - .stream_name = "Primary MI2S Capture", - .cpu_dai_name = "msm-dai-q6-mi2s.0", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_PRI_MI2S_TX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_mi2s_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_SEC_MI2S_RX, - .stream_name = "Secondary MI2S Playback", - .cpu_dai_name = "msm-dai-q6-mi2s.1", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_mi2s_be_ops, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - }, - { - .name = LPASS_BE_SEC_MI2S_TX, - .stream_name = "Secondary MI2S Capture", - .cpu_dai_name = "msm-dai-q6-mi2s.1", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_mi2s_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_TERT_MI2S_RX, - .stream_name = "Tertiary MI2S Playback", - .cpu_dai_name = "msm-dai-q6-mi2s.2", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_mi2s_be_ops, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - }, - { - .name = LPASS_BE_TERT_MI2S_TX, - .stream_name = "Tertiary MI2S Capture", - .cpu_dai_name = "msm-dai-q6-mi2s.2", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_mi2s_be_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_QUAT_MI2S_RX, - .stream_name = "Quaternary MI2S Playback", - .cpu_dai_name = "msm-dai-q6-mi2s.3", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_mi2s_be_ops, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - }, - { - .name = LPASS_BE_QUAT_MI2S_TX, - .stream_name = "Quaternary MI2S Capture", - .cpu_dai_name = "msm-dai-q6-mi2s.3", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ops = &msm_mi2s_be_ops, - .ignore_suspend = 1, - }, -}; - -static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = { - /* Primary AUX PCM Backend DAI Links */ - { - .name = LPASS_BE_AUXPCM_RX, - .stream_name = "AUX PCM Playback", - .cpu_dai_name = "msm-dai-q6-auxpcm.1", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_AUXPCM_RX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - .ops = &msm_aux_pcm_be_ops, - }, - { - .name = LPASS_BE_AUXPCM_TX, - .stream_name = "AUX PCM Capture", - .cpu_dai_name = "msm-dai-q6-auxpcm.1", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_AUXPCM_TX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - .ops = &msm_aux_pcm_be_ops, - }, - /* Secondary AUX PCM Backend DAI Links */ - { - .name = LPASS_BE_SEC_AUXPCM_RX, - .stream_name = "Sec AUX PCM Playback", - .cpu_dai_name = "msm-dai-q6-auxpcm.2", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_SEC_AUXPCM_RX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - .ops = &msm_aux_pcm_be_ops, - }, - { - .name = LPASS_BE_SEC_AUXPCM_TX, - .stream_name = "Sec AUX PCM Capture", - .cpu_dai_name = "msm-dai-q6-auxpcm.2", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_SEC_AUXPCM_TX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .ops = &msm_aux_pcm_be_ops, - }, - /* Tertiary AUX PCM Backend DAI Links */ - { - .name = LPASS_BE_TERT_AUXPCM_RX, - .stream_name = "Tert AUX PCM Playback", - .cpu_dai_name = "msm-dai-q6-auxpcm.3", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_TERT_AUXPCM_RX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - .ops = &msm_aux_pcm_be_ops, - }, - { - .name = LPASS_BE_TERT_AUXPCM_TX, - .stream_name = "Tert AUX PCM Capture", - .cpu_dai_name = "msm-dai-q6-auxpcm.3", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_TERT_AUXPCM_TX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .ops = &msm_aux_pcm_be_ops, - }, - /* Quaternary AUX PCM Backend DAI Links */ - { - .name = LPASS_BE_QUAT_AUXPCM_RX, - .stream_name = "Quat AUX PCM Playback", - .cpu_dai_name = "msm-dai-q6-auxpcm.4", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - .ops = &msm_aux_pcm_be_ops, - }, - { - .name = LPASS_BE_QUAT_AUXPCM_TX, - .stream_name = "Quat AUX PCM Capture", - .cpu_dai_name = "msm-dai-q6-auxpcm.4", - .platform_name = "msm-pcm-routing", - .codec_name = "msm-stub-codec.1", - .codec_dai_name = "msm-stub-tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX, - .be_hw_params_fixup = msm_common_be_hw_params_fixup, - .ignore_suspend = 1, - .ignore_pmdown_time = 1, - .ops = &msm_aux_pcm_be_ops, - }, -}; - - -static struct snd_soc_dai_link msm_wcn_be_dai_links[] = { - { - .name = LPASS_BE_SLIMBUS_7_RX, - .stream_name = "Slimbus7 Playback", - .cpu_dai_name = "msm-dai-q6-dev.16398", - .platform_name = "msm-pcm-routing", - .codec_name = "btfmslim_slave", - /* BT codec driver determines capabilities based on - * dai name, bt codecdai name should always contains - * supported usecase information - */ - .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx", - .no_pcm = 1, - .dpcm_playback = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_7_RX, - .be_hw_params_fixup = msm_btfm_be_hw_params_fixup, - .ops = &msm_wcn_ops, - /* dai link has playback support */ - .ignore_pmdown_time = 1, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_SLIMBUS_7_TX, - .stream_name = "Slimbus7 Capture", - .cpu_dai_name = "msm-dai-q6-dev.16399", - .platform_name = "msm-pcm-routing", - .codec_name = "btfmslim_slave", - .codec_dai_name = "btfm_bt_sco_slim_tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_7_TX, - .be_hw_params_fixup = msm_btfm_be_hw_params_fixup, - .ops = &msm_wcn_ops, - .ignore_suspend = 1, - }, - { - .name = LPASS_BE_SLIMBUS_8_TX, - .stream_name = "Slimbus8 Capture", - .cpu_dai_name = "msm-dai-q6-dev.16401", - .platform_name = "msm-pcm-routing", - .codec_name = "btfmslim_slave", - .codec_dai_name = "btfm_fm_slim_tx", - .no_pcm = 1, - .dpcm_capture = 1, - .be_id = MSM_BACKEND_DAI_SLIMBUS_8_TX, - .be_hw_params_fixup = msm_btfm_be_hw_params_fixup, - .init = &msm_wcn_init, - .ops = &msm_wcn_ops, - .ignore_suspend = 1, - }, -}; - -static struct snd_soc_dai_link msm_int_dai_links[ -ARRAY_SIZE(msm_int_dai) + -ARRAY_SIZE(msm_mi2s_be_dai_links) + -ARRAY_SIZE(msm_auxpcm_be_dai_links)+ -ARRAY_SIZE(msm_wcn_be_dai_links)]; - -static struct snd_soc_card msmfalcon_card = { - /* snd_soc_card_msmfalcon */ - .name = "msmfalcon-snd-card", - .dai_link = msm_int_dai, - .num_links = ARRAY_SIZE(msm_int_dai), -}; - -static void msm_disable_int_mclk0(struct work_struct *work) -{ - struct msm_asoc_mach_data *pdata = NULL; - struct delayed_work *dwork; - int ret = 0; - - dwork = to_delayed_work(work); - pdata = container_of(dwork, struct msm_asoc_mach_data, - disable_int_mclk0_work); - mutex_lock(&pdata->cdc_int_mclk0_mutex); - pr_debug("%s: mclk_enabled %d mclk_rsc_ref %d\n", __func__, - atomic_read(&pdata->int_mclk0_enabled), - atomic_read(&pdata->int_mclk0_rsc_ref)); - - if (atomic_read(&pdata->int_mclk0_enabled) == true - && atomic_read(&pdata->int_mclk0_rsc_ref) == 0) { - pr_debug("Disable the mclk\n"); - pdata->digital_cdc_core_clk.enable = 0; - ret = afe_set_lpass_clock_v2( - AFE_PORT_ID_INT0_MI2S_RX, - &pdata->digital_cdc_core_clk); - if (ret < 0) - pr_err("%s failed to disable the CCLK\n", __func__); - atomic_set(&pdata->int_mclk0_enabled, false); - } - mutex_unlock(&pdata->cdc_int_mclk0_mutex); -} - -static void msm_int_dt_parse_cap_info(struct platform_device *pdev, - struct msm_asoc_mach_data *pdata) -{ - const char *ext1_cap = "qcom,msm-micbias1-ext-cap"; - const char *ext2_cap = "qcom,msm-micbias2-ext-cap"; - - pdata->micbias1_cap_mode = - (of_property_read_bool(pdev->dev.of_node, ext1_cap) ? - MICBIAS_EXT_BYP_CAP : MICBIAS_NO_EXT_BYP_CAP); - - pdata->micbias2_cap_mode = - (of_property_read_bool(pdev->dev.of_node, ext2_cap) ? - MICBIAS_EXT_BYP_CAP : MICBIAS_NO_EXT_BYP_CAP); -} - -static struct snd_soc_card *msm_int_populate_sndcard_dailinks( - struct device *dev) -{ - struct snd_soc_card *card = &msmfalcon_card; - struct snd_soc_dai_link *dailink; - int len1; - - card->name = dev_name(dev); - len1 = ARRAY_SIZE(msm_int_dai); - memcpy(msm_int_dai_links, msm_int_dai, sizeof(msm_int_dai)); - dailink = msm_int_dai_links; - if (of_property_read_bool(dev->of_node, - "qcom,mi2s-audio-intf")) { - memcpy(dailink + len1, - msm_mi2s_be_dai_links, - sizeof(msm_mi2s_be_dai_links)); - len1 += ARRAY_SIZE(msm_mi2s_be_dai_links); - } - if (of_property_read_bool(dev->of_node, - "qcom,auxpcm-audio-intf")) { - memcpy(dailink + len1, - msm_auxpcm_be_dai_links, - sizeof(msm_auxpcm_be_dai_links)); - len1 += ARRAY_SIZE(msm_auxpcm_be_dai_links); - } - if (of_property_read_bool(dev->of_node, "qcom,wcn-btfm")) { - dev_dbg(dev, "%s(): WCN BTFM support present\n", - __func__); - memcpy(dailink + len1, - msm_wcn_be_dai_links, - sizeof(msm_wcn_be_dai_links)); - len1 += ARRAY_SIZE(msm_wcn_be_dai_links); - } - card->dai_link = dailink; - card->num_links = len1; - return card; -} - -static int msm_internal_init(struct platform_device *pdev, - struct msm_asoc_mach_data *pdata, - struct snd_soc_card *card) -{ - const char *type = NULL; - const char *hs_micbias_type = "qcom,msm-hs-micbias-type"; - int ret; - - ret = is_ext_spk_gpio_support(pdev, pdata); - if (ret < 0) - dev_dbg(&pdev->dev, - "%s: doesn't support external speaker pa\n", - __func__); - - ret = of_property_read_string(pdev->dev.of_node, - hs_micbias_type, &type); - if (ret) { - dev_err(&pdev->dev, "%s: missing %s in dt node\n", - __func__, hs_micbias_type); - goto err; - } - if (!strcmp(type, "external")) { - dev_dbg(&pdev->dev, "Headset is using external micbias\n"); - mbhc_cfg_ptr->hs_ext_micbias = true; - } else { - dev_dbg(&pdev->dev, "Headset is using internal micbias\n"); - mbhc_cfg_ptr->hs_ext_micbias = false; - } - - /* initialize the int_mclk0 */ - pdata->digital_cdc_core_clk.clk_set_minor_version = - AFE_API_VERSION_I2S_CONFIG; - pdata->digital_cdc_core_clk.clk_id = - Q6AFE_LPASS_CLK_ID_INT_MCLK_0; - pdata->digital_cdc_core_clk.clk_freq_in_hz = 0; - pdata->digital_cdc_core_clk.clk_attri = - Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO; - pdata->digital_cdc_core_clk.clk_root = - Q6AFE_LPASS_CLK_ROOT_DEFAULT; - pdata->digital_cdc_core_clk.enable = 1; - - /* Initialize loopback mode to false */ - pdata->lb_mode = false; - - msm_int_dt_parse_cap_info(pdev, pdata); - - card->dev = &pdev->dev; - platform_set_drvdata(pdev, card); - snd_soc_card_set_drvdata(card, pdata); - ret = snd_soc_of_parse_card_name(card, "qcom,model"); - if (ret) - goto err; - /* initialize timer */ - INIT_DELAYED_WORK(&pdata->disable_int_mclk0_work, - msm_disable_int_mclk0); - mutex_init(&pdata->cdc_int_mclk0_mutex); - atomic_set(&pdata->int_mclk0_rsc_ref, 0); - atomic_set(&pdata->int_mclk0_enabled, false); - - dev_info(&pdev->dev, "%s: default codec configured\n", __func__); - - return 0; -err: - return ret; -} - -/** - * msm_int_cdc_init - internal codec machine specific init. - * - * @pdev: platform device handle - * @pdata: private data of machine driver - * @card: sound card pointer reference - * @mbhc_cfg: MBHC config reference - * - * Returns 0. - */ -int msm_int_cdc_init(struct platform_device *pdev, - struct msm_asoc_mach_data *pdata, - struct snd_soc_card **card, - struct wcd_mbhc_config *mbhc_cfg) -{ - mbhc_cfg_ptr = mbhc_cfg; - - *card = msm_int_populate_sndcard_dailinks(&pdev->dev); - msm_internal_init(pdev, pdata, *card); - return 0; -} -EXPORT_SYMBOL(msm_int_cdc_init); diff --git a/sound/soc/msm/msmfalcon-internal.h b/sound/soc/msm/msmfalcon-internal.h deleted file mode 100644 index e5e3e7c66246..000000000000 --- a/sound/soc/msm/msmfalcon-internal.h +++ /dev/null @@ -1,32 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MSMFALCON_INTERNAL -#define __MSMFALCON_INTERNAL - -#include - -#ifdef CONFIG_SND_SOC_INT_CODEC -int msm_int_cdc_init(struct platform_device *pdev, - struct msm_asoc_mach_data *pdata, - struct snd_soc_card **card, - struct wcd_mbhc_config *mbhc_cfg); -#else -int msm_int_cdc_init(struct platform_device *pdev, - struct msm_asoc_mach_data *pdata, - struct snd_soc_card **card, - struct wcd_mbhc_config *mbhc_cfg) -{ - return 0; -} -#endif -#endif diff --git a/sound/soc/msm/sdm660-common.c b/sound/soc/msm/sdm660-common.c new file mode 100644 index 000000000000..623b8c5c866a --- /dev/null +++ b/sound/soc/msm/sdm660-common.c @@ -0,0 +1,2839 @@ +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include "qdsp6v2/msm-pcm-routing-v2.h" +#include "sdm660-common.h" +#include "sdm660-internal.h" +#include "sdm660-external.h" +#include "../codecs/sdm660_cdc/msm-analog-cdc.h" +#include "../codecs/wsa881x.h" + +#define DRV_NAME "sdm660-asoc-snd" + +#define MSM_INT_DIGITAL_CODEC "msm-dig-codec" +#define PMIC_INT_ANALOG_CODEC "analog-codec" + +#define DEV_NAME_STR_LEN 32 +#define DEFAULT_MCLK_RATE 9600000 + +struct dev_config { + u32 sample_rate; + u32 bit_format; + u32 channels; +}; + +/* TDM default config */ +static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = { + { /* PRI TDM */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */ + }, + { /* SEC TDM */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */ + }, + { /* TERT TDM */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */ + }, + { /* QUAT TDM */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */ + } +}; + +/* TDM default config */ +static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = { + { /* PRI TDM */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */ + }, + { /* SEC TDM */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */ + }, + { /* TERT TDM */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */ + }, + { /* QUAT TDM */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */ + } +}; + +static struct dev_config usb_rx_cfg = { + .sample_rate = SAMPLING_RATE_48KHZ, + .bit_format = SNDRV_PCM_FORMAT_S16_LE, + .channels = 2, +}; + +static struct dev_config usb_tx_cfg = { + .sample_rate = SAMPLING_RATE_48KHZ, + .bit_format = SNDRV_PCM_FORMAT_S16_LE, + .channels = 1, +}; + +enum { + PRIM_MI2S = 0, + SEC_MI2S, + TERT_MI2S, + QUAT_MI2S, + MI2S_MAX, +}; + +enum { + PRIM_AUX_PCM = 0, + SEC_AUX_PCM, + TERT_AUX_PCM, + QUAT_AUX_PCM, + AUX_PCM_MAX, +}; + +enum { + PCM_I2S_SEL_PRIM = 0, + PCM_I2S_SEL_SEC, + PCM_I2S_SEL_TERT, + PCM_I2S_SEL_QUAT, + PCM_I2S_SEL_MAX, +}; + +struct mi2s_aux_pcm_common_conf { + struct mutex lock; + void *pcm_i2s_sel_vt_addr; +}; + +struct mi2s_conf { + struct mutex lock; + u32 ref_cnt; + u32 msm_is_mi2s_master; +}; + +struct auxpcm_conf { + struct mutex lock; + u32 ref_cnt; +}; + +struct msm_wsa881x_dev_info { + struct device_node *of_node; + u32 index; +}; +static struct snd_soc_aux_dev *msm_aux_dev; +static struct snd_soc_codec_conf *msm_codec_conf; + +static bool msm_swap_gnd_mic(struct snd_soc_codec *codec); + +static struct wcd_mbhc_config mbhc_cfg = { + .read_fw_bin = false, + .calibration = NULL, + .detect_extn_cable = true, + .mono_stero_detection = false, + .swap_gnd_mic = NULL, + .hs_ext_micbias = true, + .key_code[0] = KEY_MEDIA, + .key_code[1] = KEY_VOICECOMMAND, + .key_code[2] = KEY_VOLUMEUP, + .key_code[3] = KEY_VOLUMEDOWN, + .key_code[4] = 0, + .key_code[5] = 0, + .key_code[6] = 0, + .key_code[7] = 0, + .linein_th = 5000, + .moisture_en = false, + .mbhc_micbias = 0, + .anc_micbias = 0, + .enable_anc_mic_detect = false, +}; + +static struct dev_config proxy_rx_cfg = { + .sample_rate = SAMPLING_RATE_48KHZ, + .bit_format = SNDRV_PCM_FORMAT_S16_LE, + .channels = 2, +}; + +/* Default configuration of MI2S channels */ +static struct dev_config mi2s_rx_cfg[] = { + [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, + [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, + [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, + [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, +}; + +static struct dev_config mi2s_tx_cfg[] = { + [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, +}; + +static struct dev_config aux_pcm_rx_cfg[] = { + [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, +}; + +static struct dev_config aux_pcm_tx_cfg[] = { + [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, +}; + +static char const *ch_text[] = {"Two", "Three", "Four", "Five", + "Six", "Seven", "Eight"}; +static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"}; +static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_16", + "KHZ_32", "KHZ_44P1", "KHZ_48", + "KHZ_96", "KHZ_192"}; +static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four", + "Five", "Six", "Seven", + "Eight"}; +static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE", + "S32_LE"}; +static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four", + "Five", "Six", "Seven", "Eight"}; +static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"}; +static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32", + "KHZ_44P1", "KHZ_48", "KHZ_96", + "KHZ_192", "KHZ_352P8", "KHZ_384"}; +static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four", + "Five", "Six", "Seven", + "Eight"}; +static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025", + "KHZ_16", "KHZ_22P05", + "KHZ_32", "KHZ_44P1", "KHZ_48", + "KHZ_96", "KHZ_192", "KHZ_384"}; + +static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text); +static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text); +static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text); +static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text); +static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text); +static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text); +static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text); +static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text); +static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text); +static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text); +static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text); +static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text); +static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text); +static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text); +static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text); +static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text); +static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text); +static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text); + +static struct afe_clk_set mi2s_clk[MI2S_MAX] = { + { + AFE_API_VERSION_I2S_CONFIG, + Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT, + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, + Q6AFE_LPASS_CLK_ROOT_DEFAULT, + 0, + }, + { + AFE_API_VERSION_I2S_CONFIG, + Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT, + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, + Q6AFE_LPASS_CLK_ROOT_DEFAULT, + 0, + }, + { + AFE_API_VERSION_I2S_CONFIG, + Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT, + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, + Q6AFE_LPASS_CLK_ROOT_DEFAULT, + 0, + }, + { + AFE_API_VERSION_I2S_CONFIG, + Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT, + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, + Q6AFE_LPASS_CLK_ROOT_DEFAULT, + 0, + } +}; + +static struct mi2s_aux_pcm_common_conf mi2s_auxpcm_conf[PCM_I2S_SEL_MAX]; +static struct mi2s_conf mi2s_intf_conf[MI2S_MAX]; +static struct auxpcm_conf auxpcm_intf_conf[AUX_PCM_MAX]; + +static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: proxy_rx channels = %d\n", + __func__, proxy_rx_cfg.channels); + ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2; + + return 0; +} + +static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2; + pr_debug("%s: proxy_rx channels = %d\n", + __func__, proxy_rx_cfg.channels); + + return 1; +} + +static int tdm_get_sample_rate(int value) +{ + int sample_rate = 0; + + switch (value) { + case 0: + sample_rate = SAMPLING_RATE_8KHZ; + break; + case 1: + sample_rate = SAMPLING_RATE_16KHZ; + break; + case 2: + sample_rate = SAMPLING_RATE_32KHZ; + break; + case 3: + sample_rate = SAMPLING_RATE_44P1KHZ; + break; + case 4: + sample_rate = SAMPLING_RATE_48KHZ; + break; + case 5: + sample_rate = SAMPLING_RATE_96KHZ; + break; + case 6: + sample_rate = SAMPLING_RATE_192KHZ; + break; + case 7: + sample_rate = SAMPLING_RATE_352P8KHZ; + break; + case 8: + sample_rate = SAMPLING_RATE_384KHZ; + break; + default: + sample_rate = SAMPLING_RATE_48KHZ; + break; + } + return sample_rate; +} + +static int tdm_get_sample_rate_val(int sample_rate) +{ + int sample_rate_val = 0; + + switch (sample_rate) { + case SAMPLING_RATE_8KHZ: + sample_rate_val = 0; + break; + case SAMPLING_RATE_16KHZ: + sample_rate_val = 1; + break; + case SAMPLING_RATE_32KHZ: + sample_rate_val = 2; + break; + case SAMPLING_RATE_44P1KHZ: + sample_rate_val = 3; + break; + case SAMPLING_RATE_48KHZ: + sample_rate_val = 4; + break; + case SAMPLING_RATE_96KHZ: + sample_rate_val = 5; + break; + case SAMPLING_RATE_192KHZ: + sample_rate_val = 6; + break; + case SAMPLING_RATE_352P8KHZ: + sample_rate_val = 7; + break; + case SAMPLING_RATE_384KHZ: + sample_rate_val = 8; + break; + default: + sample_rate_val = 4; + break; + } + return sample_rate_val; +} + +static int tdm_get_port_idx(struct snd_kcontrol *kcontrol, + struct tdm_port *port) +{ + if (port) { + if (strnstr(kcontrol->id.name, "PRI", + sizeof(kcontrol->id.name))) { + port->mode = TDM_PRI; + } else if (strnstr(kcontrol->id.name, "SEC", + sizeof(kcontrol->id.name))) { + port->mode = TDM_SEC; + } else if (strnstr(kcontrol->id.name, "TERT", + sizeof(kcontrol->id.name))) { + port->mode = TDM_TERT; + } else if (strnstr(kcontrol->id.name, "QUAT", + sizeof(kcontrol->id.name))) { + port->mode = TDM_QUAT; + } else { + pr_err("%s: unsupported mode in: %s", + __func__, kcontrol->id.name); + return -EINVAL; + } + + if (strnstr(kcontrol->id.name, "RX_0", + sizeof(kcontrol->id.name)) || + strnstr(kcontrol->id.name, "TX_0", + sizeof(kcontrol->id.name))) { + port->channel = TDM_0; + } else if (strnstr(kcontrol->id.name, "RX_1", + sizeof(kcontrol->id.name)) || + strnstr(kcontrol->id.name, "TX_1", + sizeof(kcontrol->id.name))) { + port->channel = TDM_1; + } else if (strnstr(kcontrol->id.name, "RX_2", + sizeof(kcontrol->id.name)) || + strnstr(kcontrol->id.name, "TX_2", + sizeof(kcontrol->id.name))) { + port->channel = TDM_2; + } else if (strnstr(kcontrol->id.name, "RX_3", + sizeof(kcontrol->id.name)) || + strnstr(kcontrol->id.name, "TX_3", + sizeof(kcontrol->id.name))) { + port->channel = TDM_3; + } else if (strnstr(kcontrol->id.name, "RX_4", + sizeof(kcontrol->id.name)) || + strnstr(kcontrol->id.name, "TX_4", + sizeof(kcontrol->id.name))) { + port->channel = TDM_4; + } else if (strnstr(kcontrol->id.name, "RX_5", + sizeof(kcontrol->id.name)) || + strnstr(kcontrol->id.name, "TX_5", + sizeof(kcontrol->id.name))) { + port->channel = TDM_5; + } else if (strnstr(kcontrol->id.name, "RX_6", + sizeof(kcontrol->id.name)) || + strnstr(kcontrol->id.name, "TX_6", + sizeof(kcontrol->id.name))) { + port->channel = TDM_6; + } else if (strnstr(kcontrol->id.name, "RX_7", + sizeof(kcontrol->id.name)) || + strnstr(kcontrol->id.name, "TX_7", + sizeof(kcontrol->id.name))) { + port->channel = TDM_7; + } else { + pr_err("%s: unsupported channel in: %s", + __func__, kcontrol->id.name); + return -EINVAL; + } + } else + return -EINVAL; + return 0; +} + +static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct tdm_port port; + int ret = tdm_get_port_idx(kcontrol, &port); + + if (ret) { + pr_err("%s: unsupported control: %s", + __func__, kcontrol->id.name); + } else { + ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val( + tdm_rx_cfg[port.mode][port.channel].sample_rate); + + pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__, + tdm_rx_cfg[port.mode][port.channel].sample_rate, + ucontrol->value.enumerated.item[0]); + } + return ret; +} + +static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct tdm_port port; + int ret = tdm_get_port_idx(kcontrol, &port); + + if (ret) { + pr_err("%s: unsupported control: %s", + __func__, kcontrol->id.name); + } else { + tdm_rx_cfg[port.mode][port.channel].sample_rate = + tdm_get_sample_rate(ucontrol->value.enumerated.item[0]); + + pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__, + tdm_rx_cfg[port.mode][port.channel].sample_rate, + ucontrol->value.enumerated.item[0]); + } + return ret; +} + +static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct tdm_port port; + int ret = tdm_get_port_idx(kcontrol, &port); + + if (ret) { + pr_err("%s: unsupported control: %s", + __func__, kcontrol->id.name); + } else { + ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val( + tdm_tx_cfg[port.mode][port.channel].sample_rate); + + pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__, + tdm_tx_cfg[port.mode][port.channel].sample_rate, + ucontrol->value.enumerated.item[0]); + } + return ret; +} + +static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct tdm_port port; + int ret = tdm_get_port_idx(kcontrol, &port); + + if (ret) { + pr_err("%s: unsupported control: %s", + __func__, kcontrol->id.name); + } else { + tdm_tx_cfg[port.mode][port.channel].sample_rate = + tdm_get_sample_rate(ucontrol->value.enumerated.item[0]); + + pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__, + tdm_tx_cfg[port.mode][port.channel].sample_rate, + ucontrol->value.enumerated.item[0]); + } + return ret; +} + +static int tdm_get_format(int value) +{ + int format = 0; + + switch (value) { + case 0: + format = SNDRV_PCM_FORMAT_S16_LE; + break; + case 1: + format = SNDRV_PCM_FORMAT_S24_LE; + break; + case 2: + format = SNDRV_PCM_FORMAT_S32_LE; + break; + default: + format = SNDRV_PCM_FORMAT_S16_LE; + break; + } + return format; +} + +static int tdm_get_format_val(int format) +{ + int value = 0; + + switch (format) { + case SNDRV_PCM_FORMAT_S16_LE: + value = 0; + break; + case SNDRV_PCM_FORMAT_S24_LE: + value = 1; + break; + case SNDRV_PCM_FORMAT_S32_LE: + value = 2; + break; + default: + value = 0; + break; + } + return value; +} + +static int tdm_rx_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct tdm_port port; + int ret = tdm_get_port_idx(kcontrol, &port); + + if (ret) { + pr_err("%s: unsupported control: %s", + __func__, kcontrol->id.name); + } else { + ucontrol->value.enumerated.item[0] = tdm_get_format_val( + tdm_rx_cfg[port.mode][port.channel].bit_format); + + pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__, + tdm_rx_cfg[port.mode][port.channel].bit_format, + ucontrol->value.enumerated.item[0]); + } + return ret; +} + +static int tdm_rx_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct tdm_port port; + int ret = tdm_get_port_idx(kcontrol, &port); + + if (ret) { + pr_err("%s: unsupported control: %s", + __func__, kcontrol->id.name); + } else { + tdm_rx_cfg[port.mode][port.channel].bit_format = + tdm_get_format(ucontrol->value.enumerated.item[0]); + + pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__, + tdm_rx_cfg[port.mode][port.channel].bit_format, + ucontrol->value.enumerated.item[0]); + } + return ret; +} + +static int tdm_tx_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct tdm_port port; + int ret = tdm_get_port_idx(kcontrol, &port); + + if (ret) { + pr_err("%s: unsupported control: %s", + __func__, kcontrol->id.name); + } else { + ucontrol->value.enumerated.item[0] = tdm_get_format_val( + tdm_tx_cfg[port.mode][port.channel].bit_format); + + pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__, + tdm_tx_cfg[port.mode][port.channel].bit_format, + ucontrol->value.enumerated.item[0]); + } + return ret; +} + +static int tdm_tx_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct tdm_port port; + int ret = tdm_get_port_idx(kcontrol, &port); + + if (ret) { + pr_err("%s: unsupported control: %s", + __func__, kcontrol->id.name); + } else { + tdm_tx_cfg[port.mode][port.channel].bit_format = + tdm_get_format(ucontrol->value.enumerated.item[0]); + + pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__, + tdm_tx_cfg[port.mode][port.channel].bit_format, + ucontrol->value.enumerated.item[0]); + } + return ret; +} + +static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct tdm_port port; + int ret = tdm_get_port_idx(kcontrol, &port); + + if (ret) { + pr_err("%s: unsupported control: %s", + __func__, kcontrol->id.name); + } else { + + ucontrol->value.enumerated.item[0] = + tdm_rx_cfg[port.mode][port.channel].channels - 1; + + pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__, + tdm_rx_cfg[port.mode][port.channel].channels - 1, + ucontrol->value.enumerated.item[0]); + } + return ret; +} + +static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct tdm_port port; + int ret = tdm_get_port_idx(kcontrol, &port); + + if (ret) { + pr_err("%s: unsupported control: %s", + __func__, kcontrol->id.name); + } else { + tdm_rx_cfg[port.mode][port.channel].channels = + ucontrol->value.enumerated.item[0] + 1; + + pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__, + tdm_rx_cfg[port.mode][port.channel].channels, + ucontrol->value.enumerated.item[0] + 1); + } + return ret; +} + +static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct tdm_port port; + int ret = tdm_get_port_idx(kcontrol, &port); + + if (ret) { + pr_err("%s: unsupported control: %s", + __func__, kcontrol->id.name); + } else { + ucontrol->value.enumerated.item[0] = + tdm_tx_cfg[port.mode][port.channel].channels - 1; + + pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__, + tdm_tx_cfg[port.mode][port.channel].channels - 1, + ucontrol->value.enumerated.item[0]); + } + return ret; +} + +static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct tdm_port port; + int ret = tdm_get_port_idx(kcontrol, &port); + + if (ret) { + pr_err("%s: unsupported control: %s", + __func__, kcontrol->id.name); + } else { + tdm_tx_cfg[port.mode][port.channel].channels = + ucontrol->value.enumerated.item[0] + 1; + + pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__, + tdm_tx_cfg[port.mode][port.channel].channels, + ucontrol->value.enumerated.item[0] + 1); + } + return ret; +} + +static int aux_pcm_get_sample_rate(int value) +{ + int sample_rate; + + switch (value) { + case 1: + sample_rate = SAMPLING_RATE_16KHZ; + break; + case 0: + default: + sample_rate = SAMPLING_RATE_8KHZ; + break; + } + return sample_rate; +} + +static int aux_pcm_get_sample_rate_val(int sample_rate) +{ + int sample_rate_val; + + switch (sample_rate) { + case SAMPLING_RATE_16KHZ: + sample_rate_val = 1; + break; + case SAMPLING_RATE_8KHZ: + default: + sample_rate_val = 0; + break; + } + return sample_rate_val; +} + +static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol) +{ + int idx; + + if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM", + sizeof("PRIM_AUX_PCM"))) + idx = PRIM_AUX_PCM; + else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM", + sizeof("SEC_AUX_PCM"))) + idx = SEC_AUX_PCM; + else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM", + sizeof("TERT_AUX_PCM"))) + idx = TERT_AUX_PCM; + else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM", + sizeof("QUAT_AUX_PCM"))) + idx = QUAT_AUX_PCM; + else { + pr_err("%s: unsupported port: %s", + __func__, kcontrol->id.name); + idx = -EINVAL; + } + + return idx; +} + +static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int idx = aux_pcm_get_port_idx(kcontrol); + + if (idx < 0) + return idx; + + aux_pcm_rx_cfg[idx].sample_rate = + aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]); + + pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__, + idx, aux_pcm_rx_cfg[idx].sample_rate, + ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int idx = aux_pcm_get_port_idx(kcontrol); + + if (idx < 0) + return idx; + + ucontrol->value.enumerated.item[0] = + aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate); + + pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__, + idx, aux_pcm_rx_cfg[idx].sample_rate, + ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int idx = aux_pcm_get_port_idx(kcontrol); + + if (idx < 0) + return idx; + + aux_pcm_tx_cfg[idx].sample_rate = + aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]); + + pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__, + idx, aux_pcm_tx_cfg[idx].sample_rate, + ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int idx = aux_pcm_get_port_idx(kcontrol); + + if (idx < 0) + return idx; + + ucontrol->value.enumerated.item[0] = + aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate); + + pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__, + idx, aux_pcm_tx_cfg[idx].sample_rate, + ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol) +{ + int idx; + + if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX", + sizeof("PRIM_MI2S_RX"))) + idx = PRIM_MI2S; + else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX", + sizeof("SEC_MI2S_RX"))) + idx = SEC_MI2S; + else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX", + sizeof("TERT_MI2S_RX"))) + idx = TERT_MI2S; + else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX", + sizeof("QUAT_MI2S_RX"))) + idx = QUAT_MI2S; + else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX", + sizeof("PRIM_MI2S_TX"))) + idx = PRIM_MI2S; + else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX", + sizeof("SEC_MI2S_TX"))) + idx = SEC_MI2S; + else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX", + sizeof("TERT_MI2S_TX"))) + idx = TERT_MI2S; + else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX", + sizeof("QUAT_MI2S_TX"))) + idx = QUAT_MI2S; + else { + pr_err("%s: unsupported channel: %s", + __func__, kcontrol->id.name); + idx = -EINVAL; + } + + return idx; +} + +static int mi2s_get_sample_rate_val(int sample_rate) +{ + int sample_rate_val; + + switch (sample_rate) { + case SAMPLING_RATE_8KHZ: + sample_rate_val = 0; + break; + case SAMPLING_RATE_16KHZ: + sample_rate_val = 1; + break; + case SAMPLING_RATE_32KHZ: + sample_rate_val = 2; + break; + case SAMPLING_RATE_44P1KHZ: + sample_rate_val = 3; + break; + case SAMPLING_RATE_48KHZ: + sample_rate_val = 4; + break; + case SAMPLING_RATE_96KHZ: + sample_rate_val = 5; + break; + case SAMPLING_RATE_192KHZ: + sample_rate_val = 6; + break; + default: + sample_rate_val = 4; + break; + } + return sample_rate_val; +} + +static int mi2s_get_sample_rate(int value) +{ + int sample_rate; + + switch (value) { + case 0: + sample_rate = SAMPLING_RATE_8KHZ; + break; + case 1: + sample_rate = SAMPLING_RATE_16KHZ; + break; + case 2: + sample_rate = SAMPLING_RATE_32KHZ; + break; + case 3: + sample_rate = SAMPLING_RATE_44P1KHZ; + break; + case 4: + sample_rate = SAMPLING_RATE_48KHZ; + break; + case 5: + sample_rate = SAMPLING_RATE_96KHZ; + break; + case 6: + sample_rate = SAMPLING_RATE_192KHZ; + break; + default: + sample_rate = SAMPLING_RATE_48KHZ; + break; + } + return sample_rate; +} + +static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int idx = mi2s_get_port_idx(kcontrol); + + if (idx < 0) + return idx; + + mi2s_rx_cfg[idx].sample_rate = + mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]); + + pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__, + idx, mi2s_rx_cfg[idx].sample_rate, + ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int idx = mi2s_get_port_idx(kcontrol); + + if (idx < 0) + return idx; + + ucontrol->value.enumerated.item[0] = + mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate); + + pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__, + idx, mi2s_rx_cfg[idx].sample_rate, + ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int idx = mi2s_get_port_idx(kcontrol); + + if (idx < 0) + return idx; + + mi2s_tx_cfg[idx].sample_rate = + mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]); + + pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__, + idx, mi2s_tx_cfg[idx].sample_rate, + ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int idx = mi2s_get_port_idx(kcontrol); + + if (idx < 0) + return idx; + + ucontrol->value.enumerated.item[0] = + mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate); + + pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__, + idx, mi2s_tx_cfg[idx].sample_rate, + ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int idx = mi2s_get_port_idx(kcontrol); + + if (idx < 0) + return idx; + + pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__, + idx, mi2s_rx_cfg[idx].channels); + ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1; + + return 0; +} + +static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int idx = mi2s_get_port_idx(kcontrol); + + if (idx < 0) + return idx; + + mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1; + pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__, + idx, mi2s_rx_cfg[idx].channels); + + return 1; +} + +static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int idx = mi2s_get_port_idx(kcontrol); + + if (idx < 0) + return idx; + + pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__, + idx, mi2s_tx_cfg[idx].channels); + ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1; + + return 0; +} + +static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int idx = mi2s_get_port_idx(kcontrol); + + if (idx < 0) + return idx; + + mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1; + pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__, + idx, mi2s_tx_cfg[idx].channels); + + return 1; +} + +static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, + usb_rx_cfg.channels); + ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1; + return 0; +} + +static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1; + + pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels); + return 1; +} + +static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int sample_rate_val; + + switch (usb_rx_cfg.sample_rate) { + case SAMPLING_RATE_384KHZ: + sample_rate_val = 9; + break; + case SAMPLING_RATE_192KHZ: + sample_rate_val = 8; + break; + case SAMPLING_RATE_96KHZ: + sample_rate_val = 7; + break; + case SAMPLING_RATE_48KHZ: + sample_rate_val = 6; + break; + case SAMPLING_RATE_44P1KHZ: + sample_rate_val = 5; + break; + case SAMPLING_RATE_32KHZ: + sample_rate_val = 4; + break; + case SAMPLING_RATE_22P05KHZ: + sample_rate_val = 3; + break; + case SAMPLING_RATE_16KHZ: + sample_rate_val = 2; + break; + case SAMPLING_RATE_11P025KHZ: + sample_rate_val = 1; + break; + case SAMPLING_RATE_8KHZ: + default: + sample_rate_val = 0; + break; + } + + ucontrol->value.integer.value[0] = sample_rate_val; + pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__, + usb_rx_cfg.sample_rate); + return 0; +} + +static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 9: + usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ; + break; + case 8: + usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ; + break; + case 7: + usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ; + break; + case 6: + usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ; + break; + case 5: + usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ; + break; + case 4: + usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ; + break; + case 3: + usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ; + break; + case 2: + usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ; + break; + case 1: + usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ; + break; + case 0: + usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ; + break; + default: + usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ; + break; + } + + pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n", + __func__, ucontrol->value.integer.value[0], + usb_rx_cfg.sample_rate); + return 0; +} + +static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (usb_rx_cfg.bit_format) { + case SNDRV_PCM_FORMAT_S32_LE: + ucontrol->value.integer.value[0] = 3; + break; + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + + pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n", + __func__, usb_rx_cfg.bit_format, + ucontrol->value.integer.value[0]); + return 0; +} + +static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int rc = 0; + + switch (ucontrol->value.integer.value[0]) { + case 3: + usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE; + break; + case 2: + usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE; + break; + case 1: + usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE; + break; + case 0: + default: + usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE; + break; + } + pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n", + __func__, usb_rx_cfg.bit_format, + ucontrol->value.integer.value[0]); + + return rc; +} + +static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, + usb_tx_cfg.channels); + ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1; + return 0; +} + +static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1; + + pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels); + return 1; +} + +static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int sample_rate_val; + + switch (usb_tx_cfg.sample_rate) { + case SAMPLING_RATE_384KHZ: + sample_rate_val = 9; + break; + case SAMPLING_RATE_192KHZ: + sample_rate_val = 8; + break; + case SAMPLING_RATE_96KHZ: + sample_rate_val = 7; + break; + case SAMPLING_RATE_48KHZ: + sample_rate_val = 6; + break; + case SAMPLING_RATE_44P1KHZ: + sample_rate_val = 5; + break; + case SAMPLING_RATE_32KHZ: + sample_rate_val = 4; + break; + case SAMPLING_RATE_22P05KHZ: + sample_rate_val = 3; + break; + case SAMPLING_RATE_16KHZ: + sample_rate_val = 2; + break; + case SAMPLING_RATE_11P025KHZ: + sample_rate_val = 1; + break; + case SAMPLING_RATE_8KHZ: + sample_rate_val = 0; + break; + default: + sample_rate_val = 6; + break; + } + + ucontrol->value.integer.value[0] = sample_rate_val; + pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__, + usb_tx_cfg.sample_rate); + return 0; +} + +static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 9: + usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ; + break; + case 8: + usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ; + break; + case 7: + usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ; + break; + case 6: + usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ; + break; + case 5: + usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ; + break; + case 4: + usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ; + break; + case 3: + usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ; + break; + case 2: + usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ; + break; + case 1: + usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ; + break; + case 0: + usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ; + break; + default: + usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ; + break; + } + + pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n", + __func__, ucontrol->value.integer.value[0], + usb_tx_cfg.sample_rate); + return 0; +} + +static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (usb_tx_cfg.bit_format) { + case SNDRV_PCM_FORMAT_S32_LE: + ucontrol->value.integer.value[0] = 3; + break; + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + + pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n", + __func__, usb_tx_cfg.bit_format, + ucontrol->value.integer.value[0]); + return 0; +} + +static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int rc = 0; + + switch (ucontrol->value.integer.value[0]) { + case 3: + usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE; + break; + case 2: + usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE; + break; + case 1: + usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE; + break; + case 0: + default: + usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE; + break; + } + pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n", + __func__, usb_tx_cfg.bit_format, + ucontrol->value.integer.value[0]); + + return rc; +} + +const struct snd_kcontrol_new msm_common_snd_controls[] = { + SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs, + proxy_rx_ch_get, proxy_rx_ch_put), + SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate, + aux_pcm_rx_sample_rate_get, + aux_pcm_rx_sample_rate_put), + SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate, + aux_pcm_rx_sample_rate_get, + aux_pcm_rx_sample_rate_put), + SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate, + aux_pcm_rx_sample_rate_get, + aux_pcm_rx_sample_rate_put), + SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate, + aux_pcm_rx_sample_rate_get, + aux_pcm_rx_sample_rate_put), + SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate, + aux_pcm_tx_sample_rate_get, + aux_pcm_tx_sample_rate_put), + SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate, + aux_pcm_tx_sample_rate_get, + aux_pcm_tx_sample_rate_put), + SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate, + aux_pcm_tx_sample_rate_get, + aux_pcm_tx_sample_rate_put), + SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate, + aux_pcm_tx_sample_rate_get, + aux_pcm_tx_sample_rate_put), + SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate, + mi2s_rx_sample_rate_get, + mi2s_rx_sample_rate_put), + SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate, + mi2s_rx_sample_rate_get, + mi2s_rx_sample_rate_put), + SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate, + mi2s_rx_sample_rate_get, + mi2s_rx_sample_rate_put), + SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate, + mi2s_rx_sample_rate_get, + mi2s_rx_sample_rate_put), + SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate, + mi2s_tx_sample_rate_get, + mi2s_tx_sample_rate_put), + SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate, + mi2s_tx_sample_rate_get, + mi2s_tx_sample_rate_put), + SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate, + mi2s_tx_sample_rate_get, + mi2s_tx_sample_rate_put), + SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate, + mi2s_tx_sample_rate_get, + mi2s_tx_sample_rate_put), + SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs, + msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put), + SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs, + msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put), + SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs, + msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put), + SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs, + msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put), + SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs, + msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put), + SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs, + msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put), + SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs, + msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put), + SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs, + msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put), + SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs, + usb_audio_rx_ch_get, usb_audio_rx_ch_put), + SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs, + usb_audio_tx_ch_get, usb_audio_tx_ch_put), + SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format, + usb_audio_rx_format_get, usb_audio_rx_format_put), + SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format, + usb_audio_tx_format_get, usb_audio_tx_format_put), + SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate, + usb_audio_rx_sample_rate_get, + usb_audio_rx_sample_rate_put), + SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate, + usb_audio_tx_sample_rate_get, + usb_audio_tx_sample_rate_put), + SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate, + tdm_rx_sample_rate_get, + tdm_rx_sample_rate_put), + SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate, + tdm_tx_sample_rate_get, + tdm_tx_sample_rate_put), + SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format, + tdm_rx_format_get, + tdm_rx_format_put), + SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format, + tdm_tx_format_get, + tdm_tx_format_put), + SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs, + tdm_rx_ch_get, + tdm_rx_ch_put), + SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs, + tdm_tx_ch_get, + tdm_tx_ch_put), + SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate, + tdm_rx_sample_rate_get, + tdm_rx_sample_rate_put), + SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate, + tdm_tx_sample_rate_get, + tdm_tx_sample_rate_put), + SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format, + tdm_rx_format_get, + tdm_rx_format_put), + SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format, + tdm_tx_format_get, + tdm_tx_format_put), + SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs, + tdm_rx_ch_get, + tdm_rx_ch_put), + SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs, + tdm_tx_ch_get, + tdm_tx_ch_put), + SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate, + tdm_rx_sample_rate_get, + tdm_rx_sample_rate_put), + SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate, + tdm_tx_sample_rate_get, + tdm_tx_sample_rate_put), + SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format, + tdm_rx_format_get, + tdm_rx_format_put), + SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format, + tdm_tx_format_get, + tdm_tx_format_put), + SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs, + tdm_rx_ch_get, + tdm_rx_ch_put), + SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs, + tdm_tx_ch_get, + tdm_tx_ch_put), + SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate, + tdm_rx_sample_rate_get, + tdm_rx_sample_rate_put), + SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate, + tdm_tx_sample_rate_get, + tdm_tx_sample_rate_put), + SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format, + tdm_rx_format_get, + tdm_rx_format_put), + SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format, + tdm_tx_format_get, + tdm_tx_format_put), + SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs, + tdm_rx_ch_get, + tdm_rx_ch_put), + SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs, + tdm_tx_ch_get, + tdm_tx_ch_put), +}; + +static inline int param_is_mask(int p) +{ + return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) && + (p <= SNDRV_PCM_HW_PARAM_LAST_MASK); +} + +static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p, + int n) +{ + return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]); +} + +static void param_set_mask(struct snd_pcm_hw_params *p, int n, unsigned bit) +{ + if (bit >= SNDRV_MASK_MAX) + return; + if (param_is_mask(n)) { + struct snd_mask *m = param_to_mask(p, n); + + m->bits[0] = 0; + m->bits[1] = 0; + m->bits[bit >> 5] |= (1 << (bit & 31)); + } +} + +/** + * msm_common_be_hw_params_fixup - updates settings of ALSA BE hw params. + * + * @rtd: runtime dailink instance + * @params: HW params of associated backend dailink. + * + * Returns 0. + */ +int msm_common_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_dai_link *dai_link = rtd->dai_link; + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + int rc = 0; + + pr_debug("%s: format = %d, rate = %d\n", + __func__, params_format(params), params_rate(params)); + + switch (dai_link->be_id) { + case MSM_BACKEND_DAI_USB_RX: + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + usb_rx_cfg.bit_format); + rate->min = rate->max = usb_rx_cfg.sample_rate; + channels->min = channels->max = usb_rx_cfg.channels; + break; + + case MSM_BACKEND_DAI_USB_TX: + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + usb_tx_cfg.bit_format); + rate->min = rate->max = usb_tx_cfg.sample_rate; + channels->min = channels->max = usb_tx_cfg.channels; + break; + + case MSM_BACKEND_DAI_AFE_PCM_RX: + channels->min = channels->max = proxy_rx_cfg.channels; + rate->min = rate->max = SAMPLING_RATE_48KHZ; + break; + + case MSM_BACKEND_DAI_PRI_TDM_RX_0: + channels->min = channels->max = + tdm_rx_cfg[TDM_PRI][TDM_0].channels; + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + tdm_rx_cfg[TDM_PRI][TDM_0].bit_format); + rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate; + break; + + case MSM_BACKEND_DAI_PRI_TDM_TX_0: + channels->min = channels->max = + tdm_tx_cfg[TDM_PRI][TDM_0].channels; + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + tdm_tx_cfg[TDM_PRI][TDM_0].bit_format); + rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate; + break; + + case MSM_BACKEND_DAI_SEC_TDM_RX_0: + channels->min = channels->max = + tdm_rx_cfg[TDM_SEC][TDM_0].channels; + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + tdm_rx_cfg[TDM_SEC][TDM_0].bit_format); + rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate; + break; + + case MSM_BACKEND_DAI_SEC_TDM_TX_0: + channels->min = channels->max = + tdm_tx_cfg[TDM_SEC][TDM_0].channels; + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + tdm_tx_cfg[TDM_SEC][TDM_0].bit_format); + rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate; + break; + + case MSM_BACKEND_DAI_TERT_TDM_RX_0: + channels->min = channels->max = + tdm_rx_cfg[TDM_TERT][TDM_0].channels; + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + tdm_rx_cfg[TDM_TERT][TDM_0].bit_format); + rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate; + break; + + case MSM_BACKEND_DAI_TERT_TDM_TX_0: + channels->min = channels->max = + tdm_tx_cfg[TDM_TERT][TDM_0].channels; + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + tdm_tx_cfg[TDM_TERT][TDM_0].bit_format); + rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate; + break; + + case MSM_BACKEND_DAI_QUAT_TDM_RX_0: + channels->min = channels->max = + tdm_rx_cfg[TDM_QUAT][TDM_0].channels; + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format); + rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate; + break; + + case MSM_BACKEND_DAI_QUAT_TDM_TX_0: + channels->min = channels->max = + tdm_tx_cfg[TDM_QUAT][TDM_0].channels; + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format); + rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate; + break; + + case MSM_BACKEND_DAI_AUXPCM_RX: + rate->min = rate->max = + aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate; + channels->min = channels->max = + aux_pcm_rx_cfg[PRIM_AUX_PCM].channels; + break; + + case MSM_BACKEND_DAI_AUXPCM_TX: + rate->min = rate->max = + aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate; + channels->min = channels->max = + aux_pcm_tx_cfg[PRIM_AUX_PCM].channels; + break; + + case MSM_BACKEND_DAI_SEC_AUXPCM_RX: + rate->min = rate->max = + aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate; + channels->min = channels->max = + aux_pcm_rx_cfg[SEC_AUX_PCM].channels; + break; + + case MSM_BACKEND_DAI_SEC_AUXPCM_TX: + rate->min = rate->max = + aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate; + channels->min = channels->max = + aux_pcm_tx_cfg[SEC_AUX_PCM].channels; + break; + + case MSM_BACKEND_DAI_TERT_AUXPCM_RX: + rate->min = rate->max = + aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate; + channels->min = channels->max = + aux_pcm_rx_cfg[TERT_AUX_PCM].channels; + break; + + case MSM_BACKEND_DAI_TERT_AUXPCM_TX: + rate->min = rate->max = + aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate; + channels->min = channels->max = + aux_pcm_tx_cfg[TERT_AUX_PCM].channels; + break; + + case MSM_BACKEND_DAI_QUAT_AUXPCM_RX: + rate->min = rate->max = + aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate; + channels->min = channels->max = + aux_pcm_rx_cfg[QUAT_AUX_PCM].channels; + break; + + case MSM_BACKEND_DAI_QUAT_AUXPCM_TX: + rate->min = rate->max = + aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate; + channels->min = channels->max = + aux_pcm_tx_cfg[QUAT_AUX_PCM].channels; + break; + + case MSM_BACKEND_DAI_PRI_MI2S_RX: + rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate; + channels->min = channels->max = + mi2s_rx_cfg[PRIM_MI2S].channels; + break; + + case MSM_BACKEND_DAI_PRI_MI2S_TX: + rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate; + channels->min = channels->max = + mi2s_tx_cfg[PRIM_MI2S].channels; + break; + + case MSM_BACKEND_DAI_SECONDARY_MI2S_RX: + rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate; + channels->min = channels->max = + mi2s_rx_cfg[SEC_MI2S].channels; + break; + + case MSM_BACKEND_DAI_SECONDARY_MI2S_TX: + rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate; + channels->min = channels->max = + mi2s_tx_cfg[SEC_MI2S].channels; + break; + + case MSM_BACKEND_DAI_TERTIARY_MI2S_RX: + rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate; + channels->min = channels->max = + mi2s_rx_cfg[TERT_MI2S].channels; + break; + + case MSM_BACKEND_DAI_TERTIARY_MI2S_TX: + rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate; + channels->min = channels->max = + mi2s_tx_cfg[TERT_MI2S].channels; + break; + + case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX: + rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate; + channels->min = channels->max = + mi2s_rx_cfg[QUAT_MI2S].channels; + break; + + case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX: + rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate; + channels->min = channels->max = + mi2s_tx_cfg[QUAT_MI2S].channels; + break; + + default: + rate->min = rate->max = SAMPLING_RATE_48KHZ; + break; + } + return rc; +} +EXPORT_SYMBOL(msm_common_be_hw_params_fixup); + +/** + * msm_aux_pcm_snd_startup - startup ops of auxpcm. + * + * @substream: PCM stream pointer of associated backend dailink + * + * Returns 0 on success or -EINVAL on error. + */ +int msm_aux_pcm_snd_startup(struct snd_pcm_substream *substream) +{ + int ret = 0; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + int index = cpu_dai->id - 1; + return ret = 0; + + dev_dbg(rtd->card->dev, + "%s: substream = %s stream = %d, dai name %s, dai ID %d\n", + __func__, substream->name, substream->stream, + cpu_dai->name, cpu_dai->id); + + if (index < PRIM_AUX_PCM || index > QUAT_AUX_PCM) { + ret = -EINVAL; + dev_err(rtd->card->dev, + "%s: CPU DAI id (%d) out of range\n", + __func__, cpu_dai->id); + goto done; + } + + mutex_lock(&auxpcm_intf_conf[index].lock); + if (++auxpcm_intf_conf[index].ref_cnt == 1) { + if (mi2s_auxpcm_conf[index].pcm_i2s_sel_vt_addr != NULL) { + mutex_lock(&mi2s_auxpcm_conf[index].lock); + iowrite32(1, + mi2s_auxpcm_conf[index].pcm_i2s_sel_vt_addr); + mutex_unlock(&mi2s_auxpcm_conf[index].lock); + } else { + dev_err(rtd->card->dev, + "%s lpaif_tert_muxsel_virt_addr is NULL\n", + __func__); + ret = -EINVAL; + } + } + if (IS_ERR_VALUE(ret)) + auxpcm_intf_conf[index].ref_cnt--; + + mutex_unlock(&auxpcm_intf_conf[index].lock); + +done: + return ret; +} +EXPORT_SYMBOL(msm_aux_pcm_snd_startup); + +/** + * msm_aux_pcm_snd_shutdown - shutdown ops of auxpcm. + * + * @substream: PCM stream pointer of associated backend dailink + */ +void msm_aux_pcm_snd_shutdown(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + int index = rtd->cpu_dai->id - 1; + + dev_dbg(rtd->card->dev, + "%s: substream = %s stream = %d, dai name %s, dai ID %d\n", + __func__, + substream->name, substream->stream, + rtd->cpu_dai->name, rtd->cpu_dai->id); + + if (index < PRIM_AUX_PCM || index > QUAT_AUX_PCM) { + dev_err(rtd->card->dev, + "%s: CPU DAI id (%d) out of range\n", + __func__, rtd->cpu_dai->id); + return; + } + + mutex_lock(&auxpcm_intf_conf[index].lock); + if (--auxpcm_intf_conf[index].ref_cnt == 0) { + if (mi2s_auxpcm_conf[index].pcm_i2s_sel_vt_addr != NULL) { + mutex_lock(&mi2s_auxpcm_conf[index].lock); + iowrite32(0, + mi2s_auxpcm_conf[index].pcm_i2s_sel_vt_addr); + mutex_unlock(&mi2s_auxpcm_conf[index].lock); + } else { + dev_err(rtd->card->dev, + "%s lpaif_tert_muxsel_virt_addr is NULL\n", + __func__); + auxpcm_intf_conf[index].ref_cnt++; + } + } + mutex_unlock(&auxpcm_intf_conf[index].lock); +} +EXPORT_SYMBOL(msm_aux_pcm_snd_shutdown); + +static int msm_get_port_id(int be_id) +{ + int afe_port_id; + + switch (be_id) { + case MSM_BACKEND_DAI_PRI_MI2S_RX: + afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX; + break; + case MSM_BACKEND_DAI_PRI_MI2S_TX: + afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX; + break; + case MSM_BACKEND_DAI_SECONDARY_MI2S_RX: + afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX; + break; + case MSM_BACKEND_DAI_SECONDARY_MI2S_TX: + afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX; + break; + case MSM_BACKEND_DAI_TERTIARY_MI2S_RX: + afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX; + break; + case MSM_BACKEND_DAI_TERTIARY_MI2S_TX: + afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX; + break; + case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX: + afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX; + break; + case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX: + afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX; + break; + default: + pr_err("%s: Invalid be_id: %d\n", __func__, be_id); + afe_port_id = -EINVAL; + } + + return afe_port_id; +} + +static u32 get_mi2s_bits_per_sample(u32 bit_format) +{ + u32 bit_per_sample; + + switch (bit_format) { + case SNDRV_PCM_FORMAT_S24_3LE: + case SNDRV_PCM_FORMAT_S24_LE: + bit_per_sample = 32; + break; + case SNDRV_PCM_FORMAT_S16_LE: + default: + bit_per_sample = 16; + break; + } + + return bit_per_sample; +} + +static void update_mi2s_clk_val(int dai_id, int stream) +{ + u32 bit_per_sample; + + if (stream == SNDRV_PCM_STREAM_PLAYBACK) { + bit_per_sample = + get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format); + mi2s_clk[dai_id].clk_freq_in_hz = + mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample; + } else { + bit_per_sample = + get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format); + mi2s_clk[dai_id].clk_freq_in_hz = + mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample; + } + + if (!mi2s_intf_conf[dai_id].msm_is_mi2s_master) + mi2s_clk[dai_id].clk_freq_in_hz = 0; +} + +static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable) +{ + int ret = 0; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + int port_id = 0; + int index = cpu_dai->id; + + port_id = msm_get_port_id(rtd->dai_link->be_id); + if (IS_ERR_VALUE(port_id)) { + dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__); + ret = port_id; + goto done; + } + + if (enable) { + update_mi2s_clk_val(index, substream->stream); + dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__, + mi2s_clk[index].clk_freq_in_hz); + } + + mi2s_clk[index].enable = enable; + ret = afe_set_lpass_clock_v2(port_id, + &mi2s_clk[index]); + if (ret < 0) { + dev_err(rtd->card->dev, + "%s: afe lpass clock failed for port 0x%x , err:%d\n", + __func__, port_id, ret); + goto done; + } + +done: + return ret; +} + +/** + * msm_mi2s_snd_startup - startup ops of mi2s. + * + * @substream: PCM stream pointer of associated backend dailink + * + * Returns 0 on success or -EINVAL on error. + */ +int msm_mi2s_snd_startup(struct snd_pcm_substream *substream) +{ + int ret = 0; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + int index = cpu_dai->id; + unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS; + + dev_dbg(rtd->card->dev, + "%s: substream = %s stream = %d, dai name %s, dai ID %d\n", + __func__, substream->name, substream->stream, + cpu_dai->name, cpu_dai->id); + + if (index < PRIM_MI2S || index > QUAT_MI2S) { + ret = -EINVAL; + dev_err(rtd->card->dev, + "%s: CPU DAI id (%d) out of range\n", + __func__, cpu_dai->id); + goto done; + } + /* + * Muxtex protection in case the same MI2S + * interface using for both TX and RX so + * that the same clock won't be enable twice. + */ + mutex_lock(&mi2s_intf_conf[index].lock); + if (++mi2s_intf_conf[index].ref_cnt == 1) { + ret = msm_mi2s_set_sclk(substream, true); + if (IS_ERR_VALUE(ret)) { + dev_err(rtd->card->dev, + "%s: afe lpass clock failed to enable MI2S clock, err:%d\n", + __func__, ret); + goto clean_up; + } + if (mi2s_auxpcm_conf[index].pcm_i2s_sel_vt_addr != NULL) { + mutex_lock(&mi2s_auxpcm_conf[index].lock); + iowrite32(0, + mi2s_auxpcm_conf[index].pcm_i2s_sel_vt_addr); + mutex_unlock(&mi2s_auxpcm_conf[index].lock); + } else { + dev_err(rtd->card->dev, + "%s lpaif_muxsel_virt_addr is NULL for dai %d\n", + __func__, index); + ret = -EINVAL; + goto clk_off; + } + /* Check if msm needs to provide the clock to the interface */ + if (!mi2s_intf_conf[index].msm_is_mi2s_master) + fmt = SND_SOC_DAIFMT_CBM_CFM; + ret = snd_soc_dai_set_fmt(cpu_dai, fmt); + if (IS_ERR_VALUE(ret)) { + dev_err(rtd->card->dev, + "%s: set fmt cpu dai failed for MI2S (%d), err:%d\n", + __func__, index, ret); + goto clk_off; + } + } +clk_off: + if (IS_ERR_VALUE(ret)) + msm_mi2s_set_sclk(substream, false); +clean_up: + if (IS_ERR_VALUE(ret)) + mi2s_intf_conf[index].ref_cnt--; + mutex_unlock(&mi2s_intf_conf[index].lock); +done: + return ret; +} +EXPORT_SYMBOL(msm_mi2s_snd_startup); + +/** + * msm_mi2s_snd_shutdown - shutdown ops of mi2s. + * + * @substream: PCM stream pointer of associated backend dailink + */ +void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream) +{ + int ret; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + int index = rtd->cpu_dai->id; + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + if (index < PRIM_MI2S || index > QUAT_MI2S) { + pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index); + return; + } + + mutex_lock(&mi2s_intf_conf[index].lock); + if (--mi2s_intf_conf[index].ref_cnt == 0) { + ret = msm_mi2s_set_sclk(substream, false); + if (ret < 0) { + pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n", + __func__, index, ret); + mi2s_intf_conf[index].ref_cnt++; + } + } + mutex_unlock(&mi2s_intf_conf[index].lock); +} +EXPORT_SYMBOL(msm_mi2s_snd_shutdown); + +/* Validate whether US EU switch is present or not */ +static int msm_prepare_us_euro(struct snd_soc_card *card) +{ + struct msm_asoc_mach_data *pdata = + snd_soc_card_get_drvdata(card); + int ret = 0; + + if (pdata->us_euro_gpio >= 0) { + dev_dbg(card->dev, "%s: us_euro gpio request %d", __func__, + pdata->us_euro_gpio); + ret = gpio_request(pdata->us_euro_gpio, "TASHA_CODEC_US_EURO"); + if (ret) { + dev_err(card->dev, + "%s: Failed to request codec US/EURO gpio %d error %d\n", + __func__, pdata->us_euro_gpio, ret); + } + } + + return ret; +} + +static bool msm_swap_gnd_mic(struct snd_soc_codec *codec) +{ + struct snd_soc_card *card = codec->component.card; + struct msm_asoc_mach_data *pdata = + snd_soc_card_get_drvdata(card); + int value = 0; + + if (pdata->us_euro_gpio_p) { + value = msm_cdc_pinctrl_get_state(pdata->us_euro_gpio_p); + if (value) + msm_cdc_pinctrl_select_sleep_state( + pdata->us_euro_gpio_p); + else + msm_cdc_pinctrl_select_active_state( + pdata->us_euro_gpio_p); + } else if (pdata->us_euro_gpio >= 0) { + value = gpio_get_value_cansleep(pdata->us_euro_gpio); + gpio_set_value_cansleep(pdata->us_euro_gpio, !value); + } + pr_debug("%s: swap select switch %d to %d\n", __func__, value, !value); + return true; +} + +static int msm_populate_dai_link_component_of_node( + struct msm_asoc_mach_data *pdata, + struct snd_soc_card *card) +{ + int i, index, ret = 0; + struct device *cdev = card->dev; + struct snd_soc_dai_link *dai_link = card->dai_link; + struct device_node *phandle; + + if (!cdev) { + pr_err("%s: Sound card device memory NULL\n", __func__); + return -ENODEV; + } + + for (i = 0; i < card->num_links; i++) { + if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node) + continue; + + /* populate platform_of_node for snd card dai links */ + if (dai_link[i].platform_name && + !dai_link[i].platform_of_node) { + index = of_property_match_string(cdev->of_node, + "asoc-platform-names", + dai_link[i].platform_name); + if (index < 0) { + pr_err("%s: No match found for platform name: %s\n", + __func__, dai_link[i].platform_name); + ret = index; + goto cpu_dai; + } + phandle = of_parse_phandle(cdev->of_node, + "asoc-platform", + index); + if (!phandle) { + pr_err("%s: retrieving phandle for platform %s, index %d failed\n", + __func__, dai_link[i].platform_name, + index); + ret = -ENODEV; + goto err; + } + dai_link[i].platform_of_node = phandle; + dai_link[i].platform_name = NULL; + } +cpu_dai: + /* populate cpu_of_node for snd card dai links */ + if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) { + index = of_property_match_string(cdev->of_node, + "asoc-cpu-names", + dai_link[i].cpu_dai_name); + if (index < 0) + goto codec_dai; + phandle = of_parse_phandle(cdev->of_node, "asoc-cpu", + index); + if (!phandle) { + pr_err("%s: retrieving phandle for cpu dai %s failed\n", + __func__, dai_link[i].cpu_dai_name); + ret = -ENODEV; + goto err; + } + dai_link[i].cpu_of_node = phandle; + dai_link[i].cpu_dai_name = NULL; + } +codec_dai: + /* populate codec_of_node for snd card dai links */ + if (dai_link[i].codec_name && !dai_link[i].codec_of_node) { + index = of_property_match_string(cdev->of_node, + "asoc-codec-names", + dai_link[i].codec_name); + if (index < 0) + continue; + phandle = of_parse_phandle(cdev->of_node, "asoc-codec", + index); + if (!phandle) { + pr_err("%s: retrieving phandle for codec dai %s failed\n", + __func__, dai_link[i].codec_name); + ret = -ENODEV; + goto err; + } + dai_link[i].codec_of_node = phandle; + dai_link[i].codec_name = NULL; + } + if (pdata->snd_card_val == INT_SND_CARD) { + if ((dai_link[i].be_id == + MSM_BACKEND_DAI_INT0_MI2S_RX) || + (dai_link[i].be_id == + MSM_BACKEND_DAI_INT1_MI2S_RX) || + (dai_link[i].be_id == + MSM_BACKEND_DAI_INT2_MI2S_TX) || + (dai_link[i].be_id == + MSM_BACKEND_DAI_INT3_MI2S_TX)) { + index = of_property_match_string(cdev->of_node, + "asoc-codec-names", + MSM_INT_DIGITAL_CODEC); + phandle = of_parse_phandle(cdev->of_node, + "asoc-codec", + index); + dai_link[i].codecs[DIG_CDC].of_node = phandle; + index = of_property_match_string(cdev->of_node, + "asoc-codec-names", + PMIC_INT_ANALOG_CODEC); + phandle = of_parse_phandle(cdev->of_node, + "asoc-codec", + index); + dai_link[i].codecs[ANA_CDC].of_node = phandle; + } + } + } +err: + return ret; +} + +static int msm_wsa881x_init(struct snd_soc_component *component) +{ + u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {100, 101, 102, 106}; + u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {103, 104, 105, 107}; + unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200}; + unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3}; + struct snd_soc_codec *codec = snd_soc_component_to_codec(component); + struct msm_asoc_mach_data *pdata; + struct snd_soc_dapm_context *dapm = + snd_soc_codec_get_dapm(codec); + + if (!codec) { + pr_err("%s codec is NULL\n", __func__); + return -EINVAL; + } + + if (!strcmp(component->name_prefix, "SpkrLeft")) { + dev_dbg(codec->dev, "%s: setting left ch map to codec %s\n", + __func__, codec->component.name); + wsa881x_set_channel_map(codec, &spkleft_ports[0], + WSA881X_MAX_SWR_PORTS, &ch_mask[0], + &ch_rate[0]); + if (dapm->component) { + snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN"); + snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR"); + } + } else if (!strcmp(component->name_prefix, "SpkrRight")) { + dev_dbg(codec->dev, "%s: setting right ch map to codec %s\n", + __func__, codec->component.name); + wsa881x_set_channel_map(codec, &spkright_ports[0], + WSA881X_MAX_SWR_PORTS, &ch_mask[0], + &ch_rate[0]); + if (dapm->component) { + snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN"); + snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR"); + } + } else { + dev_err(codec->dev, "%s: wrong codec name %s\n", __func__, + codec->component.name); + return -EINVAL; + } + + + pdata = snd_soc_card_get_drvdata(component->card); + if (pdata && pdata->codec_root) + wsa881x_codec_info_create_codec_entry(pdata->codec_root, + codec); + return 0; +} + + +static int msm_init_wsa_dev(struct platform_device *pdev, + struct snd_soc_card *card) +{ + struct device_node *wsa_of_node; + u32 wsa_max_devs; + u32 wsa_dev_cnt; + char *dev_name_str = NULL; + struct msm_wsa881x_dev_info *wsa881x_dev_info; + const char *wsa_auxdev_name_prefix[1]; + int found = 0; + int i; + int ret; + + /* Get maximum WSA device count for this platform */ + ret = of_property_read_u32(pdev->dev.of_node, + "qcom,wsa-max-devs", &wsa_max_devs); + if (ret) { + dev_dbg(&pdev->dev, + "%s: wsa-max-devs property missing in DT %s, ret = %d\n", + __func__, pdev->dev.of_node->full_name, ret); + goto err_dt; + } + if (wsa_max_devs == 0) { + dev_warn(&pdev->dev, + "%s: Max WSA devices is 0 for this target?\n", + __func__); + goto err_dt; + } + + /* Get count of WSA device phandles for this platform */ + wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node, + "qcom,wsa-devs", NULL); + if (wsa_dev_cnt == -ENOENT) { + dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n", + __func__); + goto err_dt; + } else if (wsa_dev_cnt <= 0) { + dev_err(&pdev->dev, + "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n", + __func__, wsa_dev_cnt); + ret = -EINVAL; + goto err_dt; + } + + /* + * Expect total phandles count to be NOT less than maximum possible + * WSA count. However, if it is less, then assign same value to + * max count as well. + */ + if (wsa_dev_cnt < wsa_max_devs) { + dev_dbg(&pdev->dev, + "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n", + __func__, wsa_max_devs, wsa_dev_cnt); + wsa_max_devs = wsa_dev_cnt; + } + + /* Make sure prefix string passed for each WSA device */ + ret = of_property_count_strings(pdev->dev.of_node, + "qcom,wsa-aux-dev-prefix"); + if (ret != wsa_dev_cnt) { + dev_err(&pdev->dev, + "%s: expecting %d wsa prefix. Defined only %d in DT\n", + __func__, wsa_dev_cnt, ret); + ret = -EINVAL; + goto err_dt; + } + + /* + * Alloc mem to store phandle and index info of WSA device, if already + * registered with ALSA core + */ + wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs, + sizeof(struct msm_wsa881x_dev_info), + GFP_KERNEL); + if (!wsa881x_dev_info) { + ret = -ENOMEM; + goto err_mem; + } + + /* + * search and check whether all WSA devices are already + * registered with ALSA core or not. If found a node, store + * the node and the index in a local array of struct for later + * use. + */ + for (i = 0; i < wsa_dev_cnt; i++) { + wsa_of_node = of_parse_phandle(pdev->dev.of_node, + "qcom,wsa-devs", i); + if (unlikely(!wsa_of_node)) { + /* we should not be here */ + dev_err(&pdev->dev, + "%s: wsa dev node is not present\n", + __func__); + ret = -EINVAL; + goto err_dev_node; + } + if (soc_find_component(wsa_of_node, NULL)) { + /* WSA device registered with ALSA core */ + wsa881x_dev_info[found].of_node = wsa_of_node; + wsa881x_dev_info[found].index = i; + found++; + if (found == wsa_max_devs) + break; + } + } + + if (found < wsa_max_devs) { + dev_dbg(&pdev->dev, + "%s: failed to find %d components. Found only %d\n", + __func__, wsa_max_devs, found); + return -EPROBE_DEFER; + } + dev_info(&pdev->dev, + "%s: found %d wsa881x devices registered with ALSA core\n", + __func__, found); + + card->num_aux_devs = wsa_max_devs; + card->num_configs = wsa_max_devs; + + /* Alloc array of AUX devs struct */ + msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs, + sizeof(struct snd_soc_aux_dev), + GFP_KERNEL); + if (!msm_aux_dev) { + ret = -ENOMEM; + goto err_auxdev_mem; + } + + /* Alloc array of codec conf struct */ + msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs, + sizeof(struct snd_soc_codec_conf), + GFP_KERNEL); + if (!msm_codec_conf) { + ret = -ENOMEM; + goto err_codec_conf; + } + + for (i = 0; i < card->num_aux_devs; i++) { + dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN, + GFP_KERNEL); + if (!dev_name_str) { + ret = -ENOMEM; + goto err_dev_str; + } + + ret = of_property_read_string_index(pdev->dev.of_node, + "qcom,wsa-aux-dev-prefix", + wsa881x_dev_info[i].index, + wsa_auxdev_name_prefix); + if (ret) { + dev_err(&pdev->dev, + "%s: failed to read wsa aux dev prefix, ret = %d\n", + __func__, ret); + ret = -EINVAL; + goto err_dt_prop; + } + + snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i); + msm_aux_dev[i].name = dev_name_str; + msm_aux_dev[i].codec_name = NULL; + msm_aux_dev[i].codec_of_node = + wsa881x_dev_info[i].of_node; + msm_aux_dev[i].init = msm_wsa881x_init; + msm_codec_conf[i].dev_name = NULL; + msm_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0]; + msm_codec_conf[i].of_node = wsa881x_dev_info[i].of_node; + } + card->codec_conf = msm_codec_conf; + card->aux_dev = msm_aux_dev; + + return 0; + +err_dt_prop: + devm_kfree(&pdev->dev, dev_name_str); +err_dev_str: + devm_kfree(&pdev->dev, msm_codec_conf); +err_codec_conf: + devm_kfree(&pdev->dev, msm_aux_dev); +err_auxdev_mem: +err_dev_node: + devm_kfree(&pdev->dev, wsa881x_dev_info); +err_mem: +err_dt: + return ret; +} + +static void msm_free_auxdev_mem(struct platform_device *pdev) +{ + struct snd_soc_card *card = platform_get_drvdata(pdev); + int i; + + if (card->num_aux_devs > 0) { + for (i = 0; i < card->num_aux_devs; i++) { + kfree(msm_aux_dev[i].codec_name); + kfree(msm_codec_conf[i].dev_name); + kfree(msm_codec_conf[i].name_prefix); + } + } +} + +static void i2s_auxpcm_init(struct platform_device *pdev) +{ + struct resource *muxsel; + int count; + u32 mi2s_master_slave[MI2S_MAX]; + int ret; + char *str[PCM_I2S_SEL_MAX] = { + "lpaif_pri_mode_muxsel", + "lpaif_sec_mode_muxsel", + "lpaif_tert_mode_muxsel", + "lpaif_quat_mode_muxsel" + }; + + for (count = 0; count < MI2S_MAX; count++) { + mutex_init(&mi2s_intf_conf[count].lock); + mi2s_intf_conf[count].ref_cnt = 0; + } + + for (count = 0; count < AUX_PCM_MAX; count++) { + mutex_init(&auxpcm_intf_conf[count].lock); + auxpcm_intf_conf[count].ref_cnt = 0; + } + + for (count = 0; count < PCM_I2S_SEL_MAX; count++) { + mutex_init(&mi2s_auxpcm_conf[count].lock); + mi2s_auxpcm_conf[count].pcm_i2s_sel_vt_addr = NULL; + } + + for (count = 0; count < PCM_I2S_SEL_MAX; count++) { + muxsel = platform_get_resource_byname(pdev, IORESOURCE_MEM, + str[count]); + if (muxsel) { + mi2s_auxpcm_conf[count].pcm_i2s_sel_vt_addr + = ioremap(muxsel->start, resource_size(muxsel)); + } + } + + ret = of_property_read_u32_array(pdev->dev.of_node, + "qcom,msm-mi2s-master", + mi2s_master_slave, MI2S_MAX); + if (ret) { + dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n", + __func__); + } else { + for (count = 0; count < MI2S_MAX; count++) { + mi2s_intf_conf[count].msm_is_mi2s_master = + mi2s_master_slave[count]; + } + } +} + +static void i2s_auxpcm_deinit(void) +{ + int count; + + for (count = 0; count < PCM_I2S_SEL_MAX; count++) + if (mi2s_auxpcm_conf[count].pcm_i2s_sel_vt_addr != + NULL) + iounmap( + mi2s_auxpcm_conf[count].pcm_i2s_sel_vt_addr); +} + +static const struct of_device_id sdm660_asoc_machine_of_match[] = { + { .compatible = "qcom,sdm660-asoc-snd", + .data = "internal_codec"}, + { .compatible = "qcom,sdm660-asoc-snd-tasha", + .data = "tasha_codec"}, + { .compatible = "qcom,sdm660-asoc-snd-tavil", + .data = "tavil_codec"}, + {}, +}; + +static int msm_asoc_machine_probe(struct platform_device *pdev) +{ + struct snd_soc_card *card = NULL; + struct msm_asoc_mach_data *pdata = NULL; + const char *mclk = "qcom,msm-mclk-freq"; + int ret = -EINVAL, id; + const struct of_device_id *match; + + pdata = devm_kzalloc(&pdev->dev, + sizeof(struct msm_asoc_mach_data), + GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + match = of_match_node(sdm660_asoc_machine_of_match, + pdev->dev.of_node); + if (!match) + goto err; + + ret = of_property_read_u32(pdev->dev.of_node, mclk, &id); + if (ret) { + dev_err(&pdev->dev, + "%s: missing %s in dt node\n", __func__, mclk); + id = DEFAULT_MCLK_RATE; + } + pdata->mclk_freq = id; + + if (!strcmp(match->data, "tasha_codec") || + !strcmp(match->data, "tavil_codec")) { + if (!strcmp(match->data, "tasha_codec")) + pdata->snd_card_val = EXT_SND_CARD_TASHA; + else + pdata->snd_card_val = EXT_SND_CARD_TAVIL; + ret = msm_ext_cdc_init(pdev, pdata, &card, &mbhc_cfg); + if (ret) + goto err; + } else if (!strcmp(match->data, "internal_codec")) { + pdata->snd_card_val = INT_SND_CARD; + ret = msm_int_cdc_init(pdev, pdata, &card, &mbhc_cfg); + if (ret) + goto err; + } else { + dev_err(&pdev->dev, + "%s: Not a matching DT sound node\n", __func__); + goto err; + } + if (!card) + goto err; + + if (pdata->snd_card_val == INT_SND_CARD) { + /*reading the gpio configurations from dtsi file*/ + pdata->pdm_gpio_p = of_parse_phandle(pdev->dev.of_node, + "qcom,cdc-pdm-gpios", 0); + pdata->comp_gpio_p = of_parse_phandle(pdev->dev.of_node, + "qcom,cdc-comp-gpios", 0); + pdata->sdw_gpio_p = of_parse_phandle(pdev->dev.of_node, + "qcom,cdc-sdw-gpios", 0); + pdata->dmic_gpio_p = of_parse_phandle(pdev->dev.of_node, + "qcom,cdc-dmic-gpios", 0); + pdata->ext_spk_gpio_p = of_parse_phandle(pdev->dev.of_node, + "qcom,cdc-ext-spk-gpios", 0); + } + + /* + * Parse US-Euro gpio info from DT. Report no error if us-euro + * entry is not found in DT file as some targets do not support + * US-Euro detection + */ + pdata->us_euro_gpio = of_get_named_gpio(pdev->dev.of_node, + "qcom,us-euro-gpios", 0); + if (!gpio_is_valid(pdata->us_euro_gpio)) + pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node, + "qcom,us-euro-gpios", 0); + if (!gpio_is_valid(pdata->us_euro_gpio) && (!pdata->us_euro_gpio_p)) { + dev_dbg(&pdev->dev, "property %s not detected in node %s", + "qcom,us-euro-gpios", pdev->dev.of_node->full_name); + } else { + dev_dbg(&pdev->dev, "%s detected", + "qcom,us-euro-gpios"); + mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic; + } + + ret = msm_prepare_us_euro(card); + if (ret) + dev_dbg(&pdev->dev, "msm_prepare_us_euro failed (%d)\n", + ret); + + i2s_auxpcm_init(pdev); + + ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing"); + if (ret) + goto err; + + ret = msm_populate_dai_link_component_of_node(pdata, card); + if (ret) { + ret = -EPROBE_DEFER; + goto err; + } + ret = msm_init_wsa_dev(pdev, card); + if (ret) + goto err; + + + ret = devm_snd_soc_register_card(&pdev->dev, card); + if (ret) { + dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", + ret); + goto err; + } + return 0; +err: + if (pdata->us_euro_gpio > 0) { + dev_dbg(&pdev->dev, "%s free us_euro gpio %d\n", + __func__, pdata->us_euro_gpio); + pdata->us_euro_gpio = 0; + } + if (pdata->hph_en1_gpio > 0) { + dev_dbg(&pdev->dev, "%s free hph_en1_gpio %d\n", + __func__, pdata->hph_en1_gpio); + gpio_free(pdata->hph_en1_gpio); + pdata->hph_en1_gpio = 0; + } + if (pdata->hph_en0_gpio > 0) { + dev_dbg(&pdev->dev, "%s free hph_en0_gpio %d\n", + __func__, pdata->hph_en0_gpio); + gpio_free(pdata->hph_en0_gpio); + pdata->hph_en0_gpio = 0; + } + devm_kfree(&pdev->dev, pdata); + if (pdata->snd_card_val != INT_SND_CARD) + msm_ext_cdc_deinit(); + return ret; +} + +static int msm_asoc_machine_remove(struct platform_device *pdev) +{ + struct snd_soc_card *card = platform_get_drvdata(pdev); + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + + if (pdata->snd_card_val == INT_SND_CARD) + mutex_destroy(&pdata->cdc_int_mclk0_mutex); + else + msm_ext_cdc_deinit(); + msm_free_auxdev_mem(pdev); + + gpio_free(pdata->us_euro_gpio); + gpio_free(pdata->hph_en1_gpio); + gpio_free(pdata->hph_en0_gpio); + i2s_auxpcm_deinit(); + snd_soc_unregister_card(card); + return 0; +} + +static struct platform_driver sdm660_asoc_machine_driver = { + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + .pm = &snd_soc_pm_ops, + .of_match_table = sdm660_asoc_machine_of_match, + }, + .probe = msm_asoc_machine_probe, + .remove = msm_asoc_machine_remove, +}; +module_platform_driver(sdm660_asoc_machine_driver); + +MODULE_DESCRIPTION("ALSA SoC msm"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRV_NAME); +MODULE_DEVICE_TABLE(of, sdm660_asoc_machine_of_match); diff --git a/sound/soc/msm/sdm660-common.h b/sound/soc/msm/sdm660-common.h new file mode 100644 index 000000000000..71b6a0786549 --- /dev/null +++ b/sound/soc/msm/sdm660-common.h @@ -0,0 +1,115 @@ +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_COMMON +#define __MSM_COMMON + +#include +#include +#include "../codecs/wcd-mbhc-v2.h" + +#define SAMPLING_RATE_8KHZ 8000 +#define SAMPLING_RATE_11P025KHZ 11025 +#define SAMPLING_RATE_16KHZ 16000 +#define SAMPLING_RATE_22P05KHZ 22050 +#define SAMPLING_RATE_32KHZ 32000 +#define SAMPLING_RATE_44P1KHZ 44100 +#define SAMPLING_RATE_48KHZ 48000 +#define SAMPLING_RATE_88P2KHZ 88200 +#define SAMPLING_RATE_96KHZ 96000 +#define SAMPLING_RATE_176P4KHZ 176400 +#define SAMPLING_RATE_192KHZ 192000 +#define SAMPLING_RATE_352P8KHZ 352800 +#define SAMPLING_RATE_384KHZ 384000 + +#define TDM_CHANNEL_MAX 8 +#define TDM_SLOT_OFFSET_MAX 8 + +enum { + TDM_0 = 0, + TDM_1, + TDM_2, + TDM_3, + TDM_4, + TDM_5, + TDM_6, + TDM_7, + TDM_PORT_MAX, +}; + +enum { + TDM_PRI = 0, + TDM_SEC, + TDM_TERT, + TDM_QUAT, + TDM_INTERFACE_MAX, +}; + +struct tdm_port { + u32 mode; + u32 channel; +}; + +enum { + DIG_CDC, + ANA_CDC, + CODECS_MAX, +}; + +extern const struct snd_kcontrol_new msm_common_snd_controls[]; +struct sdm660_codec { + void* (*get_afe_config_fn)(struct snd_soc_codec *codec, + enum afe_config_type config_type); +}; + +enum { + INT_SND_CARD, + EXT_SND_CARD_TASHA, + EXT_SND_CARD_TAVIL, +}; + +struct msm_asoc_mach_data { + int us_euro_gpio; /* used by gpio driver API */ + int hph_en1_gpio; + int hph_en0_gpio; + struct device_node *us_euro_gpio_p; /* used by pinctrl API */ + struct device_node *hph_en1_gpio_p; /* used by pinctrl API */ + struct device_node *hph_en0_gpio_p; /* used by pinctrl API */ + struct device_node *pdm_gpio_p; /* used by pinctrl API */ + struct device_node *comp_gpio_p; /* used by pinctrl API */ + struct device_node *sdw_gpio_p; /* used by pinctrl API */ + struct device_node *dmic_gpio_p; /* used by pinctrl API */ + struct device_node *ext_spk_gpio_p; /* used by pinctrl API */ + struct snd_soc_codec *codec; + struct sdm660_codec sdm660_codec_fn; + struct snd_info_entry *codec_root; + int spk_ext_pa_gpio; + int mclk_freq; + bool native_clk_set; + int lb_mode; + int snd_card_val; + u8 micbias1_cap_mode; + u8 micbias2_cap_mode; + atomic_t int_mclk0_rsc_ref; + atomic_t int_mclk0_enabled; + struct mutex cdc_int_mclk0_mutex; + struct delayed_work disable_int_mclk0_work; + struct afe_clk_set digital_cdc_core_clk; +}; + +int msm_common_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_aux_pcm_snd_startup(struct snd_pcm_substream *substream); +void msm_aux_pcm_snd_shutdown(struct snd_pcm_substream *substream); +int msm_mi2s_snd_startup(struct snd_pcm_substream *substream); +void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream); +#endif diff --git a/sound/soc/msm/sdm660-ext-dai-links.c b/sound/soc/msm/sdm660-ext-dai-links.c new file mode 100644 index 000000000000..3e29221fe00f --- /dev/null +++ b/sound/soc/msm/sdm660-ext-dai-links.c @@ -0,0 +1,1968 @@ +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "qdsp6v2/msm-pcm-routing-v2.h" +#include "../codecs/wcd9335.h" +#include "sdm660-common.h" +#include "sdm660-external.h" + +#define DEV_NAME_STR_LEN 32 +#define __CHIPSET__ "SDM660 " +#define MSM_DAILINK_NAME(name) (__CHIPSET__#name) + +#define WCN_CDC_SLIM_RX_CH_MAX 2 +#define WCN_CDC_SLIM_TX_CH_MAX 3 + +static struct snd_soc_card snd_soc_card_msm_card_tavil; +static struct snd_soc_card snd_soc_card_msm_card_tasha; + +static struct snd_soc_ops msm_ext_slimbus_be_ops = { + .hw_params = msm_snd_hw_params, +}; + +static struct snd_soc_ops msm_ext_cpe_ops = { + .hw_params = msm_snd_cpe_hw_params, +}; + +static struct snd_soc_ops msm_ext_slimbus_2_be_ops = { + .hw_params = msm_ext_slimbus_2_hw_params, +}; + +static struct snd_soc_ops msm_mi2s_be_ops = { + .startup = msm_mi2s_snd_startup, + .shutdown = msm_mi2s_snd_shutdown, +}; + +static struct snd_soc_ops msm_aux_pcm_be_ops = { + .startup = msm_aux_pcm_snd_startup, + .shutdown = msm_aux_pcm_snd_shutdown, +}; + +static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd) +{ + unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158}; + unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161}; + struct snd_soc_dai *codec_dai = rtd->codec_dai; + + return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch), + tx_ch, ARRAY_SIZE(rx_ch), rx_ch); +} + +static int msm_wcn_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *codec_dai = rtd->codec_dai; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct snd_soc_dai_link *dai_link = rtd->dai_link; + u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX]; + u32 rx_ch_cnt = 0, tx_ch_cnt = 0; + int ret; + + dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__, + codec_dai->name, codec_dai->id); + ret = snd_soc_dai_get_channel_map(codec_dai, + &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch); + if (ret) { + dev_err(rtd->dev, + "%s: failed to get BTFM codec chan map\n, err:%d\n", + __func__, ret); + goto exit; + } + + dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) be_id %d\n", + __func__, tx_ch_cnt, dai_link->be_id); + + ret = snd_soc_dai_set_channel_map(cpu_dai, + tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch); + if (ret) + dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n", + __func__, ret); + +exit: + return ret; +} + +static struct snd_soc_ops msm_wcn_ops = { + .hw_params = msm_wcn_hw_params, +}; + +/*TDM default offset currently only supporting TDM_RX_0 and TDM_TX_0 */ +static unsigned int tdm_slot_offset[TDM_PORT_MAX][TDM_SLOT_OFFSET_MAX] = { + {0, 4, 8, 12, 16, 20, 24, 28},/* TX_0 | RX_0 */ + {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_1 | RX_1 */ + {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_2 | RX_2 */ + {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_3 | RX_3 */ + {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_4 | RX_4 */ + {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_5 | RX_5 */ + {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_6 | RX_6 */ + {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_7 | RX_7 */ +}; + +static unsigned int tdm_param_set_slot_mask(u16 port_id, int slot_width, + int slots) +{ + unsigned int slot_mask = 0; + int i, j; + unsigned int *slot_offset; + + for (i = TDM_0; i < TDM_PORT_MAX; i++) { + slot_offset = tdm_slot_offset[i]; + + for (j = 0; j < TDM_SLOT_OFFSET_MAX; j++) { + if (slot_offset[j] != AFE_SLOT_MAPPING_OFFSET_INVALID) + slot_mask |= + (1 << ((slot_offset[j] * 8) / slot_width)); + else + break; + } + } + + return slot_mask; +} + +static int msm_tdm_snd_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + int ret = 0; + int channels, slot_width, slots; + unsigned int slot_mask; + unsigned int *slot_offset; + int offset_channels = 0; + int i; + + pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id); + + channels = params_channels(params); + switch (channels) { + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S32_LE: + case SNDRV_PCM_FORMAT_S24_LE: + case SNDRV_PCM_FORMAT_S16_LE: + /* + * up to 8 channels HW config should + * use 32 bit slot width for max support of + * stream bit width. (slot_width > bit_width) + */ + slot_width = 32; + break; + default: + pr_err("%s: invalid param format 0x%x\n", + __func__, params_format(params)); + return -EINVAL; + } + slots = 8; + slot_mask = tdm_param_set_slot_mask(cpu_dai->id, + slot_width, + slots); + if (!slot_mask) { + pr_err("%s: invalid slot_mask 0x%x\n", + __func__, slot_mask); + return -EINVAL; + } + break; + default: + pr_err("%s: invalid param channels %d\n", + __func__, channels); + return -EINVAL; + } + /* currently only supporting TDM_RX_0 and TDM_TX_0 */ + switch (cpu_dai->id) { + case AFE_PORT_ID_PRIMARY_TDM_RX: + case AFE_PORT_ID_SECONDARY_TDM_RX: + case AFE_PORT_ID_TERTIARY_TDM_RX: + case AFE_PORT_ID_QUATERNARY_TDM_RX: + case AFE_PORT_ID_PRIMARY_TDM_TX: + case AFE_PORT_ID_SECONDARY_TDM_TX: + case AFE_PORT_ID_TERTIARY_TDM_TX: + case AFE_PORT_ID_QUATERNARY_TDM_TX: + slot_offset = tdm_slot_offset[TDM_0]; + break; + default: + pr_err("%s: dai id 0x%x not supported\n", + __func__, cpu_dai->id); + return -EINVAL; + } + + for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) { + if (slot_offset[i] != AFE_SLOT_MAPPING_OFFSET_INVALID) + offset_channels++; + else + break; + } + + if (offset_channels == 0) { + pr_err("%s: slot offset not supported, offset_channels %d\n", + __func__, offset_channels); + return -EINVAL; + } + + if (channels > offset_channels) { + pr_err("%s: channels %d exceed offset_channels %d\n", + __func__, channels, offset_channels); + return -EINVAL; + } + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask, + slots, slot_width); + if (ret < 0) { + pr_err("%s: failed to set tdm slot, err:%d\n", + __func__, ret); + goto end; + } + + ret = snd_soc_dai_set_channel_map(cpu_dai, 0, NULL, + channels, slot_offset); + if (ret < 0) { + pr_err("%s: failed to set channel map, err:%d\n", + __func__, ret); + goto end; + } + } else { + ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0, + slots, slot_width); + if (ret < 0) { + pr_err("%s: failed to set tdm slot, err:%d\n", + __func__, ret); + goto end; + } + + ret = snd_soc_dai_set_channel_map(cpu_dai, channels, + slot_offset, 0, NULL); + if (ret < 0) { + pr_err("%s: failed to set channel map, err:%d\n", + __func__, ret); + goto end; + } + } +end: + return ret; +} + +static struct snd_soc_ops msm_tdm_be_ops = { + .hw_params = msm_tdm_snd_hw_params +}; + +static struct snd_soc_dai_link msm_ext_tasha_fe_dai[] = { + /* tasha_vifeedback for speaker protection */ + { + .name = LPASS_BE_SLIMBUS_4_TX, + .stream_name = "Slimbus4 Capture", + .cpu_dai_name = "msm-dai-q6-dev.16393", + .platform_name = "msm-pcm-hostless", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_vifeedback", + .be_id = MSM_BACKEND_DAI_SLIMBUS_4_TX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ops = &msm_ext_slimbus_be_ops, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + }, + /* Ultrasound RX DAI Link */ + { + .name = "SLIMBUS_2 Hostless Playback", + .stream_name = "SLIMBUS_2 Hostless Playback", + .cpu_dai_name = "msm-dai-q6-dev.16388", + .platform_name = "msm-pcm-hostless", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_rx2", + .ignore_suspend = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ops = &msm_ext_slimbus_2_be_ops, + }, + /* Ultrasound TX DAI Link */ + { + .name = "SLIMBUS_2 Hostless Capture", + .stream_name = "SLIMBUS_2 Hostless Capture", + .cpu_dai_name = "msm-dai-q6-dev.16389", + .platform_name = "msm-pcm-hostless", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_tx2", + .ignore_suspend = 1, + .dpcm_capture = 1, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ops = &msm_ext_slimbus_2_be_ops, + }, + /* CPE LSM direct dai-link */ + { + .name = "CPE Listen service", + .stream_name = "CPE Listen Audio Service", + .cpu_dai_name = "msm-dai-slim", + .platform_name = "msm-cpe-lsm", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .dpcm_capture = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "tasha_mad1", + .codec_name = "tasha_codec", + .ops = &msm_ext_cpe_ops, + }, + { + .name = "SLIMBUS_6 Hostless Playback", + .stream_name = "SLIMBUS_6 Hostless", + .cpu_dai_name = "SLIMBUS6_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dailink has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + /* CPE LSM EC PP direct dai-link */ + { + .name = "CPE Listen service ECPP", + .stream_name = "CPE Listen Audio Service ECPP", + .cpu_dai_name = "CPE_LSM_NOHOST", + .platform_name = "msm-cpe-lsm.3", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "tasha_cpe", + .codec_name = "tasha_codec", + }, +}; + +static struct snd_soc_dai_link msm_ext_tavil_fe_dai[] = { + { + .name = LPASS_BE_SLIMBUS_4_TX, + .stream_name = "Slimbus4 Capture", + .cpu_dai_name = "msm-dai-q6-dev.16393", + .platform_name = "msm-pcm-hostless", + .codec_name = "tavil_codec", + .codec_dai_name = "tavil_vifeedback", + .be_id = MSM_BACKEND_DAI_SLIMBUS_4_TX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ops = &msm_ext_slimbus_be_ops, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + }, + /* Ultrasound RX DAI Link */ + { + .name = "SLIMBUS_2 Hostless Playback", + .stream_name = "SLIMBUS_2 Hostless Playback", + .cpu_dai_name = "msm-dai-q6-dev.16388", + .platform_name = "msm-pcm-hostless", + .codec_name = "tavil_codec", + .codec_dai_name = "tavil_rx2", + .ignore_suspend = 1, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ops = &msm_ext_slimbus_2_be_ops, + }, + /* Ultrasound TX DAI Link */ + { + .name = "SLIMBUS_2 Hostless Capture", + .stream_name = "SLIMBUS_2 Hostless Capture", + .cpu_dai_name = "msm-dai-q6-dev.16389", + .platform_name = "msm-pcm-hostless", + .codec_name = "tavil_codec", + .codec_dai_name = "tavil_tx2", + .ignore_suspend = 1, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ops = &msm_ext_slimbus_2_be_ops, + }, +}; + +static struct snd_soc_dai_link msm_ext_tasha_be_dai[] = { + /* Backend DAI Links */ + { + .name = LPASS_BE_SLIMBUS_0_RX, + .stream_name = "Slimbus Playback", + .cpu_dai_name = "msm-dai-q6-dev.16384", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_mix_rx1", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_0_RX, + .init = &msm_audrx_init, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + .ops = &msm_ext_slimbus_be_ops, + }, + { + .name = LPASS_BE_SLIMBUS_0_TX, + .stream_name = "Slimbus Capture", + .cpu_dai_name = "msm-dai-q6-dev.16385", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_tx1", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_0_TX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ignore_suspend = 1, + .ops = &msm_ext_slimbus_be_ops, + }, + { + .name = LPASS_BE_SLIMBUS_1_RX, + .stream_name = "Slimbus1 Playback", + .cpu_dai_name = "msm-dai-q6-dev.16386", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_mix_rx1", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_1_RX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ops = &msm_ext_slimbus_be_ops, + /* dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_1_TX, + .stream_name = "Slimbus1 Capture", + .cpu_dai_name = "msm-dai-q6-dev.16387", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_tx3", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_1_TX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ops = &msm_ext_slimbus_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_3_RX, + .stream_name = "Slimbus3 Playback", + .cpu_dai_name = "msm-dai-q6-dev.16390", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_mix_rx1", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_3_RX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ops = &msm_ext_slimbus_be_ops, + /* dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_3_TX, + .stream_name = "Slimbus3 Capture", + .cpu_dai_name = "msm-dai-q6-dev.16391", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_tx1", + .no_pcm = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_3_TX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ops = &msm_ext_slimbus_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_4_RX, + .stream_name = "Slimbus4 Playback", + .cpu_dai_name = "msm-dai-q6-dev.16392", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_mix_rx1", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_4_RX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ops = &msm_ext_slimbus_be_ops, + /* dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_5_RX, + .stream_name = "Slimbus5 Playback", + .cpu_dai_name = "msm-dai-q6-dev.16394", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_rx3", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_5_RX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ops = &msm_ext_slimbus_be_ops, + /* dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + /* MAD BE */ + { + .name = LPASS_BE_SLIMBUS_5_TX, + .stream_name = "Slimbus5 Capture", + .cpu_dai_name = "msm-dai-q6-dev.16395", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_mad1", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_5_TX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ops = &msm_ext_slimbus_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_6_RX, + .stream_name = "Slimbus6 Playback", + .cpu_dai_name = "msm-dai-q6-dev.16396", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_rx4", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_6_RX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ops = &msm_ext_slimbus_be_ops, + /* dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm_ext_tavil_be_dai[] = { + { + .name = LPASS_BE_SLIMBUS_0_RX, + .stream_name = "Slimbus Playback", + .cpu_dai_name = "msm-dai-q6-dev.16384", + .platform_name = "msm-pcm-routing", + .codec_name = "tavil_codec", + .codec_dai_name = "tavil_rx1", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_0_RX, + .init = &msm_audrx_init, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + .ops = &msm_ext_slimbus_be_ops, + }, + { + .name = LPASS_BE_SLIMBUS_0_TX, + .stream_name = "Slimbus Capture", + .cpu_dai_name = "msm-dai-q6-dev.16385", + .platform_name = "msm-pcm-routing", + .codec_name = "tavil_codec", + .codec_dai_name = "tavil_tx1", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_0_TX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ignore_suspend = 1, + .ops = &msm_ext_slimbus_be_ops, + }, + { + .name = LPASS_BE_SLIMBUS_1_RX, + .stream_name = "Slimbus1 Playback", + .cpu_dai_name = "msm-dai-q6-dev.16386", + .platform_name = "msm-pcm-routing", + .codec_name = "tavil_codec", + .codec_dai_name = "tavil_rx1", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_1_RX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ops = &msm_ext_slimbus_be_ops, + /* dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_1_TX, + .stream_name = "Slimbus1 Capture", + .cpu_dai_name = "msm-dai-q6-dev.16387", + .platform_name = "msm-pcm-routing", + .codec_name = "tavil_codec", + .codec_dai_name = "tavil_tx3", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_1_TX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ops = &msm_ext_slimbus_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_2_RX, + .stream_name = "Slimbus2 Playback", + .cpu_dai_name = "msm-dai-q6-dev.16388", + .platform_name = "msm-pcm-routing", + .codec_name = "tavil_codec", + .codec_dai_name = "tavil_rx2", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_2_RX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ops = &msm_ext_slimbus_be_ops, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_3_RX, + .stream_name = "Slimbus3 Playback", + .cpu_dai_name = "msm-dai-q6-dev.16390", + .platform_name = "msm-pcm-routing", + .codec_name = "tavil_codec", + .codec_dai_name = "tavil_rx1", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_3_RX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ops = &msm_ext_slimbus_be_ops, + /* dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_3_TX, + .stream_name = "Slimbus3 Capture", + .cpu_dai_name = "msm-dai-q6-dev.16391", + .platform_name = "msm-pcm-routing", + .codec_name = "tavil_codec", + .codec_dai_name = "tavil_tx1", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_3_TX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ops = &msm_ext_slimbus_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_4_RX, + .stream_name = "Slimbus4 Playback", + .cpu_dai_name = "msm-dai-q6-dev.16392", + .platform_name = "msm-pcm-routing", + .codec_name = "tavil_codec", + .codec_dai_name = "tavil_rx1", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_4_RX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ops = &msm_ext_slimbus_be_ops, + /* dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_5_RX, + .stream_name = "Slimbus5 Playback", + .cpu_dai_name = "msm-dai-q6-dev.16394", + .platform_name = "msm-pcm-routing", + .codec_name = "tavil_codec", + .codec_dai_name = "tavil_rx3", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_5_RX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ops = &msm_ext_slimbus_be_ops, + /* dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + /* MAD BE */ + { + .name = LPASS_BE_SLIMBUS_5_TX, + .stream_name = "Slimbus5 Capture", + .cpu_dai_name = "msm-dai-q6-dev.16395", + .platform_name = "msm-pcm-routing", + .codec_name = "tavil_codec", + .codec_dai_name = "tavil_mad1", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_5_TX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ops = &msm_ext_slimbus_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_6_RX, + .stream_name = "Slimbus6 Playback", + .cpu_dai_name = "msm-dai-q6-dev.16396", + .platform_name = "msm-pcm-routing", + .codec_name = "tavil_codec", + .codec_dai_name = "tavil_rx4", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_6_RX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ops = &msm_ext_slimbus_be_ops, + /* dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm_ext_common_fe_dai[] = { + /* FrontEnd DAI Links */ + {/* hw:x,0 */ + .name = MSM_DAILINK_NAME(Media1), + .stream_name = "MultiMedia1", + .cpu_dai_name = "MultiMedia1", + .platform_name = "msm-pcm-dsp.0", + .dynamic = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA1 + }, + {/* hw:x,1 */ + .name = MSM_DAILINK_NAME(Media2), + .stream_name = "MultiMedia2", + .cpu_dai_name = "MultiMedia2", + .platform_name = "msm-pcm-dsp.0", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA2, + }, + {/* hw:x,2 */ + .name = "VoiceMMode1", + .stream_name = "VoiceMMode1", + .cpu_dai_name = "VoiceMMode1", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .be_id = MSM_FRONTEND_DAI_VOICEMMODE1, + }, + {/* hw:x,3 */ + .name = "MSM VoIP", + .stream_name = "VoIP", + .cpu_dai_name = "VoIP", + .platform_name = "msm-voip-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .be_id = MSM_FRONTEND_DAI_VOIP, + }, + {/* hw:x,4 */ + .name = MSM_DAILINK_NAME(ULL), + .stream_name = "ULL", + .cpu_dai_name = "MultiMedia3", + .platform_name = "msm-pcm-dsp.2", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA3, + }, + /* Hostless PCM purpose */ + {/* hw:x,5 */ + .name = "SLIMBUS_0 Hostless", + .stream_name = "SLIMBUS_0 Hostless", + .cpu_dai_name = "SLIMBUS0_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* This dai link has MI2S support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,6 */ + .name = "MSM AFE-PCM RX", + .stream_name = "AFE-PROXY RX", + .cpu_dai_name = "msm-dai-q6-dev.241", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .platform_name = "msm-pcm-afe", + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + }, + {/* hw:x,7 */ + .name = "MSM AFE-PCM TX", + .stream_name = "AFE-PROXY TX", + .cpu_dai_name = "msm-dai-q6-dev.240", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .platform_name = "msm-pcm-afe", + .ignore_suspend = 1, + }, + {/* hw:x,8 */ + .name = MSM_DAILINK_NAME(Compress1), + .stream_name = "Compress1", + .cpu_dai_name = "MultiMedia4", + .platform_name = "msm-compress-dsp", + .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS, + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA4, + }, + {/* hw:x,9*/ + .name = "AUXPCM Hostless", + .stream_name = "AUXPCM Hostless", + .cpu_dai_name = "AUXPCM_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,10 */ + .name = "SLIMBUS_1 Hostless", + .stream_name = "SLIMBUS_1 Hostless", + .cpu_dai_name = "SLIMBUS1_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,11 */ + .name = "SLIMBUS_3 Hostless", + .stream_name = "SLIMBUS_3 Hostless", + .cpu_dai_name = "SLIMBUS3_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,12 */ + .name = "SLIMBUS_4 Hostless", + .stream_name = "SLIMBUS_4 Hostless", + .cpu_dai_name = "SLIMBUS4_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,13 */ + .name = MSM_DAILINK_NAME(LowLatency), + .stream_name = "MultiMedia5", + .cpu_dai_name = "MultiMedia5", + .platform_name = "msm-pcm-dsp.1", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA5, + }, + /* LSM FE */ + {/* hw:x,14 */ + .name = "Listen 1 Audio Service", + .stream_name = "Listen 1 Audio Service", + .cpu_dai_name = "LSM1", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .be_id = MSM_FRONTEND_DAI_LSM1, + }, + {/* hw:x,15 */ + .name = MSM_DAILINK_NAME(Compress2), + .stream_name = "Compress2", + .cpu_dai_name = "MultiMedia7", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA7, + }, + {/* hw:x,16 */ + .name = MSM_DAILINK_NAME(Compress3), + .stream_name = "Compress3", + .cpu_dai_name = "MultiMedia10", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA10, + }, + {/* hw:x,17 */ + .name = MSM_DAILINK_NAME(ULL_NOIRQ), + .stream_name = "MM_NOIRQ", + .cpu_dai_name = "MultiMedia8", + .platform_name = "msm-pcm-dsp-noirq", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA8, + }, + {/* hw:x,18 */ + .name = "HDMI_RX_HOSTLESS", + .stream_name = "HDMI_RX_HOSTLESS", + .cpu_dai_name = "HDMI_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,19 */ + .name = "VoiceMMode2", + .stream_name = "VoiceMMode2", + .cpu_dai_name = "VoiceMMode2", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .be_id = MSM_FRONTEND_DAI_VOICEMMODE2, + }, + {/* hw:x,20 */ + .name = "Listen 2 Audio Service", + .stream_name = "Listen 2 Audio Service", + .cpu_dai_name = "LSM2", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .be_id = MSM_FRONTEND_DAI_LSM2, + }, + {/* hw:x,21 */ + .name = "Listen 3 Audio Service", + .stream_name = "Listen 3 Audio Service", + .cpu_dai_name = "LSM3", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .be_id = MSM_FRONTEND_DAI_LSM3, + }, + {/* hw:x,22 */ + .name = "Listen 4 Audio Service", + .stream_name = "Listen 4 Audio Service", + .cpu_dai_name = "LSM4", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .be_id = MSM_FRONTEND_DAI_LSM4, + }, + {/* hw:x,23 */ + .name = "Listen 5 Audio Service", + .stream_name = "Listen 5 Audio Service", + .cpu_dai_name = "LSM5", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .be_id = MSM_FRONTEND_DAI_LSM5, + }, + {/* hw:x,24 */ + .name = "Listen 6 Audio Service", + .stream_name = "Listen 6 Audio Service", + .cpu_dai_name = "LSM6", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .be_id = MSM_FRONTEND_DAI_LSM6 + }, + {/* hw:x,25 */ + .name = "Listen 7 Audio Service", + .stream_name = "Listen 7 Audio Service", + .cpu_dai_name = "LSM7", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .be_id = MSM_FRONTEND_DAI_LSM7, + }, + {/* hw:x,26 */ + .name = "Listen 8 Audio Service", + .stream_name = "Listen 8 Audio Service", + .cpu_dai_name = "LSM8", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .be_id = MSM_FRONTEND_DAI_LSM8, + }, + {/* hw:x,27 */ + .name = MSM_DAILINK_NAME(Media9), + .stream_name = "MultiMedia9", + .cpu_dai_name = "MultiMedia9", + .platform_name = "msm-pcm-dsp.0", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA9, + }, + {/* hw:x,28 */ + .name = MSM_DAILINK_NAME(Compress4), + .stream_name = "Compress4", + .cpu_dai_name = "MultiMedia11", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA11, + }, + {/* hw:x,29 */ + .name = MSM_DAILINK_NAME(Compress5), + .stream_name = "Compress5", + .cpu_dai_name = "MultiMedia12", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA12, + }, + {/* hw:x,30 */ + .name = MSM_DAILINK_NAME(Compress6), + .stream_name = "Compress6", + .cpu_dai_name = "MultiMedia13", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA13, + }, + {/* hw:x,31 */ + .name = MSM_DAILINK_NAME(Compress7), + .stream_name = "Compress7", + .cpu_dai_name = "MultiMedia14", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA14, + }, + {/* hw:x,32 */ + .name = MSM_DAILINK_NAME(Compress8), + .stream_name = "Compress8", + .cpu_dai_name = "MultiMedia15", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA15, + }, + {/* hw:x,33 */ + .name = MSM_DAILINK_NAME(Compress9), + .stream_name = "Compress9", + .cpu_dai_name = "MultiMedia16", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA16, + }, + {/* hw:x,34 */ + .name = "SLIMBUS_8 Hostless", + .stream_name = "SLIMBUS8_HOSTLESS Capture", + .cpu_dai_name = "SLIMBUS8_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, +}; + +static struct snd_soc_dai_link msm_ext_common_be_dai[] = { + { + .name = LPASS_BE_AFE_PCM_RX, + .stream_name = "AFE Playback", + .cpu_dai_name = "msm-dai-q6-dev.224", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_AFE_PCM_RX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_AFE_PCM_TX, + .stream_name = "AFE Capture", + .cpu_dai_name = "msm-dai-q6-dev.225", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_AFE_PCM_TX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ignore_suspend = 1, + }, + /* Incall Record Uplink BACK END DAI Link */ + { + .name = LPASS_BE_INCALL_RECORD_TX, + .stream_name = "Voice Uplink Capture", + .cpu_dai_name = "msm-dai-q6-dev.32772", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_INCALL_RECORD_TX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ignore_suspend = 1, + }, + /* Incall Record Downlink BACK END DAI Link */ + { + .name = LPASS_BE_INCALL_RECORD_RX, + .stream_name = "Voice Downlink Capture", + .cpu_dai_name = "msm-dai-q6-dev.32771", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_INCALL_RECORD_RX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ignore_suspend = 1, + }, + /* Incall Music BACK END DAI Link */ + { + .name = LPASS_BE_VOICE_PLAYBACK_TX, + .stream_name = "Voice Farend Playback", + .cpu_dai_name = "msm-dai-q6-dev.32773", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ignore_suspend = 1, + }, + /* Incall Music 2 BACK END DAI Link */ + { + .name = LPASS_BE_VOICE2_PLAYBACK_TX, + .stream_name = "Voice2 Farend Playback", + .cpu_dai_name = "msm-dai-q6-dev.32770", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_USB_AUDIO_RX, + .stream_name = "USB Audio Playback", + .cpu_dai_name = "msm-dai-q6-dev.28672", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_USB_RX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_USB_AUDIO_TX, + .stream_name = "USB Audio Capture", + .cpu_dai_name = "msm-dai-q6-dev.28673", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_USB_TX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_PRI_TDM_RX_0, + .stream_name = "Primary TDM0 Playback", + .cpu_dai_name = "msm-dai-q6-tdm.36864", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_PRI_TDM_RX_0, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_tdm_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_PRI_TDM_TX_0, + .stream_name = "Primary TDM0 Capture", + .cpu_dai_name = "msm-dai-q6-tdm.36865", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_PRI_TDM_TX_0, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_tdm_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SEC_TDM_RX_0, + .stream_name = "Secondary TDM0 Playback", + .cpu_dai_name = "msm-dai-q6-tdm.36880", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_SEC_TDM_RX_0, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_tdm_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SEC_TDM_TX_0, + .stream_name = "Secondary TDM0 Capture", + .cpu_dai_name = "msm-dai-q6-tdm.36881", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_SEC_TDM_TX_0, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_tdm_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_TERT_TDM_RX_0, + .stream_name = "Tertiary TDM0 Playback", + .cpu_dai_name = "msm-dai-q6-tdm.36896", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_TERT_TDM_RX_0, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_tdm_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_TERT_TDM_TX_0, + .stream_name = "Tertiary TDM0 Capture", + .cpu_dai_name = "msm-dai-q6-tdm.36897", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_TERT_TDM_TX_0, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_tdm_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_QUAT_TDM_RX_0, + .stream_name = "Quaternary TDM0 Playback", + .cpu_dai_name = "msm-dai-q6-tdm.36912", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_QUAT_TDM_RX_0, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_tdm_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_QUAT_TDM_TX_0, + .stream_name = "Quaternary TDM0 Capture", + .cpu_dai_name = "msm-dai-q6-tdm.36913", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_QUAT_TDM_TX_0, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_tdm_be_ops, + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = { + { + .name = LPASS_BE_PRI_MI2S_RX, + .stream_name = "Primary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.0", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_PRI_MI2S_RX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_mi2s_be_ops, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + }, + { + .name = LPASS_BE_PRI_MI2S_TX, + .stream_name = "Primary MI2S Capture", + .cpu_dai_name = "msm-dai-q6-mi2s.0", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_PRI_MI2S_TX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_mi2s_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SEC_MI2S_RX, + .stream_name = "Secondary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.1", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_mi2s_be_ops, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + }, + { + .name = LPASS_BE_SEC_MI2S_TX, + .stream_name = "Secondary MI2S Capture", + .cpu_dai_name = "msm-dai-q6-mi2s.1", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_mi2s_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_TERT_MI2S_RX, + .stream_name = "Tertiary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.2", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_mi2s_be_ops, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + }, + { + .name = LPASS_BE_TERT_MI2S_TX, + .stream_name = "Tertiary MI2S Capture", + .cpu_dai_name = "msm-dai-q6-mi2s.2", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_mi2s_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_QUAT_MI2S_RX, + .stream_name = "Quaternary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.3", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_mi2s_be_ops, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + }, + { + .name = LPASS_BE_QUAT_MI2S_TX, + .stream_name = "Quaternary MI2S Capture", + .cpu_dai_name = "msm-dai-q6-mi2s.3", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_mi2s_be_ops, + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = { + /* Primary AUX PCM Backend DAI Links */ + { + .name = LPASS_BE_AUXPCM_RX, + .stream_name = "AUX PCM Playback", + .cpu_dai_name = "msm-dai-q6-auxpcm.1", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_AUXPCM_RX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + .ops = &msm_aux_pcm_be_ops, + }, + { + .name = LPASS_BE_AUXPCM_TX, + .stream_name = "AUX PCM Capture", + .cpu_dai_name = "msm-dai-q6-auxpcm.1", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_AUXPCM_TX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + .ops = &msm_aux_pcm_be_ops, + }, + /* Secondary AUX PCM Backend DAI Links */ + { + .name = LPASS_BE_SEC_AUXPCM_RX, + .stream_name = "Sec AUX PCM Playback", + .cpu_dai_name = "msm-dai-q6-auxpcm.2", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_SEC_AUXPCM_RX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + .ops = &msm_aux_pcm_be_ops, + }, + { + .name = LPASS_BE_SEC_AUXPCM_TX, + .stream_name = "Sec AUX PCM Capture", + .cpu_dai_name = "msm-dai-q6-auxpcm.2", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_SEC_AUXPCM_TX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .ops = &msm_aux_pcm_be_ops, + }, + /* Tertiary AUX PCM Backend DAI Links */ + { + .name = LPASS_BE_TERT_AUXPCM_RX, + .stream_name = "Tert AUX PCM Playback", + .cpu_dai_name = "msm-dai-q6-auxpcm.3", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_TERT_AUXPCM_RX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + .ops = &msm_aux_pcm_be_ops, + }, + { + .name = LPASS_BE_TERT_AUXPCM_TX, + .stream_name = "Tert AUX PCM Capture", + .cpu_dai_name = "msm-dai-q6-auxpcm.3", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_TERT_AUXPCM_TX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .ops = &msm_aux_pcm_be_ops, + }, + /* Quaternary AUX PCM Backend DAI Links */ + { + .name = LPASS_BE_QUAT_AUXPCM_RX, + .stream_name = "Quat AUX PCM Playback", + .cpu_dai_name = "msm-dai-q6-auxpcm.4", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + .ops = &msm_aux_pcm_be_ops, + }, + { + .name = LPASS_BE_QUAT_AUXPCM_TX, + .stream_name = "Quat AUX PCM Capture", + .cpu_dai_name = "msm-dai-q6-auxpcm.4", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .ops = &msm_aux_pcm_be_ops, + }, +}; + +static struct snd_soc_dai_link msm_wcn_be_dai_links[] = { + { + .name = LPASS_BE_SLIMBUS_7_RX, + .stream_name = "Slimbus7 Playback", + .cpu_dai_name = "msm-dai-q6-dev.16398", + .platform_name = "msm-pcm-routing", + .codec_name = "btfmslim_slave", + /* BT codec driver determines capabilities based on + * dai name, bt codecdai name should always contains + * supported usecase information + */ + .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_7_RX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ops = &msm_wcn_ops, + /* dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_7_TX, + .stream_name = "Slimbus7 Capture", + .cpu_dai_name = "msm-dai-q6-dev.16399", + .platform_name = "msm-pcm-routing", + .codec_name = "btfmslim_slave", + .codec_dai_name = "btfm_bt_sco_slim_tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_7_TX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .ops = &msm_wcn_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_8_TX, + .stream_name = "Slimbus8 Capture", + .cpu_dai_name = "msm-dai-q6-dev.16401", + .platform_name = "msm-pcm-routing", + .codec_name = "btfmslim_slave", + .codec_dai_name = "btfm_fm_slim_tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_8_TX, + .be_hw_params_fixup = msm_ext_be_hw_params_fixup, + .init = &msm_wcn_init, + .ops = &msm_wcn_ops, + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm_ext_tasha_dai_links[ +ARRAY_SIZE(msm_ext_common_fe_dai) + +ARRAY_SIZE(msm_ext_tasha_fe_dai) + +ARRAY_SIZE(msm_ext_common_be_dai) + +ARRAY_SIZE(msm_ext_tasha_be_dai) + +ARRAY_SIZE(msm_mi2s_be_dai_links) + +ARRAY_SIZE(msm_auxpcm_be_dai_links) + +ARRAY_SIZE(msm_wcn_be_dai_links)]; + +static struct snd_soc_dai_link msm_ext_tavil_dai_links[ +ARRAY_SIZE(msm_ext_common_fe_dai) + +ARRAY_SIZE(msm_ext_tavil_fe_dai) + +ARRAY_SIZE(msm_ext_common_be_dai) + +ARRAY_SIZE(msm_ext_tavil_be_dai) + +ARRAY_SIZE(msm_mi2s_be_dai_links) + +ARRAY_SIZE(msm_auxpcm_be_dai_links) + +ARRAY_SIZE(msm_wcn_be_dai_links)]; + +/** + * populate_snd_card_dailinks - prepares dailink array and initializes card. + * + * @dev: device handle + * + * Returns card on success or NULL on failure. + */ +struct snd_soc_card *populate_snd_card_dailinks(struct device *dev, + int snd_card_val) +{ + struct snd_soc_card *card; + struct snd_soc_dai_link *msm_ext_dai_links = NULL; + int ret, len1, len2, len3, len4; + enum codec_variant codec_ver = 0; + + if (snd_card_val == EXT_SND_CARD_TASHA) { + card = &snd_soc_card_msm_card_tasha; + } else if (snd_card_val == EXT_SND_CARD_TAVIL) { + card = &snd_soc_card_msm_card_tavil; + } else { + dev_err(dev, "%s: failing as no matching card name\n", + __func__); + return NULL; + } + + card->dev = dev; + ret = snd_soc_of_parse_card_name(card, "qcom,model"); + if (ret) { + dev_err(dev, "%s: parse card name failed, err:%d\n", + __func__, ret); + return NULL; + } + + if (strnstr(card->name, "tasha", strlen(card->name))) { + codec_ver = tasha_codec_ver(); + if (codec_ver == WCD9326) + card->name = "sdm660-tashalite-snd-card"; + + len1 = ARRAY_SIZE(msm_ext_common_fe_dai); + len2 = len1 + ARRAY_SIZE(msm_ext_tasha_fe_dai); + len3 = len2 + ARRAY_SIZE(msm_ext_common_be_dai); + memcpy(msm_ext_tasha_dai_links, msm_ext_common_fe_dai, + sizeof(msm_ext_common_fe_dai)); + memcpy(msm_ext_tasha_dai_links + len1, + msm_ext_tasha_fe_dai, sizeof(msm_ext_tasha_fe_dai)); + memcpy(msm_ext_tasha_dai_links + len2, + msm_ext_common_be_dai, sizeof(msm_ext_common_be_dai)); + memcpy(msm_ext_tasha_dai_links + len3, + msm_ext_tasha_be_dai, sizeof(msm_ext_tasha_be_dai)); + len4 = len3 + ARRAY_SIZE(msm_ext_tasha_be_dai); + if (of_property_read_bool(dev->of_node, + "qcom,mi2s-audio-intf")) { + memcpy(msm_ext_tasha_dai_links + len4, + msm_mi2s_be_dai_links, + sizeof(msm_mi2s_be_dai_links)); + len4 += ARRAY_SIZE(msm_mi2s_be_dai_links); + } + if (of_property_read_bool(dev->of_node, + "qcom,auxpcm-audio-intf")) { + memcpy(msm_ext_tasha_dai_links + len4, + msm_auxpcm_be_dai_links, + sizeof(msm_auxpcm_be_dai_links)); + len4 += ARRAY_SIZE(msm_auxpcm_be_dai_links); + } + if (of_property_read_bool(dev->of_node, "qcom,wcn-btfm")) { + dev_dbg(dev, "%s(): WCN BTFM support present\n", + __func__); + memcpy(msm_ext_tasha_dai_links + len4, + msm_wcn_be_dai_links, + sizeof(msm_wcn_be_dai_links)); + len4 += ARRAY_SIZE(msm_wcn_be_dai_links); + } + msm_ext_dai_links = msm_ext_tasha_dai_links; + } else if (strnstr(card->name, "tavil", strlen(card->name))) { + len1 = ARRAY_SIZE(msm_ext_common_fe_dai); + len2 = len1 + ARRAY_SIZE(msm_ext_tavil_fe_dai); + len3 = len2 + ARRAY_SIZE(msm_ext_common_be_dai); + memcpy(msm_ext_tavil_dai_links, msm_ext_common_fe_dai, + sizeof(msm_ext_common_fe_dai)); + memcpy(msm_ext_tavil_dai_links + len1, + msm_ext_tavil_fe_dai, sizeof(msm_ext_tavil_fe_dai)); + memcpy(msm_ext_tavil_dai_links + len2, + msm_ext_common_be_dai, sizeof(msm_ext_common_be_dai)); + memcpy(msm_ext_tavil_dai_links + len3, + msm_ext_tavil_be_dai, sizeof(msm_ext_tavil_be_dai)); + len4 = len3 + ARRAY_SIZE(msm_ext_tavil_be_dai); + if (of_property_read_bool(dev->of_node, + "qcom,mi2s-audio-intf")) { + memcpy(msm_ext_tavil_dai_links + len4, + msm_mi2s_be_dai_links, + sizeof(msm_mi2s_be_dai_links)); + len4 += ARRAY_SIZE(msm_mi2s_be_dai_links); + } + if (of_property_read_bool(dev->of_node, + "qcom,auxpcm-audio-intf")) { + memcpy(msm_ext_tavil_dai_links + len4, + msm_auxpcm_be_dai_links, + sizeof(msm_auxpcm_be_dai_links)); + len4 += ARRAY_SIZE(msm_auxpcm_be_dai_links); + } + if (of_property_read_bool(dev->of_node, "qcom,wcn-btfm")) { + dev_dbg(dev, "%s(): WCN BTFM support present\n", + __func__); + memcpy(msm_ext_tavil_dai_links + len4, + msm_wcn_be_dai_links, + sizeof(msm_wcn_be_dai_links)); + len4 += ARRAY_SIZE(msm_wcn_be_dai_links); + } + msm_ext_dai_links = msm_ext_tavil_dai_links; + } else { + dev_err(dev, "%s: failing as no matching card name\n", + __func__); + return NULL; + } + card->dai_link = msm_ext_dai_links; + card->num_links = len4; + + return card; +} +EXPORT_SYMBOL(populate_snd_card_dailinks); diff --git a/sound/soc/msm/sdm660-external.c b/sound/soc/msm/sdm660-external.c new file mode 100644 index 000000000000..f610eb53d5df --- /dev/null +++ b/sound/soc/msm/sdm660-external.c @@ -0,0 +1,1841 @@ +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "qdsp6v2/msm-pcm-routing-v2.h" +#include "msm-audio-pinctrl.h" +#include "sdm660-common.h" +#include "sdm660-external.h" +#include "../codecs/wcd9335.h" +#include "../codecs/wcd934x/wcd934x.h" +#include "../codecs/wcd934x/wcd934x-mbhc.h" + +#define SDM660_SPK_ON 1 +#define SDM660_SPK_OFF 0 + +#define WCD9XXX_MBHC_DEF_BUTTONS 8 +#define WCD9XXX_MBHC_DEF_RLOADS 5 +#define CODEC_EXT_CLK_RATE 9600000 +#define ADSP_STATE_READY_TIMEOUT_MS 3000 + +#define TLMM_CENTER_MPM_WAKEUP_INT_EN_0 0x03596000 +#define LPI_GPIO_22_WAKEUP_VAL 0x00000002 + +#define TLMM_LPI_DIR_CONN_INTR1_CFG_APPS 0x0359D004 +#define LPI_GPIO_22_INTR1_CFG_VAL 0x01 +#define LPI_GPIO_22_INTR1_CFG_MASK 0x03 + +#define TLMM_LPI_GPIO_INTR_CFG1 0x0359B004 +#define LPI_GPIO_INTR_CFG1_VAL 0x00000113 + +#define TLMM_LPI_GPIO22_CFG 0x15078040 +#define LPI_GPIO22_CFG_VAL 0x0000009 + +#define TLMM_LPI_GPIO22_INOUT 0x15078044 +#define LPI_GPIO22_INOUT_VAL 0x00000000 + +#define WSA8810_NAME_1 "wsa881x.20170211" +#define WSA8810_NAME_2 "wsa881x.20170212" + +static int msm_ext_spk_control = 1; +static struct wcd_mbhc_config *wcd_mbhc_cfg_ptr; + +struct msm_asoc_wcd93xx_codec { + void* (*get_afe_config_fn)(struct snd_soc_codec *codec, + enum afe_config_type config_type); + void (*mbhc_hs_detect_exit)(struct snd_soc_codec *codec); +}; + +static struct msm_asoc_wcd93xx_codec msm_codec_fn; +static struct platform_device *spdev; + +struct msm_snd_interrupt { + void __iomem *mpm_wakeup; + void __iomem *intr1_cfg_apps; + void __iomem *lpi_gpio_intr_cfg; + void __iomem *lpi_gpio_cfg; + void __iomem *lpi_gpio_inout; +}; + +static struct msm_snd_interrupt msm_snd_intr_lpi; + +static bool is_initial_boot; + +static void *def_ext_mbhc_cal(void); + +enum { + SLIM_RX_0 = 0, + SLIM_RX_1, + SLIM_RX_2, + SLIM_RX_3, + SLIM_RX_4, + SLIM_RX_5, + SLIM_RX_6, + SLIM_RX_7, + SLIM_RX_MAX, +}; + +enum { + SLIM_TX_0 = 0, + SLIM_TX_1, + SLIM_TX_2, + SLIM_TX_3, + SLIM_TX_4, + SLIM_TX_5, + SLIM_TX_6, + SLIM_TX_7, + SLIM_TX_8, + SLIM_TX_MAX, +}; + +struct dev_config { + u32 sample_rate; + u32 bit_format; + u32 channels; +}; + +/* Default configuration of slimbus channels */ +static struct dev_config slim_rx_cfg[] = { + [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, +}; + +static struct dev_config slim_tx_cfg[] = { + [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, +}; + +static int msm_vi_feed_tx_ch = 2; +static const char *const slim_rx_ch_text[] = {"One", "Two"}; +static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four", + "Five", "Six", "Seven", + "Eight"}; +static const char *const vi_feed_ch_text[] = {"One", "Two"}; +static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE", + "S32_LE"}; +static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16", + "KHZ_32", "KHZ_44P1", "KHZ_48", + "KHZ_88P2", "KHZ_96", "KHZ_176P4", + "KHZ_192", "KHZ_352P8", "KHZ_384"}; +static const char *const spk_function_text[] = {"Off", "On"}; +static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_48"}; + +static SOC_ENUM_SINGLE_EXT_DECL(spk_func_en, spk_function_text); +static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text); +static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text); +static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text); +static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text); +static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text); +static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text); +static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text); +static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text); +static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text); +static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text); +static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text); +static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text); + +static int slim_get_sample_rate_val(int sample_rate) +{ + int sample_rate_val = 0; + + switch (sample_rate) { + case SAMPLING_RATE_8KHZ: + sample_rate_val = 0; + break; + case SAMPLING_RATE_16KHZ: + sample_rate_val = 1; + break; + case SAMPLING_RATE_32KHZ: + sample_rate_val = 2; + break; + case SAMPLING_RATE_44P1KHZ: + sample_rate_val = 3; + break; + case SAMPLING_RATE_48KHZ: + sample_rate_val = 4; + break; + case SAMPLING_RATE_88P2KHZ: + sample_rate_val = 5; + break; + case SAMPLING_RATE_96KHZ: + sample_rate_val = 6; + break; + case SAMPLING_RATE_176P4KHZ: + sample_rate_val = 7; + break; + case SAMPLING_RATE_192KHZ: + sample_rate_val = 8; + break; + case SAMPLING_RATE_352P8KHZ: + sample_rate_val = 9; + break; + case SAMPLING_RATE_384KHZ: + sample_rate_val = 10; + break; + default: + sample_rate_val = 4; + break; + } + return sample_rate_val; +} + +static int slim_get_sample_rate(int value) +{ + int sample_rate = 0; + + switch (value) { + case 0: + sample_rate = SAMPLING_RATE_8KHZ; + break; + case 1: + sample_rate = SAMPLING_RATE_16KHZ; + break; + case 2: + sample_rate = SAMPLING_RATE_32KHZ; + break; + case 3: + sample_rate = SAMPLING_RATE_44P1KHZ; + break; + case 4: + sample_rate = SAMPLING_RATE_48KHZ; + break; + case 5: + sample_rate = SAMPLING_RATE_88P2KHZ; + break; + case 6: + sample_rate = SAMPLING_RATE_96KHZ; + break; + case 7: + sample_rate = SAMPLING_RATE_176P4KHZ; + break; + case 8: + sample_rate = SAMPLING_RATE_192KHZ; + break; + case 9: + sample_rate = SAMPLING_RATE_352P8KHZ; + break; + case 10: + sample_rate = SAMPLING_RATE_384KHZ; + break; + default: + sample_rate = SAMPLING_RATE_48KHZ; + break; + } + return sample_rate; +} + +static int slim_get_bit_format_val(int bit_format) +{ + int val = 0; + + switch (bit_format) { + case SNDRV_PCM_FORMAT_S32_LE: + val = 3; + break; + case SNDRV_PCM_FORMAT_S24_3LE: + val = 2; + break; + case SNDRV_PCM_FORMAT_S24_LE: + val = 1; + break; + case SNDRV_PCM_FORMAT_S16_LE: + default: + val = 0; + break; + } + return val; +} + +static int slim_get_bit_format(int val) +{ + int bit_fmt = SNDRV_PCM_FORMAT_S16_LE; + + switch (val) { + case 0: + bit_fmt = SNDRV_PCM_FORMAT_S16_LE; + break; + case 1: + bit_fmt = SNDRV_PCM_FORMAT_S24_LE; + break; + case 2: + bit_fmt = SNDRV_PCM_FORMAT_S24_3LE; + break; + case 3: + bit_fmt = SNDRV_PCM_FORMAT_S32_LE; + break; + default: + bit_fmt = SNDRV_PCM_FORMAT_S16_LE; + break; + } + return bit_fmt; +} + +static int slim_get_port_idx(struct snd_kcontrol *kcontrol) +{ + int port_id = 0; + + if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) + port_id = SLIM_RX_0; + else if (strnstr(kcontrol->id.name, "SLIM_2_RX", sizeof("SLIM_2_RX"))) + port_id = SLIM_RX_2; + else if (strnstr(kcontrol->id.name, "SLIM_5_RX", sizeof("SLIM_5_RX"))) + port_id = SLIM_RX_5; + else if (strnstr(kcontrol->id.name, "SLIM_6_RX", sizeof("SLIM_6_RX"))) + port_id = SLIM_RX_6; + else if (strnstr(kcontrol->id.name, "SLIM_0_TX", sizeof("SLIM_0_TX"))) + port_id = SLIM_TX_0; + else if (strnstr(kcontrol->id.name, "SLIM_1_TX", sizeof("SLIM_1_TX"))) + port_id = SLIM_TX_1; + else { + pr_err("%s: unsupported channel: %s", + __func__, kcontrol->id.name); + return -EINVAL; + } + + return port_id; +} + +static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + /* + * Slimbus_7_Rx/Tx sample rate values should always be in sync (same) + * when used for BT_SCO use case. Return either Rx or Tx sample rate + * value. + */ + switch (slim_rx_cfg[SLIM_RX_7].sample_rate) { + case SAMPLING_RATE_48KHZ: + ucontrol->value.integer.value[0] = 2; + break; + case SAMPLING_RATE_16KHZ: + ucontrol->value.integer.value[0] = 1; + break; + case SAMPLING_RATE_8KHZ: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + pr_debug("%s: sample rate = %d", __func__, + slim_rx_cfg[SLIM_RX_7].sample_rate); + + return 0; +} + +static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 1: + slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ; + slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ; + break; + case 2: + slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ; + slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ; + break; + case 0: + default: + slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ; + slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ; + break; + } + pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n", + __func__, + slim_rx_cfg[SLIM_RX_7].sample_rate, + slim_tx_cfg[SLIM_TX_7].sample_rate, + ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ch_num = slim_get_port_idx(kcontrol); + + if (ch_num < 0) + return ch_num; + + ucontrol->value.enumerated.item[0] = + slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate); + + pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__, + ch_num, slim_rx_cfg[ch_num].sample_rate, + ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ch_num = slim_get_port_idx(kcontrol); + + if (ch_num < 0) + return ch_num; + + slim_rx_cfg[ch_num].sample_rate = + slim_get_sample_rate(ucontrol->value.enumerated.item[0]); + + pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__, + ch_num, slim_rx_cfg[ch_num].sample_rate, + ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ch_num = slim_get_port_idx(kcontrol); + + if (ch_num < 0) + return ch_num; + + ucontrol->value.enumerated.item[0] = + slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate); + + pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__, + ch_num, slim_tx_cfg[ch_num].sample_rate, + ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int sample_rate = 0; + int ch_num = slim_get_port_idx(kcontrol); + + if (ch_num < 0) + return ch_num; + + sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]); + if (sample_rate == SAMPLING_RATE_44P1KHZ) { + pr_err("%s: Unsupported sample rate %d: for Tx path\n", + __func__, sample_rate); + return -EINVAL; + } + slim_tx_cfg[ch_num].sample_rate = sample_rate; + + pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__, + ch_num, slim_tx_cfg[ch_num].sample_rate, + ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ch_num = slim_get_port_idx(kcontrol); + + if (ch_num < 0) + return ch_num; + + ucontrol->value.enumerated.item[0] = + slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format); + + pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n", + __func__, ch_num, slim_rx_cfg[ch_num].bit_format, + ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ch_num = slim_get_port_idx(kcontrol); + + if (ch_num < 0) + return ch_num; + + slim_rx_cfg[ch_num].bit_format = + slim_get_bit_format(ucontrol->value.enumerated.item[0]); + + pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n", + __func__, ch_num, slim_rx_cfg[ch_num].bit_format, + ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ch_num = slim_get_port_idx(kcontrol); + + if (ch_num < 0) + return ch_num; + + ucontrol->value.enumerated.item[0] = + slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format); + + pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n", + __func__, ch_num, slim_tx_cfg[ch_num].bit_format, + ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ch_num = slim_get_port_idx(kcontrol); + + if (ch_num < 0) + return ch_num; + + slim_tx_cfg[ch_num].bit_format = + slim_get_bit_format(ucontrol->value.enumerated.item[0]); + + pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n", + __func__, ch_num, slim_tx_cfg[ch_num].bit_format, + ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int msm_slim_rx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ch_num = slim_get_port_idx(kcontrol); + + if (ch_num < 0) + return ch_num; + + pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__, + ch_num, slim_rx_cfg[ch_num].channels); + ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1; + + return 0; +} + +static int msm_slim_rx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ch_num = slim_get_port_idx(kcontrol); + + if (ch_num < 0) + return ch_num; + + slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1; + pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__, + ch_num, slim_rx_cfg[ch_num].channels); + + return 1; +} + +static int msm_slim_tx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ch_num = slim_get_port_idx(kcontrol); + + if (ch_num < 0) + return ch_num; + + pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__, + ch_num, slim_tx_cfg[ch_num].channels); + ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1; + + return 0; +} + +static int msm_slim_tx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ch_num = slim_get_port_idx(kcontrol); + + if (ch_num < 0) + return ch_num; + + slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1; + pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__, + ch_num, slim_tx_cfg[ch_num].channels); + + return 1; +} + +static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1; + pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__, + ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1; + + pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch); + return 1; +} + +static void *def_ext_mbhc_cal(void) +{ + void *tavil_wcd_cal; + struct wcd_mbhc_btn_detect_cfg *btn_cfg; + u16 *btn_high; + + tavil_wcd_cal = kzalloc(WCD_MBHC_CAL_SIZE(WCD_MBHC_DEF_BUTTONS, + WCD9XXX_MBHC_DEF_RLOADS), GFP_KERNEL); + if (!tavil_wcd_cal) + return NULL; + +#define S(X, Y) ((WCD_MBHC_CAL_PLUG_TYPE_PTR(tavil_wcd_cal)->X) = (Y)) + S(v_hs_max, 1600); +#undef S +#define S(X, Y) ((WCD_MBHC_CAL_BTN_DET_PTR(tavil_wcd_cal)->X) = (Y)) + S(num_btn, WCD_MBHC_DEF_BUTTONS); +#undef S + + btn_cfg = WCD_MBHC_CAL_BTN_DET_PTR(tavil_wcd_cal); + btn_high = ((void *)&btn_cfg->_v_btn_low) + + (sizeof(btn_cfg->_v_btn_low[0]) * btn_cfg->num_btn); + + btn_high[0] = 75; + btn_high[1] = 150; + btn_high[2] = 237; + btn_high[3] = 500; + btn_high[4] = 500; + btn_high[5] = 500; + btn_high[6] = 500; + btn_high[7] = 500; + + return tavil_wcd_cal; +} + +static inline int param_is_mask(int p) +{ + return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) && + (p <= SNDRV_PCM_HW_PARAM_LAST_MASK); +} + +static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p, int n) +{ + return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]); +} + + +static void msm_ext_control(struct snd_soc_codec *codec) +{ + struct snd_soc_dapm_context *dapm = + snd_soc_codec_get_dapm(codec); + + pr_debug("%s: msm_ext_spk_control = %d", __func__, msm_ext_spk_control); + if (msm_ext_spk_control == SDM660_SPK_ON) { + snd_soc_dapm_enable_pin(dapm, "Lineout_1 amp"); + snd_soc_dapm_enable_pin(dapm, "Lineout_3 amp"); + } else { + snd_soc_dapm_disable_pin(dapm, "Lineout_1 amp"); + snd_soc_dapm_disable_pin(dapm, "Lineout_3 amp"); + } + snd_soc_dapm_sync(dapm); +} + +static int msm_ext_get_spk(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_ext_spk_control = %d\n", + __func__, msm_ext_spk_control); + ucontrol->value.integer.value[0] = msm_ext_spk_control; + return 0; +} + +static int msm_ext_set_spk(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + + pr_debug("%s()\n", __func__); + if (msm_ext_spk_control == ucontrol->value.integer.value[0]) + return 0; + + msm_ext_spk_control = ucontrol->value.integer.value[0]; + msm_ext_control(codec); + return 1; +} + + +int msm_ext_enable_codec_mclk(struct snd_soc_codec *codec, int enable, + bool dapm) +{ + int ret; + + pr_debug("%s: enable = %d\n", __func__, enable); + + if (!strcmp(dev_name(codec->dev), "tasha_codec")) + ret = tasha_cdc_mclk_enable(codec, enable, dapm); + else if (!strcmp(dev_name(codec->dev), "tavil_codec")) + ret = tavil_cdc_mclk_enable(codec, enable); + else { + dev_err(codec->dev, "%s: unknown codec to enable ext clk\n", + __func__); + ret = -EINVAL; + } + return ret; +} + +static const struct snd_kcontrol_new msm_snd_controls[] = { + SOC_ENUM_EXT("Speaker Function", spk_func_en, msm_ext_get_spk, + msm_ext_set_spk), + SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs, + msm_slim_rx_ch_get, msm_slim_rx_ch_put), + SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs, + msm_slim_rx_ch_get, msm_slim_rx_ch_put), + SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs, + msm_slim_tx_ch_get, msm_slim_tx_ch_put), + SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs, + msm_slim_tx_ch_get, msm_slim_tx_ch_put), + SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs, + msm_slim_rx_ch_get, msm_slim_rx_ch_put), + SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs, + msm_slim_rx_ch_get, msm_slim_rx_ch_put), + SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs, + msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put), + SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format, + slim_rx_bit_format_get, slim_rx_bit_format_put), + SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format, + slim_rx_bit_format_get, slim_rx_bit_format_put), + SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format, + slim_rx_bit_format_get, slim_rx_bit_format_put), + SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format, + slim_tx_bit_format_get, slim_tx_bit_format_put), + SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate, + slim_rx_sample_rate_get, slim_rx_sample_rate_put), + SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate, + slim_rx_sample_rate_get, slim_rx_sample_rate_put), + SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate, + slim_tx_sample_rate_get, slim_tx_sample_rate_put), + SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate, + slim_rx_sample_rate_get, slim_rx_sample_rate_put), + SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate, + slim_rx_sample_rate_get, slim_rx_sample_rate_put), + SOC_ENUM_EXT("BT SampleRate", bt_sample_rate, + msm_bt_sample_rate_get, + msm_bt_sample_rate_put), +}; + +static int msm_slim_get_ch_from_beid(int32_t be_id) +{ + int ch_id = 0; + + switch (be_id) { + case MSM_BACKEND_DAI_SLIMBUS_0_RX: + ch_id = SLIM_RX_0; + break; + case MSM_BACKEND_DAI_SLIMBUS_1_RX: + ch_id = SLIM_RX_1; + break; + case MSM_BACKEND_DAI_SLIMBUS_2_RX: + ch_id = SLIM_RX_2; + break; + case MSM_BACKEND_DAI_SLIMBUS_3_RX: + ch_id = SLIM_RX_3; + break; + case MSM_BACKEND_DAI_SLIMBUS_4_RX: + ch_id = SLIM_RX_4; + break; + case MSM_BACKEND_DAI_SLIMBUS_6_RX: + ch_id = SLIM_RX_6; + break; + case MSM_BACKEND_DAI_SLIMBUS_0_TX: + ch_id = SLIM_TX_0; + break; + case MSM_BACKEND_DAI_SLIMBUS_3_TX: + ch_id = SLIM_TX_3; + break; + default: + ch_id = SLIM_RX_0; + break; + } + + return ch_id; +} + +static void param_set_mask(struct snd_pcm_hw_params *p, int n, unsigned bit) +{ + if (bit >= SNDRV_MASK_MAX) + return; + if (param_is_mask(n)) { + struct snd_mask *m = param_to_mask(p, n); + + m->bits[0] = 0; + m->bits[1] = 0; + m->bits[bit >> 5] |= (1 << (bit & 31)); + } +} + +/** + * msm_ext_be_hw_params_fixup - updates settings of ALSA BE hw params. + * + * @rtd: runtime dailink instance + * @params: HW params of associated backend dailink. + * + * Returns 0 on success or rc on failure. + */ +int msm_ext_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_dai_link *dai_link = rtd->dai_link; + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + int rc = 0; + int idx; + void *config = NULL; + struct snd_soc_codec *codec = rtd->codec; + + pr_debug("%s: format = %d, rate = %d\n", + __func__, params_format(params), params_rate(params)); + + switch (dai_link->be_id) { + case MSM_BACKEND_DAI_SLIMBUS_0_RX: + case MSM_BACKEND_DAI_SLIMBUS_1_RX: + case MSM_BACKEND_DAI_SLIMBUS_2_RX: + case MSM_BACKEND_DAI_SLIMBUS_3_RX: + case MSM_BACKEND_DAI_SLIMBUS_4_RX: + case MSM_BACKEND_DAI_SLIMBUS_6_RX: + idx = msm_slim_get_ch_from_beid(dai_link->be_id); + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + slim_rx_cfg[idx].bit_format); + rate->min = rate->max = slim_rx_cfg[idx].sample_rate; + channels->min = channels->max = slim_rx_cfg[idx].channels; + break; + + case MSM_BACKEND_DAI_SLIMBUS_0_TX: + case MSM_BACKEND_DAI_SLIMBUS_3_TX: + idx = msm_slim_get_ch_from_beid(dai_link->be_id); + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + slim_tx_cfg[idx].bit_format); + rate->min = rate->max = slim_tx_cfg[idx].sample_rate; + channels->min = channels->max = slim_tx_cfg[idx].channels; + break; + + case MSM_BACKEND_DAI_SLIMBUS_1_TX: + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + slim_tx_cfg[1].bit_format); + rate->min = rate->max = slim_tx_cfg[1].sample_rate; + channels->min = channels->max = slim_tx_cfg[1].channels; + break; + + case MSM_BACKEND_DAI_SLIMBUS_4_TX: + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + SNDRV_PCM_FORMAT_S32_LE); + rate->min = rate->max = SAMPLING_RATE_8KHZ; + channels->min = channels->max = msm_vi_feed_tx_ch; + break; + + case MSM_BACKEND_DAI_SLIMBUS_5_RX: + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + slim_rx_cfg[5].bit_format); + rate->min = rate->max = slim_rx_cfg[5].sample_rate; + channels->min = channels->max = slim_rx_cfg[5].channels; + break; + + case MSM_BACKEND_DAI_SLIMBUS_5_TX: + rate->min = rate->max = SAMPLING_RATE_16KHZ; + channels->min = channels->max = 1; + + config = msm_codec_fn.get_afe_config_fn(codec, + AFE_SLIMBUS_SLAVE_PORT_CONFIG); + if (config) { + rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG, + config, SLIMBUS_5_TX); + if (rc) + pr_err("%s: Failed to set slimbus slave port config %d\n", + __func__, rc); + } + break; + + case MSM_BACKEND_DAI_SLIMBUS_7_RX: + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + slim_rx_cfg[SLIM_RX_7].bit_format); + rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate; + channels->min = channels->max = + slim_rx_cfg[SLIM_RX_7].channels; + break; + + case MSM_BACKEND_DAI_SLIMBUS_7_TX: + rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate; + channels->min = channels->max = + slim_tx_cfg[SLIM_TX_7].channels; + break; + + case MSM_BACKEND_DAI_SLIMBUS_8_TX: + rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate; + channels->min = channels->max = + slim_tx_cfg[SLIM_TX_8].channels; + break; + + default: + rate->min = rate->max = SAMPLING_RATE_48KHZ; + break; + } + return rc; +} +EXPORT_SYMBOL(msm_ext_be_hw_params_fixup); + +/** + * msm_snd_hw_params - hw params ops of backend dailink. + * + * @substream: PCM stream of associated backend dailink. + * @params: HW params of associated backend dailink. + * + * Returns 0 on success or ret on failure. + */ +int msm_snd_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *codec_dai = rtd->codec_dai; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct snd_soc_dai_link *dai_link = rtd->dai_link; + + int ret = 0; + u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS]; + u32 rx_ch_cnt = 0, tx_ch_cnt = 0; + u32 user_set_tx_ch = 0; + u32 rx_ch_count; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + ret = snd_soc_dai_get_channel_map(codec_dai, + &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch); + if (ret < 0) { + pr_err("%s: failed to get codec chan map, err:%d\n", + __func__, ret); + goto err_ch_map; + } + if (dai_link->be_id == MSM_BACKEND_DAI_SLIMBUS_5_RX) { + pr_debug("%s: rx_5_ch=%d\n", __func__, + slim_rx_cfg[5].channels); + rx_ch_count = slim_rx_cfg[5].channels; + } else if (dai_link->be_id == MSM_BACKEND_DAI_SLIMBUS_2_RX) { + pr_debug("%s: rx_2_ch=%d\n", __func__, + slim_rx_cfg[2].channels); + rx_ch_count = slim_rx_cfg[2].channels; + } else if (dai_link->be_id == MSM_BACKEND_DAI_SLIMBUS_6_RX) { + pr_debug("%s: rx_6_ch=%d\n", __func__, + slim_rx_cfg[6].channels); + rx_ch_count = slim_rx_cfg[6].channels; + } else { + pr_debug("%s: rx_0_ch=%d\n", __func__, + slim_rx_cfg[0].channels); + rx_ch_count = slim_rx_cfg[0].channels; + } + ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0, + rx_ch_count, rx_ch); + if (ret < 0) { + pr_err("%s: failed to set cpu chan map, err:%d\n", + __func__, ret); + goto err_ch_map; + } + } else { + pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__, + codec_dai->name, codec_dai->id, user_set_tx_ch); + ret = snd_soc_dai_get_channel_map(codec_dai, + &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch); + if (ret < 0) { + pr_err("%s: failed to get codec chan map\n, err:%d\n", + __func__, ret); + goto err_ch_map; + } + /* For _tx1 case */ + if (dai_link->be_id == MSM_BACKEND_DAI_SLIMBUS_0_TX) + user_set_tx_ch = slim_tx_cfg[0].channels; + /* For _tx3 case */ + else if (dai_link->be_id == MSM_BACKEND_DAI_SLIMBUS_1_TX) + user_set_tx_ch = slim_tx_cfg[1].channels; + else if (dai_link->be_id == MSM_BACKEND_DAI_SLIMBUS_4_TX) + user_set_tx_ch = msm_vi_feed_tx_ch; + else + user_set_tx_ch = tx_ch_cnt; + + pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), be_id (%d)\n", + __func__, slim_tx_cfg[0].channels, user_set_tx_ch, + tx_ch_cnt, dai_link->be_id); + + ret = snd_soc_dai_set_channel_map(cpu_dai, + user_set_tx_ch, tx_ch, 0, 0); + if (ret < 0) + pr_err("%s: failed to set cpu chan map, err:%d\n", + __func__, ret); + } + +err_ch_map: + return ret; +} +EXPORT_SYMBOL(msm_snd_hw_params); + +/** + * msm_ext_slimbus_2_hw_params - hw params ops of slimbus_2 BE. + * + * @substream: PCM stream of associated backend dailink. + * @params: HW params of associated backend dailink. + * + * Returns 0 on success or ret on failure. + */ +int msm_ext_slimbus_2_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *codec_dai = rtd->codec_dai; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + int ret = 0; + unsigned int rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS]; + unsigned int rx_ch_cnt = 0, tx_ch_cnt = 0; + unsigned int num_tx_ch = 0; + unsigned int num_rx_ch = 0; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + num_rx_ch = params_channels(params); + pr_debug("%s: %s rx_dai_id = %d num_ch = %d\n", __func__, + codec_dai->name, codec_dai->id, num_rx_ch); + ret = snd_soc_dai_get_channel_map(codec_dai, + &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch); + if (ret < 0) { + pr_err("%s: failed to get codec chan map, err:%d\n", + __func__, ret); + goto end; + } + ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0, + num_rx_ch, rx_ch); + if (ret < 0) { + pr_err("%s: failed to set cpu chan map, err:%d\n", + __func__, ret); + goto end; + } + } else { + num_tx_ch = params_channels(params); + pr_debug("%s: %s tx_dai_id = %d num_ch = %d\n", __func__, + codec_dai->name, codec_dai->id, num_tx_ch); + ret = snd_soc_dai_get_channel_map(codec_dai, + &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch); + if (ret < 0) { + pr_err("%s: failed to get codec chan map, err:%d\n", + __func__, ret); + goto end; + } + ret = snd_soc_dai_set_channel_map(cpu_dai, + num_tx_ch, tx_ch, 0, 0); + if (ret < 0) { + pr_err("%s: failed to set cpu chan map, err:%d\n", + __func__, ret); + goto end; + } + } +end: + return ret; +} +EXPORT_SYMBOL(msm_ext_slimbus_2_hw_params); + +/** + * msm_snd_cpe_hw_params - hw params ops of CPE backend. + * + * @substream: PCM stream of associated backend dailink. + * @params: HW params of associated backend dailink. + * + * Returns 0 on success or ret on failure. + */ +int msm_snd_cpe_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *codec_dai = rtd->codec_dai; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct snd_soc_dai_link *dai_link = rtd->dai_link; + int ret = 0; + u32 tx_ch[SLIM_MAX_TX_PORTS]; + u32 tx_ch_cnt = 0; + + if (substream->stream != SNDRV_PCM_STREAM_CAPTURE) { + pr_err("%s: Invalid stream type %d\n", + __func__, substream->stream); + ret = -EINVAL; + goto end; + } + + pr_debug("%s: %s_tx_dai_id_%d\n", __func__, + codec_dai->name, codec_dai->id); + ret = snd_soc_dai_get_channel_map(codec_dai, + &tx_ch_cnt, tx_ch, NULL, NULL); + if (ret < 0) { + pr_err("%s: failed to get codec chan map\n, err:%d\n", + __func__, ret); + goto end; + } + + pr_debug("%s: tx_ch_cnt(%d) be_id %d\n", + __func__, tx_ch_cnt, dai_link->be_id); + + ret = snd_soc_dai_set_channel_map(cpu_dai, + tx_ch_cnt, tx_ch, 0, 0); + if (ret < 0) { + pr_err("%s: failed to set cpu chan map, err:%d\n", + __func__, ret); + goto end; + } +end: + return ret; +} +EXPORT_SYMBOL(msm_snd_cpe_hw_params); + +static int msm_afe_set_config(struct snd_soc_codec *codec) +{ + int rc; + void *config_data; + + pr_debug("%s: enter\n", __func__); + + if (!msm_codec_fn.get_afe_config_fn) { + dev_err(codec->dev, "%s: codec get afe config not init'ed\n", + __func__); + return -EINVAL; + } + config_data = msm_codec_fn.get_afe_config_fn(codec, + AFE_CDC_REGISTERS_CONFIG); + if (config_data) { + rc = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0); + if (rc) { + pr_err("%s: Failed to set codec registers config %d\n", + __func__, rc); + return rc; + } + } + + config_data = msm_codec_fn.get_afe_config_fn(codec, + AFE_CDC_REGISTER_PAGE_CONFIG); + if (config_data) { + rc = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data, + 0); + if (rc) + pr_err("%s: Failed to set cdc register page config\n", + __func__); + } + + config_data = msm_codec_fn.get_afe_config_fn(codec, + AFE_SLIMBUS_SLAVE_CONFIG); + if (config_data) { + rc = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0); + if (rc) { + pr_err("%s: Failed to set slimbus slave config %d\n", + __func__, rc); + return rc; + } + } + + config_data = msm_codec_fn.get_afe_config_fn(codec, + AFE_AANC_VERSION); + if (config_data) { + rc = afe_set_config(AFE_AANC_VERSION, config_data, 0); + if (rc) { + pr_err("%s: Failed to set AANC version %d\n", + __func__, rc); + return rc; + } + } + + config_data = msm_codec_fn.get_afe_config_fn(codec, + AFE_CDC_CLIP_REGISTERS_CONFIG); + if (config_data) { + rc = afe_set_config(AFE_CDC_CLIP_REGISTERS_CONFIG, + config_data, 0); + if (rc) { + pr_err("%s: Failed to set clip registers %d\n", + __func__, rc); + return rc; + } + } + + config_data = msm_codec_fn.get_afe_config_fn(codec, + AFE_CLIP_BANK_SEL); + if (config_data) { + rc = afe_set_config(AFE_CLIP_BANK_SEL, + config_data, 0); + if (rc) { + pr_err("%s: Failed to set AFE bank selection %d\n", + __func__, rc); + return rc; + } + } + + config_data = msm_codec_fn.get_afe_config_fn(codec, + AFE_CDC_REGISTER_PAGE_CONFIG); + if (config_data) { + rc = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data, + 0); + if (rc) + pr_err("%s: Failed to set cdc register page config\n", + __func__); + } + + return 0; +} + +static void msm_afe_clear_config(void) +{ + afe_clear_config(AFE_CDC_REGISTERS_CONFIG); + afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG); +} + +static void msm_snd_interrupt_config(void) +{ + int val; + + val = ioread32(msm_snd_intr_lpi.mpm_wakeup); + val |= LPI_GPIO_22_WAKEUP_VAL; + iowrite32(val, msm_snd_intr_lpi.mpm_wakeup); + + val = ioread32(msm_snd_intr_lpi.intr1_cfg_apps); + val &= ~(LPI_GPIO_22_INTR1_CFG_MASK); + val |= LPI_GPIO_22_INTR1_CFG_VAL; + iowrite32(val, msm_snd_intr_lpi.intr1_cfg_apps); + + iowrite32(LPI_GPIO_INTR_CFG1_VAL, + msm_snd_intr_lpi.lpi_gpio_intr_cfg); + iowrite32(LPI_GPIO22_CFG_VAL, + msm_snd_intr_lpi.lpi_gpio_cfg); + iowrite32(LPI_GPIO22_INOUT_VAL, + msm_snd_intr_lpi.lpi_gpio_inout); +} + +static int msm_adsp_power_up_config(struct snd_soc_codec *codec) +{ + int ret = 0; + unsigned long timeout; + int adsp_ready = 0; + + timeout = jiffies + + msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS); + + do { + if (q6core_is_adsp_ready()) { + pr_debug("%s: ADSP Audio is ready\n", __func__); + adsp_ready = 1; + break; + } + /* + * ADSP will be coming up after subsystem restart and + * it might not be fully up when the control reaches + * here. So, wait for 50msec before checking ADSP state + */ + msleep(50); + } while (time_after(timeout, jiffies)); + + if (!adsp_ready) { + pr_err("%s: timed out waiting for ADSP Audio\n", __func__); + ret = -ETIMEDOUT; + goto err_fail; + } + msm_snd_interrupt_config(); + + ret = msm_afe_set_config(codec); + if (ret) + pr_err("%s: Failed to set AFE config. err %d\n", + __func__, ret); + + return 0; + +err_fail: + return ret; +} + +static int sdm660_notifier_service_cb(struct notifier_block *this, + unsigned long opcode, void *ptr) +{ + int ret; + struct snd_soc_card *card = NULL; + const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX; + struct snd_soc_pcm_runtime *rtd; + struct snd_soc_codec *codec; + + pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode); + + switch (opcode) { + case AUDIO_NOTIFIER_SERVICE_DOWN: + /* + * Use flag to ignore initial boot notifications + * On initial boot msm_adsp_power_up_config is + * called on init. There is no need to clear + * and set the config again on initial boot. + */ + if (is_initial_boot) + break; + msm_afe_clear_config(); + break; + case AUDIO_NOTIFIER_SERVICE_UP: + if (is_initial_boot) { + is_initial_boot = false; + break; + } + if (!spdev) + return -EINVAL; + + card = platform_get_drvdata(spdev); + rtd = snd_soc_get_pcm_runtime(card, be_dl_name); + if (!rtd) { + dev_err(card->dev, + "%s: snd_soc_get_pcm_runtime for %s failed!\n", + __func__, be_dl_name); + ret = -EINVAL; + goto done; + } + codec = rtd->codec; + + ret = msm_adsp_power_up_config(codec); + if (ret < 0) { + dev_err(card->dev, + "%s: msm_adsp_power_up_config failed ret = %d!\n", + __func__, ret); + goto done; + } + break; + default: + break; + } +done: + return NOTIFY_OK; +} + +static struct notifier_block service_nb = { + .notifier_call = sdm660_notifier_service_cb, + .priority = -INT_MAX, +}; + +static int msm_config_hph_en0_gpio(struct snd_soc_codec *codec, bool high) +{ + struct snd_soc_card *card = codec->component.card; + struct msm_asoc_mach_data *pdata; + int val; + + if (!card) + return 0; + + pdata = snd_soc_card_get_drvdata(card); + if (!pdata || !gpio_is_valid(pdata->hph_en0_gpio)) + return 0; + + val = gpio_get_value_cansleep(pdata->hph_en0_gpio); + if ((!!val) == high) + return 0; + + gpio_direction_output(pdata->hph_en0_gpio, (int)high); + + return 1; +} + +static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_codec *codec, + int enable, bool dapm) +{ + int ret = 0; + + if (!strcmp(dev_name(codec->dev), "tasha_codec")) + ret = tasha_cdc_mclk_tx_enable(codec, enable, dapm); + else { + dev_err(codec->dev, "%s: unknown codec to enable ext clk\n", + __func__); + ret = -EINVAL; + } + return ret; +} + +static int msm_ext_mclk_tx_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + + pr_debug("%s: event = %d\n", __func__, event); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + return msm_snd_enable_codec_ext_tx_clk(codec, 1, true); + case SND_SOC_DAPM_POST_PMD: + return msm_snd_enable_codec_ext_tx_clk(codec, 0, true); + } + return 0; +} + +static int msm_ext_mclk_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + + pr_debug("%s: event = %d\n", __func__, event); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + return msm_ext_enable_codec_mclk(codec, 1, true); + case SND_SOC_DAPM_POST_PMD: + return msm_ext_enable_codec_mclk(codec, 0, true); + } + return 0; +} + +static int msm_ext_prepare_hifi(struct msm_asoc_mach_data *pdata) +{ + int ret = 0; + + if (gpio_is_valid(pdata->hph_en1_gpio)) { + pr_debug("%s: hph_en1_gpio request %d\n", __func__, + pdata->hph_en1_gpio); + ret = gpio_request(pdata->hph_en1_gpio, "hph_en1_gpio"); + if (ret) { + pr_err("%s: hph_en1_gpio request failed, ret:%d\n", + __func__, ret); + goto err; + } + } + if (gpio_is_valid(pdata->hph_en0_gpio)) { + pr_debug("%s: hph_en0_gpio request %d\n", __func__, + pdata->hph_en0_gpio); + ret = gpio_request(pdata->hph_en0_gpio, "hph_en0_gpio"); + if (ret) + pr_err("%s: hph_en0_gpio request failed, ret:%d\n", + __func__, ret); + } + +err: + return ret; +} + +static const struct snd_soc_dapm_widget msm_dapm_widgets[] = { + + SND_SOC_DAPM_SUPPLY_S("MCLK", -1, SND_SOC_NOPM, 0, 0, + msm_ext_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_SUPPLY_S("MCLK TX", -1, SND_SOC_NOPM, 0, 0, + msm_ext_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_SPK("Lineout_1 amp", NULL), + SND_SOC_DAPM_SPK("Lineout_3 amp", NULL), + SND_SOC_DAPM_SPK("Lineout_2 amp", NULL), + SND_SOC_DAPM_SPK("Lineout_4 amp", NULL), + SND_SOC_DAPM_MIC("Handset Mic", NULL), + SND_SOC_DAPM_MIC("Headset Mic", NULL), + SND_SOC_DAPM_MIC("Secondary Mic", NULL), + SND_SOC_DAPM_MIC("ANCRight Headset Mic", NULL), + SND_SOC_DAPM_MIC("ANCLeft Headset Mic", NULL), + SND_SOC_DAPM_MIC("Analog Mic4", NULL), + SND_SOC_DAPM_MIC("Analog Mic6", NULL), + SND_SOC_DAPM_MIC("Analog Mic7", NULL), + SND_SOC_DAPM_MIC("Analog Mic8", NULL), + + SND_SOC_DAPM_MIC("Digital Mic0", NULL), + SND_SOC_DAPM_MIC("Digital Mic1", NULL), + SND_SOC_DAPM_MIC("Digital Mic2", NULL), + SND_SOC_DAPM_MIC("Digital Mic3", NULL), + SND_SOC_DAPM_MIC("Digital Mic4", NULL), + SND_SOC_DAPM_MIC("Digital Mic5", NULL), + SND_SOC_DAPM_MIC("Digital Mic6", NULL), +}; + +static struct snd_soc_dapm_route wcd_audio_paths_tasha[] = { + {"MIC BIAS1", NULL, "MCLK TX"}, + {"MIC BIAS2", NULL, "MCLK TX"}, + {"MIC BIAS3", NULL, "MCLK TX"}, + {"MIC BIAS4", NULL, "MCLK TX"}, +}; + +static struct snd_soc_dapm_route wcd_audio_paths[] = { + {"MIC BIAS1", NULL, "MCLK"}, + {"MIC BIAS2", NULL, "MCLK"}, + {"MIC BIAS3", NULL, "MCLK"}, + {"MIC BIAS4", NULL, "MCLK"}, +}; + +/** + * msm_audrx_init - Audio init function of sound card instantiate. + * + * @rtd: runtime dailink instance + * + * Returns 0 on success or ret on failure. + */ +int msm_audrx_init(struct snd_soc_pcm_runtime *rtd) +{ + int ret; + void *config_data; + struct snd_soc_codec *codec = rtd->codec; + struct snd_soc_dapm_context *dapm = + snd_soc_codec_get_dapm(codec); + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct snd_soc_dai *codec_dai = rtd->codec_dai; + struct snd_soc_pcm_runtime *rtd_aux = rtd->card->rtd_aux; + struct snd_card *card; + struct snd_info_entry *entry; + struct msm_asoc_mach_data *pdata = + snd_soc_card_get_drvdata(rtd->card); + + /* Codec SLIMBUS configuration + * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8, RX9, RX10, RX11, RX12, RX13 + * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13 + * TX14, TX15, TX16 + */ + unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150, + 151, 152, 153, 154, 155, 156}; + unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133, + 134, 135, 136, 137, 138, 139, + 140, 141, 142, 143}; + + pr_debug("%s: dev_name%s\n", __func__, dev_name(cpu_dai->dev)); + + rtd->pmdown_time = 0; + + ret = snd_soc_add_codec_controls(codec, msm_snd_controls, + ARRAY_SIZE(msm_snd_controls)); + if (ret < 0) { + pr_err("%s: add_codec_controls failed: %d\n", + __func__, ret); + return ret; + } + + snd_soc_dapm_new_controls(dapm, msm_dapm_widgets, + ARRAY_SIZE(msm_dapm_widgets)); + + if (!strcmp(dev_name(codec_dai->dev), "tasha_codec")) + snd_soc_dapm_add_routes(dapm, wcd_audio_paths_tasha, + ARRAY_SIZE(wcd_audio_paths_tasha)); + else + snd_soc_dapm_add_routes(dapm, wcd_audio_paths, + ARRAY_SIZE(wcd_audio_paths)); + + snd_soc_dapm_enable_pin(dapm, "Lineout_1 amp"); + snd_soc_dapm_enable_pin(dapm, "Lineout_3 amp"); + snd_soc_dapm_enable_pin(dapm, "Lineout_2 amp"); + snd_soc_dapm_enable_pin(dapm, "Lineout_4 amp"); + + snd_soc_dapm_ignore_suspend(dapm, "MADINPUT"); + snd_soc_dapm_ignore_suspend(dapm, "MAD_CPE_INPUT"); + snd_soc_dapm_ignore_suspend(dapm, "Handset Mic"); + snd_soc_dapm_ignore_suspend(dapm, "Headset Mic"); + snd_soc_dapm_ignore_suspend(dapm, "Secondary Mic"); + snd_soc_dapm_ignore_suspend(dapm, "Lineout_1 amp"); + snd_soc_dapm_ignore_suspend(dapm, "Lineout_3 amp"); + snd_soc_dapm_ignore_suspend(dapm, "Lineout_2 amp"); + snd_soc_dapm_ignore_suspend(dapm, "Lineout_4 amp"); + snd_soc_dapm_ignore_suspend(dapm, "ANCRight Headset Mic"); + snd_soc_dapm_ignore_suspend(dapm, "ANCLeft Headset Mic"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5"); + snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4"); + snd_soc_dapm_ignore_suspend(dapm, "Analog Mic6"); + snd_soc_dapm_ignore_suspend(dapm, "Analog Mic7"); + snd_soc_dapm_ignore_suspend(dapm, "Analog Mic8"); + + snd_soc_dapm_ignore_suspend(dapm, "EAR"); + snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1"); + snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2"); + snd_soc_dapm_ignore_suspend(dapm, "LINEOUT3"); + snd_soc_dapm_ignore_suspend(dapm, "LINEOUT4"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC1"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC2"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC3"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC4"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC5"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC6"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC0"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC1"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC2"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC3"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC4"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC5"); + snd_soc_dapm_ignore_suspend(dapm, "ANC EAR"); + snd_soc_dapm_ignore_suspend(dapm, "ANC HEADPHONE"); + snd_soc_dapm_ignore_suspend(dapm, "SPK1 OUT"); + snd_soc_dapm_ignore_suspend(dapm, "SPK2 OUT"); + snd_soc_dapm_ignore_suspend(dapm, "HPHL"); + snd_soc_dapm_ignore_suspend(dapm, "HPHR"); + snd_soc_dapm_ignore_suspend(dapm, "ANC HPHL"); + snd_soc_dapm_ignore_suspend(dapm, "ANC HPHR"); + snd_soc_dapm_ignore_suspend(dapm, "ANC LINEOUT1"); + snd_soc_dapm_ignore_suspend(dapm, "ANC LINEOUT2"); + snd_soc_dapm_ignore_suspend(dapm, "AIF4 VI"); + snd_soc_dapm_ignore_suspend(dapm, "VIINPUT"); + + snd_soc_dapm_sync(dapm); + snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch), + tx_ch, ARRAY_SIZE(rx_ch), rx_ch); + + if (!strcmp(dev_name(codec_dai->dev), "tavil_codec")) { + msm_codec_fn.get_afe_config_fn = tavil_get_afe_config; + } else { + msm_codec_fn.get_afe_config_fn = tasha_get_afe_config; + msm_codec_fn.mbhc_hs_detect_exit = tasha_mbhc_hs_detect_exit; + } + + ret = msm_adsp_power_up_config(codec); + if (ret) { + pr_err("%s: Failed to set AFE config %d\n", __func__, ret); + goto err_afe_cfg; + } + + config_data = msm_codec_fn.get_afe_config_fn(codec, + AFE_AANC_VERSION); + if (config_data) { + ret = afe_set_config(AFE_AANC_VERSION, config_data, 0); + if (ret) { + pr_err("%s: Failed to set aanc version %d\n", + __func__, ret); + goto err_afe_cfg; + } + } + + if (!strcmp(dev_name(codec_dai->dev), "tasha_codec")) { + config_data = msm_codec_fn.get_afe_config_fn(codec, + AFE_CDC_CLIP_REGISTERS_CONFIG); + if (config_data) { + ret = afe_set_config(AFE_CDC_CLIP_REGISTERS_CONFIG, + config_data, 0); + if (ret) { + pr_err("%s: Failed to set clip registers %d\n", + __func__, ret); + goto err_afe_cfg; + } + } + config_data = msm_codec_fn.get_afe_config_fn(codec, + AFE_CLIP_BANK_SEL); + if (config_data) { + ret = afe_set_config(AFE_CLIP_BANK_SEL, config_data, 0); + if (ret) { + pr_err("%s: Failed to set AFE bank selection %d\n", + __func__, ret); + goto err_afe_cfg; + } + } + } + + /* + * Send speaker configuration only for WSA8810. + * Defalut configuration is for WSA8815. + */ + if (!strcmp(dev_name(codec_dai->dev), "tavil_codec")) { + if (rtd_aux && rtd_aux->component) + if (!strcmp(rtd_aux->component->name, WSA8810_NAME_1) || + !strcmp(rtd_aux->component->name, WSA8810_NAME_2)) { + tavil_set_spkr_mode(rtd->codec, SPKR_MODE_1); + tavil_set_spkr_gain_offset(rtd->codec, + RX_GAIN_OFFSET_M1P5_DB); + } + card = rtd->card->snd_card; + entry = snd_register_module_info(card->module, "codecs", + card->proc_root); + if (!entry) { + pr_debug("%s: Cannot create codecs module entry\n", + __func__); + pdata->codec_root = NULL; + goto done; + } + pdata->codec_root = entry; + tavil_codec_info_create_codec_entry(pdata->codec_root, codec); + } else { + if (rtd_aux && rtd_aux->component) + if (!strcmp(rtd_aux->component->name, WSA8810_NAME_1) || + !strcmp(rtd_aux->component->name, WSA8810_NAME_2)) { + tasha_set_spkr_mode(rtd->codec, SPKR_MODE_1); + tasha_set_spkr_gain_offset(rtd->codec, + RX_GAIN_OFFSET_M1P5_DB); + } + card = rtd->card->snd_card; + entry = snd_register_module_info(card->module, "codecs", + card->proc_root); + if (!entry) { + pr_debug("%s: Cannot create codecs module entry\n", + __func__); + ret = 0; + goto err_snd_module; + } + pdata->codec_root = entry; + tasha_codec_info_create_codec_entry(pdata->codec_root, codec); + tasha_mbhc_zdet_gpio_ctrl(msm_config_hph_en0_gpio, rtd->codec); + } + + wcd_mbhc_cfg_ptr->calibration = def_ext_mbhc_cal(); + if (!strcmp(dev_name(codec_dai->dev), "tavil_codec")) { + if (wcd_mbhc_cfg_ptr->calibration) { + pdata->codec = codec; + ret = tavil_mbhc_hs_detect(codec, wcd_mbhc_cfg_ptr); + if (ret < 0) + pr_err("%s: Failed to intialise mbhc %d\n", + __func__, ret); + } else { + pr_err("%s: wcd_mbhc_cfg calibration is NULL\n", + __func__); + ret = -ENOMEM; + goto err_mbhc_cal; + } + } else { + if (wcd_mbhc_cfg_ptr->calibration) { + pdata->codec = codec; + ret = tasha_mbhc_hs_detect(codec, wcd_mbhc_cfg_ptr); + if (ret < 0) + pr_err("%s: Failed to intialise mbhc %d\n", + __func__, ret); + } else { + pr_err("%s: wcd_mbhc_cfg calibration is NULL\n", + __func__); + ret = -ENOMEM; + goto err_mbhc_cal; + } + + } +done: + return 0; + +err_snd_module: +err_afe_cfg: +err_mbhc_cal: + return ret; +} +EXPORT_SYMBOL(msm_audrx_init); + +/** + * msm_ext_register_audio_notifier - register SSR notifier. + */ +void msm_ext_register_audio_notifier(void) +{ + int ret; + + ret = audio_notifier_register("sdm660", AUDIO_NOTIFIER_ADSP_DOMAIN, + &service_nb); + if (ret < 0) + pr_err("%s: Audio notifier register failed ret = %d\n", + __func__, ret); +} +EXPORT_SYMBOL(msm_ext_register_audio_notifier); + +/** + * msm_ext_cdc_init - external codec machine specific init. + * + * @pdev: platform device handle + * @pdata: private data of machine driver + * @card: sound card pointer reference + * @mbhc_cfg: MBHC config reference + * + * Returns 0 on success or ret on failure. + */ +int msm_ext_cdc_init(struct platform_device *pdev, + struct msm_asoc_mach_data *pdata, + struct snd_soc_card **card, + struct wcd_mbhc_config *wcd_mbhc_cfg_ptr1) +{ + int ret = 0; + + wcd_mbhc_cfg_ptr = wcd_mbhc_cfg_ptr1; + pdev->id = 0; + wcd_mbhc_cfg_ptr->moisture_en = true; + wcd_mbhc_cfg_ptr->mbhc_micbias = MIC_BIAS_2; + wcd_mbhc_cfg_ptr->anc_micbias = MIC_BIAS_2; + wcd_mbhc_cfg_ptr->enable_anc_mic_detect = false; + + *card = populate_snd_card_dailinks(&pdev->dev, pdata->snd_card_val); + if (!(*card)) { + dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__); + ret = -EPROBE_DEFER; + goto err; + } + spdev = pdev; + platform_set_drvdata(pdev, *card); + snd_soc_card_set_drvdata(*card, pdata); + is_initial_boot = true; + pdata->hph_en1_gpio = of_get_named_gpio(pdev->dev.of_node, + "qcom,hph-en1-gpio", 0); + if (!gpio_is_valid(pdata->hph_en1_gpio)) + pdata->hph_en1_gpio_p = of_parse_phandle(pdev->dev.of_node, + "qcom,hph-en1-gpio", 0); + if (!gpio_is_valid(pdata->hph_en1_gpio) && (!pdata->hph_en1_gpio_p)) { + dev_dbg(&pdev->dev, "property %s not detected in node %s", + "qcom,hph-en1-gpio", pdev->dev.of_node->full_name); + } + + pdata->hph_en0_gpio = of_get_named_gpio(pdev->dev.of_node, + "qcom,hph-en0-gpio", 0); + if (!gpio_is_valid(pdata->hph_en0_gpio)) + pdata->hph_en0_gpio_p = of_parse_phandle(pdev->dev.of_node, + "qcom,hph-en0-gpio", 0); + if (!gpio_is_valid(pdata->hph_en0_gpio) && (!pdata->hph_en0_gpio_p)) { + dev_dbg(&pdev->dev, "property %s not detected in node %s", + "qcom,hph-en0-gpio", pdev->dev.of_node->full_name); + } + + ret = msm_ext_prepare_hifi(pdata); + if (ret) { + dev_dbg(&pdev->dev, "msm_ext_prepare_hifi failed (%d)\n", + ret); + ret = 0; + } + msm_snd_intr_lpi.mpm_wakeup = + ioremap(TLMM_CENTER_MPM_WAKEUP_INT_EN_0, 4); + msm_snd_intr_lpi.intr1_cfg_apps = + ioremap(TLMM_LPI_DIR_CONN_INTR1_CFG_APPS, 4); + msm_snd_intr_lpi.lpi_gpio_intr_cfg = + ioremap(TLMM_LPI_GPIO_INTR_CFG1, 4); + msm_snd_intr_lpi.lpi_gpio_cfg = + ioremap(TLMM_LPI_GPIO22_CFG, 4); + msm_snd_intr_lpi.lpi_gpio_inout = + ioremap(TLMM_LPI_GPIO22_INOUT, 4); +err: + return ret; +} +EXPORT_SYMBOL(msm_ext_cdc_init); + +/** + * msm_ext_cdc_deinit - external codec machine specific deinit. + */ +void msm_ext_cdc_deinit(void) +{ + if (msm_snd_intr_lpi.mpm_wakeup) + iounmap(msm_snd_intr_lpi.mpm_wakeup); + if (msm_snd_intr_lpi.intr1_cfg_apps) + iounmap(msm_snd_intr_lpi.intr1_cfg_apps); + if (msm_snd_intr_lpi.lpi_gpio_intr_cfg) + iounmap(msm_snd_intr_lpi.lpi_gpio_intr_cfg); + if (msm_snd_intr_lpi.lpi_gpio_cfg) + iounmap(msm_snd_intr_lpi.lpi_gpio_cfg); + if (msm_snd_intr_lpi.lpi_gpio_inout) + iounmap(msm_snd_intr_lpi.lpi_gpio_inout); +} +EXPORT_SYMBOL(msm_ext_cdc_deinit); diff --git a/sound/soc/msm/sdm660-external.h b/sound/soc/msm/sdm660-external.h new file mode 100644 index 000000000000..0ede06f0c082 --- /dev/null +++ b/sound/soc/msm/sdm660-external.h @@ -0,0 +1,54 @@ +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SDM660_EXTERNAL +#define __SDM660_EXTERNAL + +int msm_snd_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); +int msm_ext_slimbus_2_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); +int msm_btsco_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_proxy_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_proxy_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_audrx_init(struct snd_soc_pcm_runtime *rtd); +int msm_snd_cpe_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); +struct snd_soc_card *populate_snd_card_dailinks(struct device *dev, + int snd_card_val); +int msm_ext_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +#ifdef CONFIG_SND_SOC_EXT_CODEC +int msm_ext_cdc_init(struct platform_device *, struct msm_asoc_mach_data *, + struct snd_soc_card **, struct wcd_mbhc_config *); +void msm_ext_register_audio_notifier(void); +void msm_ext_cdc_deinit(void); +#else +inline int msm_ext_cdc_init(struct platform_device *pdev, + struct msm_asoc_mach_data *pdata, + struct snd_soc_card **card, + struct wcd_mbhc_config *wcd_mbhc_cfg_ptr1) +{ + return 0; +} + +inline void msm_ext_register_audio_notifier(void) +{ +} +inline void msm_ext_cdc_deinit(void) +{ +} +#endif +#endif diff --git a/sound/soc/msm/sdm660-internal.c b/sound/soc/msm/sdm660-internal.c new file mode 100644 index 000000000000..aa094fe853ee --- /dev/null +++ b/sound/soc/msm/sdm660-internal.c @@ -0,0 +1,3089 @@ +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include "qdsp6v2/msm-pcm-routing-v2.h" +#include "sdm660-common.h" +#include "../codecs/sdm660_cdc/msm-digital-cdc.h" +#include "../codecs/sdm660_cdc/msm-analog-cdc.h" +#include "../codecs/msm_sdw/msm_sdw.h" + +#define __CHIPSET__ "SDM660 " +#define MSM_DAILINK_NAME(name) (__CHIPSET__#name) + +#define DEFAULT_MCLK_RATE 9600000 +#define NATIVE_MCLK_RATE 11289600 + +#define WCD_MBHC_DEF_RLOADS 5 + +#define WCN_CDC_SLIM_RX_CH_MAX 2 +#define WCN_CDC_SLIM_TX_CH_MAX 3 + +#define WSA8810_NAME_1 "wsa881x.20170211" +#define WSA8810_NAME_2 "wsa881x.20170212" + +enum { + INT0_MI2S = 0, + INT1_MI2S, + INT2_MI2S, + INT3_MI2S, + INT4_MI2S, + INT5_MI2S, + INT6_MI2S, + INT_MI2S_MAX, +}; + +enum { + BT_SLIM7, + FM_SLIM8, + SLIM_MAX, +}; + +/*TDM default offset currently only supporting TDM_RX_0 and TDM_TX_0 */ +static unsigned int tdm_slot_offset[TDM_PORT_MAX][TDM_SLOT_OFFSET_MAX] = { + {0, 4, 8, 12, 16, 20, 24, 28},/* TX_0 | RX_0 */ + {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_1 | RX_1 */ + {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_2 | RX_2 */ + {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_3 | RX_3 */ + {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_4 | RX_4 */ + {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_5 | RX_5 */ + {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_6 | RX_6 */ + {AFE_SLOT_MAPPING_OFFSET_INVALID},/* TX_7 | RX_7 */ +}; + +static struct afe_clk_set int_mi2s_clk[INT_MI2S_MAX] = { + { + AFE_API_VERSION_I2S_CONFIG, + Q6AFE_LPASS_CLK_ID_INT0_MI2S_IBIT, + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, + Q6AFE_LPASS_CLK_ROOT_DEFAULT, + 0, + }, + { + AFE_API_VERSION_I2S_CONFIG, + Q6AFE_LPASS_CLK_ID_INT1_MI2S_IBIT, + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, + Q6AFE_LPASS_CLK_ROOT_DEFAULT, + 0, + }, + { + AFE_API_VERSION_I2S_CONFIG, + Q6AFE_LPASS_CLK_ID_INT2_MI2S_IBIT, + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, + Q6AFE_LPASS_CLK_ROOT_DEFAULT, + 0, + }, + { + AFE_API_VERSION_I2S_CONFIG, + Q6AFE_LPASS_CLK_ID_INT3_MI2S_IBIT, + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, + Q6AFE_LPASS_CLK_ROOT_DEFAULT, + 0, + }, + { + AFE_API_VERSION_I2S_CONFIG, + Q6AFE_LPASS_CLK_ID_INT4_MI2S_IBIT, + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, + Q6AFE_LPASS_CLK_ROOT_DEFAULT, + 0, + }, + { + AFE_API_VERSION_I2S_CONFIG, + Q6AFE_LPASS_CLK_ID_INT5_MI2S_IBIT, + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, + Q6AFE_LPASS_CLK_ROOT_DEFAULT, + 0, + }, + { + AFE_API_VERSION_I2S_CONFIG, + Q6AFE_LPASS_CLK_ID_INT6_MI2S_IBIT, + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, + Q6AFE_LPASS_CLK_ROOT_DEFAULT, + 0, + }, +}; + +struct dev_config { + u32 sample_rate; + u32 bit_format; + u32 channels; +}; + +/* Default configuration of MI2S channels */ +static struct dev_config int_mi2s_cfg[] = { + [INT0_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, + [INT1_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [INT2_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [INT3_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [INT4_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [INT5_MI2S] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, + [INT6_MI2S] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, +}; + +static struct dev_config bt_fm_cfg[] = { + [BT_SLIM7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, + [FM_SLIM8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, +}; + +static char const *int_mi2s_rate_text[] = {"KHZ_8", "KHZ_16", + "KHZ_32", "KHZ_44P1", "KHZ_48", + "KHZ_96", "KHZ_192"}; +static const char *const int_mi2s_ch_text[] = {"One", "Two"}; +static const char *const int_mi2s_tx_ch_text[] = {"One", "Two", + "Three", "Four"}; +static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE"}; +static const char *const loopback_mclk_text[] = {"DISABLE", "ENABLE"}; +static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_48"}; + +static SOC_ENUM_SINGLE_EXT_DECL(int0_mi2s_rx_sample_rate, int_mi2s_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(int0_mi2s_rx_chs, int_mi2s_ch_text); +static SOC_ENUM_SINGLE_EXT_DECL(int0_mi2s_rx_format, bit_format_text); +static SOC_ENUM_SINGLE_EXT_DECL(int2_mi2s_tx_sample_rate, int_mi2s_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(int2_mi2s_tx_chs, int_mi2s_tx_ch_text); +static SOC_ENUM_SINGLE_EXT_DECL(int2_mi2s_tx_format, bit_format_text); +static SOC_ENUM_SINGLE_EXT_DECL(int3_mi2s_tx_sample_rate, int_mi2s_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(int3_mi2s_tx_chs, int_mi2s_tx_ch_text); +static SOC_ENUM_SINGLE_EXT_DECL(int3_mi2s_tx_format, bit_format_text); +static SOC_ENUM_SINGLE_EXT_DECL(int4_mi2s_rx_sample_rate, int_mi2s_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(int4_mi2s_rx_chs, int_mi2s_ch_text); +static SOC_ENUM_SINGLE_EXT_DECL(int4_mi2s_rx_format, bit_format_text); +static SOC_ENUM_SINGLE_EXT_DECL(int5_mi2s_tx_chs, int_mi2s_ch_text); +static SOC_ENUM_SINGLE_EXT_DECL(loopback_mclk_en, loopback_mclk_text); +static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text); + +static int msm_dmic_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); +static int msm_int_enable_dig_cdc_clk(struct snd_soc_codec *codec, int enable, + bool dapm); +static int msm_int_mclk0_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); +static int msm_int_mi2s_snd_startup(struct snd_pcm_substream *substream); +static void msm_int_mi2s_snd_shutdown(struct snd_pcm_substream *substream); + +static struct wcd_mbhc_config *mbhc_cfg_ptr; +static struct snd_info_entry *msm_sdw_codec_root; +static struct snd_info_entry *msm_dig_codec_root; +static struct snd_info_entry *pmic_analog_codec_root; + +static int int_mi2s_get_bit_format_val(int bit_format) +{ + int val = 0; + + switch (bit_format) { + case SNDRV_PCM_FORMAT_S24_3LE: + val = 2; + break; + case SNDRV_PCM_FORMAT_S24_LE: + val = 1; + break; + case SNDRV_PCM_FORMAT_S16_LE: + default: + val = 0; + break; + } + return val; +} + +static int int_mi2s_get_bit_format(int val) +{ + int bit_fmt = SNDRV_PCM_FORMAT_S16_LE; + + switch (val) { + case 0: + bit_fmt = SNDRV_PCM_FORMAT_S16_LE; + break; + case 1: + bit_fmt = SNDRV_PCM_FORMAT_S24_LE; + break; + case 2: + bit_fmt = SNDRV_PCM_FORMAT_S24_3LE; + break; + default: + bit_fmt = SNDRV_PCM_FORMAT_S16_LE; + break; + } + return bit_fmt; +} + +static int int_mi2s_get_port_idx(struct snd_kcontrol *kcontrol) +{ + int port_id = 0; + + if (strnstr(kcontrol->id.name, "INT0_MI2S", sizeof("INT0_MI2S"))) + port_id = INT0_MI2S; + else if (strnstr(kcontrol->id.name, "INT2_MI2S", sizeof("INT2_MI2S"))) + port_id = INT2_MI2S; + else if (strnstr(kcontrol->id.name, "INT3_MI2S", sizeof("INT3_MI2S"))) + port_id = INT3_MI2S; + else if (strnstr(kcontrol->id.name, "INT4_MI2S", sizeof("INT4_MI2S"))) + port_id = INT4_MI2S; + else { + pr_err("%s: unsupported channel: %s", + __func__, kcontrol->id.name); + return -EINVAL; + } + + return port_id; +} + +static int int_mi2s_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ch_num = int_mi2s_get_port_idx(kcontrol); + + if (ch_num < 0) + return ch_num; + + ucontrol->value.enumerated.item[0] = + int_mi2s_get_bit_format_val(int_mi2s_cfg[ch_num].bit_format); + + pr_debug("%s: int_mi2s[%d]_bit_format = %d, ucontrol value = %d\n", + __func__, ch_num, int_mi2s_cfg[ch_num].bit_format, + ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int int_mi2s_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ch_num = int_mi2s_get_port_idx(kcontrol); + + if (ch_num < 0) + return ch_num; + + int_mi2s_cfg[ch_num].bit_format = + int_mi2s_get_bit_format(ucontrol->value.enumerated.item[0]); + + pr_debug("%s: int_mi2s[%d]_rx_bit_format = %d, ucontrol value = %d\n", + __func__, ch_num, int_mi2s_cfg[ch_num].bit_format, + ucontrol->value.enumerated.item[0]); + + return 0; +} + +static inline int param_is_mask(int p) +{ + return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) && + (p <= SNDRV_PCM_HW_PARAM_LAST_MASK); +} + +static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p, + int n) +{ + return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]); +} + +static void param_set_mask(struct snd_pcm_hw_params *p, int n, unsigned bit) +{ + if (bit >= SNDRV_MASK_MAX) + return; + if (param_is_mask(n)) { + struct snd_mask *m = param_to_mask(p, n); + + m->bits[0] = 0; + m->bits[1] = 0; + m->bits[bit >> 5] |= (1 << (bit & 31)); + } +} + +static int int_mi2s_get_sample_rate_val(int sample_rate) +{ + int sample_rate_val; + + switch (sample_rate) { + case SAMPLING_RATE_8KHZ: + sample_rate_val = 0; + break; + case SAMPLING_RATE_16KHZ: + sample_rate_val = 1; + break; + case SAMPLING_RATE_32KHZ: + sample_rate_val = 2; + break; + case SAMPLING_RATE_44P1KHZ: + sample_rate_val = 3; + break; + case SAMPLING_RATE_48KHZ: + sample_rate_val = 4; + break; + case SAMPLING_RATE_96KHZ: + sample_rate_val = 5; + break; + case SAMPLING_RATE_192KHZ: + sample_rate_val = 6; + break; + default: + sample_rate_val = 4; + break; + } + return sample_rate_val; +} + +static int int_mi2s_get_sample_rate(int value) +{ + int sample_rate; + + switch (value) { + case 0: + sample_rate = SAMPLING_RATE_8KHZ; + break; + case 1: + sample_rate = SAMPLING_RATE_16KHZ; + break; + case 2: + sample_rate = SAMPLING_RATE_32KHZ; + break; + case 3: + sample_rate = SAMPLING_RATE_44P1KHZ; + break; + case 4: + sample_rate = SAMPLING_RATE_48KHZ; + break; + case 5: + sample_rate = SAMPLING_RATE_96KHZ; + break; + case 6: + sample_rate = SAMPLING_RATE_192KHZ; + break; + default: + sample_rate = SAMPLING_RATE_48KHZ; + break; + } + return sample_rate; +} + +static int int_mi2s_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int idx = int_mi2s_get_port_idx(kcontrol); + + if (idx < 0) + return idx; + + int_mi2s_cfg[idx].sample_rate = + int_mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]); + + pr_debug("%s: idx[%d]_sample_rate = %d, item = %d\n", __func__, + idx, int_mi2s_cfg[idx].sample_rate, + ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int int_mi2s_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int idx = int_mi2s_get_port_idx(kcontrol); + + if (idx < 0) + return idx; + + ucontrol->value.enumerated.item[0] = + int_mi2s_get_sample_rate_val(int_mi2s_cfg[idx].sample_rate); + + pr_debug("%s: idx[%d]_sample_rate = %d, item = %d\n", __func__, + idx, int_mi2s_cfg[idx].sample_rate, + ucontrol->value.enumerated.item[0]); + + return 0; +} + +static int int_mi2s_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int idx = int_mi2s_get_port_idx(kcontrol); + + if (idx < 0) + return idx; + + pr_debug("%s: int_mi2s_[%d]_rx_ch = %d\n", __func__, + idx, int_mi2s_cfg[idx].channels); + ucontrol->value.enumerated.item[0] = int_mi2s_cfg[idx].channels - 1; + + return 0; +} + +static int int_mi2s_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int idx = int_mi2s_get_port_idx(kcontrol); + + if (idx < 0) + return idx; + + int_mi2s_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1; + pr_debug("%s: int_mi2s_[%d]_ch = %d\n", __func__, + idx, int_mi2s_cfg[idx].channels); + + return 1; +} + +static const struct snd_soc_dapm_widget msm_int_dapm_widgets[] = { + SND_SOC_DAPM_SUPPLY_S("INT_MCLK0", -1, SND_SOC_NOPM, 0, 0, + msm_int_mclk0_event, SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_MIC("Handset Mic", NULL), + SND_SOC_DAPM_MIC("Headset Mic", NULL), + SND_SOC_DAPM_MIC("Secondary Mic", NULL), + SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event), + SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event), + SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event), + SND_SOC_DAPM_MIC("Digital Mic4", msm_dmic_event), +}; + +static int msm_config_hph_compander_gpio(bool enable, + struct snd_soc_codec *codec) +{ + struct snd_soc_card *card = codec->component.card; + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + int ret = 0; + + pr_debug("%s: %s HPH Compander\n", __func__, + enable ? "Enable" : "Disable"); + + if (enable) { + ret = msm_cdc_pinctrl_select_active_state(pdata->comp_gpio_p); + if (ret) { + pr_err("%s: gpio set cannot be activated %s\n", + __func__, "comp_gpio"); + goto done; + } + } else { + ret = msm_cdc_pinctrl_select_sleep_state(pdata->comp_gpio_p); + if (ret) { + pr_err("%s: gpio set cannot be de-activated %s\n", + __func__, "comp_gpio"); + goto done; + } + } + +done: + return ret; +} + +static int is_ext_spk_gpio_support(struct platform_device *pdev, + struct msm_asoc_mach_data *pdata) +{ + const char *spk_ext_pa = "qcom,msm-spk-ext-pa"; + + pr_debug("%s:Enter\n", __func__); + + pdata->spk_ext_pa_gpio = of_get_named_gpio(pdev->dev.of_node, + spk_ext_pa, 0); + + if (pdata->spk_ext_pa_gpio < 0) { + dev_dbg(&pdev->dev, + "%s: missing %s in dt node\n", __func__, spk_ext_pa); + } else { + if (!gpio_is_valid(pdata->spk_ext_pa_gpio)) { + pr_err("%s: Invalid external speaker gpio: %d", + __func__, pdata->spk_ext_pa_gpio); + return -EINVAL; + } + } + return 0; +} + +static int enable_spk_ext_pa(struct snd_soc_codec *codec, int enable) +{ + struct snd_soc_card *card = codec->component.card; + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + int ret; + + if (!gpio_is_valid(pdata->spk_ext_pa_gpio)) { + pr_err("%s: Invalid gpio: %d\n", __func__, + pdata->spk_ext_pa_gpio); + return false; + } + + pr_debug("%s: %s external speaker PA\n", __func__, + enable ? "Enable" : "Disable"); + + if (enable) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->ext_spk_gpio_p); + if (ret) { + pr_err("%s: gpio set cannot be de-activated %s\n", + __func__, "ext_spk_gpio"); + return ret; + } + gpio_set_value_cansleep(pdata->spk_ext_pa_gpio, enable); + } else { + gpio_set_value_cansleep(pdata->spk_ext_pa_gpio, enable); + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->ext_spk_gpio_p); + if (ret) { + pr_err("%s: gpio set cannot be de-activated %s\n", + __func__, "ext_spk_gpio"); + return ret; + } + } + return 0; +} + +static int msm_config_sdw_gpio(bool enable, struct snd_soc_codec *codec) +{ + struct snd_soc_card *card = codec->component.card; + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + int ret = 0; + + pr_debug("%s: %s SDW Clk/Data Gpios\n", __func__, + enable ? "Enable" : "Disable"); + + if (enable) { + ret = msm_cdc_pinctrl_select_active_state(pdata->sdw_gpio_p); + if (ret) { + pr_err("%s: gpio set cannot be activated %s\n", + __func__, "sdw_pin"); + goto done; + } + } else { + ret = msm_cdc_pinctrl_select_sleep_state(pdata->sdw_gpio_p); + if (ret) { + pr_err("%s: gpio set cannot be de-activated %s\n", + __func__, "sdw_pin"); + goto done; + } + } + +done: + return ret; +} + +static int int_mi2s_get_idx_from_beid(int32_t be_id) +{ + int idx = 0; + + switch (be_id) { + case MSM_BACKEND_DAI_INT0_MI2S_RX: + idx = INT0_MI2S; + break; + case MSM_BACKEND_DAI_INT2_MI2S_TX: + idx = INT2_MI2S; + break; + case MSM_BACKEND_DAI_INT3_MI2S_TX: + idx = INT3_MI2S; + break; + case MSM_BACKEND_DAI_INT4_MI2S_RX: + idx = INT4_MI2S; + break; + case MSM_BACKEND_DAI_INT5_MI2S_TX: + idx = INT5_MI2S; + break; + default: + idx = INT0_MI2S; + break; + } + + return idx; +} + +static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("%s()\n", __func__); + rate->min = rate->max = 48000; + channels->min = channels->max = 2; + + return 0; +} + +static int int_mi2s_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_dai_link *dai_link = rtd->dai_link; + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + int idx; + + pr_debug("%s: format = %d, rate = %d\n", + __func__, params_format(params), params_rate(params)); + + switch (dai_link->be_id) { + case MSM_BACKEND_DAI_INT0_MI2S_RX: + case MSM_BACKEND_DAI_INT2_MI2S_TX: + case MSM_BACKEND_DAI_INT3_MI2S_TX: + case MSM_BACKEND_DAI_INT4_MI2S_RX: + case MSM_BACKEND_DAI_INT5_MI2S_TX: + idx = int_mi2s_get_idx_from_beid(dai_link->be_id); + rate->min = rate->max = int_mi2s_cfg[idx].sample_rate; + channels->min = channels->max = + int_mi2s_cfg[idx].channels; + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + int_mi2s_cfg[idx].bit_format); + break; + default: + rate->min = rate->max = SAMPLING_RATE_48KHZ; + break; + } + return 0; +} + +static int msm_btfm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_dai_link *dai_link = rtd->dai_link; + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + switch (dai_link->be_id) { + case MSM_BACKEND_DAI_SLIMBUS_7_RX: + case MSM_BACKEND_DAI_SLIMBUS_7_TX: + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + bt_fm_cfg[BT_SLIM7].bit_format); + rate->min = rate->max = bt_fm_cfg[BT_SLIM7].sample_rate; + channels->min = channels->max = + bt_fm_cfg[BT_SLIM7].channels; + break; + + case MSM_BACKEND_DAI_SLIMBUS_8_TX: + rate->min = rate->max = bt_fm_cfg[FM_SLIM8].sample_rate; + channels->min = channels->max = + bt_fm_cfg[FM_SLIM8].channels; + break; + + default: + rate->min = rate->max = SAMPLING_RATE_48KHZ; + break; + } + return 0; +} + +static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = + (int_mi2s_cfg[INT5_MI2S].channels/2 - 1); + pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__, + ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int_mi2s_cfg[INT5_MI2S].channels = + roundup_pow_of_two(ucontrol->value.integer.value[0] + 2); + + pr_debug("%s: msm_vi_feed_tx_ch = %d\n", + __func__, int_mi2s_cfg[INT5_MI2S].channels); + return 1; +} + +static int msm_int_enable_dig_cdc_clk(struct snd_soc_codec *codec, + int enable, bool dapm) +{ + int ret = 0; + struct msm_asoc_mach_data *pdata = NULL; + int clk_freq_in_hz; + bool int_mclk0_freq_chg = false; + + pdata = snd_soc_card_get_drvdata(codec->component.card); + pr_debug("%s: enable %d mclk ref counter %d\n", + __func__, enable, + atomic_read(&pdata->int_mclk0_rsc_ref)); + if (enable) { + if (int_mi2s_cfg[INT0_MI2S].sample_rate == + SAMPLING_RATE_44P1KHZ) { + clk_freq_in_hz = NATIVE_MCLK_RATE; + pdata->native_clk_set = true; + } else { + clk_freq_in_hz = pdata->mclk_freq; + pdata->native_clk_set = false; + } + + if (pdata->digital_cdc_core_clk.clk_freq_in_hz + != clk_freq_in_hz) + int_mclk0_freq_chg = true; + if (!atomic_read(&pdata->int_mclk0_rsc_ref) || + int_mclk0_freq_chg) { + cancel_delayed_work_sync( + &pdata->disable_int_mclk0_work); + mutex_lock(&pdata->cdc_int_mclk0_mutex); + if (atomic_read(&pdata->int_mclk0_enabled) == false || + int_mclk0_freq_chg) { + pdata->digital_cdc_core_clk.clk_freq_in_hz = + clk_freq_in_hz; + pdata->digital_cdc_core_clk.enable = 1; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_INT0_MI2S_RX, + &pdata->digital_cdc_core_clk); + if (ret < 0) { + pr_err("%s: failed to enable CCLK\n", + __func__); + mutex_unlock( + &pdata->cdc_int_mclk0_mutex); + return ret; + } + pr_debug("enabled digital codec core clk\n"); + atomic_set(&pdata->int_mclk0_enabled, true); + } + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + } + atomic_inc(&pdata->int_mclk0_rsc_ref); + } else { + cancel_delayed_work_sync(&pdata->disable_int_mclk0_work); + mutex_lock(&pdata->cdc_int_mclk0_mutex); + if (atomic_read(&pdata->int_mclk0_enabled) == true) { + pdata->digital_cdc_core_clk.enable = 0; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_INT0_MI2S_RX, + &pdata->digital_cdc_core_clk); + if (ret < 0) + pr_err("%s: failed to disable CCLK\n", + __func__); + atomic_set(&pdata->int_mclk0_enabled, false); + } + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + } + return ret; +} + +static int loopback_mclk_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s\n", __func__); + return 0; +} + +static int loopback_mclk_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret = -EINVAL; + struct msm_asoc_mach_data *pdata = NULL; + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + + pdata = snd_soc_card_get_drvdata(codec->component.card); + pr_debug("%s: mclk_rsc_ref %d enable %ld\n", + __func__, atomic_read(&pdata->int_mclk0_rsc_ref), + ucontrol->value.integer.value[0]); + switch (ucontrol->value.integer.value[0]) { + case 1: + ret = msm_cdc_pinctrl_select_active_state(pdata->pdm_gpio_p); + if (ret) { + pr_err("%s: failed to enable the pri gpios: %d\n", + __func__, ret); + break; + } + mutex_lock(&pdata->cdc_int_mclk0_mutex); + if ((!atomic_read(&pdata->int_mclk0_rsc_ref)) && + (!atomic_read(&pdata->int_mclk0_enabled))) { + pdata->digital_cdc_core_clk.enable = 1; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_INT0_MI2S_RX, + &pdata->digital_cdc_core_clk); + if (ret < 0) { + pr_err("%s: failed to enable the MCLK: %d\n", + __func__, ret); + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->pdm_gpio_p); + if (ret) + pr_err("%s: failed to disable the pri gpios: %d\n", + __func__, ret); + break; + } + atomic_set(&pdata->int_mclk0_enabled, true); + } + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + atomic_inc(&pdata->int_mclk0_rsc_ref); + msm_anlg_cdc_mclk_enable(codec, 1, true); + break; + case 0: + if (atomic_read(&pdata->int_mclk0_rsc_ref) <= 0) + break; + msm_anlg_cdc_mclk_enable(codec, 0, true); + mutex_lock(&pdata->cdc_int_mclk0_mutex); + if ((!atomic_dec_return(&pdata->int_mclk0_rsc_ref)) && + (atomic_read(&pdata->int_mclk0_enabled))) { + pdata->digital_cdc_core_clk.enable = 0; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_INT0_MI2S_RX, + &pdata->digital_cdc_core_clk); + if (ret < 0) { + pr_err("%s: failed to disable the CCLK: %d\n", + __func__, ret); + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + break; + } + atomic_set(&pdata->int_mclk0_enabled, false); + } + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + ret = msm_cdc_pinctrl_select_sleep_state(pdata->pdm_gpio_p); + if (ret) + pr_err("%s: failed to disable the pri gpios: %d\n", + __func__, ret); + break; + default: + pr_err("%s: Unexpected input value\n", __func__); + break; + } + return ret; +} + +static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + /* + * Slimbus_7_Rx/Tx sample rate values should always be in sync (same) + * when used for BT_SCO use case. Return either Rx or Tx sample rate + * value. + */ + switch (bt_fm_cfg[BT_SLIM7].sample_rate) { + case SAMPLING_RATE_48KHZ: + ucontrol->value.integer.value[0] = 2; + break; + case SAMPLING_RATE_16KHZ: + ucontrol->value.integer.value[0] = 1; + break; + case SAMPLING_RATE_8KHZ: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + pr_debug("%s: sample rate = %d", __func__, + bt_fm_cfg[BT_SLIM7].sample_rate); + + return 0; +} + +static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 1: + bt_fm_cfg[BT_SLIM7].sample_rate = SAMPLING_RATE_16KHZ; + break; + case 2: + bt_fm_cfg[BT_SLIM7].sample_rate = SAMPLING_RATE_48KHZ; + break; + case 0: + default: + bt_fm_cfg[BT_SLIM7].sample_rate = SAMPLING_RATE_8KHZ; + break; + } + pr_debug("%s: sample rates: slim7_rx = %d, value = %d\n", + __func__, + bt_fm_cfg[BT_SLIM7].sample_rate, + ucontrol->value.enumerated.item[0]); + + return 0; +} + +static const struct snd_kcontrol_new msm_snd_controls[] = { + SOC_ENUM_EXT("INT0_MI2S_RX Format", int0_mi2s_rx_format, + int_mi2s_bit_format_get, int_mi2s_bit_format_put), + SOC_ENUM_EXT("INT2_MI2S_TX Format", int2_mi2s_tx_format, + int_mi2s_bit_format_get, int_mi2s_bit_format_put), + SOC_ENUM_EXT("INT3_MI2S_TX Format", int3_mi2s_tx_format, + int_mi2s_bit_format_get, int_mi2s_bit_format_put), + SOC_ENUM_EXT("INT0_MI2S_RX SampleRate", int0_mi2s_rx_sample_rate, + int_mi2s_sample_rate_get, + int_mi2s_sample_rate_put), + SOC_ENUM_EXT("INT2_MI2S_TX SampleRate", int2_mi2s_tx_sample_rate, + int_mi2s_sample_rate_get, + int_mi2s_sample_rate_put), + SOC_ENUM_EXT("INT3_MI2S_TX SampleRate", int3_mi2s_tx_sample_rate, + int_mi2s_sample_rate_get, + int_mi2s_sample_rate_put), + SOC_ENUM_EXT("INT0_MI2S_RX SampleRate", int0_mi2s_rx_sample_rate, + int_mi2s_sample_rate_get, + int_mi2s_sample_rate_put), + SOC_ENUM_EXT("INT2_MI2S_TX SampleRate", int2_mi2s_tx_sample_rate, + int_mi2s_sample_rate_get, + int_mi2s_sample_rate_put), + SOC_ENUM_EXT("INT3_MI2S_TX SampleRate", int3_mi2s_tx_sample_rate, + int_mi2s_sample_rate_get, + int_mi2s_sample_rate_put), + SOC_ENUM_EXT("INT0_MI2S_RX Channels", int0_mi2s_rx_chs, + int_mi2s_ch_get, int_mi2s_ch_put), + SOC_ENUM_EXT("INT2_MI2S_TX Channels", int2_mi2s_tx_chs, + int_mi2s_ch_get, int_mi2s_ch_put), + SOC_ENUM_EXT("INT3_MI2S_TX Channels", int3_mi2s_tx_chs, + int_mi2s_ch_get, int_mi2s_ch_put), + SOC_ENUM_EXT("Loopback MCLK", loopback_mclk_en, + loopback_mclk_get, loopback_mclk_put), + SOC_ENUM_EXT("BT SampleRate", bt_sample_rate, + msm_bt_sample_rate_get, + msm_bt_sample_rate_put), +}; + +static const struct snd_kcontrol_new msm_sdw_controls[] = { + SOC_ENUM_EXT("INT4_MI2S_RX Format", int4_mi2s_rx_format, + int_mi2s_bit_format_get, int_mi2s_bit_format_put), + SOC_ENUM_EXT("INT4_MI2S_RX SampleRate", int4_mi2s_rx_sample_rate, + int_mi2s_sample_rate_get, + int_mi2s_sample_rate_put), + SOC_ENUM_EXT("INT4_MI2S_RX SampleRate", int4_mi2s_rx_sample_rate, + int_mi2s_sample_rate_get, + int_mi2s_sample_rate_put), + SOC_ENUM_EXT("INT4_MI2S_RX Channels", int4_mi2s_rx_chs, + int_mi2s_ch_get, int_mi2s_ch_put), + SOC_ENUM_EXT("VI_FEED_TX Channels", int5_mi2s_tx_chs, + msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put), +}; + +static int msm_dmic_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct msm_asoc_mach_data *pdata = NULL; + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + int ret = 0; + + pdata = snd_soc_card_get_drvdata(codec->component.card); + pr_debug("%s: event = %d\n", __func__, event); + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + ret = msm_cdc_pinctrl_select_active_state(pdata->dmic_gpio_p); + if (ret < 0) { + pr_err("%s: gpio set cannot be activated %sd", + __func__, "dmic_gpio"); + return ret; + } + break; + case SND_SOC_DAPM_POST_PMD: + ret = msm_cdc_pinctrl_select_sleep_state(pdata->dmic_gpio_p); + if (ret < 0) { + pr_err("%s: gpio set cannot be de-activated %sd", + __func__, "dmic_gpio"); + return ret; + } + break; + default: + pr_err("%s: invalid DAPM event %d\n", __func__, event); + return -EINVAL; + } + return 0; +} + +static int msm_int_mclk0_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct msm_asoc_mach_data *pdata = NULL; + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + int ret = 0; + + pdata = snd_soc_card_get_drvdata(codec->component.card); + pr_debug("%s: event = %d\n", __func__, event); + switch (event) { + case SND_SOC_DAPM_POST_PMD: + pr_debug("%s: mclk_res_ref = %d\n", + __func__, atomic_read(&pdata->int_mclk0_rsc_ref)); + ret = msm_cdc_pinctrl_select_sleep_state(pdata->pdm_gpio_p); + if (ret < 0) { + pr_err("%s: gpio set cannot be de-activated %sd", + __func__, "int_pdm"); + return ret; + } + if (atomic_read(&pdata->int_mclk0_rsc_ref) == 0) { + pr_debug("%s: disabling MCLK\n", __func__); + /* disable the codec mclk config*/ + msm_anlg_cdc_mclk_enable(codec, 0, true); + msm_int_enable_dig_cdc_clk(codec, 0, true); + } + break; + default: + pr_err("%s: invalid DAPM event %d\n", __func__, event); + return -EINVAL; + } + return 0; +} + +static int int_mi2s_get_port_id(int be_id) +{ + int afe_port_id; + + switch (be_id) { + case MSM_BACKEND_DAI_INT0_MI2S_RX: + afe_port_id = AFE_PORT_ID_INT0_MI2S_RX; + break; + case MSM_BACKEND_DAI_INT2_MI2S_TX: + afe_port_id = AFE_PORT_ID_INT2_MI2S_TX; + break; + case MSM_BACKEND_DAI_INT3_MI2S_TX: + afe_port_id = AFE_PORT_ID_INT3_MI2S_TX; + break; + case MSM_BACKEND_DAI_INT4_MI2S_RX: + afe_port_id = AFE_PORT_ID_INT4_MI2S_RX; + break; + case MSM_BACKEND_DAI_INT5_MI2S_TX: + afe_port_id = AFE_PORT_ID_INT5_MI2S_TX; + break; + default: + pr_err("%s: Invalid be_id: %d\n", __func__, be_id); + afe_port_id = -EINVAL; + } + + return afe_port_id; +} + +static int int_mi2s_get_index(int port_id) +{ + int index; + + switch (port_id) { + case AFE_PORT_ID_INT0_MI2S_RX: + index = INT0_MI2S; + break; + case AFE_PORT_ID_INT2_MI2S_TX: + index = INT2_MI2S; + break; + case AFE_PORT_ID_INT3_MI2S_TX: + index = INT3_MI2S; + break; + case AFE_PORT_ID_INT4_MI2S_RX: + index = INT4_MI2S; + break; + case AFE_PORT_ID_INT5_MI2S_TX: + index = INT5_MI2S; + break; + default: + pr_err("%s: Invalid port_id: %d\n", __func__, port_id); + index = -EINVAL; + } + + return index; +} + +static u32 get_int_mi2s_bits_per_sample(u32 bit_format) +{ + u32 bit_per_sample; + + switch (bit_format) { + case SNDRV_PCM_FORMAT_S24_3LE: + case SNDRV_PCM_FORMAT_S24_LE: + bit_per_sample = 32; + break; + case SNDRV_PCM_FORMAT_S16_LE: + default: + bit_per_sample = 16; + break; + } + + return bit_per_sample; +} + +static void update_int_mi2s_clk_val(int idx, int stream) +{ + u32 bit_per_sample; + + bit_per_sample = + get_int_mi2s_bits_per_sample(int_mi2s_cfg[idx].bit_format); + int_mi2s_clk[idx].clk_freq_in_hz = + (int_mi2s_cfg[idx].sample_rate * int_mi2s_cfg[idx].channels + * bit_per_sample); +} + +static int int_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable) +{ + int ret = 0; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + int port_id = 0; + int index; + + port_id = int_mi2s_get_port_id(rtd->dai_link->be_id); + if (IS_ERR_VALUE(port_id)) { + dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__); + ret = port_id; + goto done; + } + index = int_mi2s_get_index(port_id); + if (index < 0) { + dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__); + ret = port_id; + goto done; + } + if (enable) { + update_int_mi2s_clk_val(index, substream->stream); + dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__, + int_mi2s_clk[index].clk_freq_in_hz); + } + + int_mi2s_clk[index].enable = enable; + ret = afe_set_lpass_clock_v2(port_id, + &int_mi2s_clk[index]); + if (ret < 0) { + dev_err(rtd->card->dev, + "%s: afe lpass clock failed for port 0x%x , err:%d\n", + __func__, port_id, ret); + goto done; + } + +done: + return ret; +} + +static int msm_sdw_mi2s_snd_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + int ret = 0; + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + + ret = int_mi2s_set_sclk(substream, true); + if (ret < 0) { + pr_err("%s: failed to enable sclk %d\n", + __func__, ret); + return ret; + } + ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBS_CFS); + if (ret < 0) + pr_err("%s: set fmt cpu dai failed; ret=%d\n", __func__, ret); + + return ret; +} + +static void msm_sdw_mi2s_snd_shutdown(struct snd_pcm_substream *substream) +{ + int ret; + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + + ret = int_mi2s_set_sclk(substream, false); + if (ret < 0) + pr_err("%s:clock disable failed; ret=%d\n", __func__, + ret); +} + +static int msm_int_mi2s_snd_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct snd_soc_codec *codec = rtd->codec_dais[ANA_CDC]->codec; + int ret = 0; + struct msm_asoc_mach_data *pdata = NULL; + + pdata = snd_soc_card_get_drvdata(codec->component.card); + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + + ret = int_mi2s_set_sclk(substream, true); + if (ret < 0) { + pr_err("%s: failed to enable sclk %d\n", + __func__, ret); + return ret; + } + ret = msm_int_enable_dig_cdc_clk(codec, 1, true); + if (ret < 0) { + pr_err("failed to enable mclk\n"); + return ret; + } + /* Enable the codec mclk config */ + ret = msm_cdc_pinctrl_select_active_state(pdata->pdm_gpio_p); + if (ret < 0) { + pr_err("%s: gpio set cannot be activated %s\n", + __func__, "int_pdm"); + return ret; + } + msm_anlg_cdc_mclk_enable(codec, 1, true); + ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBS_CFS); + if (ret < 0) + pr_err("%s: set fmt cpu dai failed; ret=%d\n", __func__, ret); + + return ret; +} + +static void msm_int_mi2s_snd_shutdown(struct snd_pcm_substream *substream) +{ + int ret; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + + ret = int_mi2s_set_sclk(substream, false); + if (ret < 0) + pr_err("%s:clock disable failed; ret=%d\n", __func__, + ret); + if (atomic_read(&pdata->int_mclk0_rsc_ref) > 0) { + atomic_dec(&pdata->int_mclk0_rsc_ref); + pr_debug("%s: decrementing mclk_res_ref %d\n", + __func__, + atomic_read(&pdata->int_mclk0_rsc_ref)); + } +} + +static void *def_msm_int_wcd_mbhc_cal(void) +{ + void *msm_int_wcd_cal; + struct wcd_mbhc_btn_detect_cfg *btn_cfg; + u16 *btn_low, *btn_high; + + msm_int_wcd_cal = kzalloc(WCD_MBHC_CAL_SIZE(WCD_MBHC_DEF_BUTTONS, + WCD_MBHC_DEF_RLOADS), GFP_KERNEL); + if (!msm_int_wcd_cal) + return NULL; + +#define S(X, Y) ((WCD_MBHC_CAL_PLUG_TYPE_PTR(msm_int_wcd_cal)->X) = (Y)) + S(v_hs_max, 1500); +#undef S +#define S(X, Y) ((WCD_MBHC_CAL_BTN_DET_PTR(msm_int_wcd_cal)->X) = (Y)) + S(num_btn, WCD_MBHC_DEF_BUTTONS); +#undef S + + + btn_cfg = WCD_MBHC_CAL_BTN_DET_PTR(msm_int_wcd_cal); + btn_low = btn_cfg->_v_btn_low; + btn_high = ((void *)&btn_cfg->_v_btn_low) + + (sizeof(btn_cfg->_v_btn_low[0]) * btn_cfg->num_btn); + + /* + * In SW we are maintaining two sets of threshold register + * one for current source and another for Micbias. + * all btn_low corresponds to threshold for current source + * all bt_high corresponds to threshold for Micbias + * Below thresholds are based on following resistances + * 0-70 == Button 0 + * 110-180 == Button 1 + * 210-290 == Button 2 + * 360-680 == Button 3 + */ + btn_low[0] = 75; + btn_high[0] = 75; + btn_low[1] = 150; + btn_high[1] = 150; + btn_low[2] = 225; + btn_high[2] = 225; + btn_low[3] = 450; + btn_high[3] = 450; + btn_low[4] = 500; + btn_high[4] = 500; + + return msm_int_wcd_cal; +} + +static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd) +{ + struct snd_soc_codec *dig_cdc = rtd->codec_dais[DIG_CDC]->codec; + struct snd_soc_codec *ana_cdc = rtd->codec_dais[ANA_CDC]->codec; + struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(ana_cdc); + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct snd_soc_pcm_runtime *rtd_aux = rtd->card->rtd_aux; + struct snd_card *card; + struct snd_info_entry *entry; + int ret = -ENOMEM; + + pr_debug("%s(),dev_name%s\n", __func__, dev_name(cpu_dai->dev)); + + snd_soc_add_codec_controls(ana_cdc, msm_snd_controls, + ARRAY_SIZE(msm_snd_controls)); + + snd_soc_dapm_new_controls(dapm, msm_int_dapm_widgets, + ARRAY_SIZE(msm_int_dapm_widgets)); + + snd_soc_dapm_ignore_suspend(dapm, "Handset Mic"); + snd_soc_dapm_ignore_suspend(dapm, "Headset Mic"); + snd_soc_dapm_ignore_suspend(dapm, "Secondary Mic"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2"); + + snd_soc_dapm_ignore_suspend(dapm, "EAR"); + snd_soc_dapm_ignore_suspend(dapm, "HEADPHONE"); + snd_soc_dapm_ignore_suspend(dapm, "SPK_OUT"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC1"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC2"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC3"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC1"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC2"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC3"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC4"); + + snd_soc_dapm_sync(dapm); + + /* + * Send speaker configuration only for WSA8810. + * Defalut configuration is for WSA8815. + */ + if (rtd_aux && rtd_aux->component) + if (!strcmp(rtd_aux->component->name, WSA8810_NAME_1) || + !strcmp(rtd_aux->component->name, WSA8810_NAME_2)) { + msm_sdw_set_spkr_mode(rtd->codec, SPKR_MODE_1); + msm_sdw_set_spkr_gain_offset(rtd->codec, + RX_GAIN_OFFSET_M1P5_DB); + } + msm_anlg_cdc_spk_ext_pa_cb(enable_spk_ext_pa, ana_cdc); + msm_dig_cdc_hph_comp_cb(msm_config_hph_compander_gpio, dig_cdc); + + mbhc_cfg_ptr->calibration = def_msm_int_wcd_mbhc_cal(); + if (mbhc_cfg_ptr->calibration) { + ret = msm_anlg_cdc_hs_detect(ana_cdc, mbhc_cfg_ptr); + if (ret) { + pr_err("%s: msm_anlg_cdc_hs_detect failed\n", __func__); + kfree(mbhc_cfg_ptr->calibration); + return ret; + } + } + card = rtd->card->snd_card; + entry = snd_register_module_info(card->module, "codecs", + card->proc_root); + if (!entry) { + pr_debug("%s: Cannot create codecs module entry\n", + __func__); + msm_dig_codec_root = NULL; + goto done; + } + msm_dig_codec_root = entry; + msm_dig_codec_info_create_codec_entry(msm_dig_codec_root, dig_cdc); + entry = snd_register_module_info(card->module, "codecs", + card->proc_root); + if (!entry) { + pr_debug("%s: Cannot create codecs module entry\n", + __func__); + pmic_analog_codec_root = NULL; + goto done; + } + pmic_analog_codec_root = entry; + msm_anlg_codec_info_create_codec_entry(pmic_analog_codec_root, ana_cdc); +done: + return 0; +} + +static int msm_sdw_audrx_init(struct snd_soc_pcm_runtime *rtd) +{ + struct snd_soc_codec *codec = rtd->codec; + struct snd_soc_dapm_context *dapm = + snd_soc_codec_get_dapm(codec); + struct snd_card *card; + struct snd_info_entry *entry; + + snd_soc_add_codec_controls(codec, msm_sdw_controls, + ARRAY_SIZE(msm_sdw_controls)); + + snd_soc_dapm_ignore_suspend(dapm, "AIF1_SDW Playback"); + snd_soc_dapm_ignore_suspend(dapm, "VIfeed_SDW"); + snd_soc_dapm_ignore_suspend(dapm, "SPK1 OUT"); + snd_soc_dapm_ignore_suspend(dapm, "SPK2 OUT"); + snd_soc_dapm_ignore_suspend(dapm, "AIF1_SDW VI"); + snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_SDW"); + + snd_soc_dapm_sync(dapm); + msm_sdw_gpio_cb(msm_config_sdw_gpio, codec); + card = rtd->card->snd_card; + entry = snd_register_module_info(card->module, "codecs", + card->proc_root); + if (!entry) { + pr_debug("%s: Cannot create codecs module entry\n", + __func__); + msm_sdw_codec_root = NULL; + goto done; + } + msm_sdw_codec_root = entry; + msm_sdw_codec_info_create_codec_entry(msm_sdw_codec_root, codec); +done: + return 0; +} + +static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd) +{ + unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158}; + unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161}; + struct snd_soc_dai *codec_dai = rtd->codec_dai; + + return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch), + tx_ch, ARRAY_SIZE(rx_ch), rx_ch); +} + +static int msm_wcn_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *codec_dai = rtd->codec_dai; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct snd_soc_dai_link *dai_link = rtd->dai_link; + u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX]; + u32 rx_ch_cnt = 0, tx_ch_cnt = 0; + int ret; + + dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__, + codec_dai->name, codec_dai->id); + ret = snd_soc_dai_get_channel_map(codec_dai, + &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch); + if (ret) { + dev_err(rtd->dev, + "%s: failed to get BTFM codec chan map\n, err:%d\n", + __func__, ret); + goto exit; + } + + dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) be_id %d\n", + __func__, tx_ch_cnt, dai_link->be_id); + + ret = snd_soc_dai_set_channel_map(cpu_dai, + tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch); + if (ret) + dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n", + __func__, ret); + +exit: + return ret; +} + +static unsigned int tdm_param_set_slot_mask(u16 port_id, int slot_width, + int slots) +{ + unsigned int slot_mask = 0; + int i, j; + unsigned int *slot_offset; + + for (i = TDM_0; i < TDM_PORT_MAX; i++) { + slot_offset = tdm_slot_offset[i]; + + for (j = 0; j < TDM_SLOT_OFFSET_MAX; j++) { + if (slot_offset[j] != AFE_SLOT_MAPPING_OFFSET_INVALID) + slot_mask |= + (1 << ((slot_offset[j] * 8) / slot_width)); + else + break; + } + } + + return slot_mask; +} + +static int msm_tdm_snd_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + int ret = 0; + int channels, slot_width, slots; + unsigned int slot_mask; + unsigned int *slot_offset; + int offset_channels = 0; + int i; + + pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id); + + channels = params_channels(params); + switch (channels) { + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 8: + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S32_LE: + case SNDRV_PCM_FORMAT_S24_LE: + case SNDRV_PCM_FORMAT_S16_LE: + /* + * up to 8 channels HW config should + * use 32 bit slot width for max support of + * stream bit width. (slot_width > bit_width) + */ + slot_width = 32; + break; + default: + pr_err("%s: invalid param format 0x%x\n", + __func__, params_format(params)); + return -EINVAL; + } + slots = 8; + slot_mask = tdm_param_set_slot_mask(cpu_dai->id, + slot_width, + slots); + if (!slot_mask) { + pr_err("%s: invalid slot_mask 0x%x\n", + __func__, slot_mask); + return -EINVAL; + } + break; + default: + pr_err("%s: invalid param channels %d\n", + __func__, channels); + return -EINVAL; + } + /* currently only supporting TDM_RX_0 and TDM_TX_0 */ + switch (cpu_dai->id) { + case AFE_PORT_ID_PRIMARY_TDM_RX: + case AFE_PORT_ID_SECONDARY_TDM_RX: + case AFE_PORT_ID_TERTIARY_TDM_RX: + case AFE_PORT_ID_QUATERNARY_TDM_RX: + case AFE_PORT_ID_PRIMARY_TDM_TX: + case AFE_PORT_ID_SECONDARY_TDM_TX: + case AFE_PORT_ID_TERTIARY_TDM_TX: + case AFE_PORT_ID_QUATERNARY_TDM_TX: + slot_offset = tdm_slot_offset[TDM_0]; + break; + default: + pr_err("%s: dai id 0x%x not supported\n", + __func__, cpu_dai->id); + return -EINVAL; + } + + for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) { + if (slot_offset[i] != AFE_SLOT_MAPPING_OFFSET_INVALID) + offset_channels++; + else + break; + } + + if (offset_channels == 0) { + pr_err("%s: slot offset not supported, offset_channels %d\n", + __func__, offset_channels); + return -EINVAL; + } + + if (channels > offset_channels) { + pr_err("%s: channels %d exceed offset_channels %d\n", + __func__, channels, offset_channels); + return -EINVAL; + } + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask, + slots, slot_width); + if (ret < 0) { + pr_err("%s: failed to set tdm slot, err:%d\n", + __func__, ret); + goto end; + } + + ret = snd_soc_dai_set_channel_map(cpu_dai, 0, NULL, + channels, slot_offset); + if (ret < 0) { + pr_err("%s: failed to set channel map, err:%d\n", + __func__, ret); + goto end; + } + } else { + ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0, + slots, slot_width); + if (ret < 0) { + pr_err("%s: failed to set tdm slot, err:%d\n", + __func__, ret); + goto end; + } + + ret = snd_soc_dai_set_channel_map(cpu_dai, channels, + slot_offset, 0, NULL); + if (ret < 0) { + pr_err("%s: failed to set channel map, err:%d\n", + __func__, ret); + goto end; + } + } +end: + return ret; +} + +static struct snd_soc_ops msm_tdm_be_ops = { + .hw_params = msm_tdm_snd_hw_params +}; + +static struct snd_soc_ops msm_wcn_ops = { + .hw_params = msm_wcn_hw_params, +}; + +static struct snd_soc_ops msm_mi2s_be_ops = { + .startup = msm_mi2s_snd_startup, + .shutdown = msm_mi2s_snd_shutdown, +}; + +static struct snd_soc_ops msm_aux_pcm_be_ops = { + .startup = msm_aux_pcm_snd_startup, + .shutdown = msm_aux_pcm_snd_shutdown, +}; + +static struct snd_soc_ops msm_int_mi2s_be_ops = { + .startup = msm_int_mi2s_snd_startup, + .shutdown = msm_int_mi2s_snd_shutdown, +}; + +static struct snd_soc_ops msm_sdw_mi2s_be_ops = { + .startup = msm_sdw_mi2s_snd_startup, + .shutdown = msm_sdw_mi2s_snd_shutdown, +}; + +struct snd_soc_dai_link_component dlc_rx1[] = { + { + .of_node = NULL, + .dai_name = "msm_dig_cdc_dai_rx1", + }, + { + .of_node = NULL, + .dai_name = "msm_anlg_cdc_i2s_rx1", + }, +}; + +struct snd_soc_dai_link_component dlc_tx1[] = { + { + .of_node = NULL, + .dai_name = "msm_dig_cdc_dai_tx1", + }, + { + .of_node = NULL, + .dai_name = "msm_anlg_cdc_i2s_tx1", + }, +}; + +struct snd_soc_dai_link_component dlc_tx2[] = { + { + .of_node = NULL, + .dai_name = "msm_dig_cdc_dai_tx2", + }, + { + .of_node = NULL, + .dai_name = "msm_anlg_cdc_i2s_tx2", + }, +}; + +/* Digital audio interface glue - connects codec <---> CPU */ +static struct snd_soc_dai_link msm_int_dai[] = { + /* FrontEnd DAI Links */ + {/* hw:x,0 */ + .name = MSM_DAILINK_NAME(Media1), + .stream_name = "MultiMedia1", + .cpu_dai_name = "MultiMedia1", + .platform_name = "msm-pcm-dsp.0", + .dynamic = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA1 + }, + {/* hw:x,1 */ + .name = MSM_DAILINK_NAME(Media2), + .stream_name = "MultiMedia2", + .cpu_dai_name = "MultiMedia2", + .platform_name = "msm-pcm-dsp.0", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA2, + }, + {/* hw:x,2 */ + .name = "VoiceMMode1", + .stream_name = "VoiceMMode1", + .cpu_dai_name = "VoiceMMode1", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .be_id = MSM_FRONTEND_DAI_VOICEMMODE1, + }, + {/* hw:x,3 */ + .name = "MSM VoIP", + .stream_name = "VoIP", + .cpu_dai_name = "VoIP", + .platform_name = "msm-voip-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .be_id = MSM_FRONTEND_DAI_VOIP, + }, + {/* hw:x,4 */ + .name = MSM_DAILINK_NAME(ULL), + .stream_name = "ULL", + .cpu_dai_name = "MultiMedia3", + .platform_name = "msm-pcm-dsp.2", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA3, + }, + /* Hostless PCM purpose */ + {/* hw:x,5 */ + .name = "INT4 MI2S_RX Hostless", + .stream_name = "INT4 MI2S_RX Hostless", + .cpu_dai_name = "INT4_MI2S_RX_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dailink has playback support */ + .ignore_pmdown_time = 1, + /* This dainlink has MI2S support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,6 */ + .name = "MSM AFE-PCM RX", + .stream_name = "AFE-PROXY RX", + .cpu_dai_name = "msm-dai-q6-dev.241", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .platform_name = "msm-pcm-afe", + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + }, + {/* hw:x,7 */ + .name = "MSM AFE-PCM TX", + .stream_name = "AFE-PROXY TX", + .cpu_dai_name = "msm-dai-q6-dev.240", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .platform_name = "msm-pcm-afe", + .ignore_suspend = 1, + }, + {/* hw:x,8 */ + .name = MSM_DAILINK_NAME(Compress1), + .stream_name = "Compress1", + .cpu_dai_name = "MultiMedia4", + .platform_name = "msm-compress-dsp", + .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS, + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA4, + }, + {/* hw:x,9*/ + .name = "AUXPCM Hostless", + .stream_name = "AUXPCM Hostless", + .cpu_dai_name = "AUXPCM_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,10 */ + .name = "SLIMBUS_1 Hostless", + .stream_name = "SLIMBUS_1 Hostless", + .cpu_dai_name = "SLIMBUS1_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,11 */ + .name = "INT3 MI2S_TX Hostless", + .stream_name = "INT3 MI2S_TX Hostless", + .cpu_dai_name = "INT3_MI2S_TX_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,12 */ + .name = "SLIMBUS_7 Hostless", + .stream_name = "SLIMBUS_7 Hostless", + .cpu_dai_name = "SLIMBUS7_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,13 */ + .name = MSM_DAILINK_NAME(LowLatency), + .stream_name = "MultiMedia5", + .cpu_dai_name = "MultiMedia5", + .platform_name = "msm-pcm-dsp.1", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA5, + }, + /* LSM FE */ + {/* hw:x,14 */ + .name = "Listen 1 Audio Service", + .stream_name = "Listen 1 Audio Service", + .cpu_dai_name = "LSM1", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .be_id = MSM_FRONTEND_DAI_LSM1, + }, + {/* hw:x,15 */ + .name = MSM_DAILINK_NAME(Compress2), + .stream_name = "Compress2", + .cpu_dai_name = "MultiMedia7", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA7, + }, + {/* hw:x,16 */ + .name = MSM_DAILINK_NAME(Compress3), + .stream_name = "Compress3", + .cpu_dai_name = "MultiMedia10", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA10, + }, + {/* hw:x,17 */ + .name = MSM_DAILINK_NAME(ULL_NOIRQ), + .stream_name = "MM_NOIRQ", + .cpu_dai_name = "MultiMedia8", + .platform_name = "msm-pcm-dsp-noirq", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA8, + }, + {/* hw:x,18 */ + .name = "HDMI_RX_HOSTLESS", + .stream_name = "HDMI_RX_HOSTLESS", + .cpu_dai_name = "HDMI_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,19 */ + .name = "VoiceMMode2", + .stream_name = "VoiceMMode2", + .cpu_dai_name = "VoiceMMode2", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .be_id = MSM_FRONTEND_DAI_VOICEMMODE2, + }, + {/* hw:x,20 */ + .name = "Listen 2 Audio Service", + .stream_name = "Listen 2 Audio Service", + .cpu_dai_name = "LSM2", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .be_id = MSM_FRONTEND_DAI_LSM2, + }, + {/* hw:x,21 */ + .name = "Listen 3 Audio Service", + .stream_name = "Listen 3 Audio Service", + .cpu_dai_name = "LSM3", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .be_id = MSM_FRONTEND_DAI_LSM3, + }, + {/* hw:x,22 */ + .name = "Listen 4 Audio Service", + .stream_name = "Listen 4 Audio Service", + .cpu_dai_name = "LSM4", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .be_id = MSM_FRONTEND_DAI_LSM4, + }, + {/* hw:x,23 */ + .name = "Listen 5 Audio Service", + .stream_name = "Listen 5 Audio Service", + .cpu_dai_name = "LSM5", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .be_id = MSM_FRONTEND_DAI_LSM5, + }, + {/* hw:x,24 */ + .name = "Listen 6 Audio Service", + .stream_name = "Listen 6 Audio Service", + .cpu_dai_name = "LSM6", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .be_id = MSM_FRONTEND_DAI_LSM6 + }, + {/* hw:x,25 */ + .name = "Listen 7 Audio Service", + .stream_name = "Listen 7 Audio Service", + .cpu_dai_name = "LSM7", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .be_id = MSM_FRONTEND_DAI_LSM7, + }, + {/* hw:x,26 */ + .name = "Listen 8 Audio Service", + .stream_name = "Listen 8 Audio Service", + .cpu_dai_name = "LSM8", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .be_id = MSM_FRONTEND_DAI_LSM8, + }, + {/* hw:x,27 */ + .name = MSM_DAILINK_NAME(Media9), + .stream_name = "MultiMedia9", + .cpu_dai_name = "MultiMedia9", + .platform_name = "msm-pcm-dsp.0", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA9, + }, + {/* hw:x,28 */ + .name = MSM_DAILINK_NAME(Compress4), + .stream_name = "Compress4", + .cpu_dai_name = "MultiMedia11", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA11, + }, + {/* hw:x,29 */ + .name = MSM_DAILINK_NAME(Compress5), + .stream_name = "Compress5", + .cpu_dai_name = "MultiMedia12", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA12, + }, + {/* hw:x,30 */ + .name = MSM_DAILINK_NAME(Compress6), + .stream_name = "Compress6", + .cpu_dai_name = "MultiMedia13", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA13, + }, + {/* hw:x,31 */ + .name = MSM_DAILINK_NAME(Compress7), + .stream_name = "Compress7", + .cpu_dai_name = "MultiMedia14", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA14, + }, + {/* hw:x,32 */ + .name = MSM_DAILINK_NAME(Compress8), + .stream_name = "Compress8", + .cpu_dai_name = "MultiMedia15", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA15, + }, + {/* hw:x,33 */ + .name = MSM_DAILINK_NAME(Compress9), + .stream_name = "Compress9", + .cpu_dai_name = "MultiMedia16", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .be_id = MSM_FRONTEND_DAI_MULTIMEDIA16, + }, + {/* hw:x,34 */ + .name = "SLIMBUS_8 Hostless", + .stream_name = "SLIMBUS8_HOSTLESS Capture", + .cpu_dai_name = "SLIMBUS8_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,35 */ + .name = LPASS_BE_INT5_MI2S_TX, + .stream_name = "INT5_mi2s Capture", + .cpu_dai_name = "msm-dai-q6-mi2s.12", + .platform_name = "msm-pcm-hostless", + .codec_name = "msm_sdw_codec", + .codec_dai_name = "msm_sdw_vifeedback", + .be_id = MSM_BACKEND_DAI_INT5_MI2S_TX, + .be_hw_params_fixup = int_mi2s_be_hw_params_fixup, + .ops = &msm_sdw_mi2s_be_ops, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .dpcm_capture = 1, + .ignore_pmdown_time = 1, + }, + {/* hw:x,36 */ + .name = "Primary MI2S_RX Hostless", + .stream_name = "Primary MI2S_RX Hostless", + .cpu_dai_name = "PRI_MI2S_RX_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dailink has playback support */ + .ignore_pmdown_time = 1, + /* This dainlink has MI2S support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,37 */ + .name = "Secondary MI2S_RX Hostless", + .stream_name = "Secondary MI2S_RX Hostless", + .cpu_dai_name = "SEC_MI2S_RX_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dailink has playback support */ + .ignore_pmdown_time = 1, + /* This dainlink has MI2S support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,38 */ + .name = "Tertiary MI2S_RX Hostless", + .stream_name = "Tertiary MI2S_RX Hostless", + .cpu_dai_name = "TERT_MI2S_RX_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dailink has playback support */ + .ignore_pmdown_time = 1, + /* This dainlink has MI2S support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,39 */ + .name = "INT0 MI2S_RX Hostless", + .stream_name = "INT0 MI2S_RX Hostless", + .cpu_dai_name = "INT0_MI2S_RX_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dailink has playback support */ + .ignore_pmdown_time = 1, + /* This dainlink has MI2S support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + /* Backend I2S DAI Links */ + { + .name = LPASS_BE_INT0_MI2S_RX, + .stream_name = "INT0 MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.7", + .platform_name = "msm-pcm-routing", + .codecs = dlc_rx1, + .num_codecs = CODECS_MAX, + .no_pcm = 1, + .dpcm_playback = 1, + .async_ops = ASYNC_DPCM_SND_SOC_PREPARE | + ASYNC_DPCM_SND_SOC_HW_PARAMS, + .be_id = MSM_BACKEND_DAI_INT0_MI2S_RX, + .init = &msm_audrx_init, + .be_hw_params_fixup = int_mi2s_be_hw_params_fixup, + .ops = &msm_int_mi2s_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_INT3_MI2S_TX, + .stream_name = "INT3 MI2S Capture", + .cpu_dai_name = "msm-dai-q6-mi2s.10", + .platform_name = "msm-pcm-routing", + .codecs = dlc_tx1, + .num_codecs = CODECS_MAX, + .no_pcm = 1, + .dpcm_capture = 1, + .async_ops = ASYNC_DPCM_SND_SOC_PREPARE | + ASYNC_DPCM_SND_SOC_HW_PARAMS, + .be_id = MSM_BACKEND_DAI_INT3_MI2S_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ops = &msm_int_mi2s_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_INT4_MI2S_RX, + .stream_name = "INT4 MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.11", + .platform_name = "msm-pcm-routing", + .codec_name = "msm_sdw_codec", + .codec_dai_name = "msm_sdw_i2s_rx1", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_INT4_MI2S_RX, + .init = &msm_sdw_audrx_init, + .be_hw_params_fixup = int_mi2s_be_hw_params_fixup, + .ops = &msm_sdw_mi2s_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_INT2_MI2S_TX, + .stream_name = "INT2 MI2S Capture", + .cpu_dai_name = "msm-dai-q6-mi2s.9", + .platform_name = "msm-pcm-routing", + .codecs = dlc_tx2, + .num_codecs = CODECS_MAX, + .no_pcm = 1, + .dpcm_capture = 1, + .async_ops = ASYNC_DPCM_SND_SOC_PREPARE | + ASYNC_DPCM_SND_SOC_HW_PARAMS, + .be_id = MSM_BACKEND_DAI_INT2_MI2S_TX, + .be_hw_params_fixup = int_mi2s_be_hw_params_fixup, + .ops = &msm_int_mi2s_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_AFE_PCM_RX, + .stream_name = "AFE Playback", + .cpu_dai_name = "msm-dai-q6-dev.224", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_AFE_PCM_RX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_AFE_PCM_TX, + .stream_name = "AFE Capture", + .cpu_dai_name = "msm-dai-q6-dev.225", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_AFE_PCM_TX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ignore_suspend = 1, + }, + /* Incall Record Uplink BACK END DAI Link */ + { + .name = LPASS_BE_INCALL_RECORD_TX, + .stream_name = "Voice Uplink Capture", + .cpu_dai_name = "msm-dai-q6-dev.32772", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_INCALL_RECORD_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_suspend = 1, + }, + /* Incall Record Downlink BACK END DAI Link */ + { + .name = LPASS_BE_INCALL_RECORD_RX, + .stream_name = "Voice Downlink Capture", + .cpu_dai_name = "msm-dai-q6-dev.32771", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_INCALL_RECORD_RX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_suspend = 1, + }, + /* Incall Music BACK END DAI Link */ + { + .name = LPASS_BE_VOICE_PLAYBACK_TX, + .stream_name = "Voice Farend Playback", + .cpu_dai_name = "msm-dai-q6-dev.32773", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_suspend = 1, + }, + /* Incall Music 2 BACK END DAI Link */ + { + .name = LPASS_BE_VOICE2_PLAYBACK_TX, + .stream_name = "Voice2 Farend Playback", + .cpu_dai_name = "msm-dai-q6-dev.32770", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_USB_AUDIO_RX, + .stream_name = "USB Audio Playback", + .cpu_dai_name = "msm-dai-q6-dev.28672", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_USB_RX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_USB_AUDIO_TX, + .stream_name = "USB Audio Capture", + .cpu_dai_name = "msm-dai-q6-dev.28673", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_USB_TX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_PRI_TDM_RX_0, + .stream_name = "Primary TDM0 Playback", + .cpu_dai_name = "msm-dai-q6-tdm.36864", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_PRI_TDM_RX_0, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_tdm_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_PRI_TDM_TX_0, + .stream_name = "Primary TDM0 Capture", + .cpu_dai_name = "msm-dai-q6-tdm.36865", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_PRI_TDM_TX_0, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_tdm_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SEC_TDM_RX_0, + .stream_name = "Secondary TDM0 Playback", + .cpu_dai_name = "msm-dai-q6-tdm.36880", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_SEC_TDM_RX_0, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_tdm_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SEC_TDM_TX_0, + .stream_name = "Secondary TDM0 Capture", + .cpu_dai_name = "msm-dai-q6-tdm.36881", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_SEC_TDM_TX_0, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_tdm_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_TERT_TDM_RX_0, + .stream_name = "Tertiary TDM0 Playback", + .cpu_dai_name = "msm-dai-q6-tdm.36896", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_TERT_TDM_RX_0, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_tdm_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_TERT_TDM_TX_0, + .stream_name = "Tertiary TDM0 Capture", + .cpu_dai_name = "msm-dai-q6-tdm.36897", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_TERT_TDM_TX_0, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_tdm_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_QUAT_TDM_RX_0, + .stream_name = "Quaternary TDM0 Playback", + .cpu_dai_name = "msm-dai-q6-tdm.36912", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_QUAT_TDM_RX_0, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_tdm_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_QUAT_TDM_TX_0, + .stream_name = "Quaternary TDM0 Capture", + .cpu_dai_name = "msm-dai-q6-tdm.36913", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_QUAT_TDM_TX_0, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_tdm_be_ops, + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = { + { + .name = LPASS_BE_PRI_MI2S_RX, + .stream_name = "Primary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.0", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_PRI_MI2S_RX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_mi2s_be_ops, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + }, + { + .name = LPASS_BE_PRI_MI2S_TX, + .stream_name = "Primary MI2S Capture", + .cpu_dai_name = "msm-dai-q6-mi2s.0", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_PRI_MI2S_TX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_mi2s_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SEC_MI2S_RX, + .stream_name = "Secondary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.1", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_mi2s_be_ops, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + }, + { + .name = LPASS_BE_SEC_MI2S_TX, + .stream_name = "Secondary MI2S Capture", + .cpu_dai_name = "msm-dai-q6-mi2s.1", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_mi2s_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_TERT_MI2S_RX, + .stream_name = "Tertiary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.2", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_mi2s_be_ops, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + }, + { + .name = LPASS_BE_TERT_MI2S_TX, + .stream_name = "Tertiary MI2S Capture", + .cpu_dai_name = "msm-dai-q6-mi2s.2", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_mi2s_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_QUAT_MI2S_RX, + .stream_name = "Quaternary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.3", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_mi2s_be_ops, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + }, + { + .name = LPASS_BE_QUAT_MI2S_TX, + .stream_name = "Quaternary MI2S Capture", + .cpu_dai_name = "msm-dai-q6-mi2s.3", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ops = &msm_mi2s_be_ops, + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = { + /* Primary AUX PCM Backend DAI Links */ + { + .name = LPASS_BE_AUXPCM_RX, + .stream_name = "AUX PCM Playback", + .cpu_dai_name = "msm-dai-q6-auxpcm.1", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_AUXPCM_RX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + .ops = &msm_aux_pcm_be_ops, + }, + { + .name = LPASS_BE_AUXPCM_TX, + .stream_name = "AUX PCM Capture", + .cpu_dai_name = "msm-dai-q6-auxpcm.1", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_AUXPCM_TX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + .ops = &msm_aux_pcm_be_ops, + }, + /* Secondary AUX PCM Backend DAI Links */ + { + .name = LPASS_BE_SEC_AUXPCM_RX, + .stream_name = "Sec AUX PCM Playback", + .cpu_dai_name = "msm-dai-q6-auxpcm.2", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_SEC_AUXPCM_RX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + .ops = &msm_aux_pcm_be_ops, + }, + { + .name = LPASS_BE_SEC_AUXPCM_TX, + .stream_name = "Sec AUX PCM Capture", + .cpu_dai_name = "msm-dai-q6-auxpcm.2", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_SEC_AUXPCM_TX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .ops = &msm_aux_pcm_be_ops, + }, + /* Tertiary AUX PCM Backend DAI Links */ + { + .name = LPASS_BE_TERT_AUXPCM_RX, + .stream_name = "Tert AUX PCM Playback", + .cpu_dai_name = "msm-dai-q6-auxpcm.3", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_TERT_AUXPCM_RX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + .ops = &msm_aux_pcm_be_ops, + }, + { + .name = LPASS_BE_TERT_AUXPCM_TX, + .stream_name = "Tert AUX PCM Capture", + .cpu_dai_name = "msm-dai-q6-auxpcm.3", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_TERT_AUXPCM_TX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .ops = &msm_aux_pcm_be_ops, + }, + /* Quaternary AUX PCM Backend DAI Links */ + { + .name = LPASS_BE_QUAT_AUXPCM_RX, + .stream_name = "Quat AUX PCM Playback", + .cpu_dai_name = "msm-dai-q6-auxpcm.4", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + .ops = &msm_aux_pcm_be_ops, + }, + { + .name = LPASS_BE_QUAT_AUXPCM_TX, + .stream_name = "Quat AUX PCM Capture", + .cpu_dai_name = "msm-dai-q6-auxpcm.4", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX, + .be_hw_params_fixup = msm_common_be_hw_params_fixup, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .ops = &msm_aux_pcm_be_ops, + }, +}; + + +static struct snd_soc_dai_link msm_wcn_be_dai_links[] = { + { + .name = LPASS_BE_SLIMBUS_7_RX, + .stream_name = "Slimbus7 Playback", + .cpu_dai_name = "msm-dai-q6-dev.16398", + .platform_name = "msm-pcm-routing", + .codec_name = "btfmslim_slave", + /* BT codec driver determines capabilities based on + * dai name, bt codecdai name should always contains + * supported usecase information + */ + .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx", + .no_pcm = 1, + .dpcm_playback = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_7_RX, + .be_hw_params_fixup = msm_btfm_be_hw_params_fixup, + .ops = &msm_wcn_ops, + /* dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_7_TX, + .stream_name = "Slimbus7 Capture", + .cpu_dai_name = "msm-dai-q6-dev.16399", + .platform_name = "msm-pcm-routing", + .codec_name = "btfmslim_slave", + .codec_dai_name = "btfm_bt_sco_slim_tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_7_TX, + .be_hw_params_fixup = msm_btfm_be_hw_params_fixup, + .ops = &msm_wcn_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_8_TX, + .stream_name = "Slimbus8 Capture", + .cpu_dai_name = "msm-dai-q6-dev.16401", + .platform_name = "msm-pcm-routing", + .codec_name = "btfmslim_slave", + .codec_dai_name = "btfm_fm_slim_tx", + .no_pcm = 1, + .dpcm_capture = 1, + .be_id = MSM_BACKEND_DAI_SLIMBUS_8_TX, + .be_hw_params_fixup = msm_btfm_be_hw_params_fixup, + .init = &msm_wcn_init, + .ops = &msm_wcn_ops, + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm_int_dai_links[ +ARRAY_SIZE(msm_int_dai) + +ARRAY_SIZE(msm_mi2s_be_dai_links) + +ARRAY_SIZE(msm_auxpcm_be_dai_links)+ +ARRAY_SIZE(msm_wcn_be_dai_links)]; + +static struct snd_soc_card sdm660_card = { + /* snd_soc_card_sdm660 */ + .name = "sdm660-snd-card", + .dai_link = msm_int_dai, + .num_links = ARRAY_SIZE(msm_int_dai), +}; + +static void msm_disable_int_mclk0(struct work_struct *work) +{ + struct msm_asoc_mach_data *pdata = NULL; + struct delayed_work *dwork; + int ret = 0; + + dwork = to_delayed_work(work); + pdata = container_of(dwork, struct msm_asoc_mach_data, + disable_int_mclk0_work); + mutex_lock(&pdata->cdc_int_mclk0_mutex); + pr_debug("%s: mclk_enabled %d mclk_rsc_ref %d\n", __func__, + atomic_read(&pdata->int_mclk0_enabled), + atomic_read(&pdata->int_mclk0_rsc_ref)); + + if (atomic_read(&pdata->int_mclk0_enabled) == true + && atomic_read(&pdata->int_mclk0_rsc_ref) == 0) { + pr_debug("Disable the mclk\n"); + pdata->digital_cdc_core_clk.enable = 0; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_INT0_MI2S_RX, + &pdata->digital_cdc_core_clk); + if (ret < 0) + pr_err("%s failed to disable the CCLK\n", __func__); + atomic_set(&pdata->int_mclk0_enabled, false); + } + mutex_unlock(&pdata->cdc_int_mclk0_mutex); +} + +static void msm_int_dt_parse_cap_info(struct platform_device *pdev, + struct msm_asoc_mach_data *pdata) +{ + const char *ext1_cap = "qcom,msm-micbias1-ext-cap"; + const char *ext2_cap = "qcom,msm-micbias2-ext-cap"; + + pdata->micbias1_cap_mode = + (of_property_read_bool(pdev->dev.of_node, ext1_cap) ? + MICBIAS_EXT_BYP_CAP : MICBIAS_NO_EXT_BYP_CAP); + + pdata->micbias2_cap_mode = + (of_property_read_bool(pdev->dev.of_node, ext2_cap) ? + MICBIAS_EXT_BYP_CAP : MICBIAS_NO_EXT_BYP_CAP); +} + +static struct snd_soc_card *msm_int_populate_sndcard_dailinks( + struct device *dev) +{ + struct snd_soc_card *card = &sdm660_card; + struct snd_soc_dai_link *dailink; + int len1; + + card->name = dev_name(dev); + len1 = ARRAY_SIZE(msm_int_dai); + memcpy(msm_int_dai_links, msm_int_dai, sizeof(msm_int_dai)); + dailink = msm_int_dai_links; + if (of_property_read_bool(dev->of_node, + "qcom,mi2s-audio-intf")) { + memcpy(dailink + len1, + msm_mi2s_be_dai_links, + sizeof(msm_mi2s_be_dai_links)); + len1 += ARRAY_SIZE(msm_mi2s_be_dai_links); + } + if (of_property_read_bool(dev->of_node, + "qcom,auxpcm-audio-intf")) { + memcpy(dailink + len1, + msm_auxpcm_be_dai_links, + sizeof(msm_auxpcm_be_dai_links)); + len1 += ARRAY_SIZE(msm_auxpcm_be_dai_links); + } + if (of_property_read_bool(dev->of_node, "qcom,wcn-btfm")) { + dev_dbg(dev, "%s(): WCN BTFM support present\n", + __func__); + memcpy(dailink + len1, + msm_wcn_be_dai_links, + sizeof(msm_wcn_be_dai_links)); + len1 += ARRAY_SIZE(msm_wcn_be_dai_links); + } + card->dai_link = dailink; + card->num_links = len1; + return card; +} + +static int msm_internal_init(struct platform_device *pdev, + struct msm_asoc_mach_data *pdata, + struct snd_soc_card *card) +{ + const char *type = NULL; + const char *hs_micbias_type = "qcom,msm-hs-micbias-type"; + int ret; + + ret = is_ext_spk_gpio_support(pdev, pdata); + if (ret < 0) + dev_dbg(&pdev->dev, + "%s: doesn't support external speaker pa\n", + __func__); + + ret = of_property_read_string(pdev->dev.of_node, + hs_micbias_type, &type); + if (ret) { + dev_err(&pdev->dev, "%s: missing %s in dt node\n", + __func__, hs_micbias_type); + goto err; + } + if (!strcmp(type, "external")) { + dev_dbg(&pdev->dev, "Headset is using external micbias\n"); + mbhc_cfg_ptr->hs_ext_micbias = true; + } else { + dev_dbg(&pdev->dev, "Headset is using internal micbias\n"); + mbhc_cfg_ptr->hs_ext_micbias = false; + } + + /* initialize the int_mclk0 */ + pdata->digital_cdc_core_clk.clk_set_minor_version = + AFE_API_VERSION_I2S_CONFIG; + pdata->digital_cdc_core_clk.clk_id = + Q6AFE_LPASS_CLK_ID_INT_MCLK_0; + pdata->digital_cdc_core_clk.clk_freq_in_hz = 0; + pdata->digital_cdc_core_clk.clk_attri = + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO; + pdata->digital_cdc_core_clk.clk_root = + Q6AFE_LPASS_CLK_ROOT_DEFAULT; + pdata->digital_cdc_core_clk.enable = 1; + + /* Initialize loopback mode to false */ + pdata->lb_mode = false; + + msm_int_dt_parse_cap_info(pdev, pdata); + + card->dev = &pdev->dev; + platform_set_drvdata(pdev, card); + snd_soc_card_set_drvdata(card, pdata); + ret = snd_soc_of_parse_card_name(card, "qcom,model"); + if (ret) + goto err; + /* initialize timer */ + INIT_DELAYED_WORK(&pdata->disable_int_mclk0_work, + msm_disable_int_mclk0); + mutex_init(&pdata->cdc_int_mclk0_mutex); + atomic_set(&pdata->int_mclk0_rsc_ref, 0); + atomic_set(&pdata->int_mclk0_enabled, false); + + dev_info(&pdev->dev, "%s: default codec configured\n", __func__); + + return 0; +err: + return ret; +} + +/** + * msm_int_cdc_init - internal codec machine specific init. + * + * @pdev: platform device handle + * @pdata: private data of machine driver + * @card: sound card pointer reference + * @mbhc_cfg: MBHC config reference + * + * Returns 0. + */ +int msm_int_cdc_init(struct platform_device *pdev, + struct msm_asoc_mach_data *pdata, + struct snd_soc_card **card, + struct wcd_mbhc_config *mbhc_cfg) +{ + mbhc_cfg_ptr = mbhc_cfg; + + *card = msm_int_populate_sndcard_dailinks(&pdev->dev); + msm_internal_init(pdev, pdata, *card); + return 0; +} +EXPORT_SYMBOL(msm_int_cdc_init); diff --git a/sound/soc/msm/sdm660-internal.h b/sound/soc/msm/sdm660-internal.h new file mode 100644 index 000000000000..ccc62b8f33dc --- /dev/null +++ b/sound/soc/msm/sdm660-internal.h @@ -0,0 +1,32 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SDM660_INTERNAL +#define __SDM660_INTERNAL + +#include + +#ifdef CONFIG_SND_SOC_INT_CODEC +int msm_int_cdc_init(struct platform_device *pdev, + struct msm_asoc_mach_data *pdata, + struct snd_soc_card **card, + struct wcd_mbhc_config *mbhc_cfg); +#else +int msm_int_cdc_init(struct platform_device *pdev, + struct msm_asoc_mach_data *pdata, + struct snd_soc_card **card, + struct wcd_mbhc_config *mbhc_cfg) +{ + return 0; +} +#endif +#endif -- cgit v1.2.3