diff options
| author | Subhash Jadavani <subhashj@codeaurora.org> | 2015-12-17 18:21:39 -0800 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-22 11:01:31 -0700 |
| commit | f4b811368a2cfaac24080149c6740b262d4d7c0b (patch) | |
| tree | f60c5793ea5e4be86caad11550cd8f5eb8f01a50 | |
| parent | 927cc5408937bca2c417aee84ba2ada905e703b8 (diff) | |
phy: qcom-ufs-qmp-14nm: disable filler symbol relock
FILLER relock on error recovery may create an alignment that is not
compatible with host controller. When this issue happens, host controller
no longer detects symbols until LINE-RESET is done by host controller as
a recovery sequence. This change disables FILLER symbol relock.
Change-Id: Id7147bfb0de6be45de4936fe3429a9ad76a3868b
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
| -rw-r--r-- | drivers/phy/phy-qcom-ufs-qmp-14nm.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/phy/phy-qcom-ufs-qmp-14nm.h b/drivers/phy/phy-qcom-ufs-qmp-14nm.h index 038afd8e18db..46e652f34401 100644 --- a/drivers/phy/phy-qcom-ufs-qmp-14nm.h +++ b/drivers/phy/phy-qcom-ufs-qmp-14nm.h @@ -90,6 +90,7 @@ #define UFS_PHY_TX_SMALL_AMP_DRV_LVL PHY_OFF(0x3C) #define UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP PHY_OFF(0xCC) #define UFS_PHY_LINECFG_DISABLE PHY_OFF(0x138) +#define UFS_PHY_RX_SYM_RESYNC_CTRL PHY_OFF(0x13C) #define UFS_PHY_RX_SIGDET_CTRL2 PHY_OFF(0x148) #define UFS_PHY_RX_PWM_GEAR_BAND PHY_OFF(0x154) #define UFS_PHY_PCS_READY_STATUS PHY_OFF(0x168) @@ -204,6 +205,7 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_2_0_0[] = { UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x12), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x06), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYM_RESYNC_CTRL, 0x03), /* * UFS_PHY_RX_PWM_GEAR_BAND configuration is changed after the power up @@ -296,6 +298,7 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_2_1_0[] = { UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x12), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x06), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYM_RESYNC_CTRL, 0x03), }; static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_2_2_0[] = { @@ -377,6 +380,7 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_2_2_0[] = { UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0A), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYM_RESYNC_CTRL, 0x03), }; static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = { |