diff options
| author | Subhash Jadavani <subhashj@codeaurora.org> | 2015-11-19 11:06:05 -0800 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-22 11:01:30 -0700 |
| commit | 927cc5408937bca2c417aee84ba2ada905e703b8 (patch) | |
| tree | 55e1e0ffe05acf2d958bc35f92a18e65f03565ea | |
| parent | 415748c434a90a0e1b3f6982bd9f2fba256ab60b (diff) | |
phy: qcom-ufs-qmp-14nm: update rx min stall noconfig time
Hibernate entry failures have been observed with some UFS devices.
The UFS PHY Rx termination is not disabled within the specified
RX_Min_STALL_NoConfig_Time_Capability of 15 SI. The UFS device enables
mid-termination after RX_Min_STALL_NoConfig_Time_Capability SI. The
combination of Rx terminated and device Tx mid-termination collapses
the line state to near the differential mid-point. The signal detect
may report the line state incorrectly as DIF-P. The incorrect DIF-P
moves the Rx FSM into the HS-Burst state rather than the intended
Hibern8 state. Fix this issue by setting the UFS PHY's
RX_MIN_STALL_NOCONFIG_TIME_CAPABILITY to 40.
Change-Id: I475e03686831e8131fd7ec1c30e6e8f53a6e188c
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
| -rw-r--r-- | drivers/phy/phy-qcom-ufs-qmp-14nm.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/phy/phy-qcom-ufs-qmp-14nm.h b/drivers/phy/phy-qcom-ufs-qmp-14nm.h index 4f1c37ba7c8a..038afd8e18db 100644 --- a/drivers/phy/phy-qcom-ufs-qmp-14nm.h +++ b/drivers/phy/phy-qcom-ufs-qmp-14nm.h @@ -88,6 +88,7 @@ #define UFS_PHY_POWER_DOWN_CONTROL PHY_OFF(0x04) #define UFS_PHY_TX_LARGE_AMP_DRV_LVL PHY_OFF(0x34) #define UFS_PHY_TX_SMALL_AMP_DRV_LVL PHY_OFF(0x3C) +#define UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP PHY_OFF(0xCC) #define UFS_PHY_LINECFG_DISABLE PHY_OFF(0x138) #define UFS_PHY_RX_SIGDET_CTRL2 PHY_OFF(0x148) #define UFS_PHY_RX_PWM_GEAR_BAND PHY_OFF(0x154) @@ -202,6 +203,7 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_2_0_0[] = { UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6c), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x12), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x06), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), /* * UFS_PHY_RX_PWM_GEAR_BAND configuration is changed after the power up @@ -293,6 +295,7 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_2_1_0[] = { UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6c), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x12), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x06), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), }; static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_2_2_0[] = { @@ -373,6 +376,7 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_2_2_0[] = { UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6c), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0A), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02), + UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), }; static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = { |