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authorPuja Gupta <pujag@codeaurora.org>2016-02-26 13:43:42 -0800
committerDavid Keitel <dkeitel@codeaurora.org>2016-03-22 11:16:24 -0700
commit89ad80b38e2beaaf4c24c31ad86256aecc8b2a15 (patch)
tree7bd9e204a91d88e9a033d914dc1765f56a1f9b62
parent66573349f8f5226da250fcd98f5c88e36f9fd623 (diff)
ARM: dts: msm: Move SPSS device specific info for MSMCOBALT.
Move SCSR register offsets and bit positions specific to SPSS from driver to device tree entry. CRs-Fixed: 972423 Change-Id: I9712cc550b858af54c90ae92c8636e1d37b3f993 Signed-off-by: Puja Gupta <pujag@codeaurora.org>
-rw-r--r--arch/arm64/boot/dts/qcom/msmcobalt.dtsi9
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/qcom/msmcobalt.dtsi b/arch/arm64/boot/dts/qcom/msmcobalt.dtsi
index 0b5ac8858b6c..b341981b67a5 100644
--- a/arch/arm64/boot/dts/qcom/msmcobalt.dtsi
+++ b/arch/arm64/boot/dts/qcom/msmcobalt.dtsi
@@ -1389,8 +1389,12 @@
qcom,spss@1d00000 {
compatible = "qcom,pil-tz-generic";
- reg = <0x1d00000 0x20000>;
- reg-names = "sp_scsr_base";
+ reg = <0x1d0101c 0x4>,
+ <0x1d01024 0x4>,
+ <0x1d01028 0x4>,
+ <0x1d0103c 0x4>;
+ reg-names = "sp2soc_irq_status", "sp2soc_irq_clr",
+ "sp2soc_irq_mask","rmb_err";
interrupts = <0 352 1>;
vdd_cx-supply = <&pmcobalt_s1_level>;
@@ -1406,6 +1410,7 @@
qcom,proxy-timeout-ms = <10000>;
qcom,firmware-name = "spss";
memory-region = <&peripheral_mem>;
+ qcom,spss-scsr-bits = <0 1 2 3 16 17 24 25>;
};
qcom,msm-rtb {