diff options
| author | Avaneesh Kumar Dwivedi <akdwived@codeaurora.org> | 2016-02-16 19:54:51 +0530 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-22 11:16:22 -0700 |
| commit | 66573349f8f5226da250fcd98f5c88e36f9fd623 (patch) | |
| tree | e4f097dda298566cb640e488a349947acae6c5c5 | |
| parent | 92bec5f61b9310140840bf6ff2e50ffbf83a6874 (diff) | |
soc: qcom: pil-q6v5: Read the written value back in reset sequence
Read back value of QDSP6SS_MEM_PWR_CTL after writing, to comply with
reset sequence specification.
Change-Id: Ib803656355c4d498c83fe5cd017823afc5db2c60
Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org>
| -rw-r--r-- | drivers/soc/qcom/pil-q6v5.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/soc/qcom/pil-q6v5.c b/drivers/soc/qcom/pil-q6v5.c index a62091b0854d..05540e407120 100644 --- a/drivers/soc/qcom/pil-q6v5.c +++ b/drivers/soc/qcom/pil-q6v5.c @@ -443,6 +443,8 @@ static int __pil_q6v55_reset(struct pil_desc *pil) val |= BIT(i); writel_relaxed(val, drv->reg_base + QDSP6SS_MEM_PWR_CTL); + val |= readl_relaxed(drv->reg_base + + QDSP6SS_MEM_PWR_CTL); /* * Wait for 1us for both memory peripheral and * data array to turn on. |
