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| author | Raghuram Subramani <raghus2247@gmail.com> | 2022-06-19 19:47:51 +0530 |
|---|---|---|
| committer | Raghuram Subramani <raghus2247@gmail.com> | 2022-06-19 19:47:51 +0530 |
| commit | 4fd287655a72b9aea14cdac715ad5b90ed082ed2 (patch) | |
| tree | 65d393bc0e699dd12d05b29ba568e04cea666207 /circuitpython/lib/tinyusb/hw/bsp/lpcxpresso1347/board.mk | |
| parent | 0150f70ce9c39e9e6dd878766c0620c85e47bed0 (diff) | |
add circuitpython code
Diffstat (limited to 'circuitpython/lib/tinyusb/hw/bsp/lpcxpresso1347/board.mk')
| -rw-r--r-- | circuitpython/lib/tinyusb/hw/bsp/lpcxpresso1347/board.mk | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/circuitpython/lib/tinyusb/hw/bsp/lpcxpresso1347/board.mk b/circuitpython/lib/tinyusb/hw/bsp/lpcxpresso1347/board.mk new file mode 100644 index 0000000..62135c2 --- /dev/null +++ b/circuitpython/lib/tinyusb/hw/bsp/lpcxpresso1347/board.mk @@ -0,0 +1,45 @@ +DEPS_SUBMODULES += hw/mcu/nxp/lpcopen + +CFLAGS += \ + -flto \ + -mthumb \ + -mabi=aapcs \ + -mcpu=cortex-m3 \ + -nostdlib \ + -DCORE_M3 \ + -D__USE_LPCOPEN \ + -DCFG_EXAMPLE_MSC_READONLY \ + -DCFG_EXAMPLE_VIDEO_READONLY \ + -DCFG_TUSB_MCU=OPT_MCU_LPC13XX \ + -DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \ + -DCFG_TUSB_MEM_ALIGN='__attribute__((aligned(64)))' + +# startup.c and lpc_types.h cause following errors +CFLAGS += -Wno-error=strict-prototypes + +MCU_DIR = hw/mcu/nxp/lpcopen/lpc13xx/lpc_chip_13xx + +# All source paths should be relative to the top level. +LD_FILE = hw/bsp/$(BOARD)/lpc1347.ld + +SRC_C += \ + src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \ + $(MCU_DIR)/../gcc/cr_startup_lpc13xx.c \ + $(MCU_DIR)/src/chip_13xx.c \ + $(MCU_DIR)/src/clock_13xx.c \ + $(MCU_DIR)/src/gpio_13xx_1.c \ + $(MCU_DIR)/src/iocon_13xx.c \ + $(MCU_DIR)/src/sysctl_13xx.c \ + $(MCU_DIR)/src/sysinit_13xx.c + +INC += \ + $(TOP)/$(MCU_DIR)/inc + +# For freeRTOS port source +FREERTOS_PORT = ARM_CM3 + +# For flash-jlink target +JLINK_DEVICE = LPC1347 + +# flash using jlink +flash: flash-jlink |