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* phy: qcom-ufs-qmp-v3: add ops to dump phy regsVenkat Gopalakrishnan2016-09-12
| | | | | | | | | It's useful to dump phy registers on failure to debug link issues. Export a new ops for the ufs driver to invoke during link failures. Change-Id: Id3a9c9085375b783d97e7f2ffd3e11ec469aedb9 Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* phy: qcom-ufs: add svs2 supportVenkat Gopalakrishnan2016-06-08
| | | | | | | | | | | | phy-qcom-ufs-qmp-v3 supports SVS2 voltage scaling mode that allows lowest power consumption in HS G1. The PHY must be put in hibern8 state before configuring the PHY to enter SVS2 mode. The voltage can be reduced after this to SVS2 level. This change exposes an API that allows the UFS driver to configure the PHY to enter SVS2 mode. Change-Id: I2ef01d98603840289c436e14bf3df54a2ab9198b Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* ufs: qcom: add dts property to disable LPM modesGilad Broner2016-03-23
| | | | | | | | | | | | | | | Since msmcobalt RUMI uses QRBTC-V2 UFS PHY, there are a few limitations that must be applied in order to be able to initialize UFS: 1. UFS should remain in PWM-G1 1-Lane and never change its gear, as other gears are not stable 2. hibern8 enter/exit should be bypassed 3. we should avoid any power change (as in runtime suspend/resume) Add "qcom,disable-lpm" property to facilitate disabling of these. Change-Id: I3f1801da1e2bf1ce8ce98f5ab08211683106ae8c Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
* scsi/phy: Remove orphaned files after renamingVenkat Gopalakrishnan2016-03-22
| | | | | | | | Delete renamed orphan files after rebasing 3.18 ufs driver changes onto 4.4 ufs driver. Change-Id: Id241ad01bbb0fa74e209c66f8a2d97c05088e33b Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* scsi: ufs: minimize exposure of ufs header filesYaniv Gardi2016-03-22
| | | | | | | | | | | | | | | | | | | | Until now, the phy-qcom-ufs-*.* files used ufs data structures and macros and thus, we had to expose most of them in include/linux/scsi/ufs path. But now, after removing support for phy 28nm in apq8084 under kernel 3.14, we can minimize the exposure of code to essential minimum. To do that, we relocate the ufs.h, unipro.h, ufshcd.h and ufs-qcom.h files back to reside internally in the driver. Also this patch contains some very minor changes suggested by the upstream checkpatch script. Change-Id: Id2a923a6a0b1c76565c25f2797a666f3a0d1315f Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> [subhashj@codeaurora.org: resolved merge conflicts] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org> [venkatg@codeaurora.org: fixed header includes and other trivial merge conflicts] Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* phy: ufs-qcom: disable RX LineCfgSubhash Jadavani2016-03-22
| | | | | | | | | | | | | | Some UFS devices send incorrect LineCfg data as part of power mode change sequence which may cause host PHY to go into bad state. Currently we workaround this issue by disabling the device's TX LCC but disabling TX LCC is much more complicated if both host and device supports UniPro 1.6 specification. To simplify the workaround, this change disables the host PHY's RX LineCfg to skip processing incorrect LineCfg from device. Change-Id: I1eac56c11dd001eb0c53ba8e16aa512a656ab9ea Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org> [venkatg@codeaurora.org: resolved trivial merge conflicts] Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* scsi: ufs-qcom: remove support for save/restore phy configurationYaniv Gardi2016-03-22
| | | | | | | | | | | | | | Since support for 28nm phy removed in kernel 3.14, all related code that is specific to phy 28nm is also removed. Specifically the quirk that enables save/restore phy configuration is removed (and all its relevant callbacks) as it's unique to 28nm ufs phy. Change-Id: Ie723885bacb52548573fc1140d09b0ea5f067382 Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> [venkatg@codeaurora.org: drop changes to include/linux/phy/phy-qcom-ufs.h] Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* scsi: ufs: remove unwanted checks from hibern8 sequenceSubhash Jadavani2016-03-22
| | | | | | | | | | | | | We are unnecessarily checking for the request/task doorbell status during hibern8 enter/exit path but it's very important to have the minimal latencies for hibern8 enter/exit in order to achieve agressive power management strategies for UFS. So these unecessary checks are moved out of this hot path. Change-Id: Ibaeddca7bd516d71eb03b02a1fc1a86f05038f08 Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org> [venkatg@codeaurora.org: resolved trivial merge conflicts] Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* phy: relocate and rename phy ufs filesYaniv Gardi2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | This change contains: 1. Relocating the phy ufs files to reside under the phy driver since this is the location of any file that implements the APIs presented in the generic phy framework 2. Renaming ufs-msm-phy*.* files to be phy-qcom-ufs*.* files. Since UFS is not used strictly in a specific set of targets but rather its code is applicable to MSM, APQ, IPQ etc, any mentioning of "msm" in the file name should be changed to "qcom". Also, prefix of "phy-" is the naming convention of platform driver files that reside in the phy driver. 3. As a result of the relocation of files into the phy driver, a new path is created (include/linux/scsi/ufs) and there we expose ufs header files that are being used also from the drivers/scsi/ufs and from drivers/phy as well. Change-Id: Ie5cb47718911ff711d9401a389f56fa508fcddf3 Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> [gbroner@codeaurora.org: fix merge conflicts] Signed-off-by: Gilad Broner <gbroner@codeaurora.org> [venkatg@codeaurora.org: resolved merge conflicts by keeping upstream version] Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* Merge tag 'phy-for-v4.2' of ↵Greg Kroah-Hartman2015-06-03
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next Kishon writes: phy: for 4.2 merge window *) new Broadcom SATA3 PHY driver for Broadcom STB SoCs *) new phy API to get PHY by index which is used in EHCI and OHCI controller drivers *) support specifying supply at port level used for multi-port PHYs *) sparse warning fixes in miphy PHYs *) fix pm_runtime issues in twl4030 driver Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| * phy: core: Add devm_of_phy_get_by_index to phy-coreArun Ramamurthy2015-05-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some generic drivers, such as ehci, may use multiple phys and for such drivers referencing phy(s) by name(s) does not make sense. Instead of inventing new naming schemes and using custom code to iterate through them, such drivers are better of using nameless phy bindings and using this newly introduced API to iterate through them. Signed-off-by: Arun Ramamurthy <arun.ramamurthy@broadcom.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> [kishon@ti.com: fix compilation errors] Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* | phy: sun4i-usb: Add a sunxi specific function for setting squelch-detectHans de Goede2015-05-27
|/ | | | | | | | | | | | | The sunxi otg phy has a bug where it wrongly detects a high speed squelch when reset on the root port gets de-asserted with a lo-speed device. The workaround for this is to disable squelch detect before de-asserting reset, and re-enabling it after the reset de-assert is done. Add a sunxi specific phy function to allow the sunxi-musb glue to do this. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsiLinus Torvalds2015-02-11
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull first round of SCSI updates from James Bottomley: "This is the usual grab bag of driver updates (hpsa, storvsc, mp2sas, megaraid_sas, ses) plus an assortment of minor updates. There's also an update to ufs which adds new phy drivers and finally a new logging infrastructure for SCSI" * tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi: (114 commits) scsi_logging: return void for dev_printk() functions scsi: print single-character strings with seq_putc scsi: merge consecutive seq_puts calls scsi: replace seq_printf with seq_puts aha152x: replace seq_printf with seq_puts advansys: replace seq_printf with seq_puts scsi: remove SPRINTF macro sg: remove an unused variable hpsa: Use local workqueues instead of system workqueues hpsa: add in P840ar controller model name hpsa: add in gen9 controller model names hpsa: detect and report failures changing controller transport modes hpsa: shorten the wait for the CISS doorbell mode change ack hpsa: refactor duplicated scan completion code into a new routine hpsa: move SG descriptor set-up out of hpsa_scatter_gather() hpsa: do not use function pointers in fast path command submission hpsa: print CDBs instead of kernel virtual addresses for uncommon errors hpsa: do not use a void pointer for scsi_cmd field of struct CommandList hpsa: return failed from device reset/abort handlers hpsa: check for ctlr lockup after command allocation in main io path ...
| * phy: qcom-ufs: add support for 20nm phyYaniv Gardi2015-01-20
| | | | | | | | | | | | | | | | | | This change adds a support for a 20nm qcom-ufs phy that is required in platforms that use ufs-qcom controller. Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> Reviewed-by: Dov Levenglick <dovl@codeaurora.org> Signed-off-by: Christoph Hellwig <hch@lst.de>
* | phy: phy-ti-pipe3: fix inconsistent enumeration of PCIe gen2 cardsVignesh R2014-12-23
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to DRA74x silicon rev 1.1, pcie_pcs register bits 8-15 and bits 16-23 were used to configure RC delay count for phy1 and phy2 respectively. phyid was used as index to distinguish the phys and to configure the delay values appropriately. As of DRA74x silicon rev 1.1, pcie_pcs register definition has changed. Bits 16-23 are used to configure delay values for *both* phy1 and phy2. Hence phyid is no longer required. So, drop id field from ti_pipe3 structure and its subsequent references for configuring pcie_pcs register. Also, pcie_pcs register now needs to be configured with delay value of 0x96 at bit positions 16-23. See register description of CTRL_CORE_PCIE_PCS in ARM572x TRM, SPRUHZ6, October 2014, section 18.5.2.2, table 18-1804. This is needed to ensure Gen2 cards are enumerated consistently. DRA72x silicon behaves same way as DRA74x rev 1.1 as far as this functionality is considered. Test results on DRA74x and DRA72x EVMs: Before patch ------------ DRA74x ES 1.0: Gen1 cards work, Gen2 cards do not work (expected result due to silicon errata) DRA74x ES 1.1: Gen1 cards work, Gen2 cards do not work sometimes due to incorrect programming of register DRA72x: Gen1 cards work, Gen2 cards do not work sometimes due to incorrect programming of register After patch ----------- DRA74x ES 1.0: Gen1 cards work, Gen2 cards do not work (expected result due to silicon errata) DRA74x ES 1.1: Gen1 cards work, Gen2 cards work consistently. DRA72x: Gen1 and Gen2 cards enumerate consistently. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: remove the old lookup methodHeikki Krogerus2014-11-22
| | | | | | | | | The users of the old method are now converted to the new one. Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> [ kishon@ti.com : made phy-berlin-usb.c and phy-miphy28lp.c to use the updated devm_phy_create API.] Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: improved lookup methodHeikki Krogerus2014-11-21
| | | | | | | | Separates registration of the phy and the lookup. The method is copied from clkdev.c, Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: safer to_phy() macroHeikki Krogerus2014-11-21
| | | | | | | | | | This makes to_phy() macro work with other variable names besides "dev". Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Tested-by: Vivek Gautam <gautam.vivek@samsung.com> Acked-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: core: Let node ptr of PHY point to PHY and not of PHY providerKishon Vijay Abraham I2014-07-22
| | | | | | | | | | | In case of multi-phy PHY providers, each PHY should be modeled as a sub node of the PHY provider. Then each PHY will have a different node pointer (node pointer of sub node) than that of PHY provider. Added this provision in the PHY core. Also fixed all drivers to use the updated API. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Lee Jones <lee.jones@linaro.org>
* phy: core: Support regulator supply for PHY powerRoger Quadros2014-07-22
| | | | | | | | | Some PHYs can be powered by an external power regulator. e.g. USB_HS PHY on DRA7 SoC. Make the PHY core support a power regulator. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: pipe3: insert delay to enumerate in GEN2 modeKishon Vijay Abraham I2014-07-22
| | | | | | | | | 8-bit delay value (0xF1) is required for GEN2 devices to be enumerated consistently. Added an API to be called from PHY drivers to set this delay value and called it from PIPE3 driver to set the delay value. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Roger Quadros <rogerq@ti.com>
* phy: core: make NULL a valid phy reference if !CONFIG_GENERIC_PHYGrygorii Strashko2014-04-24
| | | | | | | | | | | | | | | | | | | | | | | | This fixes a regression on Keystone 2 platforms caused by patch 57303488cd37da58263e842de134dc65f7c626d5 "usb: dwc3: adapt dwc3 core to use Generic PHY Framework" which adds optional support of generic phy in DWC3 core. On Keystone 2 platforms the USB is not working now because CONFIG_GENERIC_PHY isn't set and, as result, Generic PHY APIs stubs return -ENOSYS always. The log shows: dwc3 2690000.dwc3: failed to initialize core dwc3: probe of 2690000.dwc3 failed with error -38 Hence, fix it by making NULL a valid phy reference in Generic PHY APIs stubs in the same way as it was done by the patch 04c2facad8fee66c981a51852806d8923336f362 "drivers: phy: Make NULL a valid phy reference". Acked-by: Felipe Balbi <balbi@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* phy: rename struct omap_control_usb to struct omap_control_phyKishon Vijay Abraham I2014-03-09
| | | | | | | | | | | Rename struct omap_control_usb to struct omap_control_phy since it can be used to control PHY of USB, SATA and PCIE. Also move the driver and include files under *phy* and made the corresponding changes in the users of phy-omap-control. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Felipe Balbi <balbi@ti.com>
* phy: omap-usb2: Provide workaround for USB2PHY false disconnectAustin Beam2014-03-09
| | | | | | | | | | | | | | | | | Enable the dra7x errata workaround for false disconnect problem with USB2PHY. False disconnects were detected with some of the devices. Reduce the sensitivity of the disconnect logic within the USB2PHY subsystem to enusre these false disconnects are not registered. [george.cherian@ti.com] While at that, pass proper flags for each SoC's. This is a common driver used across OMAP4,OMAP5,DRA7xx and AM437x USB2PHY. False disconnect workaround is currently applicable for only DRA7x. Signed-off-by: Austin Beam <austinbeam@ti.com> Signed-off-by: George Cherian <george.cherian@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: omap-usb2: Adapt phy-omap-usb2 for AM437xGeorge Cherian2014-03-09
| | | | | | | | | | Adapt phy-omap-usb2 driver for AM437x. - Add new comaptible "ti,am437x-usb2" for AM437x - Pass proper data to differentiate AM437x and others. - AM437x doesnot support set_vbus and start_srp. Signed-off-by: George Cherian <george.cherian@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: core: Add devm_of_phy_get to phy-coreKamil Debski2014-03-08
| | | | | | | | | Adding devm_of_phy_get will allow to get phys by supplying a pointer to the struct device_node instead of struct device. Signed-off-by: Kamil Debski <k.debski@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: core: Add an exported of_phy_get functionKamil Debski2014-03-08
| | | | | | | | | | | | | | Previously the of_phy_get function took a struct device * and was declared static. It was impossible to call it from another driver and thus it was impossible to get phy defined for a given node. The old function was renamed to _of_phy_get and was left for internal use. of_phy_get function was added and it was exported. The function enables to get a phy for a given device tree node. Signed-off-by: Kamil Debski <k.debski@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: omap-usb2: move omap_usb.h from linux/usb/ to linux/phy/Kishon Vijay Abraham I2014-03-07
| | | | | | | | No functional change. Moved omap_usb.h from linux/usb/ to linux/phy/. Also removed the unused members of struct omap_usb (after phy-omap-pipe3 started using it's own header file) Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* drivers: phy: Add support for optional physAndrew Lunn2014-02-05
| | | | | | | | | | | | Add devm_phy_optional_get and phy_optional_get, which should be used when the phy is optional. They does not return an error when the phy does not exist, rather they returns NULL, which is considered as a valid phy, but results in NOPs when used with the consumer API. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* phy: add phy_get_bus_width()/phy_set_bus_width() callsMatt Porter2013-12-23
| | | | | | | | | | | | This adds a pair of APIs that allows the generic PHY subsystem to provide information on the PHY bus width. The PHY provider driver may use phy_set_bus_width() to set the bus width that the PHY supports. The controller driver may then use phy_get_bus_width() to fetch the PHY bus width in order to properly configure the controller. Signed-off-by: Matt Porter <mporter@linaro.org> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* drivers: phy: add generic PHY frameworkKishon Vijay Abraham I2013-09-27
The PHY framework provides a set of APIs for the PHY drivers to create/destroy a PHY and APIs for the PHY users to obtain a reference to the PHY with or without using phandle. For dt-boot, the PHY drivers should also register *PHY provider* with the framework. PHY drivers should create the PHY by passing id and ops like init, exit, power_on and power_off. This framework is also pm runtime enabled. The documentation for the generic PHY framework is added in Documentation/phy.txt and the documentation for dt binding can be found at Documentation/devicetree/bindings/phy/phy-bindings.txt Cc: Tomasz Figa <t.figa@samsung.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Felipe Balbi <balbi@ti.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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