| Commit message (Collapse) | Author | Age |
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Currently, separate submissions are made for page table
switch and context switch to the ring buffer. However, if the
page table switch succeeds but the context switch fails,
it can lead to use of wrong page table for drawctxt.
To address this issue, rollback the pagetable to current pagetable.
Also,correctly put the refcount of adreno context during error
cleanup.
Change-Id: I1bb4ee3ebb0ce6ea32f0b6799cfb7fa89c0d09c7
Signed-off-by: Rakesh Naidu Bhaviripudi <quic_rakeshb@quicinc.com>
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Check MMU type for below operations to make NOMMU functional:
- adreno_iommu_set_pt_ctx() tries to set pagetable during context
switch without really checking on type of MMU.
- skip tracking of gpuaddr in case of NoMMU during
kgsl_mem_entry_track_gpuaddr().
- In case of nommu the function kgsl_allocate_global() should
always allocate contiguous memory from CMA.
Change-Id: I8cb59e1475376167c7a8a60c54df0939597f5083
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
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Force any command triggered context switch to the GPU - it should
be on the GPU anyway, but we were already passing a flags parameter
(unused) so this is a good chance to force the issue and make sure
that the cpu path decision isn't in play here.
CRs-Fixed: 1009124
Change-Id: Ic0dedbadb277a6498d0840b45c90e1265e2f354a
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Allow 5XX targets to preempt quickly from an atomic context. In
particular this allows quicker transition from a high priority
ringbuffer to a lower one without having to wait for the worker
to schedule.
CRs-Fixed: 1009124
Change-Id: Ic0dedbad01a31a5da2954b097cb6fa937d45ef5c
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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It is no longer power efficient to independently enable and disable
the MMU clocks. We can safely enable and disable them with the rest
of the GPU clocks and take back the infrastructure needed to handle
the clocks.
CRs-Fixed: 1009124
Change-Id: Ic0dedbadc48095eada9c5fce6004475a2cb0f0a9
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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The memstore shared between the CPU and GPU is old but can not be
messed with. Rather than stealing values from it where available,
add a new block of shared memory that is exclusive to the driver
and GPU. This block can be used more freely than the old
memstore block.
Program the GPU to write the RPTR out to an address the CPU can read rather
than having the CPU read a GPU register directly. There are some very
small but very real conditions where different blocks on the GPU have
outdated values for the RPTR. When scheduling preemption the value read
from the register could not reflect the actual value of the RPTR in the CP.
This can cause the save/restore from preemption to give back incorrect RPTR
values causing much confusion between the GPU and CPU.
Remove the ringbuffers copy of the read pointer shadow.
Now that the GPU will update a shared memory address with the
value of the read pointer, there is no need to poll the register
to get the value and then keep a local copy of it.
CRs-Fixed: 987082
Change-Id: Ic44759d1a5c6e48b2f0f566ea8c153f01cf68279
Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Disable the guardpage workaround for A5x and instead
selectively suppress pagefaults. Suppress read pagefaults
that are likely caused due to UCHE overfetches. For this,
the fault address must be within the first 64 bytes of a
page and the fault page must be preceded by a valid allocation.
CRs-Fixed: 975293
Change-Id: I6a0995af3ab4129c6923726043c5f34c747641f9
Signed-off-by: Sushmita Susheelendra <ssusheel@codeaurora.org>
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The current MMU code assumes a binary state - either there is a
IOMMU or there isn't. This precludes other memory models and
makes for a lot of inherent IOMMU knowledge in the generic MMU
code and the rest of the driver. Reorganize and cleanup the
MMU and IOMMU code:
* Add a Kconfig boolean dependent on ARM and/or MSM SMMU support.
* Make "nommu" mode an actual MMU subtype and figure out available
MMU subtypes at probe time.
* Move IOMMU device tree parsing to the IOMMU code.
* Move the MMU subtype private structures into struct kgsl_mmu.
* Move adreno_iommu specific functions out of other generic
adreno code.
* Move A4XX specific preemption code out of the ringbuffer code.
CRs-Fixed: 970264
Change-Id: Ic0dedbad1293a1d129b7c4ed1105d684ca84d97f
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Add a helper macro to convert an adreno_device pointer to a
struct kgsl_device pointer. This is mostly syntatic sugar
but it makes the code a bit cleaner and it abstracts a bit of
the ugliness away.
Change-Id: Ic0dedbadd97bda3316a58514a5a64757bd4154c7
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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The ringbuffer structures are static members of struct adreno_device
which means that they are permanently associated with a specific
adreno device and by extension a struct kgsl_device too. The upshot
is that we can use macro math to derive the adreno device from
a ringbuffer pointer and get rid of the device shortcut in the
ringbuffer struct. This also gives us a chance to clean up
how functions use the ringbuffer and adreno_device structs
to limit unnessesary dereferencing.
Change-Id: Ic0dedbad909ef71e99cd3319713cee38fb1700f0
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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The setstate memory is a IOMMU specific construct. Move it to the
IOMMU code where it belongs.
Change-Id: Ic0dedbada977f2861f7c1300a5365da5b09d70a9
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Make sure the allocated memory is freed before returning.
Change-Id: I6da7d1ffbd83ad206970e38ac99f9da211ffe86c
Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
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Snapshot of the Qualcom Adreno GPU driver (KGSL) as of msm-3.18 commit
commit e70ad0cd5efd ("Promotion of kernel.lnx.3.18-151201.").
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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