Merge tag 'for-linus-20141015' of git://git.infradead.org/linux-mtd

Pull MTD update from Brian Norris:
 "Sorry for delaying this a bit later than usual.  There's one mild
  regression from 3.16 that was noticed during the 3.17 cycle, and I
  meant to send a fix for it along with this pull request.  I'll
  probably try to queue it up for a later pull request once I've had a
  better look at it, hopefully by -rc2 at the latest.

  Summary for this pull:

  NAND
   - Cleanup for Denali driver
   - Atmel: add support for new page sizes
   - Atmel: fix up 'raw' mode support
   - Atmel: miscellaneous cleanups
   - New timing mode helpers for non-ONFI NAND
   - OMAP: allow driver to be (properly) built as a module
   - bcm47xx: RESET support and other cleanups

  SPI NOR
   - Miscellaneous cleanups, to prepare framework for wider use (some
     further work still pending)
   - Compile-time configuration to select 4K vs.  64K support for flash
     that support both (necessary for using UBIFS on some SPI NOR)

  A few scattered code quality fixes, detected by Coverity

  See the changesets for more"

* tag 'for-linus-20141015' of git://git.infradead.org/linux-mtd: (59 commits)
  mtd: nand: omap: Correct CONFIG_MTD_NAND_OMAP_BCH help message
  mtd: nand: Force omap_elm to be built as a module if omap2_nand is a module
  mtd: move support for struct flash_platform_data into m25p80
  mtd: spi-nor: add Kconfig option to disable 4K sectors
  mtd: nand: Move ELM driver and rename as omap_elm
  nand: omap2: Replace pr_err with dev_err
  nand: omap2: Remove horrible ifdefs to fix module probe
  mtd: nand: add Hynix's H27UCG8T2ATR-BC to nand_ids table
  mtd: nand: support ONFI timing mode retrieval for non-ONFI NANDs
  mtd: physmap_of: Add non-obsolete map_rom probe
  mtd: physmap_of: Fix ROM support via OF
  MAINTAINERS: add l2-mtd.git, 'next' tree for MTD
  mtd: denali: fix indents and other trivial things
  mtd: denali: remove unnecessary parentheses
  mtd: denali: remove another set-but-unused variable
  mtd: denali: fix include guard and license block of denali.h
  mtd: nand: don't break long print messages
  mtd: bcm47xxnflash: replace some magic numbers
  mtd: bcm47xxnflash: NAND_CMD_RESET support
  mtd: bcm47xxnflash: add cmd_ctrl handler
  ...

1 files changed, 12 insertions, 0 deletions

diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index c300db3ae285..e4d451e4600b 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -587,6 +587,11 @@ struct nand_buffers {
  * @ecc_step_ds:	[INTERN] ECC step required by the @ecc_strength_ds,
  *                      also from the datasheet. It is the recommended ECC step
  *			size, if known; if unknown, set to zero.
+ * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
+ *			      either deduced from the datasheet if the NAND
+ *			      chip is not ONFI compliant or set to 0 if it is
+ *			      (an ONFI chip is always configured in mode 0
+ *			      after a NAND reset)
  * @numchips:		[INTERN] number of physical chips
  * @chipsize:		[INTERN] the size of one chip for multichip arrays
  * @pagemask:		[INTERN] page number mask = number of (pages / chip) - 1
@@ -671,6 +676,7 @@ struct nand_chip {
 	uint8_t bits_per_cell;
 	uint16_t ecc_strength_ds;
 	uint16_t ecc_step_ds;
+	int onfi_timing_mode_default;
 	int badblockpos;
 	int badblockbits;
 
@@ -766,12 +772,17 @@ struct nand_chip {
  * @options: stores various chip bit options
  * @id_len: The valid length of the @id.
  * @oobsize: OOB size
+ * @ecc: ECC correctability and step information from the datasheet.
  * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
  *                   @ecc_strength_ds in nand_chip{}.
  * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
  *               @ecc_step_ds in nand_chip{}, also from the datasheet.
  *               For example, the "4bit ECC for each 512Byte" can be set with
  *               NAND_ECC_INFO(4, 512).
+ * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
+ *			      reset. Should be deduced from timings described
+ *			      in the datasheet.
+ *
  */
 struct nand_flash_dev {
 	char *name;
@@ -792,6 +803,7 @@ struct nand_flash_dev {
 		uint16_t strength_ds;
 		uint16_t step_ds;
 	} ecc;
+	int onfi_timing_mode_default;
 };
 
 /**