diff options
| author | Clarence Ip <cip@codeaurora.org> | 2016-02-24 10:57:34 -0500 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 20:33:27 -0700 |
| commit | eb5019c32c9083f8c23f84b6384c62b45b2ec71f (patch) | |
| tree | 747c31c7e091649736303be69e6753d949788586 /drivers/video/fbdev/msm/mdss_util.c | |
| parent | 29e5a92bb220354b6875071b980b65e40b9b520a (diff) | |
msm: mdss: Add support for separate irq line for DSI 6G
In ferrum DSI has an irq line which is different from mdp.
Add support for irq handling this case. It makes use of
utility functions provided by mdss.
Change-Id: Ia6dca1050957f4755b7547f4c1a08ace913c2ac7
Signed-off-by: Shivaraj Shetty <shivaraj@codeaurora.org>
[cip@codeaurora.org: Resolved merge conflict,
removed IRQF_DISABLED flag]
Signed-off-by: Clarence Ip <cip@codeaurora.org>
Diffstat (limited to 'drivers/video/fbdev/msm/mdss_util.c')
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_util.c | 46 |
1 files changed, 21 insertions, 25 deletions
diff --git a/drivers/video/fbdev/msm/mdss_util.c b/drivers/video/fbdev/msm/mdss_util.c index f09bbd0da87b..1c86516a894b 100644 --- a/drivers/video/fbdev/msm/mdss_util.c +++ b/drivers/video/fbdev/msm/mdss_util.c @@ -56,17 +56,17 @@ void mdss_enable_irq(struct mdss_hw *hw) ndx_bit = BIT(hw->hw_ndx); pr_debug("Enable HW=%d irq ena=%d mask=%x\n", hw->hw_ndx, - mdss_res->irq_ena, mdss_res->irq_mask); + hw->irq_info->irq_ena, hw->irq_info->irq_mask); spin_lock_irqsave(&mdss_lock, irq_flags); - if (mdss_res->irq_mask & ndx_bit) { + if (hw->irq_info->irq_mask & ndx_bit) { pr_debug("MDSS HW ndx=%d is already set, mask=%x\n", - hw->hw_ndx, mdss_res->irq_mask); + hw->hw_ndx, hw->irq_info->irq_mask); } else { - mdss_res->irq_mask |= ndx_bit; - if (!mdss_res->irq_ena) { - mdss_res->irq_ena = true; - enable_irq(mdss_res->irq); + hw->irq_info->irq_mask |= ndx_bit; + if (!hw->irq_info->irq_ena) { + hw->irq_info->irq_ena = true; + enable_irq(hw->irq_info->irq); } } spin_unlock_irqrestore(&mdss_lock, irq_flags); @@ -83,18 +83,16 @@ void mdss_disable_irq(struct mdss_hw *hw) ndx_bit = BIT(hw->hw_ndx); pr_debug("Disable HW=%d irq ena=%d mask=%x\n", hw->hw_ndx, - mdss_res->irq_ena, mdss_res->irq_mask); + hw->irq_info->irq_ena, hw->irq_info->irq_mask); spin_lock_irqsave(&mdss_lock, irq_flags); - if (!(mdss_res->irq_mask & ndx_bit)) { - pr_warn("MDSS HW ndx=%d is NOT set, mask=%x, hist mask=%x\n", - hw->hw_ndx, mdss_res->mdp_irq_mask, - mdss_res->mdp_hist_irq_mask); + if (!(hw->irq_info->irq_mask & ndx_bit)) { + pr_warn("MDSS HW ndx=%d is NOT set\n", hw->hw_ndx); } else { - mdss_res->irq_mask &= ~ndx_bit; - if (mdss_res->irq_mask == 0) { - mdss_res->irq_ena = false; - disable_irq_nosync(mdss_res->irq); + hw->irq_info->irq_mask &= ~ndx_bit; + if (hw->irq_info->irq_mask == 0) { + hw->irq_info->irq_ena = false; + disable_irq_nosync(hw->irq_info->irq); } } spin_unlock_irqrestore(&mdss_lock, irq_flags); @@ -111,18 +109,16 @@ void mdss_disable_irq_nosync(struct mdss_hw *hw) ndx_bit = BIT(hw->hw_ndx); pr_debug("Disable HW=%d irq ena=%d mask=%x\n", hw->hw_ndx, - mdss_res->irq_ena, mdss_res->irq_mask); + hw->irq_info->irq_ena, hw->irq_info->irq_mask); spin_lock(&mdss_lock); - if (!(mdss_res->irq_mask & ndx_bit)) { - pr_warn("MDSS HW ndx=%d is NOT set, mask=%x, hist mask=%x\n", - hw->hw_ndx, mdss_res->mdp_irq_mask, - mdss_res->mdp_hist_irq_mask); + if (!(hw->irq_info->irq_mask & ndx_bit)) { + pr_warn("MDSS HW ndx=%d is NOT set\n", hw->hw_ndx); } else { - mdss_res->irq_mask &= ~ndx_bit; - if (mdss_res->irq_mask == 0) { - mdss_res->irq_ena = false; - disable_irq_nosync(mdss_res->irq); + hw->irq_info->irq_mask &= ~ndx_bit; + if (hw->irq_info->irq_mask == 0) { + hw->irq_info->irq_ena = false; + disable_irq_nosync(hw->irq_info->irq); } } spin_unlock(&mdss_lock); |