diff options
| author | Tatenda Chipeperekwa <tatendac@codeaurora.org> | 2014-07-29 16:41:57 -0400 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 21:20:57 -0700 |
| commit | 7833d2e68db90a275475c7f417d07313d3dedd0e (patch) | |
| tree | ac2172fcc1d489d731d00c043b5c736c3888234f /drivers/video/fbdev/msm/mdss_util.c | |
| parent | 87f34e2e551b28400eb6f337bc485bd9b34700e6 (diff) | |
msm: mdss: hdmi: add support for CEC suspend and resume events
Add support for CEC commands to suspend and resume the device.
The HDMI core must be kept on when the CEC wakeup feature is
enabled and the device is going into suspend state. Furthermore,
interrupts must be enabled in this state to capture CEC commands.
This allows the device to be resumed later on via CEC wakeup commands.
Change-Id: Ie6fcbc666e4f40335ab8faaa969d4b03aa83e17c
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Diffstat (limited to 'drivers/video/fbdev/msm/mdss_util.c')
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_util.c | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/drivers/video/fbdev/msm/mdss_util.c b/drivers/video/fbdev/msm/mdss_util.c index 3a9ff9b6adb3..db318de6fc6d 100644 --- a/drivers/video/fbdev/msm/mdss_util.c +++ b/drivers/video/fbdev/msm/mdss_util.c @@ -139,10 +139,72 @@ int mdss_irq_dispatch(u32 hw_ndx, int irq, void *ptr) return rc; } +void mdss_enable_irq_wake(struct mdss_hw *hw) +{ + unsigned long irq_flags; + u32 ndx_bit; + + if (hw->hw_ndx >= MDSS_MAX_HW_BLK) + return; + + if (!mdss_irq_handlers[hw->hw_ndx]) { + pr_err("failed. First register the irq then enable it.\n"); + return; + } + + ndx_bit = BIT(hw->hw_ndx); + + pr_debug("Enable HW=%d irq ena=%d mask=%x\n", hw->hw_ndx, + hw->irq_info->irq_wake_ena, + hw->irq_info->irq_wake_mask); + + spin_lock_irqsave(&mdss_lock, irq_flags); + if (hw->irq_info->irq_wake_mask & ndx_bit) { + pr_debug("MDSS HW ndx=%d is already set, mask=%x\n", + hw->hw_ndx, hw->irq_info->irq_wake_mask); + } else { + hw->irq_info->irq_wake_mask |= ndx_bit; + if (!hw->irq_info->irq_wake_ena) { + hw->irq_info->irq_wake_ena = true; + enable_irq_wake(hw->irq_info->irq); + } + } + spin_unlock_irqrestore(&mdss_lock, irq_flags); +} + +void mdss_disable_irq_wake(struct mdss_hw *hw) +{ + unsigned long irq_flags; + u32 ndx_bit; + + if (hw->hw_ndx >= MDSS_MAX_HW_BLK) + return; + + ndx_bit = BIT(hw->hw_ndx); + + pr_debug("Disable HW=%d irq ena=%d mask=%x\n", hw->hw_ndx, + hw->irq_info->irq_wake_ena, + hw->irq_info->irq_wake_mask); + + spin_lock_irqsave(&mdss_lock, irq_flags); + if (!(hw->irq_info->irq_wake_mask & ndx_bit)) { + pr_warn("MDSS HW ndx=%d is NOT set\n", hw->hw_ndx); + } else { + hw->irq_info->irq_wake_mask &= ~ndx_bit; + if (hw->irq_info->irq_wake_ena) { + hw->irq_info->irq_wake_ena = false; + disable_irq_wake(hw->irq_info->irq); + } + } + spin_unlock_irqrestore(&mdss_lock, irq_flags); +} + struct mdss_util_intf mdss_util = { .register_irq = mdss_register_irq, .enable_irq = mdss_enable_irq, .disable_irq = mdss_disable_irq, + .enable_wake_irq = mdss_enable_irq_wake, + .disable_wake_irq = mdss_disable_irq_wake, .disable_irq_nosync = mdss_disable_irq_nosync, .irq_dispatch = mdss_irq_dispatch, .get_iommu_domain = NULL, |