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| author | Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> | 2018-06-20 16:42:58 -0400 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-08-15 17:42:10 +0200 |
| commit | dc48c1a2f45b628d3128ad4bb31d1bcd342c059d (patch) | |
| tree | 070019bdf719a43d97239cea8921ff5c845be1e1 /arch/x86/mm/init.c | |
| parent | df7fd6ccb358bd4aa3abc8a6ff995b1f3da1b0fb (diff) | |
x86/cpufeatures: Add detection of L1D cache flush support.
commit 11e34e64e4103955fc4568750914c75d65ea87ee upstream
336996-Speculative-Execution-Side-Channel-Mitigations.pdf defines a new MSR
(IA32_FLUSH_CMD) which is detected by CPUID.7.EDX[28]=1 bit being set.
This new MSR "gives software a way to invalidate structures with finer
granularity than other architectual methods like WBINVD."
A copy of this document is available at
https://bugzilla.kernel.org/show_bug.cgi?id=199511
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/x86/mm/init.c')
0 files changed, 0 insertions, 0 deletions