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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-08-23 17:48:45 +0100 |
|---|---|---|
| committer | Bruno Martins <bgcngm@gmail.com> | 2022-10-28 15:57:24 +0100 |
| commit | 21bb344a664b9a9eb9dd0dc415af263c4e5b9def (patch) | |
| tree | 42f76d8a29f03b2d39444418715f6935a08d0e27 /arch/arm64/include/asm/assembler.h | |
| parent | 26d5a53c6e0d987bdd75e01d1a35d721c3a5774e (diff) | |
BACKPORT: crypto: arm64/aes-modes - get rid of literal load of addend vector
commit ed6ed11830a9ded520db31a6e2b69b6b0a1eb0e2 upstream.
Replace the literal load of the addend vector with a sequence that
performs each add individually. This sequence is only 2 instructions
longer than the original, and 2% faster on Cortex-A53.
This is an improvement by itself, but also works around a Clang issue,
whose integrated assembler does not implement the GNU ARM asm syntax
completely, and does not support the =literal notation for FP registers
(more info at https://bugs.llvm.org/show_bug.cgi?id=38642)
Cc: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Change-Id: Ic8f7adcd28bd2da57b465a8e11e9d55b5669a539
Diffstat (limited to 'arch/arm64/include/asm/assembler.h')
0 files changed, 0 insertions, 0 deletions