diff options
| author | Tengfei Fan <tengfeif@codeaurora.org> | 2018-11-19 13:45:29 +0800 |
|---|---|---|
| committer | Georg Veichtlbauer <georg@vware.at> | 2023-07-16 12:47:43 +0200 |
| commit | c0b317c27d445025c40d2f3af1a052115e027e5e (patch) | |
| tree | d3f4a249b411ca3c6dc9ededa4062104628ed59a | |
| parent | 45df1516d04a155794e56e6ded1c4813a3e56048 (diff) | |
pinctrl: qcom: Clear status bit on irq_unmask
The gpio interrupt status bit is getting set after the
irq is disabled and causing an immediate interrupt after
enablling the irq, so clear status bit on irq_unmask.
Change-Id: I89245b90b06b37671369e59c15fb24a991cc114a
Signed-off-by: Tengfei Fan <tengfeif@codeaurora.org>
| -rw-r--r-- | drivers/pinctrl/qcom/pinctrl-msm.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index d4a1f5378ac5..ee8c09717597 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -631,6 +631,7 @@ static void msm_gpio_irq_enable(struct irq_data *d) static void msm_gpio_irq_unmask(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + uint32_t irqtype = irqd_get_trigger_type(d); struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); const struct msm_pingroup *g; unsigned long flags; @@ -640,6 +641,12 @@ static void msm_gpio_irq_unmask(struct irq_data *d) spin_lock_irqsave(&pctrl->lock, flags); + if (irqtype & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { + val = readl_relaxed(pctrl->regs + g->intr_status_reg); + val &= ~BIT(g->intr_status_bit); + writel_relaxed(val, pctrl->regs + g->intr_status_reg); + } + val = readl(pctrl->regs + g->intr_status_reg); val &= ~BIT(g->intr_status_bit); writel(val, pctrl->regs + g->intr_status_reg); |