1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
|
MSM USB PHY transceivers
HSUSB PHY
Required properties:
- compatible: Should be "qcom,usb-hsphy"
- reg: Address and length of the register set for the device
Required regs are:
"core" : the QSCRATCH base register set
- <supply-name>-supply: phandle to the regulator device tree node
Required "supply-name" examples are:
"vdd" : vdd supply for HSPHY digital circuit operation
"vdda18" : 1.8v supply for HSPHY
"vdda33" : 3.3v supply for HSPHY
- qcom,vdd-voltage-level: This property must be a list of three integer
values (no, min, max) where each value represents either a voltage in
microvolts or a value corresponding to voltage corner
Optional properties:
- reg: Additional registers
"tcsr" : top-level CSR register to be written during power-on reset
initialize the internal MUX that controls whether this PHY is
used with the USB3 or the USB2 controller.
- qcom,hsphy-init: Init value used to override HSPHY parameters into
QSCRATCH register. This 32-bit value represents parameters as follows:
bits 0-5 PARAMETER_OVERRIDE_A
bits 6-12 PARAMETER_OVERRIDE_B
bits 13-19 PARAMETER_OVERRIDE_C
bits 20-25 PARAMETER_OVERRIDE_D
- qcom,ext-vbus-id: If present, indicates that the PHY does not handle VBUS and ID changes.
- qcom,vbus-valid-override: If present, indicates VBUS pin is not connected to
the USB PHY and the controller must rely on external VBUS notification in
order to manually enable the D+ pull-up resistor.
- qcom,primary-phy: If present, indicates this is a secondary PHY and is
dependent on the primary PHY referenced by this phandle.
- qcom,set-pllbtune: If present, PLL tune is required in PHY initialization.
- qcom,num_ports: Indicates the number of ports that supported by the HS PHY.
If omitted, defaults to 1
- qcom,sleep-clk-reset: If present, the HSUSB PHY sleep clock supports the clk_reset
operation, and should be called during initialization.
- qcom,vdda-force-on: If present, HW requires a workaround that forces 1.8V and 3.1V
regulator supplies to be left on even when PHY enters into
low power mode.
Example:
hsphy@f9200000 {
compatible = "qcom,usb-hsphy";
reg = <0xf9200000 0xfc000>;
qcom,hsphy-init = <0x00D191A4>;
vdd-supply = <&pm8841_s2_corner>;
vdda18-supply = <&pm8941_l6>;
vdda33-supply = <&pm8941_l24>;
qcom,num_of_ports = <3>;
qcom,vdd-voltage-level = <1 5 7>;
};
SSUSB PHY
Required properties:
- compatible: Should be "qcom,usb-ssphy" or "qcom,usb-ssphy-qmp-v2"
- reg: Address and length of the register set for the device
- <supply-name>-supply: phandle to the regulator device tree node
Required "supply-name" examples are:
"vdd" : vdd supply for SSPHY digital circuit operation
"vdda18" : 1.8v high-voltage analog supply for SSPHY
- qcom,vdd-voltage-level: This property must be a list of three integer
values (no, min, max) where each value represents either a voltage in
microvolts or a value corresponding to voltage corner
Optional properties:
- qcom,vbus-valid-override: If present, indicates VBUS pin is not connected to
the USB PHY and the controller must rely on external VBUS notification in
order to manually relay the notification to the SSPHY.
- qcom,deemphasis-value: This property if present represents ss phy
deemphasis value to be used for overriding into SSPHY register.
- qcom,primary-phy: If present, indicates this is a secondary PHY and is
dependent on the primary PHY referenced by this phandle.
Example:
ssphy@f9200000 {
compatible = "qcom,usb-ssphy";
reg = <0xf9200000 0xfc000>;
vdd-supply = <&pm8841_s2_corner>;
vdda18-supply = <&pm8941_l6>;
qcom,vdd-voltage-level = <1 5 7>;
qcom,deemphasis-value = <26>;
};
SSUSB-QMP PHY
Required properties:
- compatible: Should be "qcom,usb-ssphy-qmp", "qcom,usb-ssphy-qmp-v1" or
"qcom,usb-ssphy-qmp-v2"
- reg: Address and length of the register set for the device
Required regs are:
"qmp_phy_base" : QMP PHY Base register set.
- <supply-name>-supply: phandle to the regulator device tree node
Required "supply-name" examples are:
"vdd" : vdd supply for SSPHY digital circuit operation
"core" : high-voltage analog supply for SSPHY
- clocks: a list of phandles to the PHY clocks. Use as per
Documentation/devicetree/bindings/clock/clock-bindings.txt
- clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
property. Required clocks are "aux_clk" and "pipe_clk".
- qcom,vdd-voltage-level: This property must be a list of three integer
values (no, min, max) where each value represents either a voltage in
microvolts or a value corresponding to voltage corner
- qcom,qmp-phy-init-seq: QMP PHY initialization sequence with reg offset, its
value, delay after register write. It is not must property to have for emulation.
- qcom,qmp-phy-reg-offset: Provides important phy register offsets in an order
defined in the phy driver. Provide below mentioned register offsets in order:
USB3_PHY_PCS_STATUS,
USB3_PHY_AUTONOMOUS_MODE_CTRL,
USB3_PHY_LFPS_RXTERM_IRQ_CLEAR,
USB3_PHY_POWER_DOWN_CONTROL,
USB3_PHY_SW_RESET,
USB3_PHY_START
- resets: reset specifier pair consists of phandle for the reset controller
and reset lines used by this controller.
- reset-names: reset signal name strings sorted in the same order as the resets
property.
Optional properties:
- reg: Additional register set of address and length to control QMP PHY are:
"vls_clamp_reg" : top-level CSR register to be written to enable phy vls
clamp which allows phy to detect autonomous mode.
"tcsr_usb3_dp_phymode" : top-level CSR register to be written to select
super speed usb qmp phy.
- clocks: a list of phandles to the PHY clocks. Use as per
Documentation/devicetree/bindings/clock/clock-bindings.txt
- clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
property. "cfg_ahb_clk" is an optional clock.
- qcom,vbus-valid-override: If present, indicates VBUS pin is not connected to
the USB PHY and the controller must rely on external VBUS notification in
order to manually relay the notification to the SSPHY.
- qcom,emulation: Indicates that we are running on emulation platform.
- qcom,core-voltage-level: This property must be a list of three integer
values (no, min, max) where each value represents either a voltage in
microvolts or a value corresponding to voltage corner.
Example:
ssphy0: ssphy@f9b38000 {
compatible = "qcom,usb-ssphy-qmp";
reg = <0xf9b38000 0x16c>,
<0x01947244 0x4>;
reg-names = "qmp_phy_base",
"vls_clamp_reg";
vdd-supply = <&pmd9635_l4>;
vdda18-supply = <&pmd9635_l8>;
qcom,vdd-voltage-level = <0 900000 1050000>;
qcom,vbus-valid-override;
clocks = <&clock_gcc clk_gcc_usb3_phy_aux_clk>,
<&clock_gcc clk_gcc_usb3_phy_pipe_clk>,
<&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,
<&clock_gcc clk_ln_bb_clk1>,
<&clock_gcc clk_gcc_usb3_clkref_clk>;
clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk",
"ref_clk_src", "ref_clk";
resets = <&clock_gcc GCC_USB3_PHY_BCR>,
<&clock_gcc GCC_USB3PHY_PHY_BCR>;
reset-names = "phy_reset",
"phy_phy_reset";
};
QUSB2 High-Speed PHY
Required properties:
- compatible: Should be "qcom,qusb2phy" or "qcom,qusb2phy-v2"
- reg: Address and length of the QUSB2 PHY register set
- reg-names: Should be "qusb_phy_base".
- <supply-name>-supply: phandle to the regulator device tree node
Required supplies are:
"vdd" : vdd supply for digital circuit operation
"vdda18" : 1.8v high-voltage analog supply
"vdda33" : 3.3v high-voltage analog supply
"vdda12" : 1.2v high-voltage analog supply
- qcom,vdd-voltage-level: This property must be a list of three integer
values (no, min, max) where each value represents either a voltage in
microvolts or a value corresponding to voltage corner
- phy_type: Should be one of "ulpi" or "utmi". ChipIdea core uses "ulpi" mode.
- resets: reset specifier pair consists of phandle for the reset controller
and reset lines used by this controller.
- reset-names: reset signal name strings sorted in the same order as the resets
property.
Optional properties:
- reg-names: Additional registers corresponding with the following:
"efuse_addr": EFUSE address to read and update analog tune parameter.
"emu_phy_base" : phy base address used for programming emulation target phy.
"ref_clk_addr" : ref_clk bcr address used for on/off ref_clk before reset.
"tcsr_clamp_dig_n" : To enable/disable digital clamp to the phy. When
de-asserted, it will prevent random leakage from qusb2 phy resulting from
out of sequence turn on/off of 1p8, 3p3 and DVDD regulators.
- clocks: a list of phandles to the PHY clocks. Use as per
Documentation/devicetree/bindings/clock/clock-bindings.txt
- clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
property. "cfg_ahb_clk", "ref_clk_src" and "ref_clk" are optional clocks.
- qcom,qusb-phy-init-seq: QUSB PHY initialization sequence with value,reg pair.
- qcom,qusb-phy-host-init-seq: QUSB PHY initialization sequence for host mode
with value,reg pair.
- qcom,emu-init-seq : emulation initialization sequence with value,reg pair.
- qcom,phy-pll-reset-seq : emulation PLL reset sequence with value,reg pair.
- qcom,emu-dcm-reset-seq : emulation DCM reset sequence with value,reg pair.
- qcom,efuse-bit-pos: start bit position within EFUSE register
- qcom,efuse-num-bits: Number of bits to read from EFUSE register
- qcom,emulation: Indicates that we are running on emulation platform.
- qcom,hold-reset: Indicates that hold QUSB PHY into reset state.
- qcom,phy-clk-scheme: Should be one of "cml" or "cmos" if ref_clk_addr is provided.
- qcom,major-rev: provide major revision number to differentiate power up sequence. default is 2.0
- qcom,vdda33-voltage-level: A list of three integer values (min, op, max) representing
specific voltages (in microvolts) used for the vdda33 supply.
- qcom,tune2-efuse-correction: The value to be adjusted from fused value for
improved rise/fall times.
Example:
qusb_phy: qusb@f9b39000 {
compatible = "qcom,qusb2phy";
reg = <0x00079000 0x7000>;
reg-names = "qusb_phy_base";
vdd-supply = <&pm8994_s2_corner>;
vdda18-supply = <&pm8994_l6>;
vdda33-supply = <&pm8994_l24>;
qcom,vdd-voltage-level = <1 5 7>;
qcom,efuse-bit-pos = <21>;
qcom,efuse-num-bits = <3>;
clocks = <&clock_rpm clk_ln_bb_clk>,
<&clock_gcc clk_gcc_rx2_usb1_clkref_clk>,
<&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>;
clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk";
resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>;
reset-names = "phy_reset";
};
|
