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| * | clk: msm: Add support for block reset clocks for msmcobaltTaniya Das2016-08-12
| | | | | | | | | | | | | | | | | | | | | | | | Add the block reset clocks which will be used by clients to assert/deassert these clocks using the reset controller framework. Change-Id: I19f4f6e764ffde26ecf3b7cce3fb53a9bf2cc91a Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | | Merge "clk: msm: gcc-cobalt: Remove support for wcss clocks"Linux Build Service Account2016-08-26
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| * | | clk: msm: gcc-cobalt: Remove support for wcss clocksDevesh Jhunjhunwala2016-08-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The wcss clocks are not owned by APCS, and thus should not be modelled in the clock driver. CRs-Fixed: 1054449 Change-Id: I7677bef6a58c028876b72dbade37c1064b428ee2 Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
* | | | Merge "clk: msm: mdss: update Dp PLL/Phy configuration"Linux Build Service Account2016-08-26
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| * | | | clk: msm: mdss: update Dp PLL/Phy configurationChandan Uddaraju2016-08-22
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the Display-Port PHY and PLL configuration with the recommended settings. Remove the support for 9.72Ghz VCO frequency. Update the divider settings to support the new frequency plan. Update the Phy Aux settings and voltage/pre-emphasis settings according to recommended configuration. Change-Id: Ic4d206da3dc6b45214e7601e7556cfb0bef81a7d Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
* / | | clk: msm: clock: Add voter clocks for mmss_camss_jpeg0_clkDeepak Katragadda2016-08-22
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | Add separate voter clocks for controlling the mmss_camss_jpeg0_clk from two clients on MSMCOBALT. CRs-Fixed: 1049594 Change-Id: I530e35054fd512574bca9e5937317099f58d2bb6 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | | Merge "clk: msm: clock: Control the GPLL0 input sources to MMSSCC and GPUCC"Linux Build Service Account2016-08-19
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| * | | clk: msm: clock: Control the GPLL0 input sources to MMSSCC and GPUCCDeepak Katragadda2016-08-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPLL0 input to the multimedia and graphics clock controllers can be managed by use of voting registers. Enable this usage and turn off the inputs when no clocks within these clock controllers need a GPLL0/GPLL0 divider input. CRs-Fixed: 1009689 Change-Id: Iea17649eb63522510cf7887a630d17a2f64a615b Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | | | Merge "clk: msm: clock: Update clock frequencies on MSMCOBALT"Linux Build Service Account2016-08-16
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| * | | clk: msm: clock: Update clock frequencies on MSMCOBALTDeepak Katragadda2016-08-10
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the graphics and multimedia clock frequencies and FMAXes to align with the v2 and vq frequency plans. While doing so, remove support for the gpu_pll1 PLL since it is not going to be used to generate any frequencies. CRs-Fixed: 1051170 Change-Id: I4d6547d95bd76d8ca6f4d729009d8b4a78716d5b Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | / clock: qcom: Update the list of clocks supported on MSMFalconTaniya Das2016-08-12
| |/ |/| | | | | | | | | | | | | | | | | | | | | Add the new clocks and update the clock ids for GCC, GPU, MMSS clock controllers. Also add the RPM clocks which are supported and would be used by the clients for all clock operations for RPM controlled clocks. There are separate MMSS and GPU clock controllers, so add the dummy controllers for the same. Change-Id: I5a98b6128f5d54163ab5d03c4c023a748e6a4e95 Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: msm: Add support for block reset clocksTaniya Das2016-08-08
|/ | | | | | | | Add the block reset clocks which will be used by clients to assert/deassert these clocks using the reset controller framework. Change-Id: I3e9f7f85bf1faf0e1bb501196ba9d7e197111a03 Signed-off-by: Taniya Das <tdas@codeaurora.org>
* Merge "clk: msm: clock: Remove support for the USB cfg_ahb2phy clock from HLOS"Linux Build Service Account2016-07-27
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| * clk: msm: clock: Remove support for the USB cfg_ahb2phy clock from HLOSDeepak Katragadda2016-07-26
| | | | | | | | | | | | | | | | | | The gcc_usb_phy_cfg_ahb2phy_clk clock will be managed by RPM. There is no need to model it in the linux clock driver or to control it from the USB driver. Change-Id: I05641c2d532ada36623da1e1cc687c90bc4ee906 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | Merge "ASoC: aud-ext-clk: enable lnbbclk2 for tavil"Linux Build Service Account2016-07-18
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| * | ASoC: aud-ext-clk: enable lnbbclk2 for tavilYeleswarapu Nagaradhesh2016-07-16
| |/ | | | | | | | | | | | | | | | | Tavil is sourced from lnbbclk2 and hence enable this clock for tavil codec. CRs-Fixed: 1041199 Change-Id: I5409b0f4ed58fefdd25abbe79f144de7e693c1a1 Signed-off-by: Yeleswarapu Nagaradhesh <nagaradh@codeaurora.org>
* / clk: msm: clock-gcc-cobalt: Remove support for gcc_bimc_hmss_axi_clkDeepak Katragadda2016-07-15
|/ | | | | | | | | The gcc_bimc_hmss_axi_clk will be configured outside of HLOS. The linux clock driver does not need to manually enable it. CRs-Fixed: 1012646 Change-Id: Ib0b848fb410f4bf266b09cefed0e8bce7292d2ec Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* clk: msm: clock-mmss-cobalt: Add display port clock supportDeepak Katragadda2016-07-11
| | | | | | | | Add support for the DP link and crypto clocks on MSMCOBALT. CRs-Fixed: 1028725 Change-Id: I6cdb366499f9589dff9a42491c7ff357e98d65c5 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* clock: qcom: Add the clocks supported on MSMFalconTaniya Das2016-07-05
| | | | | | | | | Add all the clocks which are supported on msmfalcon and would be used by the clients for all clock operations for GCC, MMSS, GPU clock controllers. Change-Id: Ie328cb0516644d8a3d66fd0c054575a5cff637dc Signed-off-by: Taniya Das <tdas@codeaurora.org>
* clk: qcom: rpmcc: Add rpm clock data for msm8996Rajendra Nayak2016-06-23
| | | | | | | | | | | Add all RPM clock data for msm8996 family of devices ToDo: Adapt to changes needed for RPM over GLINK against RPM over SMD that the driver currently supports Change-Id: Ib095af601a4f03d866cf94c8e277d04630abb42b Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* clk: qcom: Add support for RPM ClocksGeorgi Djakov2016-06-23
| | | | | | | | | | | | | | This adds initial support for clocks controlled by the Resource Power Manager (RPM) processor on some Qualcomm SoCs, which use the qcom_rpm driver to communicate with RPM. Such platforms are apq8064 and msm8960. Change-Id: I1a73355bc9117c34589a25cf58446cad13ceb6e3 (cherry picked from commit 06d998a24c68be94685af38e8becfda3c8bf757b) Git-commit: 06d998a24c68be94685af38e8becfda3c8bf757b Git-repo: https://git.linaro.org/landing-teams/working/qualcomm/kernel.git Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* clk: qcom: Add support for SMD-RPM ClocksGeorgi Djakov2016-06-23
| | | | | | | | | | | | | | | | | | | | | | | This adds initial support for clocks controlled by the Resource Power Manager (RPM) processor on some Qualcomm SoCs, which use the qcom_smd_rpm driver to communicate with RPM. Such platforms are msm8916, apq8084 and msm8974. The RPM is a dedicated hardware engine for managing the shared SoC resources in order to keep the lowest power profile. It communicates with other hardware subsystems via shared memory and accepts clock requests, aggregates the requests and turns the clocks on/off or scales them on demand. This driver is based on the codeaurora.org driver: https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/clk/qcom/clock-rpm.c Change-Id: I8d2882de9410a992a8045caedc7ab71e3c3e45b2 (cherry picked from commit 69edeaf51c07c24e06b433762b3ada7b3d786315) Git-commit: 69edeaf51c07c24e06b433762b3ada7b3d786315 Git-repo: https://git.linaro.org/landing-teams/working/qualcomm/kernel.git Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* clk: msm: clock: Add support for programming MDP_LUT_CBCR registerDeepak Katragadda2016-06-20
| | | | | | | | | | | Add support for the mdss_mdp_lut_clk clock on MSMCOBALT. In addition, remove toggling the memory retention bits for the mdp core clock during gdsc_enable/disable. The display driver will use the set_flags API to set the core clock memory retention. CRs-Fixed: 1025605 Change-Id: If812473a67a7900c8f7b8b97f32fbf003f0e80a4 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* clk: qcom: gdsc: Add the missing BIMC gdsc for msm8996Rajendra Nayak2016-06-17
| | | | | | | | Add BIMC gdsc data found in MMCC part of msm8996 family of devices. Change-Id: Ibeac134f941f402bcad8e803bdb73ba73f55909d Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* clk: qcom: gdsc: Add mmcc gdscs for msm8996 familyRajendra Nayak2016-06-17
| | | | | | | | | Add all gdsc data which are part of mmcc on msm8996 family Change-Id: I77caf8f26bf676a7553b6873eb188acb02a9c44d Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* clk: qcom: Add MSM8996 Multimedia Clock Controller (MMCC) driverStephen Boyd2016-06-17
| | | | | | | | | | Add a driver for the multimedia clock controller found on MSM8996 based devices. This should allow most multimedia device drivers to probe and control their clocks. Change-Id: I0b69b1e78a8b0faeaff3e5c87c73e24b1c19ba55 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
* clk: qcom: gcc-msm8996: Add missing BCR for USB3 and PCIE clocksAmit Nischal2016-06-16
| | | | | | | | The block reset registers for USB3 and PCIE will be required by the clients to reset their subsystem blocks so add them in the reset map. Change-Id: Ie30158592fca057454152f3f46a5d8b89ae36b88 Signed-off-by: Amit Nischal <anischal@codeaurora.org>
* clk: msm: hdmi: add cobalt hdmi pll calculator and clocksAjay Singh Parmar2016-06-09
| | | | | | | | | | Add PLL and PHY programming for HDMI. Dynamically calculate the register values to be programmed for a given pixel clock. CRs-Fixed: 1022772 Change-Id: Ibf7877eb6edd29baefee57bc12188989d897d47e Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org> Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
* clk: msm: clock: Add support for programming the GCC_GPU_IREF_EN registerDeepak Katragadda2016-06-07
| | | | | | | | | | Add a new gcc_gpu_iref_clk that the graphics driver can control as needed. The default state of the clock is ON; so having this control will mean saving current. CRs-Fixed: 1024948 Change-Id: I562bb546f49b1605f20fb7d705f40584d190230b Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* clk: qcom: gdsc: Add GDSCs in msm8996 GCCRajendra Nayak2016-06-06
| | | | | | | | | Add all data for the GDSCs which are part of msm8996 GCC block Change-Id: I12323575c44b1a3ba4cb2764a498480b3e62dcaa Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* clk: msm: clock-gcc-cobalt: Add the cnoc_periph RPM resource supportDeepak Katragadda2016-06-02
| | | | | | | | | | Add support for modelling a new cnoc_periph RPM resource on MSM COBALT. In addition, fix the rpm_res_type being used for the mmssnoc_axi_clk and remove the pnoc resource support. CRs-Fixed: 1003213 Change-Id: I9f9845fea425fc4463dae72e8f8ab6e8bda23121 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* clk: qcom: Add MSM8996 Global Clock Control (GCC) driverStephen Boyd2016-06-01
| | | | | | | | | | Add support for the global clock controller found on MSM8996 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Change-Id: I559f5976b56bf8933df2c68fc4e29b2bd0ce1160 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* clk: msm: clock-gcc-cobalt: Add reset capability to PCIE pipe clockDeepak Katragadda2016-05-15
| | | | | | | | | Instead of having a separate reset clock for PCIE 0 reset, tag the BCR register with the gcc_pcie_0_pipe_clk directly. CRs-Fixed: 1014989 Change-Id: Icbc3a4a237bd0ac75fbef0857238e18cfb0ca533 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* clk: msm: clock-gcc-cobalt: Add new hw_ctl_clk type UFS clocksDeepak Katragadda2016-05-10
| | | | | | | | | Add new UFS clocks to support enabling/disabling the hardware dynamic gating for their corresponding branch clocks. CRs-Fixed: 1012355 Change-Id: I4836ad8a775b0ec0375e37d27fcbe380e661a7b2 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* clk: qcom: mdss: add Display-port pll clock driver supportChandan Uddaraju2016-05-09
| | | | | | | | | | Add support for new Display-port PLL clock driver to handle different DP panel resolutions in msmcobalt. Add separate files to support this new PHY PLL block. CRs-Fixed: 1009740 Change-Id: Ic282c7e14fc6e23f4d044cb6a58249bdb4c8c2d8 Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
* msm: clock: clock-gcc-cobalt: Support QSPI clocks on MSMHAMSTERDeepak Katragadda2016-05-06
| | | | | | | | | Add programming support for the qspi_ref and qspi_ahb clocks in the linux clocks driver. CRs-Fixed: 1011840 Change-Id: Ic67b72b1e9341fec33bcdbde67f9e2c7e8045ec1 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* clk: msm: clock-gcc-cobalt: Add clock reset support for additional clocksDeepak Katragadda2016-05-03
| | | | | | | | | Add the BCR register for the gcc_ufs_axi_clk and gcc_blsp1/2_ahb_clk clocks. CRs-Fixed: 1005036 Change-Id: I8cd2403bed66141c99ccf8b9c57e59b936c1d90e Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* clk: msm: clock: Support peripheral clocks on MSMHAMSTERDeepak Katragadda2016-04-29
| | | | | | | | | Add support for controlling the peripheral clocks on MSM HAMSTER. CRs-Fixed: 1004885 Change-Id: If77ad3d662fbba145374abe38ea14a1a6e540fee Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* dt-bindings: clock: Add audio external clock of_idx entriesPhani Kumar Uppalapati2016-04-28
| | | | | | | | | Add clock of_idx entries for audio external clock registered to the msm clock framework. CRs-fixed: 1006637 Change-Id: Ia300cafb7246c08ba35fb24c2dc79489edb280a3 Signed-off-by: Phani Kumar Uppalapati <phaniu@codeaurora.org>
* clk: msm: osm: model LMh RCG to ensure OSM clock runs at 200 MHzOsvaldo Banuelos2016-04-27
| | | | | | | | | | The OSM clock is sourced from the LMh RCG. Model this RCG so that it can be configured properly to provide the OSM a 200 MHz clock source. Change-Id: Ib799e8c082977ac226d6bd31ffad8ca63597c0fc CRs-Fixed: 1007896 Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
* ARM: msm: dts: Add interrupt and clock gpios for codec on msmcobaltSudheer Papothi2016-04-26
| | | | | | | | | Add interrupt and clock gpios for wcd9335 codec on msmcobalt target. These changes will provide interrupts from the codec and clock to the codec. Change-Id: I4bd278c9f6e22cdaeed012d0d0d6314acfacd36e Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
* clk: msm: mdss: add support for dsi pll on msmcobaltAravind Venkateswaran2016-04-25
| | | | | | | | | Add support to program the DSI PLL on msmcobalt which is needed to drive the DSI byte and pixel clocks. CRs-Fixed: 1000576 Change-Id: Ic11a3747a0e008e1f71df91a1a79d33242d2a2a4 Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
* clk: msm: clock-gcc-cobalt: Remove support for glm clocksDevesh Jhunjhunwala2016-04-22
| | | | | | | | The glm clocks are controlled by TZ, so remove support for these clocks from the clock-gcc-cobalt driver. Change-Id: Ibfb8f211ca8c29617aca4ff0ee885366f95aac00 Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
* clk: msm: clock-mmss-cobalt: Do not model the Throttle clock registersDeepak Katragadda2016-04-22
| | | | | | | | | | The throttle clocks are managed by XBL and HLOS does not need to control them. Remove support for these clocks from the clock driver. CRs-Fixed: 1006824 Change-Id: I1a33b3dbde6d5526be1073874e28b12350adad5e Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* clk: msm: clock: Add support for the mdss byte_intf_div clocksDeepak Katragadda2016-04-18
| | | | | | | | | | There is a configurable divider between the byte_clk_src RCGs and the mmss_mdss_byte_intf_clk clocks. Add support to program it. CRs-Fixed: 1003173 Change-Id: I976c2b9e9739b603f6cfb10d11c7b1d64cb577c5 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* clk: msm: clock: Register graphics clocks in separate probe functionsDeepak Katragadda2016-04-12
| | | | | | | | | | | | | | The CPR driver on MSMCOBALT needs the gpucc_rbcpr_clk clock in order to probe and register the gfx_vreg regulator which the graphics clock driver in-turn is dependent on for registering the gfx3d clocks. To break this circular dependency, register the non-gfx clocks first, let the CPR driver probe, and then register the GPU PLLs and gfx3d clocks. Also, correct the gfx CRC sequence. CRs-Fixed: 986619 Change-Id: Id16ad7940e96cc9d5a3127551c8a92b05cfbb181 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* clk: msm: clock: Remove support for the gcc_mmss_qm_ahb_clk clockDeepak Katragadda2016-03-25
| | | | | | | | | | The gcc_mmss_qm_ahb_ahb_clk is controlled by XBL on MSMCOBALT. There is no need to control it separately from the linux clock driver. Remove support for it. CRs-Fixed: 988972 Change-Id: I23b4114096758342403e07058ef4df9b18f6622c Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* clk: msm: clock: Add support for programming the DCC AHB clock registerDeepak Katragadda2016-03-25
| | | | | | | | | | The gcc_dcc_ahb_clk needs to be controlled by the HLOS clock driver on MSMCOBALT since its use is restricted to the HLOS debug driver. CRs-Fixed: 988930 Change-Id: I1abef9f1268080dbe5dba1e91f4b84fab03ce66c Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* clk: msm: clock-mmss-cobalt: Add support for some display clocksDeepak Katragadda2016-03-25
| | | | | | | | | The mmss_mdss_byte0/1_intf_clk clocks are needed by the display driver. Add support to program them in the clock driver. CRs-Fixed: 981902 Change-Id: I17b1ecaec9c98261faa49c6f088c4802a716ecf7 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* clk: msm: clock-cpu-8996: Increase CBF PLL post-divider to 4 for 8996proVikram Mulukutla2016-03-23
| | | | | | | | | | | | | | To open up the frequency range from 150 to 300MHz, change the fixed CBF PLL post divider from 2 to 4. That way, to generate frequencies less than 300MHz, the VCO can be run at 4x with the CBF mux set to use the main output. While we're here, add the cbf_pll_main clock to the lookup table. CRs-Fixed: 980903 Change-Id: I9f70f18e01199c41e1940857afb7bdd477c1c04c Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-21 15:35:13 +0000