diff options
| author | Deepak Katragadda <dkatraga@codeaurora.org> | 2016-06-14 13:52:41 -0700 |
|---|---|---|
| committer | Deepak Katragadda <dkatraga@codeaurora.org> | 2016-08-10 17:38:21 -0700 |
| commit | 10991cc6f3d759dd983e6ed3ceffffd3c904967a (patch) | |
| tree | 229f83379999da62f17af8660d80db2cdcda20de /include/dt-bindings/clock | |
| parent | e94b446eac88a43e42ecde105275d48b677ea5b3 (diff) | |
clk: msm: clock: Update clock frequencies on MSMCOBALT
Update the graphics and multimedia clock frequencies and FMAXes
to align with the v2 and vq frequency plans. While doing so,
remove support for the gpu_pll1 PLL since it is not going to be
used to generate any frequencies.
CRs-Fixed: 1051170
Change-Id: I4d6547d95bd76d8ca6f4d729009d8b4a78716d5b
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Diffstat (limited to 'include/dt-bindings/clock')
| -rw-r--r-- | include/dt-bindings/clock/msm-clocks-cobalt.h | 4 | ||||
| -rw-r--r-- | include/dt-bindings/clock/msm-clocks-hwio-cobalt.h | 2 |
2 files changed, 0 insertions, 6 deletions
diff --git a/include/dt-bindings/clock/msm-clocks-cobalt.h b/include/dt-bindings/clock/msm-clocks-cobalt.h index 28efd55ea8f6..85e28a9edc03 100644 --- a/include/dt-bindings/clock/msm-clocks-cobalt.h +++ b/include/dt-bindings/clock/msm-clocks-cobalt.h @@ -484,10 +484,6 @@ #define clk_gpu_pll0_pll_out_even 0xb0ed5009 #define clk_gpu_pll0_pll_out_odd 0x08c5a8a5 #define clk_gpu_pll0_postdiv_clk 0x76c19f3c -#define clk_gpu_pll1_pll 0x09ac81ef -#define clk_gpu_pll1_pll_out_even 0xa503de04 -#define clk_gpu_pll1_pll_out_odd 0x1c205dfb -#define clk_gpu_pll1_postdiv_clk 0xdf546700 #define clk_gpucc_mx_clk 0x1edbb879 #define clk_gpucc_gcc_dbg_clk 0x9ae8cd3c #define clk_gfxcc_dbg_clk 0x3ed47625 diff --git a/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h b/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h index 7ef57256d8f0..6f0e35511cc9 100644 --- a/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h +++ b/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h @@ -235,8 +235,6 @@ #define GPUCC_GPU_PLL0_PLL_MODE 0x00000 #define GPUCC_GPU_PLL0_USER_CTL_MODE 0x0000C -#define GPUCC_GPU_PLL1_PLL_MODE 0x00040 -#define GPUCC_GPU_PLL1_USER_CTL_MODE 0x0004C #define GPUCC_GFX3D_CMD_RCGR 0x01070 #define GPUCC_RBBMTIMER_CMD_RCGR 0x010B0 #define GPUCC_GFX3D_ISENSE_CMD_RCGR 0x01100 |