| Commit message (Collapse) | Author | Age |
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For some panels, the mdp kickoff transaction must
be controlled and only triggered when the scanline
is within certain region. This change adds the
support to control the scanline where the kickoff
can be triggered through panel properties and
if the scanline is not within this region, then
driver will wait for an extra delay that is also
configurable through a panel property.
Change-Id: I06bc6b03f77109adfed428b876915f59d3b5bbfd
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
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User space may request of concurrent writeback (CWB) on the previously
programmed frame where input HW reprogramming may not be needed.
This change make sure mdp control flush is force triggered when
CWB is requested. Since signaling of fence timeline mandates a non-zero
commit count on the display, this change tracks a separate commit count
each time CWB is requested for the frame.
Change-Id: I7f6a134af9e5ad245a53063a90f1d7b625882a15
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
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Update the QoS settings for concurrent writeback in the
supported targets.
Change-Id: I9f190393eb4fcf9f5b3e004732cafeb7ee622894
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
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For power measurements, it is needed to disable
the panel in order to determine the delta
between the consumption with and without
the panel and it's dependencies.
This change adds a sysfs note to disable
the panel and dependencies without disturbing
any of the dsi/mdp configurations.
CRs-Fixed: 878591
Change-Id: I57c1f49aa57f645cb96714edd2f297fa06187c03
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
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Add required changes to fix 32-bit compilation issues in
MDSS PP and DP/HDMI interface drivers.
Change-Id: I0b342c0307b257cb8c66fcae73dd94d0fb3122db
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
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Currently, due to the optimizations made in SMMU with the use of
lazy map/unmap, mapped address would be totally released only when
the buffer is freed and not during the last unmap. So, if app buffers
ends up holding 1G memory due to any reason, it would result in
mapping issues in driver as SMMU still holds reference for all the
1G buffers though it was unmapped from MDP perspective. Increase the
SMMU mapping range to avoid such cases.
Change-Id: I6c28e0fe752fba3f4674b6b5ba454fce5b6e7665
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
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msmcobalt""
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RPM has no way to know if they have to disable the MMSS gdsc
during idle power collapse or if its a full suspend.
Setting up the RPM RAM msg to 1 going into idle power collapse
and setting it to 0 while going to full suspend.
All these states mentioned are from a display point of
view.
Crs-Fixed: 1068650
Change-Id: I0ed47e89f6a4dd332ff28e8a1203ae3bfe44e7fa
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
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This change increases the test points
for vbif debug bus in msmcobalt target.
Change-Id: I07f0ef2ee8d37336047a37aa93c8b4f26d07cd72
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
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Pixel clock can have a 64 bits value; this
value is truncated in some parts of the
driver where it is handled as a 32 bits value.
This change corrects the driver to make sure we
always handle the pixel clock as a 64 bits.
Change-Id: Ia97cb849ac7ce08a5c387eb11b1b01aad36244a0
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
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Fix variable initialization and NULL pointer referencing under error
condition handling in the MDSS driver.
CRs-Fixed: 1067141
Change-Id: Idd971601d5358104831784d645d84b1f9d2b631c
Signed-off-by: Benjamin Chan <bkchan@codeaurora.org>
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When destination scaler is enabled, DSC panel dimension should base on
the scaler destination dimension, and not using the mixer output
dimension. Also move DSC dimension validation after destination scaler
setting applied successfully.
CRs-Fixed: 1065274
Change-Id: Iee328c847ffc16154e78682515454be6a61b35b4
Signed-off-by: Benjamin Chan <bkchan@codeaurora.org>
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Client Driven Prefetch is enabled by Default in HW
and SW whereas the recommended configuration is to
disable this feature.
This change makes sure that driver disables this
feature in msmcobalt and only enables the feature
for targets that need to keep it enabled.
Change-Id: I34c4feb0297838889cc2505eb3e08516165c5f2f
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
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For some use cases, the calculation of the ib
bandwidth prevails over the ab bandwidth. For
such use cases, we must consider the ib as well
as the ab before reducing/increasing the vote,
so the correct sequence to apply the bw vote
is executed along with the HW changes.
Current driver only considers the ab bw and
misses to consider the ib bw during the decision
of when to apply the bw vote.
This change includes ib into the consideration of
when to apply the bw vote.
CRs-Fixed: 1057105
Change-Id: I0822f2e60c4ac22b1636d1d5988ba322dafcdb49
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
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hdcp 1.x can be used by different interfaces attached to
different frame buffers. Add hdcp 1.x data to the panel
specific data so that hdcp 1.x module can access the
corresponding data.
Change-Id: I19917582aa1a52b11eb04e2031403c09bc0aba9b
CRs-Fixed: 1050304
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
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Fix the hdcp 1.x sink address where the random number for the
first part of authentication protocol will be written.
Furthermore, fix the read of random number as generated
on the device before it is sent during authentication.
Change-Id: I665008509a2c00d6627e49a5806069747e00eafd
CRs-Fixed: 1050304
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
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Do not reset interrupt in Display Port driver as HDCP
module also uses same register for interrupts. Use proper
parameters for AUX APIs to avoid communication failures.
CRs-Fixed: 1050304
Change-Id: Ib7b046ca5a0071e571758fd656c86a3fd3be51af
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
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Update the DSI phy v3 initialization sequence as per the
recommended values. The key changes include changing the operating
mode from hybrid to full-rate only.
Change-Id: I999c6f2f76b8991172cd2f5c4b6c99e0ed5d186b
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
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Certain frequencies of DP VCO clock are more than 4.29 GHz
and are not supported by clock framework on 32 bit builds,
since it exceeds the maximum value of unsigned long data type.
To fix this issue, change the DP link clock frequencies in order
of KHz in DP FB driver/MMSS cobalt clock driver/DP PLL driver.
Change-Id: I46d9b5c57f94aa1f10df08c4430b617355a82eec
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
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Program the HDMI/DP core select register during interface setup
since this acts as a mux select for shared interface with LPASS
for audio programming. The mux value is set to 1 for DP and to
0 for HDMI and all other panels.
CRs-Fixed: 1009284
Change-Id: I3283c6255f9cdbbfbffc47057c60b30eb7bdacde
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
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Update the audio programming sequence for Display Port
to include the selection of the maud/naud values for a
given frequency, programming of the safe to exit level
for the main link, and the calculation of the parity bytes
for each byte of a Secondary Data Packet.
CRs-Fixed: 1009284
Change-Id: I3d83b735a81fed834befca21307cafda89eb5878
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
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As part of the PHY shut down sequence, current driver
disable the phy pmic regulators. This is not the
expected sequence, so make sure the pmic phy
regulators stay enabled.
Change-Id: Ia65a71347666ed9fa3f6bf92fe7c573638301254
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
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Currently, as soon as the mode switch for video-cmd mode request
kicks in, few software structures are changed immediately. This
might cause issues when the previous kickoff is in progress with
the kernel thread. Add wait for kickoff before executing mode
switch to avoid such issues.
Change-Id: I2646d00d64416523da9c936715e9af9a2b258eeb
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
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LM provides data stream with some write gaps that are propagated
through VBIF to AXI. If write gap is big enough it hangs AXI/BMIC.
In order to ensure there are no gaps in the outgoing data transfer
to AXI interface, all write data must available before initiating
an access. Starting with SDE3xx, the outgoing burst data collection
function is implemented in VBIF module, and it is HW recommendation
to enable this for WB2.
Change-Id: I6f0495068dd6344f8cd161175947391e5998b8d4
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
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Add sysfs node to provide the status of display-port's 3D
mode support. Framework will query about the interface for
3D mode status before enabling the corresponding
FrameBuffer.
Change-Id: If53a034c3c5ee39a95b2501ee495e572f60d6b56
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
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In the current implementation, if a DSI panel does not explicitly
specify the minimum supported refresh rate, then it is set to
48 by default. This is incorrect since many panels may not support
that low of a refresh rate. Fix this by setting the default value
to the panel's actual refresh rate.
CRs-Fixed: 1056610
Change-Id: I8d4267528068e36a648c328fbe6d6a35943f3810
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
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msmcobalt requires MDP clks ON when configuring the retention bits of
MDSS_MDP_CBCR and MDSS_MDP_LUT_CBCR registers, so that the retention
signals can be propagated to memories. This change adds the code
to support the new requirement.
Change-Id: I75b83ce99f061104641188c0f0d3d6cd3e0cfb09
Signed-off-by: Ping Li <pingli@codeaurora.org>
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Store the avr vtotal information computed from the initial timing
information and use it to restore the register values to avoid
flickering issues during suspend/resume usecase.
CRs-Fixed: 1056610
Change-Id: I8c7d27a062b90a3f200904f0ba20fbdb0bb32d70
Signed-off-by: Ramkumar Radhakrishnan <ramkumar@codeaurora.org>
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