diff options
| author | Tatenda Chipeperekwa <tatendac@codeaurora.org> | 2016-08-22 15:33:45 -0700 |
|---|---|---|
| committer | Tatenda Chipeperekwa <tatendac@codeaurora.org> | 2016-09-08 12:52:38 -0700 |
| commit | 64add74566134283ab725f0db9ba4ebda087e576 (patch) | |
| tree | bdfb8e64c944d5b34b8123932e7c91284c577df3 /drivers/video/fbdev | |
| parent | 02bc9609c3b01109a67f5ff9bd33c96e20fd9f9c (diff) | |
msm: mdss: program HDMI/DP core select during interface setup
Program the HDMI/DP core select register during interface setup
since this acts as a mux select for shared interface with LPASS
for audio programming. The mux value is set to 1 for DP and to
0 for HDMI and all other panels.
CRs-Fixed: 1009284
Change-Id: I3283c6255f9cdbbfbffc47057c60b30eb7bdacde
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Diffstat (limited to 'drivers/video/fbdev')
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_mdp_hwio.h | 1 | ||||
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_mdp_intf_video.c | 6 |
2 files changed, 7 insertions, 0 deletions
diff --git a/drivers/video/fbdev/msm/mdss_mdp_hwio.h b/drivers/video/fbdev/msm/mdss_mdp_hwio.h index f54cbb575535..78a52dba53d1 100644 --- a/drivers/video/fbdev/msm/mdss_mdp_hwio.h +++ b/drivers/video/fbdev/msm/mdss_mdp_hwio.h @@ -822,6 +822,7 @@ enum mdss_mdp_pingpong_index { #define MDSS_MDP_DSPP_DEBUGBUS_STATUS 0x34C /* Following offsets are with respect to MDP base */ +#define MDSS_MDP_HDMI_DP_CORE_SELECT 0x408 #define MDSS_MDP_MDP_OUT_CTL_0 0x410 #define MDSS_MDP_INTF_CMD_MISR_CTRL (MDSS_MDP_INTF_MISR_CTRL + 0x8) #define MDSS_MDP_INTF_CMD_MISR_SIGNATURE (MDSS_MDP_INTF_MISR_CTRL + 0xC) diff --git a/drivers/video/fbdev/msm/mdss_mdp_intf_video.c b/drivers/video/fbdev/msm/mdss_mdp_intf_video.c index cee168a33f85..0f582e6706b9 100644 --- a/drivers/video/fbdev/msm/mdss_mdp_intf_video.c +++ b/drivers/video/fbdev/msm/mdss_mdp_intf_video.c @@ -1845,6 +1845,7 @@ static int mdss_mdp_video_ctx_setup(struct mdss_mdp_ctl *ctl, u32 dst_bpp; struct mdss_data_type *mdata = ctl->mdata; struct dsc_desc *dsc = NULL; + u32 hdmi_dp_core; ctx->ctl = ctl; ctx->intf_type = ctl->intf_type; @@ -1966,6 +1967,11 @@ static int mdss_mdp_video_ctx_setup(struct mdss_mdp_ctl *ctl, mdp_video_write(ctx, MDSS_MDP_REG_INTF_PANEL_FORMAT, ctl->dst_format); + hdmi_dp_core = (ctx->intf_type == MDSS_INTF_EDP) ? 1 : 0; + + writel_relaxed(hdmi_dp_core, mdata->mdp_base + + MDSS_MDP_HDMI_DP_CORE_SELECT); + return 0; } |