| Commit message (Collapse) | Author | Age |
|---|
| |
|
|
|
|
|
|
| |
The MSM PCIE core is enabled in endpoint mode and handles the
link from PCIE root complex on host side.
Change-Id: I5a23ea1a41fede2d57850ff032bf2b1a92d02463
Signed-off-by: Yimin Peng <yiminp@codeaurora.org>
|
| |
|
|
|
|
|
|
| |
Update the PHY register dump for PCIe Endpoint mode so that more
debugging information could be acquired in case of PHY failure.
Change-Id: I6b40df668d8a5c912547af701e8a2150db47452f
Signed-off-by: Yan He <yanhe@codeaurora.org>
|
| |
|
|
|
|
|
| |
Update the PHY sequence of PCIe Endpoint mode to support L1ss.
Change-Id: Ib80a2fab167e232540240183387a441d246463a5
Signed-off-by: Yan He <yanhe@codeaurora.org>
|
| |
|
|
|
|
|
|
| |
Add the support of MDM2AP GPIO so that MDM can notify AP about
updated status.
Change-Id: Ia5a020898d4d04dcd4fec6b3928aba380663ac56
Signed-off-by: Yan He <yanhe@codeaurora.org>
|
| |
|
|
|
|
|
|
| |
Add the support to generate both PCIe PARF based MSI generation
and iATU based address write MSI generation for unit test.
Change-Id: I8c5abf8dcae4ebf2c33fee182f6bc147979f74dd
Signed-off-by: Yan He <yanhe@codeaurora.org>
|
| |
|
|
|
|
|
| |
Configure PCIe debug register to enable IRQ for BME.
Change-Id: I497d86fcdbe862d770b9e7841dabd023cfe6d1f8
Signed-off-by: Yan He <yanhe@codeaurora.org>
|
| |
|
|
|
|
|
|
| |
Set up the execution environment before PCIe link training to
provide better adaptability to various hosts.
Change-Id: I72721d3b88a7e5b1a0a1f408da2228391559468e
Signed-off-by: Yan He <yanhe@codeaurora.org>
|
| |
|
|
|
|
|
|
|
| |
The PCIe clients will utilize the original MSI address instead of
mapped local address when active config is enabled. The change here
provides the original address to the clients.
Change-Id: I0d35fa9508d7c3ec2e97bd7d61754974e798bf8a
Signed-off-by: Yan He <yanhe@codeaurora.org>
|
| |
|
|
|
|
|
|
| |
Update the regulator API used in PCIe endpoint driver for 4.4
kernel upgrade.
Change-Id: Iacca851bfbd7f5a5544b97ac82630d9a2dc5ebfc
Signed-off-by: Yan He <yanhe@codeaurora.org>
|
| |
|
|
|
|
|
| |
Add the support of PCIe Endpoint (EP) mode for mdmcalifornium.
Change-Id: I55c85813e674810d865b444b7e19ce4157cea479
Signed-off-by: Yan He <yanhe@codeaurora.org>
|
| |
|
|
|
|
|
|
|
|
| |
Update check for valid MSI enable and setting using
MSI_ENABLE bit instead of address and data. Host can
set address and data to 0 therefore check if MSI_ENABLE
is set.
Change-Id: I686c3ed155b8c5c843d12a49218f4720655dcc18
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
|
| |
|
|
|
|
|
| |
Update the configuration of PCIe PHY based on the version of PHY.
Change-Id: I1faf65c2cc1215cd6ad679d0c4558a17f43db3fc
Signed-off-by: Yan He <yanhe@codeaurora.org>
|
| |
|
|
|
|
|
| |
Add the support to trigger link training based on PCIe PHY version.
Change-Id: I4c765797d8e8adf5c15effae95da350a0d8ec0c3
Signed-off-by: Yan He <yanhe@codeaurora.org>
|
| |
|
|
|
|
|
|
| |
Add the phy reset clock for PCIe endpoint mode and add the support
of this optional clock.
Change-Id: Id92e2fd589d0e97e8a3db2e1eeb1d6c99a464777
Signed-off-by: Yan He <yanhe@codeaurora.org>
|
| |
|
|
|
|
|
|
|
| |
PCIe device ID can't be got from register when the power of the
core is off. Thus, use the saved device ID so that we can turn on
link in the debugfs testing.
Change-Id: I28ec17b4fdf84b130cd32267d097b1c0d7c32aed
Signed-off-by: Yan He <yanhe@codeaurora.org>
|
| |
|
|
|
|
|
|
| |
Fix the bug of the power status of PCIe core and update the power
status as soon as power is turned on.
Change-Id: Ib5b550c78a630d36049296daf1291065a1a44cd5
Signed-off-by: Yan He <yanhe@codeaurora.org>
|
| |
|
|
|
|
|
|
| |
Update retry counters and intervals for PCIe PHY init and PCIe link
training to accommodate various hosts.
Change-Id: I767de1f08580137559e974c0ef90273ccf5f4b76
Signed-off-by: Yan He <yanhe@codeaurora.org>
|
| |
|
|
|
|
|
|
| |
Update the lpeak values of PCIe LDOs based on the updated HW
requirement.
Change-Id: I2f8b63edf3f8571ea960abdebde982324f7f6d74
Signed-off-by: Yan He <yanhe@codeaurora.org>
|
| |
|
|
|
|
|
| |
Enable L1ss support in L1ss capability register.
Change-Id: I51e6e1bbd8073e7bb88c7e041199d862db020ae7
Signed-off-by: Yan He <yanhe@codeaurora.org>
|
| |
|
|
|
|
|
| |
Disable debouncers for PCIe endpoint mode.
Change-Id: I504418193920861296d995bd898f01307e6dc518
Signed-off-by: Yan He <yanhe@codeaurora.org>
|
| |
|
|
|
|
|
|
| |
Update some read-only PCIe registers with non-arbitrary values
which are required by PCIe compliance testing.
Change-Id: I10fd448f38d874ba582d1a46a98a76d29e0d9cb4
Signed-off-by: Yan He <yanhe@codeaurora.org>
|
| |
|
|
|
|
|
|
|
| |
The logging macro has multiple outputs. If we increase the counter
as a parameter to the logging macro, the counter will be increased
for multiple times. The change here fixes this bug.
Change-Id: I321e281b506e35770e222def86f5b04ae0bfdce2
Signed-off-by: Yan He <yanhe@codeaurora.org>
|
| |
|
|
|
|
|
|
| |
Correct the PME configuration for PCIe endpoint to support D0, D3
hot and D3 cold.
Change-Id: Ib906fbafc490be75e5f178176e33882c392d074e
Signed-off-by: Yan He <yanhe@codeaurora.org>
|
| |
|
|
|
|
|
|
|
| |
PCIe client may need to wake up the host when PCIe link is still
on. Add the support to assert wake to host side when PCIe is in
D3hot.
Change-Id: I15ffd5f03183054c7ef5d143757b923f32de0adc
Signed-off-by: Yan He <yanhe@codeaurora.org>
|
|
|
The MSM PCIe endpoint driver enables the PCIe core in endpoint mode
and handles the control signaling with PCIe root complex on host
side.
Change-Id: Ifc2735e061820762c6040eda44089a2dc26fc065
Signed-off-by: Yan He <yanhe@codeaurora.org>
|
