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path: root/drivers/phy/Makefile (follow)
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* msm: Rename msmfalcon/apqfalcon to sdm660/sda660Neeraj Upadhyay2016-12-28
| | | | | | | | | Update the code name from msmfalcon/apqfalcon to sdm660/sda660. As part of this, update the filename containing "falcon" and files content containing "falcon". Change-Id: Iec85862251b9e1b4dcc8bdce8b214ce87c0049bc Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
* phy: ufs: add UFS PHY support for msmfalconAsutosh Das2016-12-12
| | | | | | | | | | | | Add support for new UFS PHY that is used in falcon msm. This PHY is identical to the final 8996 PHY except it has been moved to VDDMX and level shifters have been added between the controller/chip and the PHY. Change-Id: I50681c877917a58c3d70262597300b0d66b1e3a8 Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
* phy: qcom-ufs: add QRBTC V2 UFS phy to makefileYaniv Gardi2016-03-22
| | | | | | | | | | This change adds the qrbtc-v2 files to the phy makefile. Change-Id: I32a1cd2804f11d5b8cc68ae625301be08e710dc8 Signed-off-by: Gilad Broner <gbroner@codeaurora.org> Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> [venkatg@codeaurora.org: resolved trivial merge conflicts] Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* Revert "phy: qcom-ufs: add ufs phy type selection"Yaniv Gardi2016-03-22
| | | | | | | | | | | | | This reverts commit 6ed4bd3af2c153ae3246d89c2d62cfe7919d0320 ("phy: qcom-ufs: add ufs phy type selection") Since a single boot.img should support all phy-qcom-ufs configurations, all phy-qcom-ufs files should be compiled all together. Change-Id: I81b3891fb44d927046f39bbe72b5ed24dd9d99d2 Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> [venkatg@codeaurora.org: resolved trivial merge conflicts] Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* phy: qcom-ufs: add UFS PHY support for msmcobalt rumi platformYaniv Gardi2016-03-22
| | | | | | | Add support for QRBTC V2 UFS PHY that is used in msmcobalt rumi platform. Change-Id: I21ad3f0db23ea16d05ba40593cc7650e1a443702 Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
* phy: qcom-ufs: add support in UFS PHY for msmcobalt platformYaniv Gardi2016-03-22
| | | | | | | | | | Add support for new QCOM UFS PHY that is used in future platforms. Change-Id: I53f162738668ae9f24f5edb9c42a17f947e68b40 Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> [venkatg@codeaurora.org: resolved trivial merge conflict] Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* phy: qcom-ufs: add ufs phy type selectionGilad Broner2016-03-22
| | | | | | | | | | | | Currently both 14nm phy and 20nm phy are compiled and built into the kernel, while only one type is actually present and used. Add a choice selection to the kernel configuration to specify which phy type shall be used. Change-Id: I5608d32fb4815db15e91a970e53099762eabbddd Signed-off-by: Gilad Broner <gbroner@codeaurora.org> [venkatg@codeaurora.org: resolved trivial merge conflicts] Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* phy: qcom-ufs: remove support for 28nm phyYaniv Gardi2016-03-22
| | | | | | | | | | | As there is no support for UFS in APQ8084 under kernel 3.14, we also can remove the support for 28nm ufs phy (since APQ8084 is the only platform that uses this phy). Change-Id: Iae76f98424842cc29e9397c0050a37a010509bcc Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> [subhashj@codeaurora.org: resolved trivial merge conflicts] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* phy: relocate and rename phy ufs filesYaniv Gardi2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | This change contains: 1. Relocating the phy ufs files to reside under the phy driver since this is the location of any file that implements the APIs presented in the generic phy framework 2. Renaming ufs-msm-phy*.* files to be phy-qcom-ufs*.* files. Since UFS is not used strictly in a specific set of targets but rather its code is applicable to MSM, APQ, IPQ etc, any mentioning of "msm" in the file name should be changed to "qcom". Also, prefix of "phy-" is the naming convention of platform driver files that reside in the phy driver. 3. As a result of the relocation of files into the phy driver, a new path is created (include/linux/scsi/ufs) and there we expose ufs header files that are being used also from the drivers/scsi/ufs and from drivers/phy as well. Change-Id: Ie5cb47718911ff711d9401a389f56fa508fcddf3 Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> [gbroner@codeaurora.org: fix merge conflicts] Signed-off-by: Gilad Broner <gbroner@codeaurora.org> [venkatg@codeaurora.org: resolved merge conflicts by keeping upstream version] Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* phy: cygnus: pcie: Add Cygnus PCIe PHY supportRay Jui2015-10-06
| | | | | | | | | | | This patch adds the PCIe PHY support for the Broadcom PCIe RC interface on Cygnus Signed-off-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Arun Parameswaran <aparames@broadcom.com> Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: add usb3.0 phy driver for mt65xx SoCsChunfeng Yun2015-10-06
| | | | | | | support usb3.0 phy of mt65xx SoCs Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: add lpc18xx usb otg phy driverJoachim Eastwood2015-07-25
| | | | | | | | | | Add PHY driver for the internal USB OTG PHY found on NXP LPC18xx and LPC43xx devices. This driver takes care of enabling the PHY in CREG (syscon) and setting the required clock frequency. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2015-06-27
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: - Improvements to the tlb_dump code - KVM fixes - Add support for appended DTB - Minor improvements to the R12000 support - Minor improvements to the R12000 support - Various platform improvments for BCM47xx - The usual pile of minor cleanups - A number of BPF fixes and improvments - Some improvments to the support for R3000 and DECstations - Some improvments to the ATH79 platform support - A major patchset for the JZ4740 SOC adding support for the CI20 platform - Add support for the Pistachio SOC - Minor BMIPS/BCM63xx platform support improvments. - Avoid "SYNC 0" as memory barrier when unlocking spinlocks - Add support for the XWR-1750 board. - Paul's __cpuinit/__cpuinitdata cleanups. - New Malta CPU board support large memory so enable ZONE_DMA32. * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (131 commits) MIPS: spinlock: Adjust arch_spin_lock back-off time MIPS: asmmacro: Ensure 64-bit FP registers are used with MSA MIPS: BCM47xx: Simplify handling SPROM revisions MIPS: Cobalt Don't use module_init in non-modular MTD registration. MIPS: BCM47xx: Move NVRAM driver to the drivers/firmware/ MIPS: use for_each_sg() MIPS: BCM47xx: Don't select BCMA_HOST_PCI MIPS: BCM47xx: Add helper variable for storing NVRAM length MIPS: IRQ/IP27: Move IRQ allocation API to platform code. MIPS: Replace smp_mb with release barrier function in unlocks. MIPS: i8259: DT support MIPS: Malta: Basic DT plumbing MIPS: include errno.h for ENODEV in mips-cm.h MIPS: Define GCR_GIC_STATUS register fields MIPS: BPF: Introduce BPF ASM helpers MIPS: BPF: Use BPF register names to describe the ABI MIPS: BPF: Move register definition to the BPF header MIPS: net: BPF: Replace RSIZE with SZREG MIPS: BPF: Free up some callee-saved registers MIPS: Xtalk: Update xwidget.h with known Xtalk device numbers ...
| * PHY: Add driver for Pistachio USB2.0 PHYAndrew Bresticker2015-06-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the USB2.0 PHY found on the IMG Pistachio SoC. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: James Hartley <james.hartley@imgtec.com> Cc: Damien Horsley <Damien.Horsley@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/9728/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | phy: add Marvell HSIC 28nm PHYRob Herring2015-06-09
| | | | | | | | | | | | | | | | | | Add PHY driver for the Marvell HSIC 28nm PHY. This PHY is found in PXA1928 SOC. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | phy: Add Marvell USB 2.0 OTG 28nm PHYRob Herring2015-06-09
| | | | | | | | | | | | | | | | Add driver for USB 28nm PHY found in Marvell PXA1928 SOC. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | Merge tag 'phy-for-v4.2' of ↵Greg Kroah-Hartman2015-06-03
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next Kishon writes: phy: for 4.2 merge window *) new Broadcom SATA3 PHY driver for Broadcom STB SoCs *) new phy API to get PHY by index which is used in EHCI and OHCI controller drivers *) support specifying supply at port level used for multi-port PHYs *) sparse warning fixes in miphy PHYs *) fix pm_runtime issues in twl4030 driver Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| * | phy: add Broadcom SATA3 PHY driver for Broadcom STB SoCsBrian Norris2015-05-22
| |/ | | | | | | | | | | | | | | Supports up to two ports which can each be powered on/off and configured independently. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* / phy: add driver for TI TUSB1210 ULPI PHYHeikki Krogerus2015-05-13
|/ | | | | | | | | | | | | TUSB1210 ULPI PHY has vendor specific register for eye diagram tuning. On some platforms the system firmware has set optimized value to it. In order to not loose the optimized value, the driver stores it during probe and restores it every time the PHY is powered back on. Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Acked-by: David Cohen <david.a.cohen@linux.intel.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* phy: Add driver to support individual USB PHYs on sun9iChen-Yu Tsai2015-04-03
| | | | | | | | | | | | Unlike previous Allwinner SoCs, there is no central PHY control block on the A80. Also, OTG support is completely split off into a different controller. This adds a new driver to support the regular USB PHYs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: Add a driver for dm816x USB PHYTony Lindgren2015-04-03
| | | | | | | | | | | | | | | | | Add a minimal driver for dm816x USB. This makes USB work on dm816x without any other changes needed as it can use the existing musb_dsps glue layer for the USB controller. Note that this phy is different from dm814x and am335x. Cc: Bin Liu <binmlist@gmail.com> Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Felipe Balbi <balbi@ti.com> Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Cc: Paul Bolle <pebolle@tiscali.nl> Cc: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* Merge tag 'usb-3.20-rc1' of ↵Linus Torvalds2015-02-15
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB patches from Greg KH: "Here's the big pull request for the USB driver tree for 3.20-rc1. Nothing major happening here, just lots of gadget driver updates, new device ids, and a bunch of cleanups. All of these have been in linux-next for a while with no reported issues" * tag 'usb-3.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (299 commits) usb: musb: fix device hotplug behind hub usb: dwc2: Fix a bug in reading the endpoint directions from reg. staging: emxx_udc: fix the build error usb: Retry port status check on resume to work around RH bugs Revert "usb: Reset USB-3 devices on USB-3 link bounce" uhci-hub: use HUB_CHAR_* usb: kconfig: replace PPC_OF with PPC ehci-pci: disable for Intel MID platforms (update) usb: gadget: Kconfig: use bool instead of boolean usb: musb: blackfin: remove incorrect __exit_p() USB: fix use-after-free bug in usb_hcd_unlink_urb() ehci-pci: disable for Intel MID platforms usb: host: pci_quirks: joing string literals USB: add flag for HCDs that can't receive wakeup requests (isp1760-hcd) USB: usbfs: allow URBs to be reaped after disconnection cdc-acm: kill unnecessary messages cdc-acm: add sanity checks usb: phy: phy-generic: Fix USB PHY gpio reset usb: dwc2: fix USB core dependencies usb: renesas_usbhs: fix NULL pointer dereference in dma_release_channel() ...
| * phy: add a driver for the Rockchip SoC internal USB2.0 PHYYunzhi Li2015-01-30
| | | | | | | | | | | | | | | | | | | | | | | | This patch to add a generic PHY driver for ROCKCHIP usb PHYs, currently this driver can support RK3288. The RK3288 SoC have three independent USB PHY IPs which are all configured through a set of registers located in the GRF (general register files) module. Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* | phy: qcom-ufs: add support for 14nm phyYaniv Gardi2015-01-20
| | | | | | | | | | | | | | | | | | This change adds a support for a 14nm qcom-ufs phy that is required in platforms that use ufs-qcom controller. Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> Reviewed-by: Dov Levenglick <dovl@codeaurora.org> Signed-off-by: Christoph Hellwig <hch@lst.de>
* | phy: qcom-ufs: add support for 20nm phyYaniv Gardi2015-01-20
| | | | | | | | | | | | | | | | | | This change adds a support for a 20nm qcom-ufs phy that is required in platforms that use ufs-qcom controller. Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> Reviewed-by: Dov Levenglick <dovl@codeaurora.org> Signed-off-by: Christoph Hellwig <hch@lst.de>
* | phy: qcom-ufs: add support for QUALCOMM Technologies UFS PHY driversYaniv Gardi2015-01-20
|/ | | | | | | | | | | This change adds a generic and common API support for ufs phy QUALCOMM Technologies. This support provides common code and also points to specific phy callbacks to differentiate between different behaviors of frequent use-cases (like power on, power off, phy calibration etc). Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> Reviewed-by: Dov Levenglick <dovl@codeaurora.org> Signed-off-by: Christoph Hellwig <hch@lst.de>
* phy: add support for USB cluster on the Armada 375 SoCGregory CLEMENT2014-11-26
| | | | | | | | | | | | | | | | The Armada 375 SoC comes with an USB2 host and device controller and an USB3 controller. The USB cluster control register allows to manage common features of both USB controllers. This commit adds a driver integrated in the generic PHY framework to control this USB cluster feature. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [ kishon@ti.com : Made it to use the updated devm_phy_create API and soem cosmentic changes in Kconfig file.] Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
* phy: add the Berlin USB PHY driverAntoine Tenart2014-11-21
| | | | | | | | Add the driver driving the Marvell Berlin USB PHY. This allows to initialize the PHY and to use it from the USB driver later. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: miphy28lp: Provide support for the MiPHY28lp Generic PHYGabriel FERNANDEZ2014-11-12
| | | | | | | | | | The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe or USB3 devices. Signed-off-by: alexandre torgue <alexandre.torgue@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-stih41x-usb: Add usb phy support for STiH41x SoCs.Peter Griffin2014-09-24
| | | | | | | | | This driver adds support for USB (1.1 and 2.0) phy for STiH415 and STiH416 System-On-Chips from STMicroelectronics. Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: phy-stih407-usb: Add usb picoPHY driver found on stih407 SoC familyPeter Griffin2014-09-24
| | | | | | | | | | This is the generic phy driver for the picoPHY ports used by the USB2 and USB3 Host controllers when controlling usb2/1.1 devices. It is found on STiH407 SoC family from STMicroelectronics. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: Renesas R-Car Gen2 PHY driverSergei Shtylyov2014-09-24
| | | | | | | | | | | | | | | | | | This PHY, though formally being a part of Renesas USBHS controller, contains the UGCTRL2 register that controls multiplexing of the USB ports (Renesas calls them channels) to the different USB controllers: channel 0 can be connected to either PCI EHCI/OHCI or USBHS controllers, channel 2 can be connected to PCI EHCI/OHCI or xHCI controllers. This is a new driver for this USB PHY currently already supported under drivers/ usb/phy/. The reason for writing the new driver was the requirement that the multiplexing of USB channels to the controller be dynamic, depending on what USB drivers are loaded, rather than static as provided by the old driver. The infrastructure provided by drivers/phy/phy-core.c seems to fit that purpose ideally. The new driver only supports device tree probing for now. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* Merge tag 'drivers-for-3.17' of ↵Linus Torvalds2014-08-08
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver changes from Olof Johansson: "A handful of driver-related changes. We've had a bunch of them going in through other branches as well, so it's only a part of what we really have this release. Larger pieces are: - Removal of a now unused PWM driver for atmel [ This includes AVR32 changes that have been appropriately acked ] - Performance counter support for the arm CCN interconnect - OMAP mailbox driver cleanups and consolidation - PCI and SATA PHY drivers for SPEAr 13xx platforms - Redefinition (with backwards compatibility!) of PCI DT bindings for Tegra to better model regulators/power" Note: this merge also fixes up the semantic conflict with the new calling convention for devm_phy_create(), see commit f0ed817638b5 ("phy: core: Let node ptr of PHY point to PHY and not of PHY provider") that came in through Greg's USB tree. Semantic merge patch by Stephen Rothwell <sfr@canb.auug.org.au> through the next tree. * tag 'drivers-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (38 commits) bus: arm-ccn: Fix error handling at event allocation mailbox/omap: add a parent structure for every IP instance mailbox/omap: remove the private mailbox structure mailbox/omap: consolidate OMAP mailbox driver mailbox/omap: simplify the fifo assignment by using macros mailbox/omap: remove omap_mbox_type_t from mailbox ops mailbox/omap: remove OMAP1 mailbox driver mailbox/omap: use devm_* interfaces bus: ARM CCN: add PERF_EVENTS dependency bus: ARM CCN PMU driver PCI: spear: Remove spear13xx_pcie_remove() PCI: spear: Fix Section mismatch compilation warning for probe() ARM: tegra: Remove legacy PCIe power supply properties PCI: tegra: Remove deprecated power supply properties PCI: tegra: Implement accurate power supply scheme ARM: SPEAr13xx: Update defconfigs ARM: SPEAr13xx: Add pcie and miphy DT nodes ARM: SPEAr13xx: Add bindings and dt node for misc block ARM: SPEAr13xx: Fix static mapping table phy: Add drivers for PCIe and SATA phy on SPEAr13xx ...
| * phy: Add drivers for PCIe and SATA phy on SPEAr13xxPratyush Anand2014-07-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM based ST Microelectronics's SPEAr1310/40 platforms uses ST's phy (known as 'miphy') for PCIe and SATA. This patch adds drivers for these miphys. This also adds proper bindings for miphys. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Pratyush Anand <pratyush.anand@st.com> Tested-by: Mohit Kumar <mohit.kumar@st.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> [viresh: fixed logs/cclist/checkpatch warnings, broken into smaller patches] Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
* | Merge tag 'soc-for-3.17' of ↵Linus Torvalds2014-08-08
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform changes from Olof Johansson: "This is the bulk of new SoC enablement and other platform changes for 3.17: - Samsung S5PV210 has been converted to DT and multiplatform - Clock drivers and bindings for some of the lower-end i.MX 1/2 platforms - Kirkwood, one of the popular Marvell platforms, is folded into the mvebu platform code, removing mach-kirkwood - Hwmod data for TI AM43xx and DRA7 platforms - More additions of Renesas shmobile platform support - Removal of plat-samsung contents that can be removed with S5PV210 being multiplatform/DT-enabled and the other two old platforms being removed New platforms (most with only basic support right now): - Hisilicon X5HD2 settop box chipset is introduced - Mediatek MT6589 (mobile chipset) is introduced - Broadcom BCM7xxx settop box chipset is introduced + as usual a lot other pieces all over the platform code" * tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (240 commits) ARM: hisi: remove smp from machine descriptor power: reset: move hisilicon reboot code ARM: dts: Add hix5hd2-dkb dts file. ARM: debug: Rename Hi3716 to HIX5HD2 ARM: hisi: enable hix5hd2 SoC ARM: hisi: add ARCH_HISI MAINTAINERS: add entry for Broadcom ARM STB architecture ARM: brcmstb: select GISB arbiter and interrupt drivers ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs ARM: configs: enable SMP in bcm_defconfig ARM: add SMP support for Broadcom mobile SoCs Documentation: arm: misc updates to Marvell EBU SoC status Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC ARM: mvebu: fix build without platforms selected ARM: mvebu: add cpuidle support for Armada 38x ARM: mvebu: add cpuidle support for Armada 370 cpuidle: mvebu: add Armada 38x support cpuidle: mvebu: add Armada 370 support cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7 ARM: mvebu: export the SCU address ...
| * | phy: Add support for S5PV210 to the Exynos USB 2.0 PHY driverMateusz Krawczuk2014-07-19
| |/ | | | | | | | | | | | | | | | | | | | | | | Add support for the Samsung's S5PV210 SoC to the Exynos USB 2.0 PHY driver. Signed-off-by: Mateusz Krawczuk <m.krawczuk@partner.samsung.com> [k.debski@samsung.com: cleanup and commit description] [k.debski@samsung.com: make changes accordingly to the mailing list comments] Signed-off-by: Kamil Debski <k.debski@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | phy: miphy365x: Provide support for the MiPHY356x Generic PHYLee Jones2014-07-22
| | | | | | | | | | | | | | | | | | | | | | The MiPHY365x is a Generic PHY which can serve various SATA or PCIe devices. It has 2 ports which it can use for either; both SATA, both PCIe or one of each in any configuration. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* | phy: qcom: Add driver for QCOM IPQ806x SATA PHYKumar Gala2014-07-22
| | | | | | | | | | | | | | | | Add a PHY driver for uses with AHCI based SATA controller driver on the IPQ806x family of SoCs. Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* | phy: add a driver for the Berlin SATA PHYAntoine Ténart2014-07-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Berlin SoC has a two SATA ports. Add a PHY driver to handle them. The mode selection can let us think this PHY can be configured to fit other purposes. But there are reasons to think the SATA mode will be the only one usable: the PHY registers are only accessible indirectly through two registers in the SATA range, the PHY seems to be integrated and no information tells us the contrary. For these reasons, make the driver a SATA PHY driver. Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* | phy: qcom: Add driver for QCOM APQ8064 SATA PHYSrinivas Kandagatla2014-07-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a PHY driver for uses with AHCI based SATA controller driver on the APQ8064 family of SoCs. This patch is a forward port from Qualcomm's v3.4 andriod kernel. Tested on IFC6410 board. CC: Sujit Reddy Thumma <sthumma@codeaurora.org> Tested-by: Kiran Padwal <kiran.padwal@smartplayin.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* | phy: add hix5hd2-sata-phy driverJiancheng Xue2014-07-22
|/ | | | | | | | Add hix5hd2-sata-phy driver on Hisilicon hix5hd2 soc. Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: Add new Exynos5 USB 3.0 PHY driverVivek Gautam2014-05-13
| | | | | | | | | | | | | Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. Also, created a new header file in linux/mfd/syscon/ for Exynos5 SoCs and put the required PMU offset definitions for the basic available PHYs. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: exynos: fix building as a moduleArnd Bergmann2014-04-24
| | | | | | | | | | | | | | | The top-level phy-samsung-usb2 driver may be configured as a loadable module, which currently causes link errors because of the dependency on the exynos{5250,4x12,4210}_usb2_phy_config symbol. Solving this could be achieved by exporting these symbols, but as the SoC-specific parts of the driver are not currently built as modules, it seems better to just link everything into one module and avoid the need for the export. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Kamil Debski <k.debski@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* PHY: add APM X-Gene SoC 15Gbps Multi-purpose PHY driverLoc Ho2014-03-09
| | | | | | | | | | | | This patch adds support for the APM X-Gene SoC 15Gbps Multi-purpose PHY. This is the physical layer interface for the corresponding host controller. Currently, only external clock and Gen3 SATA mode are supported. Signed-off-by: Loc Ho <lho@apm.com> Signed-off-by: Tuan Phan <tphan@apm.com> Signed-off-by: Suman Tripathi <stripathi@apm.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: rename struct omap_control_usb to struct omap_control_phyKishon Vijay Abraham I2014-03-09
| | | | | | | | | | | Rename struct omap_control_usb to struct omap_control_phy since it can be used to control PHY of USB, SATA and PCIE. Also move the driver and include files under *phy* and made the corresponding changes in the users of phy-omap-control. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Felipe Balbi <balbi@ti.com>
* phy: Add Exynos 5250 support to the Exynos USB 2.0 PHY driverKamil Debski2014-03-08
| | | | | | | | Add support for Exynos 5250. This driver is to replace the old USB 2.0 PHY driver. Signed-off-by: Kamil Debski <k.debski@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* phy: Add new Exynos USB 2.0 PHY driverKamil Debski2014-03-08
| | | | | | | | | | Add a new driver for the Exynos USB 2.0 PHY. The new driver uses the generic PHY framework. The driver includes support for the Exynos 4x10 and 4x12 SoC families. Signed-off-by: Kamil Debski <k.debski@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* drivers: phy: usb3/pipe3: Adapt pipe3 driver to Generic PHY FrameworkKishon Vijay Abraham I2014-03-06
| | | | | | | | | Adapted omap-usb3 PHY driver to Generic PHY Framework and moved phy-omap-usb3 driver in drivers/usb/phy to drivers/phy and also renamed the file to phy-ti-pipe3 since this same driver will be used for SATA PHY and PCIE PHY. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* PHY: sunxi: Add driver for sunxi usb phyHans de Goede2014-03-03
| | | | | | | | | | | | The Allwinner A1x / A2x SoCs have 2 or 3 usb phys which are all accessed through a single set of registers. Besides this there are also some other phy related bits which need poking, which are per phy, but shared between the ohci and ehci controllers, so these are also controlled from this new phy driver. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* PHY: Exynos: Add Exynos5250 SATA PHY driverYuvaraj Kumar C D2014-03-03
| | | | | | | | | | | | This patch adds the SATA PHY driver for Exynos5250.This driver uses the generic PHY framework to deal with SATA PHY.Exynos5250 SATA PHY comprises of CMU and TRSV blocks which are of I2C register Map.So this driver configures the CMU and TRSV block of exynos5250 SATA PHY using i2c. Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com> Signed-off-by: Girish K S <ks.giri@samsung.com> Signed-off-by: Vasanth Ananthan <vasanth.a@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-26 09:54:43 +0000