summaryrefslogtreecommitdiff
path: root/drivers/irqchip/Makefile (follow)
Commit message (Collapse)AuthorAge
* Merge android-4.4.116 (20ddb25) into msm-4.4Srinivasarao P2018-03-01
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * refs/heads/tmp-20ddb25 Linux 4.4.116 ftrace: Remove incorrect setting of glob search field mn10300/misalignment: Use SIGSEGV SEGV_MAPERR to report a failed user copy ovl: fix failure to fsync lower dir ACPI: sbshc: remove raw pointer from printk() message nvme: Fix managing degraded controllers btrfs: Handle btrfs_set_extent_delalloc failure in fixup worker pktcdvd: Fix pkt_setup_dev() error path EDAC, octeon: Fix an uninitialized variable warning xtensa: fix futex_atomic_cmpxchg_inatomic alpha: fix reboot on Avanti platform alpha: fix crash if pthread_create races with signal delivery signal/sh: Ensure si_signo is initialized in do_divide_error signal/openrisc: Fix do_unaligned_access to send the proper signal Bluetooth: btusb: Restore QCA Rome suspend/resume fix with a "rewritten" version Revert "Bluetooth: btusb: fix QCA Rome suspend/resume" Bluetooth: btsdio: Do not bind to non-removable BCM43341 HID: quirks: Fix keyboard + touchpad on Toshiba Click Mini not working kernel/async.c: revert "async: simplify lowest_in_progress()" media: cxusb, dib0700: ignore XC2028_I2C_FLUSH media: ts2020: avoid integer overflows on 32 bit machines watchdog: imx2_wdt: restore previous timeout after suspend+resume KVM: nVMX: Fix races when sending nested PI while dest enters/leaves L2 arm: KVM: Fix SMCCC handling of unimplemented SMC/HVC calls crypto: caam - fix endless loop when DECO acquire fails media: v4l2-compat-ioctl32.c: refactor compat ioctl32 logic media: v4l2-compat-ioctl32.c: don't copy back the result for certain errors media: v4l2-compat-ioctl32.c: drop pr_info for unknown buffer type media: v4l2-compat-ioctl32.c: copy clip list in put_v4l2_window32 media: v4l2-compat-ioctl32: Copy v4l2_window->global_alpha media: v4l2-compat-ioctl32.c: make ctrl_is_pointer work for subdevs media: v4l2-compat-ioctl32.c: fix ctrl_is_pointer media: v4l2-compat-ioctl32.c: copy m.userptr in put_v4l2_plane32 media: v4l2-compat-ioctl32.c: avoid sizeof(type) media: v4l2-compat-ioctl32.c: move 'helper' functions to __get/put_v4l2_format32 media: v4l2-compat-ioctl32.c: fix the indentation media: v4l2-compat-ioctl32.c: add missing VIDIOC_PREPARE_BUF vb2: V4L2_BUF_FLAG_DONE is set after DQBUF media: v4l2-ioctl.c: don't copy back the result for -ENOTTY nsfs: mark dentry with DCACHE_RCUACCESS crypto: poly1305 - remove ->setkey() method crypto: cryptd - pass through absence of ->setkey() crypto: hash - introduce crypto_hash_alg_has_setkey() ahci: Add Intel Cannon Lake PCH-H PCI ID ahci: Add PCI ids for Intel Bay Trail, Cherry Trail and Apollo Lake AHCI ahci: Annotate PCI ids for mobile Intel chipsets as such kernfs: fix regression in kernfs_fop_write caused by wrong type NFS: reject request for id_legacy key without auxdata NFS: commit direct writes even if they fail partially NFS: Add a cond_resched() to nfs_commit_release_pages() nfs/pnfs: fix nfs_direct_req ref leak when i/o falls back to the mds ubi: block: Fix locking for idr_alloc/idr_remove mtd: nand: sunxi: Fix ECC strength choice mtd: nand: Fix nand_do_read_oob() return value mtd: nand: brcmnand: Disable prefetch by default mtd: cfi: convert inline functions to macros media: dvb-usb-v2: lmedm04: move ts2020 attach to dm04_lme2510_tuner media: dvb-usb-v2: lmedm04: Improve logic checking of warm start dccp: CVE-2017-8824: use-after-free in DCCP code sched/rt: Up the root domain ref count when passing it around via IPIs sched/rt: Use container_of() to get root domain in rto_push_irq_work_func() usb: gadget: uvc: Missing files for configfs interface posix-timer: Properly check sigevent->sigev_notify netfilter: nf_queue: Make the queue_handler pernet kaiser: fix compile error without vsyscall x86/kaiser: fix build error with KASAN && !FUNCTION_GRAPH_TRACER dmaengine: dmatest: fix container_of member in dmatest_callback CIFS: zero sensitive data when freeing cifs: Fix autonegotiate security settings mismatch cifs: Fix missing put_xid in cifs_file_strict_mmap powerpc/pseries: include linux/types.h in asm/hvcall.h x86/microcode: Do the family check first x86/microcode/AMD: Do not load when running on a hypervisor crypto: tcrypt - fix S/G table for test_aead_speed() don't put symlink bodies in pagecache into highmem KEYS: encrypted: fix buffer overread in valid_master_desc() media: soc_camera: soc_scale_crop: add missing MODULE_DESCRIPTION/AUTHOR/LICENSE vhost_net: stop device during reset owner tcp: release sk_frag.page in tcp_disconnect r8169: fix RTL8168EP take too long to complete driver initialization. qlcnic: fix deadlock bug net: igmp: add a missing rcu locking section ip6mr: fix stale iterator x86/asm: Fix inline asm call constraints for GCC 4.4 drm: rcar-du: Fix race condition when disabling planes at CRTC stop drm: rcar-du: Use the VBK interrupt for vblank events ASoC: rsnd: avoid duplicate free_irq() ASoC: rsnd: don't call free_irq() on Parent SSI ASoC: simple-card: Fix misleading error message net: cdc_ncm: initialize drvflags before usage usbip: fix 3eee23c3ec14 tcp_socket address still in the status file usbip: vhci_hcd: clear just the USB_PORT_STAT_POWER bit ASoC: pcm512x: add missing MODULE_DESCRIPTION/AUTHOR/LICENSE powerpc/64s: Allow control of RFI flush via debugfs powerpc/64s: Wire up cpu_show_meltdown() powerpc/powernv: Check device-tree for RFI flush settings powerpc/pseries: Query hypervisor for RFI flush settings powerpc/64s: Support disabling RFI flush with no_rfi_flush and nopti powerpc/64s: Add support for RFI flush of L1-D cache powerpc/64s: Convert slb_miss_common to use RFI_TO_USER/KERNEL powerpc/64: Convert the syscall exit path to use RFI_TO_USER/KERNEL powerpc/64: Convert fast_exception_return to use RFI_TO_USER/KERNEL powerpc/64s: Simple RFI macro conversions powerpc/64: Add macros for annotating the destination of rfid/hrfid powerpc/pseries: Add H_GET_CPU_CHARACTERISTICS flags & wrapper powerpc: Simplify module TOC handling powerpc: Fix VSX enabling/flushing to also test MSR_FP and MSR_VEC powerpc/64: Fix flush_(d|i)cache_range() called from modules powerpc/bpf/jit: Disable classic BPF JIT on ppc64le BACKPORT: xfrm: Fix return value check of copy_sec_ctx. time: Fix ktime_get_raw() incorrect base accumulation sched/fair: prevent possible infinite loop in sched_group_energy UPSTREAM: MIPS: Fix build of compressed image ANDROID: qtaguid: Fix the UAF probelm with tag_ref_tree UPSTREAM: ANDROID: binder: remove waitqueue when thread exits. UPSTREAM: arm64/efi: Make strnlen() available to the EFI namespace UPSTREAM: ARM: boot: Add an implementation of strnlen for libfdt ANDROID: MIPS: Add ranchu[32r5|32r6|64]_defconfig FROMLIST: tty: goldfish: Enable 'earlycon' only if built-in FROMLIST: MIPS: ranchu: Add Ranchu as a new generic-based board FROMLIST: MIPS: Add noexec=on|off kernel parameter FROMLIST: MIPS: CPC: Map registers using DT in mips_cpc_default_phys_base() FROMLIST: dt-bindings: Document mti,mips-cpc binding FROMLIST: MIPS: math-emu: Mark fall throughs in switch statements with a comment FROMLIST: MIPS: math-emu: Avoid multiple assignment FROMLIST: MIPS: math-emu: Avoid an assignment within if statement condition FROMLIST: MIPS: math-emu: Declare function srl128() as static FROMLIST: MIPS: math-emu: Avoid definition duplication for macro DPXMULT() FROMLIST: MIPS: math-emu: Remove an unnecessary header inclusion UPSTREAM: scripts/dtc: Update to upstream version 0931cea3ba20 UPSTREAM: scripts/dtc: dt_to_config - kernel config options for a devicetree UPSTREAM: scripts/dtc: Update to upstream version 53bf130b1cdd UPSTREAM: scripts/dtc: Update to upstream commit b06e55c88b9b UPSTREAM: scripts/dtc: dtx_diff - add info to error message UPSTREAM: dtc: create tool to diff device trees UPSTREAM: config: android-base: disable CONFIG_NFSD and CONFIG_NFS_FS UPSTREAM: config: android-base: add CGROUP_BPF UPSTREAM: config: android-base: add CONFIG_MODULES option UPSTREAM: config: android-base: add CONFIG_IKCONFIG option UPSTREAM: config: android-base: disable CONFIG_USELIB and CONFIG_FHANDLE UPSTREAM: config: android-base: enable hardened usercopy and kernel ASLR UPSTREAM: config: android: enable CONFIG_SECCOMP UPSTREAM: config: android: set SELinux as default security mode UPSTREAM: config: android: move device mapper options to recommended UPSTREAM: config/android: Remove CONFIG_IPV6_PRIVACY UPSTREAM: config: add android config fragments BACKPORT: MIPS: generic: Add a MAINTAINERS entry BACKPORT: irqchip/irq-goldfish-pic: Add Goldfish PIC driver UPSTREAM: dt-bindings/goldfish-pic: Add device tree binding for Goldfish PIC driver UPSTREAM: MIPS: Allow storing pgd in C0_CONTEXT for MIPSr6 UPSTREAM: MIPS: CPS: Handle spurious VP starts more gracefully UPSTREAM: MIPS: CPS: Handle cores not powering down more gracefully UPSTREAM: MIPS: CPS: Prevent multi-core with dcache aliasing UPSTREAM: MIPS: CPS: Select CONFIG_SYS_SUPPORTS_SCHED_SMT for MIPSr6 UPSTREAM: MIPS: CM: WARN on attempt to lock invalid VP, not BUG UPSTREAM: MIPS: CM: Avoid per-core locking with CM3 & higher UPSTREAM: MIPS: smp-cps: Avoid BUG() when offlining pre-r6 CPUs UPSTREAM: MIPS: smp-cps: Add support for CPU hotplug of MIPSr6 processors UPSTREAM: MIPS: generic: Bump default NR_CPUS to 16 UPSTREAM: MIPS: pm-cps: Change FSB workaround to CPU blacklist UPSTREAM: MIPS: Fix early CM probing UPSTREAM: MIPS: smp-cps: Stop printing EJTAG exceptions to UART UPSTREAM: MIPS: smp-cps: Add nothreads kernel parameter UPSTREAM: MIPS: smp-cps: Support MIPSr6 Virtual Processors UPSTREAM: MIPS: smp-cps: Skip core setup if coherent UPSTREAM: MIPS: smp-cps: Pull boot config retrieval out of mips_cps_boot_vpes UPSTREAM: MIPS: smp-cps: Pull cache init into a function UPSTREAM: MIPS: smp-cps: Ensure our VP ident calculation is correct UPSTREAM: irqchip: mips-gic: Provide VP ID accessor UPSTREAM: irqchip: mips-gic: Use HW IDs for VPE_OTHER_ADDR UPSTREAM: MIPS: CM: Fix mips_cm_max_vp_width for UP kernels UPSTREAM: MIPS: CM: Add CM GCR_BEV_BASE accessors UPSTREAM: MIPS: CPC: Add start, stop and running CM3 CPC registers UPSTREAM: MIPS: pm-cps: Avoid offset overflow on MIPSr6 UPSTREAM: MIPS: traps: Make sure secondary cores have a sane ebase register UPSTREAM: MIPS: Detect MIPSr6 Virtual Processor support UPSTREAM: Documentation: Add device tree binding for Goldfish FB driver UPSTREAM: MIPS: math-emu: Use preferred flavor of unsigned integer declarations UPSTREAM: MIPS: math-emu: <MADDF|MSUBF>.D: Fix accuracy (64-bit case) UPSTREAM: MIPS: math-emu: <MADDF|MSUBF>.S: Fix accuracy (32-bit case) UPSTREAM: MIPS: Update Goldfish RTC driver maintainer email address UPSTREAM: MIPS: Update RINT emulation maintainer email address UPSTREAM: MIPS: math-emu: do not use bools for arithmetic UPSTREAM: rtc: goldfish: Add RTC driver for Android emulator BACKPORT: dt-bindings: Add device tree binding for Goldfish RTC driver UPSTREAM: tty: goldfish: Implement support for kernel 'earlycon' parameter UPSTREAM: tty: goldfish: Use streaming DMA for r/w operations on Ranchu platforms UPSTREAM: tty: goldfish: Refactor constants to better reflect their nature UPSTREAM: MIPS: math-emu: Add FP emu debugfs stats for individual instructions UPSTREAM: MIPS: math-emu: Add FP emu debugfs clear functionality UPSTREAM: MIPS: math-emu: Add FP emu debugfs statistics for branches BACKPORT: MIPS: math-emu: CLASS.D: Zero bits 32-63 of the result BACKPORT: MIPS: math-emu: RINT.<D|S>: Fix several problems by reimplementation UPSTREAM: MIPS: math-emu: CMP.Sxxx.<D|S>: Prevent occurrences of SIGILL crashes UPSTREAM: MIPS: math-emu: <MADDF|MSUBF>.<D|S>: Clean up "maddf_flags" enumeration UPSTREAM: MIPS: math-emu: <MADDF|MSUBF>.<D|S>: Fix some cases of zero inputs UPSTREAM: MIPS: math-emu: <MADDF|MSUBF>.<D|S>: Fix some cases of infinite inputs UPSTREAM: MIPS: math-emu: <MADDF|MSUBF>.<D|S>: Fix NaN propagation UPSTREAM: tty: goldfish: Fix a parameter of a call to free_irq UPSTREAM: MIPS: VDSO: Fix clobber lists in fallback code paths UPSTREAM: MIPS: VDSO: Fix a mismatch between comment and preprocessor constant UPSTREAM: MIPS: VDSO: Add implementation of gettimeofday() fallback UPSTREAM: MIPS: VDSO: Add implementation of clock_gettime() fallback UPSTREAM: MIPS: VDSO: Fix conversions in do_monotonic()/do_monotonic_coarse() UPSTREAM: MIPS: unaligned: Add DSP lwx & lhx missaligned access support UPSTREAM: MIPS: build: Fix "-modd-spreg" switch usage when compiling for mips32r6 UPSTREAM: MIPS: cmdline: Add support for 'memmap' parameter UPSTREAM: MIPS: math-emu: Handle zero accumulator case in MADDF and MSUBF separately UPSTREAM: MIPS: Support per-device DMA coherence UPSTREAM: MIPS: dma-default: Don't check hw_coherentio if device is non-coherent UPSTREAM: MIPS: Sanitise coherentio semantics UPSTREAM: MIPS: CPC: Provide default mips_cpc_default_phys_base to ignore CPC UPSTREAM: MIPS: generic: Introduce generic DT-based board support UPSTREAM: MIPS: Support generating Flattened Image Trees (.itb) UPSTREAM: MIPS: Allow emulation for unaligned [LS]DXC1 instructions UPSTREAM: MIPS: math-emu: Fix BC1EQZ and BC1NEZ condition handling UPSTREAM: MIPS: r2-on-r6-emu: Clear BLTZALL and BGEZALL debugfs counters UPSTREAM: MIPS: r2-on-r6-emu: Fix BLEZL and BGTZL identification UPSTREAM: MIPS: remove aliasing alignment if HW has antialising support BACKPORT: MIPS: store the appended dtb address in a variable UPSTREAM: MIPS: Fix FCSR Cause bit handling for correct SIGFPE issue UPSTREAM: MIPS: kernel: Audit and remove any unnecessary uses of module.h UPSTREAM: MIPS: c-r4k: Fix sigtramp SMP call to use kmap UPSTREAM: MIPS: c-r4k: Fix protected_writeback_scache_line for EVA UPSTREAM: MIPS: Spelling fix lets -> let's UPSTREAM: MIPS: R6: Fix typo UPSTREAM: MIPS: traps: Correct the SIGTRAP debug ABI in `do_watch' and `do_trap_or_bp' UPSTREAM: MIPS: inst.h: Rename cbcond{0,1}_op to pop{1,3}0_op UPSTREAM: MIPS: inst.h: Rename b{eq,ne}zcji[al]c_op to pop{6,7}6_op UPSTREAM: MIPS: math-emu: Fix m{add,sub}.s shifts UPSTREAM: MIPS: inst: Declare fsel_op for sel.fmt instruction UPSTREAM: MIPS: math-emu: Fix code indentation UPSTREAM: MIPS: math-emu: Fix bit-width in ieee754dp_{mul, maddf, msubf} comments UPSTREAM: MIPS: math-emu: Add z argument macros UPSTREAM: MIPS: math-emu: Unify ieee754dp_m{add,sub}f UPSTREAM: MIPS: math-emu: Unify ieee754sp_m{add,sub}f UPSTREAM: MIPS: math-emu: Emulate MIPSr6 sel.fmt instruction UPSTREAM: MIPS: math-emu: Fix BC1{EQ,NE}Z emulation UPSTREAM: MIPS: math-emu: Always propagate sNaN payload in quieting UPSTREAM: MIPS: Fix misspellings in comments. UPSTREAM: MIPS: math-emu: Add IEEE Std 754-2008 NaN encoding emulation UPSTREAM: MIPS: math-emu: Add IEEE Std 754-2008 ABS.fmt and NEG.fmt emulation UPSTREAM: MIPS: non-exec stack & heap when non-exec PT_GNU_STACK is present UPSTREAM: MIPS: Add IEEE Std 754 conformance mode selection UPSTREAM: MIPS: Determine the presence of IEEE Std 754-2008 features UPSTREAM: MIPS: Define the legacy-NaN and 2008-NaN features UPSTREAM: MIPS: ELF: Interpret the NAN2008 file header flag UPSTREAM: ELF: Also pass any interpreter's file header to `arch_check_elf' UPSTREAM: MIPS: Use a union to access the ELF file header UPSTREAM: MIPS: Fix delay slot emulation count in debugfs BACKPORT: exit_thread: accept a task parameter to be exited UPSTREAM: mn10300: let exit_fpu accept a task UPSTREAM: MIPS: Use per-mm page to execute branch delay slot instructions BACKPORT: s390: get rid of exit_thread() BACKPORT: exit_thread: remove empty bodies UPSTREAM: MIPS: Make flush_thread UPSTREAM: MIPS: Properly disable FPU in start_thread() UPSTREAM: MIPS: Select CONFIG_HANDLE_DOMAIN_IRQ and make it work. UPSTREAM: MIPS: math-emu: Fix typo UPSTREAM: MIPS: math-emu: dsemul: Remove an unused bit in ADDIUPC emulation UPSTREAM: MIPS: math-emu: dsemul: Reduce `get_isa16_mode' clutter UPSTREAM: MIPS: math-emu: dsemul: Correct description of the emulation frame UPSTREAM: MIPS: math-emu: Correct the emulation of microMIPS ADDIUPC instruction UPSTREAM: MIPS: math-emu: Make microMIPS branch delay slot emulation work UPSTREAM: MIPS: math-emu: dsemul: Fix ill formatting of microMIPS part UPSTREAM: MIPS: math-emu: Correctly handle NOP emulation Conflicts: drivers/irqchip/Kconfig drivers/irqchip/Makefile drivers/media/v4l2-core/v4l2-compat-ioctl32.c Change-Id: I98374358ab24ce80dba3afa2f4562c71f45b7aab Signed-off-by: Srinivasarao P <spathi@codeaurora.org>
| * BACKPORT: irqchip/irq-goldfish-pic: Add Goldfish PIC driverMiodrag Dinic2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add device driver for a virtual programmable interrupt controller The virtual PIC is designed as a device tree-based interrupt controller. The compatible string used by OS for binding the driver is "google,goldfish-pic". Signed-off-by: Miodrag Dinic <miodrag.dinic@mips.com> Signed-off-by: Goran Ferenc <goran.ferenc@mips.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@mips.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> (cherry picked from commit 4235ff50cf98dd42ba15175687570f9f03e124a1) Conflicts: drivers/irqchip/Kconfig drivers/irqchip/Makefile drivers/irqchip/irq-goldfish-pic.c Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | irqchip: add snapshot of msm_show_resume_irqAbhimanyu Kapur2016-06-29
| | | | | | | | | | | | | | | | | | | | | | This is a snapshot of drivers/irqchip/msm_show_resume_irq.c as of msm-3.18 commit <e17a72ad7344065> ("Merge "ARM: dts: mdm: Adjust memory region peripheral1_mem for MDM9640""). CRs-Fixed: 1033023 Change-Id: Ia928cf5e23eebc7a0f80638f4be81beec7ed2878 Signed-off-by: Runmin Wang <runminw@codeaurora.org> Signed-off-by: Kyle Yan <kyan@codeaurora.org>
* | irqchip: irq-msm: Delete irq-msm.cTrilok Soni2016-05-05
| | | | | | | | | | | | | | | | | | | | There is no need of irq-msm.c since the users of this file have moved their callbacks to the respective file (like wcdxxx) and starting 4.4 we don't use the USE_PINCTRL_IRQ. CRs-Fixed: 1007342 Change-Id: I9016aadac88483c8547ed1a40cb6c55909f347cf Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
* | irqchip: msm: Add snaphot of msm irq driverAbhimanyu Kapur2016-03-22
|/ | | | | | | | | | | | | | | Snapshot the msm irq driver as of msm-3.14 commit: 3bc54cf86bdc7affa7cd4bf7faa3c57fe8f8819d (Merge "msm: camera: Add dummy sub module in sensor pipeline") Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org> Conflicts: drivers/irqchip/Kconfig drivers/irqchip/Makefile Change-Id: Idf5284906af960fe03dcf881df1b57149c8e6ad8
* irqchip/mxs: Add Alphascale ASM9260 supportOleksij Rempel2015-10-14
| | | | | | | | | | | | | | | | | | | | Freescale iMX23/iMX28 and Alphascale ASM9260 have similar interrupt collectors. We already prepared the mxs driver to handle a different register layout. Add the actual ASM9260 support. Differences between these devices: - Different register offsets - Different count of interupt lines per register - ASM9260 does not provide reset bit - ASM9260 does not support FIQ. Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Tested-by: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: marc.zyngier@arm.com Cc: jason@lakedaemon.net Link: http://lkml.kernel.org/r/1444677334-12242-6-git-send-email-linux@rempel-privat.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* irqchip/imx-gpcv2: IMX GPCv2 driver for wakeup sourcesShenwei Wang2015-08-24
| | | | | | | | | | | | | | | | | | | | IMX7D contains a new version of GPC IP block (GPCv2). It has two major functions: power management and wakeup source management. When the system is in WFI (wait for interrupt) mode, the GPC block will be the first block on the platform to be activated and signaled. In normal wait mode during cpu idle, the system can be woken up by any enabled interrupts. In standby or suspend mode, the system can only be wokem up by the pre-defined wakeup sources. Based-on-patch-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shenwei Wang <shenwei.wang@freescale.com> Cc: <linux-arm-kernel@lists.infradead.org> Cc: <shawn.guo@linaro.org> Cc: <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/1440443055-7291-1-git-send-email-shenwei.wang@freescale.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* irqchip: Add bcm2836 interrupt controller for Raspberry Pi 2Eric Anholt2015-08-20
| | | | | | | | | | | | | | | | | | | This interrupt controller is the new root interrupt controller with the timer, PMU events, and IPIs, and the bcm2835's interrupt controller is chained off of it to handle the peripherals. I wrote the interrupt chip support, while Andrea Merello wrote the IPI code. Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Cc: linux-rpi-kernel@lists.infradead.org Cc: Lee Jones <lee@kernel.org> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/1438902033-31477-5-git-send-email-eric@anholt.net Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* MIPS/irqchip: Move i8259 irqchip driver to drivers/irqchipRalf Baechle2015-07-31
| | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* irqchip/gicv3-its: Add platform MSI supportMarc Zyngier2015-07-30
| | | | | | | | | | | | | | | | | | | | In order to support non-PCI MSI with the GICv3 ITS, add the minimal required entry points for the MSI domain (an msi_prepare implementation). The rest is only boilerplate code to find the raw ITS domain. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Cc: <linux-arm-kernel@lists.infradead.org> Cc: Yijing Wang <wangyijing@huawei.com> Cc: Ma Jun <majun258@huawei.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Duc Dang <dhdang@apm.com> Cc: Hanjun Guo <hanjun.guo@linaro.org> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: Jason Cooper <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/1438091186-10244-16-git-send-email-marc.zyngier@arm.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* irqchip/gicv3-its: Split PCI/MSI code from the core ITS driverMarc Zyngier2015-07-30
| | | | | | | | | | | | | | | | | | | | | | | | | | It is becoming obvious that having the PCI/MSI code in the same file as the the core ITS code is giving people implementing non-PCI MSI support the wrong kind of idea. In order to make things a bit clearer, let's move the PCI/MSI code out to its own file. Hopefully it will make it clear that whoever thinks of hooking into the core ITS better have a very strong point. We use a temporary entry point that will get removed in a subsequent patch, once the proper infrastructure is added. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Cc: <linux-arm-kernel@lists.infradead.org> Cc: Yijing Wang <wangyijing@huawei.com> Cc: Ma Jun <majun258@huawei.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Duc Dang <dhdang@apm.com> Cc: Hanjun Guo <hanjun.guo@linaro.org> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: Jason Cooper <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/1438091186-10244-12-git-send-email-marc.zyngier@arm.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2015-06-27
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: - Improvements to the tlb_dump code - KVM fixes - Add support for appended DTB - Minor improvements to the R12000 support - Minor improvements to the R12000 support - Various platform improvments for BCM47xx - The usual pile of minor cleanups - A number of BPF fixes and improvments - Some improvments to the support for R3000 and DECstations - Some improvments to the ATH79 platform support - A major patchset for the JZ4740 SOC adding support for the CI20 platform - Add support for the Pistachio SOC - Minor BMIPS/BCM63xx platform support improvments. - Avoid "SYNC 0" as memory barrier when unlocking spinlocks - Add support for the XWR-1750 board. - Paul's __cpuinit/__cpuinitdata cleanups. - New Malta CPU board support large memory so enable ZONE_DMA32. * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (131 commits) MIPS: spinlock: Adjust arch_spin_lock back-off time MIPS: asmmacro: Ensure 64-bit FP registers are used with MSA MIPS: BCM47xx: Simplify handling SPROM revisions MIPS: Cobalt Don't use module_init in non-modular MTD registration. MIPS: BCM47xx: Move NVRAM driver to the drivers/firmware/ MIPS: use for_each_sg() MIPS: BCM47xx: Don't select BCMA_HOST_PCI MIPS: BCM47xx: Add helper variable for storing NVRAM length MIPS: IRQ/IP27: Move IRQ allocation API to platform code. MIPS: Replace smp_mb with release barrier function in unlocks. MIPS: i8259: DT support MIPS: Malta: Basic DT plumbing MIPS: include errno.h for ENODEV in mips-cm.h MIPS: Define GCR_GIC_STATUS register fields MIPS: BPF: Introduce BPF ASM helpers MIPS: BPF: Use BPF register names to describe the ABI MIPS: BPF: Move register definition to the BPF header MIPS: net: BPF: Replace RSIZE with SZREG MIPS: BPF: Free up some callee-saved registers MIPS: Xtalk: Update xwidget.h with known Xtalk device numbers ...
| * MIPS/IRQCHIP: Move Ingenic SoC intc driver to drivers/irqchipPaul Burton2015-06-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the driver for Ingenic SoC interrupt controllers into drivers/irqchip where it belongs. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Brian Norris <computersforpeace@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/10147/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS/IRQCHIP: Move irq_chip from arch/mips to drivers/irqchip.Ralf Baechle2015-06-21
| | | | | | | | | | | | | | While at it, rename it because in drivers/irqchip no longer every CPU is a MIPS. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-armLinus Torvalds2015-06-26
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM updates from Russell King: "Bigger items included in this update are: - A series of updates from Arnd for ARM randconfig build failures - Updates from Dmitry for StrongARM SA-1100 to move IRQ handling to drivers/irqchip/ - Move ARMs SP804 timer to drivers/clocksource/ - Perf updates from Mark Rutland in preparation to move the ARM perf code into drivers/ so it can be shared with ARM64. - MCPM updates from Nicolas - Add support for taking platform serial number from DT - Re-implement Keystone2 physical address space switch to conform to architecture requirements - Clean up ARMv7 LPAE code, which goes in hand with the Keystone2 changes. - L2C cleanups to avoid unlocking caches if we're prevented by the secure support to unlock. - Avoid cleaning a potentially dirty cache containing stale data on CPU initialisation - Add ARM-only entry point for secondary startup (for machines that can only call into a Thumb kernel in ARM mode). Same thing is also done for the resume entry point. - Provide arch_irqs_disabled via asm-generic - Enlarge ARMv7M vector table - Always use BFD linker for VDSO, as gold doesn't accept some of the options we need. - Fix an incorrect BSYM (for Thumb symbols) usage, and convert all BSYM compiler macros to a "badr" (for branch address). - Shut up compiler warnings provoked by our cmpxchg() implementation. - Ensure bad xchg sizes fail to link" * 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (75 commits) ARM: Fix build if CLKDEV_LOOKUP is not configured ARM: fix new BSYM() usage introduced via for-arm-soc branch ARM: 8383/1: nommu: avoid deprecated source register on mov ARM: 8391/1: l2c: add options to overwrite prefetching behavior ARM: 8390/1: irqflags: Get arch_irqs_disabled from asm-generic ARM: 8387/1: arm/mm/dma-mapping.c: Add arm_coherent_dma_mmap ARM: 8388/1: tcm: Don't crash when TCM banks are protected by TrustZone ARM: 8384/1: VDSO: force use of BFD linker ARM: 8385/1: VDSO: group link options ARM: cmpxchg: avoid warnings from macro-ized cmpxchg() implementations ARM: remove __bad_xchg definition ARM: 8369/1: ARMv7M: define size of vector table for Vybrid ARM: 8382/1: clocksource: make ARM_TIMER_SP804 depend on GENERIC_SCHED_CLOCK ARM: 8366/1: move Dual-Timer SP804 driver to drivers/clocksource ARM: 8365/1: introduce sp804_timer_disable and remove arm_timer.h inclusion ARM: 8364/1: fix BE32 module loading ARM: 8360/1: add secondary_startup_arm prototype in header file ARM: 8359/1: correct secondary_startup_arm mode ARM: proc-v7: sanitise and document registers around errata ARM: proc-v7: clean up MIDR access ...
| * | ARM: 8368/1: sa1100: move irq driver to drivers/irqchip/Dmitry Eremin-Solenikov2015-05-28
| |/ | | | | | | | | | | | | | | Move current sa11x0 IRQ driver to the irqchip subsystem. Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* / h8300: IRQ chip driverYoshinori Sato2015-06-23
|/ | | | Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2015-04-17
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: "This is the main pull request for MIPS for Linux 4.1. Most noteworthy: - Add more Octeon-optimized crypto functions - Octeon crypto preemption and locking fixes - Little endian support for Octeon - Use correct CSR to soft reset Octeons - Support LEDs on the Octeon-based DSR-1000N - Fix PCI interrupt mapping for the Octeon-based DSR-1000N - Mark prom_free_prom_memory() as __init for a number of systems - Support for Imagination's Pistachio SOC. This includes arch and CLK bits. I'd like to merge pinctrl bits later - Improve parallelism of csum_partial for certain pipelines - Organize DTB files in subdirs like other architectures - Implement read_sched_clock for all MIPS platforms other than Octeon - Massive series of 38 fixes and cleanups for the FPU emulator / kernel - Further FPU remulator work to support new features. This sits on a separate branch which also has been pulled into the 4.1 KVM branch - Clean up and fixes for the SEAD3 eval board; remove unused file - Various updates for Netlogic platforms - A number of small updates for Loongson 3 platforms - Increase the memory limit for ATH79 platforms to 256MB - A fair number of fixes and updates for BCM47xx platforms - Finish the implementation of XPA support - MIPS FDC support. No, not floppy controller but Fast Debug Channel :) - Detect the R16000 used in SGI legacy platforms - Fix Kconfig dependencies for the SSB bus support" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (265 commits) MIPS: Makefile: Fix MIPS ASE detection code MIPS: asm: elf: Set O32 default FPU flags MIPS: BCM47XX: Fix detecting Microsoft MN-700 & Asus WL500G MIPS: Kconfig: Disable SMP/CPS for 64-bit MIPS: Hibernate: flush TLB entries earlier MIPS: smp-cps: cpu_set FPU mask if FPU present MIPS: lose_fpu(): Disable FPU when MSA enabled MIPS: ralink: add missing symbol for RALINK_ILL_ACC MIPS: ralink: Fix bad config symbol in PCI makefile. SSB: fix Kconfig dependencies MIPS: Malta: Detect and fix bad memsize values Revert "MIPS: Avoid pipeline stalls on some MIPS32R2 cores." MIPS: Octeon: Delete override of cpu_has_mips_r2_exec_hazard. MIPS: Fix cpu_has_mips_r2_exec_hazard. MIPS: kernel: entry.S: Set correct ISA level for mips_ihb MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case MIPS: r4kcache: Use correct base register for MIPS R6 cache flushes MIPS: Kconfig: Fix typo for the r2-to-r6 emulator kernel parameter MIPS: unaligned: Fix regular load/store instruction emulation for EVA MIPS: unaligned: Surround load/store macros in do {} while statements ...
| * IRQCHIP: Add new driver for BCM7038-style level 1 interrupt controllersKevin Cernekee2015-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the main peripheral IRQ controller on the BCM7xxx MIPS chips; it has the following characteristics: - 64 to 160+ level IRQs - Atomic set/clear registers - Reasonably predictable register layout (N status words, then N mask status words, then N mask set words, then N mask clear words) - SMP affinity supported on most systems - Typically connected to MIPS IRQ 2,3,2,3 on CPUs 0,1,2,3 This driver registers one IRQ domain and one IRQ chip to cover all instances of the block. Up to 4 instances of the block may appear, as it supports 4-way IRQ affinity on BCM7435. The same block exists on the ARM BCM7xxx chips, but typically the ARM GIC is used instead. So this driver is primarily intended for MIPS STB chips. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8844/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | Merge branch 'irqchip/stacked-tegra' into irqchip/coreJason Cooper2015-04-10
|\ \
| * | irqchip: tegra: Add DT-based support for legacy interrupt controllerMarc Zyngier2015-03-15
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra's LIC (Legacy Interrupt Controller) has been so far only supported as a weird extension of the GIC, which is not exactly pretty. The stacked IRQ domain framework fits this pretty well, and allows the LIC code to be turned into a standalone irqchip. In the process, make the driver DT aware, something that was sorely missing from the mach-tegra implementation. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1426088583-15097-3-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | Merge branch 'irqchip/vybrid' into irqchip/coreJason Cooper2015-03-15
|\ \
| * | irqchip: vf610-mscm-ir: Add support for Vybrid MSCM interrupt routerStefan Agner2015-03-08
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for Vybrid's interrupt router. On VF6xx models, almost all peripherals can be used by either of the two CPU's, the Cortex-A5 or the Cortex-M4. The interrupt router routes the peripheral interrupts to the configured CPU. This IRQ chip driver configures the interrupt router to route the requested interrupt to the CPU the kernel is running on. The driver makes use of the irqdomain hierarchy support. The parent is given by the device tree. This should be one of the two possible parents either ARM GIC or the ARM NVIC interrupt controller. The latter is currently not yet supported. Note that there is no resource control mechnism implemented to avoid concurrent access of the same peripheral. The user needs to make sure to use device trees which assign the peripherals orthogonally. However, this driver warns the user in case the interrupt is already configured for the other CPU. This provides a poor man's resource controller. Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Link: https://lkml.kernel.org/r/1425249689-32354-2-git-send-email-stefan@agner.ch Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* / irqchip: st: Supply new driver for STi based devicesLee Jones2015-03-03
|/ | | | | | | | | | This driver is used to enable System Configuration Register controlled External, CTI (Core Sight), PMU (Performance Management), and PL310 L2 Cache IRQs prior to use. Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lkml.kernel.org/r/1424272444-16230-3-git-send-email-lee.jones@linaro.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* irqchip: Conexant CX92755 interrupts controller driverBaruch Siach2015-01-26
| | | | | | | | | | | | | | | Add interrupt controller driver to the Conexant CX92755 SoC, part of the Digicolor SoCs series. Use the generic irq framework support. Use syscon to access the system global UC_IRQ_CONTROL register. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Cc: linux-arm-kernel@lists.infradead.org Cc: Arnd Bergmann <arnd@arndb.de> Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/5b769e3c23dfa5fde08c4f3bc966c2c2b3921d8a.1421317616.git.baruch@tkos.co.il Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* Merge branch 'irq-irqdomain-arm-for-linus' of ↵Linus Torvalds2014-12-15
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq domain ARM updates from Thomas Gleixner: "This set of changes make use of hierarchical irqdomains to provide: - MSI/ITS support for GICv3 - MSI support for GICv2m - Interrupt polarity extender for GICv1 Marc has come more cleanups for the existing extension hooks of GIC in the pipeline, but they are going to be 3.20 material" * 'irq-irqdomain-arm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (22 commits) irqchip: gicv3-its: Fix ITT allocation irqchip: gicv3-its: Move some alloc/free code to activate/deactivate irqchip: gicv3-its: Fix domain free in multi-MSI case irqchip: gic: Remove warning by including linux/irqdomain.h irqchip: gic-v2m: Add DT bindings for GICv2m irqchip: gic-v2m: Add support for ARM GICv2m MSI(-X) doorbell irqchip: mtk-sysirq: dt-bindings: Add bindings for mediatek sysirq irqchip: mtk-sysirq: Add sysirq interrupt polarity support irqchip: gic: Support hierarchy irq domain. irqchip: GICv3: Binding updates for ITS irqchip: GICv3: ITS: enable compilation of the ITS driver irqchip: GICv3: ITS: plug ITS init into main GICv3 code irqchip: GICv3: ITS: DT probing and initialization irqchip: GICv3: ITS: MSI support irqchip: GICv3: ITS: device allocation and configuration irqchip: GICv3: ITS: tables allocators irqchip: GICv3: ITS: LPI allocator irqchip: GICv3: ITS: irqchip implementation irqchip: GICv3: ITS command queue irqchip: GICv3: rework redistributor structure ...
| * irqchip: gic-v2m: Add support for ARM GICv2m MSI(-X) doorbellSuravee Suthikulpanit2014-11-26
| | | | | | | | | | | | | | | | | | | | | | | | | | ARM GICv2m specification extends GICv2 to support MSI(-X) with a new register frame. This allows a GICv2 based system to support MSI with minimal changes. Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> [maz: converted the driver to use stacked irq domains, updated changelog] Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416941243-7181-2-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * irqchip: mtk-sysirq: Add sysirq interrupt polarity supportYingjoe Chen2014-11-26
| | | | | | | | | | | | | | | | | | | | Mediatek SoCs have interrupt polarity support in sysirq which allows to invert polarity for given interrupt. Add this support using hierarchy irq domain. Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Link: https://lkml.kernel.org/r/1416902662-19281-3-git-send-email-yingjoe.chen@mediatek.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * irqchip: GICv3: ITS: enable compilation of the ITS driverMarc Zyngier2014-11-26
| | | | | | | | | | | | | | | | Get the show on the road... Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-13-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2014-12-11
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: "This is an unusually large pull request for MIPS - in parts because lots of patches missed the 3.18 deadline but primarily because some folks opened the flood gates. - Retire the MIPS-specific phys_t with the generic phys_addr_t. - Improvments for the backtrace code used by oprofile. - Better backtraces on SMP systems. - Cleanups for the Octeon platform code. - Cleanups and fixes for the Loongson platform code. - Cleanups and fixes to the firmware library. - Switch ATH79 platform to use the firmware library. - Grand overhault to the SEAD3 and Malta interrupt code. - Move the GIC interrupt code to drivers/irqchip - Lots of GIC cleanups and updates to the GIC code to use modern IRQ infrastructures and features of the kernel. - OF documentation updates for the GIC bindings - Move GIC clocksource driver to drivers/clocksource - Merge GIC clocksource driver with clockevent driver. - Further updates to bring the GIC clocksource driver up to date. - R3000 TLB code cleanups - Improvments to the Loongson 3 platform code. - Convert pr_warning to pr_warn. - Merge a bunch of small lantiq and ralink fixes that have been staged/lingering inside the openwrt tree for a while. - Update archhelp for IP22/IP32 - Fix a number of issues for Loongson 1B. - New clocksource and clockevent driver for Loongson 1B. - Further work on clk handling for Loongson 1B. - Platform work for Broadcom BMIPS. - Error handling cleanups for TurboChannel. - Fixes and optimization to the microMIPS support. - Option to disable the FTLB. - Dump more relevant information on machine check exception - Change binfmt to allow arch to examine PT_*PROC headers - Support for new style FPU register model in O32 - VDSO randomization. - BCM47xx cleanups - BCM47xx reimplement the way the kernel accesses NVRAM information. - Random cleanups - Add support for ATH25 platforms - Remove pointless locking code in some PCI platforms. - Some improvments to EVA support - Minor Alchemy cleanup" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (185 commits) MIPS: Add MFHC0 and MTHC0 instructions to uasm. MIPS: Cosmetic cleanups of page table headers. MIPS: Add CP0 macros for extended EntryLo registers MIPS: Remove now unused definition of phys_t. MIPS: Replace use of phys_t with phys_addr_t. MIPS: Replace MIPS-specific 64BIT_PHYS_ADDR with generic PHYS_ADDR_T_64BIT PCMCIA: Alchemy Don't select 64BIT_PHYS_ADDR in Kconfig. MIPS: lib: memset: Clean up some MIPS{EL,EB} ifdefery MIPS: iomap: Use __mem_{read,write}{b,w,l} for MMIO MIPS: <asm/types.h> fix indentation. MAINTAINERS: Add entry for BMIPS multiplatform kernel MIPS: Enable VDSO randomization MIPS: Remove a temporary hack for debugging cache flushes in SMTC configuration MIPS: Remove declaration of obsolete arch_init_clk_ops() MIPS: atomic.h: Reformat to fit in 79 columns MIPS: Apply `.insn' to fixup labels throughout MIPS: Fix microMIPS LL/SC immediate offsets MIPS: Kconfig: Only allow 32-bit microMIPS builds MIPS: signal.c: Fix an invalid cast in ISA mode bit handling MIPS: mm: Only build one microassembler that is suitable ...
| * | MIPS: Move GIC to drivers/irqchip/Andrew Bresticker2014-11-24
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move GIC irqchip support to drivers/irqchip/ and rename the Kconfig option from IRQ_GIC to MIPS_GIC to avoid confusion with the ARM GIC. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7812/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* / irqchip: bcm7120-l2: Decouple driver from brcmstb-l2Kevin Cernekee2014-11-09
|/ | | | | | | | | | | | Some chips, such as BCM6328, only require bcm7120-l2. Some BCM7xxx STB configurations only require brcmstb-l2. Treat them as two separate entities, and update the mach-bcm dependencies to reflect the change. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lkml.kernel.org/r/1415342669-30640-13-git-send-email-cernekee@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* Merge branch 'irq-core-for-linus' of ↵Linus Torvalds2014-10-09
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq updates from Thomas Gleixner: "The irq departement delivers: - a cleanup series to get rid of mindlessly copied code. - another bunch of new pointlessly different interrupt chip drivers. Adding homebrewn irq chips (and timers) to SoCs must provide a value add which is beyond the imagination of mere mortals. - the usual SoC irq controller updates, IOW my second cat herding project" * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (44 commits) irqchip: gic-v3: Implement CPU PM notifier irqchip: gic-v3: Refactor gic_enable_redist to support both enabling and disabling irqchip: renesas-intc-irqpin: Add minimal runtime PM support irqchip: renesas-intc-irqpin: Add helper variable dev = &pdev->dev irqchip: atmel-aic5: Add sama5d4 support irqchip: atmel-aic5: The sama5d3 has 48 IRQs Documentation: bcm7120-l2: Add Broadcom BCM7120-style L2 binding irqchip: bcm7120-l2: Add Broadcom BCM7120-style Level 2 interrupt controller irqchip: renesas-irqc: Add binding docs for new R-Car Gen2 SoCs irqchip: renesas-irqc: Add DT binding documentation irqchip: renesas-intc-irqpin: Document SoC-specific bindings openrisc: Get rid of handle_IRQ arm64: Get rid of handle_IRQ ARM: omap2: irq: Convert to handle_domain_irq ARM: imx: tzic: Convert to handle_domain_irq ARM: imx: avic: Convert to handle_domain_irq irqchip: or1k-pic: Convert to handle_domain_irq irqchip: atmel-aic5: Convert to handle_domain_irq irqchip: atmel-aic: Convert to handle_domain_irq irqchip: gic-v3: Convert to handle_domain_irq ...
| * Merge branch 'irqchip/broadcom' into irqchip/coreJason Cooper2014-10-02
| |\ | | | | | | | | | | | | Conflicts: drivers/irqchip/Makefile
| | * irqchip: bcm7120-l2: Add Broadcom BCM7120-style Level 2 interrupt controllerFlorian Fainelli2014-09-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the Level-2 interrupt controller hardware found in Broadcom Set Top Box System-on-a-Chip devices. This interrupt controller is implemented using a single enable register. This interrupt controller is always present on the platforms supported by the irq-brcmstb-l2 driver, hence the reason why both are compiled using the same Kconfig symbol. [jac] removed the following warning: drivers/irqchip/irq-bcm7120-l2.c: In function 'bcm7120_l2_intc_irq_handle': drivers/irqchip/irq-bcm7120-l2.c:49:27: warning: unused variable 'gc' [-Wunused-variable] Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lkml.kernel.org/r/1410309862-27784-2-git-send-email-f.fainelli@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | Merge branch 'irqchip/hip04' into irqchip/coreJason Cooper2014-09-14
| |\ \
| | * | irqchip: hip04: Enable Hisilicon HiP04 interrupt controllerHaojian Zhuang2014-08-20
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HiP04 GIC is the variate of ARM GICv2. ARM GICv2 supports 8 cores. HiP04 GIC extends to support 16 cores. It results that bit fields in GIC_DIST_TARGET & GIC_DIST_SOFTINT are different from ARM GICv2. And the maximium IRQ is downgrade from 1020 to 510. Since different register offset & bitfields definitation breaks compartible with ARM GICv2, create a new hip04 irq driver. And this driver is derived from irq-gic.c to support the Hisilicon HiP04 interrupt controller, which is similar to the GIC, but deviates at some points. Support for power management, non-banked registers, cascaded GICs (and multiple controllers in general) and bigLittle support has been removed from the GIC driver. Affinity related functions have been adjusted to match the Hisilicon hardware implementation. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Link: https://lkml.kernel.org/r/1407408695-19626-9-git-send-email-haojian.zhuang@linaro.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * / irqchip: keystone: Add irq controller ip driverGrygorii Strashko2014-08-17
| |/ | | | | | | | | | | | | | | | | | | | | | | | | On Keystone SOCs, DSP cores can send interrupts to ARM host using the IRQ controller IP. It provides 28 IRQ signals to ARM. The IRQ handler running on HOST OS can identify DSP signal source by analyzing SRCCx bits in IPCARx registers. This is one of the component used by the IPC mechanism used on Keystone SOCs. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Link: https://lkml.kernel.org/r/1406126430-9978-1-git-send-email-grygorii.strashko@ti.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* / arm: omap: irq: move irq.c to drivers/irqchip/Felipe Balbi2014-09-16
|/ | | | | | | | Just move the code over as it has no dependencies on arch/arm/ anymore. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* Merge branch 'irqchip/atmel-aic' into irqchip/coreJason Cooper2014-07-18
|\ | | | | | | | | Topic branch set up to facilitate merging the rest of the series which removes the driver from arch code.
| * irqchip: atmel-aic: Add atmel AIC/AIC5 driversBoris BREZILLON2014-07-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add AIC (Advanced Interrupt Controller) and AIC5 (AIC5 is an evolution of the AIC block) drivers. Put common code in irq-atmel-aic-common.c/.h so that both driver can access shared functions (this will ease maintenance). These drivers are only compatible with dt enabled board and replace the old implementation found in arch/arm/mach-at91/irq.c. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Link: https://lkml.kernel.org/r/1405012462-766-4-git-send-email-boris.brezillon@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | Merge tag 'tags/deps-irqchip-gic-3.17' into irqchip/coreJason Cooper2014-07-18
|\ \ | | | | | | | | | | | | From local branch irqchip/gic, this is topic branch that was set up to facilitate merging other changes depending on the new GICv3 driver.
| * | irqchip: gic-v3: Initial support for GICv3Marc Zyngier2014-07-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Generic Interrupt Controller (version 3) offers services that are similar to GICv2, with a number of additional features: - Affinity routing based on the CPU MPIDR (ARE) - System register for the CPU interfaces (SRE) - Support for more that 8 CPUs - Locality-specific Peripheral Interrupts (LPIs) - Interrupt Translation Services (ITS) This patch adds preliminary support for GICv3 with ARE and SRE, non-secure mode only. It relies on higher exception levels to grant ARE and SRE access. Support for LPI and ITS will be added at a later time. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Zi Shen Lim <zlim@broadcom.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Reviewed-by: Tirumalesh Chalamarla <tchalamarla@cavium.com> Reviewed-by: Yun Wu <wuyun.wu@huawei.com> Reviewed-by: Zhen Lei <thunder.leizhen@huawei.com> Tested-by: Tirumalesh Chalamarla<tchalamarla@cavium.com> Tested-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Acked-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Link: https://lkml.kernel.org/r/1404140510-5382-3-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | irqchip: gic: Move some bits of GICv2 to a library-type fileMarc Zyngier2014-07-08
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | A few GICv2 low-level function are actually very useful to GICv3, and it makes some sense to share them across the two drivers. They end-up in their own file, with an additional parameter used to ensure an optional synchronization (unused on GICv2). Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1404140510-5382-2-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* / irqchip: or1k-pic: Migrate from arch/openrisc/Stefan Kristiansson2014-07-01
|/ | | | | | | | | | | | | | | | | | | | | In addition to consolidating the or1k-pic with other interrupt controllers, this makes OpenRISC less tied to its on-cpu interrupt controller. All or1k-pic specific parts are moved out of irq.c and into drivers/irqchip/irq-or1k-pic.c In that transition, the functionality have been divided into three chip variants. One that handles level triggered interrupts, one that handles edge triggered interrupts and one that handles the interrupt controller that is present in the or1200 OpenRISC cpu implementation. Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> Link: https://lkml.kernel.org/r/1401136302-27654-1-git-send-email-stefan.kristiansson@saunalahti.fi Acked-by: Jonas Bonn <jonas@southpole.se> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* irqchip: brcmstb-l2: Add Broadcom Set Top Box Level-2 interrupt controllerFlorian Fainelli2014-05-27
| | | | | | | | | | | | This patch adds support for the Level-2 interrupt controller hardware found in Broadcom Set Top Box System-on-a-Chip devices. This interrupt controller is implemented using the generic IRQ chip driver with separate enable and disable registers. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Link: https://lkml.kernel.org/r/1400892054-24457-2-git-send-email-f.fainelli@gmail.com Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* Merge tag 'drivers-3.15' of ↵Linus Torvalds2014-04-05
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver changes from Arnd Bergmann: "These changes are mostly for ARM specific device drivers that either don't have an upstream maintainer, or that had the maintainer ask us to pick up the changes to avoid conflicts. A large chunk of this are clock drivers (bcm281xx, exynos, versatile, shmobile), aside from that, reset controllers for STi as well as a large rework of the Marvell Orion/EBU watchdog driver are notable" * tag 'drivers-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (99 commits) Revert "dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac." Revert "net: stmmac: Add SOCFPGA glue driver" ARM: shmobile: r8a7791: Fix SCIFA3-5 clocks ARM: STi: Add reset controller support to mach-sti Kconfig drivers: reset: stih416: add softreset controller drivers: reset: stih415: add softreset controller drivers: reset: Reset controller driver for STiH416 drivers: reset: Reset controller driver for STiH415 drivers: reset: STi SoC system configuration reset controller support dts: socfpga: Add sysmgr node so the gmac can use to reference dts: socfpga: Add support for SD/MMC on the SOCFPGA platform reset: Add optional resets and stubs ARM: shmobile: r7s72100: fix bus clock calculation Power: Reset: Generalize qnap-poweroff to work on Synology devices. dts: socfpga: Update clock entry to support multiple parents ARM: socfpga: Update socfpga_defconfig dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac. net: stmmac: Add SOCFPGA glue driver watchdog: orion_wdt: Use %pa to print 'phys_addr_t' drivers: cci: Export CCI PMU revision ...
| * Merge tag 'omap-for-v3.15/crossbar-signed' of ↵Olof Johansson2014-03-08
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers Merge OMAP crossbar support from Tony Lindgren: Add support for GIC crossbar that routes interrupts on newer omaps. Looks like people wanted these merged via the omap tree as it's the only user for the GIC crossbar. * tag 'omap-for-v3.15/crossbar-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: DRA: Enable Crossbar IP support for DRA7XX ARM: OMAP4+: Correct Wakeup-gen code to use physical irq number DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs Signed-off-by: Olof Johansson <olof@lixom.net>
| | * DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IPSricharan R2014-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some socs have a large number of interrupts requests to service the needs of its many peripherals and subsystems. All of the interrupt lines from the subsystems are not needed at the same time, so they have to be muxed to the irq-controller appropriately. In such places a interrupt controllers are preceded by an CROSSBAR that provides flexibility in muxing the device requests to the controller inputs. This driver takes care a allocating a free irq and then configuring the crossbar IP as a part of the mpu's irqchip callbacks. crossbar_init should be called right before the irqchip_init, so that it is setup to handle the irqchip callbacks. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Tony Lindgren <tony@atomide.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Sricharan R <r.sricharan@ti.com> Acked-by: Kumar Gala <galak@codeaurora.org> (for DT binding portion) Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Thomas Gleixner <tglx@linutronix.de>
* | | Merge tag 'soc-3.15' of ↵Linus Torvalds2014-04-05
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC specific changes from Arnd Bergmann: "Lots of changes specific to one of the SoC families. Some that stick out are: - mach-qcom gains new features, most importantly SMP support for the newer chips (Stephen Boyd, Rohit Vaswani) - mvebu gains support for three new SoCs: Armada 375, 380 and 385 (Thomas Petazzoni and Free-electrons team) - SMP support for Rockchips (Heiko Stübner) - Lots of i.MX changes (Shawn Guo) - Added support for BCM5301x SoC (Hauke Mehrtens) - Multiplatform support for Marvell Kirkwood and Dove (Andrew Lunn and Sebastian Hesselbarth doing the final part of a long journey) - Unify davinci platforms and remove obsolete ones (Sekhar Nori, Arnd Bergmann)" * tag 'soc-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (126 commits) ARM: sunxi: Select HAVE_ARM_ARCH_TIMER ARM: cache-tauros2: remove ARMv6 code ARM: mvebu: don't select CONFIG_NEON ARM: davinci: fix DT booting with default defconfig ARM: configs: bcm_defconfig: enable bcm590xx regulator support ARM: davinci: remove tnetv107x support MAINTAINERS: Update ARM STi maintainers ARM: restrict BCM_KONA_UART to ARCH_BCM_MOBILE ARM: bcm21664: Add board support. ARM: sunxi: Add the new watchog compatibles to the reboot code ARM: enable ARM_HAS_SG_CHAIN for multiplatform ARM: davinci: remove da8xx_omapl_defconfig ARM: davinci: da8xx: fix multiple watchdog device registration ARM: davinci: add da8xx specific configs to davinci_all_defconfig ARM: davinci: enable da8xx build concurrently with older devices ARM: BCM5301X: workaround suppress fault ARM: BCM5301X: add early debugging support ARM: BCM5301X: initial support for the BCM5301X/BCM470X SoCs with ARM CPU ARM: mach-bcm: Remove GENERIC_TIME ARM: shmobile: APMU: Fix warnings due to improper printk formats ...
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-26 17:30:59 +0000