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* | msm: kgsl: Disable ISENSE CGCOleg Perelet2016-05-03
| | | | | | | | | | | | | | | | Disable GPU ISENSE clock gating as workaround of ISENSE HW issue. CRs-Fixed: 973565 Change-Id: If54caf008c654f488986a279bd19bea97457dc2c Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
* | msm: kgsl: Explicitly set ISENSE clock rate for A540.Oleg Perelet2016-04-29
| | | | | | | | | | | | | | | | On A540 ISENSE clock rate is controlled by GPU driver. CRs-Fixed: 973565 Change-Id: Iab40cff01b6e65db51a4b793572714d2059a78ad Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
* | msm: kgsl: Update ucode workarounds for A5xx GPUsPrakash Kamliya2016-04-22
| | | | | | | | | | | | | | | | | | | | Update ucode workarounds for A5xx GPUs based on new microcode and hardware changes. CRs-Fixed: 1000396 Change-Id: I87a1ba9bfc441cad2ed6a6959d07af1cc1e2c7bc Signed-off-by: Prakash Kamliya <pkamliya@codeaurora.org> Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
* | msm: kgsl: Invoke DCVS callbacks on A540Oleg Perelet2016-04-13
| | | | | | | | | | | | | | | | | | As long as GPMU is enabled, DCVS has to handshake with firmware. It is a new requirement of A540 power management. CRs-Fixed: 973565 Change-Id: Ie6480fc3ba0e1b95aab40e31b09ff2bd798ff30f Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
* | msm: kgsl: Return EOPNOTSUPP for A3XX command batch profilingHareesh Gundu2016-04-13
| | | | | | | | | | | | | | | | | | | | A3XX doesn't have support for command batch profiling. Return EOPNOTSUPP for a command batch profiling request on A3XX, so that userspace code knows that this feature is not supported. CRs-Fixed: 986169 Change-Id: I6dfcab462a933ef31e3bba6bef07f17016ae50b9 Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
* | msm: kgsl: Pass correct buffer size for mapping gpuobj user memoryTarun Karra2016-04-13
| | | | | | | | | | | | | | | | | | | | | | Current code incorrectly specifies buffer size as 0 for mapping gpuobj user memory. This causes the map to fail because buffer size is expected to be a non zero value. Fix this by passing the correct size of the buffer to be mapped. CRs-Fixed: 995378 Change-Id: I1a9aeb3f1dd67f014847322e5b14cba8775a82a4 Signed-off-by: Tarun Karra <tkarra@codeaurora.org>
* | msm: kgsl: Fix gpudev NULL dereference in adreno_removeHareesh Gundu2016-04-13
| | | | | | | | | | | | | | | | | | | | In adreno_remove() there is possibility of dereference of gpudev without NULL check. Fix this by getting gpudev after adreno_dev NULL check. CRs-Fixed: 993267 Change-Id: I17d8b4ba2c74a787a065dbdb0ac88d065605fcb1 Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
* | msm: kgsl: verify user memory permissions before mapping to GPU driverTarun Karra2016-04-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For user memory of type KGSL_USER_MEM_TYPE_ADDR mapped to GPU driver verify permissions and map GPU permissions same as CPU permissions. If elevated permissions are requested return an error to prevent privilege escalation. Without this check user could map readonly memory into GPU driver as readwrite and gain elevated privilege. Write permissions check is currently inverted causing readonly user pages to be mapped as readwrite in GPU driver. Fix this check to map readonly pages as readonly. CRs-Fixed: 988993 Change-Id: I0e097d7e4e4c414c0849e33bcc61a26fb94291ad Signed-off-by: Tarun Karra <tkarra@codeaurora.org>
* | msm: kgsl: Enable GPMU and SPTP/RAC power collapse on A540Oleg Perelet2016-04-13
| | | | | | | | | | | | | | | | Enable GPMU and SPTP/RAC power collapse on A540. CRs-Fixed: 973565 Change-Id: I73b40d264c4054a43c2776337b80af88adff077e Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
* | msm: kgsl: Zero the adreno ioctl command bufferHarshdeep Dhatt2016-04-13
| | | | | | | | | | | | | | | | | | | | The kernel command buffer is not zeroed in the adreno ioctls, and may contain garbage. The garbage value can lead to unexpected results. CRs-Fixed: 993518 Change-Id: I75033cdf4637881ecd6fa4dd31aea083b134e6d2 Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
* | msm: kgsl: Correct the order of preemption packetsHarshdeep Dhatt2016-04-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current order: IB1 batch, timestamp writes, SRM=NULL, CP_YIELD_ENABLE, CP_CONTEXT_SWITCH_YIELD Correct order: IB1 batch, SRM=NULL, CP_YIELD_ENABLE, timestamp writes, CP_CONTEXT_SWITCH_YIELD Reason: if preemption is initiated after the last checkpoint but before SET_RENDER_MODE == NULL is executed, all of the PM4s starting at the preamble of the check point will be replayed up to the SRM == NULL, including an attempt to re-timestamp/ re-retire the last batch of IBs. If what was intended here was to make sure that the IB batch would be retired once then the SET_RENDER_MODE == NULL and CP_YIELD_ENABLE should be placed immediately after IB_PFE packets and before the time stamping PM4 packets in the ring buffer. CRs-Fixed: 990078 Change-Id: I04a1a44f12dd3a09c50b4fe39e14a2bd636b24de Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
* | msm: kgsl: Attach mem_entry once we have valid GPU addressRajesh Kemisetti2016-03-25
| | | | | | | | | | | | | | | | | | | | | | | | | | kgsl_mem_entry_attach_process() adds new entry to the mem_idr list without really having a valid GPU address. This new entry can be used by other thread with GPUADDR_IN_MEMDESC() and destroy it. Get GPU address first and then add it to the mem_idr list. Change-Id: I4d66cec754ca5315df3c9fe09644f55596c3c33c Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
* | msm: kgsl: Track and pass number of active context to governorDeepak Kumar2016-03-25
| | | | | | | | | | | | | | | | | | | | | | Track number of active context and pass it to governor along with busy stats. This allows GPU DCVS to make decision based on context count and busy stats, which helps in handling sudden workloads. Change-Id: I9b40e4917b30ee3f15f2c8e99669e090578f1289 Signed-off-by: Deepak Kumar <dkumar@codeaurora.org> Signed-off-by: Divya Ponnusamy <pdivya@codeaurora.org>
* | msm: kgsl: Allocate guard page on demandHareesh Gundu2016-03-25
| | | | | | | | | | | | | | | | | | | | | | Allocate guard page when the first buffer is mapped into the IOMMU. This also ensures that the guard page gets allocated if the guard page mmu feature is enabled. CRs-Fixed: 988093 Change-Id: Id97492707463a1f15a4bf1c67b9c0f03214e6283 Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
* | msm: kgsl: Fix race condition during mem_entry detachRajesh Kemisetti2016-03-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | kgsl_mem_entry_detach_process() makes gpuaddr to NULL and then removes the entry from mem_idr list. Sometimes this can cause kgsl_sharedmem_find() to return the same entry for a different gpuaddr/thread if it satisfies GPUADDR_IN_MEMDESC(). To avoid this, first remove the entry from mem_idr list and proceed with unmap/untrack calls. Change-Id: Ib9f2bc0fdaecd394735dd61b18fdc7de57aa3748 Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
* | msm: kgsl: Avoid racing against context delete while releasing contextsDeepak Kumar2016-03-25
| | | | | | | | | | | | | | | | | | While releasing contexts take a reference to context inside read rcu lock to avoid racing against context deletion. This will avoid using dangling context pointer in device_release_contexts. Change-Id: I76e787f6dde5a324fec23e81829174bd28134c6c Signed-off-by: Deepak Kumar <dkumar@codeaurora.org>
* | msm: kgsl: Do not switch pagetable if context is detachedHarshdeep Dhatt2016-03-25
| | | | | | | | | | | | | | | | | | | | This is done to avoid a race condition between a context getting detached and destroyed before the GPU has executed the pt switch commands. CRs-Fixed: 987587 Change-Id: I5c485e41a23b288f27e607b3e3ed5bf66cbad98a Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
* | msm: kgsl: Standardize ringbuffers in the snapshotJordan Crouse2016-03-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'start' and 'stop' in the snapshot ringbuffer header are supposed to be the dword offset that the data starts and stops at respectively. For the current ringbuffer which is parsed 'start' and 'stop' are equal to the CP wptr but all other ringbuffers are just dumped from start to finish so 'start' and stop' should be 0 and KGSL_RB_DWORDS. And having said that, why are we bothering to make the current ringbuffer special anyway? In every case we are dumping the entire ringbuffer so we might as well dump it in order. While messing about in this code go a few more steps to make sure that we don't dump the same ringbuffer more than once. Change-Id: Ic0dedbada33adda660b7f0bf5eb165b0aa159004 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | msm: kgsl: Add pm_qos_cpu_mask_latency to avoid L2PC on mask CPUDivya Ponnusamy2016-03-25
| | | | | | | | | | | | | | | | | | Add a l2pc-cpu-mask-latency in device tree. This latency is used in kgsl_pwrctrl_update_l2pc() API to avoid L2PC on masked CPUs by giving reduced latency value. Change-Id: I0447977bce5ed5c09a863b03bb42b9428686a9f5 Signed-off-by: Divya Ponnusamy <pdivya@codeaurora.org>
* | msm: kgsl: Fix VBIF out register settings for A306aHareesh Gundu2016-03-25
| | | | | | | | | | | | | | Recommended value for A306a VBIF out registers is 0x10. Change-Id: I5ea3f4203b7649007fa62bdfe70a41c8d86432ef Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
* | msm: kgsl: Add secure memory flag in process mem fileHarshdeep Dhatt2016-03-25
| | | | | | | | | | | | | | | | | | Secure memory will have 's' flag set in its flag fields. This is needed to track secure memory of a process. CRs-Fixed: 985767 Change-Id: I011dcc951b1db8adf763f85701aa869f6d4744d3 Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
* | msm: kgsl: Unbind the kgsl-event workqueueJonathan Wicks2016-03-25
| | | | | | | | | | | | | | | | | | Allow the kgsl-event workqueue to run on any available core. The other workqueues in KGSL were already unbound. CRs-Fixed: 985082 Change-Id: I7e843b57541b7ddcb53848078f73b05c88238711 Signed-off-by: Jonathan Wicks <jwicks@codeaurora.org>
* | msm: kgsl: change ISENSE calibration handshake orderOleg Perelet2016-03-25
| | | | | | | | | | | | | | | | Force ISENSE calibration to stop before starting new calibration. CRs-Fixed: 973565 Change-Id: I86dcbaa7feaecd630a027c5aca41d62a5855efda Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
* | msm: kgsl: Invoke AGC handshake on A540Oleg Perelet2016-03-25
| | | | | | | | | | | | | | | | | | Invoke AGC handshake on A540 even when LM is disabled, pass 0 for LM and pass HW patchid. CRs-Fixed: 973565 Change-Id: I62c32b55bf2e3a1ec498b1ec0a8bebf34ac803a9 Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
* | msm: kgsl: Streamline ringbuffer initializationCarter Cooper2016-03-25
| | | | | | | | | | | | | | | | Move device specific features to the device rather than trying to do them in the common initialization code. Change-Id: I812db29a2eae90ca532755c265aaa2e52db972d7 Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
* | msm: kgsl: Disable guardpage for A5x and suppress pagefaultsSushmita Susheelendra2016-03-25
| | | | | | | | | | | | | | | | | | | | | | | | Disable the guardpage workaround for A5x and instead selectively suppress pagefaults. Suppress read pagefaults that are likely caused due to UCHE overfetches. For this, the fault address must be within the first 64 bytes of a page and the fault page must be preceded by a valid allocation. CRs-Fixed: 975293 Change-Id: I6a0995af3ab4129c6923726043c5f34c747641f9 Signed-off-by: Sushmita Susheelendra <ssusheel@codeaurora.org>
* | msm: kgsl: Change the active context trackerPrakash Kamliya2016-03-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The active context tracker that we bolted on the side of the dispatcher was designed mainly to see if there was 1 OR more than 1 active context, not much more than that. Since it is apparent that we'll need to track up to 4 contexts and possibly more later the algorithm needs to change. The new algorithm puts all active contexts on a linked list - every time a context is used it is popped from the list and put on the tip with an updated time. To count the number of active contexts walk the list until you get a context with an active time older than you are looking for. You also can do other magic on the context, like see if it matches up with a given command queue. Change-Id: Ic0dedbad6be9fd1925121ee54e0000c42b089f44 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Prakash Kamliya <pkamliya@codeaurora.org>
* | msm: kgsl: Change GPU RAC hardware clockgatingOleg Perelet2016-03-25
| | | | | | | | | | | | | | | | | | On A5xx disable LRZ clockgating, by setting 0x0 for bits 18:16 of RBBM_CLOCK_CNTL2_RAC. CRs-Fixed: 964234 Change-Id: Icf858e3431e1c7f9943762067a74b1ce2af7ca6f Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
* | sync: oneshot_sync: Add oneshot_sync driverJordan Crouse2016-03-23
| | | | | | | | | | | | | | Add the oneshot_sync driver as of msm-3.18 commit 7892968f (sync: oneshot_sync: Update oneshot_sync for new sync APIs). Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | msm: kgsl: Use CONFIG_QCOM_KGSL_IOMMUJordan Crouse2016-03-23
| | | | | | | | | | | | | | The rest of the driver started using CONFIG_QCOM_KGSL_IOMMU. The replayed MMU changes didn't get the memo. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | msm: kgsl: Add NULL check for preemption_schedule callHareesh Gundu2016-03-23
| | | | | | | | | | | | | | | | | | | | preemption_schedule() is not implemented for A3xx targets. Invoking this function without NULL check result into crash in A3xx target. Fix this by adding a NULL check before invoking the preemption_schedule(). Change-Id: Ic600235f149cade57fedc5454bdc0f6794c67bd9 Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
* | msm: kgsl: Initialize coresight at boot timeJordan Crouse2016-03-23
| | | | | | | | | | | | | | | | | | Initialize coresight at boot time so that it is available to be configured before the first open of /dev/kgsl-3d0 to get GPU scan dumps during initial power up. Change-Id: Ic0dedbadbda251f12855895cc0aa53852f79a8b8 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | msm: kgsl: Add quirk for masking out hang detect signalsShrenuj Bansal2016-03-23
| | | | | | | | | | | | | | | | | | | | Add a quirk to mask out the RB 1-3 activity signals in the hang detection logic. Set this quirk in the devicetree for 8996v2 and v3. CRs-Fixed: 978849 Change-Id: I63073b5973644453e775b41a9361de55d7933a07 Signed-off-by: Shrenuj Bansal <shrenujb@codeaurora.org>
* | msm: kgsl: Submit a set of critical packets right after ME initShrenuj Bansal2016-03-23
| | | | | | | | | | | | | | | | | | | | During the initialization sequence, submit a set of important packets to the GPU in order to pre-load the I-cache with the critical ucode instructions. CRs-Fixed: 978777 Change-Id: Ic6a17b24d8c3aa383af8e25cf9ef771459d65796 Signed-off-by: Shrenuj Bansal <shrenujb@codeaurora.org>
* | msm: kgsl: Enable guard page for GPUOBJ_IMPORT ioctlSushmita Susheelendra2016-03-23
| | | | | | | | | | | | | | | | | | | | The guard page should be enabled on the gpuobj import path to ensure allocations that are mapped are safe from the UCHE overfetch bug. CRs-Fixed: 975219 Change-Id: I42b7046ce3d314ec21c8fb03ef4fbbcdb094d8cf Signed-off-by: Sushmita Susheelendra <ssusheel@codeaurora.org>
* | msm: kgsl: Use fault context to retrieve process informationSushmita Susheelendra2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | Instead of looking up the process by pagetable base and name, use the fault context to extract the pid and other process specific information. This works for both the per-process and global pagetable configurations and also reduces some locking. This also reports the correct pid and task name in the global pagetable configuration. CRs-Fixed: 971753 Change-Id: I9c869527c3d1b2606f3d12234163935d6f5e43a9 Signed-off-by: Sushmita Susheelendra <ssusheel@codeaurora.org>
* | msm: kgsl: Update RBBM_CLOCK_HYST_UCHE idle setting value for A50xHareesh Gundu2016-03-23
| | | | | | | | | | | | | | | | A50x GPU RBBM_CLOCK_HYST_UCHE idle setting recommended value is 0x00FFFFF4. Update accordingly to reflect the same. Change-Id: I95d79040c645e418ed26ea72ba84af2c2c7efce9 Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
* | msm: kgsl: Specify the initial pwrlevel for each speed binSuman Tatiraju2016-03-23
| | | | | | | | | | | | | | | | | | | | Some platforms support multiple GPU clock plans based on the speed bin in the efuse. Specify the wake up frequency of each speed bin individually to wake the gpu at the correct powerlevel. CRs-Fixed: 967494 Change-Id: I9890b8a710d7055c30f9ae7612b092af8fa8a9f5 Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
* | msm: kgsl: Disable all HW clockgating during snapshotOleg Perelet2016-03-23
| | | | | | | | | | | | | | | | While producing snapshot disable all HWCG branches, not only top level. CRs-Fixed: 978122 Change-Id: I4b01224a0ba46c276115a284a0da6207c7968f72 Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
* | msm: kgsl: Add run time hardware clockgating controlOleg Perelet2016-03-23
| | | | | | | | | | | | | | | | Create sysfs nodes to enable/disable hardware clock gating. CRs-Fixed: 973565 Change-Id: If5f0215e0d7f3d7be1a0cf00fbd8789c6adf2f0f Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
* | msm: kgsl: Fix race condition in adreno_spin_idle()Suman Tatiraju2016-03-23
| | | | | | | | | | | | | | | | | | | | | | adreno_spin_idle spins for a timeout checking for gpu to idle. Sometimes due to race conditions the timeout can occur before the loop is executed. Change the logic to a do-while loop and add an extra idle check after the timeout before returning failure. CRs-Fixed: 978122 Change-Id: Idb92a0180dd8cc3e662b1ccf44d69e4bbafb29f1 Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
* | msm: kgsl: Set the DDR high bank bit if specified in the device treeJordan Crouse2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On 5XX targets we need to program the bit of the highest DDR bank into a number of registers, one of which is protected which would cause problems if the user mode driver tried to write to it. Specify the high bank bit in the device tree files, set the problematic register in the kernel and then pass the value up to the user mode driver as a property and let them program the other registers. This makes the device tree the authoratative source of the high bit value which is exactly how it should be. If the value isn't specified by the device tree for whatever reason return an error for the property request - that will give the UMD a clue that the value wasn't specified and they should just set a default. CRs-Fixed: 970272 Change-Id: Ic0dedbad830321329b74da7fa3e172fdaf765c4d Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | msm: kgsl: Add disable-busy-time-burst to disable ceiling thresholdDivya Ponnusamy2016-03-23
| | | | | | | | | | | | | | | | | | | | Add a devicetree property disable-busy-time-burst to disable ceiling threshold in the governor. The ceiling threshold cause busy time burst that switch power level for large frames based on busy time. Change-Id: I44f8a51e0aa49bb0b2210703f57874fd5f219c18 Signed-off-by: Divya Ponnusamy <pdivya@codeaurora.org>
* | msm: kgsl: Enable GPU clock gating for MSM8996proSuman Tatiraju2016-03-23
| | | | | | | | | | | | | | | | | | The current code enables GPU clock gating only for v2 and v3. Enable it for MSM8996pro also. CRs-Fixed: 974760 Change-Id: I2bcdbf73be080fba836c24616fc7959ad7c4c1e9 Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
* | msm: kgsl: Enable content protection for A506Rajesh Kemisetti2016-03-23
| | | | | | | | | | | | | | | | | | | | | | Enable content protection for A506 from gpulist. Also, skip scm call to program CP secure ucode base registers since A506 supports retention for these registers. Change-Id: I48a0f04826430bfb927c755c176255be45199b26 Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
* | msm: kgsl: Restrict secure contexts to ringbuffer level preemptionTarun Karra2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Preemption from secure to unsecure needs zap shader to be run to clear all secure content. CP does not know during preemption if it is switching between secure and unsecure contexts so restrict secure contexts to be preempted at ringbuffer level. At the end of each secure submission we switch back to unsecure mode and run the zap shader to clear secure contents. Ringbuffer level preemption ensures Zap shader is run before switching back to unsecure mode. CRs-Fixed: 974102 Change-Id: Iff11c1d5732d46fe5a1fbdbc7d162aaa1736741b Signed-off-by: Tarun Karra <tkarra@codeaurora.org>
* | msm: kgsl: Read speed bin information from device treeSuman Tatiraju2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | Speed bin information is sometimes written to efuses to specify a GPU frequency plan available on a platform. The current code only supports reading the efuses for msm8996v3. Hence specify it in the platform device tree node to support multiple platforms. CRs-Fixed: 967494 Change-Id: I5db4d5a35e2700250517ea6cac3d4d736936ce9f Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
* | msm: kgsl: Update clocks for GPU on MSMCOBALTOleg Perelet2016-03-23
| | | | | | | | | | | | | | | | | | Add new clocks for MSMCOBALT. CRs-Fixed: 973565 Change-Id: I579875f34cff0ff9b714c0378084826aee0f893c Signed-off-by: George Shen <sqiao@codeaurora.org> Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
* | msm: kgsl: fix some uninitialized variablesHareesh Gundu2016-03-23
| | | | | | | | | | | | | | | | This change set default value for uninitialized variables, to address errors related to them. Change-Id: Idd306cafa4dfca322945ea8398e0c4d6c18d6ff6 Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
* | msm: kgsl: Update snapshot ringbuffer parser for type7 ibsHarshdeep Dhatt2016-03-23
| | | | | | | | | | | | | | | | | | Fix the wraparound logic when searching for ibs in the ringbuffer. The ibs can either be type3 or type7 packets so handle both cases. CRs-Fixed: 971163 Change-Id: I9bc4b4a72cddfe7f3d3892612c6e28861fdd0324 Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
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