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authorOleg Perelet <operelet@codeaurora.org>2016-02-08 14:46:08 -0800
committerDavid Keitel <dkeitel@codeaurora.org>2016-03-23 21:20:47 -0700
commite70b298fa41cc025f4f78bc39aa10b911f221b99 (patch)
tree1f74190c4daf7d761fbd64e0982d176792327091 /drivers/gpu
parent2456b24f24928d0ee5e6daa8ebac30b67f79d6c1 (diff)
msm: kgsl: Add run time hardware clockgating control
Create sysfs nodes to enable/disable hardware clock gating. CRs-Fixed: 973565 Change-Id: If5f0215e0d7f3d7be1a0cf00fbd8789c6adf2f0f Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/msm/adreno.c2
-rw-r--r--drivers/gpu/msm/adreno.h1
-rw-r--r--drivers/gpu/msm/adreno_a5xx.c3
-rw-r--r--drivers/gpu/msm/adreno_sysfs.c14
4 files changed, 19 insertions, 1 deletions
diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c
index 337a7f2023f7..0719690df01e 100644
--- a/drivers/gpu/msm/adreno.c
+++ b/drivers/gpu/msm/adreno.c
@@ -97,7 +97,7 @@ static struct adreno_device device_3d0 = {
.input_work = __WORK_INITIALIZER(device_3d0.input_work,
adreno_input_work),
.pwrctrl_flag = BIT(ADRENO_SPTP_PC_CTRL) | BIT(ADRENO_PPD_CTRL) |
- BIT(ADRENO_LM_CTRL),
+ BIT(ADRENO_LM_CTRL) | BIT(ADRENO_HWCG_CTRL),
.profile.enabled = false,
};
diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h
index 8a6aae3472f1..f40a14165acc 100644
--- a/drivers/gpu/msm/adreno.h
+++ b/drivers/gpu/msm/adreno.h
@@ -188,6 +188,7 @@ enum adreno_gpurev {
#define ADRENO_SPTP_PC_CTRL 0
#define ADRENO_PPD_CTRL 1
#define ADRENO_LM_CTRL 2
+#define ADRENO_HWCG_CTRL 3
/* number of throttle counters for DCVS adjustment */
#define ADRENO_GPMU_THROTTLE_COUNTERS 4
diff --git a/drivers/gpu/msm/adreno_a5xx.c b/drivers/gpu/msm/adreno_a5xx.c
index d25218ad7e96..bb7dc9dcde33 100644
--- a/drivers/gpu/msm/adreno_a5xx.c
+++ b/drivers/gpu/msm/adreno_a5xx.c
@@ -1197,6 +1197,9 @@ static void a5xx_hwcg_init(struct adreno_device *adreno_dev)
const struct kgsl_hwcg_reg *regs;
int i, j;
+ if (!test_bit(ADRENO_HWCG_CTRL, &adreno_dev->pwrctrl_flag))
+ return;
+
for (i = 0; i < ARRAY_SIZE(a5xx_hwcg_registers); i++) {
if (a5xx_hwcg_registers[i].devfunc(adreno_dev))
break;
diff --git a/drivers/gpu/msm/adreno_sysfs.c b/drivers/gpu/msm/adreno_sysfs.c
index 977ba7624d3f..f9d16222177c 100644
--- a/drivers/gpu/msm/adreno_sysfs.c
+++ b/drivers/gpu/msm/adreno_sysfs.c
@@ -190,6 +190,17 @@ static unsigned int _preemption_show(struct adreno_device *adreno_dev)
return adreno_is_preemption_enabled(adreno_dev);
}
+static int _hwcg_store(struct adreno_device *adreno_dev,
+ unsigned int val)
+{
+ return _pwrctrl_store(adreno_dev, val, ADRENO_HWCG_CTRL);
+}
+
+static unsigned int _hwcg_show(struct adreno_device *adreno_dev)
+{
+ return test_bit(ADRENO_HWCG_CTRL, &adreno_dev->pwrctrl_flag);
+}
+
static int _sptp_pc_store(struct adreno_device *adreno_dev,
unsigned int val)
{
@@ -303,6 +314,8 @@ static DEVICE_INT_ATTR(wake_timeout, 0644, adreno_wake_timeout);
static ADRENO_SYSFS_BOOL(sptp_pc);
static ADRENO_SYSFS_BOOL(lm);
static ADRENO_SYSFS_BOOL(preemption);
+static ADRENO_SYSFS_BOOL(hwcg);
+
static const struct device_attribute *_attr_list[] = {
&adreno_attr_ft_policy.attr,
@@ -315,6 +328,7 @@ static const struct device_attribute *_attr_list[] = {
&adreno_attr_sptp_pc.attr,
&adreno_attr_lm.attr,
&adreno_attr_preemption.attr,
+ &adreno_attr_hwcg.attr,
NULL,
};