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* drm/nouveau/i2c: Disable i2c bus access after ->fini()Lyude Paul2019-06-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 342406e4fbba9a174125fbfe6aeac3d64ef90f76 upstream. For a while, we've had the problem of i2c bus access not grabbing a runtime PM ref when it's being used in userspace by i2c-dev, resulting in nouveau spamming the kernel log with errors if anything attempts to access the i2c bus while the GPU is in runtime suspend. An example: [ 130.078386] nouveau 0000:01:00.0: i2c: aux 000d: begin idle timeout ffffffff Since the GPU is in runtime suspend, the MMIO region that the i2c bus is on isn't accessible. On x86, the standard behavior for accessing an unavailable MMIO region is to just return ~0. Except, that turned out to be a lie. While computers with a clean concious will return ~0 in this scenario, some machines will actually completely hang a CPU on certian bad MMIO accesses. This was witnessed with someone's Lenovo ThinkPad P50, where sensors-detect attempting to access the i2c bus while the GPU was suspended would result in a CPU hang: CPU: 5 PID: 12438 Comm: sensors-detect Not tainted 5.0.0-0.rc4.git3.1.fc30.x86_64 #1 Hardware name: LENOVO 20EQS64N17/20EQS64N17, BIOS N1EET74W (1.47 ) 11/21/2017 RIP: 0010:ioread32+0x2b/0x30 Code: 81 ff ff ff 03 00 77 20 48 81 ff 00 00 01 00 76 05 0f b7 d7 ed c3 48 c7 c6 e1 0c 36 96 e8 2d ff ff ff b8 ff ff ff ff c3 8b 07 <c3> 0f 1f 40 00 49 89 f0 48 81 fe ff ff 03 00 76 04 40 88 3e c3 48 RSP: 0018:ffffaac3c5007b48 EFLAGS: 00000292 ORIG_RAX: ffffffffffffff13 RAX: 0000000001111000 RBX: 0000000001111000 RCX: 0000043017a97186 RDX: 0000000000000aaa RSI: 0000000000000005 RDI: ffffaac3c400e4e4 RBP: ffff9e6443902c00 R08: ffffaac3c400e4e4 R09: ffffaac3c5007be7 R10: 0000000000000004 R11: 0000000000000001 R12: ffff9e6445dd0000 R13: 000000000000e4e4 R14: 00000000000003c4 R15: 0000000000000000 FS: 00007f253155a740(0000) GS:ffff9e644f600000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00005630d1500358 CR3: 0000000417c44006 CR4: 00000000003606e0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: g94_i2c_aux_xfer+0x326/0x850 [nouveau] nvkm_i2c_aux_i2c_xfer+0x9e/0x140 [nouveau] __i2c_transfer+0x14b/0x620 i2c_smbus_xfer_emulated+0x159/0x680 ? _raw_spin_unlock_irqrestore+0x1/0x60 ? rt_mutex_slowlock.constprop.0+0x13d/0x1e0 ? __lock_is_held+0x59/0xa0 __i2c_smbus_xfer+0x138/0x5a0 i2c_smbus_xfer+0x4f/0x80 i2cdev_ioctl_smbus+0x162/0x2d0 [i2c_dev] i2cdev_ioctl+0x1db/0x2c0 [i2c_dev] do_vfs_ioctl+0x408/0x750 ksys_ioctl+0x5e/0x90 __x64_sys_ioctl+0x16/0x20 do_syscall_64+0x60/0x1e0 entry_SYSCALL_64_after_hwframe+0x49/0xbe RIP: 0033:0x7f25317f546b Code: 0f 1e fa 48 8b 05 1d da 0c 00 64 c7 00 26 00 00 00 48 c7 c0 ff ff ff ff c3 66 0f 1f 44 00 00 f3 0f 1e fa b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d ed d9 0c 00 f7 d8 64 89 01 48 RSP: 002b:00007ffc88caab68 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 RAX: ffffffffffffffda RBX: 00005630d0fe7260 RCX: 00007f25317f546b RDX: 00005630d1598e80 RSI: 0000000000000720 RDI: 0000000000000003 RBP: 00005630d155b968 R08: 0000000000000001 R09: 00005630d15a1da0 R10: 0000000000000070 R11: 0000000000000246 R12: 00005630d1598e80 R13: 00005630d12f3d28 R14: 0000000000000720 R15: 00005630d12f3ce0 watchdog: BUG: soft lockup - CPU#5 stuck for 23s! [sensors-detect:12438] Yikes! While I wanted to try to make it so that accessing an i2c bus on nouveau would wake up the GPU as needed, airlied pointed out that pretty much any usecase for userspace accessing an i2c bus on a GPU (mainly for the DDC brightness control that some displays have) is going to only be useful while there's at least one display enabled on the GPU anyway, and the GPU never sleeps while there's displays running. Since teaching the i2c bus to wake up the GPU on userspace accesses is a good deal more difficult than it might seem, mostly due to the fact that we have to use the i2c bus during runtime resume of the GPU, we instead opt for the easiest solution: don't let userspace access i2c busses on the GPU at all while it's in runtime suspend. Changes since v1: * Also disable i2c busses that run over DP AUX Signed-off-by: Lyude Paul <lyude@redhat.com> Cc: stable@vger.kernel.org Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* drm/nouveau/tmr: fully separate alarm execution/pending listsBen Skeggs2017-06-14
| | | | | | | | | | | | | | | commit b4e382ca7586a63b6c1e5221ce0863ff867c2df6 upstream. Reusing the list_head for both is a bad idea. Callback execution is done with the lock dropped so that alarms can be rescheduled from the callback, which means that with some unfortunate timing, lists can get corrupted. The execution list should not require its own locking, the single function that uses it can only be called from a single context. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* drm/nouveau/pmu: remove whitelist for PGOB-exit WAR, enable by defaultBen Skeggs2015-12-09
| | | | | | | | | NVIDIA have indicated that the workaround is required on all GK10[467] boards that have the PGOB fuse set. I've left the commandline option in place for now, as paranoia. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/instmem: protect instobj list with a spinlockBen Skeggs2015-11-25
| | | | | | | | | No locking is required for the traversal of this list, as it only happens during suspend/resume where nothing else can be executing. Fixes some of the issues noticed during parallel piglit runs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/bus/hwsq: Implement VBLANK waiting heuristicRoy Spliet2015-11-03
| | | | | | | | | Avoids waiting for VBLANKS that never arrive on headless or otherwise unconventional set-ups. Strategy taken from MEMX. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fb/ramgt215: Change FBVDD/Q when BIOS asks for itRoy Spliet2015-11-03
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/bios/rammap: Identify DLLoff for >= GF100Roy Spliet2015-11-03
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pci: Handle 5-bit and 8-bit tag fieldPierre Moreau2015-11-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the hardware supports extended tag field (8-bit ones), then enable it. This is usually done by the VBIOS, but not on some MBPs (see fdo#86537). In case extended tag field is not supported, 5-bit tag field is used which limits the possible number of requests to 32. Apparently bits 7:0 of 0x08841c stores some number of outstanding requests, so cap it to 32 if extended tag is unsupported. Fixes: fdo#86537 v2: Restrict changes to chipsets >= 0x84 v3: * Add nvkm_pci_mask to pci.h * Mask bit 8 before setting it v4: * Rename `add` argument of nvkm_pci_mask to `value` * Move code from nvkm_pci_init to g84_pci_init and remove PCIe and chipset checks v5: * Rebase code on latest PCI structure * Restore PCIe check * Fix namings in nvkm_pci_mask * Rephrase part of the commit message Signed-off-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: remove unused functionSudip Mukherjee2015-11-03
| | | | | | | | | | coverity.com reported that memset was using a buffer of size 0, on checking the code it turned out that the function was not being used. So remove it. Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pci/nv46: attempt to fix msi, and re-enable by defaultBen Skeggs2015-11-03
| | | | | | | | Was not able to obtain a trace of NVRM due to kernel version annoyances, however, experimentally confirmed that the WAR we use on NV50/G8x boards works here too. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pci/g94: split implementation from nv40Ben Skeggs2015-11-03
| | | | | | | An upcoming patch will implement functionality that we don't use on any NV40 chipset. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pci/g84: split implementation from nv50Ben Skeggs2015-11-03
| | | | | | | An upcoming patch will implement functionality that we don't use on the original NV50. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/ibus/gf100: increase wait timeout to avoid read faultsSamuel Pitoiset2015-11-03
| | | | | | | | | | | | Increase clock timeout of some unknown engines in order to avoid failure at high gpcclk rate. This fixes IBUS read faults on my GF119 when reclocking is manually enabled. Note that memory reclocking is completely broken and NvMemExec has to be disabled to allow core clock reclocking only. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/volt/gk104: add support for pwm and gpio modesMartin Peres2015-11-03
| | | | | | | | | | | | | Most Keplers actually use the GPIO-based voltage management instead of the new PWM-based one. Use the GPIO mode as a fallback as it already gracefully handles the case where no GPIOs exist. All the Maxwells seem to use the PWM method though. v2: - Do not forget to commit the PWM configuration change! Signed-off-by: Martin Peres <martin.peres@free.fr>
* drm/nouveau/bios/volt: add support for pwm-based volt managementMartin Peres2015-11-03
| | | | | Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/platform: allow to specify the IOMMU bitAlexandre Courbot2015-11-03
| | | | | | | | | | | Current Tegra code taking advantage of the IOMMU assumes a hardcoded value for the IOMMU bit. Make it a platform property instead for flexibility. v2 (Ben Skeggs): remove nvkm dependence on drm structures Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/ltc/gf100: add flush/invalidate functionsAlexandre Courbot2015-11-03
| | | | | | | | Allow clients to manually flush and invalidate L2. This will be useful for Tegra systems for which we want to write instmem using the CPU. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/ltc: add hooks for invalidate and flushAlexandre Courbot2015-11-03
| | | | | | | | These are useful for systems without a coherent CPU/GPU bus. For such systems we may need to maintain the L2 ourselves. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/timer: re-introduce nvkm_wait_xsec macrosAlexandre Courbot2015-11-03
| | | | | | | | | Reintroduce macros allowing us to test a register against a certain mask, since this is the most common usage pattern for the more generic nvkm_xsec macros and makes the code more concise and readable. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/tegra: merge platform setup from nouveau drmBen Skeggs2015-08-28
| | | | | | | | The copyright header in nvkm/engine/device/platform.c has been replaced with the NVIDIA one from drm/nouveau_platform.c, as most of the actual code is now theirs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pci: merge agp handling from nouveau drmBen Skeggs2015-08-28
| | | | | | | This commit reinstates the pre-DEVINIT AGP fiddling that was broken in an earlier commit. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/device: remove pci/platform_device from common structBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/device: import pciid list and integrate quirks with itBen Skeggs2015-08-28
| | | | | | PCI IDs taken from the NVIDIA binary driver, with permission. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/device: cleaner abstraction for device resource functionsBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mc: move device irq handling to platform-specific codeBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mc: abstract interface to master intr registersBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pci: new subdevBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/object: merge with handleBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: remove the remainder of the previous styleBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mpeg: convert to new-style nvkm_engineBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/sw: convert to new-style nvkm_engineBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pm: convert to new-style nvkm_engineBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gr: convert to new-style nvkm_engineBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo: convert to new-style nvkm_engineBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/disp: convert to new-style nvkm_engineBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/dma: convert to new-style nvkm_engineBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/cipher: convert to new-style nvkm_engineBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/ce: convert to new-style nvkm_engineBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/xtensa: convert to new-style nvkm_engineBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/falcon: convert to new-style nvkm_engineBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/volt: convert to new-style nvkm_subdevBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/tmr: convert to new-style nvkm_subdevBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/therm: convert to new-style nvkm_subdevBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pmu: convert to new-style nvkm_subdevBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mxm: convert to new-style nvkm_subdevBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mmu: convert to new-style nvkm_subdevBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/mc: convert to new-style nvkm_subdevBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/ltc: convert to new-style nvkm_subdevBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/imem: convert to new-style nvkm_subdevBen Skeggs2015-08-28
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/devinit: run devinit scripts right after preinitBen Skeggs2015-08-28
| | | | | | | | This ensures we have a valid mask of disabled engines before we start trying to execute fini()/init() on the subdevs, potentially touching devices that don't exist. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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