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* Merge branch 'android-4.4-p' of ↵Michael Bestas2021-05-31
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://android.googlesource.com/kernel/common into lineage-18.1-caf-msm8998 This brings LA.UM.9.2.r1-03300-SDMxx0.0 up to date with https://android.googlesource.com/kernel/common/ android-4.4-p at commit: 3628cdd31199d Merge 4.4.270 into android-4.4-p Conflicts: drivers/mmc/core/core.c drivers/usb/core/hub.c kernel/trace/trace.c Change-Id: I6b81471122341f9769ce9c65cbd0fedd5e908b38
| * drm/msm/mdp5: Configure PP_SYNC_HEIGHT to double the vtotalMarijn Suijten2021-05-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [ Upstream commit 2ad52bdb220de5ab348098e3482b01235d15a842 ] Leaving this at a close-to-maximum register value 0xFFF0 means it takes very long for the MDSS to generate a software vsync interrupt when the hardware TE interrupt doesn't arrive. Configuring this to double the vtotal (like some downstream kernels) leads to a frame to take at most twice before the vsync signal, until hardware TE comes up. In this case the hardware interrupt responsible for providing this signal - "disp-te" gpio - is not hooked up to the mdp5 vsync/pp logic at all. This solves severe panel update issues observed on at least the Xperia Loire and Tone series, until said gpio is properly hooked up to an irq. Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210406214726.131534-2-marijn.suijten@somainline.org Signed-off-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
| * drm/msm/mdp5: Fix mdp5_cfg_init error returnJeffrey Hugo2020-01-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [ Upstream commit fc19cbb785d7bbd1a1af26229b5240a3ab332744 ] If mdp5_cfg_init fails because of an unknown major version, a null pointer dereference occurs. This is because the caller of init expects error pointers, but init returns NULL on error. Fix this by returning the expected values on error. Fixes: 2e362e1772b8 (drm/msm/mdp5: introduce mdp5_cfg module) Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
* | drm: msm: fix potential NULL pointer dereferenceSuprith Malligere Shankaregowda2018-04-09
| | | | | | | | | | | | | | adding NULL check before dereferencing a pointer. Change-Id: I260b016abdcb16f5b16e58671ed208df21c99a46 Signed-off-by: Suprith Malligere Shankaregowda <supgow@codeaurora.org>
* | drm: msm: fix potential NULL pointer dereferenceGuchun Chen2018-03-27
| | | | | | | | | | | | | | | | | | Add checker before using pointers, to avoid NULL pointer dereference happens. CRs-Fixed: 2202957 Change-Id: I99930e1e9477130fcfceadad3f3a2ff5c9e89cda Signed-off-by: Guchun Chen <guchunc@codeaurora.org>
* | drm/msm: Separate locking of buffer resources from struct_mutexSushmita Susheelendra2017-05-31
| | | | | | | | | | | | | | | | | | | | | | | | | | Buffer object specific resources like pages, domains, sg list need not be protected with struct_mutex. They can be protected with a buffer object level lock. This simplifies locking and makes it easier to avoid potential recursive locking scenarios for SVM involving mmap_sem and struct_mutex. This also removes unnecessary serialization when creating buffer objects, and also between buffer object creation and GPU command submission. Change-Id: I40cb437d0186c3d9aac365c9baba0aa4792f0aa1 Signed-off-by: Sushmita Susheelendra <ssusheel@codeaurora.org>
* | drm/msm: Remove iommu names during attachJordan Crouse2017-04-26
| | | | | | | | | | | | | | | | | | None of the existing iommu implementations use the names passed in at attach time by the API. Save a bit of .data room by removing the static string definitions and passing NULL to the attach function. Change-Id: Ic0dedbada9561768b8d9716ea101619e6b549ea4 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | drm/msm: Refactor GPU IOMMUJordan Crouse2017-04-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Very soon we will be adding support for secure domains and so a bit of refactoring is needed the GPU IOMMU code: * Add support for directly probing the context bank device at create instead of at attach. This makes it a little bit easier to directly associate a mmu device with a specific context bank. * Specify the domain type at create time. Add a new domain type MSM_DOMAIN_USER to associate the user domain with the gfx3d_user context bank. Also add MSM_DOMAIN_DEFAULT with no context bank for legacy devices (read MDP4) with only one context bank to attach to the parent device. Adding a domain type saves us from having to create N entry points for each domain type. Note that dynamic domains stay with their own initalization function. This is because dynamic domains are cloned from the parent domain so the semantics are too different to try to smash into the generic functions. Change-Id: Ic0dedbad41692e776cddc72cda653ae637f9ec77 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | Merge "drm/msm: mdp5: Correctly return ERR_PTR for mdp5_cfg_init"Linux Build Service Account2017-02-23
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| * | drm/msm: mdp5: Correctly return ERR_PTR for mdp5_cfg_initJordan Crouse2017-02-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | The caller for mdp5_cfg_init expects a valid pointer or a ERR_PTR encoded error. Returning NULL leads to a kernel oops. Change-Id: Ic0dedbad44e37bdbc458fad6713d42ab249428d8 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | | drm/msm: Reference count address spacesJordan Crouse2017-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are reasons for a memory object to outlive the file descriptor that created it and so the address space that a buffer object is attached to must also outlive the file descriptor. Reference count the address space so that it can remain viable until all the objects have released their addresses. Change-Id: Ic0dedbad3769801b62152d81b37f2f43f962d308 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | | drm/msm: Support dynamic IOMMU domainsJordan Crouse2017-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Dynamic IOMMU domains allow multiple pagetables to be attached to the same IOMMU device. These can be used by smart devices like the GPU that can switch the pagetable dynamically between DRM instances. Add support for dynamic IOMMU domains if they are enabled and supported by your friendly neighborhood IOMMU driver. Change-Id: Ic0dedbaded3a9e57a7fbb8e745c44c183f6b4655 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | | drm/msm: Use 64 bit containers for iovasJordan Crouse2017-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Newer Adreno GPUs are able to support 64 bit virtual addressing. To prepare for this brave new world switch all IOVA related variables and members to a uint64_t container. This is harmless for the display and older targets that do not have 64 bit addressing because a 32 bit address is just a 64 bit address with lots of zeros. To avoid ambiguity and compiler oddness make sure to use lower_32_bits() and upper_32_bits() everywhere the IOVA is used to ensure that you get what you expect. Change-Id: Ic0dedbad23322fae32509c1f4d75d9b4e2863081 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | | drm/msm: get an iova from the address space instead of an idJordan Crouse2017-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the future we won't have a fixed set of addresses spaces. Instead of going through the effort of assigning a ID for each address space just use the address space itself as a token for getting / putting an iova. This forces a few changes in the gem object however: instead of using a simple index into a list of domains, we need to maintain a list of them. Luckily the list will be pretty small; even with dynamic address spaces we wouldn't ever see more than two or three. Change-Id: Ic0dedbad4495f02a21135217f3605b93f8b8dfea Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | | drm/msm: Support different SMMU backends for address spacesJordan Crouse2017-02-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SDE and the GPU have different requirements for the SMMU backends - the SDE generates its own iova addresses and needs special support for DMA buffers and the GPU does its own IOMMU operations. Add a shim layer to aspace to break out the address generation and call the appropriate SMMU functions. There is probably consolidation that can be done, but for now this is the best way to deal with the two use cases. Change-Id: Ic0dedbadc6dc03504ef7dffded18ba09fb3ef291 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | | drm/msm: support multiple address spacesRob Clark2017-02-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can have various combinations of 64b and 32b address space, ie. 64b CPU but 32b display and gpu, or 64b CPU and GPU but 32b display. So best to decouple the device iova's from mmap offset. Change-Id: Ic0dedbad2b36b535df3e8fb2ddddc20add592cea Signed-off-by: Rob Clark <robdclark@gmail.com> Git-commit: 22877bcbdacd50d076f9b2f829e6a3753aa9821f Git-repo: https://github.com/freedreno/kernel-msm.git [jcrouse@codeaurora.org: Fix merge conflicts, remove mdp5 due to large infrastructure changes, compile fixes] Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | | drm/msm: update generated headersRob Clark2017-02-13
|/ / | | | | | | | | | | | | | | | | | | Pull in additional regs needed for a430, etc. Change-Id: Ic0dedbada256c546268b2a19556a78e8912d06e4 Signed-off-by: Rob Clark <robdclark@gmail.com> Git-commit: a2272e48eef02869dc3fa031720f36dd4cb05e4f Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | drm/msm: use sde specific color format throughoutLloyd Atkinson2016-08-01
| | | | | | | | | | | | | | | | | | Move sde_kms to register its own color format structure for get_format to consolidate all format definitions. Also, make sde_format structure compatible with mdp_format by having a common msm_format base. Change-Id: I79bd4e84633618865456c0d21bcace67c3c8cb80 Signed-off-by: Lloyd Atkinson <latkinso@codeaurora.org>
* | drm/msm: add smmu handlerAdrian Salido-Moreno2016-08-01
| | | | | | | | | | | | | | | | | | | | | | Add msm_smmu driver to support mapping buffers to arm smmu memory. msm_smmu adds the hooks to support drm hooks. Current change only supports the unsecure domain memory. msm_gem object is also updated to attach the new msm_smmu driver. Change-Id: I4899bd74d8b41b864ed5e0dec2da11e929c7fa95 Signed-off-by: Adrian Salido-Moreno <adrianm@codeaurora.org>
* | iommu: Use proper bus for domain allocation in client driversChintan Pandya2016-03-23
|/ | | | | | | | | | | | | | | | | | | | When there are multiple IOMMU drivers in the system, each one will be sitting on different busses. This way, clients should be choosing the right bus to declare their domain on. Once and for all, update all the clients code to use proper bus abstraction API msm_iommu_get_bus() to get right bus. Change-Id: I5edf7037e7b1e4af6a559b6aeaa0b6de0976bf35 Signed-off-by: Chintan Pandya <cpandya@codeaurora.org> [cip@codeaurora.org: Removed changes to drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c, drivers/media/platform/msm/camera_v2/common/cam_smmu_api.c, drivers/media/platform/msm/vidc/venus_boot.c, drivers/platform/msm/ipa/ipa_v2/ipa.c, drivers/platform/msm/ipa/ipa_v3/ipa.c, drivers/platform/msm/msm_11ad/msm_11ad.c] Signed-off-by: Clarence Ip <cip@codeaurora.org>
* drm/msm/mdp5: Basic support for MDP5 v1.7 (MSM8996)Stephane Viau2015-10-22
| | | | | | | This change adds the basic MDP5 support for MSM8996. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp: Add Software Pixel Extension supportStephane Viau2015-10-22
| | | | | | | | | | | | | | | | | | | In order to produce an image, the scalar needs to be fed extra pixels. These top/bottom/left/right values depend on a various of factors, including resolution, scaling type, phase step and initial phase. Pixel Extension are programmed by hardware in most targets - and can be overwritten by software. For some targets (e.g.: msm8996), software *must* program those registers. In order to ease this computation, let's always use bilinear filters, which are easier to program from kernel. Eventually, all of these values will come down from user space for better quality. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Use the newly introduced enum mdp_component_typeStephane Viau2015-10-22
| | | | | | | | | | When calculating phase steps, let's use the same enum mdp_component_type in order to ease the readability; 0/1 indexes are a bit confusing and we now have explicit values to index this type of arrays. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Avoid printing error messages for optional clocksStephane Viau2015-10-22
| | | | | | | | | | | | | The current behavior is to try to get optional clocks and print a dev_err message in case of failure. This looks rather confusing and may increase with the amount of optional clocks. We may need a cleaner way to handle per-device clocks but in the meantime, let's reduce the amount of dev_err messages during the probe. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Fix IOMMU clean up path in case msm_iommu_new() failsStephane Viau2015-10-22
| | | | | | | | | msm_iommu_new() can fail and this change makes sure that we detect the failure and free the allocated domain before going any further. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: remove the cfg pointer from SMP structStephane Viau2015-10-22
| | | | | | | | | We want to make sure we control all the information being passed down to SMP block. Having access to the cfg pointer here may create bad things in the future. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: update generated headersRob Clark2015-10-22
| | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
* Merge tag 'v4.3-rc2' into topic/drm-miscDaniel Vetter2015-09-24
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Backmerge Linux 4.3-rc2 because of conflicts in the dp helper code between bugfixes and new code. Just adjacent lines really. On top of that there's a silent conflict in the new fsl-dcu driver merged into 4.3 and commit 844f9111f6f54f88eb2f0fac121b82ce77193866 Author: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Date: Wed Sep 2 10:42:40 2015 +0200 drm/atomic: Make prepare_fb/cleanup_fb only take state, v3. which Thierry Reding spotted and provided a fixup for. Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
| * gpu/drm: Kill off set_irq_flags usageRob Herring2015-09-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | set_irq_flags is ARM specific with custom flags which have genirq equivalents. Convert drivers to use the genirq interfaces directly, so we can kill off set_irq_flags. The translation of flags is as follows: IRQF_VALID -> !IRQ_NOREQUEST IRQF_PROBE -> !IRQ_NOPROBE IRQF_NOAUTOEN -> IRQ_NOAUTOEN For IRQs managed by an irqdomain, the irqdomain core code handles clearing and setting IRQ_NOREQUEST already, so there is no need to do this in .map() functions and we can simply remove the set_irq_flags calls. Some users also modify IRQ_NOPROBE and this has been maintained although it is not clear that is really needed. There appears to be a great deal of blind copy and paste of this code. Signed-off-by: Rob Herring <robh@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: Russell King <linux@arm.linux.org.uk> Cc: David Airlie <airlied@linux.ie> Cc: dri-devel@lists.freedesktop.org Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* | drm/atomic: Make prepare_fb/cleanup_fb only take state, v3.Maarten Lankhorst2015-09-08
|/ | | | | | | | | | | | | | | | | | This removes the need to separately track fb changes i915. That will be done as a separate commit, however. Changes since v1: - Add dri-devel to cc. - Fix a check in intel's prepare and cleanup fb to take rotation into account. Changes since v2: - Split out i915 changes to a separate commit. Cc: dri-devel@lists.freedesktop.org Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Daniel Stone <daniels@collabora.com> [danvet: Squash in msm fixup from Maarten.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
* drm/msm/mdp: Clear pending interrupt status before enable interruptjilai wang2015-08-15
| | | | | | | | | Pending interrupt status needs to be cleared before enable the interrupt. Otherwise it's possible to get a pending interrupt instead of an incoming interrupt. Signed-off-by: Jilai Wang <jilaiw@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Add rotation (hflip/vflip) support to MDP5 planes (v2)jilai wang2015-08-15
| | | | | | | | | | | | | | MDP5 SSPPs can flip the input source horizontally or vertically. This change is to add this support to MDP5 planes. v1: Initial change v2: Use existing "rotation" property instead of creating msm specific properties. In order to be compatiable with legacy non-atomic set_property, switch to drm_atomic_helper_plane_set_property helper function. Signed-off-by: Jilai Wang <jilaiw@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: add calls to prepare and unprepare panelSrinivas Kandagatla2015-08-15
| | | | | | | | | | Prepare the panel before it's enabled and un-prepare after disable, this will make sure that the regulators are switched on and off correctly. Tested it on APQ8064 based IFC6410 with panel. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: mdp4 lvds: get panel node via of graph parsingArchit Taneja2015-08-15
| | | | | | | | | | | | | | | We currently get the output connected to LVDS by looking for a phandle called 'qcom,lvds-panel' under the mdp DT node. Use the more standard of_graph approach to create an lvds output port, and retrieve the panel node from the port's endpoint data. v3 - Fix return value checks of of_graph_* calls. Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Enable clocks during enable/disable_vblank() callbacksHai Li2015-08-15
| | | | | | | | | | | | | AHB clock should be enabled before accessing registers during enable/disable_vblank(). Since these 2 callbacks are called in atomic context while clk_prepare may cause thread sleep, a work is scheduled to control vblanks. v2: fixup spinlock initialization Signed-off-by: Hai Li <hali@codeaurora.org> [add comment about cancel_work_sync() before drm_irq_uninstall()] Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Add support for msm8x74v1jilai wang2015-08-15
| | | | | | | | msm8x74v1 has different MDP5 version (v1.0) from msm8x74v2 (v1.2). Add a separate config data to support msm8x74v1. Signed-off-by: Jilai Wang <jilaiw@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Add DMA pipe planes for MDP5jilai wang2015-08-15
| | | | | | | | | | This change is to add planes which use DMA pipes for MDP5. Signed-off-by: Jilai Wang <jilaiw@codeaurora.org> [slight comment adjust to s/Construct public planes/Construct video planes/ since DMA planes are public planes too, they just can't scale or CSC] Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp: Add capabilities to MDP planes (v2)jilai wang2015-08-15
| | | | | | | | | | | | | | MDP planes can be implemented using different type of HW pipes, RGB/VIG/DMA pipes for MDP5 and RGB/VG/DMA pipes for MDP4. Each type of pipe has different HW capabilities such as scaling, color space conversion, decimation... Add a variable in plane data structure to specify the difference of each plane which comes from mdp5_cfg data and use it to differenciate the plane operation. V1: Initial change V2: Fix a typo in mdp4_kms.h Signed-off-by: Jilai Wang <jilaiw@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: add more YUV formats for MDP5Stephane Viau2015-08-15
| | | | | | | | Add packed YUV422 and planar YUV420 formats to MDP supported formats. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: use 2 memory clients for YUV formats on newer mdp5Wentao Xu2015-08-15
| | | | | | | | | | Newer MDP5 uses 2 shared memory pool clients for certain YUV formats. For example, if VIG0 is used to fetch data in YUYV format, it will use VIG0_Y for Y component, and VIG0_Cr for UV packed. Signed-off-by: Wentao Xu <wentaox@codeaurora.org> [rebase] Signed-off-by: Stephane Viau <sviau@codeaurora.org>
* drm/msm/mdp: mark if a MDP format is YUV at definitionWentao Xu2015-08-15
| | | | | | | | | | | This makes it easy to determine if a format is YUV. The old method of using chroma sample type incorrectly marks YUV444 as RGB format. Signed-off-by: Wentao Xu <wentaox@codeaurora.org> [rebase] Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Allocate CTL0/1 for dual DSI single FLUSHHai Li2015-08-15
| | | | | | | | | This change takes advantage of a HW feature that synchronize flush operation on CTL1 to CTL0, to keep dual DSI pipes in sync. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Allocate CTL for each display interfaceHai Li2015-08-15
| | | | | | | | | | | | | In MDP5, CTL contains information of the whole pipeline whose output goes down to a display interface. In various cases, one interface may require 2 CRTCs, but only one CTL. Some interfaces also require to use certain CTLs. Instead of allocating CTL for each active CRTC, this change is to associate a CTL with each interface. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Add plane blending operation support for MDP5 (v2)jilai wang2015-08-15
| | | | | | | | | | | | This change is to add properties alpha/zpos/blend_mode to mdp5 plane for alpha blending operation to generate the blended output. v1: Initial change v2: Change "premultilied" property to enum (Rob's comment) Signed-off-by: Jilai Wang <jilaiw@codeaurora.org> [Don't actually expose alpha/premultiplied props to userspace yet pending a chance for discussion and some userspace to exercise it] Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: don't install plane properties on crtcRob Clark2015-08-15
| | | | | | | | | This was a hold-over from the pre-atomic days and legacy userspace that only understood CRTCs. Fortunately we don't have any properties, so this doesn't change anything. But before we start growing some plane properties, we should fix this. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Set different display size limitation on each targetHai Li2015-08-15
| | | | | | | | | | | | | The maximum output width of one pipeline depends on the LayerMixer's capability. It may be different on each target. Also, MDP5 doesn't have vertical limitation in one frame, as long as the pixel clock can be supported. This change obtains the maximum LM resolution from configuration table and treat it as the whole pipe's limitation for MDP5. The size limit on MDP4 is not changed. Signed-off-by: Hai Li <hali@codeaurora.org>
* drm/msm: Add support for msm8x94Stephane Viau2015-08-15
| | | | | | | | | | | | | | This change adds the MDP and HDMI support for msm8x94. Note that HDMI PHY registers are not being accessed anymore from the driver. Signed-off-by: Stephane Viau <sviau@codeaurora.org> [rename compatible s/8x94/8994/ since preference is to not trust the marketing folks who invent chip #'s but instead name things after the lead chip.. we should rename some 80XY to 89XY to standardize on the lead chip but leave that for another patch. Also, update dt bindings doc] Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: update generated headersRob Clark2015-08-15
| | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: release SMB (shared memory blocks) in various casesWentao Xu2015-08-14
| | | | | | | | | | | | | Release all blocks after the pipe is disabled, even when vsync didn't happen in some error cases. Allow requesting SMB multiple times before configuring to hardware, by releasing blocks not programmed to hardware yet for shrinking case. This fixes a potential leak of shared memory pool blocks. Signed-off-by: Wentao Xu <wentaox@codeaurora.org> Tested-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: mdp4: Fix drm_framebuffer dereference crashArchit Taneja2015-08-14
| | | | | | | | mdp4_get_frame_format() can dereference a drm_framebuffer when it's NULL. Call it in mdp4_plane_mode_set only when we know fb is non-NULL. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-28 20:18:49 +0000