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* | clk: msm: clock-cpu-8996: Correct the ACS configuration logicDeepak Katragadda2016-03-23
| | | | | | | | | | | | | | | | | | Correct the settings to switch to always-on clock source during certain LPM mode exit paths on msm8996 Pro. CRs-Fixed: 972298 Change-Id: Ice256b453fad07bc80be79d9c15d10545c90fb20 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: msm-clock-controller: check for null along with errorAbhimanyu Kapur2016-03-23
| | | | | | | | | | | | | | | | | | | | While parsing the device tree node, perform a null check along with the error check by substituting IS_ERR with IS_ERR_OR_NULL on the parser pointer. CRs-Fixed: 971705 Change-Id: Id91981be0cdc135099b8e3d9866549268ab237a3 Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
* | clk: msm: clock: Keep the graphics clock peripheral memory always onDeepak Katragadda2016-03-23
| | | | | | | | | | | | | | | | | | | | Due to an issue with the RBBM perf counter being corrupted after NAP state, force turn on the gfx3d_clk peripheral memory at probe and leave it enabled. CRs-Fixed: 933216 Change-Id: I707b44c56e5e6d3ec9056dded9fe488163be276c Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: clock-gpu-cobalt: Add the CRC programming sequenceDeepak Katragadda2016-03-23
| | | | | | | | | | | | | | | | | | | | The clock ramp controller helps in mitigating PDN droop during low power use cases. Add the sequence to enable it in the clock driver. CRs-Fixed: 942848 Change-Id: Ia9afcd6492ddb38e3371a469c15ea07143c3c358 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: clock-generic: Fix max_div calculation for 32 bitTaniya Das2016-03-23
| | | | | | | | | | | | | | | | | | | | The ULONG_MAX value on 32 bit compilers is +4,294,967,295 and when divided with some high frequencies, it could lead to min_div > max_div. Thus resulting in clk_set_rate failure for higher frequencies. CRs-Fixed: 971371 Change-Id: Id982328aeadf24d29e295e042a57453ea4e35c1b Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: msm: clock: Enable auto-calibration during certain LPM mode pathsDeepak Katragadda2016-03-23
| | | | | | | | | | | | | | | | | | Add settings to switch to always-on clock source during certain LPM mode exit paths on msm8996 Pro. CRs-Fixed: 968587 Change-Id: I6138681e2a85b7d1ad11350718544de6abe38131 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: clock: Add the MMSS clock driver support for MSMCOBALTDeepak Katragadda2016-03-23
| | | | | | | | | | | | | | Add support to model the multimedia clocks on MSMCOBALT. Change-Id: Iec33fa93e745a65205cf4206759289d7e842fe36 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: clock: Decouple PLL min frequency from being fabia specificDeepak Katragadda2016-03-23
| | | | | | | | | | | | | | | | | | Currently, the min_supported_rate is only used for fabia PLLs. This is a generic PLL property which needs to be checked for all PLLs. Change-Id: Iaec2ee84468bb40a68ded9355aa7587eabbe86b9 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: clock-local2: Add support for branch clocks rate aggregationDeepak Katragadda2016-03-23
| | | | | | | | | | | | | | | | | | | | There are cases when multiple branch clocks need to be able to scale their RCG independently. The RCG should then be configured to run at the maximum rate of all it's children clocks which are enabled at that point. Add support for this. Change-Id: I90b7a9a3007792f65e0292d375e409ce1dbf0c08 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: qcom: mdss: set the hdmi vco clock rateTatenda Chipeperekwa2016-03-23
| | | | | | | | | | | | | | | | | | Set the VCO rate properly during handoff. This VCO rate can be used during suspend-resume to reconfigure the PLL. Change-Id: Ib67d68f28aa5bd3a09bf7bcc5802ee3b7af342ee Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org> Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
* | clk: msm: clock: Add GPUCC clock driver support for MSMCOBALTDeepak Katragadda2016-03-23
| | | | | | | | | | | | | | Add support to model the graphics clocks on MSMCOBALT. Change-Id: I31c3dda59a0bb7e9b6b6cee8176fb46f46767629 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: clock-alpha-pll: Fix out of bound accessTaniya Das2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BUG: KASAN: global-out-of-bounds in dyna_alpha_pll_enable+0x1a8/0x450 at addr ffffffc003412ee0 Read of size 8 by task surfaceflinger/548 page:ffffffba45a3cc60 count:1 mapcount:0 mapping: (null) index:0x0 flags: 0x400(reserved) page dumped because: kasan: bad access detected Address belongs to variable p_vco_8937+0x20/0x40 Call trace: Memory state around the buggy address: ffffffc003412d80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ffffffc003412e00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >ffffffc003412e80: 00 00 00 00 fa fa fa fa 00 00 00 fa fa fa fa fa ^ ffffffc003412f00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ffffffc003412f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ================================================================== ================================================================== When slewing is enabled the expectation is the vco will operate in the same vco mode. The calibrated frequency should use only index '0'. Change-Id: I1fdcb7d8c09b4f7ff41a1c1a9b36351a6c808c47 Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: msm: clock-pll: Add test_ctl_dbg flag to configure test bitsTaniya Das2016-03-23
| | | | | | | | | | | | | | | | | | The PLL hardware configuration does not mandate to modify the test control bits of the PLL, in those cases introduce a flag which when present will skip configuration of the test control bits. Change-Id: I70588398cffae193d56cb510faa19b1f96f05fea Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: qcom: clock-generic: Fix handoff for mux_div clockTaniya Das2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation would check for the parent rate and decide the handoff state of the clock, which is not true for mux clocks. With this logic the function returns 'enabled' even when the clock downstream of this clock is disabled. The handoff code will unnecessarily enable the current parent of this clock. If this function always returns 'disabled' and a clock downstream is on, the clock handoff code will bump up the ref count for this clock and its current parent as necessary. The clocks without an actual HW gate can always return handoff disabled. Change-Id: I1f06842e2761b336b49a9390a556064de44f2e36 Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: msm: Add support to control MEM_PERPIH_OFF bit of branch clockDevesh Jhunjhunwala2016-03-23
| | | | | | | | | | | | | | | | Update cbcr_set_flags method to add support for controlling the MEM_PERPIH_OFF bit for branch clocks. Change-Id: I87451b02cb9000dc850fdfaa52a5a9f9fd2893a1 Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
* | clk: msm: clock-gcc-8996: Add USB_20_BCRJack Pham2016-03-23
| | | | | | | | | | | | | | | | Add the BCR to reset USB20 block to gcc_usb20_master_clk. This will allow the driver to correctly call clk_reset(). Change-Id: Ib4f8b73317032c88f5272a530007ff08d14dbd4a Signed-off-by: Jack Pham <jackp@codeaurora.org>
* | clk: msm: mdss: Read PLL/PHY status once during bootupTatenda Chipeperekwa2016-03-23
| | | | | | | | | | | | | | | | | | | | Read the PLL/PHY status once during bootup to avoid delays due to polling. Polling for PLL/PHY status is only required when handling HDMI use cases in which the cable is connected after bootup is complete. Change-Id: Ie1d5983a7784cb5f3472527d1b510f128ae9d325 Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
* | clk: msm: mdss: add DT support for SSC frequency and PPM valuesPadmanabhan Komanduru2016-03-23
| | | | | | | | | | | | | | | | | | The SSC frequency and PPM values are currently hardcoded in the DSI PLL driver. Add DT properties to specify the SSC frequency and SSC PPM values for DSI SSC feature. Change-Id: I0faed9f48694f7407c6855b067ffa4510d7e3fdd Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
* | clk: msm: gdsc: Add the "qcom,gds-timeout" DT property for GDSC pollingDeepak Katragadda2016-03-23
| | | | | | | | | | | | | | | | | | | | | | Instead of hard-coding the GDSC polling timeouts, use the "qcom,gds-timeout" property to load the desired values. These polling times vary for the votable GDSCs especially depending on the sequence, clock rates and the clock SLEEP and WAKEUP settings. Change-Id: Id43ce13fcb5f386d5659280f2b561b6065eb0248 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: mdss: Change PLL/PHY status messages to debug levelTatenda Chipeperekwa2016-03-23
| | | | | | | | | | | | | | | | | | | | | | The utility functions to check for PLL lock status and PHY ready status should only report the status, and log messages for debug/information purposes. The caller must decide on how to treat the return value, and log appropriately depending on the use case. Change-Id: Id369b8c4e326d71a071a244e3de432efe89bd483 Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
* | drivers: iommu, leds, input, clk, devfreq: fix warningsRohit Vaswani2016-03-23
| | | | | | | | | | | | | | | | Fix some variable initializations which would otherwise cause forbidden warnings. Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org> Signed-off-by: David Keitel <dkeitel@codeaurora.org>
* | clk: msm: mdss: fix 32 bit compilation issuesVishnuvardhan Prodduturi2016-03-23
| | | | | | | | | | | | | | | | | | | | Fix 32bit compilation issues in DSI and HDMI pll driver. Also avoid udelay of more than 2ms as it gives a fake __bad_udelay reference at link-time on 32bit build. Change-Id: I2681c0fb2a7d69ee8a3f9f6d18164c3cb482d2f7 Signed-off-by: Vishnuvardhan Prodduturi <vproddut@codeaurora.org> Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
* | clk: mdss: shadow clock implementation for dynamic refresh rateJeevan Shriram2016-03-23
| | | | | | | | | | | | | | | | | | This change implements shadow software mux and clocks for updating dynamic refresh registers through 14nm DSI PLL calculations. Change-Id: I461402a249d842d1fb2a8e9ecf82c2c87a37691c Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org> Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
* | clk: msm: mdss: add HDMI PLL sequence for external 1.8V supplyClarence Ip2016-03-23
| | | | | | | | | | | | | | | | | | | | Add support to bring up HDMI PLL on bridge chips with an external 1.8V supply by modifying the existing MSM8996v3 sequence. Change-Id: I6c893f25e7bcf2900d0aa83d42ef314aab4b5746 Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org> [cip@codeaurora.org: Resolved merge conflicts] Signed-off-by: Clarence Ip <cip@codeaurora.org>
* | msm: dsi-pll: update pll ref config before start for msm8996Dhaval Patel2016-03-23
| | | | | | | | | | | | | | | | Reset pll_verf_cfg1 to default value of 0x10 before pll start for msm8996 based on hardware recommendation. Change-Id: I95a89c18de4f7eb65a8ea0a8e4810560ddb0b44f Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
* | clk: msm: mdss: read pre-calibrated PLL codes from dfps memoryJeevan Shriram2016-03-23
| | | | | | | | | | | | | | | | | | These PLL codes are stored in memory in bootloader, so that pll driver can use these pre-calibrated values to lock to a new frequency when dynamic refresh rate feature is enabled. Change-Id: I527e03aa3efcb3904dd6057cd2e63356062436ca Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
* | clk: msm: mdss: Increase polling timer before SW calibrationCasey Piper2016-03-23
| | | | | | | | | | | | | | | | | | | | Before completing SW calibration of HDMI PLL on msm8996 v2, poll C READY register for an increased period to ensure that we do not mistakenly perform software calibration when it is not needed. Change-Id: I7ec25665700ecf20b9fe2337eb01015b1e156b9b Signed-off-by: Casey Piper <cpiper@codeaurora.org>
* | clk: msm: hdmi: Increase PLL ready bit timeoutCasey Piper2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | When using 4k resolutions at 60fps, the PLL ready bit will take slightly longer than other video modes. Increase the timeout value to ensure that the PLL lock is successful. Also modify the lane mode values to improve Shmoo margin with low core voltage. Change-Id: I9d65535b941e755fe706e4dd61cb357a7a62cdc2 Signed-off-by: Casey Piper <cpiper@codeaurora.org>
* | clk: mdss: hdmi: enable PLL value calculations for MSM8996V3Casey Piper2016-03-23
| | | | | | | | | | | | | | | | | | In the V3 revision of MSM8996, there is a different recommended power on sequence. Update this sequence for MSM8996V3 only with the new sequence and calculations. Change-Id: I29612a3a4c9d148df61169c091015079ada6b41c Signed-off-by: Casey Piper <cpiper@codeaurora.org>
* | clk: msm: mdss: enable pll resources once in prepareVinu Deokaran2016-03-23
| | | | | | | | | | | | | | | | | | Enable PLL resource only once in prepare. The current driver enables and disables PLL resources multiple times during the course of prepare routine. Change-Id: I9fbf58e7e509dda55d8ec01ec7d305ccf1691f94 Signed-off-by: Vinu Deokaran <vinud@codeaurora.org>
* | msm: mdss: add support of dsi pll SSC for 8996Kuogee Hsieh2016-03-23
| | | | | | | | | | | | | | | | | | DSI SSC enabled through dtsi. Both down spread and center spread are supported. Default is down spread when SSC enabled. Change-Id: I4c5ef632e5442ef610444ea5439d4bb78541791b Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
* | clk: msm: mdss: update HDMI PLL locking sequence for MSM8996v1Casey Piper2016-03-23
| | | | | | | | | | | | | | | | | | Update SVS mode and driver level settings for MSM8996v1 PLL locking sequence, based on Si characterization. Change-Id: Ic25e89f62b222847eef491a1c4138434ab2b38fe Signed-off-by: Casey Piper <cpiper@codeaurora.org>
* | msm: mdss: add pll master/slave auto detection for 8996Kuogee Hsieh2016-03-23
| | | | | | | | | | | | | | | | Set up pll master/slave status base on both pll GLBL_TEST_CTRL and CLKBUFLR_EN pll registers value. Change-Id: Ic75e77d5fccb88613ebe435f97a39f5d745fb264 Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
* | clk: mdss: remove configuring phy registers during pll disableJeevan Shriram2016-03-23
| | | | | | | | | | | | | | | | | | | | | | DSI driver needs to disable pll and enable clamps before entering into low power state. Since the PLL disable is configuring GLBL_TEST_CNTRL, CLK_BUF PHY registers to 0, these registers are not restored after the clamps are disabled. This change avoids configuring these registers during PLL disable and gets disabled during dsi off. Change-Id: Ia577099679f23cb9d0d42417863b6b3ad3af635b Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
* | clk: msm: mdss: increase VCO frequency to above 8.9GhzCasey Piper2016-03-23
| | | | | | | | | | | | | | | | | | | | For some resolutions on MSM8996 V2, PLL can become unlocked at high operating temperatures. To prevent this, use a VCO frequency of at least 8.9Ghz for bit clocks of at least 282Mhz. Change-Id: I409f286d23a924eab8bcd204638602e530597d77 Signed-off-by: Casey Piper <cpiper@codeaurora.org>
* | clk: msm: mdss: Export DSI1 PLL clocksAravind Venkateswaran2016-03-23
| | | | | | | | | | | | | | | | | | | | | | Add support for all the clocks provided by the DSI1 PLL in preparation for supporting two independent displays using the two DSI controllers. Change-Id: I9c9e4cddd23be869d9f16a5c3e1351a88f88699f Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org> Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org> [cip@codeaurora.org: Removed .dtsi file updates] Signed-off-by: Clarence Ip <cip@codeaurora.org>
* | clk: qcom: mdss: remove DSI1 PLL configuration from DSI0 PLLAravind Venkateswaran2016-03-23
| | | | | | | | | | | | | | | | | | | | | | In the current implementation, DSI0 PLL driver explicitly disables DSI1 PLL at numerous instances to work around a hardware issue that requires explicitly powering down any unused PLLs whenever MDSS GDSC is toggled. However, this is not needed anymore since each PLL can independently power itself down as part of the GDSC notifier worker thread. Change-Id: Ic56f0ce350dd9ad648f3b96baa753345a74897b0 Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
* | clk: msm: mdss: add HDMI PLL sequence for MSM8996v2Casey Piper2016-03-23
| | | | | | | | | | | | | | | | | | MSM8996v2 does not share the same HDMI PLL sequence as MSM8996v1. Update the HDMI PLL driver for MSM8996 to support the differing sequences. Change-Id: Ibfdac25383e6504c707f2abe95b9fa2732283acf Signed-off-by: Casey Piper <cpiper@codeaurora.org>
* | msm: clk: mdss: fix vco clk get rate API for msm8996Dhaval Patel2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Incorrect get rate for n1 divider and vco rate leads to wrong calculation of byte clock and pixel clock during handoff for continuous splash screen. Correct n1 divider should be read from register instead of software because software structures are not set during handoff. Incorrect vco calculation also provides invalid vco rate. This change fixes both APIs to provide correct rate for byte and pixel clock rate calculation. Change-Id: I2b42490a58061cee429aaa777a43eaf7c384b6d9 Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
* | msm: mdss: fix pll stop sequence for msm8996 targetDhaval Patel2016-03-23
| | | | | | | | | | | | | | | | | | | | | | Turning off pll digital block before link clocks leads to clock status stuck ON. Ideally, DSI driver should first stop the lanes, followed by link clock stop and pll disable. This change implements these recommended sequence for both DSI controllers. Change-Id: Ibe3061a65bad2dbfdffd9505d469f10f62a6e39d Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
* | clk: msm: mdss: update pll ldo configuration for 8996 v2Dhaval Patel2016-03-23
| | | | | | | | | | | | | | | | | | msm8996 v2 pll needs different ldo configuration in DSI pll compared to v1 target. This changes updates the DSI pll driver to support this new configuration. Change-Id: Idccfad2e388273a15b45a0e8bb822513fcbbe70e Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
* | msm: mdss: fixed calculation of pll fractional dividerKuogee Hsieh2016-03-23
| | | | | | | | | | | | | | | | | | Pll unlocked due to wrong pll fractional divider calculated. Pll fraction divider should be reminder of 2^20 after vco rate divided by reference clock rate. Change-Id: I9e4c2e3c0631e533d114c3e6acf65b71b9bf00d2 Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
* | clk: mdss: Remove pll support for all targets except msm8996Veera Sundaram Sankaran2016-03-23
| | | | | | | | | | | | | | | | As part of 3.18 upgrade, remove support pll support for all other targets except msm8996. Change-Id: Idc778ccba25ce22ad7e418c45f2bd8d21ccb95e8 Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
* | clk: mdss: Replace thulium with msm8996 in pllVeera Sundaram Sankaran2016-03-23
| | | | | | | | | | | | | | Use appropriate SOC name. Change-Id: I10b554129775e4b73e15ab173de7f8f3ef0a6b58 Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
* | clk: mdss: write lane mode when powering on HDMI PHYCasey Piper2016-03-23
| | | | | | | | | | | | | | | | | | | | | | To improve the timing margin, lane mode selection needs to be written during the HDMI PHY startup sequence. This prevents a timing failure when VDDCX or VCCA_CORE are applied rather than the nominal value. Change-Id: I2ed54f63903a473eca12fb4d8f3b542585397dae Signed-off-by: Casey Piper <cpiper@codeaurora.org>
* | clk: msm: mdss: update pll calculator with new settingsVinu Deokaran2016-03-23
| | | | | | | | | | | | | | | | | | Update HDMI PLL calculation for thulium. These changes are based on latest settings from PHY team. Change-Id: I9ab20c4101ff7cbebab61c35553b3e9d4799019f Signed-off-by: Vinu Deokaran <vinud@codeaurora.org> Signed-off-by: Casey Piper <cpiper@codeaurora.org>
* | msm: mdss: add configuration for dsi pll-1's clock dividersKuogee Hsieh2016-03-23
| | | | | | | | | | | | | | | | | | During split display case, pll-1 share vco output of pll-0. Therefore pll-1's related clock dividers need to be configured along with pll-0. Change-Id: I98744ec0b8a5bea952f41754788ba44d824d3373 Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
* | clk: qcom: mdss: remove references to 14nmVinu Deokaran2016-03-23
| | | | | | | | | | | | | | Remove references to 14nm and replace them with thulium. Change-Id: I8a3a86d3510bea71f19003bebe89318c2fb399d4 Signed-off-by: Vinu Deokaran <vinud@codeaurora.org>
* | msm: mdss: add thulium dsi pll supportKuogee Hsieh2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement dsi related clocks framework so that dsi vco pll related function be called to output correct vco rate base on byte clock rate. After that pixel clock rate can be achieved through MND setting. Change-Id: I819f9fcb8afd9430f131679434c4da34641ce3f8 [veeras@codeaurora.org: As part of 3.18 upgrade, remove all non-display related code from this commit include/dt-bindings/clock/msm-clocks-thulium.h] Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org> Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
* | clk: mdss: fix pll 1 leakage issue by calling power down sequenceHuaibin Yang2016-03-23
| | | | | | | | | | | | | | | | | | To completely shutdown pll 1, power down sequence has to be called. This is different from the old sequence where disable pll sequence acturally turn off pll. Change-Id: Ia8b9adb8f78241e34420c0966c3c25b7684b1262 Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-23 02:58:05 +0000